; -------------------------------------------------------------------------------- ; @Title: RM48Lxx On-chip Peripherals ; @Props: Released ; @Author: ZAK, JAM ; @Changelog: 2012-09-28 ZAK ; 2019-02-13 JAM ; @Manufacturer: TI - Texas Instruments ; @Doc: rm48lx_spnu503.pdf (2011.09); rm48l952.pdf (2011.09) ; rm48l950.pdf (2011.09); rm48l940.pdf (2011.09); rm48l930.pdf (2011.09) ; rm48l750.pdf (2011.09); rm48l740.pdf (2011.09); rm48l730.pdf (2011.09) ; rm48l550.pdf (2011.09); rm48l540.pdf (2011.09); rm48l530.pdf (2011.09) ; rm46l852.pdf (2012.09); rm46l850.pdf (2012.09); rm46l830.pdf (2012.09) ; rm46l450.pdf (2012.09); rm46l440.pdf (2012.09); rm46lx_spnu514.pdf (2012.09) ; rm46l430.pdf (2012.09); rm42lx_spnu516.pdf (2012.09); rm42l432.pdf (2012.09) ; @Core: Cortex-R4 ; @Chip: RM48L940-ZWT, RM48L950-PGE, RM48L950-ZWT, RM48L952-PGE ; @Copyright: (C) 1989-2019 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: perrm48l.per 13224 2021-04-28 12:54:48Z kwitkowski $ config 16. 8. tree "Core Registers (Cortex-R4)" AUTOINDENT.PUSH AUTOINDENT.OFF width 0x8 ; -------------------------------------------------------------------------------- ; Identification registers ; -------------------------------------------------------------------------------- tree "ID Registers" rgroup c15:0x0--0x0 line.long 0x0 "MIDR,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code" bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. " ARCH , Architecture" "Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,ARMv7" textline " " hexmask.long.word 0x0 4.--15. 0x1 " PART ,Primary Part Number" bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup c15:0x100--0x100 line.long 0x0 "CTR,Cache Type Register" bitfld.long 0x0 29.--31. " FORMAT ,Format" "Not ARMv7,Not ARMv7,Not ARMv7,Not ARMv7,ARMv7,Not ARMv7,Not ARMv7,Not ARMv7" bitfld.long 0x0 16.--19. " DMINLINE ,D-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words" bitfld.long 0x0 14.--15. " L1POLICY ,L1 Instruction cache policy" "Reserved,ASID,Virtual,Physical" textline " " bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words" rgroup c15:0x200--0x200 line.long 0x0 "TCMSR,Tighly-Coupled Memory Status Register" bitfld.long 0x0 16.--19. " DTCMS ,Data Banks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 0.--3. " ITCMS ,Instruction Banks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup c15:0x400--0x400 line.long 0x0 "MPUIR,MPU type register" hexmask.long.byte 0x00 8.--15. 1. " REGNUM ,Number of regions" bitfld.long 0x00 0. " TYPE ,Type of MPU regions" "Unified,Seperated" rgroup c15:0x500--0x500 line.long 0x0 "MPIDR,Multiprocessor Affinity Register" hexmask.long.byte 0x00 16.--23. 1. " AFFL2 ,Affitnity Level 2" hexmask.long.byte 0x00 8.--15. 1. " AFFL1 ,Affitnity Level 1" hexmask.long.byte 0x00 0.--7. 1. " AFFL0 ,Affitnity Level 0" textline " " rgroup c15:0x0410++0x00 line.long 0x00 "MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " CC_PLEA ,Cache Coherency With PLE Agent/Shared Memory Support" "Not supported,?..." bitfld.long 0x00 8.--11. " CC_CPUA ,Cache Coherency Support With CPU Agent/Shared Memory Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..." bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..." rgroup c15:0x0510++0x00 line.long 0x00 "MMFR1,Memory Model Feature Register 1" bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..." bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..." textline " " bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..." textline " " bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..." rgroup c15:0x0610++0x00 line.long 0x00 "MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..." bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." rgroup c15:0x0710++0x00 line.long 0x00 "MMFR3,Memory Model Feature Register 3" bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..." rgroup c15:0x0020++0x00 line.long 0x00 "ISAR0,Instruction Set Attribute Register 0" bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..." bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..." bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " AI ,Atomic Load and Store Instructions Support" "Reserved,Supported,?..." rgroup c15:0x0120++0x00 line.long 0x00 "ISAR1,Instruction Set Attribute Register 1" bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " ENDI ,Endianness Control Instructions Support" "Reserved,Supported,?..." rgroup c15:0x0220++0x00 line.long 0x00 "ISAR2,Instruction Set Attribute Register 2" bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..." textline " " bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..." rgroup c15:0x0320++0x00 line.long 0x00 "ISAR3,Instruction Set Attribute Register 3" bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " SWII ,SWI Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..." rgroup c15:0x0420++0x00 line.long 0x00 "ISAR4,Instruction Set Attribute Register 4" bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..." rgroup c15:0x0520++0x00 line.long 0x00 "ISAR5,Instruction Set Attribute Registers 5 (Reserved)" rgroup c15:0x0620++0x00 line.long 0x00 "ISAR6,Instruction Set Attribute Registers 6 (Reserved)" rgroup c15:0x0720++0x00 line.long 0x00 "ISAR7,Instruction Set Attribute Registers 7 (Reserved)" rgroup c15:0x0010++0x00 line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..." bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..." rgroup c15:0x0110++0x00 line.long 0x00 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..." bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..." textline " " rgroup c15:0x0210++0x00 line.long 0x00 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..." bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." textline " " bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..." bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..." rgroup c15:0x0310++0x00 line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" tree.end width 0x8 tree "System Control and Configuration" group c15:0x1--0x1 line.long 0x0 "SCTLR,Control Register" bitfld.long 0x0 31. " IE ,Instruction endianness" "Little,Big" bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disable,Enable" bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disable,Enable" bitfld.long 0x0 27. " NMFI ,Nonmaskable Fast Interrupt enable" "Disable,Enable" textline " " bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big" bitfld.long 0x0 24. " VE ,Vector Enable" "Disable,Vectored" bitfld.long 0x0 21. " FI ,Fast Interrupts enable" "Disable,Enable" bitfld.long 0x0 19. " DZ ,Divide by Zero exception bit" "Disable,Enable" bitfld.long 0x0 14. " RR ,Round-Robin bit" "Random,RRobin" bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000" textline " " bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disable,Enable" bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disable,Enable" bitfld.long 0x0 2. " C ,Enable data cache" "Disable,Enable" bitfld.long 0x0 1. " A ,Strict Alignment" "Disable,Enable" bitfld.long 0x0 0. " M ,MPU Enable" "Disable,Enable" textline " " group c15:0x101--0x101 line.long 0x0 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 31. " DICDI ,Disable Case C dual issue control" "Enable,Disable" bitfld.long 0x00 30. " DIB2DI ,Disable Case B2 dual issue control" "Enable,Disable" bitfld.long 0x00 29. " DIB1DI ,Disable Case B1 dual issue control" "Enable,Disable" textline " " bitfld.long 0x00 28. " DIADI ,Disable Case A dual issue control" "Enable,Disable" bitfld.long 0x00 27. " B1TCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable" bitfld.long 0x00 26. " B0TCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable" textline " " bitfld.long 0x00 25. " ATCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable" bitfld.long 0x00 24. " AXISCEN ,AXI slave cache access enable" "Disable,Enable" bitfld.long 0x00 23. " AXISCUEN ,AXI slave cache User mode access enable" "Disable,Enable" textline " " bitfld.long 0x00 22. " DILSM ,Disable LIL on load/store multiples" "Disable,Enable" bitfld.long 0x00 21. " DEOLP ,Disable end of loop prediction" "Disable,Enable" bitfld.long 0x00 20. " DBHE ,Disable BH extension" "Enable,Disable" textline " " bitfld.long 0x00 19. " FRCDIS ,Fetch rate control disable" "Enable,Disable" bitfld.long 0x00 17. " RSDIS ,Return stack disable" "Enable,Disable" bitfld.long 0x00 15.--16. " BP ,Control of the branch prediction policy" "Normal,Taken,Not taken,?..." textline " " bitfld.long 0x00 14. " DBWR ,Disable write_burst on AXI master" "Enable,Disable" bitfld.long 0x00 13. " DSWT ,Disable should_wait on AXI master" "Enable,Disable" bitfld.long 0x00 12. " ERPEG ,Enable random parity error generation" "Disable,Enable" textline " " bitfld.long 0x00 11. " DOLT ,Disable outstanding line fill on AXI master" "Enable,Disable" bitfld.long 0x00 10. " FORA ,Force outer read allocate (ORA) for outer write allocate (OWA) regions" "Not forced,Forced" bitfld.long 0x00 9. " FWT ,Force write-through (WT) for write-back (WB) regions" "Not forced,Forced" textline " " bitfld.long 0x00 8. " FDSnS ,Force D-side to not-shared when MPU is off" "Not forced,Forced" bitfld.long 0x00 7. " sMOV ,sMOV disabled" "Enabled,Disabled" bitfld.long 0x0 6. " DILS ,Disable low interrupt latency on all load/store instructions" "Enable,Disable" textline " " bitfld.long 0x00 5. " DA ,DA Disable abort on cache parity error" "Enable,Disable" bitfld.long 0x00 4. " EHR ,Enable hardware recovery from cache parity errors" "Disable,Enable" bitfld.long 0x00 2. " I1TCMECEN ,Instruction 1 TCM error check enable" "Disable,Enable" textline " " bitfld.long 0x00 1. " I0TCMECEN ,Instruction 1 TCM error check enable" "Disable,Enable" bitfld.long 0x00 0. " ITCMECEN ,Instruction TCM error check enable" "Disable,Enable" textline " " group c15:0x0f--0x0f line.long 0x0 "SACTLR,Secondary Auxiliary Control Register" bitfld.long 0x00 22. " DCHE ,Disable hard-error support in the caches" "Enable,Disable" bitfld.long 0x00 21. " DR2B ,Enable random 2-bit error genration in cache RAMs" "Disable,Enable" bitfld.long 0x00 20. " DF6DI ,F6 dual issue control" "Enable,Disable" textline " " bitfld.long 0x00 19. " DF2DI ,F2 dual issue control" "Enable,Disable" bitfld.long 0x00 18. " DDI ,F1/F3/F4 dual issue control" "Enable,Disable" bitfld.long 0x00 17. " DOODPFP ,Out-of-order Double Precision Floating-point control" "Enable,Disable" textline " " bitfld.long 0x00 16. " DOOFMACS ,Out-of-order FMACS control" "Enable,Disable" bitfld.long 0x00 13. " IXC ,Floating-point inexact exception output mask" "Mask,Propagate" bitfld.long 0x00 12. " OFC ,Floating-point overflow exception output mask" "Mask,Propagate" textline " " bitfld.long 0x00 11. " UFC ,Floating-point underflow exception output mask" "Mask,Propagate" bitfld.long 0x00 10. " IOC ,Floating-point invalid operation exception output mask" "Mask,Propagate" bitfld.long 0x00 9. " DZC ,Floating-point divide-by-zero exception output mask" "Mask,Propagate" textline " " bitfld.long 0x00 8. " IDC ,Floating-point input denormal exception output mask" "Mask,Propagate" bitfld.long 0x00 3. " BTCMECC ,Correction for internal ECC logic on BTCM ports" "Enable,Disable" bitfld.long 0x00 2. " ATCMECC ,Correction for internal ECC logic on ATCM port" "Enable,Disable" textline " " bitfld.long 0x00 1. " BTCMRMW ,Enable 64-bit stores on BTCMs" "Disable,Enable" bitfld.long 0x00 0. " ATCMRMW ,Enable 64-bit stores on ATCM" "Disable,Enable" textline " " group c15:0x201--0x201 line.long 0x0 "CPACR,Coprocessor Access Control Register" bitfld.long 0x0 26.--27. " CP13 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 24.--25. " CP12 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 22.--23. " CP11 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 20.--21. " CP10 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 18.--19. " CP9 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 16.--17. " CP8 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 14.--15. " CP7 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 12.--13. " CP6 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 10.--11. " CP5 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 8.--9. " CP4 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 6.--7. " CP3 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 4.--5. " CP2 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 2.--3. " CP1 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 0.--1. " CP0 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " group.long c15:0x0b--0x0b line.long 0x00 "SPC,Slave Port Control" bitfld.long 0x00 1. " PRIV ,Privilege access only" "User/Privilege,Privilege only" bitfld.long 0x00 0. " AXISLEN ,AXI slave port disable" "Enabled,Disabled" tree.end width 0x8 tree "MPU Control and Configuration" group c15:0x0001--0x0001 line.long 0x0 "SCTLR,Control Register" bitfld.long 0x0 31. " IE ,Instruction endianness" "Little,Big" bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disable,Enable" bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disable,Enable" bitfld.long 0x0 27. " NMFI ,Nonmaskable Fast Interrupt enable" "Disable,Enable" textline " " bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big" bitfld.long 0x0 24. " VE ,Vector Enable" "Disable,Vectored" bitfld.long 0x0 21. " FI ,Fast Interrupts enable" "Disable,Enable" bitfld.long 0x0 19. " DZ ,Divide by Zero exception bit" "Disable,Enable" bitfld.long 0x0 14. " RR ,Round-Robin bit" "Random,RRobin" bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000" textline " " bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disable,Enable" bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disable,Enable" bitfld.long 0x0 2. " C ,Enable data cache" "Disable,Enable" bitfld.long 0x0 1. " A ,Strict Alignment" "Disable,Enable" bitfld.long 0x0 0. " M ,MPU Enable" "Disable,Enable" textline " " group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 11. " RW ,Access Caused an Abort Type" "Read,Write" textline " " bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15" bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..." group.long c15:0x0015++0x00 line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register" group.long c15:0x0006++0x00 line.long 0x00 "DFAR,Data Fault Address Register" group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..." group.long c15:0x0115++0x00 line.long 0x00 "AIFSR,Auxiliary Instruction Fault Status Register" group.long c15:0x0206++0x00 line.long 0x00 "IFAR,Instruction Fault Address Register" textline " " group c15:0x0016++0x00 line.long 0x00 "RBAR,Region Base Address Register" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 line.long 0x00 "RSER,Region Size and Enable Register" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 line.long 0x00 "RACR,Region Access Control Register" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " TYPE ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" group c15:0x0026++0x00 line.long 0x00 "MRNR,Memory Region Number Register" bitfld.long 0x00 0.--3. " REGION ,Defines the group of registers to be accessed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " group c15:0x010d++0x00 line.long 0x00 "CIDR,Context ID Register" group.long c15:0x20d++0x00 line.long 0x00 "TIDRURW,User read/write Thread and Process ID Register" group.long c15:0x30d++0x00 line.long 0x00 "TIDRURO,User read only Thread and Process ID Register" group.long c15:0x40d++0x00 line.long 0x00 "TIDRPRW,Privileged Only Thread and Process ID Register" tree "MPU regions" group c15:0x0016++0x00 saveout c15:0x26 %l 0x0 line.long 0x00 "RBAR0,Region Base Address Register 0" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x0 line.long 0x00 "RSER0,Region Size and Enable Register 0" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x0 line.long 0x00 "RACR0,Region Access Control Register 0" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x1 line.long 0x00 "RBAR1,Region Base Address Register 1" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x1 line.long 0x00 "RSER1,Region Size and Enable Register 1" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x1 line.long 0x00 "RACR1,Region Access Control Register 1" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x2 line.long 0x00 "RBAR2,Region Base Address Register 2" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x2 line.long 0x00 "RSER2,Region Size and Enable Register 2" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x2 line.long 0x00 "RACR2,Region Access Control Register 2" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x3 line.long 0x00 "RBAR3,Region Base Address Register 3" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x3 line.long 0x00 "RSER3,Region Size and Enable Register 3" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x3 line.long 0x00 "RACR3,Region Access Control Register 3" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x4 line.long 0x00 "RBAR4,Region Base Address Register 4" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x4 line.long 0x00 "RSER4,Region Size and Enable Register 4" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x4 line.long 0x00 "RACR4,Region Access Control Register 4" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x5 line.long 0x00 "RBAR5,Region Base Address Register 5" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x5 line.long 0x00 "RSER5,Region Size and Enable Register 5" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x5 line.long 0x00 "RACR5,Region Access Control Register 5" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x6 line.long 0x00 "RBAR6,Region Base Address Register 6" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x6 line.long 0x00 "RSER6,Region Size and Enable Register 6" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x6 line.long 0x00 "RACR6,Region Access Control Register 6" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x7 line.long 0x00 "RBAR7,Region Base Address Register 7" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x7 line.long 0x00 "RSER7,Region Size and Enable Register 7" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x7 line.long 0x00 "RACR7,Region Access Control Register 7" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x8 line.long 0x00 "RBAR8,Region Base Address Register 8" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x8 line.long 0x00 "RSER8,Region Size and Enable Register 8" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x8 line.long 0x00 "RACR8,Region Access Control Register 8" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x9 line.long 0x00 "RBAR9,Region Base Address Register 9" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x9 line.long 0x00 "RSER9,Region Size and Enable Register 9" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x9 line.long 0x00 "RACR9,Region Access Control Register 9" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0xA line.long 0x00 "RBAR10,Region Base Address Register 10" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0xA line.long 0x00 "RSER10,Region Size and Enable Register 10" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0xA line.long 0x00 "RACR10,Region Access Control Register 10" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0xB line.long 0x00 "RBAR11,Region Base Address Register 11" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0xB line.long 0x00 "RSER11,Region Size and Enable Register 11" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0xB line.long 0x00 "RACR11,Region Access Control Register 11" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " tree.end tree.end width 0x9 tree "TCM Control and Configuration" rgroup.long c15:0x200++0x00 line.long 0x00 "TCMTR,TCM Type Register" bitfld.long 0x00 16.--18. " BTCM ,Number of BTCMs implemented" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " ATCM ,Number of ATCMs implemented" "0,1,2,3,4,5,6,7" group.long c15:0x019++0x00 line.long 0x00 "BTCMRR,BTCM Region Register" hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address (physical address)" bitfld.long 0x00 2.--6. " SIZE ,Size of instruction TCM on reads" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,?..." bitfld.long 0x00 0. " EN ,Enable instruction TCM" "Disabled,Enabled" group.long c15:0x119++0x00 line.long 0x00 "ATCMRR,ATCM Region Register" hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address (physical address)" bitfld.long 0x00 2.--6. " SIZE ,Size of instruction TCM on reads" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,?..." bitfld.long 0x00 0. " EN ,Enable instruction TCM" "Disabled,Enabled" rgroup.long c15:0x29++0x00 line.long 0x00 "TCMSEL,TCM Selection Register" tree.end width 0xC tree "Cache Control and Configuration" rgroup.long c15:0x1100--0x1100 line.long 0x0 "CLIDR,Cache Level ID Register" bitfld.long 0x00 27.--29. " LoU ,Level of Unification" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " LoC ,Level of Coherency" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8" textline " " bitfld.long 0x00 21.--23. " CL8 ,Cache Level (CL) 8" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. " CL7 ,Cache Level (CL) 7" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 15.--17. " CL6 ,Cache Level (CL) 6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. " CL5 ,Cache Level (CL) 5" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 9.--11. " CL4 ,Cache Level (CL) 4" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. " CL3 ,Cache Level (CL) 3" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 3.--5. " CL2 ,Cache Level (CL) 2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " CL1 ,Cache Level (CL) 1" "0,1,2,3,4,5,6,7" rgroup.long c15:0x1000++0x00 line.long 0x00 "CCSIDR,Cache Size ID Register" bitfld.long 0x00 31. " WT ,Write-Through" "Not supported,Supported" bitfld.long 0x00 30. " WB ,Write-Back" "Not supported,Supported" textline " " bitfld.long 0x00 29. " RA ,Read-Allocate" "Not supported,Supported" bitfld.long 0x00 28. " WA ,Write-Allocate" "Not supported,Supported" textline " " hexmask.long.word 0x00 13.--27. 1. " NUMSETS ,Number of sets" hexmask.long.word 0x00 3.--12. 1. " ASSOCIATIVITY ,Associativity" textline " " bitfld.long 0x00 0.--2. " LINESIZE ,Number of words in each cache line" "0,1,2,3,4,5,6,7" group.long c15:0x2000--0x2000 line.long 0x0 "CSSELR,Cache Size Selection Register" bitfld.long 0x00 1.--3. " Level ,Cache level to select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " InD ,Instruction or data or unified cache to use" "Data/unified,Instruction" group.long c15:0x03f++0x00 line.long 0x00 "CFLR,Correctable Fault Location Register" bitfld.long 0x00 26.--29. " WAY ,Way of the error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--25. " SIDE ,Source of the error" "0,1,2,3" textline " " hexmask.long.word 0x00 5.--13. 1. " INDEX ,index of the location where the error occurred" bitfld.long 0x00 0.--1. " TYPE ,Type of access that caused the error" "Instruction cache,Data cache,Reserved,ACP" rgroup.long c15:0x0ef++0x0 line.long 0x00 "CSOR,Cache Size Override Register" bitfld.long 0x00 4.--6. " Dcache ,Validation data cache size" "Not presented,Reserved,Reserved,4k,8k,16k,32k,64k" bitfld.long 0x00 0.--2. " Icache ,Validation instruction cache size" "Not presented,Reserved,Reserved,4k,8k,16k,32k,64k" tree.end width 8. tree "System Performance Monitor" group c15:0xC9--0xC9 line.long 0x0 "PMNC,Performance Monitor Control Register" hexmask.long.byte 0x00 24.--31. 1. " IMP ,Implementer code" hexmask.long.byte 0x00 16.--23. 1. " IDCODE ,Identification code" bitfld.long 0x00 11.--15. " N ,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " DP ,Disable CCNT when prohibited" "Enabled,Disabled" textline " " bitfld.long 0x00 4. " X ,Export Enabled" "Disabled,Enabled" bitfld.long 0x00 3. " D ,Clock Divider" "Every cycle,64th cycle" bitfld.long 0x00 2. " C ,Clock Counter Reset" "No action,Reset" bitfld.long 0x00 1. " P ,Performance Counter Reset" "No action,Reset" textline " " bitfld.long 0x00 0. " E ,Counters Enable" "Disabled,Enabled" group c15:0x1C9--0x1C9 line.long 0x0 "CNTENS,Count Enable Set Register" eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled" eventfld.long 0x00 3. " P3 ,PMN3 Enabled / Enable / Disable counter" "Disabled,Enabled" eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / Disable counter" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / Disable counter" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / Disable counter" "Disabled,Enabled" group c15:0x2C9--0x2C9 line.long 0x0 "CNTENC,Count Enable Clear Register" eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled" eventfld.long 0x00 3. " P3 ,PMN3 Enabled / Enable / Disable counter" "Disabled,Enabled" eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / Disable counter" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / Disable counter" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / Disable counter" "Disabled,Enabled" group c15:0x3C9--0x3C9 line.long 0x0 "FLAG,Overflow Flag Status Register" eventfld.long 0x00 31. " C ,CCNT overflowed" "No overflow,Overflow" eventfld.long 0x00 3. " P3 ,PMN3 overflowed" "No overflow,Overflow" eventfld.long 0x00 2. " P2 ,PMN2 overflowed" "No overflow,Overflow" eventfld.long 0x00 1. " P1 ,PMN1 overflowed" "No overflow,Overflow" eventfld.long 0x00 0. " P0 ,PMN0 overflowed" "No overflow,Overflow" group c15:0x4C9--0x4C9 line.long 0x0 "SWINCR,Software Increment Register" eventfld.long 0x00 3. " P3 ,Increment PMN3" "No action,Increment" eventfld.long 0x00 2. " P2 ,Increment PMN2" "No action,Increment" eventfld.long 0x00 1. " P1 ,Increment PMN1" "No action,Increment" eventfld.long 0x00 0. " P0 ,Increment PMN0" "No action,Increment" group c15:0x5C9--0x5C9 line.long 0x0 "PMNXSEL,Performance Counter Selection Register" bitfld.long 0x00 0.--4. " SEL ,Selection value" "CNT0,CNT1,CNT2,CNT3,?..." group c15:0xD9--0xD9 line.long 0x0 "CCNT,Cycle Count Register" group c15:0x01d9++0x00 line.long 0x00 "ESR,Event Selection Register" hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection" group c15:0x02d9++0x00 line.long 0x00 "PMCR,Performance Monitor Count Register" group c15:0x01d9++0x00 saveout c15:0x5C9 %l 0x0 line.long 0x00 "ESR0,Event Selection Register 0" hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection" group c15:0x02d9++0x00 saveout c15:0x5C9 %l 0x0 line.long 0x00 "PMCR0,Performance Monitor Count Register 0" hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count" group c15:0x01d9++0x00 saveout c15:0x5C9 %l 0x1 line.long 0x00 "ESR1,Event Selection Register 1" hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection" group c15:0x02d9++0x00 saveout c15:0x5C9 %l 0x1 line.long 0x00 "PMCR1,Performance Monitor Count Register 1" hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count" group c15:0x01d9++0x00 saveout c15:0x5C9 %l 0x2 line.long 0x00 "ESR2,Event Selection Register 2" hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection" group c15:0x02d9++0x00 saveout c15:0x5C9 %l 0x2 line.long 0x00 "PMCR2,Performance Monitor Count Register 2" hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count" group c15:0xE9--0xE9 line.long 0x0 "USEREN,User Enable Register" bitfld.long 0x00 0. " EN ,User Mode Enable" "Disabled,Enabled" group c15:0x1E9--0x1E9 line.long 0x0 "INTENS,Interrupt Enable Set Register" eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 3. " P3 ,Interrupt on PMN3 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" group c15:0x2E9--0x2E9 line.long 0x0 "INTENC,Interrupt Enable Clear Register" eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 3. " P3 ,Interrupt on PMN3 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" tree.end width 8. tree "Debug Registers" width 11. tree "Processor Identifier Registers" rgroup c14:0x340--0x340 line.long 0x00 "MIDR,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code" hexmask.long.byte 0x0 20.--23. 0x1 " SPECREV ,Variant number" textline " " hexmask.long.byte 0x0 16.--19. 0x1 " ARCH , Architecture" hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number" textline " " hexmask.long.byte 0x0 0.--3. 0x1 " REV ,Layout Revision" rgroup c14:0x341--0x341 line.long 0x00 "CACHETYPE,Cache Type Register" bitfld.long 0x00 16.--19. " DMINLINE ,Words of Smallest Line Length in L1 or L2 Data Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..." bitfld.long 0x00 14.--15. " L1_IPOLICY ,VIPT Instruction Cache Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " IMINLINE ,Words of Smallest Line Length in L1 or L2 Instruction Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..." rgroup c14:0x343--0x343 line.long 0x00 "TLBTYPE,TLB Type Register" hexmask.long.byte 0x0 16.--23. 0x1 " ILSIZE ,Specifies the number of instruction TLB lockable entries" hexmask.long.byte 0x0 8.--15. 0x1 " DLSIZE ,Specifies the number of unified or data TLB lockable entries" textline " " bitfld.long 0x0 0. " U ,Unified or separate instruction TLBs" "Unified,Separate" rgroup c14:0x348--0x348 line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..." rgroup c14:0x349--0x349 line.long 0x00 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..." bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..." rgroup c14:0x34a--0x34a line.long 0x00 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..." bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..." bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..." rgroup c14:0x34b--0x34b line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" hexmask.long 0x00 0.--31. 1. " AF ,Auxiliary Feature" rgroup c14:0x34c--0x34c line.long 0x00 "ID_MMFR0,Processor Feature Register 0" bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " CC_PLEA ,Cache Coherency With PLE Agent/Shared Memory Support" "Not supported,?..." bitfld.long 0x00 8.--11. " CC_CPUA ,Cache Coherency Support With CPU Agent/Shared Memory Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..." bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..." rgroup c14:0x34d--0x34d line.long 0x00 "ID_MMFR1,Processor Feature Register 1" bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..." bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..." textline " " bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..." textline " " bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..." rgroup c14:0x34e--0x34e line.long 0x00 "ID_MMFR2,Processor Feature Register 2" bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..." bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." rgroup c14:0x34f--0x34f line.long 0x00 "ID_MMFR3,Processor Feature Register 3" bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..." rgroup c14:0x350--0x350 line.long 0x00 "ID_ISAR0,ISA Feature Register 0" bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..." bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..." bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " AI ,Atomic Load and Store Instructions Support" "Reserved,Supported,?..." rgroup c14:0x351--0x351 line.long 0x00 "ID_ISAR1,ISA Feature Register 1" bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " ENDI ,Endianness Control Instructions Support" "Reserved,Supported,?..." rgroup c14:0x352--0x352 line.long 0x00 "ID_ISAR2,ISA Feature Register 2" bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..." textline " " bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..." rgroup c14:0x353--0x353 line.long 0x00 "ID_ISAR3,ISA Feature Register 3" bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " SWII ,SWI Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..." rgroup c14:0x354--0x354 line.long 0x00 "ID_ISAR4,ISA Feature Register 4" bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..." rgroup c14:0x355--0x355 line.long 0x00 "ID_ISAR5,ISA Feature Register 5" tree.end tree "Coresight Management Registers" width 0xC textline " " group c14:0x03bd++0x00 line.long 0x00 "ITCTRL_IOC,Integration Internal Output Control Register" bitfld.long 0x00 5. " I_DBGTRIGGER ,Internal DBGTRIGGER" "0,1" bitfld.long 0x00 4. " I_DBGRESTARTED ,Internal DBGRESTARTED" "0,1" textline " " bitfld.long 0x00 3. " I_NPMUIRQ ,Internal nPMUIRQ" "0,1" bitfld.long 0x00 2. " InternalCOMMTX ,Internal COMMTX" "0,1" textline " " bitfld.long 0x00 1. " I_COMMRX ,Internal COMMRX" "0,1" bitfld.long 0x00 0. " I_DBGACK ,Internal DBGACK" "0,1" group c14:0x03be++0x00 line.long 0x00 "ITCTRL_EOC,Integration External Output Control Register" bitfld.long 0x00 7. " NDMAEXTERRIQ ,External nDMAEXTERRIRQ" "0,1" bitfld.long 0x00 6. " NDMASIRQ ,External nDMASIRQ" "0,1" textline " " bitfld.long 0x00 5. " NDMAIRQ ,External nDMAIRQ" "0,1" bitfld.long 0x00 4. " NPMUIRQ ,External nPMUIRQ" "0,1" textline " " bitfld.long 0x00 3. " STANDBYWFI ,External STANDBYWFI" "0,1" bitfld.long 0x00 2. " COMMTX ,External COMMTX" "0,1" textline " " bitfld.long 0x00 1. " COMMRX ,External COMMRX" "0,1" bitfld.long 0x00 0. " DBGACK ,External DBGACK" "0,1" rgroup c14:0x03bf++0x00 line.long 0x00 "ITCTRL_IS,Integration Input Status Register" bitfld.long 0x00 11. " CTI_DBGRESTART ,CTI Debug Restart" "0,1" bitfld.long 0x00 10. " CTI_EDBGRQ ,CTI Debug Request" "0,1" textline " " bitfld.long 0x00 9. " CTI_PMUEXTIN[1] ,CTI PMUEXTIN[1] Signal" "0,1" bitfld.long 0x00 8. " CTI_PMUEXTIN[0] ,CTI PMUEXTIN[0] Signal" "0,1" textline " " bitfld.long 0x00 2. " NFIQ ,nFIQ Input" "0,1" bitfld.long 0x00 1. " NIRQ ,nIRQ Input" "0,1" textline " " bitfld.long 0x00 0. " EDBGRQ ,EDBGRQ Input" "0,1" group c14:0x3c0--0x3c0 line.long 0x0 "ITCTRL,Integration Mode Control Register" bitfld.long 0x0 0. " IME ,Integration Mode Enable" "Disabled,Enabled" group c14:0x3e8--0x3e8 line.long 0x0 "CLAIMSET,Claim Tag Set Register" bitfld.long 0x0 7. " CT7 ,Claim Tag 7" "No Effect,Set" bitfld.long 0x0 6. " CT6 ,Claim Tag 6" "No Effect,Set" textline " " bitfld.long 0x0 5. " CT5 ,Claim Tag 5" "No Effect,Set" bitfld.long 0x0 4. " CT4 ,Claim Tag 4" "No Effect,Set" textline " " bitfld.long 0x0 3. " CT3 ,Claim Tag 3" "No Effect,Set" bitfld.long 0x0 2. " CT2 ,Claim Tag 2" "No Effect,Set" textline " " bitfld.long 0x0 1. " CT1 ,Claim Tag 1" "No Effect,Set" bitfld.long 0x0 0. " CT0 ,Claim Tag 0" "No Effect,Set" group c14:0x3e9--0x3e9 line.long 0x0 "CLAIMCLR,Claim Tag Clear Register" bitfld.long 0x0 7. " CT7 ,Claim Tag 7" "No Effect,Cleared" bitfld.long 0x0 6. " CT6 ,Claim Tag 6" "No Effect,Cleared" textline " " bitfld.long 0x0 5. " CT5 ,Claim Tag 5" "No Effect,Cleared" bitfld.long 0x0 4. " CT4 ,Claim Tag 4" "No Effect,Cleared" textline " " bitfld.long 0x0 3. " CT3 ,Claim Tag 3" "No Effect,Cleared" bitfld.long 0x0 2. " CT2 ,Claim Tag 2" "No Effect,Cleared" textline " " bitfld.long 0x0 1. " CT1 ,Claim Tag 1" "No Effect,Cleared" bitfld.long 0x0 0. " CT0 ,Claim Tag 0" "No Effect,Cleared" wgroup c14:0x3ec--0x3ec line.long 0x0 "LAR,Lock Access Register" hexmask.long.long 0x0 0.--31. 1. " LACK ,Lock Access Control Key" rgroup c14:0x3ed--0x3ed line.long 0x0 "LSR,Lock Status Register" bitfld.long 0x0 2. " 32ACND ,32-bit Access Needed" "Needed,Not needed" bitfld.long 0x0 1. " WLCK ,Writes Lock" "Permitted,Ignored" textline " " bitfld.long 0x0 0. " LI ,Lock Implementation" "Lock ignored,Unlock required" rgroup c14:0x3ee--0x3ee line.long 0x0 "AUTHSTATUS,Authentication Status Register" bitfld.long 0x0 7. " SNIDFI ,Secure Non-invasive Debug Features Implemented" "Not Implemented,Implemented" bitfld.long 0x0 6. " SNIDE ,Secure Non-invasive Debug Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 5. " SIDFI ,Secure Invasive Debug Feauter Implemented" "Not Implemented,Implemented" bitfld.long 0x0 4. " SIDE ,Secure Invasive Debug Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 3. " NSNIDFI ,Non-secure Non-invasive Debug Feature Implemented" "Not Implemented,Implemented" bitfld.long 0x0 2. " NSNIDE ,Non-secure Non-invasive Debug Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 1. " NSIDFI ,Non-secure Invasive Debug Implemented" "Not Implemented,Implemented" bitfld.long 0x0 0. " NSIDE ,Non-secure Invasive Debug Enable" "Disabled,Enabled" hgroup c14:0x3f2--0x3f2 hide.long 0x0 "DEVID,Device Identifier (RESERVED)" rgroup c14:0x3f3--0x3f3 line.long 0x0 "DEVTYPE,Device Type" hexmask.long.byte 0x00 4.--7. 1. " SUBTYPE ,Subtype" hexmask.long.byte 0x00 0.--3. 1. " MAIN_CLASS ,Main class" rgroup c14:0x3f8--0x3f8 line.long 0x0 "PID0,Peripherial ID0" hexmask.long.byte 0x0 0.--7. 1. " PN ,Part Number [7:0]" rgroup c14:0x3f9--0x3f9 line.long 0x0 "PID1,Peripherial ID1" hexmask.long.byte 0x0 4.--7. 1. " JEP106 ,JEP106 Identity Code [3:0]" hexmask.long.byte 0x0 0.--3. 1. " PN ,Part Number [11:8]" rgroup c14:0x3fa--0x3fa line.long 0x0 "PID2,Peripherial ID2" hexmask.long.byte 0x0 4.--7. 1. " REV ,Revision" hexmask.long.byte 0x0 0.--2. 1. " JEP106 ,JEP106 Identity Code [6:4]" rgroup c14:0x3fb--0x3fb line.long 0x0 "PID3,Peripherial ID3" hexmask.long.byte 0x0 4.--7. 1. " REVA ,RevAnd" hexmask.long.byte 0x0 0.--3. 1. " CMOD ,Customer Modified" rgroup c14:0x3f4--0x3f4 line.long 0x0 "PID4,Peripherial ID4" bitfld.long 0x0 4.--7. " 4KBC ,Number of 4KB Blocks Occupied" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768" bitfld.long 0x0 0.--3. " JEP106 ,JEP106 Continuation Code" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111" rgroup c14:0x3fc--0x3fc line.long 0x0 "COMPONENTID0,Component ID0" hexmask.long.byte 0x0 0.--7. 1. " PRBL ,Preamble" rgroup c14:0x3fd--0x3fd line.long 0x0 "COMPONENTID1,Component ID1" hexmask.long.byte 0x0 4.--7. 1. " CCLASS ,Component Class (CoreSight Component)" hexmask.long.byte 0x0 0.--3. 1. " PRBL ,Preamble" rgroup c14:0x3fe--0x3fe line.long 0x0 "COMPONENTID2,Component ID2" hexmask.long.byte 0x0 0.--7. 1. " PRBL ,Preamble" rgroup c14:0x3ff--0x3ff line.long 0x0 "COMPONENTID3,Component ID3" hexmask.long.byte 0x0 0.--7. 1. " PRBL ,Preamble" tree.end textline " " width 0x7 rgroup c14:0x000--0x000 line.long 0x0 "DIDR,Debug ID Register" bitfld.long 0x0 28.--31. " WRP ,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0 24.--27. " BRP ,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" bitfld.long 0x0 20.--23. " CTX_CMP ,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" textline " " bitfld.long 0x0 16.--19. " VERSION ,Debug Architecture Version" "Reserved,ARMv6,ARMv6.1,ARMv7,?..." textline " " bitfld.long 0x0 13. " PCSAMPLE ,PC Sample register implemented" "Low,High" bitfld.long 0x0 12. " SECURITY ,Security Extensions implemented" "Not implemented,Implemented" textline " " bitfld.long 0x0 4.--7. " VARIANT ,Implementation-defined Variant Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 0.--3. " REVISION ,Implementation-defined Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group c14:0x22--0x22 line.long 0x0 "DSCR,Debug Status and Control Register" bitfld.long 0x0 30. " DTRRXFULL ,The DTRRX Full Flag" "Empty,Full" bitfld.long 0x0 29. " DTRTXfull ,The DTRTX Full Flag" "Empty,Full" textline " " bitfld.long 0x00 27. " DTRRXFULL_L ,The DTRRX Full Flag 1" "Empty,Full" bitfld.long 0x00 26. " DTRTXFULL_L ,The DTRTX Full Flag 1" "Empty,Full" textline " " bitfld.long 0x0 25. " SPA ,Sticky Pipeline Advance" "No effect,Instruction retired" bitfld.long 0x0 24. " IC ,Instruction Complete" "Executing,Not executing" textline " " bitfld.long 0x0 20.--21. " DTR ,DTR Access Mode" "Non-blocking,Stall,Fast,?..." bitfld.long 0x0 19. " NSWS ,Imprecise Data Aborts discarded" "Not discarded,Discarded" textline " " bitfld.long 0x0 18. " NS ,Non-secure World Status" "Secured,Not secured" bitfld.long 0x0 17. " NSPNIDEN ,Secure Non-invasive Debug Disabled" "Enabled,Disabled" textline " " bitfld.long 0x0 16. " NSPIDEN ,Secure Invasive Debug Disabled" "Enabled,Disabled" bitfld.long 0x0 15. " MONITOR ,Monitor Debug-mode enable" "Disabled,Enabled" textline " " bitfld.long 0x0 14. " HDEN ,Halting Debug-mode enable" "Disabled,Enabled" bitfld.long 0x0 13. " EXECUTE ,Execute instruction enable" "Disabled,Enabled" textline " " bitfld.long 0x0 12. " COMMS ,User mode access to Comms Channel disable" "Enabled,Disabled" bitfld.long 0x0 11. " INTDIS ,Disable Interrupts" "Enabled,Disabled" textline " " bitfld.long 0x0 10. " DBGACK ,Force Debug Acknowledge" "Not forced,Forced" bitfld.long 0x0 8. " UEXT ,Sticky Undefined Exception" "No exception,Exception" textline " " bitfld.long 0x0 7. " IABORT ,Sticky Imprecise Abort" "Not aborted,Aborted" bitfld.long 0x0 6. " PABORT ,Sticky Precise Abort" "Not aborted,Aborted" textline " " bitfld.long 0x0 2.--5. " MOE ,Method of Debug Entry" "Debug Entry,Breakpoint,Imprecise Watchpoint,BKPT instruction,External debug,Vector catch,Reserved,Reserved,OS Unlock,?..." bitfld.long 0x0 1. " RESTARTED ,Core Restarted" "Debug not exited,Debug exited" textline " " bitfld.long 0x0 0. " HALTED ,Core Halted" "Normal state,Debug state" if (((data.long(c14:0x00))&0x01000)==0x00000) group c14:0x007--0x007 line.long 0x0 "VCR,Vector Catch Register" bitfld.long 0x0 7. " FIQ ,Vector Catch Enable FIQ" "Disabled,Enabled" bitfld.long 0x0 6. " IRQ ,Vector Catch Enable IRQ" "Disabled,Enabled" textline " " bitfld.long 0x0 4. " DABORT ,Vector Catch Enable Data Abort" "Disabled,Enabled" bitfld.long 0x0 3. " PABORT ,Vector Catch Enable Prefetch Abort" "Disabled,Enabled" textline " " bitfld.long 0x0 2. " SWI ,Vector Catch Enable SWI" "Disabled,Enabled" bitfld.long 0x0 1. " UNDEF ,Vector Catch Enable Undefined Instruction" "Disabled,Enabled" textline " " bitfld.long 0x0 0. " RESET ,Vector Catch Enable Reset" "Disabled,Enabled" else group c14:0x007--0x007 line.long 0x0 "VCR,Vector Catch Register" bitfld.long 0x0 31. " FIQN ,Vector Catch Enable FIQ (Non-secure)" "Disabled,Enabled" bitfld.long 0x0 30. " IRQN ,Vector Catch Enable IRQ (Non-secure)" "Disabled,Enabled" textline " " bitfld.long 0x0 28. " DABORTN ,Vector Catch Enable Data Abort (Non-secure)" "Disabled,Enabled" bitfld.long 0x0 27. " PABORTN ,Vector Catch Enable Prefetch abort (Non-secure)" "Disabled,Enabled" textline " " bitfld.long 0x0 26. " SWIN ,Vector Catch Enable SWI (Non-secure)" "Disabled,Enabled" bitfld.long 0x0 25. " UNDEFS ,Vector Catch Enable Undefined (Non-secure)" "Disabled,Enabled" textline " " bitfld.long 0x0 15. " FIQS ,Vector Catch Enable FIQ (Secure)" "Disabled,Enabled" bitfld.long 0x0 14. " IRQS ,Vector Catch Enable IRQ (Secure)" "Disabled,Enabled" textline " " bitfld.long 0x0 12. " DABORTS ,Vector Catch Enable Data Abort (Secure)" "Disabled,Enabled" bitfld.long 0x00 11. " PABORTS ,Vector Catch Enable Prefetch abort (Secure)" "Disabled,Enabled" textline " " bitfld.long 0x0 10. " SMI ,Vector Catch Enable SMI (Secure)" "Disabled,Enabled" bitfld.long 0x0 7. " FIQ ,Vector Catch Enable FIQ" "Disabled,Enabled" textline " " bitfld.long 0x0 6. " IRQ ,Vector Catch Enable IRQ" "Disabled,Enabled" bitfld.long 0x0 4. " DABORT0 ,Vector Catch Enable Data Abort" "Disabled,Enabled" textline " " bitfld.long 0x0 3. " PABORT ,Vector Catch Enable Prefetch Abort" "Disabled,Enabled" bitfld.long 0x0 2. " SWI ,Vector Catch Enable SWI" "Disabled,Enabled" textline " " bitfld.long 0x0 1. " UNDEF ,Vector Catch Enable Undefined Instruction" "Disabled,Enabled" bitfld.long 0x0 0. " RESET ,Vector Catch Enable Reset" "Disabled,Enabled" endif hgroup c14:0x020--0x020 hide.long 0x0 "DTRRX,Target -> Host Data Transfer Register" in group c14:0x023--0x023 line.long 0x0 "DTRTX,Host -> Target Data Transfer Register" hexmask.long 0x00 0.--31. 1. " HTD ,Host -> target data" group c14:0x09++0x00 line.long 0x00 "ECR,Event Catch Register" bitfld.long 0x00 0. " OSUC ,OS Unlock Catch" "Disabled,Enabled" group c14:0x0a++0x00 line.long 0x00 "DSCCR,Debug State Cache Control Register" bitfld.long 0x00 2. " NWT ,Not Write-Through" "Forced,Normal" bitfld.long 0x00 0. " DUCL ,Data and Unified Cache Linefill" "Disabled,Normal" wgroup c14:0x21++0x00 line.long 0x00 "ITR,Instruction Transfer Register" hexmask.long 0x00 0.--31. 1. " Data ,ARM Instruction for the Processor in Debug State Execute" wgroup c14:0x24++0x00 line.long 0x00 "DRCR,Debug Run Control Register" bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance" "Not cleared,Cleared" bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions" "Not cleared,Cleared" textline " " bitfld.long 0x00 1. " RR ,Restart Request" "Not requested,Requested" bitfld.long 0x00 0. " HR ,Halt Request" "Not requested,Requested" wgroup c14:0xc0++0x00 line.long 0x00 "OSLAR,Operating System Lock Access Register" hexmask.long 0x00 0.--31. 1. " OSLA ,OS Lock Access" rgroup c14:0xc1++0x00 line.long 0x00 "OSLSR,Operating System Lock Status Register" bitfld.long 0x00 2. " 32_BA ,32-Bit Access" "Not required,Required" bitfld.long 0x00 1. " LB ,Locked Bit" "Not locked,Locked" bitfld.long 0x00 0. " LIB ,Lock Implemented Bit" "Not implemented,Implemented" group c14:0xc2++0x00 line.long 0x00 "OSSRR,Operating System Save and Restore Register" hexmask.long 0x00 0.--31. 1. " OSSR ,OS Save and Restore" group c14:0xc4++0x00 line.long 0x00 "PRCR,Device Power-Down and Reset Control Register" bitfld.long 0x00 2. " HIR ,Hold Internal Reset" "Not held,Held" bitfld.long 0x00 1. " FIR ,Force Internal Reset" "Not forced,Forced" bitfld.long 0x00 0. " NPD ,No Power-Down" "DBGNOPWRDWN low,DBGNOPWRDWN high" hgroup c14:0xc5++0x00 hide.long 0x00 "PRSR,Device Power-Down and Reset Status Register" in tree.end tree "Breakpoint Registers" group c14:0x40++0x00 line.long 0x00 "BVR0,Breakpoint Value Register 0" hexmask.long 0x00 0.--31. 1. " BV0 ,Breakpoint Value 0" group c14:0x50++0x00 line.long 0x00 "BCR0,Breakpoint Control Register 0" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group c14:0x41++0x00 line.long 0x00 "BVR1,Breakpoint Value Register 1" hexmask.long 0x00 0.--31. 1. " BV1 ,Breakpoint Value 1" group c14:0x51++0x00 line.long 0x00 "BCR1,Breakpoint Control Register 1" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group c14:0x42++0x00 line.long 0x00 "BVR2,Breakpoint Value Register 2" hexmask.long 0x00 0.--31. 1. " BV2 ,Breakpoint Value 2" group c14:0x52++0x00 line.long 0x00 "BCR2,Breakpoint Control Register 2" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group c14:0x43++0x00 line.long 0x00 "BVR3,Breakpoint Value Register 3" hexmask.long 0x00 0.--31. 1. " BV3 ,Breakpoint Value 3" group c14:0x53++0x00 line.long 0x00 "BCR3,Breakpoint Control Register 3" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group c14:0x44++0x00 line.long 0x00 "BVR4,Breakpoint Value Register 4" hexmask.long 0x00 0.--31. 1. " BV4 ,Breakpoint Value 4" group c14:0x54++0x00 line.long 0x00 "BCR4,Breakpoint Control Register 4" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group c14:0x45++0x00 line.long 0x00 "BVR5,Breakpoint Value Register 5" hexmask.long 0x00 0.--31. 1. " BV5 ,Breakpoint Value 5" group c14:0x55++0x00 line.long 0x00 "BCR5,Breakpoint Control Register 5" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group c14:0x46++0x00 line.long 0x00 "BVR6,Breakpoint Value Register 6" hexmask.long 0x00 0.--31. 1. " BV6 ,Breakpoint Value 6" group c14:0x56++0x00 line.long 0x00 "BCR6,Breakpoint Control Register 6" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group c14:0x47++0x00 line.long 0x00 "BVR7,Breakpoint Value Register 7" hexmask.long 0x00 0.--31. 1. " BV7 ,Breakpoint Value 7" group c14:0x57++0x00 line.long 0x00 "BCR7,Breakpoint Control Register 7" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" tree.end tree "Watchpoint Control Registers" group c14:0x60++0x00 line.long 0x00 "WVR0,Watchpoint Value Register 0" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group c14:0x70--0x70 line.long 0x0 "WCR0,Watchpoint Control Register 0" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group c14:0x61++0x00 line.long 0x00 "WVR1,Watchpoint Value Register 1" hexmask.long 0x00 2.--31. 0x04 " WA1 ,Watchpoint Address 1" group c14:0x71--0x71 line.long 0x0 "WCR1,Watchpoint Control Register 1" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group c14:0x62++0x00 line.long 0x00 "WVR2,Watchpoint Value Register 2" hexmask.long 0x00 2.--31. 0x04 " WA2 ,Watchpoint Address 2" group c14:0x72--0x72 line.long 0x0 "WCR2,Watchpoint Control Register 2" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group c14:0x63++0x00 line.long 0x00 "WVR3,Watchpoint Value Register 3" hexmask.long 0x00 2.--31. 0x04 " WA3 ,Watchpoint Address 3" group c14:0x73--0x73 line.long 0x0 "WCR3,Watchpoint Control Register 3" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group c14:0x64++0x00 line.long 0x00 "WVR4,Watchpoint Value Register 4" hexmask.long 0x00 2.--31. 0x04 " WA4 ,Watchpoint Address 4" group c14:0x74--0x74 line.long 0x0 "WCR4,Watchpoint Control Register 4" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group c14:0x65++0x00 line.long 0x00 "WVR5,Watchpoint Value Register 5" hexmask.long 0x00 2.--31. 0x04 " WA5 ,Watchpoint Address 5" group c14:0x75--0x75 line.long 0x0 "WCR5,Watchpoint Control Register 5" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group c14:0x66++0x00 line.long 0x00 "WVR6,Watchpoint Value Register 6" hexmask.long 0x00 2.--31. 0x04 " WA6 ,Watchpoint Address 6" group c14:0x76--0x76 line.long 0x0 "WCR6,Watchpoint Control Register 6" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group c14:0x67++0x00 line.long 0x00 "WVR7,Watchpoint Value Register 7" hexmask.long 0x00 2.--31. 0x04 " WA7 ,Watchpoint Address 7" group c14:0x77--0x77 line.long 0x0 "WCR7,Watchpoint Control Register 7" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group c14:0x006--0x006 line.long 0x0 "WFAR,Watchpoint Fault Address Register" hexmask.long.long 0x00 1.--31. 0x02 " WFAR ,Address of the watchpointed instruction" tree.end AUTOINDENT.POP tree.end tree "SYS (Primary System Control Registers)" tree "SYS1" base ad:0xFFFFFF00 width 9. tree "System Pin Control Registers" group.long 0x00++0x7 line.long 0x0 "SYSPC1,SYS Pin Control Register 1" bitfld.long 0x00 0. " ECPCLKFUN ,ECPCLK Function" "GIO,ECPCLK" line.long 0x04 "SYSPC2,SYS Pin Control Register 2" bitfld.long 0x04 0. " ECPCLKDIR ,ECPCLK Data Direction" "Input,Output" rgroup.long 0x08++0x3 line.long 0x0 "SYSPC3,SYS Pin Control Register 3" bitfld.long 0x00 0. " ECPCLKDIN ,ECPCLK Data In" "Low,High" sif (cpuis("RM48L950*")) if ((((d.l(ad:0xFFFFFF00))&0x01000000)==0x00)&&(((d.l(ad:0xFFFFFF00+0x04))&0x01000000)==0x01000000)) group.long 0x0C++0x3 line.long 0x0 "SYSPC4,SYS Pin Control Register 4" bitfld.long 0x00 0. " ECPCLKDOUT ,ECPCLK Data Out Write" "Low,High" elif (((d.l(ad:0xFFFFFF00))&0x01000000)==0x00) rgroup.long 0x0C++0x3 line.long 0x0 "SYSPC4,SYS Pin Control Register 4" bitfld.long 0x00 0. " ECPCLKDOUT ,ECPCLK Data Out Write" "Low,High" else hgroup.long 0x0C++0x3 hide.long 0x0 "SYSPC4,SYS Pin Control Register 4" endif else if ((((d.l(ad:0xFFFFFF00))&0x01)==0x00)&&(((d.l(ad:0xFFFFFF00+0x04))&0x01)==0x01)) group.long 0x0C++0x3 line.long 0x0 "SYSPC4,SYS Pin Control Register 4" bitfld.long 0x00 0. " ECPCLKDOUT ,ECPCLK Data Out Write" "Low,High" elif (((d.l(ad:0xFFFFFF00))&0x01)==0x00) rgroup.long 0x0C++0x3 line.long 0x0 "SYSPC4,SYS Pin Control Register 4" bitfld.long 0x00 0. " ECPCLKDOUT ,ECPCLK Data Out Write" "Low,High" else hgroup.long 0x0C++0x3 hide.long 0x0 "SYSPC4,SYS Pin Control Register 4" endif endif sif (cpuis("RM48L950*")) if ((((d.l(ad:0xFFFFFF00))&0x01000000)==0x00)&&(((d.l(ad:0xFFFFFF00+0x04))&0x01000000)==0x01000000)) group.long 0x10++0x7 line.long 0x0 "SYSPC5,SYS Pin Control Register 5" bitfld.long 0x00 0. " ECPCLKSET ,ECPCLK Data Out Set" "Low,High" line.long 0x04 "SYSPC6,SYS Pin Control Register 6" bitfld.long 0x04 0. " ECPCLKCLR ,ECPCLK Data Out clear" "Low,High" else hgroup.long 0x10++0x7 hide.long 0x00 "SYSPC5,SYS Pin Control Register 5" hide.long 0x04 "SYSPC6,SYS Pin Control Register 6" endif else if ((((d.l(ad:0xFFFFFF00))&0x01)==0x00)&&(((d.l(ad:0xFFFFFF00+0x04))&0x01)==0x01)) group.long 0x10++0x7 line.long 0x0 "SYSPC5,SYS Pin Control Register 5" bitfld.long 0x00 0. " ECPCLKSET ,ECPCLK Data Out Set" "Low,High" line.long 0x04 "SYSPC6,SYS Pin Control Register 6" bitfld.long 0x04 0. " ECPCLKCLR ,ECPCLK Data Out clear" "Low,High" else hgroup.long 0x10++0x7 hide.long 0x00 "SYSPC5,SYS Pin Control Register 5" hide.long 0x04 "SYSPC6,SYS Pin Control Register 6" endif endif sif (cpuis("RM48L950*")) if (((d.l(ad:0xFFFFFF00))&0x01000000)==0x00) group.long 0x18++0x3 line.long 0x0 "SYSPC7,SYS Pin Control Register 7" bitfld.long 0x00 0. " ECPCLKODE ,ECPCLK Open Drain Enable" "Push/pull,Open drain" else hgroup.long 0x18++0x3 hide.long 0x0 "SYSPC7,SYS Pin Control Register 7" endif else if (((d.l(ad:0xFFFFFF00))&0x01)==0x00) group.long 0x18++0x3 line.long 0x0 "SYSPC7,SYS Pin Control Register 7" bitfld.long 0x00 0. " ECPCLKODE ,ECPCLK Open Drain Enable" "Push/pull,Open drain" else hgroup.long 0x18++0x3 hide.long 0x0 "SYSPC7,SYS Pin Control Register 7" endif endif sif (cpuis("RM48L950*")) if ((((d.l(ad:0xFFFFFF00))&0x01000000)==0x00)&&(((d.l(ad:0xFFFFFF00+0x04))&0x01000000)==0x00)) group.long 0x1C++0x3 line.long 0x0 "SYSPC8,SYS Pin Control Register 8" bitfld.long 0x00 0. " ECPCLKPULDIS ,ECPCLK Pull Disable" "Active,Inactive" else hgroup.long 0x1C++0x3 hide.long 0x0 "SYSPC8,SYS Pin Control Register 8" endif else if ((((d.l(ad:0xFFFFFF00))&0x01)==0x00)&&(((d.l(ad:0xFFFFFF00+0x04))&0x01)==0x00)) group.long 0x1C++0x3 line.long 0x0 "SYSPC8,SYS Pin Control Register 8" bitfld.long 0x00 0. " ECPCLKPULDIS ,ECPCLK Pull Disable" "Active,Inactive" else hgroup.long 0x1C++0x3 hide.long 0x0 "SYSPC8,SYS Pin Control Register 8" endif endif sif (cpuis("RM48L950*")) if ((((d.l(ad:0xFFFFFF00))&0x01000000)==0x00)&&(((d.l(ad:0xFFFFFF00+0x04))&0x01000000)==0x00)&&(((d.l(ad:0xFFFFFF00+0x1C))&0x01000000)==0x00)) group.long 0x20++0x3 line.long 0x0 "SYSPC9,SYS Pin Control Register 9" bitfld.long 0x00 0. " ECPCLKPSEL ,ECPCLK Pull Up/Pull Down Select" "Down,Up" else hgroup.long 0x20++0x3 hide.long 0x0 "SYSPC9,SYS Pin Control Register 9" endif else if ((((d.l(ad:0xFFFFFF00))&0x01)==0x00)&&(((d.l(ad:0xFFFFFF00+0x04))&0x01)==0x00)&&(((d.l(ad:0xFFFFFF00+0x1C))&0x01)==0x00)) group.long 0x20++0x3 line.long 0x0 "SYSPC9,SYS Pin Control Register 9" bitfld.long 0x00 0. " ECPCLKPSEL ,ECPCLK Pull Up/Pull Down Select" "Down,Up" else hgroup.long 0x20++0x3 hide.long 0x0 "SYSPC9,SYS Pin Control Register 9" endif endif sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")) group.long 0x78++0x3 line.long 0x0 "SYSPC10,SYS Pin Control Register 10" bitfld.long 0x00 0. " ECPCLK_SLEW ,ECPCLK Slew Control" "Fast,Slow" endif tree.end tree "System SSW PLL BIST Control Registers" sif !(cpu()==("TMS570LS2124-PGE")||cpu()==("TMS570LS2124-ZWT")||cpu()==("TMS570LS2125-PGE")||cpu()==("TMS570LS2125-ZWT")||(cpu()=="TMS570LS2126")||(cpu()=="TMS570LS2127")||cpu()==("TMS570LS2134-PGE")||cpu()==("TMS570LS2134-ZWT")||cpu()==("TMS570LS2135-PGE")||cpu()==("TMS570LS2135-ZWT")||(cpu()=="TMS570LS2136")||(cpu()=="TMS570LS2137")||cpu()==("TMS570LS3134-PGE")||cpu()==("TMS570LS3134-ZWT")||cpu()==("TMS570LS3135-PGE")||cpu()==("TMS570LS3135-ZWT")||(cpu()=="TMS570LS3136")||(cpu()=="TMS570LS3137-PGE")||(cpu()=="TMS570LS3137-ZWT")||(cpu()=="TMS570LS30336")||(cpu()=="RM48L950")||cpu()=="RM48L952-PGE"||cpu()=="RM48L952-ZWT"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L540-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE"||cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE"||cpu()=="RM42L432"||cpu()=="RM48L550-ZWT"||cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||!cpuis("TMS570LS1114*")||!cpuis("TMS570LS1115*")||!cpuis("TMS570LS1224*")||!cpuis("TMS570LS1225*")||!cpuis("TMS570LS1227*")) group.long 0x24++0x3 line.long 0x0 "SSWPLL1,SSW PLL BIST Control Register 1" hexmask.long.byte 0x00 8.--15. 1. " CAPTURE_WINDOW_INDEX ,Window capture index" bitfld.long 0x00 6. " COUNTER_READ_READY ,Counter Read Ready" "Not ready,Ready" textline " " bitfld.long 0x00 5. " COUNTER_RESET ,Counter Reset" "No reset,Reset" bitfld.long 0x00 4. " COUNTER_EN ,Counter Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1.--3. " TAP_COUNTER_DIS[3:1] ,TAP Counter Disable" "Bit 16,Bit 18,Bit 20,Bit 22,Bit 24,Bit 26,Bit 28,Bit 30" bitfld.long 0x00 0. " EXT_COUNTER_EN ,Modulation Depth/Frequency Measurement mode" "Modulation Dept,Frequency" rgroup.long 0x28++0x3 line.long 0x0 "SSWPLL2,SSW PLL BIST Control Register 2" rgroup.long 0x2C++0x3 line.long 0x0 "SSWPLL3,SSW PLL BIST Control Register 3" endif tree.end width 7. tree "System Clock Source/Domain Disable Registers" group.long 0x30++0x3 line.long 0x0 "CSDIS,Clock Source Disable Register" sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")) setclrfld.long 0x00 7. 0x04 7. 0x08 7. " CLKSR7_OFF_set/clr ,Clock Source 7 (External Clock In 2) Off" "Enabled,Disabled" textline " " setclrfld.long 0x00 6. 0x04 6. 0x08 6. " CLKSR6_OFF_set/clr ,Clock Source 6 (PLL2) Off" "Enabled,Disabled" endif setclrfld.long 0x00 5. 0x04 5. 0x08 5. " CLKSR5_OFF_set/clr ,Clock Source 5 (LPO High Frequency Clock) Off" "Enabled,Disabled" textline " " setclrfld.long 0x00 4. 0x04 4. 0x08 4. " CLKSR4_OFF_set/clr ,Clock Source 4 (LPO Low Frequency Clock) Off" "Enabled,Disabled" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " CLKSR3_OFF_set/clr ,Clock Source 3 (External Clock In) Off" "Enabled,Disabled" textline " " setclrfld.long 0x00 1. 0x04 1. 0x08 1. " CLKSR1_OFF_set/clr ,Clock Source 1 (PLL1) Off" "Enabled,Disabled" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " CLKSR0_OFF_set/clr ,Clock Source 0 (Oscillator) Off" "Enabled,Disabled" group.long 0x3C++0x3 line.long 0x0 "CDDIS,Clock Domain Disable Register" sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")) setclrfld.long 0x00 11. 0x4 11. 0x8 11. " VCLKA4OFF_set/clr ,VCLKA4 Domain Off" "Enabled,Disabled" setclrfld.long 0x00 10. 0x4 10. 0x8 10. " VCLKA3OFF_set/clr ,VCLKA3 Domain Off" "Enabled,Disabled" textline " " setclrfld.long 0x00 8. 0x4 8. 0x8 8. " VCLK3OFF_set/clr ,VCLK3 Domain Off" "Enabled,Disabled" else setclrfld.long 0x00 9. 0x4 9. 0x8 9. " VCLK_EQEP_OFF_set/clr ,VCLK_EQEP_OFF domain off" "Enabled,Disabled" endif setclrfld.long 0x00 6. 0x4 6. 0x8 6. " RTICLK1OFF_set/clr ,RTICLK1 Domain Off" "Enabled,Disabled" textline " " sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")) setclrfld.long 0x00 5. 0x4 5. 0x8 5. " VCLKA2OFF_set/clr ,VCLKA2 Domain Off" "Enabled,Disabled" endif setclrfld.long 0x00 4. 0x4 4. 0x8 4. " VCLKA1OFF_set/clr ,VCLKA1 Domain Off" "Enabled,Disabled" textline " " setclrfld.long 0x00 3. 0x4 3. 0x8 3. " VCLK2OFF_set/clr ,VCLK2 Domain Off" "Enabled,Disabled" setclrfld.long 0x00 2. 0x4 2. 0x8 2. " VCLKPOFF_set/clr ,VCLKP Domain Off" "Enabled,Disabled" textline " " setclrfld.long 0x00 1. 0x4 1. 0x8 1. " HCLKOFF_set/clr ,HCLK Domain Off" "Enabled,Disabled" setclrfld.long 0x00 0. 0x4 0. 0x8 0. " GCLKOFF_set/clr ,GCLK Domain Off" "Enabled,Disabled" tree.end width 13. group.long 0x48++0x3 line.long 0x0 "GHVSRC,GCLK/HCLK/VCLK and VCLK2 Source Register" sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")) bitfld.long 0x00 24.--27. " GHVWAKE[3:0] ,GCLK/HCLK/VCLK/VCLK2/VCLK3/VCLK4 Source on Wakeup" "Source 0,Source 1,Reserved,Source 3,Source 4,Source 5,?..." bitfld.long 0x00 16.--19. " HVLPM[3:0] ,HCLK/VCLK/VCLK2/VCLK3/VCLK4 Source on Wakeup (GCLK Turned Off)" "Source 0,Source 1,Reserved,Source 3,Source 4,Source 5,?..." textline " " bitfld.long 0x00 0.--3. " GHVSRC[3:0] ,GCLK/HCLK/VCLK/VCLK2/VCLK3/VCLK4 Current Source" "Source 0,Source 1,Reserved,Source 3,Source 4,Source 5,?..." elif (cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")) bitfld.long 0x00 24.--27. " GHVWAKE[3:0] ,GCLK/HCLK/VCLK/VCLK2/VCLK3/VCLK4 Source on Wakeup" "Source 0,Source 1,Reserved,Source 3,Source 4,Source 5,Source 6,Source 7,?..." bitfld.long 0x00 16.--19. " HVLPM[3:0] ,HCLK/VCLK/VCLK2/VCLK3/VCLK4 Source on Wakeup (GCLK Turned Off)" "Source 0,Source 1,Reserved,Source 3,Source 4,Source 5,Source 6,Source 7,?..." textline " " bitfld.long 0x00 0.--3. " GHVSRC[3:0] ,GCLK/HCLK/VCLK/VCLK2/VCLK3/VCLK4 Current Source" "Source 0,Source 1,Reserved,Source 3,Source 4,Source 5,Source 6,Source 7,?..." else bitfld.long 0x00 24.--27. " GHVWAKE[3:0] ,GCLK/HCLK/VCLK/VCLK2/VCLK3/VCLK4 Source on Wakeup" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,?..." bitfld.long 0x00 16.--19. " HVLPM[3:0] ,HCLK/VCLK/VCLK2/VCLK3/VCLK4 Source on Wakeup (GCLK Turned Off)" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,?..." textline " " bitfld.long 0x00 0.--3. " GHVSRC[3:0] ,GCLK/HCLK/VCLK/VCLK2/VCLK3/VCLK4 Current Source" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,?..." endif group.long 0x4C++0x3 line.long 0x0 "VCLKASRC,Peripheral Asynchronous Clock Source Register" sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")) bitfld.long 0x00 0.--3. " VCLKA1S[3:0] ,Peripheral Asynchronous Clock 1 Source" "Source 0,Source 1,Reserved,Source 3,Source 4,Source 5Reserved,Reserved,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,?..." elif (cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")) bitfld.long 0x00 8.--11. " VCLKA2S[3:0] ,Peripheral Asynchronous Clock 2 Source" "Source 0,Source 1,Reserved,Source 3,Source 4,Source 5,Source 6,Source 7,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK" bitfld.long 0x00 0.--3. " VCLKA1S[3:0] ,Peripheral Asynchronous Clock 1 Source" "Source 0,Source 1,Reserved,Source 3,Source 4,Source 5,Source 6,Source 7,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK" else bitfld.long 0x00 8.--11. " VCLKA2S[3:0] ,Peripheral Asynchronous Clock 2 Source" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK" bitfld.long 0x00 0.--3. " VCLKA1S[3:0] ,Peripheral Asynchronous Clock 1 Source" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK" endif group.long 0x50++0x3 line.long 0x0 "RCLKSRC,RTI Clock Source Register" bitfld.long 0x00 8.--9. " RTI1DIV[1:0] ,RTI Clock 1 Divider" "RTICLK1,RTICLK1/2,RTICLK1/4,RTICLK1/8" sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")) bitfld.long 0x00 0.--3. " RTI1SRC[3:0] ,RTI Clock 1 Source" "Source 0,Source 1,Reserved,Source 3,Source 4,Source 5,Reserved,Reserved,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK" elif (cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")) bitfld.long 0x00 0.--3. " RTI1SRC[3:0] ,RTI Clock 1 Source" "Source 0,Source 1,Reserved,Source 3,Source 4,Source 5,Source 6,Source 7,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK" else bitfld.long 0x00 0.--3. " RTI1SRC[3:0] ,RTI Clock 1 Source" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK" endif width 13. rgroup.long 0x54++0x3 line.long 0x0 "CSVSTAT,Clock Source Valid Status Register" sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")) bitfld.long 0x00 7. " CLKSR7V ,Clock Source 7 Valid" "Not valid,Valid" bitfld.long 0x00 6. " CLKSR6V ,Clock Source 6 Valid" "Not valid,Valid" endif bitfld.long 0x00 5. " CLKSR5V ,Clock Source 5 Valid" "Not valid,Valid" textline " " bitfld.long 0x00 4. " CLKSR4V ,Clock Source 4 Valid" "Not valid,Valid" bitfld.long 0x00 3. " CLKSR3V ,Clock Source 3 Valid" "Not valid,Valid" textline " " bitfld.long 0x00 1. " CLKSR1V ,Clock Source 1 Valid" "Not valid,Valid" bitfld.long 0x00 0. " CLKSR0V ,Clock Source 0 Valid" "Not valid,Valid" group.long 0x58++0x3 line.long 0x0 "MSTGCR,Memory Self-Test Global Control Register" sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")) hexmask.long.byte 0x00 16.--23. 1. " MBIST_ALGSEL ,Selects Different Algorithm for MBIST" bitfld.long 0x00 8.--9. " ROM_DIV[1:0] ,ROM Clock Source Prescaler Divider" "HCLK,HCLK/2,HCLK/4,HCLK/8" endif bitfld.long 0x00 0.--3. " MSTGENA[3:0] ,Memory Self-Test Controller Global Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" group.long 0x5C++0x3 line.long 0x0 "MINITGCR,Memory Hardware Initialization Global Control Register" bitfld.long 0x00 0.--3. " MINITGENA[3:0] ,Memory Hardware Initialization Global Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" group.long 0x60++0x3 line.long 0x0 "MSINENA,MBIST Controller/Memory Initialization Enable Register" bitfld.long 0x00 31. " MSIENA31 ,MBIST Controller/Memory Initialization Enable 31" "Disabled,Enabled" bitfld.long 0x00 30. " MSIENA30 ,MBIST Controller/Memory Initialization Enable 30" "Disabled,Enabled" bitfld.long 0x00 29. " MSIENA29 ,MBIST Controller/Memory Initialization Enable 29" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " MSIENA28 ,MBIST Controller/Memory Initialization Enable 28" "Disabled,Enabled" bitfld.long 0x00 27. " MSIENA27 ,MBIST Controller/Memory Initialization Enable 27" "Disabled,Enabled" bitfld.long 0x00 26. " MSIENA26 ,MBIST Controller/Memory Initialization Enable 26" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " MSIENA25 ,MBIST Controller/Memory Initialization Enable 25" "Disabled,Enabled" bitfld.long 0x00 24. " MSIENA24 ,MBIST Controller/Memory Initialization Enable 24" "Disabled,Enabled" bitfld.long 0x00 23. " MSIENA23 ,MBIST Controller/Memory Initialization Enable 23" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " MSIENA22 ,MBIST Controller/Memory Initialization Enable 22" "Disabled,Enabled" bitfld.long 0x00 21. " MSIENA21 ,MBIST Controller/Memory Initialization Enable 21" "Disabled,Enabled" bitfld.long 0x00 20. " MSIENA20 ,MBIST Controller/Memory Initialization Enable 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " MSIENA19 ,MBIST Controller/Memory Initialization Enable 19" "Disabled,Enabled" bitfld.long 0x00 18. " MSIENA18 ,MBIST Controller/Memory Initialization Enable 18" "Disabled,Enabled" bitfld.long 0x00 17. " MSIENA17 ,MBIST Controller/Memory Initialization Enable 17" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " MSIENA16 ,MBIST Controller/Memory Initialization Enable 16" "Disabled,Enabled" bitfld.long 0x00 15. " MSIENA15 ,MBIST Controller/Memory Initialization Enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " MSIENA14 ,MBIST Controller/Memory Initialization Enable 14" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " MSIENA13 ,MBIST Controller/Memory Initialization Enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " MSIENA12 ,MBIST Controller/Memory Initialization Enable 12" "Disabled,Enabled" bitfld.long 0x00 11. " MSIENA11 ,MBIST Controller/Memory Initialization Enable 11" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " MSIENA10 ,MBIST Controller/Memory Initialization Enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " MSIENA9 ,MBIST Controller/Memory Initialization Enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " MSIENA8 ,MBIST Controller/Memory Initialization Enable 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " MSIENA7 ,MBIST Controller/Memory Initialization Enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " MSIENA6 ,MBIST Controller/Memory Initialization Enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " MSIENA5 ,MBIST Controller/Memory Initialization Enable 5" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " MSIENA4 ,MBIST Controller/Memory Initialization Enable 4" "Disabled,Enabled" bitfld.long 0x00 3. " MSIENA3 ,MBIST Controller/Memory Initialization Enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " MSIENA2 ,MBIST Controller/Memory Initialization Enable 2" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " MSIENA1 ,MBIST Controller/Memory Initialization Enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " MSIENA0 ,MBIST Controller/Memory Initialization Enable 0" "Disabled,Enabled" group.long 0x64++0x3 line.long 0x0 "MSTFAIL,Memory Self-Test Fail Status Register" eventfld.long 0x00 31. " MSTF31 ,Memory Self-Test Fail Status 31" "Not failed,Failed" eventfld.long 0x00 30. " MSTF30 ,Memory Self-Test Fail Status 30" "Not failed,Failed" eventfld.long 0x00 29. " MSTF29 ,Memory Self-Test Fail Status 29" "Not failed,Failed" textline " " eventfld.long 0x00 28. " MSTF28 ,Memory Self-Test Fail Status 28" "Not failed,Failed" eventfld.long 0x00 27. " MSTF27 ,Memory Self-Test Fail Status 27" "Not failed,Failed" eventfld.long 0x00 26. " MSTF26 ,Memory Self-Test Fail Status 26" "Not failed,Failed" textline " " eventfld.long 0x00 25. " MSTF25 ,Memory Self-Test Fail Status 25" "Not failed,Failed" eventfld.long 0x00 24. " MSTF24 ,Memory Self-Test Fail Status 24" "Not failed,Failed" eventfld.long 0x00 23. " MSTF23 ,Memory Self-Test Fail Status 23" "Not failed,Failed" textline " " eventfld.long 0x00 22. " MSTF22 ,Memory Self-Test Fail Status 22" "Not failed,Failed" eventfld.long 0x00 21. " MSTF21 ,Memory Self-Test Fail Status 21" "Not failed,Failed" eventfld.long 0x00 20. " MSTF20 ,Memory Self-Test Fail Status 20" "Not failed,Failed" textline " " eventfld.long 0x00 19. " MSTF19 ,Memory Self-Test Fail Status 19" "Not failed,Failed" eventfld.long 0x00 18. " MSTF18 ,Memory Self-Test Fail Status 18" "Not failed,Failed" eventfld.long 0x00 17. " MSTF17 ,Memory Self-Test Fail Status 17" "Not failed,Failed" textline " " eventfld.long 0x00 16. " MSTF16 ,Memory Self-Test Fail Status 16" "Not failed,Failed" eventfld.long 0x00 15. " MSTF15 ,Memory Self-Test Fail Status 15" "Not failed,Failed" eventfld.long 0x00 14. " MSTF14 ,Memory Self-Test Fail Status 14" "Not failed,Failed" textline " " eventfld.long 0x00 13. " MSTF13 ,Memory Self-Test Fail Status 13" "Not failed,Failed" eventfld.long 0x00 12. " MSTF12 ,Memory Self-Test Fail Status 12" "Not failed,Failed" eventfld.long 0x00 11. " MSTF11 ,Memory Self-Test Fail Status 11" "Not failed,Failed" textline " " eventfld.long 0x00 10. " MSTF10 ,Memory Self-Test Fail Status 10" "Not failed,Failed" eventfld.long 0x00 9. " MSTF9 ,Memory Self-Test Fail Status 9" "Not failed,Failed" eventfld.long 0x00 8. " MSTF8 ,Memory Self-Test Fail Status 8" "Not failed,Failed" textline " " eventfld.long 0x00 7. " MSTF7 ,Memory Self-Test Fail Status 7" "Not failed,Failed" eventfld.long 0x00 6. " MSTF6 ,Memory Self-Test Fail Status 6" "Not failed,Failed" eventfld.long 0x00 5. " MSTF5 ,Memory Self-Test Fail Status 5" "Not failed,Failed" textline " " eventfld.long 0x00 4. " MSTF4 ,Memory Self-Test Fail Status 4" "Not failed,Failed" eventfld.long 0x00 3. " MSTF3 ,Memory Self-Test Fail Status 3" "Not failed,Failed" eventfld.long 0x00 2. " MSTF2 ,Memory Self-Test Fail Status 2" "Not failed,Failed" textline " " eventfld.long 0x00 1. " MSTF1 ,Memory Self-Test Fail Status 1" "Not failed,Failed" eventfld.long 0x00 0. " MSTF0 ,Memory Self-Test Fail Status 0" "Not failed,Failed" group.long 0x68++0x3 line.long 0x0 "MSTCGSTAT,MSTC Global Status Register" eventfld.long 0x00 8. " MINIDONE ,Memory Hardware Initililization Test Run Complete Status" "Not completed,Completed" eventfld.long 0x00 0. " MSTDONE ,Memory Self-Test Run Complete Status" "Not completed,Completed" group.long 0x6C++0x3 line.long 0x0 "MINISTAT,Memory Hardware Initialization Status Register" eventfld.long 0x00 31. " MIDONE31 ,Memory Hardware Initialization Status 31" "Not completed,Completed" eventfld.long 0x00 30. " MIDONE30 ,Memory Hardware Initialization Status 30" "Not completed,Completed" textline " " eventfld.long 0x00 29. " MIDONE29 ,Memory Hardware Initialization Status 29" "Not completed,Completed" eventfld.long 0x00 28. " MIDONE28 ,Memory Hardware Initialization Status 28" "Not completed,Completed" textline " " eventfld.long 0x00 27. " MIDONE27 ,Memory Hardware Initialization Status 27" "Not completed,Completed" eventfld.long 0x00 26. " MIDONE26 ,Memory Hardware Initialization Status 26" "Not completed,Completed" textline " " eventfld.long 0x00 25. " MIDONE25 ,Memory Hardware Initialization Status 25" "Not completed,Completed" eventfld.long 0x00 24. " MIDONE24 ,Memory Hardware Initialization Status 24" "Not completed,Completed" textline " " eventfld.long 0x00 23. " MIDONE23 ,Memory Hardware Initialization Status 23" "Not completed,Completed" eventfld.long 0x00 22. " MIDONE22 ,Memory Hardware Initialization Status 22" "Not completed,Completed" textline " " eventfld.long 0x00 21. " MIDONE21 ,Memory Hardware Initialization Status 21" "Not completed,Completed" eventfld.long 0x00 20. " MIDONE20 ,Memory Hardware Initialization Status 20" "Not completed,Completed" textline " " eventfld.long 0x00 19. " MIDONE19 ,Memory Hardware Initialization Status 19" "Not completed,Completed" eventfld.long 0x00 18. " MIDONE18 ,Memory Hardware Initialization Status 18" "Not completed,Completed" textline " " eventfld.long 0x00 17. " MIDONE17 ,Memory Hardware Initialization Status 17" "Not completed,Completed" eventfld.long 0x00 16. " MIDONE16 ,Memory Hardware Initialization Status 16" "Not completed,Completed" textline " " eventfld.long 0x00 15. " MIDONE15 ,Memory Hardware Initialization Status 15" "Not completed,Completed" eventfld.long 0x00 14. " MIDONE14 ,Memory Hardware Initialization Status 14" "Not completed,Completed" textline " " eventfld.long 0x00 13. " MIDONE13 ,Memory Hardware Initialization Status 13" "Not completed,Completed" eventfld.long 0x00 12. " MIDONE12 ,Memory Hardware Initialization Status 12" "Not completed,Completed" textline " " eventfld.long 0x00 11. " MIDONE11 ,Memory Hardware Initialization Status 11" "Not completed,Completed" eventfld.long 0x00 10. " MIDONE10 ,Memory Hardware Initialization Status 10" "Not completed,Completed" textline " " eventfld.long 0x00 9. " MIDONE9 ,Memory Hardware Initialization Status 9" "Not completed,Completed" eventfld.long 0x00 8. " MIDONE8 ,Memory Hardware Initialization Status 8" "Not completed,Completed" textline " " eventfld.long 0x00 7. " MIDONE7 ,Memory Hardware Initialization Status 7" "Not completed,Completed" eventfld.long 0x00 6. " MIDONE6 ,Memory Hardware Initialization Status 6" "Not completed,Completed" textline " " eventfld.long 0x00 5. " MIDONE5 ,Memory Hardware Initialization Status 5" "Not completed,Completed" eventfld.long 0x00 4. " MIDONE4 ,Memory Hardware Initialization Status 4" "Not completed,Completed" textline " " eventfld.long 0x00 3. " MIDONE3 ,Memory Hardware Initialization Status 3" "Not completed,Completed" eventfld.long 0x00 2. " MIDONE2 ,Memory Hardware Initialization Status 2" "Not completed,Completed" textline " " eventfld.long 0x00 1. " MIDONE1 ,Memory Hardware Initialization Status 1" "Not completed,Completed" eventfld.long 0x00 0. " MIDONE0 ,Memory Hardware Initialization Status 0" "Not completed,Completed" width 13. group.long 0x70++0x3 line.long 0x0 "PLLCTL1,PLL Control Register 1" bitfld.long 0x00 31. " ROS ,Reset on PLL Cycle Slip" "No reset,Reset" bitfld.long 0x00 29.--30. " MASK_SLIP ,Mask detection of PLL slip" "Enabled,Enabled,Disabled,Enabled" bitfld.long 0x00 24.--28. " PLLDIV ,PLL Output Clock Divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" textline " " bitfld.long 0x00 23. " ROF ,Reset on Oscillator Fail" "No reset,Reset" bitfld.long 0x00 16.--21. " REFCLKDIV ,Reference Clock Divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" hexmask.long.word 0x00 0.--15. 1. " PLLMUL ,PLL Multiplication Factor" group.long 0x74++0x3 line.long 0x0 "PLLCTL2,PLL Control Register 2" bitfld.long 0x00 31. " FMENA ,Frequency Modulation Enable" "Disabled,Enabled" hexmask.long.word 0x00 22.--30. 1. " SPREADINGRATE ,Spreadingrate" hexmask.long.word 0x00 12.--20. 1. " MULMOD ,Multiplier Correction when Frequency Modulation is enabled" textline " " bitfld.long 0x00 9.--11. " ODPLL ,Internal PLL Output Divider" "/1,/2,/3,/4,/5,/6,/7,/8" hexmask.long.word 0x00 0.--8. 1. " SPR_AMOUNT ,Spreading Amount" rgroup.long 0x7C++0x3 line.long 0x0 "DIEIDL,Die Identification Register Lower Word" hexmask.long.word 0x00 22.--31. 1. " LOT ,Lower 10 bits of the device lot number" bitfld.long 0x00 16.--21. " WAFER ,Wafer number of the device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " hexmask.long.byte 0x00 8.--15. 1. " Y_WAFER ,Y wafer coordinate of the device" hexmask.long.byte 0x00 0.--7. 1. " X_WAFER ,X wafer coordinate of the device" rgroup.long 0x80++0x3 line.long 0x0 "DIEIDH,Die Identification Register Upper Word" hexmask.long.word 0x00 0.--13. 1. " LOT ,Upper 14 bits of the device lot number" width 13. group.long 0x88++0x3 line.long 0x0 "LPOMONCTL,LPO/Clock Monitor Control Register" bitfld.long 0x00 24. " BIAS_ENABLE ,Bias Enable" "Disabled,Enabled" bitfld.long 0x00 16. " OSCFRQCONFIGCNT ,Configures the counter based on OSC frequency" "<= 20MHz,> 20MHz & <= 80MHz" textline " " sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")) bitfld.long 0x00 8.--12. " HFTRIM[4-0] ,High frequency oscillator trim value" "29.52%,34.24%,38.85%,43.45%,47.99%,52.55%,57.02%,61.46%,65.92%,70.17%,74.55%,78.92%,83.17%,87.43%,91.75%,95.89%,100.00%,104.09%,108.17%,112.32%,116.41%,120.67%,124.42%,128.38%,132.24%,136.15%,140.15%,143.94%,148.02%,151.80%,155.50%,159.35%" bitfld.long 0x00 0.--4. " LFTRIM[4-0] ,Low frequency oscillator trim value" "20.67%,25.76%,30.84%,35.90%,40.93%,45.95%,50.97%,55.91%,60.86%,65.78%,70.75%,75.63%,80.61%,85.39%,90.23%,95.11%,100.00%,104.84%,109.51%,114.31%,119.01%,123.75%,128.62%,133.31%,138.03%,142.75%,147.32%,152.02%,156.63%,161.38%,165.90%,170.42%" else bitfld.long 0x00 8.--11. " HFTRIM[3-0] ,High frequency oscillator trim value" "29.52%,38.85%,47.99%,57.02%,65.92%,74.55%,83.17%,91.75%,100.00%,108.17%,116.41%,124.42%,132.24%,140.15%,148.02%,155.50%" bitfld.long 0x00 0.--3. " LFTRIM[3-0] ,Low frequency oscillator trim value" "20.67%,30.84%,40.93%,50.97%,60.86%,70.75%,80.61%,90.23%,100.00%,109.51%,119.01%,128.62%,138.03%,147.32%,156.63%,165.90%" endif width 13. group.long 0x8C++0x3 line.long 0x0 "CLKTEST,Clock Test Register" bitfld.long 0x00 26. " ALTLIMPCLOCKENABLE ,Alternate Limp Clock Enable" "10-MHz LPO,ALTLIMPCLOCK" textline " " bitfld.long 0x00 25. " RANGEDETCTRL ,Range Detection Control" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " RANGEDETENSSEL ,Range Detection Enable Select" "Hardware,CLKTEST[RANGEDETCTRL]" textline " " bitfld.long 0x00 16.--19. " CLK_TEST_EN[3:0] ,Clock Test Enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" textline " " sif (cpu()=="RM48L952-PGE"||cpu()=="RM48L952-ZWT"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L540-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE"||cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE"||cpu()=="RM48L550-ZWT"||!cpuis("TMS570LS1114*")||!cpuis("TMS570LS1115*")||!cpuis("TMS570LS1224*")||!cpuis("TMS570LS1225*")||!cpuis("TMS570LS1227*")) bitfld.long 0x00 8.--11. " SEL_GIO_PIN[3:0] ,Clock Source Valid Signal/Clock Source at Functional GIO Pin Select" "Oscillator,PLL,Reserved,Reserved,Reserved,High frequency clock LPO,Secondary PLL,Reserved,Low frequency clock LPO,Oscillator,Oscillator,Oscillator,Oscillator,Oscillator,Oscillator,Oscillator" elif (cpu()=="RM42L432") bitfld.long 0x00 8.--11. " SEL_N2HET_PIN[3:0] ,N2HET[2] pin clock source valid/select" "Oscillator,PLL,Reserved,Reserved,Reserved,High frequency clock LPO,Secondary PLL,Reserved,Low frequency clock LPO,Oscillator,Oscillator,Oscillator,Oscillator,Oscillator,Oscillator,Oscillator" elif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")) bitfld.long 0x00 8.--11. " SEL_N2HET_PIN[3:0] ,N2HET[2] pin clock source valid/select" "Oscillator,PLL,Reserved,Reserved,Reserved,High frequency clock LPO,Reserved,Reserved,Low frequency clock LPO,Oscillator,Oscillator,Oscillator,Oscillator,Oscillator,Oscillator,Oscillator" else bitfld.long 0x00 8.--11. " SEL_GIO_PIN[3:0] ,Clock Source Valid Signal/Clock Source at Functional GIO Pin Select" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,Source 4/pin,?..." endif textline " " bitfld.long 0x00 0.--3. " SEL_ECP_PIN[3:0] ,Clock at ECP Pin Select" "Oscillator,PLL,Reserved,EXTCLKIN1,LPO low,LPO high,Secondary PLL,EXCLKIN2,GCLK,RTI Base,Reserved,VCLKA1,VCLKA2,VCLKA3_S,VCLKA4,Flash HD Pump Oscillator" width 13. group.long 0x90++0x3 line.long 0x0 "DFTCTRLREG,DFT Control Register" bitfld.long 0x00 12.--13. " DFTWRITE ,DFT Logic Access Mode" "Stress/Slow,Stress/Fast,Screen/Slow,Screen/Fast" bitfld.long 0x00 8.--9. " DFTREAD ,DFT Logic Access" "Stress/Slow,Stress/Fast,Screen/Slow,Screen/Fast" bitfld.long 0x00 0.--3. " TEST_MODE_KEY ,Test Mode Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" group.long 0x94++0x3 line.long 0x0 "DFTCTRLREG2,DFT Control Register" bitfld.long 0x00 31. " IMPDF[27] ,DFT Implementation Defined Bit[27]" "Disabled,Enabled" bitfld.long 0x00 30. " IMPDF[26] ,DFT Implementation Defined Bit[26]" "Disabled,Enabled" bitfld.long 0x00 29. " IMPDF[25] ,DFT Implementation Defined Bit[25]" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " IMPDF[24] ,DFT Implementation Defined Bit[24]" "Disabled,Enabled" bitfld.long 0x00 27. " IMPDF[23] ,DFT Implementation Defined Bit[23]" "Disabled,Enabled" bitfld.long 0x00 26. " IMPDF[22] ,DFT Implementation Defined Bit[22]" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " IMPDF[21] ,DFT Implementation Defined Bit[21]" "Disabled,Enabled" bitfld.long 0x00 24. " IMPDF[20] ,DFT Implementation Defined Bit[20]" "Disabled,Enabled" bitfld.long 0x00 23. " IMPDF[19] ,DFT Implementation Defined Bit[19]" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " IMPDF[18] ,DFT Implementation Defined Bit[18]" "Disabled,Enabled" bitfld.long 0x00 21. " IMPDF[17] ,DFT Implementation Defined Bit[17]" "Disabled,Enabled" bitfld.long 0x00 20. " IMPDF[16] ,DFT Implementation Defined Bit[16]" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " IMPDF[15] ,DFT Implementation Defined Bit[15]" "Disabled,Enabled" bitfld.long 0x00 18. " IMPDF[14] ,DFT Implementation Defined Bit[14]" "Disabled,Enabled" bitfld.long 0x00 17. " IMPDF[13] ,DFT Implementation Defined Bit[13]" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " IMPDF[12] ,DFT Implementation Defined Bit[12]" "Disabled,Enabled" bitfld.long 0x00 15. " IMPDF[11] ,DFT Implementation Defined Bit[11]" "Disabled,Enabled" bitfld.long 0x00 14. " IMPDF[10] ,DFT Implementation Defined Bit[10]" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " IMPDF[9] ,DFT Implementation Defined Bit[9]" "Disabled,Enabled" bitfld.long 0x00 12. " IMPDF[8] ,DFT Implementation Defined Bit[8]" "Disabled,Enabled" bitfld.long 0x00 11. " IMPDF[7] ,DFT Implementation Defined Bit[7]" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " IMPDF[6] ,DFT Implementation Defined Bit[6]" "Disabled,Enabled" bitfld.long 0x00 9. " IMPDF[5] ,DFT Implementation Defined Bit[5]" "Disabled,Enabled" bitfld.long 0x00 8. " IMPDF[4] ,DFT Implementation Defined Bit[4]" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " IMPDF[3] ,DFT Implementation Defined Bit[3]" "Disabled,Enabled" bitfld.long 0x00 6. " IMPDF[2] ,DFT Implementation Defined Bit[2]" "Disabled,Enabled" bitfld.long 0x00 5. " IMPDF[1] ,DFT Implementation Defined Bit[1]" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " IMPDF[0] ,DFT Implementation Defined Bit[0]" "Disabled,Enabled" bitfld.long 0x00 0.--3. " TEST_MODE_KEY ,Test Mode Key (Internal TI Use Only)" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" width 13. group.long 0xA0++0x3 line.long 0x0 "GPREG1,General Purpose Register 1" bitfld.long 0x00 20.--25. " PLL1_FBSLIP_FILTER_COUNT ,FBSLIP down counter programmed value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 16.--19. " PLL1_RFSLIP_FILTER_KEY ,Configures the system response when a FBSLIP is indicated by the PLL macro" "Reserved,Reserved,Reserved,Reserved,Reserved,Bypassed,Reserved,Reserved,Reserved,Reserved,One-stage synchronization,Reserved,Reserved,Reserved,Reserved,Two-stage synchronization" sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")) sif (!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")) textline " " bitfld.long 0x00 15. " OUTPUT_BUFFER_LOW_EMI_MODE[15] ,EMI mode for RTP enable" "Enabled,Disabled" endif textline " " bitfld.long 0x00 14. " OUTPUT_BUFFER_LOW_EMI_MODE[14] ,EMI mode for ADEVT enable" "Enabled,Disabled" textline " " bitfld.long 0x00 13. " OUTPUT_BUFFER_LOW_EMI_MODE[13] ,EMI mode for nERROR enable" "Enabled,Disabled" textline " " bitfld.long 0x00 12. " OUTPUT_BUFFER_LOW_EMI_MODE[12] ,EMI mode for TEST enable" "Enabled,Disabled" textline " " bitfld.long 0x00 11. " OUTPUT_BUFFER_LOW_EMI_MODE[11] ,EMI mode for RTCK enable" "Enabled,Disabled" textline " " bitfld.long 0x00 10. " OUTPUT_BUFFER_LOW_EMI_MODE[10] ,EMI mode for TD0 enable" "Enabled,Disabled" textline " " bitfld.long 0x00 9. " OUTPUT_BUFFER_LOW_EMI_MODE[9] ,EMI mode for TDI enable" "Enabled,Disabled" textline " " bitfld.long 0x00 8. " OUTPUT_BUFFER_LOW_EMI_MODE[8] ,EMI mode for TMS enable" "Enabled,Disabled" textline " " bitfld.long 0x00 7. " OUTPUT_BUFFER_LOW_EMI_MODE[7] ,EMI mode for ETM enable" "Enabled,Disabled" textline " " bitfld.long 0x00 6. " OUTPUT_BUFFER_LOW_EMI_MODE[6] ,EMI mode for EMIF enable" "Enabled,Disabled" textline " " bitfld.long 0x00 5. " OUTPUT_BUFFER_LOW_EMI_MODE[5] ,EMI mode for FlexRay enable" "Enabled,Disabled" textline " " bitfld.long 0x00 4. " OUTPUT_BUFFER_LOW_EMI_MODE[4] ,EMI mode for MiBSPI5 enable" "Enabled,Disabled" textline " " bitfld.long 0x00 3. " OUTPUT_BUFFER_LOW_EMI_MODE[3] ,EMI mode for SPI4 enable" "Enabled,Disabled" textline " " bitfld.long 0x00 2. " OUTPUT_BUFFER_LOW_EMI_MODE[2] ,EMI mode for MiBSPI3 enable" "Enabled,Disabled" textline " " bitfld.long 0x00 1. " OUTPUT_BUFFER_LOW_EMI_MODE[1] ,EMI mode for SPI2 enable" "Enabled,Disabled" textline " " bitfld.long 0x00 0. " OUTPUT_BUFFER_LOW_EMI_MODE[0] ,EMI mode for MiBSPI1 enable" "Enabled,Disabled" endif hgroup.long 0xA8++0x3 hide.long 0x0 "IMPFASTS,Imprecise Fault Status Register" in rgroup.long 0xAC++0x3 line.long 0x0 "IMPFTADD,Imprecise Fault Write Address Register" width 14. tree "System Software Interrupt Request Registers" group.long 0xB0++0x3 line.long 0x0 "SSIR1,System Software Interrupt Request 1 Register" hexmask.long.byte 0x00 8.--15. 1. " SSKEY1[7:0] ,System Software Interrupt Request Key" hexmask.long.byte 0x00 0.--7. 1. " SSDATA1[7:0] ,System Software Interrupt Data" group.long 0xB4++0x3 line.long 0x0 "SSIR2,System Software Interrupt Request 2 Register" hexmask.long.byte 0x00 8.--15. 1. " SSKEY2[7:0] ,System Software Interrupt 2 Request Key" hexmask.long.byte 0x00 0.--7. 1. " SSDATA2[7:0] ,System Software Interrupt 2 Data" group.long 0xB8++0x3 line.long 0x0 "SSIR3,System Software Interrupt Request 3 Register" hexmask.long.byte 0x00 8.--15. 1. " SSKEY3[7:0] ,System Software Interrupt 3 Request Key" hexmask.long.byte 0x00 0.--7. 1. " SSDATA3[7:0] ,System Software Interrupt 3 Data" group.long 0xBC++0x3 line.long 0x0 "SSIR4,System Software Interrupt Request 4 Register" hexmask.long.byte 0x00 8.--15. 1. " SSKEY4[7:0] ,System Software Interrupt 3 Request Key" hexmask.long.byte 0x00 0.--7. 1. " SSDATA4[7:0] ,System Software Interrupt 4 Data" tree.end width 10. group.long 0xC0++0x3 line.long 0x0 "RAMGCR,RAM Control Register" bitfld.long 0x00 16.--19. " RAM_DFT_EN[3:0] ,Functional Mode RAM DFT Port Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" textline " " bitfld.long 0x00 2. " WST_AENA0 ,eSRAM0 Data Phase Wait State Enable" "Disabled,Enabled" bitfld.long 0x00 0. " WST_DENA0 ,eSRAM0 Data Phase Wait State Enable" "Disabled,Enabled" group.long 0xC4++0x3 line.long 0x0 "BMMCR1,Bus Matrix Module Control Register1" bitfld.long 0x00 0.--3. " MEMSW[3:0] ,Memory Swap Bit Key" "Reserved,Reserved,Reserved,Reserved,Reserved,Swapped,Reserved,Reserved,Reserved,Reserved,Default,?..." sif (cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&cpu()!="RM42L432"&&cpu()!="RM48L550-ZWT"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")) group.long 0xC8++0x3 line.long 0x0 "BMMCR2,Bus Matrix Module Control Register2" endif group.long 0xCC++0x3 line.long 0x0 "CPURSTCR,CPU Reset Control Register" bitfld.long 0x00 0. " CPU_RESET ,Cpu reset" "No reset,Reset" group.long 0xD0++0x3 line.long 0x0 "CLKCNTL,Clock Control Register" bitfld.long 0x00 24.--27. " VCLKR2[3:0] ,VBUS Clock 2 Ratio" "HCLK,HCLK/2,HCLK/3,HCLK/4,HCLK/5,HCLK/6,HCLK/7,HCLK/8,HCLK/9,HCLK/10,HCLK/11,HCLK/12,HCLK/13,HCLK/14,HCLK/15,HCLK/16" bitfld.long 0x00 16.--19. " VCLKR[3:0] ,VBUS Clock Ratio" "HCLK,HCLK/2,HCLK/3,HCLK/4,HCLK/5,HCLK/6,HCLK/7,HCLK/8,HCLK/9,HCLK/10,HCLK/11,HCLK/12,HCLK/13,HCLK/14,HCLK/15,HCLK/16" bitfld.long 0x00 8. " PENA ,Peripheral Enable" "Reset,No reset" group.long 0xD4++0x3 line.long 0x0 "ECPCNTRL,ECP Control Register" bitfld.long 0x00 24. " ECPSSEL ,ECP Source Clock Select for ECP Module" "Oscillator,VCLK" bitfld.long 0x00 23. " ECPCOS ,ECP Continue on Suspend" "Suspended,Continue" bitfld.long 0x00 16.--17. " ECPINSEL ,Select ECP Input Clock Source" "Tied Low,HCLK,External,Tied Low" textline " " hexmask.long.word 0x00 0.--15. 1. " ECPDIV[15:0] ,ECP Divider Value" group.long 0xDC++0x3 line.long 0x0 "DEVCR1,DEV Parity Control Register1" bitfld.long 0x00 0.--3. " DEVPARSEL ,Device Parity Select Bit Key" "Reserved,Reserved,Reserved,Reserved,Reserved,Even,Reserved,Reserved,Reserved,Reserved,Odd,?..." group.long 0xE0++0x3 line.long 0x0 "SYSECR,System Exception Control Register" bitfld.long 0x00 14.--15. " RESET[1:0] ,Software Reset" "Reset,No reset,Reset,Reset" width 10. group.long 0xE4++0x3 line.long 0x0 "SYSESR,System Exception Status Register" eventfld.long 0x00 15. " PORST ,Power-Up Reset" "No reset,Reset" eventfld.long 0x00 14. " OSCRST ,Oscillator Failure/PLL Cycle Slip Reset" "No reset,Reset" eventfld.long 0x00 13. " WDRST ,Watchdog Reset Flag" "No reset,Reset" textline " " eventfld.long 0x00 5. " CPURST ,CPU Reset Flag" "No reset,Reset" eventfld.long 0x00 4. " SWRST ,Software Reset Flag" "No reset,Reset" eventfld.long 0x00 3. " EXTRST ,External Reset Flag" "No reset,Reset" textline " " eventfld.long 0x00 0. " MPMODE ,This indicates the current memory protection unit (MPU) mode" "Disabled,Enabled" group.long 0xE8++0x3 line.long 0x0 "SYSTASR,System Test Abort Status Register" bitfld.long 0x00 0.--4. " EFUSE_ABORT[4:0] ,Test Abort Status Flag" "Read: Last operation,Read: Controller times out,Read: Autoload/Not find FuseROM,Read: Autoload/Scan chain,Read: Autoload/Not completed operation,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Write: Cleared" width 10. group.long 0xEC++0x3 line.long 0x0 "GLBSTAT,Global Status Register" eventfld.long 0x00 9. " FBSLIP ,Over Cycle Slip Detection of PLL" "Not detected,Detected" eventfld.long 0x00 8. " RFSLIP ,Under Cycle Slip Detection of PLL" "Not detected,Detected" eventfld.long 0x00 0. " OSCFAIL ,Oscillator Fail Flag" "Not failed,Failed" rgroup.long 0xF0++0x3 line.long 0x0 "DEVID,Device Identification Register" bitfld.long 0x00 31. " CP15 ,CP15 CPU" "CP15,No CP15" hexmask.long.word 0x00 17.--30. 1. " UNIQUE_ID ,Device ID" bitfld.long 0x00 13.--16. " TECH ,Device Manufacture Process Technology" "C05,F05,C035,F035,C021,F021,?..." textline " " bitfld.long 0x00 12. " I/O_VOLTAGE ,Input/Output Voltage" "3.3 V,5 V" bitfld.long 0x00 11. " PERIPHERAL_PARITY ,Peripheral Parity" "No parity,Parity" bitfld.long 0x00 9.--10. " FLASH_ECC ,Program Memory Parity Present" "Not protected,Single bit,ECC,?..." textline " " bitfld.long 0x00 8. " RAM_RECC ,RAM ECC" "No ECC,ECC" hexmask.long.byte 0x00 3.--7. 1. " VERSION ,Version" hexmask.long.byte 0x00 0.--2. 1. " PLATFORM_ID ,The TMS570Px Platform ID" hgroup.long 0xF4++0x3 hide.long 0x0 "SSIVEC,Software Interrupt Vector Register" in width 10. group.long 0xF8++0x3 line.long 0x0 "SSIF,System Software Interrupt Flag Register" eventfld.long 0x00 3. " SSI_FLAG4 ,System Software Interrupt Flag 4" "No interrupt,Interrupt" eventfld.long 0x00 2. " SSI_FLAG43 ,System Software Interrupt Flag 3" "No interrupt,Interrupt" textline " " eventfld.long 0x00 1. " SSI_FLAG42 ,System Software Interrupt Flag 2" "No interrupt,Interrupt" eventfld.long 0x00 0. " SSI_FLAG41 ,System Software Interrupt Flag 1" "No interrupt,Interrupt" width 11. tree.end tree "SYS2" base ad:0xFFFFE100 sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")) endian.be endif width 15. sif (cpu()!="RM42L432"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*")&&!cpuis("TMS570LS0232")) group.long 0x00++0x03 line.long 0x00 "PLLCTL3,PLL Control Register 3" bitfld.long 0x00 29.--31. " ODPLL2 ,Internal PLL output divider" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 24.--28. " PLLDIV2 ,PLL#2 output clock divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" newline bitfld.long 0x00 16.--21. " REFCLKDIV2 ,Reference clock divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" hexmask.long.word 0x00 0.--15. 1. " PLL_MUL2 ,PLL multiplication" endif group.long 0x08++0x03 line.long 0x00 "STCLKDIV,CPU Logic BIST Clock Divider" bitfld.long 0x00 24.--26. " CLKDIV ,Clock divider/prescaler for CPU clock during logic BIST" "/1,/2,/3,/4,/5,/6,/7,/8" sif !cpuis("RM48L952-PGE")&&!cpuis("RM48L952-ZWT")&&!cpuis("RM48L952-PGE")&&!cpuis("RM48L952-ZWT")&&!cpuis("RM48L950-PGE")&&!cpuis("RM48L950-ZWT")&&!cpuis("RM48L940-ZWT")&&!cpuis("RM48L940-PGE")&&!cpuis("RM48L930-ZWT")&&!cpuis("RM48L930-PGE")&&!cpuis("RM48L750-ZWT")&&!cpuis("RM48L750-PGE")&&!cpuis("RM48L740-ZWT")&&!cpuis("RM48L740-PGE")&&!cpuis("RM48L730-ZWT")&&!cpuis("RM48L730-PGE")&&!cpuis("RM48L550-PGE")&&!cpuis("RM48L540-ZWT")&&!cpuis("RM48L540-PGE")&&!cpuis("RM48L530-ZWT")&&!cpuis("RM48L530-PGE")&&!cpuis("RM48L550-ZWT")&&!cpuis("RM42L432")&&!cpuis("TMS570LS0332")&&!cpuis("TMS570LS0432")&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS0232")&&!cpuis("TMS570LS3137-EP") sif cpuis("RM46L852-PGE")||cpuis("RM46L852-ZWT")||cpuis("RM46L850-PGE")||cpuis("RM46L850-ZWT")||cpuis("RM46L840-ZWT")||cpuis("RM46L840-PGE")||cpuis("RM46L830-ZWT")||cpuis("RM46L830-PGE")||cpuis("RM46L450-ZWT")||cpuis("RM46L450-PGE")||cpuis("RM46L440-ZWT")||cpuis("RM46L440-PGE")||cpuis("RM46L430-ZWT")||cpuis("RM46L430-PGE")||cpuis("TMS570LS09*")||cpuis("TMS570LS07*") group.long 0x24++0x03 line.long 0x00 "ECPCNTL,ECP Control Register 1" bitfld.long 0x00 24. " ECPSSEL ,Allows the selection between VCLK and OSCIN as the clock source for ECLK2" "VCLK,OSCIN" bitfld.long 0x00 23. " ECPCOS ,ECP continue on suspend" "Disabled,Enabled" newline bitfld.long 0x00 16.--17. " ECPINSEL ,Select ECP input clock source" "Tied Low,HCLK,External clock,Tied Low" hexmask.long.word 0x00 0.--15. 1. " ECPDIV ,ECP divider value" else group.long 0x0C++0xB line.long 0x00 "CLKHB_GLBREG,Clock Hibernate Mode Global Enable Register" line.long 0x04 "CLKHB_RTIDREG,Clocked Hibernate RTI Domain Control Register" line.long 0x08 "HBCD_STAT,Hibernate Clock Domain Status Register" group.long 0x20++0x03 line.long 0x00 "CLKTRMI1,Clock Trim 1 Register" endif endif sif !cpuis("TMS570LS0232") sif (cpu()!="RM42L432"||cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")) group.long 0x3C++0x03 line.long 0x00 "CLK2CNTRL,Clock 2 Control Register" sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")) bitfld.long 0x00 8.--11. " VCLK4R ,VBUS clock4 ratio" "HCLK,HCLK/2,HCLK/3,HCLK/4,HCLK/5,HCLK/6,HCLK/7,HCLK/8,HCLK/9,HCLK/10,HCLK/11,HCLK/12,HCLK/13,HCLK/14,HCLK/15,HCLK/16" else bitfld.long 0x00 0.--3. " VCLK3R ,VBUS clock3 ratio" "HCLK,HCLK/2,HCLK/3,HCLK/4,HCLK/5,HCLK/6,HCLK/7,HCLK/8,HCLK/9,HCLK/10,HCLK/11,HCLK/12,HCLK/13,HCLK/14,HCLK/15,HCLK/16" endif sif (!cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*")) group.long 0x40++0x03 line.long 0x00 "VCLKACON1,Peripheral Asynchronous Clock Configuration 1 Register" bitfld.long 0x00 24.--26. " VCLKA4R ,Clock divider for the VCLKA4 source" "VCLKA4,VCLKA4/2,VCLKA4/3,VCLKA4/4,VCLKA4/5,VCLKA4/6,VCLKA4/7,VCLKA4/8" bitfld.long 0x00 20. " VCLKA4_DIV_CDDIS ,Disable the VCLKA4 divider output" "No,Yes" newline sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")) bitfld.long 0x00 16.--19. " VCLKA4S ,Peripheral asynchronous clock4 source" "Source 0,Source 1,,Source 3,Source 4,Source 5,Source 6,Source 7,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK" newline else bitfld.long 0x00 16.--19. " VCLKA4S ,Peripheral asynchronous clock4 source" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK" newline endif sif !cpuis("TMS570LS3137-EP") bitfld.long 0x00 8.--10. " VCLKA3R ,Clock divider for the VCLKA3 source" "VCLKA3,VCLKA3/2,VCLKA3/3,VCLKA3/4,VCLKA3/5,VCLKA3/6,VCLKA3/7,VCLKA3/8" bitfld.long 0x00 4. " VCLKA3_DIV_CDDIS ,Disable the VCLKA3 divider output" "No,Yes" newline sif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")) bitfld.long 0x00 0.--3. " VCLKA3S ,Peripheral asynchronous clock3 source" "Source 0,Source 1,,Source 3,Source 4,Source 5,Source 6,Source 7,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK" else bitfld.long 0x00 0.--3. " VCLKA3S ,Peripheral asynchronous clock3 source" "Source 0,Source 1,Source 2,Source 3,Source 4,Source 5,Source 6,Source 7,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK" endif endif endif endif endif group.long 0x70++0x03 line.long 0x00 "CLKSLIP,Clock Slip Register" sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")) bitfld.long 0x00 8.--13. " PLL1_SLIP_FILTER_COUNT ,Configure the count for the filtered PLL slip" "Disabled,Every slip recognized,At least 2 HF LPO cycles,At least 3 HF LPO cycles,At least 4 HF LPO cycles,At least 5 HF LPO cycles,At least 6 HF LPO cycles,At least 7 HF LPO cycles,At least 8 HF LPO cycles,At least 9 HF LPO cycles,At least 10 HF LPO cycles,At least 11 HF LPO cycles,At least 12 HF LPO cycles,At least 13 HF LPO cycles,At least 14 HF LPO cycles,At least 15 HF LPO cycles,At least 16 HF LPO cycles,At least 17 HF LPO cycles,At least 18 HF LPO cycles,At least 19 HF LPO cycles,At least 20 HF LPO cycles,At least 21 HF LPO cycles,At least 22 HF LPO cycles,At least 23 HF LPO cycles,At least 24 HF LPO cycles,At least 25 HF LPO cycles,At least 26 HF LPO cycles,At least 27 HF LPO cycles,At least 28 HF LPO cycles,At least 29 HF LPO cycles,At least 30 HF LPO cycles,At least 31 HF LPO cycles,At least 32 HF LPO cycles,At least 33 HF LPO cycles,At least 34 HF LPO cycles,At least 35 HF LPO cycles,At least 36 HF LPO cycles,At least 37 HF LPO cycles,At least 38 HF LPO cycles,At least 39 HF LPO cycles,At least 40 HF LPO cycles,At least 41 HF LPO cycles,At least 42 HF LPO cycles,At least 43 HF LPO cycles,At least 44 HF LPO cycles,At least 45 HF LPO cycles,At least 46 HF LPO cycles,At least 47 HF LPO cycles,At least 48 HF LPO cycles,At least 49 HF LPO cycles,At least 50 HF LPO cycles,At least 51 HF LPO cycles,At least 52 HF LPO cycles,At least 53 HF LPO cycles,At least 54 HF LPO cycles,At least 55 HF LPO cycles,At least 56 HF LPO cycles,At least 57 HF LPO cycles,At least 58 HF LPO cycles,At least 59 HF LPO cycles,At least 60 HF LPO cycles,At least 61 HF LPO cycles,At least 62 HF LPO cycles,At least 63 HF LPO cycles" newline else bitfld.long 0x00 8.--13. " PLL1_SLIP_FILTER_COUNT ,Configure the count for the filtered PLL slip" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline endif bitfld.long 0x00 0.--3. " PLL1_SLIP_FILTER_KEY ,Enable the PLL filtering" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,?..." group.long 0xEC++0x03 line.long 0x00 "EFC_CTLREG,EFUSE Controller Control Register" bitfld.long 0x00 0.--3. " EFC_INSTR_WEN ,Enable user write of 4 EFUSE controller instructions" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" rgroup.long 0xF0++0x0F line.long 0x00 "DIEIDL_REG0,Die Identification Register Lower Word" sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")||cpuis("TMS570LS3137-EP")) hexmask.long.byte 0x00 24.--31. 1. " WAFER# ,Wafer number of the device" hexmask.long.word 0x00 12.--23. 1. " Y_WAFER_COORDINATE ,Y wafer coordinate of the device" hexmask.long.word 0x00 0.--11. 1. " X_WAFER_COORDINATE ,X wafer coordinate of the device" endif line.long 0x04 "DIEIDH_REG1,Die Identification Register Upper Word" sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")||cpuis("TMS570LS3137-EP")) hexmask.long.tbyte 0x04 0.--23. 1. " LOT# ,Device lot number" endif line.long 0x08 "DIEIDH_REG2,Die Identification Register Lower Word" line.long 0x0C "DIEIDH_REG3,Die Identification Register Upper Word" sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")) endian.le endif width 0x0B tree.end tree "PCR (Peripheral Central Resource)" base ad:0xFFFFE000 width 12. tree "PCR Protection Registers" tree "PCR Memory Protection Registers" group.long 0x00++0x3 line.long 0x0 "PMPROTSET0,Set-only Register to Protect PCS Frames 0 to 31" setclrfld.long 0x00 31. 0x00 31. 0x10 31. " PCS31PROT_set/clr ,Peripheral Memory Frame Protection 31" "Not protected,Protected" setclrfld.long 0x00 30. 0x00 30. 0x10 30. " PCS30PROT_set/clr ,Peripheral Memory Frame Protection 30" "Not protected,Protected" textline " " setclrfld.long 0x00 29. 0x00 29. 0x10 29. " PCS29PROT_set/clr ,Peripheral Memory Frame Protection 29" "Not protected,Protected" setclrfld.long 0x00 28. 0x00 28. 0x10 28. " PCS28PROT_set/clr ,Peripheral Memory Frame Protection 28" "Not protected,Protected" textline " " setclrfld.long 0x00 27. 0x00 27. 0x10 27. " PCS27PROT_set/clr ,Peripheral Memory Frame Protection 27" "Not protected,Protected" setclrfld.long 0x00 26. 0x00 26. 0x10 26. " PCS26PROT_set/clr ,Peripheral Memory Frame Protection 26" "Not protected,Protected" textline " " setclrfld.long 0x00 25. 0x00 25. 0x10 25. " PCS25PROT_set/clr ,Peripheral Memory Frame Protection 25" "Not protected,Protected" setclrfld.long 0x00 24. 0x00 24. 0x10 24. " PCS24PROT_set/clr ,Peripheral Memory Frame Protection 24" "Not protected,Protected" textline " " setclrfld.long 0x00 23. 0x00 23. 0x10 23. " PCS23PROT_set/clr ,Peripheral Memory Frame Protection 23" "Not protected,Protected" setclrfld.long 0x00 22. 0x00 22. 0x10 22. " PCS22PROT_set/clr ,Peripheral Memory Frame Protection 22" "Not protected,Protected" textline " " setclrfld.long 0x00 21. 0x00 21. 0x10 21. " PCS21PROT_set/clr ,Peripheral Memory Frame Protection 21" "Not protected,Protected" setclrfld.long 0x00 20. 0x00 20. 0x10 20. " PCS20PROT_set/clr ,Peripheral Memory Frame Protection 20" "Not protected,Protected" textline " " setclrfld.long 0x00 19. 0x00 19. 0x10 19. " PCS19PROT_set/clr ,Peripheral Memory Frame Protection 19" "Not protected,Protected" setclrfld.long 0x00 18. 0x00 18. 0x10 18. " PCS18PROT_set/clr ,Peripheral Memory Frame Protection 18" "Not protected,Protected" textline " " setclrfld.long 0x00 17. 0x00 17. 0x10 17. " PCS17PROT_set/clr ,Peripheral Memory Frame Protection 17" "Not protected,Protected" setclrfld.long 0x00 16. 0x00 16. 0x10 16. " PCS16PROT_set/clr ,Peripheral Memory Frame Protection 16" "Not protected,Protected" textline " " setclrfld.long 0x00 15. 0x00 15. 0x10 15. " PCS15PROT_set/clr ,Peripheral Memory Frame Protection 15" "Not protected,Protected" setclrfld.long 0x00 14. 0x00 14. 0x10 14. " PCS14PROT_set/clr ,Peripheral Memory Frame Protection 14" "Not protected,Protected" textline " " setclrfld.long 0x00 13. 0x00 13. 0x10 13. " PCS13PROT_set/clr ,Peripheral Memory Frame Protection 13" "Not protected,Protected" setclrfld.long 0x00 12. 0x00 12. 0x10 12. " PCS12PROT_set/clr ,Peripheral Memory Frame Protection 12" "Not protected,Protected" textline " " setclrfld.long 0x00 11. 0x00 11. 0x10 11. " PCS11PROT_set/clr ,Peripheral Memory Frame Protection 11" "Not protected,Protected" setclrfld.long 0x00 10. 0x00 10. 0x10 10. " PCS10PROT_set/clr ,Peripheral Memory Frame Protection 10" "Not protected,Protected" textline " " setclrfld.long 0x00 9. 0x00 9. 0x10 9. " PCS9PROT_set/clr ,Peripheral Memory Frame Protection 9" "Not protected,Protected" setclrfld.long 0x00 8. 0x00 8. 0x10 8. " PCS8PROT_set/clr ,Peripheral Memory Frame Protection 8" "Not protected,Protected" textline " " setclrfld.long 0x00 7. 0x00 7. 0x10 7. " PCS7PROT_set/clr ,Peripheral Memory Frame Protection 7" "Not protected,Protected" setclrfld.long 0x00 6. 0x00 6. 0x10 6. " PCS6PROT_set/clr ,Peripheral Memory Frame Protection 6" "Not protected,Protected" textline " " setclrfld.long 0x00 5. 0x00 5. 0x10 5. " PCS5PROT_set/clr ,Peripheral Memory Frame Protection 5" "Not protected,Protected" setclrfld.long 0x00 4. 0x00 4. 0x10 4. " PCS4PROT_set/clr ,Peripheral Memory Frame Protection 4" "Not protected,Protected" textline " " setclrfld.long 0x00 3. 0x00 3. 0x10 3. " PCS3PROT_set/clr ,Peripheral Memory Frame Protection 3" "Not protected,Protected" setclrfld.long 0x00 2. 0x00 2. 0x10 2. " PCS2PROT_set/clr ,Peripheral Memory Frame Protection 2" "Not protected,Protected" textline " " setclrfld.long 0x00 1. 0x00 1. 0x10 1. " PCS1PROT_set/clr ,Peripheral Memory Frame Protection 1" "Not protected,Protected" setclrfld.long 0x00 0. 0x00 0. 0x10 0. " PCS0PROT_set/clr ,Peripheral Memory Frame Protection 0" "Not protected,Protected" group.long 0x04++0x3 line.long 0x0 "PMPROTSET1,Set-only Register to Protect PCS Frames 32 to 63" setclrfld.long 0x00 31. 0x00 31. 0x10 31. " PCS63PROT_set/clr ,Peripheral Memory Frame Protection 63" "Not protected,Protected" setclrfld.long 0x00 30. 0x00 30. 0x10 30. " PCS62PROT_set/clr ,Peripheral Memory Frame Protection 62" "Not protected,Protected" textline " " setclrfld.long 0x00 29. 0x00 29. 0x10 29. " PCS61PROT_set/clr ,Peripheral Memory Frame Protection 61" "Not protected,Protected" setclrfld.long 0x00 28. 0x00 28. 0x10 28. " PCS60PROT_set/clr ,Peripheral Memory Frame Protection 60" "Not protected,Protected" textline " " setclrfld.long 0x00 27. 0x00 27. 0x10 27. " PCS59PROT_set/clr ,Peripheral Memory Frame Protection 59" "Not protected,Protected" setclrfld.long 0x00 26. 0x00 26. 0x10 26. " PCS58PROT_set/clr ,Peripheral Memory Frame Protection 58" "Not protected,Protected" textline " " setclrfld.long 0x00 25. 0x00 25. 0x10 25. " PCS57PROT_set/clr ,Peripheral Memory Frame Protection 57" "Not protected,Protected" setclrfld.long 0x00 24. 0x00 24. 0x10 24. " PCS56PROT_set/clr ,Peripheral Memory Frame Protection 56" "Not protected,Protected" textline " " setclrfld.long 0x00 23. 0x00 23. 0x10 23. " PCS55PROT_set/clr ,Peripheral Memory Frame Protection 55" "Not protected,Protected" setclrfld.long 0x00 22. 0x00 22. 0x10 22. " PCS54PROT_set/clr ,Peripheral Memory Frame Protection 54" "Not protected,Protected" textline " " setclrfld.long 0x00 21. 0x00 21. 0x10 21. " PCS53PROT_set/clr ,Peripheral Memory Frame Protection 53" "Not protected,Protected" setclrfld.long 0x00 20. 0x00 20. 0x10 20. " PCS52PROT_set/clr ,Peripheral Memory Frame Protection 52" "Not protected,Protected" textline " " setclrfld.long 0x00 19. 0x00 19. 0x10 19. " PCS51PROT_set/clr ,Peripheral Memory Frame Protection 51" "Not protected,Protected" setclrfld.long 0x00 18. 0x00 18. 0x10 18. " PCS50PROT_set/clr ,Peripheral Memory Frame Protection 50" "Not protected,Protected" textline " " setclrfld.long 0x00 17. 0x00 17. 0x10 17. " PCS49PROT_set/clr ,Peripheral Memory Frame Protection 49" "Not protected,Protected" setclrfld.long 0x00 16. 0x00 16. 0x10 16. " PCS48PROT_set/clr ,Peripheral Memory Frame Protection 48" "Not protected,Protected" textline " " setclrfld.long 0x00 15. 0x00 15. 0x10 15. " PCS47PROT_set/clr ,Peripheral Memory Frame Protection 47" "Not protected,Protected" setclrfld.long 0x00 14. 0x00 14. 0x10 14. " PCS46PROT_set/clr ,Peripheral Memory Frame Protection 46" "Not protected,Protected" textline " " setclrfld.long 0x00 13. 0x00 13. 0x10 13. " PCS45PROT_set/clr ,Peripheral Memory Frame Protection 45" "Not protected,Protected" setclrfld.long 0x00 12. 0x00 12. 0x10 12. " PCS44PROT_set/clr ,Peripheral Memory Frame Protection 44" "Not protected,Protected" textline " " setclrfld.long 0x00 11. 0x00 11. 0x10 11. " PCS43PROT_set/clr ,Peripheral Memory Frame Protection 43" "Not protected,Protected" setclrfld.long 0x00 10. 0x00 10. 0x10 10. " PCS42PROT_set/clr ,Peripheral Memory Frame Protection 42" "Not protected,Protected" textline " " setclrfld.long 0x00 9. 0x00 9. 0x10 9. " PCS41PROT_set/clr ,Peripheral Memory Frame Protection 41" "Not protected,Protected" setclrfld.long 0x00 8. 0x00 8. 0x10 8. " PCS40PROT_set/clr ,Peripheral Memory Frame Protection 40" "Not protected,Protected" textline " " setclrfld.long 0x00 7. 0x00 7. 0x10 7. " PCS39PROT_set/clr ,Peripheral Memory Frame Protection 39" "Not protected,Protected" setclrfld.long 0x00 6. 0x00 6. 0x10 6. " PCS38PROT_set/clr ,Peripheral Memory Frame Protection 38" "Not protected,Protected" textline " " setclrfld.long 0x00 5. 0x00 5. 0x10 5. " PCS37PROT_set/clr ,Peripheral Memory Frame Protection 37" "Not protected,Protected" setclrfld.long 0x00 4. 0x00 4. 0x10 4. " PCS36PROT_set/clr ,Peripheral Memory Frame Protection 36" "Not protected,Protected" textline " " setclrfld.long 0x00 3. 0x00 3. 0x10 3. " PCS35PROT_set/clr ,Peripheral Memory Frame Protection 35" "Not protected,Protected" setclrfld.long 0x00 2. 0x00 2. 0x10 2. " PCS34PROT_set/clr ,Peripheral Memory Frame Protection 34" "Not protected,Protected" textline " " setclrfld.long 0x00 1. 0x00 1. 0x10 1. " PCS33PROT_set/clr ,Peripheral Memory Frame Protection 33" "Not protected,Protected" setclrfld.long 0x00 0. 0x00 0. 0x10 0. " PCS32PROT_set/clr ,Peripheral Memory Frame Protection 32" "Not protected,Protected" tree.end width 12. textline " " group.long 0x20++0x3 line.long 0x0 "PPROTSET0,Set-only Register to Protect the 32 Quadrants of PS0 to PS7" setclrfld.long 0x00 31. 0x00 31. 0x20 31. " PCS7QUAD3PROT_set/clr ,Peripheral Protection 7 3" "Not protected,Protected" textline " " setclrfld.long 0x00 30. 0x00 30. 0x20 30. " PCS7QUAD2PROT_set/clr ,Peripheral Protection 7 2" "Not protected,Protected" textline " " setclrfld.long 0x00 29. 0x00 29. 0x20 29. " PCS7QUAD1PROT_set/clr ,Peripheral Protection 7 1" "Not protected,Protected" textline " " setclrfld.long 0x00 28. 0x00 28. 0x20 28. " PCS7QUAD0PROT_set/clr ,Peripheral Protection 7 0" "Not protected,Protected" textline " " setclrfld.long 0x00 27. 0x00 27. 0x20 27. " PCS6QUAD3PROT_set/clr ,Peripheral Protection 6 3" "Not protected,Protected" textline " " setclrfld.long 0x00 26. 0x00 26. 0x20 26. " PCS6QUAD2PROT_set/clr ,Peripheral Protection 6 2" "Not protected,Protected" textline " " setclrfld.long 0x00 25. 0x00 25. 0x20 25. " PCS6QUAD1PROT_set/clr ,Peripheral Protection 6 1" "Not protected,Protected" textline " " setclrfld.long 0x00 24. 0x00 24. 0x20 24. " PCS6QUAD0PROT_set/clr ,Peripheral Protection 6 0" "Not protected,Protected" textline " " setclrfld.long 0x00 23. 0x00 23. 0x20 23. " PCS5QUAD3PROT_set/clr ,Peripheral Protection 5 3" "Not protected,Protected" textline " " setclrfld.long 0x00 22. 0x00 22. 0x20 22. " PCS5QUAD2PROT_set/clr ,Peripheral Protection 5 2" "Not protected,Protected" textline " " setclrfld.long 0x00 21. 0x00 21. 0x20 21. " PCS5QUAD1PROT_set/clr ,Peripheral Protection 5 1" "Not protected,Protected" textline " " setclrfld.long 0x00 20. 0x00 20. 0x20 20. " PCS5QUAD0PROT_set/clr ,Peripheral Protection 5 0" "Not protected,Protected" textline " " setclrfld.long 0x00 19. 0x00 19. 0x20 19. " PCS4QUAD3PROT_set/clr ,Peripheral Protection 4 3" "Not protected,Protected" textline " " setclrfld.long 0x00 18. 0x00 18. 0x20 18. " PCS4QUAD2PROT_set/clr ,Peripheral Protection 4 2" "Not protected,Protected" textline " " setclrfld.long 0x00 17. 0x00 17. 0x20 17. " PCS4QUAD1PROT_set/clr ,Peripheral Protection 4 1" "Not protected,Protected" textline " " setclrfld.long 0x00 16. 0x00 16. 0x20 16. " PCS4QUAD0PROT_set/clr ,Peripheral Protection 4 0" "Not protected,Protected" textline " " setclrfld.long 0x00 15. 0x00 15. 0x20 15. " PCS3QUAD3PROT_set/clr ,Peripheral Protection 3 3" "Not protected,Protected" textline " " setclrfld.long 0x00 14. 0x00 14. 0x20 14. " PCS3QUAD2PROT_set/clr ,Peripheral Protection 3 2" "Not protected,Protected" textline " " setclrfld.long 0x00 13. 0x00 13. 0x20 13. " PCS3QUAD1PROT_set/clr ,Peripheral Protection 3 1" "Not protected,Protected" textline " " setclrfld.long 0x00 12. 0x00 12. 0x20 12. " PCS3QUAD0PROT_set/clr ,Peripheral Protection 3 0" "Not protected,Protected" textline " " setclrfld.long 0x00 11. 0x00 11. 0x20 11. " PCS2QUAD3PROT_set/clr ,Peripheral Protection 2 3" "Not protected,Protected" textline " " setclrfld.long 0x00 10. 0x00 10. 0x20 10. " PCS2QUAD2PROT_set/clr ,Peripheral Protection 2 2" "Not protected,Protected" textline " " setclrfld.long 0x00 9. 0x00 9. 0x20 9. " PCS2QUAD1PROT_set/clr ,Peripheral Protection 2 1" "Not protected,Protected" textline " " setclrfld.long 0x00 8. 0x00 8. 0x20 8. " PCS2QUAD0PROT_set/clr ,Peripheral Protection 2 0" "Not protected,Protected" textline " " setclrfld.long 0x00 7. 0x00 7. 0x20 7. " PCS1QUAD3PROT_set/clr ,Peripheral Protection 1 3" "Not protected,Protected" textline " " setclrfld.long 0x00 6. 0x00 6. 0x20 6. " PCS1QUAD2PROT_set/clr ,Peripheral Protection 1 2" "Not protected,Protected" textline " " setclrfld.long 0x00 5. 0x00 5. 0x20 5. " PCS1QUAD1PROT_set/clr ,Peripheral Protection 1 1" "Not protected,Protected" textline " " setclrfld.long 0x00 4. 0x00 4. 0x20 4. " PCS1QUAD0PROT_set/clr ,Peripheral Protection 1 0" "Not protected,Protected" textline " " setclrfld.long 0x00 3. 0x00 3. 0x20 3. " PCS0QUAD3PROT_set/clr ,Peripheral Protection 0 3" "Not protected,Protected" textline " " setclrfld.long 0x00 2. 0x00 2. 0x20 2. " PCS0QUAD2PROT_set/clr ,Peripheral Protection 0 2" "Not protected,Protected" textline " " setclrfld.long 0x00 1. 0x00 1. 0x20 1. " PCS0QUAD1PROT_set/clr ,Peripheral Protection 0 1" "Not protected,Protected" textline " " setclrfld.long 0x00 0. 0x00 0. 0x20 0. " PCS0QUAD0PROT_set/clr ,Peripheral Protection 0 0" "Not protected,Protected" group.long 0x24++0x3 line.long 0x0 "PPROTSET1,Set-only Register to Protect the 32 Quadrants of PS8 to PS15" setclrfld.long 0x00 31. 0x00 31. 0x20 31. " PCS15QUAD3PROT_set/clr ,Peripheral Protection 15 3" "Not protected,Protected" textline " " setclrfld.long 0x00 30. 0x00 30. 0x20 30. " PCS15QUAD2PROT_set/clr ,Peripheral Protection 15 2" "Not protected,Protected" textline " " setclrfld.long 0x00 29. 0x00 29. 0x20 29. " PCS15QUAD1PROT_set/clr ,Peripheral Protection 15 1" "Not protected,Protected" textline " " setclrfld.long 0x00 28. 0x00 28. 0x20 28. " PCS15QUAD0PROT_set/clr ,Peripheral Protection 15 0" "Not protected,Protected" textline " " setclrfld.long 0x00 27. 0x00 27. 0x20 27. " PCS14QUAD3PROT_set/clr ,Peripheral Protection 14 3" "Not protected,Protected" textline " " setclrfld.long 0x00 26. 0x00 26. 0x20 26. " PCS14QUAD2PROT_set/clr ,Peripheral Protection 14 2" "Not protected,Protected" textline " " setclrfld.long 0x00 25. 0x00 25. 0x20 25. " PCS14QUAD1PROT_set/clr ,Peripheral Protection 14 1" "Not protected,Protected" textline " " setclrfld.long 0x00 24. 0x00 24. 0x20 24. " PCS14QUAD0PROT_set/clr ,Peripheral Protection 14 0" "Not protected,Protected" textline " " setclrfld.long 0x00 23. 0x00 23. 0x20 23. " PCS13QUAD3PROT_set/clr ,Peripheral Protection 13 3" "Not protected,Protected" textline " " setclrfld.long 0x00 22. 0x00 22. 0x20 22. " PCS13QUAD2PROT_set/clr ,Peripheral Protection 13 2" "Not protected,Protected" textline " " setclrfld.long 0x00 21. 0x00 21. 0x20 21. " PCS13QUAD1PROT_set/clr ,Peripheral Protection 13 1" "Not protected,Protected" textline " " setclrfld.long 0x00 20. 0x00 20. 0x20 20. " PCS13QUAD0PROT_set/clr ,Peripheral Protection 13 0" "Not protected,Protected" textline " " setclrfld.long 0x00 19. 0x00 19. 0x20 19. " PCS12QUAD3PROT_set/clr ,Peripheral Protection 12 3" "Not protected,Protected" textline " " setclrfld.long 0x00 18. 0x00 18. 0x20 18. " PCS12QUAD2PROT_set/clr ,Peripheral Protection 12 2" "Not protected,Protected" textline " " setclrfld.long 0x00 17. 0x00 17. 0x20 17. " PCS12QUAD1PROT_set/clr ,Peripheral Protection 12 1" "Not protected,Protected" textline " " setclrfld.long 0x00 16. 0x00 16. 0x20 16. " PCS12QUAD0PROT_set/clr ,Peripheral Protection 12 0" "Not protected,Protected" textline " " setclrfld.long 0x00 15. 0x00 15. 0x20 15. " PCS11QUAD3PROT_set/clr ,Peripheral Protection 11 3" "Not protected,Protected" textline " " setclrfld.long 0x00 14. 0x00 14. 0x20 14. " PCS11QUAD2PROT_set/clr ,Peripheral Protection 11 2" "Not protected,Protected" textline " " setclrfld.long 0x00 13. 0x00 13. 0x20 13. " PCS11QUAD1PROT_set/clr ,Peripheral Protection 11 1" "Not protected,Protected" textline " " setclrfld.long 0x00 12. 0x00 12. 0x20 12. " PCS11QUAD0PROT_set/clr ,Peripheral Protection 11 0" "Not protected,Protected" textline " " setclrfld.long 0x00 11. 0x00 11. 0x20 11. " PCS10QUAD3PROT_set/clr ,Peripheral Protection 10 3" "Not protected,Protected" textline " " setclrfld.long 0x00 10. 0x00 10. 0x20 10. " PCS10QUAD2PROT_set/clr ,Peripheral Protection 10 2" "Not protected,Protected" textline " " setclrfld.long 0x00 9. 0x00 9. 0x20 9. " PCS10QUAD1PROT_set/clr ,Peripheral Protection 10 1" "Not protected,Protected" textline " " setclrfld.long 0x00 8. 0x00 8. 0x20 8. " PCS10QUAD0PROT_set/clr ,Peripheral Protection 10 0" "Not protected,Protected" textline " " setclrfld.long 0x00 7. 0x00 7. 0x20 7. " PCS9QUAD3PROT_set/clr ,Peripheral Protection 9 3" "Not protected,Protected" textline " " setclrfld.long 0x00 6. 0x00 6. 0x20 6. " PCS9QUAD2PROT_set/clr ,Peripheral Protection 9 2" "Not protected,Protected" textline " " setclrfld.long 0x00 5. 0x00 5. 0x20 5. " PCS9QUAD1PROT_set/clr ,Peripheral Protection 9 1" "Not protected,Protected" textline " " setclrfld.long 0x00 4. 0x00 4. 0x20 4. " PCS9QUAD0PROT_set/clr ,Peripheral Protection 9 0" "Not protected,Protected" textline " " setclrfld.long 0x00 3. 0x00 3. 0x20 3. " PCS8QUAD3PROT_set/clr ,Peripheral Protection 8 3" "Not protected,Protected" textline " " setclrfld.long 0x00 2. 0x00 2. 0x20 2. " PCS8QUAD2PROT_set/clr ,Peripheral Protection 8 2" "Not protected,Protected" textline " " setclrfld.long 0x00 1. 0x00 1. 0x20 1. " PCS8QUAD1PROT_set/clr ,Peripheral Protection 8 1" "Not protected,Protected" textline " " setclrfld.long 0x00 0. 0x00 0. 0x20 0. " PCS8QUAD0PROT_set/clr ,Peripheral Protection 8 0" "Not protected,Protected" group.long 0x28++0x3 line.long 0x0 "PPROTSET2,Set-only Register to Protect the 32 Quadrants of PS16 to PS23" setclrfld.long 0x00 31. 0x00 31. 0x20 31. " PCS23QUAD3PROT_set/clr ,Peripheral Protection 23 3" "Not protected,Protected" textline " " setclrfld.long 0x00 30. 0x00 30. 0x20 30. " PCS23QUAD2PROT_set/clr ,Peripheral Protection 23 2" "Not protected,Protected" textline " " setclrfld.long 0x00 29. 0x00 29. 0x20 29. " PCS23QUAD1PROT_set/clr ,Peripheral Protection 23 1" "Not protected,Protected" textline " " setclrfld.long 0x00 28. 0x00 28. 0x20 28. " PCS23QUAD0PROT_set/clr ,Peripheral Protection 23 0" "Not protected,Protected" textline " " setclrfld.long 0x00 27. 0x00 27. 0x20 27. " PCS22QUAD3PROT_set/clr ,Peripheral Protection 22 3" "Not protected,Protected" textline " " setclrfld.long 0x00 26. 0x00 26. 0x20 26. " PCS22QUAD2PROT_set/clr ,Peripheral Protection 22 2" "Not protected,Protected" textline " " setclrfld.long 0x00 25. 0x00 25. 0x20 25. " PCS22QUAD1PROT_set/clr ,Peripheral Protection 22 1" "Not protected,Protected" textline " " setclrfld.long 0x00 24. 0x00 24. 0x20 24. " PCS22QUAD0PROT_set/clr ,Peripheral Protection 22 0" "Not protected,Protected" textline " " setclrfld.long 0x00 23. 0x00 23. 0x20 23. " PCS21QUAD3PROT_set/clr ,Peripheral Protection 21 3" "Not protected,Protected" textline " " setclrfld.long 0x00 22. 0x00 22. 0x20 22. " PCS21QUAD2PROT_set/clr ,Peripheral Protection 21 2" "Not protected,Protected" textline " " setclrfld.long 0x00 21. 0x00 21. 0x20 21. " PCS21QUAD1PROT_set/clr ,Peripheral Protection 21 1" "Not protected,Protected" textline " " setclrfld.long 0x00 20. 0x00 20. 0x20 20. " PCS21QUAD0PROT_set/clr ,Peripheral Protection 21 0" "Not protected,Protected" textline " " setclrfld.long 0x00 19. 0x00 19. 0x20 19. " PCS20QUAD3PROT_set/clr ,Peripheral Protection 20 3" "Not protected,Protected" textline " " setclrfld.long 0x00 18. 0x00 18. 0x20 18. " PCS20QUAD2PROT_set/clr ,Peripheral Protection 20 2" "Not protected,Protected" textline " " setclrfld.long 0x00 17. 0x00 17. 0x20 17. " PCS20QUAD1PROT_set/clr ,Peripheral Protection 20 1" "Not protected,Protected" textline " " setclrfld.long 0x00 16. 0x00 16. 0x20 16. " PCS20QUAD0PROT_set/clr ,Peripheral Protection 20 0" "Not protected,Protected" textline " " setclrfld.long 0x00 15. 0x00 15. 0x20 15. " PCS19QUAD3PROT_set/clr ,Peripheral Protection 19 3" "Not protected,Protected" textline " " setclrfld.long 0x00 14. 0x00 14. 0x20 14. " PCS19QUAD2PROT_set/clr ,Peripheral Protection 19 2" "Not protected,Protected" textline " " setclrfld.long 0x00 13. 0x00 13. 0x20 13. " PCS19QUAD1PROT_set/clr ,Peripheral Protection 19 1" "Not protected,Protected" textline " " setclrfld.long 0x00 12. 0x00 12. 0x20 12. " PCS19QUAD0PROT_set/clr ,Peripheral Protection 19 0" "Not protected,Protected" textline " " setclrfld.long 0x00 11. 0x00 11. 0x20 11. " PCS18QUAD3PROT_set/clr ,Peripheral Protection 18 3" "Not protected,Protected" textline " " setclrfld.long 0x00 10. 0x00 10. 0x20 10. " PCS18QUAD2PROT_set/clr ,Peripheral Protection 18 2" "Not protected,Protected" textline " " setclrfld.long 0x00 9. 0x00 9. 0x20 9. " PCS18QUAD1PROT_set/clr ,Peripheral Protection 18 1" "Not protected,Protected" textline " " setclrfld.long 0x00 8. 0x00 8. 0x20 8. " PCS18QUAD0PROT_set/clr ,Peripheral Protection 18 0" "Not protected,Protected" textline " " setclrfld.long 0x00 7. 0x00 7. 0x20 7. " PCS17QUAD3PROT_set/clr ,Peripheral Protection 17 3" "Not protected,Protected" textline " " setclrfld.long 0x00 6. 0x00 6. 0x20 6. " PCS17QUAD2PROT_set/clr ,Peripheral Protection 17 2" "Not protected,Protected" textline " " setclrfld.long 0x00 5. 0x00 5. 0x20 5. " PCS17QUAD1PROT_set/clr ,Peripheral Protection 17 1" "Not protected,Protected" textline " " setclrfld.long 0x00 4. 0x00 4. 0x20 4. " PCS17QUAD0PROT_set/clr ,Peripheral Protection 17 0" "Not protected,Protected" textline " " setclrfld.long 0x00 3. 0x00 3. 0x20 3. " PCS16QUAD3PROT_set/clr ,Peripheral Protection 16 3" "Not protected,Protected" textline " " setclrfld.long 0x00 2. 0x00 2. 0x20 2. " PCS16QUAD2PROT_set/clr ,Peripheral Protection 16 2" "Not protected,Protected" textline " " setclrfld.long 0x00 1. 0x00 1. 0x20 1. " PCS16QUAD1PROT_set/clr ,Peripheral Protection 16 1" "Not protected,Protected" textline " " setclrfld.long 0x00 0. 0x00 0. 0x20 0. " PCS16QUAD0PROT_set/clr ,Peripheral Protection 16 0" "Not protected,Protected" group.long 0x2C++0x3 line.long 0x0 "PPROTSET3,Set-only Register to Protect the 32 Quadrants of PS24 to PS31" setclrfld.long 0x00 31. 0x00 31. 0x20 31. " PCS31QUAD3PROT_set/clr ,Peripheral Protection 31 3" "Not protected,Protected" textline " " setclrfld.long 0x00 30. 0x00 30. 0x20 30. " PCS31QUAD2PROT_set/clr ,Peripheral Protection 31 2" "Not protected,Protected" textline " " setclrfld.long 0x00 29. 0x00 29. 0x20 29. " PCS31QUAD1PROT_set/clr ,Peripheral Protection 31 1" "Not protected,Protected" textline " " setclrfld.long 0x00 28. 0x00 28. 0x20 28. " PCS31QUAD0PROT_set/clr ,Peripheral Protection 31 0" "Not protected,Protected" textline " " setclrfld.long 0x00 27. 0x00 27. 0x20 27. " PCS30QUAD3PROT_set/clr ,Peripheral Protection 30 3" "Not protected,Protected" textline " " setclrfld.long 0x00 26. 0x00 26. 0x20 26. " PCS30QUAD2PROT_set/clr ,Peripheral Protection 30 2" "Not protected,Protected" textline " " setclrfld.long 0x00 25. 0x00 25. 0x20 25. " PCS30QUAD1PROT_set/clr ,Peripheral Protection 30 1" "Not protected,Protected" textline " " setclrfld.long 0x00 24. 0x00 24. 0x20 24. " PCS30QUAD0PROT_set/clr ,Peripheral Protection 30 0" "Not protected,Protected" textline " " setclrfld.long 0x00 23. 0x00 23. 0x20 23. " PCS29QUAD3PROT_set/clr ,Peripheral Protection 29 3" "Not protected,Protected" textline " " setclrfld.long 0x00 22. 0x00 22. 0x20 22. " PCS29QUAD2PROT_set/clr ,Peripheral Protection 29 2" "Not protected,Protected" textline " " setclrfld.long 0x00 21. 0x00 21. 0x20 21. " PCS29QUAD1PROT_set/clr ,Peripheral Protection 29 1" "Not protected,Protected" textline " " setclrfld.long 0x00 20. 0x00 20. 0x20 20. " PCS29QUAD0PROT_set/clr ,Peripheral Protection 29 0" "Not protected,Protected" textline " " setclrfld.long 0x00 19. 0x00 19. 0x20 19. " PCS28QUAD3PROT_set/clr ,Peripheral Protection 28 3" "Not protected,Protected" textline " " setclrfld.long 0x00 18. 0x00 18. 0x20 18. " PCS28QUAD2PROT_set/clr ,Peripheral Protection 28 2" "Not protected,Protected" textline " " setclrfld.long 0x00 17. 0x00 17. 0x20 17. " PCS28QUAD1PROT_set/clr ,Peripheral Protection 28 1" "Not protected,Protected" textline " " setclrfld.long 0x00 16. 0x00 16. 0x20 16. " PCS28QUAD0PROT_set/clr ,Peripheral Protection 28 0" "Not protected,Protected" textline " " setclrfld.long 0x00 15. 0x00 15. 0x20 15. " PCS27QUAD3PROT_set/clr ,Peripheral Protection 27 3" "Not protected,Protected" textline " " setclrfld.long 0x00 14. 0x00 14. 0x20 14. " PCS27QUAD2PROT_set/clr ,Peripheral Protection 27 2" "Not protected,Protected" textline " " setclrfld.long 0x00 13. 0x00 13. 0x20 13. " PCS27QUAD1PROT_set/clr ,Peripheral Protection 27 1" "Not protected,Protected" textline " " setclrfld.long 0x00 12. 0x00 12. 0x20 12. " PCS27QUAD0PROT_set/clr ,Peripheral Protection 27 0" "Not protected,Protected" textline " " setclrfld.long 0x00 11. 0x00 11. 0x20 11. " PCS26QUAD3PROT_set/clr ,Peripheral Protection 26 3" "Not protected,Protected" textline " " setclrfld.long 0x00 10. 0x00 10. 0x20 10. " PCS26QUAD2PROT_set/clr ,Peripheral Protection 26 2" "Not protected,Protected" textline " " setclrfld.long 0x00 9. 0x00 9. 0x20 9. " PCS26QUAD1PROT_set/clr ,Peripheral Protection 26 1" "Not protected,Protected" textline " " setclrfld.long 0x00 8. 0x00 8. 0x20 8. " PCS26QUAD0PROT_set/clr ,Peripheral Protection 26 0" "Not protected,Protected" textline " " setclrfld.long 0x00 7. 0x00 7. 0x20 7. " PCS25QUAD3PROT_set/clr ,Peripheral Protection 25 3" "Not protected,Protected" textline " " setclrfld.long 0x00 6. 0x00 6. 0x20 6. " PCS25QUAD2PROT_set/clr ,Peripheral Protection 25 2" "Not protected,Protected" textline " " setclrfld.long 0x00 5. 0x00 5. 0x20 5. " PCS25QUAD1PROT_set/clr ,Peripheral Protection 25 1" "Not protected,Protected" textline " " setclrfld.long 0x00 4. 0x00 4. 0x20 4. " PCS25QUAD0PROT_set/clr ,Peripheral Protection 25 0" "Not protected,Protected" textline " " setclrfld.long 0x00 3. 0x00 3. 0x20 3. " PCS24QUAD3PROT_set/clr ,Peripheral Protection 24 3" "Not protected,Protected" textline " " setclrfld.long 0x00 2. 0x00 2. 0x20 2. " PCS24QUAD2PROT_set/clr ,Peripheral Protection 24 2" "Not protected,Protected" textline " " setclrfld.long 0x00 1. 0x00 1. 0x20 1. " PCS24QUAD1PROT_set/clr ,Peripheral Protection 24 1" "Not protected,Protected" textline " " setclrfld.long 0x00 0. 0x00 0. 0x20 0. " PCS24QUAD0PROT_set/clr ,Peripheral Protection 24 0" "Not protected,Protected" tree.end width 15. tree "PCR Power Down Registers" tree "PCR Memory Power Down Registers" group.long 0x60++0x3 line.long 0x0 "PCSPWRDWNSET0,Peripheral Memory Power-Down Set Register 0" setclrfld.long 0x00 31. 0x00 31. 0x10 31. " PCS31PWRDWN_set/clr ,Peripheral Memory Power Down Enable 31" "No power down,Power down" textline " " setclrfld.long 0x00 30. 0x00 30. 0x10 30. " PCS30PWRDWN_set/clr ,Peripheral Memory Power Down Enable 30" "No power down,Power down" textline " " setclrfld.long 0x00 29. 0x00 29. 0x10 29. " PCS29PWRDWN_set/clr ,Peripheral Memory Power Down Enable 29" "No power down,Power down" textline " " setclrfld.long 0x00 28. 0x00 28. 0x10 28. " PCS28PWRDWN_set/clr ,Peripheral Memory Power Down Enable 28" "No power down,Power down" textline " " setclrfld.long 0x00 27. 0x00 27. 0x10 27. " PCS27PWRDWN_set/clr ,Peripheral Memory Power Down Enable 27" "No power down,Power down" textline " " setclrfld.long 0x00 26. 0x00 26. 0x10 26. " PCS26PWRDWN_set/clr ,Peripheral Memory Power Down Enable 26" "No power down,Power down" textline " " setclrfld.long 0x00 25. 0x00 25. 0x10 25. " PCS25PWRDWN_set/clr ,Peripheral Memory Power Down Enable 25" "No power down,Power down" textline " " setclrfld.long 0x00 24. 0x00 24. 0x10 24. " PCS24PWRDWN_set/clr ,Peripheral Memory Power Down Enable 24" "No power down,Power down" textline " " setclrfld.long 0x00 23. 0x00 23. 0x10 23. " PCS23PWRDWN_set/clr ,Peripheral Memory Power Down Enable 23" "No power down,Power down" textline " " setclrfld.long 0x00 22. 0x00 22. 0x10 22. " PCS22PWRDWN_set/clr ,Peripheral Memory Power Down Enable 22" "No power down,Power down" textline " " setclrfld.long 0x00 21. 0x00 21. 0x10 21. " PCS21PWRDWN_set/clr ,Peripheral Memory Power Down Enable 21" "No power down,Power down" textline " " setclrfld.long 0x00 20. 0x00 20. 0x10 20. " PCS20PWRDWN_set/clr ,Peripheral Memory Power Down Enable 20" "No power down,Power down" textline " " setclrfld.long 0x00 19. 0x00 19. 0x10 19. " PCS19PWRDWN_set/clr ,Peripheral Memory Power Down Enable 19" "No power down,Power down" textline " " setclrfld.long 0x00 18. 0x00 18. 0x10 18. " PCS18PWRDWN_set/clr ,Peripheral Memory Power Down Enable 18" "No power down,Power down" textline " " setclrfld.long 0x00 17. 0x00 17. 0x10 17. " PCS17PWRDWN_set/clr ,Peripheral Memory Power Down Enable 17" "No power down,Power down" textline " " setclrfld.long 0x00 16. 0x00 16. 0x10 16. " PCS16PWRDWN_set/clr ,Peripheral Memory Power Down Enable 16" "No power down,Power down" textline " " setclrfld.long 0x00 15. 0x00 15. 0x10 15. " PCS15PWRDWN_set/clr ,Peripheral Memory Power Down Enable 15" "No power down,Power down" textline " " setclrfld.long 0x00 14. 0x00 14. 0x10 14. " PCS14PWRDWN_set/clr ,Peripheral Memory Power Down Enable 14" "No power down,Power down" textline " " setclrfld.long 0x00 13. 0x00 13. 0x10 13. " PCS13PWRDWN_set/clr ,Peripheral Memory Power Down Enable 13" "No power down,Power down" textline " " setclrfld.long 0x00 12. 0x00 12. 0x10 12. " PCS12PWRDWN_set/clr ,Peripheral Memory Power Down Enable 12" "No power down,Power down" textline " " setclrfld.long 0x00 11. 0x00 11. 0x10 11. " PCS11PWRDWN_set/clr ,Peripheral Memory Power Down Enable 11" "No power down,Power down" textline " " setclrfld.long 0x00 10. 0x00 10. 0x10 10. " PCS10PWRDWN_set/clr ,Peripheral Memory Power Down Enable 10" "No power down,Power down" textline " " setclrfld.long 0x00 9. 0x00 9. 0x10 9. " PCS9PWRDWN_set/clr ,Peripheral Memory Power Down Enable 9" "No power down,Power down" textline " " setclrfld.long 0x00 8. 0x00 8. 0x10 8. " PCS8PWRDWN_set/clr ,Peripheral Memory Power Down Enable 8" "No power down,Power down" textline " " setclrfld.long 0x00 7. 0x00 7. 0x10 7. " PCS7PWRDWN_set/clr ,Peripheral Memory Power Down Enable 7" "No power down,Power down" textline " " setclrfld.long 0x00 6. 0x00 6. 0x10 6. " PCS6PWRDWN_set/clr ,Peripheral Memory Power Down Enable 6" "No power down,Power down" textline " " setclrfld.long 0x00 5. 0x00 5. 0x10 5. " PCS5PWRDWN_set/clr ,Peripheral Memory Power Down Enable 5" "No power down,Power down" textline " " setclrfld.long 0x00 4. 0x00 4. 0x10 4. " PCS4PWRDWN_set/clr ,Peripheral Memory Power Down Enable 4" "No power down,Power down" textline " " setclrfld.long 0x00 3. 0x00 3. 0x10 3. " PCS3PWRDWN_set/clr ,Peripheral Memory Power Down Enable 3" "No power down,Power down" textline " " setclrfld.long 0x00 2. 0x00 2. 0x10 2. " PCS2PWRDWN_set/clr ,Peripheral Memory Power Down Enable 2" "No power down,Power down" textline " " setclrfld.long 0x00 1. 0x00 1. 0x10 1. " PCS1PWRDWN_set/clr ,Peripheral Memory Power Down Enable 1" "No power down,Power down" textline " " setclrfld.long 0x00 0. 0x00 0. 0x10 0. " PCS0PWRDWN_set/clr ,Peripheral Memory Power Down Enable 0" "No power down,Power down" group.long 0x64++0x3 line.long 0x0 "PCSPWRDWNSET1,Peripheral Memory Power-Down Set Register 1" setclrfld.long 0x00 31. 0x00 31. 0x10 31. " PCS63PWRDWN_set/clr ,Peripheral Memory Power Down Enable 63" "No power down,Power down" textline " " setclrfld.long 0x00 30. 0x00 30. 0x10 30. " PCS62PWRDWN_set/clr ,Peripheral Memory Power Down Enable 62" "No power down,Power down" textline " " setclrfld.long 0x00 29. 0x00 29. 0x10 29. " PCS61PWRDWN_set/clr ,Peripheral Memory Power Down Enable 61" "No power down,Power down" textline " " setclrfld.long 0x00 28. 0x00 28. 0x10 28. " PCS60PWRDWN_set/clr ,Peripheral Memory Power Down Enable 60" "No power down,Power down" textline " " setclrfld.long 0x00 27. 0x00 27. 0x10 27. " PCS59PWRDWN_set/clr ,Peripheral Memory Power Down Enable 59" "No power down,Power down" textline " " setclrfld.long 0x00 26. 0x00 26. 0x10 26. " PCS58PWRDWN_set/clr ,Peripheral Memory Power Down Enable 58" "No power down,Power down" textline " " setclrfld.long 0x00 25. 0x00 25. 0x10 25. " PCS57PWRDWN_set/clr ,Peripheral Memory Power Down Enable 57" "No power down,Power down" textline " " setclrfld.long 0x00 24. 0x00 24. 0x10 24. " PCS56PWRDWN_set/clr ,Peripheral Memory Power Down Enable 56" "No power down,Power down" textline " " setclrfld.long 0x00 23. 0x00 23. 0x10 23. " PCS55PWRDWN_set/clr ,Peripheral Memory Power Down Enable 55" "No power down,Power down" textline " " setclrfld.long 0x00 22. 0x00 22. 0x10 22. " PCS54PWRDWN_set/clr ,Peripheral Memory Power Down Enable 54" "No power down,Power down" textline " " setclrfld.long 0x00 21. 0x00 21. 0x10 21. " PC531PWRDWN_set/clr ,Peripheral Memory Power Down Enable 53" "No power down,Power down" textline " " setclrfld.long 0x00 20. 0x00 20. 0x10 20. " PCS52PWRDWN_set/clr ,Peripheral Memory Power Down Enable 52" "No power down,Power down" textline " " setclrfld.long 0x00 19. 0x00 19. 0x10 19. " PCS51PWRDWN_set/clr ,Peripheral Memory Power Down Enable 51" "No power down,Power down" textline " " setclrfld.long 0x00 18. 0x00 18. 0x10 18. " PCS50PWRDWN_set/clr ,Peripheral Memory Power Down Enable 50" "No power down,Power down" textline " " setclrfld.long 0x00 17. 0x00 17. 0x10 17. " PCS49PWRDWN_set/clr ,Peripheral Memory Power Down Enable 49" "No power down,Power down" textline " " setclrfld.long 0x00 16. 0x00 16. 0x10 16. " PCS48PWRDWN_set/clr ,Peripheral Memory Power Down Enable 48" "No power down,Power down" textline " " setclrfld.long 0x00 15. 0x00 15. 0x10 15. " PCS47PWRDWN_set/clr ,Peripheral Memory Power Down Enable 47" "No power down,Power down" textline " " setclrfld.long 0x00 14. 0x00 14. 0x10 14. " PCS46PWRDWN_set/clr ,Peripheral Memory Power Down Enable 46" "No power down,Power down" textline " " setclrfld.long 0x00 13. 0x00 13. 0x10 13. " PCS45PWRDWN_set/clr ,Peripheral Memory Power Down Enable 45" "No power down,Power down" textline " " setclrfld.long 0x00 12. 0x00 12. 0x10 12. " PCS44PWRDWN_set/clr ,Peripheral Memory Power Down Enable 44" "No power down,Power down" textline " " setclrfld.long 0x00 11. 0x00 11. 0x10 11. " PCS43PWRDWN_set/clr ,Peripheral Memory Power Down Enable 43" "No power down,Power down" textline " " setclrfld.long 0x00 10. 0x00 10. 0x10 10. " PCS42PWRDWN_set/clr ,Peripheral Memory Power Down Enable 42" "No power down,Power down" textline " " setclrfld.long 0x00 9. 0x00 9. 0x10 9. " PCS41PWRDWN_set/clr ,Peripheral Memory Power Down Enable 41" "No power down,Power down" textline " " setclrfld.long 0x00 8. 0x00 8. 0x10 8. " PCS40PWRDWN_set/clr ,Peripheral Memory Power Down Enable 40" "No power down,Power down" textline " " setclrfld.long 0x00 7. 0x00 7. 0x10 7. " PCS39PWRDWN_set/clr ,Peripheral Memory Power Down Enable 39" "No power down,Power down" textline " " setclrfld.long 0x00 6. 0x00 6. 0x10 6. " PCS38PWRDWN_set/clr ,Peripheral Memory Power Down Enable 38" "No power down,Power down" textline " " setclrfld.long 0x00 5. 0x00 5. 0x10 5. " PCS37PWRDWN_set/clr ,Peripheral Memory Power Down Enable 37" "No power down,Power down" textline " " setclrfld.long 0x00 4. 0x00 4. 0x10 4. " PCS36PWRDWN_set/clr ,Peripheral Memory Power Down Enable 36" "No power down,Power down" textline " " setclrfld.long 0x00 3. 0x00 3. 0x10 3. " PCS35PWRDWN_set/clr ,Peripheral Memory Power Down Enable 35" "No power down,Power down" textline " " setclrfld.long 0x00 2. 0x00 2. 0x10 2. " PCS34PWRDWN_set/clr ,Peripheral Memory Power Down Enable 34" "No power down,Power down" textline " " setclrfld.long 0x00 1. 0x00 1. 0x10 1. " PCS33PWRDWN_set/clr ,Peripheral Memory Power Down Enable 33" "No power down,Power down" textline " " setclrfld.long 0x00 0. 0x00 0. 0x10 0. " PCS32PWRDWN_set/clr ,Peripheral Memory Power Down Enable 32" "No power down,Power down" tree.end width 15. textline " " group.long 0x80++0x3 line.long 0x0 "PSPWRDWNSET0,Peripheral Power-Down Set Register 0" setclrfld.long 0x00 31. 0x00 31. 0x20 31. " PS7QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 7 3" "No power down,Power down" textline " " setclrfld.long 0x00 30. 0x00 30. 0x20 30. " PS7QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 7 2" "No power down,Power down" textline " " setclrfld.long 0x00 29. 0x00 29. 0x20 29. " PS7QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 7 1" "No power down,Power down" textline " " setclrfld.long 0x00 28. 0x00 28. 0x20 28. " PS7QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 7 0" "No power down,Power down" textline " " setclrfld.long 0x00 27. 0x00 27. 0x20 27. " PS6QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 6 3" "No power down,Power down" textline " " setclrfld.long 0x00 26. 0x00 26. 0x20 26. " PS6QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 6 2" "No power down,Power down" textline " " setclrfld.long 0x00 25. 0x00 25. 0x20 25. " PS6QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 6 1" "No power down,Power down" textline " " setclrfld.long 0x00 24. 0x00 24. 0x20 24. " PS6QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 6 0" "No power down,Power down" textline " " setclrfld.long 0x00 23. 0x00 23. 0x20 23. " PS5QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 5 3" "No power down,Power down" textline " " setclrfld.long 0x00 22. 0x00 22. 0x20 22. " PS5QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 5 2" "No power down,Power down" textline " " setclrfld.long 0x00 21. 0x00 21. 0x20 21. " PS5QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 5 1" "No power down,Power down" textline " " setclrfld.long 0x00 20. 0x00 20. 0x20 20. " PS5QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 5 0" "No power down,Power down" textline " " setclrfld.long 0x00 19. 0x00 19. 0x20 19. " PS4QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 4 3" "No power down,Power down" textline " " setclrfld.long 0x00 18. 0x00 18. 0x20 18. " PS4QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 4 2" "No power down,Power down" textline " " setclrfld.long 0x00 17. 0x00 17. 0x20 17. " PS4QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 4 1" "No power down,Power down" textline " " setclrfld.long 0x00 16. 0x00 16. 0x20 16. " PS4QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 4 0" "No power down,Power down" textline " " setclrfld.long 0x00 15. 0x00 15. 0x20 15. " PS3QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 3 3" "No power down,Power down" textline " " setclrfld.long 0x00 14. 0x00 14. 0x20 14. " PS3QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 3 2" "No power down,Power down" textline " " setclrfld.long 0x00 13. 0x00 13. 0x20 13. " PS3QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 3 1" "No power down,Power down" textline " " setclrfld.long 0x00 12. 0x00 12. 0x20 12. " PS3QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 3 0" "No power down,Power down" textline " " setclrfld.long 0x00 11. 0x00 11. 0x20 11. " PS2QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 2 3" "No power down,Power down" textline " " setclrfld.long 0x00 10. 0x00 10. 0x20 10. " PS2QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 2 2" "No power down,Power down" textline " " setclrfld.long 0x00 9. 0x00 9. 0x20 9. " PS2QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 2 1" "No power down,Power down" textline " " setclrfld.long 0x00 8. 0x00 8. 0x20 8. " PS2QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 2 0" "No power down,Power down" textline " " setclrfld.long 0x00 7. 0x00 7. 0x20 7. " PS1QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 1 3" "No power down,Power down" textline " " setclrfld.long 0x00 6. 0x00 6. 0x20 6. " PS1QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 1 2" "No power down,Power down" textline " " setclrfld.long 0x00 5. 0x00 5. 0x20 5. " PS1QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 1 1" "No power down,Power down" textline " " setclrfld.long 0x00 4. 0x00 4. 0x20 4. " PS1QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 1 0" "No power down,Power down" textline " " setclrfld.long 0x00 3. 0x00 3. 0x20 3. " PS0QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 0 3" "No power down,Power down" textline " " setclrfld.long 0x00 2. 0x00 2. 0x20 2. " PS0QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 0 2" "No power down,Power down" textline " " setclrfld.long 0x00 1. 0x00 1. 0x20 1. " PS0QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 0 1" "No power down,Power down" textline " " setclrfld.long 0x00 0. 0x00 0. 0x20 0. " PS0QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 0 0" "No power down,Power down" group.long 0x84++0x3 line.long 0x0 "PSPWRDWNSET1,Peripheral Power-Down Set Register 1" setclrfld.long 0x00 31. 0x00 31. 0x20 31. " PS15QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 15 3" "No power down,Power down" textline " " setclrfld.long 0x00 30. 0x00 30. 0x20 30. " PS15QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 15 2" "No power down,Power down" textline " " setclrfld.long 0x00 29. 0x00 29. 0x20 29. " PS15QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 15 1" "No power down,Power down" textline " " setclrfld.long 0x00 28. 0x00 28. 0x20 28. " PS15QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 15 0" "No power down,Power down" textline " " setclrfld.long 0x00 27. 0x00 27. 0x20 27. " PS14QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 14 3" "No power down,Power down" textline " " setclrfld.long 0x00 26. 0x00 26. 0x20 26. " PS14QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 14 2" "No power down,Power down" textline " " setclrfld.long 0x00 25. 0x00 25. 0x20 25. " PS14QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 14 1" "No power down,Power down" textline " " setclrfld.long 0x00 24. 0x00 24. 0x20 24. " PS14QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 14 0" "No power down,Power down" textline " " setclrfld.long 0x00 23. 0x00 23. 0x20 23. " PS13QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 13 3" "No power down,Power down" textline " " setclrfld.long 0x00 22. 0x00 22. 0x20 22. " PS13QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 13 2" "No power down,Power down" textline " " setclrfld.long 0x00 21. 0x00 21. 0x20 21. " PS13QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 13 1" "No power down,Power down" textline " " setclrfld.long 0x00 20. 0x00 20. 0x20 20. " PS13QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 13 0" "No power down,Power down" textline " " setclrfld.long 0x00 19. 0x00 19. 0x20 19. " PS12QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 12 3" "No power down,Power down" textline " " setclrfld.long 0x00 18. 0x00 18. 0x20 18. " PS12QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 12 2" "No power down,Power down" textline " " setclrfld.long 0x00 17. 0x00 17. 0x20 17. " PS12QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 12 1" "No power down,Power down" textline " " setclrfld.long 0x00 16. 0x00 16. 0x20 16. " PS12QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 12 0" "No power down,Power down" textline " " setclrfld.long 0x00 15. 0x00 15. 0x20 15. " PS11QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 11 3" "No power down,Power down" textline " " setclrfld.long 0x00 14. 0x00 14. 0x20 14. " PS11QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 11 2" "No power down,Power down" textline " " setclrfld.long 0x00 13. 0x00 13. 0x20 13. " PS11QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 11 1" "No power down,Power down" textline " " setclrfld.long 0x00 12. 0x00 12. 0x20 12. " PS11QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 11 0" "No power down,Power down" textline " " setclrfld.long 0x00 11. 0x00 11. 0x20 11. " PS10QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 10 3" "No power down,Power down" textline " " setclrfld.long 0x00 10. 0x00 10. 0x20 10. " PS10QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 10 2" "No power down,Power down" textline " " setclrfld.long 0x00 9. 0x00 9. 0x20 9. " PS10QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 10 1" "No power down,Power down" textline " " setclrfld.long 0x00 8. 0x00 8. 0x20 8. " PS10QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 10 0" "No power down,Power down" textline " " setclrfld.long 0x00 7. 0x00 7. 0x20 7. " PS9QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 9 3" "No power down,Power down" textline " " setclrfld.long 0x00 6. 0x00 6. 0x20 6. " PS9QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 9 2" "No power down,Power down" textline " " setclrfld.long 0x00 5. 0x00 5. 0x20 5. " PS9QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 9 1" "No power down,Power down" textline " " setclrfld.long 0x00 4. 0x00 4. 0x20 4. " PS9QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 9 0" "No power down,Power down" textline " " setclrfld.long 0x00 3. 0x00 3. 0x20 3. " PS8QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 8 3" "No power down,Power down" textline " " setclrfld.long 0x00 2. 0x00 2. 0x20 2. " PS8QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 8 2" "No power down,Power down" textline " " setclrfld.long 0x00 1. 0x00 1. 0x20 1. " PS8QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 8 1" "No power down,Power down" textline " " setclrfld.long 0x00 0. 0x00 0. 0x20 0. " PS8QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 8 0" "No power down,Power down" group.long 0x88++0x3 line.long 0x0 "PSPWRDWNSET2,Peripheral Power-Down Set Register 2" setclrfld.long 0x00 31. 0x00 31. 0x20 31. " PS23QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 23 3" "No power down,Power down" textline " " setclrfld.long 0x00 30. 0x00 30. 0x20 30. " PS23QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 23 2" "No power down,Power down" textline " " setclrfld.long 0x00 29. 0x00 29. 0x20 29. " PS23QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 23 1" "No power down,Power down" textline " " setclrfld.long 0x00 28. 0x00 28. 0x20 28. " PS23QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 23 0" "No power down,Power down" textline " " setclrfld.long 0x00 27. 0x00 27. 0x20 27. " PS22QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 22 3" "No power down,Power down" textline " " setclrfld.long 0x00 26. 0x00 26. 0x20 26. " PS22QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 22 2" "No power down,Power down" textline " " setclrfld.long 0x00 25. 0x00 25. 0x20 25. " PS22QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 22 1" "No power down,Power down" textline " " setclrfld.long 0x00 24. 0x00 24. 0x20 24. " PS22QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 22 0" "No power down,Power down" textline " " setclrfld.long 0x00 23. 0x00 23. 0x20 23. " PS21QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 21 3" "No power down,Power down" textline " " setclrfld.long 0x00 22. 0x00 22. 0x20 22. " PS21QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 21 2" "No power down,Power down" textline " " setclrfld.long 0x00 21. 0x00 21. 0x20 21. " PS21QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 21 1" "No power down,Power down" textline " " setclrfld.long 0x00 20. 0x00 20. 0x20 20. " PS21QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 21 0" "No power down,Power down" textline " " setclrfld.long 0x00 19. 0x00 19. 0x20 19. " PS20QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 20 3" "No power down,Power down" textline " " setclrfld.long 0x00 18. 0x00 18. 0x20 18. " PS20QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 20 2" "No power down,Power down" textline " " setclrfld.long 0x00 17. 0x00 17. 0x20 17. " PS20QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 20 1" "No power down,Power down" textline " " setclrfld.long 0x00 16. 0x00 16. 0x20 16. " PS20QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 20 0" "No power down,Power down" textline " " setclrfld.long 0x00 15. 0x00 15. 0x20 15. " PS19QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 19 3" "No power down,Power down" textline " " setclrfld.long 0x00 14. 0x00 14. 0x20 14. " PS19QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 19 2" "No power down,Power down" textline " " setclrfld.long 0x00 13. 0x00 13. 0x20 13. " PS19QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 19 1" "No power down,Power down" textline " " setclrfld.long 0x00 12. 0x00 12. 0x20 12. " PS19QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 19 0" "No power down,Power down" textline " " setclrfld.long 0x00 11. 0x00 11. 0x20 11. " PS18QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 18 3" "No power down,Power down" textline " " setclrfld.long 0x00 10. 0x00 10. 0x20 10. " PS18QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 18 2" "No power down,Power down" textline " " setclrfld.long 0x00 9. 0x00 9. 0x20 9. " PS18QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 18 1" "No power down,Power down" textline " " setclrfld.long 0x00 8. 0x00 8. 0x20 8. " PS18QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 18 0" "No power down,Power down" textline " " setclrfld.long 0x00 7. 0x00 7. 0x20 7. " PS17QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 17 3" "No power down,Power down" textline " " setclrfld.long 0x00 6. 0x00 6. 0x20 6. " PS17QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 17 2" "No power down,Power down" textline " " setclrfld.long 0x00 5. 0x00 5. 0x20 5. " PS17QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 17 1" "No power down,Power down" textline " " setclrfld.long 0x00 4. 0x00 4. 0x20 4. " PS17QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 17 0" "No power down,Power down" textline " " setclrfld.long 0x00 3. 0x00 3. 0x20 3. " PS16QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 16 3" "No power down,Power down" textline " " setclrfld.long 0x00 2. 0x00 2. 0x20 2. " PS16QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 16 2" "No power down,Power down" textline " " setclrfld.long 0x00 1. 0x00 1. 0x20 1. " PS16QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 16 1" "No power down,Power down" textline " " setclrfld.long 0x00 0. 0x00 0. 0x20 0. " PS16QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 16 0" "No power down,Power down" group.long 0x8C++0x3 line.long 0x0 "PSPWRDWNSET3,Peripheral Power-Down Set Register 3" setclrfld.long 0x00 31. 0x00 31. 0x20 31. " PS31QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 31 3" "No power down,Power down" textline " " setclrfld.long 0x00 30. 0x00 30. 0x20 30. " PS31QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 31 2" "No power down,Power down" textline " " setclrfld.long 0x00 29. 0x00 29. 0x20 29. " PS31QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 31 1" "No power down,Power down" textline " " setclrfld.long 0x00 28. 0x00 28. 0x20 28. " PS31QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 31 0" "No power down,Power down" textline " " setclrfld.long 0x00 27. 0x00 27. 0x20 27. " PS30QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 30 3" "No power down,Power down" textline " " setclrfld.long 0x00 26. 0x00 26. 0x20 26. " PS30QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 30 2" "No power down,Power down" textline " " setclrfld.long 0x00 25. 0x00 25. 0x20 25. " PS30QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 30 1" "No power down,Power down" textline " " setclrfld.long 0x00 24. 0x00 24. 0x20 24. " PS30QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 30 0" "No power down,Power down" textline " " setclrfld.long 0x00 23. 0x00 23. 0x20 23. " PS29QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 29 3" "No power down,Power down" textline " " setclrfld.long 0x00 22. 0x00 22. 0x20 22. " PS29QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 29 2" "No power down,Power down" textline " " setclrfld.long 0x00 21. 0x00 21. 0x20 21. " PS29QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 29 1" "No power down,Power down" textline " " setclrfld.long 0x00 20. 0x00 20. 0x20 20. " PS29QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 29 0" "No power down,Power down" textline " " setclrfld.long 0x00 19. 0x00 19. 0x20 19. " PS28QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 28 3" "No power down,Power down" textline " " setclrfld.long 0x00 18. 0x00 18. 0x20 18. " PS28QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 28 2" "No power down,Power down" textline " " setclrfld.long 0x00 17. 0x00 17. 0x20 17. " PS28QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 28 1" "No power down,Power down" textline " " setclrfld.long 0x00 16. 0x00 16. 0x20 16. " PS28QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 28 0" "No power down,Power down" textline " " setclrfld.long 0x00 15. 0x00 15. 0x20 15. " PS27QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 27 3" "No power down,Power down" textline " " setclrfld.long 0x00 14. 0x00 14. 0x20 14. " PS27QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 27 2" "No power down,Power down" textline " " setclrfld.long 0x00 13. 0x00 13. 0x20 13. " PS27QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 27 1" "No power down,Power down" textline " " setclrfld.long 0x00 12. 0x00 12. 0x20 12. " PS27QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 27 0" "No power down,Power down" textline " " setclrfld.long 0x00 11. 0x00 11. 0x20 11. " PS26QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 26 3" "No power down,Power down" textline " " setclrfld.long 0x00 10. 0x00 10. 0x20 10. " PS26QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 26 2" "No power down,Power down" textline " " setclrfld.long 0x00 9. 0x00 9. 0x20 9. " PS26QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 26 1" "No power down,Power down" textline " " setclrfld.long 0x00 8. 0x00 8. 0x20 8. " PS26QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 26 0" "No power down,Power down" textline " " setclrfld.long 0x00 7. 0x00 7. 0x20 7. " PS25QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 25 3" "No power down,Power down" textline " " setclrfld.long 0x00 6. 0x00 6. 0x20 6. " PS25QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 25 2" "No power down,Power down" textline " " setclrfld.long 0x00 5. 0x00 5. 0x20 5. " PS25QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 25 1" "No power down,Power down" textline " " setclrfld.long 0x00 4. 0x00 4. 0x20 4. " PS25QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 25 0" "No power down,Power down" textline " " setclrfld.long 0x00 3. 0x00 3. 0x20 3. " PS24QUAD3PWRDWN_set/clr ,Peripheral Power Down Enable 24 3" "No power down,Power down" textline " " setclrfld.long 0x00 2. 0x00 2. 0x20 2. " PS24QUAD2PWRDWN_set/clr ,Peripheral Power Down Enable 24 2" "No power down,Power down" textline " " setclrfld.long 0x00 1. 0x00 1. 0x20 1. " PS24QUAD1PWRDWN_set/clr ,Peripheral Power Down Enable 24 1" "No power down,Power down" textline " " setclrfld.long 0x00 0. 0x00 0. 0x20 0. " PS24QUAD0PWRDWN_set/clr ,Peripheral Power Down Enable 24 0" "No power down,Power down" tree.end width 0xb tree.end tree.end sif (cpu()!="RM42L432") tree "PMM (Power Management Module)" base ad:0xFFFF0000 width 17. group.long 0x0++0x3 line.long 0x0 "LOGICPDPWRCTRL0,Logic Power Domain Control Register 0" bitfld.long 0x00 24.--27. " LOGICPDON0 ,Power domain PD2 state" "Active,Active,Active,Active,Active,Active,Active,Active,Active,Reserved,Off,Active,Active,Active,Active,Active" bitfld.long 0x00 16.--19. " LOGICPDON1 ,Power domain PD3 state" "Active,Active,Active,Active,Active,Active,Active,Active,Active,Reserved,Off,Active,Active,Active,Active,Active" textline " " bitfld.long 0x00 8.--11. " LOGICPDON2 ,Power domain PD4 state" "Active,Active,Active,Active,Active,Active,Active,Active,Active,Reserved,Off,Active,Active,Active,Active,Active" bitfld.long 0x00 0.--3. " LOGICPDON3 ,Power domain PD5 state" "Active,Active,Active,Active,Active,Active,Active,Active,Active,Reserved,Off,Active,Active,Active,Active,Active" group.long 0x10++0x3 line.long 0x0 "MEMPDPWRCTRL0,Memory Power Domain Control Register 0" bitfld.long 0x00 24.--27. " MEMPDON0 ,Power domain RAM_PD1 state" "Active,Active,Active,Active,Active,Active,Active,Active,Active,Reserved,Off,Active,Active,Active,Active,Active" bitfld.long 0x00 16.--19. " MEMPDON1 ,Power domain RAM_PD2 state" "Active,Active,Active,Active,Active,Active,Active,Active,Active,Reserved,Off,Active,Active,Active,Active,Active" sif (!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")) textline " " bitfld.long 0x00 8.--11. " MEMPDON2 ,Power domain RAM_PD3 state" "Active,Active,Active,Active,Active,Active,Active,Active,Active,Reserved,Off,Active,Active,Active,Active,Active" endif group.long 0x20++0x3 line.long 0x0 "PDCLKDIS,Power Domain Clock Disable Register SET/CLR" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " PDCLK_DIS[3]_set/clr ,Clocks to logic power domain PD5 disable" "No,Yes" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " PDCLK_DIS[2]_set/clr ,Clocks to logic power domain PD4 disable" "No,Yes" textline " " setclrfld.long 0x00 1. 0x04 1. 0x08 1. " PDCLK_DIS[1]_set/clr ,Clocks to logic power domain PD3 disable" "No,Yes" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PDCLK_DIS[0]_set/clr ,Clocks to logic power domain PD2 disable" "No,Yes" rgroup.long 0x40++0xf line.long 0x0 "LOGICPDPWRSTAT0,Logic power domain status 0" bitfld.long 0x0 24. " LOGIC_IN_TRANS0 ,Logic in transition status for power domain PD2" "Active/Off,Power-down/Up" bitfld.long 0x0 16. " MEM_IN_TRANS0 ,Memory in transition status for power domain PD2" "Active/Off,Power-down/Up" textline " " bitfld.long 0x0 8. " DOMAIN_ON0 ,Current state of power domain PD2" "Off,Active" bitfld.long 0x0 0.--1. " LOGICPDPWR_STAT0 ,Logic power domain PD2 power state" "Off,Idle,Reserved,Active" line.long 0x4 "LOGICPDPWRSTAT1,Logic power domain status 1" bitfld.long 0x4 24. " LOGIC_IN_TRANS1 ,Logic in transition status for power domain PD3" "Active/Off,Power-down/Up" bitfld.long 0x4 16. " MEM_IN_TRANS1 ,Memory in transition status for power domain PD3" "Active/Off,Power-down/Up" textline " " bitfld.long 0x4 8. " DOMAIN_ON1 ,Current state of power domain PD3" "Off,Active" bitfld.long 0x4 0.--1. " LOGICPDPWR_STAT1 ,Logic power domain PD3 power state" "Off,Idle,Reserved,Active" line.long 0x8 "LOGICPDPWRSTAT2,Logic power domain status 2" bitfld.long 0x8 24. " LOGIC_IN_TRANS2 ,Logic in transition status for power domain PD4" "Active/Off,Power-down/Up" bitfld.long 0x8 16. " MEM_IN_TRANS2 ,Memory in transition status for power domain PD4" "Active/Off,Power-down/Up" textline " " bitfld.long 0x8 8. " DOMAIN_ON2 ,Current state of power domain PD4" "Off,Active" bitfld.long 0x8 0.--1. " LOGICPDPWR_STAT2 ,Logic power domain PD4 power state" "Off,Idle,Reserved,Active" line.long 0xC "LOGICPDPWRSTAT3,Logic power domain status 3" bitfld.long 0xC 24. " LOGIC_IN_TRANS3 ,Logic in transition status for power domain PD5" "Active/Off,Power-down/Up" bitfld.long 0xC 16. " MEM_IN_TRANS3 ,Memory in transition status for power domain PD5" "Active/Off,Power-down/Up" textline " " bitfld.long 0xC 8. " DOMAIN_ON3 ,Current state of power domain PD5" "Off,Active" bitfld.long 0xC 0.--1. " LOGICPDPWR_STAT3 ,Logic power domain PD5 power state" "Off,Idle,Reserved,Active" sif (cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE"||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")) rgroup.long 0x80++0x7 line.long 0x0 "MEMPDPWRSTAT0,Memory Power Domain Status 0" bitfld.long 0x0 24. " LOGIC_IN_TRANS0 ,Logic in transition status for power domain RAM_PD1" "Active/Off,Power-down/up" bitfld.long 0x0 16. " MEM_IN_TRANS0 ,Memory in transition status for power domain RAM_PD1" "Active/Off,Power-down/up" textline " " bitfld.long 0x0 8. " DOMAIN_ON0 ,Current state of power domain RAM_PD1" "Off,Active" bitfld.long 0x0 0.--1. " MEMPDPWRSTAT0 ,Memory power domain RAM_PD1 power state" "Off,Idle,Reserved,Active" line.long 0x4 "MEMPDPWRSTAT1,Memory Power Domain Status 1" bitfld.long 0x4 24. " LOGIC_IN_TRANS1 ,Logic in transition status for power domain RAM_PD2" "Active/Off,Power-down/up" bitfld.long 0x4 16. " MEM_IN_TRANS1 ,Memory in transition status for power domain RAM_PD2" "Active/Off,Power-down/up" textline " " bitfld.long 0x4 8. " DOMAIN_ON1 ,Current state of power domain RAM_PD2" "Off,Active" bitfld.long 0x4 0.--1. " MEMPDPWRSTAT1 ,Memory power domain RAM_PD2 power state" "Off,Idle,Reserved,Active" else rgroup.long 0x80++0xb line.long 0x0 "MEMPDPWRSTAT0,Memory Power Domain Status 0" bitfld.long 0x0 24. " LOGIC_IN_TRANS0 ,Logic in transition status for power domain RAM_PD1" "Active/Off,Power-down/up" bitfld.long 0x0 16. " MEM_IN_TRANS0 ,Memory in transition status for power domain RAM_PD1" "Active/Off,Power-down/up" textline " " bitfld.long 0x0 8. " DOMAIN_ON0 ,Current state of power domain RAM_PD1" "Off,Active" bitfld.long 0x0 0.--1. " MEMPDPWRSTAT0 ,Memory power domain RAM_PD1 power state" "Off,Idle,Reserved,Active" line.long 0x4 "MEMPDPWRSTAT1,Memory Power Domain Status 1" bitfld.long 0x4 24. " LOGIC_IN_TRANS1 ,Logic in transition status for power domain RAM_PD2" "Active/Off,Power-down/up" bitfld.long 0x4 16. " MEM_IN_TRANS1 ,Memory in transition status for power domain RAM_PD2" "Active/Off,Power-down/up" textline " " bitfld.long 0x4 8. " DOMAIN_ON1 ,Current state of power domain RAM_PD2" "Off,Active" bitfld.long 0x4 0.--1. " MEMPDPWRSTAT1 ,Memory power domain RAM_PD2 power state" "Off,Idle,Reserved,Active" line.long 0x8 "MEMPDPWRSTAT2,Memory Power Domain Status 2" bitfld.long 0x8 24. " LOGIC_IN_TRANS2 ,Logic in transition status for power domain RAM_PD3" "Active/Off,Power-down/up" bitfld.long 0x8 16. " MEM_IN_TRANS2 ,Memory in transition status for power domain RAM_PD3" "Active/Off,Power-down/up" textline " " bitfld.long 0x8 8. " DOMAIN_ON2 ,Current state of power domain RAM_PD3" "Off,Active" bitfld.long 0x8 0.--1. " MEMPDPWRSTAT2 ,Memory power domain RAM_PD3 power state" "Off,Idle,Reserved,Active" endif group.long 0xA0++0x3 line.long 0x0 "GLOBALCTRL1,Global Control Register1" bitfld.long 0x00 8. " PMCTRL_PWRDN ,PMC/PSCON Power Down bit" "Not powered down,Powered down" bitfld.long 0x00 0. " AUTO_CLK_WAKE_ENA ,Automatic Clock Enable on Wake Up" "Disabled,Enabled" rgroup.long 0xA8++0x3 line.long 0x0 "GLOBALSTAT,Global Status Register" bitfld.long 0x00 0. " PMCTRL_IDLE ,State of PMC and all PSCONs" "Busy,Idle" group.long 0xAC++0x3 line.long 0x0 "PRCKEYREG,PSCON Diagnostic Compare Key Register" bitfld.long 0x00 0.--3. " MKEY ,Diagnostic PSCON Mode Key" "Lock Step,Lock Step,Lock Step,Lock Step,Lock Step,Lock Step,Self Test,Lock Step,Lock Step,Error Forcing,Lock Step,Lock Step,Lock Step,Lock Step,Lock Step,Self Test Error Forcing" group.long 0xB0++0x3 line.long 0x0 "LPDDCSTAT1,Logic PD PSCON diagnostic compare status register 1" eventfld.long 0x00 19. " LCMPE3 ,Logic Power Domain Compare Error for PD5" "No error,Error" eventfld.long 0x00 18. " LCMPE2 ,Logic Power Domain Compare Error for PD4" "No error,Error" textline " " eventfld.long 0x00 17. " LCMPE1 ,Logic Power Domain Compare Error for PD3" "No error,Error" eventfld.long 0x00 16. " LCMPE0 ,Logic Power Domain Compare Error for PD2" "No error,Error" textline " " bitfld.long 0x00 3. " LSTC3 ,Logic Power Domain Self Test Complete for PD5" "Not completed,Completed" bitfld.long 0x00 2. " LSTC2 ,Logic Power Domain Self Test Complete for PD4" "Not completed,Completed" textline " " bitfld.long 0x00 1. " LSTC1 ,Logic Power Domain Self Test Complete for PD3" "Not completed,Completed" bitfld.long 0x00 0. " LSTC0 ,Logic Power Domain Self Test Complete for PD2" "Not completed,Completed" rgroup.long 0xB4++0x3 line.long 0x0 "LPDDCSTAT2,Logic PD PSCON diagnostic compare status register 2" bitfld.long 0x00 19. " LSTET3 ,Logic Power Domain Self Test Error Type for PD5" "During match test,During mismatch test" bitfld.long 0x00 18. " LSTET2 ,Logic Power Domain Self Test Error Type for PD4" "During match test,During mismatch test" textline " " bitfld.long 0x00 17. " LSTET1 ,Logic Power Domain Self Test Error Type for PD3" "During match test,During mismatch test" bitfld.long 0x00 16. " LSTET0 ,Logic Power Domain Self Test Error Type for PD2" "During match test,During mismatch test" textline " " bitfld.long 0x00 3. " LSTE3 ,Logic Power Domain Self Test Error for PD5" "Passed,Failed" bitfld.long 0x00 2. " LSTE2 ,Logic Power Domain Self Test Error for PD4" "Passed,Failed" textline " " bitfld.long 0x00 1. " LSTE1 ,Logic Power Domain Self Test Error for PD3" "Passed,Failed" bitfld.long 0x00 0. " LSTE0 ,Logic Power Domain Self Test Error for PD2" "Passed,Failed" group.long 0xB8++0x3 line.long 0x0 "MPDDCSTAT1,Memory PD PSCON Diagnostic Compare Status Register1" sif (cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")) bitfld.long 0x00 18. " MCMPE2 ,Memory Power Domain Compare Error for RAM_PD3" "No error,Error" textline " " endif bitfld.long 0x00 17. " MCMPE1 ,Memory Power Domain Compare Error for RAM_PD2" "No error,Error" textline " " bitfld.long 0x00 16. " MCMPE0 ,Memory Power Domain Compare Error for RAM_PD1" "No error,Error" sif (cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")) textline " " bitfld.long 0x00 2. " MSTC2 ,Memory Power Domain Self Test Complete for RAM_PD3" "Not completed,Completed" endif textline " " bitfld.long 0x00 1. " MSTC1 ,Memory Power Domain Self Test Complete for RAM_PD2" "Not completed,Completed" textline " " bitfld.long 0x00 0. " MSTC0 ,Memory Power Domain Self Test Complete for RAM_PD1" "Not completed,Completed" group.long 0xBC++0x3 line.long 0x0 "MPDDCSTAT2,Memory PD PSCON Diagnostic Compare Status Register2" sif (cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")) bitfld.long 0x00 18. " MSTET2 ,Memory Power Domain Self Test Error Type for RAM_PD3" "During match test,During mismatch test" textline " " endif bitfld.long 0x00 17. " MSTET1 ,Memory Power Domain Self Test Error Type for RAM_PD2" "During match test,During mismatch test" textline " " bitfld.long 0x00 16. " MSTET0 ,Memory Power Domain Self Test Error Type for RAM_PD1" "During match test,During mismatch test" textline " " sif (cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")) bitfld.long 0x00 2. " MSTE2 ,Memory Power Domain Self Test Error for RAM_PD3" "No error,Error" textline " " endif bitfld.long 0x00 1. " MSTE1 ,Memory Power Domain Self Test Error for RAM_PD2" "No error,Error" textline " " bitfld.long 0x00 0. " MSTE0 ,Memory Power Domain Self Test Error for RAM_PD1" "No error,Error" rgroup.long 0xC0++0x3 line.long 0x0 "ISODIAGSTAT,Isolation Diagnostic Status Register" bitfld.long 0x00 3. " ISO_DIAG3 ,Isolation Diagnostic for PD5" "Enabled,Disabled" bitfld.long 0x00 2. " ISO_DIAG2 ,Isolation Diagnostic for PD4" "Enabled,Disabled" textline " " bitfld.long 0x00 1. " ISO_DIAG1 ,Isolation Diagnostic for PD3" "Enabled,Disabled" bitfld.long 0x00 0. " ISO_DIAG0 ,Isolation Diagnostic for PD2" "Enabled,Disabled" width 11. tree.end endif sif cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE" tree "IOMM (I/O Multiplexing and Control Module)" base ad:0xFFFFEA00 width 24. rgroup.long 0x0++0x3 line.long 0x0 "REVISION_REG,Module Revision Register" bitfld.long 0x00 30.--31. " REV_SCHEME ,Revision Scheme" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " REV_MODULE ,Module Id" textline " " bitfld.long 0x00 11.--15. " REV_RTL ,RTL Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. " REV_MAJOR ,Major Revision" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 6.--7. " REV_CUSTOM ,Custom Revision" "0,1,2,3" bitfld.long 0x00 0.--5. " REV_MINOR ,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x20++0x3 line.long 0x0 "BOOT_REG,Boot Config Register 0" bitfld.long 0x00 0. " ENDIAN ,Device endianness" "Little endian,Big endian" group.long 0x38++0x3 line.long 0x0 "KICK_REG0,Kicker Register 0" group.long 0x3C++0x3 line.long 0x0 "KICK_REG1,Kicker Register 1" group.long 0xE0++0x3 line.long 0x0 "ERR_RAW_STATUS_REG,Error Raw Status/Set Register" bitfld.long 0x00 1. " ADDR_ERR ,Addressing Error Status and Error Signaling Enable" "No error,Error" bitfld.long 0x00 0. " PROT_ERR ,Protection Error Status and Error Signaling Enable" "No error,Error" group.long 0xE4++0x3 line.long 0x0 "ERR_ENABLED_STATUS_REG,Error Enabled Status/Clear Register" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " ADDR_ERR_set/clr ,Addressing Error Signaling Enable Status and Status Clear" "Disabled,Enabled" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PROT_ERR_set/clr ,Protection Error Signaling Enable Status and Status Clear" "Disabled,Enabled" group.long 0xF4++0x3 line.long 0x0 "FAULT_ADDRESS_REG,Fault Address Register" rgroup.long 0xF8++0x3 line.long 0x0 "FAULT_STATUS_REG,Fault Status Register" bitfld.long 0x00 24.--27. " FAULT_ID ,Faulting Transaction ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--23. 1. " FAULT_MSTID ,Id of Master that initiated the faulting transaction" textline " " bitfld.long 0x00 9.--12. " FAULT_PRIVID ,Faulting Privilege Id" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " FAULT_NS ,Fault: Non-secure access detected" "Not detected,Detected" textline " " bitfld.long 0x00 0.--5. " FAULT_TYPE ,Type of fault detected" "No fault,User execute fault,User write fault,Reserved,User read fault,Reserved,Reserved,Reserved,Supervisor execute fault,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supervisor write fault,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supervisor read fault,?..." group.long 0xFC++0x3 line.long 0x0 "FAULT_CLEAR_REG,Fault Clear Register" bitfld.long 0x00 0. " FAULT_CLEAR ,Fault Clear" "Not cleared,Cleared" width 10. tree "Output Multiplexing and Control Registers" group.long 0x110++0x3B line.long 0x00 "PINMMR0,Pin Multiplexing Control Register 0" bitfld.long 0x00 27. " NTZ2 ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x00 26. " N2HET1[27] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x00 25. " I2C_SDA ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x00 24. " MIBSPI3NCS[2] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x00 19. " NTZ1 ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x00 18. " N2HET1[29] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x00 17. " I2C_SCL ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x00 16. " MIBSPI3NCS[3] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x00 10. " USB_FUNC_RXDPI ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x00 9. " USB2_VP ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x00 8. " GIOA[0] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x00 2. " USB_FUNC_RXDI ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x00 1. " USB2_RCV ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x00 0. " GIOB[3] ,Control the functionality on a given ball/pin" "0,1" line.long 0x04 "PINMMR1,Pin Multiplexing Control Register 1" bitfld.long 0x04 13. " ETPWM1SYNCO ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x04 12. " USB_FUNC_VBUSI ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x04 11. " USB2_OVER_CURRENT ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x04 10. " N2HET2[18] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x04 9. " MIBSPI3NCS[4] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x04 8. " N2HET1[11] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x04 2. " USB_FUNC_RXDMI ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x04 1. " USB2_VM ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x04 0. " GIOA[1] ,Control the functionality on a given ball/pin" "0,1" line.long 0x08 "PINMMR2,Pin Multiplexing Control Register 2" bitfld.long 0x08 26. " ETPWM1A ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x08 25. " EXTCLKIN ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x08 24. " GIOA[5] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x08 17. " N2HET2[2] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x08 16. " GIOA[3] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x08 4. " EQEP2I ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x08 3. " N2HET2[0] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x08 2. " USB_FUNC_TXDO ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x08 1. " USB2_TXDAT ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x08 0. " GIOA[2] ,Control the functionality on a given ball/pin" "0,1" line.long 0x0C "PINMMR3,Pin Multiplexing Control Register 3" bitfld.long 0x0C 18. " ETPWM1B ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x0C 17. " N2HET2[4] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x0C 16. " GIOA[6] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x0C 10. " USB_FUNC_SE0O ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x0C 9. " USB2_TXSE0 ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x0C 8. " N2HET1[22] ,Control the functionality on a given ball/pin" "0,1" line.long 0x10 "PINMMR4,Pin Multiplexing Control Register 4" bitfld.long 0x10 29. " EQEP2B ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x10 28. " N2HET2[10] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x10 27. " USB_FUNC_PUENON ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x10 26. " USB2_SPEED ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x10 25. " SPI4NCS[0] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x10 24. " N2HET1[03] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x10 21. " EQEP2A ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x10 20. " N2HET2[8] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x10 19. " USB_FUNC_PUENO ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x10 18. " USB2_TXEN ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x10 17. " SPI4NENA ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x10 16. " N2HET1[01] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x10 2. " ETPWM2A ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x10 1. " N2HET2[6] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x10 0. " GIOA[7] ,Control the functionality on a given ball/pin" "0,1" line.long 0x14 "PINMMR5,Pin Multiplexing Control Register 5" bitfld.long 0x14 19. " ETPWM3B ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x14 18. " N2HET2[12] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x14 17. " SPI4SOMI ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x14 16. " N2HET1[05] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x14 10. " ETPWM3A ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x14 9. " SPI4SIMO ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x14 8. " N2HET1[02] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x14 2. " ETPWM2B ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x14 1. " SPI4CLK ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x14 0. " N2HET1[0] ,Control the functionality on a given ball/pin" "0,1" line.long 0x18 "PINMMR6,Pin Multiplexing Control Register 6" bitfld.long 0x18 20. " ETPWM7A ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x18 19. " USB_FUNC_SUSPENDO ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x18 18. " USB2_SUSPEND ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x18 17. " N2HET1[09] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x18 16. " N2HET1[09] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x18 9. " EMIF_DATA[11] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x18 8. " EMIF_DATA[11] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x18 4. " ETPWM7B ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x18 3. " N2HET2[14] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x18 2. " USB_FUNC_GZO ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x18 1. " USB2_PORTPOWER ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x18 0. " N2HET1[07] ,Control the functionality on a given ball/pin" "0,1" line.long 0x1C "PINMMR7,Pin Multiplexing Control Register 7" bitfld.long 0x1C 17. " SCIRX ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x1C 16. " N2HET1[06] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x1C 10. " MDCLK ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x1C 9. " N2HET1[25] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x1C 8. " MIBSPI3NCS[1] ,Control the functionality on a given ball/pin" "0,1" line.long 0x20 "PINMMR8,Pin Multiplexing Control Register 8" bitfld.long 0x20 18. " ECAP1 ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x20 17. " MIBSPI1NCS[4] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x20 16. " N2HET1[15] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x20 10. " MDIO ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x20 9. " N2HET1[19] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x20 8. " MIBSPI1NCS[2] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x20 2. " MDCLK ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x20 1. " N2HET1[25] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x20 0. " MIBSPI3NCS[1] ,Control the functionality on a given ball/pin" "0,1" line.long 0x24 "PINMMR9,Pin Multiplexing Control Register 9" bitfld.long 0x24 25. " N2HET1[21] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x24 24. " MIBSPI1NCS[3] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x24 19. " EQEP1I ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x24 17. " AD2EVT ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x24 16. " MIBSPI3NCS[0] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x24 11. " EQEP1B ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x24 10. " N2HET1[31] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x24 9. " MIBSPI3NCS[5] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x24 8. " MIBSPI3NENA ,Control the functionality on a given ball/pin" "0,1" line.long 0x28 "PINMMR10,Pin Multiplexing Control Register 10" bitfld.long 0x28 18. " N2HET2[7] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x28 16. " EMIF_NCS[0] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x28 2. " RMII_RX_ER ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x28 1. " MII_RX_ER ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x28 0. " AD1EVT ,Control the functionality on a given ball/pin" "0,1" line.long 0x2C "PINMMR11,Pin Multiplexing Control Register 11" bitfld.long 0x2C 27. " RMII_RXD[0] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x2C 26. " MII_RXD[0] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x2C 25. " MIBSPI1NCS[5] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x2C 24. " EMIF_NCS[3] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x2C 2. " N2HET2[9] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x2C 0. " EMIF_NCS[3] ,Control the functionality on a given ball/pin" "0,1" line.long 0x30 "PINMMR12,Pin Multiplexing Control Register 12" bitfld.long 0x30 29. " ECAP5 ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x30 28. " MIBSPI5SOMI[1] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x30 27. " USB1_VM ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x30 26. " MII_RXD[3] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x30 24. " MIBSPI5NENA ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x30 20. " ECAP4 ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x30 19. " USB1_VP ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x30 18. " MII_RXD[2] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x30 17. " N2HET1[23] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x30 16. " MIBSPI1NENA ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x30 2. " RMII_RXD[1] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x30 1. " MII_RXD[1] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x30 0. " N2HET1[26] ,Control the functionality on a given ball/pin" "0,1" line.long 0x34 "PINMMR13,Pin Multiplexing Control Register 13" bitfld.long 0x34 28. " ECAP6 ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x34 27. " USB1_RCV ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x34 26. " MII_TXD[2] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x34 25. " MIBSPI1SOMI[1] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x34 24. " MIBSPI1NCS[0] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x34 19. " RMII_TXEN ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x34 18. " MII_TXEN ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x34 16. " MIBSPI5CLK ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x34 12. " MIBSPI5SOMI[2] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x34 11. " RMII_TXD[1] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x34 10. " MII_TXD[1] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x34 8. " MIBSPI5SIMO[0] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x34 3. " RMII_TXD[0] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x34 2. " MII_TXD[0] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x34 0. " MIBSPI5SOMI[0] ,Control the functionality on a given ball/pin" "0,1" line.long 0x38 "PINMMR14,Pin Multiplexing Control Register 14" bitfld.long 0x38 25. " N2HET2[5] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x38 24. " EMIF_BA[1] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x38 17. " EMIF_RNW ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x38 16. " EMIF_NWE ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x38 11. " MII_RX_AVCLK4 ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x38 10. " RMII_REFCLK ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x38 9. " MII_RXCLK ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x38 8. " N2HET1[28] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x38 3. " USB1_OVERCURRENT ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x38 2. " MII_TXD[3] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x38 1. " MIBSPI1SIMO[1] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x38 0. " N2HET1[08] ,Control the functionality on a given ball/pin" "0,1" group.long 0x154++0x1B line.long 0x00 "PINMMR17,Pin Multiplexing Control Register 17" bitfld.long 0x00 18. " RMII_CRS_DV ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x00 17. " MII_CRS ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x00 16. " N2HET1[12] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x00 4. " NTZ3 ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x00 3. " MII_TX_AVCLK4 ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x00 2. " USB1_TXEN ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x00 1. " MII_TX_CLK ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x00 0. " N2HET1[10] ,Control the functionality on a given ball/pin" "0,1" line.long 0x04 "PINMMR18,Pin Multiplexing Control Register 18" bitfld.long 0x04 25. " USB1_TXDAT ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x04 24. " GIOB[0] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x04 9. " USB1_TXSE0 ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x04 8. " N2HET1[14] ,Control the functionality on a given ball/pin" "0,1" line.long 0x08 "PINMMR19,Pin Multiplexing Control Register 19" bitfld.long 0x08 11. " EQEP2S ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x08 10. " USB1_SPEED ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x08 9. " MII_RX_DV ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x08 8. " N2HET1[30] ,Control the functionality on a given ball/pin" "0,1" line.long 0x0C "PINMMR20,Pin Multiplexing Control Register 20" bitfld.long 0x0C 20. " EQEP1S ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x0C 19. " USB1_SUSPEND ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x0C 18. " MII_COL ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x0C 17. " N2HET1[17] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x0C 16. " MIBSPI1NCS[1] ,Control the functionality on a given ball/pin" "0,1" line.long 0x10 "PINMMR21,Pin Multiplexing Control Register 21" bitfld.long 0x10 9. " USB1_PORTPOWER ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x10 8. " GIOB[1] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x10 1. " N2HET2[3] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x10 0. " EMIF_ADDR[1] ,Control the functionality on a given ball/pin" "0,1" line.long 0x14 "PINMMR22,Pin Multiplexing Control Register 22" bitfld.long 0x14 1. " N2HET2[1] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x14 0. " EMIF_ADDR[0] ,Control the functionality on a given ball/pin" "0,1" line.long 0x18 "PINMMR23,Pin Multiplexing Control Register 23" bitfld.long 0x18 2. " N2HET2[15] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x18 0. " EMIF_ADDR[8] ,Control the functionality on a given ball/pin" "0,1" group.long 0x184++0x03 line.long 0x00 "PINMMR29,Pin Multiplexing Control Register 29" bitfld.long 0x00 16. " GIOB[2] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x00 1. " SPI2NCS[1] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x00 0. " SPI2NENA ,Control the functionality on a given ball/pin" "0,1" group.long 0x194++0x07 line.long 0x00 "PINMMR33,Pin Multiplexing Control Register 33" bitfld.long 0x00 26. " EQEP1A ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x00 25. " AWM_EXT_SEL[1] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x00 24. " MIBSPI3CLK ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x00 18. " ECAP3 ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x00 17. " AWM_EXT_SEL[0] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x00 16. " MIBSPI3SIMO[0] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x00 10. " ECAP2 ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x00 9. " AWM_EXT_ENA ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x00 8. " MIBSPI3SOMI[0] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x00 1. " ETPWM4B ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x00 0. " N2HET1[04] ,Control the functionality on a given ball/pin" "0,1" line.long 0x04 "PINMMR34,Pin Multiplexing Control Register 34" bitfld.long 0x04 17. " ETPWM6B ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x04 16. " N2HET1[20] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x04 9. " ETPWM6A ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x04 8. " N2HET1[18] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x04 2. " ETPWM1SYNCO[2] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x04 1. " ETPWM1SYN ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x04 0. " N2HET1[16] ,Control the functionality on a given ball/pin" "0,1" tree.end width 11. tree.end elif (cpu()=="RM42L432") tree "IOMM (I/O Multiplexing and Control Module)" base ad:0xFFFFEA00 width 24. rgroup.long 0x0++0x3 line.long 0x0 "REVISION_REG,Module Revision Register" bitfld.long 0x00 30.--31. " REV_SCHEME ,Revision Scheme" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " REV_MODULE ,Module Id" textline " " bitfld.long 0x00 11.--15. " REV_RTL ,RTL Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. " REV_MAJOR ,Major Revision" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 6.--7. " REV_CUSTOM ,Custom Revision" "0,1,2,3" bitfld.long 0x00 0.--5. " REV_MINOR ,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x20++0x3 line.long 0x0 "BOOT_REG,Boot Config Register 0" bitfld.long 0x00 0. " ENDIAN ,Device endianness" "Little endian,Big endian" group.long 0x38++0x3 line.long 0x0 "KICK_REG0,Kicker Register 0" group.long 0x3C++0x3 line.long 0x0 "KICK_REG1,Kicker Register 1" group.long 0xE0++0x3 line.long 0x0 "ERR_RAW_STATUS_REG,Error Raw Status/Set Register" bitfld.long 0x00 1. " ADDR_ERR ,Addressing Error Status and Error Signaling Enable" "No error,Error" bitfld.long 0x00 0. " PROT_ERR ,Protection Error Status and Error Signaling Enable" "No error,Error" group.long 0xE4++0x3 line.long 0x0 "ERR_ENABLED_STATUS_REG,Error Enabled Status/Clear Register" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " ADDR_ERR_set/clr ,Addressing Error Signaling Enable Status and Status Clear" "Disabled,Enabled" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PROT_ERR_set/clr ,Protection Error Signaling Enable Status and Status Clear" "Disabled,Enabled" group.long 0xF4++0x3 line.long 0x0 "FAULT_ADDRESS_REG,Fault Address Register" rgroup.long 0xF8++0x3 line.long 0x0 "FAULT_STATUS_REG,Fault Status Register" bitfld.long 0x00 24.--27. " FAULT_ID ,Faulting Transaction ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--23. 1. " FAULT_MSTID ,Id of Master that initiated the faulting transaction" textline " " bitfld.long 0x00 9.--12. " FAULT_PRIVID ,Faulting Privilege Id" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " FAULT_NS ,Fault: Non-secure access detected" "Not detected,Detected" textline " " bitfld.long 0x00 0.--5. " FAULT_TYPE ,Type of fault detected" "No fault,User execute fault,User write fault,Reserved,User read fault,Reserved,Reserved,Reserved,Supervisor execute fault,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supervisor write fault,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supervisor read fault,?..." group.long 0xFC++0x3 line.long 0x0 "FAULT_CLEAR_REG,Fault Clear Register" bitfld.long 0x00 0. " FAULT_CLEAR ,Fault Clear" "Not cleared,Cleared" width 9. tree "Output Multiplexing and Control Registers" group.long 0x110++0x1B line.long 0x00 "PINMMR0,Pin Multiplexing Control Register 0" bitfld.long 0x00 9. " SPI3NCS[3] ,Control the functionality on a given ball/pin - Alternate Function 1" "0,1" bitfld.long 0x00 8. " GIOA[0] ,Control the functionality on a given ball/pin - Default Function" "0,1" line.long 0x04 "PINMMR1,Pin Multiplexing Control Register 1" bitfld.long 0x04 25. " SPI2NCS[2] ,Control the functionality on a given ball/pin - Alternate Function 1" "0,1" bitfld.long 0x04 24. " GIOA[4] ,Control the functionality on a given ball/pin - Default Function" "0,1" textline " " bitfld.long 0x04 17. " SPI2NCS[3] ,Control the functionality on a given ball/pin - Alternate Function 1" "0,1" bitfld.long 0x04 16. " GIOA[3] ,Control the functionality on a given ball/pin - Default Function" "0,1" textline " " bitfld.long 0x04 9. " SPI3NCS[1] ,Control the functionality on a given ball/pin - Alternate Function 1" "0,1" bitfld.long 0x04 8. " GIOA[2] ,Control the functionality on a given ball/pin - Default Function" "0,1" textline " " bitfld.long 0x04 1. " SPI3NCS[2] ,Control the functionality on a given ball/pin - Alternate Function 1" "0,1" bitfld.long 0x04 0. " GIOA[1] ,Control the functionality on a given ball/pin - Default Function" "0,1" line.long 0x08 "PINMMR2,Pin Multiplexing Control Register 2" bitfld.long 0x08 17. " N2HET[29] ,Control the functionality on a given ball/pin - Alternate Function 1" "0,1" bitfld.long 0x08 16. " GIOA[7] ,Control the functionality on a given ball/pin - Default Function" "0,1" textline " " bitfld.long 0x08 10. " N2HET[31] ,Control the functionality on a given ball/pin - Alternate Function 2" "0,1" bitfld.long 0x08 9. " SPI2NCS[1] ,Control the functionality on a given ball/pin - Alternate Function 1" "0,1" bitfld.long 0x08 8. " GIOA[6] ,Control the functionality on a given ball/pin - Default Function" "0,1" textline " " bitfld.long 0x08 1. " EXTCLKIN ,Control the functionality on a given ball/pin - Alternate Function 1" "0,1" bitfld.long 0x08 0. " GIOA[5] ,Control the functionality on a given ball/pin - Default Function" "0,1" line.long 0x0C "PINMMR3,Pin Multiplexing Control Register 3" bitfld.long 0x0C 25. " EQEPB ,Control the functionality on a given ball/pin - Alternate Function 1" "0,1" bitfld.long 0x0C 24. " SPI3NENA ,Control the functionality on a given ball/pin - Default Function" "0,1" textline " " bitfld.long 0x0C 17. " EQEPA ,Control the functionality on a given ball/pin - Alternate Function 1" "0,1" bitfld.long 0x0C 16. " SPI3CLK ,Control the functionality on a given ball/pin - Default Function" "0,1" textline " " bitfld.long 0x0C 2. " N2HET[19] ,Control the functionality on a given ball/pin - Alternate Function 2" "0,1" bitfld.long 0x0C 1. " N2HET[20] ,Control the functionality on a given ball/pin - Alternate Function 1" "0,1" bitfld.long 0x0C 0. " MIBSPI1NCS[2] ,Control the functionality on a given ball/pin - Default Function" "0,1" line.long 0x10 "PINMMR4,Pin Multiplexing Control Register 4" bitfld.long 0x10 17. " N2HET[28] ,Control the functionality on a given ball/pin - Alternate Function 1" "0,1" bitfld.long 0x10 16. " ADEVT ,Control the functionality on a given ball/pin - Default Function" "0,1" textline " " bitfld.long 0x10 9. " N2HET[26] ,Control the functionality on a given ball/pin - Alternate Function 1" "0,1" bitfld.long 0x10 8. " MIBSPI1NCS[3] ,Control the functionality on a given ball/pin - Default Function" "0,1" textline " " bitfld.long 0x10 1. " EQEPI ,Control the functionality on a given ball/pin - Alternate Function 1" "0,1" bitfld.long 0x10 0. " SPI3NCS[0] ,Control the functionality on a given ball/pin - Default Function" "0,1" line.long 0x14 "PINMMR5,Pin Multiplexing Control Register 5" bitfld.long 0x14 10. " NHET[30] ,Control the functionality on a given ball/pin - Alternate Function 2" "0,1" bitfld.long 0x14 9. " N2HET[23] ,Control the functionality on a given ball/pin - Alternate Function 1" "0,1" bitfld.long 0x14 8. " MIBSPI1NENA ,Control the functionality on a given ball/pin - Default Function" "0,1" line.long 0x18 "PINMMR6,Pin Multiplexing Control Register 6" bitfld.long 0x18 10. " N2HET[17] ,Control the functionality on a given ball/pin - Alternate Function 2" "0,1" bitfld.long 0x18 9. " EQEPS ,Control the functionality on a given ball/pin - Alternate Function 1" "0,1" bitfld.long 0x18 8. " MIBSPI1NCS[1] ,Control the functionality on a given ball/pin - Default Function" "0,1" tree.end width 11. tree.end else tree "IOMM (I/O Multiplexing and Control Module)" base ad:0xFFFFEA00 width 23. rgroup.long 0x0++0x3 line.long 0x0 "REVISION_REG,Module Revision Register" bitfld.long 0x00 30.--31. " REV_SCHEME ,Revision Scheme" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " REV_MODULE ,Module Id" textline " " bitfld.long 0x00 11.--15. " REV_RTL ,RTL Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. " REV_MAJOR ,Major Revision" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 6.--7. " REV_CUSTOM ,Custom Revision" "0,1,2,3" bitfld.long 0x00 0.--5. " REV_MINOR ,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x20++0x3 line.long 0x0 "BOOT_REG,Boot Config Register 0" bitfld.long 0x00 0. " ENDIAN ,Device endianness" "Little endian,Big endian" group.long 0x38++0x3 line.long 0x0 "KICK_REG0,Kicker Register 0" group.long 0x3C++0x3 line.long 0x0 "KICK_REG1,Kicker Register 1" group.long 0xE0++0x3 line.long 0x0 "ERR_RAW_STATUS_REG,Error Raw Status/Set Register" bitfld.long 0x00 1. " ADDR_ERR ,Addressing Error Status and Error Signaling Enable" "No error,Error" bitfld.long 0x00 0. " PROT_ERR ,Protection Error Status and Error Signaling Enable" "No error,Error" group.long 0xE4++0x3 line.long 0x0 "ERR_ENABLED_STATUS_REG,Error Enabled Status/Clear Register" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " ADDR_ERR_set/clr ,Addressing Error Signaling Enable Status and Status Clear" "Disabled,Enabled" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " PROT_ERR_set/clr ,Protection Error Signaling Enable Status and Status Clear" "Disabled,Enabled" group.long 0xF4++0x3 line.long 0x0 "FAULT_ADDRESS_REG,Fault Address Register" rgroup.long 0xF8++0x3 line.long 0x0 "FAULT_STATUS_REG,Fault Status Register" bitfld.long 0x00 24.--27. " FAULT_ID ,Faulting Transaction ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--23. 1. " FAULT_MSTID ,Id of Master that initiated the faulting transaction" textline " " bitfld.long 0x00 9.--12. " FAULT_PRIVID ,Faulting Privilege Id" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. " FAULT_NS ,Fault: Non-secure access detected" "Not detected,Detected" textline " " bitfld.long 0x00 0.--5. " FAULT_TYPE ,Type of fault detected" "No fault,User execute fault,User write fault,Reserved,User read fault,Reserved,Reserved,Reserved,Supervisor execute fault,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supervisor write fault,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Supervisor read fault,?..." group.long 0xFC++0x3 line.long 0x0 "FAULT_CLEAR_REG,Fault Clear Register" bitfld.long 0x00 0. " FAULT_CLEAR ,Fault Clear" "Not cleared,Cleared" tree "Output Multiplexing and Control Registers" width 10. group.long 0x110++0x33 line.long 0x00 "PINMMR00,Pin Multiplexing Control Register 00" bitfld.long 0x00 26. " N2HET1[27] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x00 25. " I2C_SDA ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x00 24. " MIBSPI3NCS[2] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x00 18. " N2HET1[29] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x00 17. " I2C_SCL ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x00 16. " MIBSPI3NCS[3] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x00 8. " GIOA[0] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x00 0. " GIOB[3] ,Control the functionality on a given ball/pin" "0,1" line.long 0x04 "PINMMR01,Pin Multiplexing Control Register 01" bitfld.long 0x04 25. " EMIF_DATA[4] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x04 24. " ETMDATA[21] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x04 17. " EMIF_DATA[4] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x04 16. " ETMDATA[20] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x04 10. " N2HET2[18] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x04 9. " MIBSPI3NCS[4] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x04 8. " N2HET1[11] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x04 0. " GIOA[1] ,Control the functionality on a given ball/pin" "0,1" line.long 0x08 "PINMMR02,Pin Multiplexing Control Register 02" bitfld.long 0x08 25. " EXTCLKIN ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x08 24. " GIOA[5] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x08 17. " N2HET2[2] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x08 16. " GIOA[3] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x08 9. " EMIF_DATA[6] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x08 8. " ETMDATA[22] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x08 3. " NHET2[0] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x08 0. " GIOA[2] ,Control the functionality on a given ball/pin" "0,1" line.long 0x0C "PINMMR03,Pin Multiplexing Control Register 03" bitfld.long 0x0C 25. " EMIF_DATA[8] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x0C 24. " ETMDATA[24] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x0C 17. " N2HET2[4] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x0C 16. " GIOA[6] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x0C 8. " ETMDATA[23] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x0C 1. " EMIF_DATA[7] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x0C 0. " ETMDATA[23] ,Control the functionality on a given ball/pin" "0,1" line.long 0x10 "PINMMR04,Pin Multiplexing Control Register 04" bitfld.long 0x10 28. " N2HET2[10] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x10 25. " SPI4NCS[0] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x10 24. " N2HET1[03] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x10 20. " N2HET2[8] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x10 17. " SPI4NENA ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x10 16. " N2HET1[01] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x10 9. " EMIF_DATA[9] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x10 8. " ETMDATA[25] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x10 1. " N2HET2[6] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x10 0. " GIOA[7] ,Control the functionality on a given ball/pin" "0,1" line.long 0x14 "PINMMR05,Pin Multiplexing Control Register 05" bitfld.long 0x14 25. " EMIF_DATA[10] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x14 24. " ETMDATA[26] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x14 18. " N2HET2[12] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x14 17. " SPI4SOMI ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x14 16. " N2HET1[05] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x14 9. " SPI4SIMO ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x14 8. " N2HET1[02] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x14 1. " SPI4CLK ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x14 0. " N2HET1[0] ,Control the functionality on a given ball/pin" "0,1" line.long 0x18 "PINMMR06,Pin Multiplexing Control Register 06" bitfld.long 0x18 25. " EMIF_DATA[12] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x18 24. " ETMDATA[28] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x18 17. " N2HET2[16] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x18 16. " N2HET1[09] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x18 9. " EMIF_DATA[11] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x18 8. " ETMDATA[27] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x18 3. " N2HET2[14] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x18 0. " ETMDATA[26] ,Control the functionality on a given ball/pin" "0,1" line.long 0x1C "PINMMR07,Pin Multiplexing Control Register 07" bitfld.long 0x1C 25. " EMIF_DATA[14] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x1C 24. " ETMDATA[30] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x1C 17. " SCIRX ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x1C 16. " N2HET1[06] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x1C 10. " MDCLK ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x1C 9. " N2HET1[25] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x1C 8. " MIBSPI3NCS[1] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x1C 1. " EMIF_DATA[13] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x1C 0. " ETMDATA[29] ,Control the functionality on a given ball/pin" "0,1" line.long 0x20 "PINMMR08,Pin Multiplexing Control Register 08" bitfld.long 0x20 25. " EMIF_DATA[15] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x20 24. " ETMDATA[31] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x20 17. " MIBSPI1NCS[4] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x20 16. " N2HET1[15] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x20 10. " MDIO ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x20 9. " N2HET1[19] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x20 8. " MIBSPI1NCS[2] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x20 1. " SCITX ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x20 0. " N2HET1[13] ,Control the functionality on a given ball/pin" "0,1" line.long 0x24 "PINMMR09,Pin Multiplexing Control Register 09" bitfld.long 0x24 25. " N2HET1[21] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x24 24. " MIBSPI1NCS[3] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x24 17. " AD2EVT ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x24 16. " MIBSPI3NCS[0] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x24 10. " N2HET1[31] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x24 9. " MIBSPI3NCS[5] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x24 8. " MIBSPI3NENA ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x24 1. " EXTCLKIN2 ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x24 0. " ETMTRACECLKIN ,Control the functionality on a given ball/pin" "0,1" line.long 0x28 "PINMMR10,Pin Multiplexing Control Register 10" bitfld.long 0x28 25. " EMIF_DATA[2] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x28 24. " ETMDATA[18] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x28 18. " N2HET2[7] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x28 17. " RTP_DATA[15] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x28 16. " EMIF_NCS[0] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x28 9. " EMIF_DATA[3] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x28 8. " ETMDATA[19] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x28 2. " RMII_RX_ER ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x28 1. " MII_RX_ER ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x28 0. " AD1EVT ,Control the functionality on a given ball/pin" "0,1" line.long 0x2C "PINMMR11,Pin Multiplexing Control Register 11" bitfld.long 0x2C 27. " RMII_RXD[0] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x2C 26. " MII_RXD[0] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x2C 25. " MIBSPI1NCS[5] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x2C 24. " N2HET1[24] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x2C 12. " EMIF_DATA[1] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x2C 11. " ETMDATA[17] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x2C 9. " RTP_DATA[07] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x2C 8. " EMIF_NCS[4] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x2C 2. " N2HET2[9] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x2C 1. " RTP_DATA[14] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x2C 0. " EMIF_NCS[3] ,Control the functionality on a given ball/pin" "0,1" line.long 0x30 "PINMMR12,Pin Multiplexing Control Register 12" bitfld.long 0x30 18. " MII_RXD[2] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x30 17. " N2HET1[23] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x30 16. " EMIF_DATA[0] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x30 9. " EMIF_DATA[0] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x30 8. " ETMDATA[16] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x30 2. " RMII_RXD[1] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x30 1. " MII_RXD[1] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x30 0. " N2HET1[26] ,Control the functionality on a given ball/pin" "0,1" group.long 0x144++0x033 line.long 0x00 "PINMMR13,Pin Multiplexing Control Register 13" bitfld.long 0x00 26. " MII_TXD[2] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x00 25. " MIBSPI1SOMNI[1] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x00 24. " MIBSPI1NCS[0] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x00 19. " RMII_TXEN ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x00 18. " MII_TXEN ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x00 17. " DMM_DATA[4] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x00 16. " MIBSPI5CLK ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x00 11. " RMII_TXD[1] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x00 10. " MII_TXD[1] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x00 9. " DMM_DATA[8] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x00 8. " MIBSPI5SIMO[0] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x00 3. " RMII_TXD[0] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x00 2. " MII_TXD[0] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x00 1. " DMM_DATA[12] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x00 0. " MIBSPI5SOMI[0] ,Control the functionality on a given ball/pin" "0,1" line.long 0x04 "PINMMR14,Pin Multiplexing Control Register 14" bitfld.long 0x04 25. " N2HET2[5] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x04 24. " EMIF_BA[1] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x04 17. " EMIF_RNW ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x04 16. " EMIF_NWE ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x04 11. " MII_RX_AVCLK4 ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x04 10. " RMII_REFCLK ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x04 9. " MII_RXCLK ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x04 8. " N2HET1[28] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x04 2. " MII_TXD[3] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x04 1. " MIBSPI1SIMO[1] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x04 0. " N2HET1[8] ,Control the functionality on a given ball/pin" "0,1" line.long 0x08 "PINMMR15,Pin Multiplexing Control Register 15" bitfld.long 0x08 25. " RTP_DATA[0] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x08 24. " EMIF_ADDR[18] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x08 17. " RTP_NENA ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x08 16. " EMIF_ADDR[19] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x08 9. " RTP_NSYNC ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x08 8. " EMIF_ADDR[20] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x08 1. " RTP_CLK ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x08 0. " EMIF_ADDR[21] ,Control the functionality on a given ball/pin" "0,1" line.long 0x0C "PINMMR16,Pin Multiplexing Control Register 16" bitfld.long 0x0C 25. " EMIF_NOE ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x0C 24. " RTP_DATA[13] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x0C 17. " RTP_DATA[02] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x0C 16. " EMIF_ADDR[16] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x0C 9. " RTP_DATA[01] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x0C 8. " EMIF_ADDR[17] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x0C 1. " EMIF_BA[0] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x0C 0. " ETMDATA[12] ,Control the functionality on a given ball/pin" "0,1" line.long 0x10 "PINMMR17,Pin Multiplexing Control Register 17" bitfld.long 0x10 25. " EMIF_ADDR[5] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x10 24. " ETMDATA[8] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x10 18. " RMII_CRS_DV ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x10 17. " MII_CRS ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x10 16. " N2HET1[12] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x10 9. " EMIF_NDQM[1] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x10 8. " ETMDATA[14] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x10 3. " MII_TX_AVCLK4 ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x10 1. " MII_TX_CLK ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x10 0. " N2HET1[10] ,Control the functionality on a given ball/pin" "0,1" line.long 0x14 "PINMMR18,Pin Multiplexing Control Register 18" bitfld.long 0x14 24. " GIOB[0] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x14 17. " RTP_DATA[04] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x14 16. " EMIF_ADDR[14] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x14 8. " N2HET1[14] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x14 1. " RTP_DATA[03] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x14 0. " EMIF_ADDR[15] ,Control the functionality on a given ball/pin" "0,1" line.long 0x18 "PINMMR19,Pin Multiplexing Control Register 19" bitfld.long 0x18 25. " EMIF_ADDR[3] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x18 24. " ETMDATA[10] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x18 17. " EMIF_NDQM[0] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x18 16. " ETMDATA[15] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x18 9. " MII_RX_DV ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x18 8. " N2HET1[30] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x18 1. " EMIF_ADDR[4] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x18 0. " ETMDATA[09] ,Control the functionality on a given ball/pin" "0,1" line.long 0x1C "PINMMR20,Pin Multiplexing Control Register 20" bitfld.long 0x1C 25. " RTP_DATA[8] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x1C 24. " EMIF_ADDR[11] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x1C 18. " MII_COL ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x1C 17. " N2HET1[17] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x1C 16. " MIBSPI1NCS[1] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x1C 9. " RTP_DATA[06] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x1C 8. " EMIF_ADDR[12] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x1C 1. " RTP_DATA[05] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x1C 0. " EMIF_ADDR[13] ,Control the functionality on a given ball/pin" "0,1" line.long 0x20 "PINMMR21,Pin Multiplexing Control Register 21" bitfld.long 0x20 25. " RTP_DATA[10] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x20 24. " EMIF_ADDR[9] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x20 17. " RTP_DATA[09] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x20 16. " EMIF_ADDR[10] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x20 8. " GIOB[1] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x20 1. " N2HET2[3] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x20 0. " EMIF_ADDR[1] ,Control the functionality on a given ball/pin" "0,1" line.long 0x24 "PINMMR22,Pin Multiplexing Control Register 22" bitfld.long 0x24 25. " EMIF_ADDR[2] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x24 24. " ETMDATA[11] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x24 18. " MII_TXEN ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x24 17. " DMM_DATA[4] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x24 16. " MIBSPI5CLK ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x24 10. " N2HET2[13] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x24 9. " RTP_DATA[12] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x24 8. " EMIF_ADDR[7] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x24 1. " N2HET2[1] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x24 0. " EMIF_ADDR[0] ,Control the functionality on a given ball/pin" "0,1" line.long 0x28 "PINMMR23,Pin Multiplexing Control Register 23" bitfld.long 0x28 24. " SPI4SOMI ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x28 16. " SPI4SIMO ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x28 8. " SPI4CLK ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x28 2. " N2HET2[15] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x28 1. " RTP_DATA[11] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x28 0. " EMIF_ADDR[8] ,Control the functionality on a given ball/pin" "0,1" line.long 0x2C "PINMMR24,Pin Multiplexing Control Register 24" bitfld.long 0x2C 24. " N2HET1[19] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x2C 16. " N2HET1[17] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x2C 8. " SPI4NCS[0] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x2C 0. " SPI4NENA ,Control the functionality on a given ball/pin" "0,1" line.long 0x30 "PINMMR25,Pin Multiplexing Control Register 25" bitfld.long 0x30 24. " N2HET1[27] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x30 16. " N2HET1[25] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x30 8. " N2HET1[23] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x30 0. " N2HET1[21] ,Control the functionality on a given ball/pin" "0,1" group.long 0x178++0x13 line.long 0x00 "PINMMR26,Pin Multiplexing Control Register 26" bitfld.long 0x00 25. " DMM_DATA[3] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x00 24. " MIBSPI5NCS[3] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x00 17. " DMM_DATA[2] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x00 16. " MIBSPI5NCS[2] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x00 8. " N2HET1[31] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x00 0. " N2HET1[29] ,Control the functionality on a given ball/pin" "0,1" line.long 0x04 "PINMMR27,Pin Multiplexing Control Register 27" bitfld.long 0x04 25. " DMM_DATA[10] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x04 24. " MIBSPI5SIMO[2] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x04 17. " DMM_DATA[9] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x04 16. " MIBSPI5SIMO[1] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x04 9. " DMM_DATA[6] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x04 8. " MIBSPI5NCS[1] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x04 1. " DMM_DATA[5] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x04 0. " MIBSPI5NCS[0] ,Control the functionality on a given ball/pin" "0,1" line.long 0x08 "PINMMR28,Pin Multiplexing Control Register 28" bitfld.long 0x08 25. " DMM_DATA[15] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x08 24. " MIBSPI5SOMI[3] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x08 17. " DMM_DATA[14] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x08 16. " MIBSPI5SOMI[2] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x08 9. " DMM_DATA[13] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x08 8. " MIBSPI5SOMI[1] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x08 1. " DMM_DATA[11] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x08 0. " MIBSPI5SIMO[3] ,Control the functionality on a given ball/pin" "0,1" line.long 0x0C "PINMMR29,Pin Multiplexing Control Register 29" bitfld.long 0x0C 24. " GMII_SEL ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x0C 16. " GIOB[2] ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x0C 8. " EMIF_CLK_SEL ,Control the functionality on a given ball/pin" "0,1" textline " " bitfld.long 0x0C 1. " SPI2NCS[1] ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x0C 0. " SPI2NENA ,Control the functionality on a given ball/pin" "0,1" line.long 0x10 "PINMMR30,Pin Multiplexing Control Register 30" bitfld.long 0x10 1. " ADC_TRG2 ,Control the functionality on a given ball/pin" "0,1" bitfld.long 0x10 0. " ADC_TRG1 ,Control the functionality on a given ball/pin" "0,1" tree.end width 11. tree.end endif sif (cpu()=="RM42L432"||cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE") tree "F021 Flash Module Controller" base ad:0xFFF87000 width 15. group.long 0x00++0x3 line.long 0x0 "FRDCNTL,Read Control Register" bitfld.long 0x00 8.--11. " RWAIT ,Random Read Wait State" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles" bitfld.long 0x00 4. " ASWSTEN ,Address Setup Wait State Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " ENPIPE ,Enable Pipeline Mode" "Disabled,Enabled" group.long 0x08++0x0B line.long 0x0 "FEDACCTRL1,Error Correction Control Register1" bitfld.long 0x00 24. " SUSP_IGNR ,Suspend Ignore" "Not ignored,Ignored" bitfld.long 0x00 16.--19. " EDACMODE ,Error Correction Mode" "Correction mode,Correction mode,Correction mode,Correction mode,Correction mode,Detection mode,Correction mode,Correction mode,Correction mode,Correction mode,Correction mode,Correction mode,Correction mode,Correction mode,Correction mode,Correction mode" textline " " bitfld.long 0x00 10. " EOFEN ,Event on Ones Fail Enable" "Disabled,Enabled" bitfld.long 0x00 9. " EZFEN ,Error on Zero Fail Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " EPEN ,Error Profiling Enable" "Disabled,Enabled" bitfld.long 0x00 0.--3. " EDACEN ,Error Detection and Correction Enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" line.long 0x4 "FEDACCTRL2,Error Correction Control Register2" hexmask.long.word 0x04 0.--15. 1. " SEC_THRESHOLD ,Single Error Correction Threshold" line.long 0x08 "FCOR_ERR_CNT,Flash Correctable Error Count Register" hexmask.long.word 0x08 0.--15. 1. " FERRCNT ,Single Error Correction Count" rgroup.long 0x14++0x07 line.long 0x00 "FCOR_ERR_ADD,Flash Correctable Error Address Register" hexmask.long 0x00 3.--31. 0x8 " COR_ERR_ADD ,Correctable Error Address" bitfld.long 0x00 0.--2. " B_OFF ,Byte Offset" "0,1,2,3,%d..." line.long 0x04 "FCOR_ERR_POS,Flash Correctable Error Position Register" bitfld.long 0x04 9. " BUS2 ,Bus 2 Error" "Main flash,OTP read" textline " " bitfld.long 0x04 8. " TYPE ,ErrorType" "One of the 64 data bits,One of the 8 check bits" textline " " hexmask.long.byte 0x04 0.--7. 1. " ERR_POS ,The bit address of the single bit error" group.long 0x1C++0x03 line.long 0x00 "FEDACSTATUS,Flash Error Detection and Correction Status Register" eventfld.long 0x00 24. " FSM_DONE ,Flash State Machine Done" "Not occurred,Occurred" eventfld.long 0x00 19. " COMB2_MAL_G ,Bus 2 Compare Malfunction Flag" "Detected,Not detected" textline " " eventfld.long 0x00 18. " ,Bus 2 ECC Malfunction Error Flag" "No error,Error" eventfld.long 0x00 17. " B2_UNC_ERR ,Bus 2 uncorrectable error" "No error,Error" textline " " eventfld.long 0x00 16. " B2_COR_ERR ,Bus 2 Correctable Error" "No error,Error" eventfld.long 0x00 12. " D_UNC_ERR ,Bus 2 ECC Malfunction Error Flag" "No error,Error" textline " " eventfld.long 0x00 11. " ADD_TAG_ERR ,Address Tag Register Error Flag" "No error,Error" eventfld.long 0x00 10. " ADD_PAR_ERR ,Address Parity Error Flag" "No error,Error" textline " " eventfld.long 0x00 8. " B1_UNC_ERR ,Bus 1 Uncorrectable Error Flag" "No error,Error" eventfld.long 0x00 3. " D_CORR_ERR ,Diagnostic Correctable Error Status Flag" "No error,Error" textline " " eventfld.long 0x00 2. " ERR_ONE_FLG ,Error on One Fail Status Flag" "Not occurred,Occurred" eventfld.long 0x00 1. " ,Error on Zero Fail Status Flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 0. " ERR_PRF_FLG ,Error Profiling Status Flag" "Not occurred,Occurred" rgroup.long 0x20++0x3 line.long 0x0 "FUNC_ERR_ADD,Un-correctable Error Address" hexmask.long 0x00 3.--31. 0x8 " UNC_ERR_ADD ,Un-correctable Error Address" bitfld.long 0x00 0.--2. " B_OFF ,Byte offset" "0,1,2,3,4,5,6,7" group.long 0x24++0x03 line.long 0x00 "FEDACSDIS,Flash Error Detection and Correction Sector Disable Register" bitfld.long 0x00 29.--31. " BANKID1_INVERSE ,The bank ID inverse bits are used with the bank ID bits to select the bank for which a sector is disabled" "ECC checking disabled,No sector is disabled,No sector is disabled,No sector is disabled,No sector is disabled,No sector is disabled,No sector is disabled,No sector is disabled" bitfld.long 0x00 24.--27. " SECTORID1_INVERSE ,The sector ID inverse bits are used with the sector ID bits to determine which sector is disabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21.--23. " BANKID1 ,The bank ID bits are used with the bank ID inverse bits to select the bank for which a sector is disabled" "ECC checking disabled,No sector is disabled,No sector is disabled,No sector is disabled,No sector is disabled,No sector is disabled,No sector is disabled,No sector is disabled" bitfld.long 0x00 16.--19. " SECTORID1 ,The sector ID bits are used with the sector ID inverse bits to determine which sector is disabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 13.--15. " BANKID0_INVERSE ,The bank ID inverse bits are used with the bank ID bits to select the bank for which a sector is disabled" "ECC checking disabled,No sector is disabled,No sector is disabled,No sector is disabled,No sector is disabled,No sector is disabled,No sector is disabled,No sector is disabled" bitfld.long 0x00 8.--11. " SECTORID0_INVERSE ,The sector ID inverse bits are used with the sector ID bits to determine which sector is disabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 5.--7. " BANKID0 ,The bank ID bits are used with the bank ID inverse bits to select the bank for which a sector is disabled" "ECC checking disabled,No sector disabled,No sector is disabled,No sector disabled,No sector is disabled,No sector is disabled,No sector is disabled,No sector is disabled" bitfld.long 0x00 0.--3. " SECTORID0 ,The sector ID bits are used with the sector ID inverse bits to determine which sector is disabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x28++0x07 line.long 0x00 "FPRIM_ADD_TAG,Primary Address Tag Register" hexmask.long 0x00 4.--31. 0x10 " PRIM_ADD_TAG ,Primary Address Tag Register" line.long 0x04 "FDUP_ADD_TAG,Duplicate Address Tag Register" hexmask.long 0x04 4.--31. 0x10 " DUP_ADD_TAG ,Duplicate Address Tag Register" group.long 0x30++0x7 line.long 0x0 "FBPROT,Bank Protection Register" bitfld.long 0x00 0. " PROTL1DIS ,Level 1 Protection Disable" "No,Yes" line.long 0x4 "FBSE,Bank Sector Enable Register" bitfld.long 0x04 15. " BSE[15] ,Bank Sector Enable 15" "Disabled,Enabled" bitfld.long 0x04 14. " BSE[14] ,Bank Sector Enable 14" "Disabled,Enabled" textline " " bitfld.long 0x04 13. " BSE[13] ,Bank Sector Enable 13" "Disabled,Enabled" bitfld.long 0x04 12. " BSE[12] ,Bank Sector Enable 12" "Disabled,Enabled" textline " " bitfld.long 0x04 11. " BSE[11] ,Bank Sector Enable 11" "Disabled,Enabled" bitfld.long 0x04 10. " BSE[10] ,Bank Sector Enable 10" "Disabled,Enabled" textline " " bitfld.long 0x04 9. " BSE[9] ,Bank Sector Enable 9" "Disabled,Enabled" bitfld.long 0x04 8. " BSE[8] ,Bank Sector Enable 8" "Disabled,Enabled" textline " " bitfld.long 0x04 7. " BSE[7] ,Bank Sector Enable 7" "Disabled,Enabled" bitfld.long 0x04 6. " BSE[6] ,Bank Sector Enable 6" "Disabled,Enabled" textline " " bitfld.long 0x04 5. " BSE[5] ,Bank Sector Enable 5" "Disabled,Enabled" bitfld.long 0x04 4. " BSE[4] ,Bank Sector Enable 4" "Disabled,Enabled" textline " " bitfld.long 0x04 3. " BSE[3] ,Bank Sector Enable 3" "Disabled,Enabled" bitfld.long 0x04 2. " BSE[2] ,Bank Sector Enable 2" "Disabled,Enabled" textline " " bitfld.long 0x04 1. " BSE[1] ,Bank Sector Enable 1" "Disabled,Enabled" bitfld.long 0x04 0. " BSE[0] ,Bank Sector Enable 0" "Disabled,Enabled" rgroup.long 0x38++0x03 line.long 0x00 "FBBUSY,Flash Bank Busy Register" bitfld.long 0x00 7. " BUSY[7] ,Bank Busy 7" "Not busy,Not busy/not implemented" textline " " bitfld.long 0x00 6. " BUSY[6] ,Bank Busy 6" "Not busy,Not busy/not implemented" textline " " bitfld.long 0x00 5. " BUSY[5] ,Bank Busy 5" "Not busy,Not busy/not implemented" textline " " bitfld.long 0x00 4. " BUSY[4] ,Bank Busy 4" "Not busy,Not busy/not implemented" textline " " bitfld.long 0x00 3. " BUSY[3] ,Bank Busy 3" "Not busy,Not busy/not implemented" textline " " bitfld.long 0x00 2. " BUSY[2] ,Bank Busy 2" "Not busy,Not busy/not implemented" textline " " bitfld.long 0x00 1. " BUSY[1] ,Bank Busy 1" "Not busy,Not busy/not implemented" textline " " bitfld.long 0x00 0. " BUSY[0] ,Bank Busy 0" "Not busy,Not busy/not implemented" group.long 0x3C++0x7 line.long 0x0 "FBAC,Bank Access Control Register" bitfld.long 0x00 23. " OTPPROTDIS[7] ,OTP Sector Protection Disable 7" "Disabled,Enabled" bitfld.long 0x00 22. " OTPPROTDIS[6] ,OTP Sector Protection Disable 6" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " OTPPROTDIS[5] ,OTP Sector Protection Disable 5" "Disabled,Enabled" bitfld.long 0x00 20. " OTPPROTDIS[4] ,OTP Sector Protection Disable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " OTPPROTDIS[3] ,OTP Sector Protection Disable 3" "Disabled,Enabled" bitfld.long 0x00 18. " OTPPROTDIS[2] ,OTP Sector Protection Disable 2" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " OTPPROTDIS[1] ,OTP Sector Protection Disable 1" "Disabled,Enabled" bitfld.long 0x00 16. " OTPPROTDIS[0] ,OTP Sector Protection Disable 0" "Disabled,Enabled" textline " " hexmask.long.byte 0x00 8.--15. 1. " BAGP[7:0] ,Bank Active Grace Period" hexmask.long.byte 0x00 0.--7. 1. " VREADST[7:0] ,VREAD Setup" line.long 0x4 "FBFALLBACK,Bank Fallback Power Register" bitfld.long 0x04 6.--7. " BANKPWR7 ,Bank 3 Fallback Power Mode" "Sleep,Standby,Reserved,Active" bitfld.long 0x04 2.--3. " BANKPWR1 ,Bank 1 Fallback Power Mode" "Sleep,Standby,Reserved,Active" textline " " bitfld.long 0x04 0.--1. " BANKPWR0 ,Bank 0 Fallback Power Mode" "Sleep,Standby,Reserved,Active" group.long 0x48++0xb line.long 0x0 "FPAC1,Pump Access Control Register 1" hexmask.long.word 0x00 16.--26. 1. " PSLEEP[10:0] ,Pump Sleep" bitfld.long 0x00 0. " PUMPPWR ,Flash Charge Pump Fallback Power Mode" "Sleep,Active" line.long 0x4 "FPAC2,Pump Access Control Register 2" hexmask.long.word 0x4 0.--15. 1. " PAGP[15:0] ,Pump Active Grace Period" line.long 0x8 "FMAC,Module Access Control Register" bitfld.long 0x8 0.--2. " BANK[2:0] ,Bank Enable" "Bank 0,Bank 1,Bank 2,Bank 3,Bank 4,Bank 5,Bank 6,Bank 7" rgroup.long 0x54++0x3 line.long 0x00 "FMSTAT,Flash Module Status Register" bitfld.long 0x00 17. " RVSUSP ,Read Verify Suspend" "Not detected,Detected" bitfld.long 0x00 16. " RVDER ,Read verify command currently underway" "Not detected,Detected" textline " " bitfld.long 0x00 15. " RVF ,Read Verify Failure" "Not detected,Detected" bitfld.long 0x00 14. " ILA ,Illegal Address" "Not detected,Detected" textline " " bitfld.long 0x00 13. " DBT ,Disturbance Test Fail" "Not detected,Detected" bitfld.long 0x00 12. " PGV ,Program Verify" "Not detected,Detected" textline " " bitfld.long 0x00 11. " PCV ,Precondition Verify" "Not detected,Detected" bitfld.long 0x00 10. " EV ,Erase Verify" "Not detected,Detected" textline " " bitfld.long 0x00 9. " CV ,Compact Verify" "Not detected,Detected" bitfld.long 0x00 8. " BUSY ,Busy" "Idle,Busy" textline " " bitfld.long 0x00 7. " ERS ,Erase Active" "Not detected,Detected" bitfld.long 0x00 6. " PGM ,Program Active" "Not detected,Detected" textline " " bitfld.long 0x00 5. " INVDAT ,Invalid Data" "Not detected,Detected" bitfld.long 0x00 4. " CSTAT ,Command Status" "No effect,Stopped" textline " " bitfld.long 0x00 3. " VOLTSTAT ,Core Voltage Status" "0,1" bitfld.long 0x00 2. " ESUSP ,Erase Suspended" "Not suspended,Suspended" textline " " bitfld.long 0x00 1. " PSUSP ,Program Suspended" "Not suspended,Suspended" bitfld.long 0x00 0. " SLOCK ,Sector Lock Status" "Not locked,Locked" group.long 0x58++0x13 line.long 0x00 "FEMU_DMSW,EEPROM Emulation Data MSW Register" line.long 0x04 "FEMU_DLSW,EEPROM Emulation Data LSW Register" line.long 0x08 "FEMU_ECC,EEPROM Emulation ECC Register" hexmask.long.byte 0x08 0.--7. 1. " EMU_ECC ,EEPROM Emulation ECC" line.long 0x0C "FLOCK,Flash Lock Register" hexmask.long.word 0x0C 0.--15. 1. " ENCOM ,Enable writes to FEDACCTRL1 register" line.long 0x10 "FEMU_ADDR,EEPROM Emulation Address Register" hexmask.long.tbyte 0x10 3.--21. 0x8 " EMU_ADDR ,EEPROM Emulation Address" group.long 0x6C++0x03 line.long 0x00 "FDIAGCTRL,Diagnostic Control Register" bitfld.long 0x00 24. " DIAG_TRIG ,Diagnostic Trigger" "0,1" textline " " bitfld.long 0x00 16.--19. " DIAG_EN_KEY ,Diagnostic Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,?..." textline " " bitfld.long 0x00 12.--14. " DIAG_ECC_SEL ,Diagnostic SECDED Select" "SECDED0,SECDED1,SECDED2,SECDED3,BUS2 SECDED,FEE SECDED,?..." textline " " bitfld.long 0x00 8.--9. " DIAG_BUF_SEL ,Diagnostic Buffer Select" "Instruction Buffer 0,Data Buffer 0,Instruction Buffer 1,Data Buffer 1" textline " " bitfld.long 0x00 0.--2. " DIAGMODE ,Diagnostic Mode" "Disabled,ECC data correction,ECC syndrome reporting,ECC malfunction test,ECC malfunction,Address tag register diagnostic,Reserved,ECC Data Correction Diagnostic" group.long 0x70++0x07 line.long 0x00 "FRAW_DATAH,Uncorrected Raw Data High Register" line.long 0x04 "FRAW_DATAL,Uncorrected Raw Data Low Register" group.long 0x78++0x07 line.long 0x00 "FRAW_ECC,Uncorrected Raw ECC Register" eventfld.long 0x00 8. " PIPE_BUF ,Error came from pipeline buffer hit" "No error,Error" hexmask.long.byte 0x00 0.--7. 1. " RAW_ECC ,Uncorrected Raw ECC" line.long 0x04 "FPAR_OVR,Parity Override Register" bitfld.long 0x04 16. " BNK_INV_PAR ,Buffer Invert Parity" "Not inverted,Inverted" bitfld.long 0x04 12.--15. " BUS_PAR_DIS ,Disable Bus Parity" "Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled" textline " " bitfld.long 0x04 9.--11. " PAR_OVR_KEY ,Parity Override" "DEVCR1,DEVCR1,DEVCR1,DEVCR1,DEVCR1,ADD_INV_PAR and DAT_INV_PAR active,DEVCR1,DEVCR1" bitfld.long 0x04 8. " ADD_INV_PAR ,Address Odd Parity" "Not inverted,Inverted" textline " " bitfld.long 0x04 7. " DAT_INV_PAR[7] ,Data Odd Parity bit 7" "Not inverted,Inverted" bitfld.long 0x04 6. " DAT_INV_PAR[6] ,Data Odd Parity bit 6" "Not inverted,Inverted" textline " " bitfld.long 0x04 5. " DAT_INV_PAR[5] ,Data Odd Parity bit 5" "Not inverted,Inverted" bitfld.long 0x04 4. " DAT_INV_PAR[4] ,Data Odd Parity bit 4" "Not inverted,Inverted" textline " " bitfld.long 0x04 3. " DAT_INV_PAR[3] ,Data Odd Parity bit 3" "Not inverted,Inverted" bitfld.long 0x04 2. " DAT_INV_PAR[2] ,Data Odd Parity bit 2" "Not inverted,Inverted" textline " " bitfld.long 0x04 1. " DAT_INV_PAR[1] ,Data Odd Parity bit 1" "Not inverted,Inverted" bitfld.long 0x04 0. " DAT_INV_PAR[0] ,Data Odd Parity bit 0" "Not inverted,Inverted" group.long 0xC0++0x03 line.long 0x00 "FEDACSDIS2,Flash Error Detection and Correction Sector Disable Register" bitfld.long 0x00 29.--31. " BANKID3_INVERSE ,The bank ID inverse bits are used with the bank ID bits to select the bank for which a sector is disabled" "ECC checking disabled,No sector is disabled,No sector is disabled,No sector is disabled,No sector is disabled,No sector is disabled,No sector is disabled,No sector is disabled" bitfld.long 0x00 24.--27. " SECTORID3_INVERSE ,The sector ID inverse bits are used with the sector ID bits to determine which sector is disabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21.--23. " BANKID3 ,The bank ID bits are used with the bank ID inverse bits to select the bank for which a sector is disabled" "ECC checking disabled,No sector is disabled,No sector is disabled,No sector is disabled,No sector is disabled,No sector is disabled,No sector is disabled,No sector is disabled" bitfld.long 0x00 16.--19. " SECTORID3 ,The sector ID bits are used with the sector ID inverse bits to determine which sector is disabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 13.--15. " BANKID2_INVERSE ,The bank ID inverse bits are used with the bank ID bits to select the bank for which a sector is disabled" "ECC checking disabled,No sector is disabled,No sector is disabled,No sector is disabled,No sector is disabled,No sector is disabled,No sector is disabled,No sector is disabled" bitfld.long 0x00 8.--11. " SECTORID2_INVERSE ,The sector ID inverse bits are used with the sector ID bits to determine which sector is disabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 5.--8. " SECTORID2 ,The sector ID bits are used with the sector ID inverse bits to determine which sector is disabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,%d..." bitfld.long 0x00 0.--3. " BANKID2 ,The bank ID bits are used with the bank ID inverse bits to select the bank for which a sector is disabled" "ECC checking disabled,No sector is disabled,No sector is disabled,No sector is disabled,No sector is disabled,No sector is disabled,No sector is disabled,No sector is disabled,?..." group.long 0x288++0x3 line.long 0x00 "FSM_WR_ENA,FSM Register Write Enable" bitfld.long 0x00 0.--2. " WR_ENA ,FSM Write Enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled" group.long 0x2A4++0x03 line.long 0x00 "FSM_WR_ENA,FSM Sector Register" bitfld.long 0x00 31. " SECT_ERASED[15] ,Sectors 15 Erased" "Erased,Not erased" bitfld.long 0x00 30. " SECT_ERASED[14] ,Sectors 14 Erased" "Erased,Not erased" textline " " bitfld.long 0x00 29. " SECT_ERASED[13] ,Sectors 13 Erased" "Erased,Not erased" bitfld.long 0x00 28. " SECT_ERASED[12] ,Sectors 12 Erased" "Erased,Not erased" textline " " bitfld.long 0x00 27. " SECT_ERASED[11] ,Sectors 11 Erased" "Erased,Not erased" bitfld.long 0x00 26. " SECT_ERASED[10] ,Sectors 10 Erased" "Erased,Not erased" textline " " bitfld.long 0x00 25. " SECT_ERASED[9] ,Sectors 9 Erased" "Erased,Not erased" bitfld.long 0x00 24. " SECT_ERASED[8] ,Sectors 8 Erased" "Erased,Not erased" textline " " bitfld.long 0x00 23. " SECT_ERASED[7] ,Sectors 7 Erased" "Erased,Not erased" bitfld.long 0x00 22. " SECT_ERASED[6] ,Sectors 6 Erased" "Erased,Not erased" textline " " bitfld.long 0x00 21. " SECT_ERASED[5] ,Sectors 5 Erased" "Erased,Not erased" bitfld.long 0x00 20. " SECT_ERASED[4] ,Sectors 4 Erased" "Erased,Not erased" textline " " bitfld.long 0x00 19. " SECT_ERASED[3] ,Sectors 3 Erased" "Erased,Not erased" bitfld.long 0x00 18. " SECT_ERASED[2] ,Sectors 2 Erased" "Erased,Not erased" textline " " bitfld.long 0x00 17. " SECT_ERASED[1] ,Sectors 1 Erased" "Erased,Not erased" bitfld.long 0x00 16. " SECT_ERASED[0] ,Sectors 0 Erased" "Erased,Not erased" group.long 0x2B8++0x3 line.long 0x00 "EEPROM_CONFIG,EEPROM Emulation configuration Register" bitfld.long 0x00 16.--19. " EWAIT ,EEPROM Wait state Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " AUTOSUSP_EN ,Auto Suspend Enable" "Disabled,Enabled" textline " " hexmask.long.byte 0x00 0.--7. 1. " AUTOSTART_GRACE ,Auto-suspend Startup Grace Period" group.long 0x308++0x13 line.long 0x00 "EE_CTRL1,EEPROM Emulation Error Detection and Correction Control Register 1" bitfld.long 0x00 16.--19. " EE_EDACMODE ,Error Correction Mode" "Corrected&Detected,Corrected&Detected,Corrected&Detected,Corrected&Detected,Corrected&Detected,Detected only,Corrected&Detected,Corrected&Detected,Corrected&Detected,Corrected&Detected,Corrected&Detected,Corrected&Detected,Corrected&Detected,Corrected&Detected,Corrected&Detected,Corrected&Detected" bitfld.long 0x00 10. " EE_EOFEN ,EEPROM Emulation Event on a correctable One's Fail Enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EE_EZFEN ,EEPROM Emulation Event on a correctable Zero's Fail Enable bit" "Disabled,Enabled" bitfld.long 0x00 8. " EE_EPEN ,EEPROM Emulation Error Profiling Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EE_ALL1_OK ,EEPROM Emulation All One Condition Valid" "Disabled,Enabled" bitfld.long 0x00 4. " EE_ALL0_OK ,EEPROM Emulation All Zero Condition Valid" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--3. " EE_EDACEN ,EEPROM Emulation Error Detection and Correction Enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" line.long 0x04 "EE_CTRL2,EEPROM Emulation Error Correction and Correction Control Register 2" hexmask.long.word 0x04 0.--15. 1. " EE_SEC_THRESHOLD ,EEPROM Emulation Single Error Correction Threshold" line.long 0x08 "EE_COR_ERR_CNT,EEPROM Emulation Correctable Error Count Register" hexmask.long.word 0x08 0.--15. 1. " EE_ERRCNT ,Single Error Correction Count" line.long 0x0C "EE_COR_ERR_ADD,EEPROM Emulation Correctable Error Address Register" hexmask.long 0x0C 3.--31. 0x8 " COR_ERR_ADD ,Correctable Error Address" bitfld.long 0x0C 0.--2. " B_OFF ,Byte offset" "0,1,2,3,4,5,6,7" line.long 0x10 "EE_COR_ERR_POS,EEPROM Emulation Correctable Error Position Register" bitfld.long 0x10 8. " TYPE ,ErrorType" "One of the 64 data bits,One of the 8 check bits" hexmask.long.byte 0x10 0.--7. 1. " EE_ERR_POS ,The bit address of the single bit error" group.long 0x31C++0x03 line.long 0x00 "EE_STATUS,EEPROM Emulation Error Status Register" eventfld.long 0x00 12. " EE_D_UNC_ERR ,Diagnostic Mode Uncorrectable Error Status Flag" "No error,Error" eventfld.long 0x00 8. " EE_UNC_ERR ,EEPROM Emulation Uncorrectable Error Flag" "No error,Error" textline " " bitfld.long 0x00 6. " EE_CMG ,EEPROM Emulation Compare Malfunction Good" "No error,Error" bitfld.long 0x00 4. " EE_CME ,EE_CME" "0,1" textline " " eventfld.long 0x00 3. " EE_D_COR_ERR ,Diagnostic Correctable Error Flag" "No error,Error" eventfld.long 0x00 2. " EE_ERR_ONE_FLG ,Error on One Fail Error Flag" "No error,Error" textline " " eventfld.long 0x00 1. " EE_ERR_ZERO_FLG ,Error on Zero Fail Error Flag" "No error,Error" eventfld.long 0x00 0. " EE_ERR_PRF_FLG ,Error Profiling Error Flag" "No error,Error" rgroup.long 0x320++0x03 line.long 0x00 "EE_UNC_ERR_ADD,EEPROM Emulation Uncorrectable Error Address Register" hexmask.long 0x00 3.--31. 0x8 " UNC_ERR_ADD ,Uncorrectable Error Address" bitfld.long 0x00 0.--2. " B_OFF ,Byte offset" "0,1,2,3,4,5,6,7" rgroup.long 0x400++0x03 line.long 0x00 "FCFG_BANK,Flash Bank Configuration Register" hexmask.long.word 0x00 20.--31. 1. " EE_BANK_WIDTH ,Bank 7 width (72 bits wide)" hexmask.long.word 0x00 4.--15. 1. " MAIN_BANK_WIDTH ,Width of main flash banks (144 bits wide)" width 0xb tree.end else tree "F021 Flash Module" base ad:0xFFF87000 width 15. group.long 0x00++0x3 line.long 0x0 "FRDCNTL,Read Control Register" bitfld.long 0x00 8.--11. " RWAIT ,Random Read Wait State" "0 cycles,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles" bitfld.long 0x00 4. " ASWSTEN ,Address Setup Wait State Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " ENPIPE ,Enable Pipeline Mode" "Disabled,Enabled" group.long 0x08++0x7 line.long 0x0 "FEDACCTRL1,Error Correction Control Register1" bitfld.long 0x00 24. " SUSP_IGNR ,Suspend Ignore" "Not ignored,Ignored" bitfld.long 0x00 16.--19. " EDACMODE ,Error Correction Mode" "Correction mode,Correction mode,Correction mode,Correction mode,Correction mode,Detection mode,Correction mode,Correction mode,Correction mode,Correction mode,Correction mode,Correction mode,Correction mode,Correction mode,Correction mode,Correction mode" textline " " bitfld.long 0x00 9. " EZFEN ,Error on Zero Fail Enable" "Disabled,Enabled" bitfld.long 0x00 8. " EPEN ,Error Profiling Enable" "Disabled,Enabled" bitfld.long 0x00 0.--3. " EDACEN ,Error Detection and Correction Enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" line.long 0x4 "FEDACCTRL2,Error Correction Control Register2" hexmask.long.word 0x04 0.--15. 1. " SEC_THRESHOLD ,Single Error Correction Threshold" rgroup.long 0x20++0x3 line.long 0x0 "FUNC_ERR_ADD,Un-correctable Error Address" hexmask.long 0x00 3.--31. 0x8 " UNC_ERR_ADD ,Un-correctable Error Address" bitfld.long 0x00 0.--2. " WORD_OFFSET ,Last 3 digit of the address" "000,001,010,011,100,101,110,111" group.long 0x30++0x7 line.long 0x0 "FBPROT,Bank Protection Register" bitfld.long 0x00 0. " PROTL1DIS ,Level 1 Protection Disable" "No,Yes" line.long 0x4 "FBSE,Bank Sector Enable Register" bitfld.long 0x04 15. " BSE[15] ,Bank Sector Enable 15" "Disabled,Enabled" bitfld.long 0x04 14. " BSE[14] ,Bank Sector Enable 14" "Disabled,Enabled" bitfld.long 0x04 13. " BSE[13] ,Bank Sector Enable 13" "Disabled,Enabled" textline " " bitfld.long 0x04 12. " BSE[12] ,Bank Sector Enable 12" "Disabled,Enabled" bitfld.long 0x04 11. " BSE[11] ,Bank Sector Enable 11" "Disabled,Enabled" bitfld.long 0x04 10. " BSE[10] ,Bank Sector Enable 10" "Disabled,Enabled" textline " " bitfld.long 0x04 9. " BSE[9] ,Bank Sector Enable 9" "Disabled,Enabled" bitfld.long 0x04 8. " BSE[8] ,Bank Sector Enable 8" "Disabled,Enabled" bitfld.long 0x04 7. " BSE[7] ,Bank Sector Enable 7" "Disabled,Enabled" textline " " bitfld.long 0x04 6. " BSE[6] ,Bank Sector Enable 6" "Disabled,Enabled" bitfld.long 0x04 5. " BSE[5] ,Bank Sector Enable 5" "Disabled,Enabled" bitfld.long 0x04 4. " BSE[4] ,Bank Sector Enable 4" "Disabled,Enabled" textline " " bitfld.long 0x04 3. " BSE[3] ,Bank Sector Enable 3" "Disabled,Enabled" bitfld.long 0x04 2. " BSE[2] ,Bank Sector Enable 2" "Disabled,Enabled" bitfld.long 0x04 1. " BSE[1] ,Bank Sector Enable 1" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " BSE[0] ,Bank Sector Enable 0" "Disabled,Enabled" group.long 0x3C++0x7 line.long 0x0 "FBAC,Bank Access Control Register" bitfld.long 0x00 23. " OTPPROTDIS[7] ,OTP Sector Protection Disable 7" "Disabled,Enabled" bitfld.long 0x00 22. " OTPPROTDIS[6] ,OTP Sector Protection Disable 6" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " OTPPROTDIS[5] ,OTP Sector Protection Disable 5" "Disabled,Enabled" bitfld.long 0x00 20. " OTPPROTDIS[4] ,OTP Sector Protection Disable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " OTPPROTDIS[3] ,OTP Sector Protection Disable 3" "Disabled,Enabled" bitfld.long 0x00 18. " OTPPROTDIS[2] ,OTP Sector Protection Disable 2" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " OTPPROTDIS[1] ,OTP Sector Protection Disable 1" "Disabled,Enabled" bitfld.long 0x00 16. " OTPPROTDIS[0] ,OTP Sector Protection Disable 0" "Disabled,Enabled" textline " " hexmask.long.byte 0x00 8.--15. 1. " BAGP[7:0] ,Bank Active Grace Period" hexmask.long.byte 0x00 0.--7. 1. " VREADST[7:0] ,VREAD Setup" line.long 0x4 "FBFALLBACK,Bank Fallback Power Register" bitfld.long 0x04 6.--7. " BANKPWR3[1:0] ,Bank 3 Fallback Power Mode" "Sleep,Standby,Reserved,Active" bitfld.long 0x04 4.--5. " BANKPWR2[1:0] ,Bank 2 Fallback Power Mode" "Sleep,Standby,Reserved,Active" textline " " bitfld.long 0x04 2.--3. " BANKPWR1[1:0] ,Bank 1 Fallback Power Mode" "Sleep,Standby,Reserved,Active" bitfld.long 0x04 0.--1. " BANKPWR0[1:0] ,Bank 0 Fallback Power Mode" "Sleep,Standby,Reserved,Active" group.long 0x48++0xb line.long 0x0 "FPAC1,Pump Access Control Register 1" hexmask.long.word 0x00 16.--26. 1. " PSLEEP[10:0] ,Pump Sleep" bitfld.long 0x00 0. " PUMPPWR ,Flash Charge Pump Fallback Power Mode" "Sleep,Active" line.long 0x4 "FPAC2,Pump Access Control Register 2" hexmask.long.word 0x4 0.--15. 1. " PAGP[15:0] ,Pump Active Grace Period" line.long 0x8 "FMAC,Module Access Control Register" bitfld.long 0x8 0.--2. " BANK[2:0] ,Bank Enable" "Bank 0,Bank 1,Bank 2,Bank 3,Bank 4,Bank 5,Bank 6,Bank 7" rgroup.long 0x54++0x3 line.long 0x00 "FMSTAT,Flash Module Status Register" bitfld.long 0x00 17. " RVSUSP ,Read Verify Suspend" "Not detected,Detected" bitfld.long 0x00 16. " RVDER ,Read verify command currently underway" "Not detected,Detected" bitfld.long 0x00 15. " RVF ,Read Verify Failure" "Not detected,Detected" textline " " bitfld.long 0x00 14. " ILA ,Illegal Address" "Not detected,Detected" bitfld.long 0x00 13. " DBT ,Disturbance Test Fail" "Not detected,Detected" bitfld.long 0x00 12. " PGV ,Program Verify" "Not detected,Detected" textline " " bitfld.long 0x00 11. " PCV ,Precondition Verify" "Not detected,Detected" bitfld.long 0x00 10. " EV ,Erase Verify" "Not detected,Detected" bitfld.long 0x00 9. " CV ,Compact Verify" "Not detected,Detected" textline " " bitfld.long 0x00 8. " BUSY ,Busy" "Idle,Busy" bitfld.long 0x00 7. " ERS ,Erase Active" "Not detected,Detected" bitfld.long 0x00 6. " PGM ,Program Active" "Not detected,Detected" textline " " bitfld.long 0x00 5. " INVDAT ,Invalid Data" "Not detected,Detected" bitfld.long 0x00 4. " CSTAT ,Command Status" "No effect,Stopped" bitfld.long 0x00 3. " VOLTSTAT ,Core Voltage Status" "0,1" textline " " bitfld.long 0x00 2. " ESUSP ,Erase Suspended" "Not suspended,Suspended" bitfld.long 0x00 1. " PSUSP ,Program Suspended" "Not suspended ,Suspended " bitfld.long 0x00 0. " SLOCK ,Sector Lock Status" "Not locked,Locked" group.long 0x288++0x3 line.long 0x00 "FSM_WR_ENA,FSM Register Write Enable" bitfld.long 0x00 0.--2. " WR_ENA ,FSM Write Enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled" group.long 0x2B8++0x3 line.long 0x00 "EEPROM_CONFIG,EEPROM Emulation configuration Register" bitfld.long 0x00 16.--19. " EWAIT ,EEPROM Wait state Counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8. " AUTOSUSP_EN ,Auto Suspend Enable" "Disabled,Enabled" textline " " hexmask.long.byte 0x00 0.--7. 1. " AUTOSTART_GRACE ,Auto-suspend Startup Grace Period" width 0xb tree.end endif tree "TCRAM (Tightly-Coupled RAM Module)" tree "RAM ECC 0" base ad:0xFFFFF800 width 22. group.long 0x00++0x13 line.long 0x00 "RAMCTRL,TCRAM Module Control Register" bitfld.long 0x00 30. " EMU_TRACE_DIS ,Emulation mode trace disable" "No,Yes" bitfld.long 0x00 24.--27. " ADDR_PARITY_OVERRIDE ,Address parity override" "Same,Same,Same,Same,Same,Same,Same,Same,Same,Same,Same,Same,Same,Opposite,Same,Same" newline bitfld.long 0x00 16.--19. " ADDR_PARITY_DISABLE ,Address parity detect disable" "No,No,No,No,No,No,No,No,No,No,Yes,No,No,No,No,No" bitfld.long 0x00 8. " ECC_WR_EN ,ECC memory write enable" "Disabled,Enabled" newline bitfld.long 0x00 0.--3. " ECC_DETECT_EN ,ECC detect enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" line.long 0x04 "RAMTHRESHOLD,TCRAM Module Single-Bit Error Correction Threshold Register" hexmask.long.word 0x04 0.--15. 1. " THRESHOLD ,Single-bit error threshold count" line.long 0x08 "RAMOCCUR,TCRAM Module Single-Bit Error Occurrences Counter Register" hexmask.long.word 0x08 0.--15. 1. " SINGLE_ERROR_OCCURRENCES ,Single-bit error correction occurrences" line.long 0x0C "RAMINTCTRL,TCRAM Module Interrupt Control Register" bitfld.long 0x0C 0. " SERR_EN ,Single-bit error correction interrupt enable" "Disabled,Enabled" line.long 0x10 "RAMERRSTATUS,TCRAM Module Error Status Register" eventfld.long 0x10 9. " WADDR_PAR_FAIL ,Write address parity failure" "Not failed,Failed" eventfld.long 0x10 8. " RADDR_PAR_FAIL ,Read address parity failure" "Not failed,Failed" newline eventfld.long 0x10 5. " DERR ,Multi-event error detected by the Cortex-R4F SECDED logic" "No error,Error" eventfld.long 0x10 4. " ADDR_COMP_LOGIC_FAIL ,Address decode logic element failed" "Not failed,Failed" newline eventfld.long 0x10 2. " ADDR_DEC_FAIL ,Address decode failed" "Not failed,Failed" eventfld.long 0x10 0. " SERR ,Single error status" "No error,Error" sif (cpu()!="TMS570LS3137-EP") rgroup.long 0x14++0x07 line.long 0x00 "RAMSERRADDR,TCRAM Module Single-Bit Error Address Register" hexmask.long.word 0x00 3.--17. 0x08 " SINGLE_ERROR_ADDRESS ,Cortex-R4F CPU detects ADDRESS a single-bit error" line.long 0x04 "RAMUERRADDR,TCRAM Module Uncorrectable Error Address Register" hexmask.long.tbyte 0x04 3.--22. 0x08 " UNCORRECTABLE_ERROR_ADDRESS ,Address for which there was an uncorrectable error or an address error" else rgroup.long 0x14++0x03 line.long 0x00 "RAMSERRADDR,TCRAM Module Single-Bit Error Address Register" hexmask.long.tbyte 0x00 3.--17. 0x08 " SINGLE_ERROR_ADDRESS ,Address for which the Cortex-R4F CPU detects a single-bit error" rgroup.long 0x1C++0x03 line.long 0x00 "RAMUERRADDR,TCRAM Module Uncorrectable Error Address Register" hexmask.long.tbyte 0x00 3.--22. 0x08 " UNCORRECTABLE_ERROR_ADDRESS ,Address for which there was an uncorrectable error or an address error" endif group.long 0x30++0x03 line.long 0x00 "RAMTEST,TCRAM Module Test Mode Control Register" bitfld.long 0x00 8. " TRIGGER ,Test trigger" "Low,High" sif (cpu()!="TMS570LS3137-EP") bitfld.long 0x00 6.--7. " TEST_MODE ,Test mode" "Reserved,Inequality check,Equality check,?..." newline bitfld.long 0x00 0.--3. " TEST_ENABLE ,Test enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" else bitfld.long 0x00 6.--7. " TEST_MODE ,Test mode" ",Inequality check,Equality check,?..." newline bitfld.long 0x00 0.--3. " TEST_ENABLE ,Test enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" endif group.long 0x38++0x03 line.long 0x00 "RAMADDRDECVECT,TCRAM Module Test Mode Vector Register" bitfld.long 0x00 26. " ECC_SELECT ,ECC select" "0,1" hexmask.long.word 0x00 0.--15. 1. " RAM_CHIP_SELECT ,RAM chip select" rgroup.long 0x3C++0x03 line.long 0x00 "RAMPERRADDR,TCRAM Module Parity Error Address Register" hexmask.long.tbyte 0x00 3.--22. 0x08 " ADDRESS_PARITY_ERROR_ADDRESS ,Parity error address" sif (cpu()=="TMS570LS3137-EP") group.long 0x40++0x03 line.long 0x00 "INIT_DOMAIN,Auto-Memory Initialization Enable Register" bitfld.long 0x00 7. " AUTO_MEM_INIT_ENABLE[7] ,Auto-memory initialization for power domain 7 enable" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Auto-memory initialization for power domain 6 enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " [5] ,Auto-memory initialization for power domain 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Auto-memory initialization for power domain 4 enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Auto-memory initialization for power domain 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Auto-memory initialization for power domain 2 enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,Auto-memory initialization for power domain 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Auto-memory initialization for power domain 0 enable" "Disabled,Enabled" endif width 0x0B tree.end tree "RAM ECC 1" base ad:0xFFFFF900 width 22. group.long 0x00++0x13 line.long 0x00 "RAMCTRL,TCRAM Module Control Register" bitfld.long 0x00 30. " EMU_TRACE_DIS ,Emulation mode trace disable" "No,Yes" bitfld.long 0x00 24.--27. " ADDR_PARITY_OVERRIDE ,Address parity override" "Same,Same,Same,Same,Same,Same,Same,Same,Same,Same,Same,Same,Same,Opposite,Same,Same" newline bitfld.long 0x00 16.--19. " ADDR_PARITY_DISABLE ,Address parity detect disable" "No,No,No,No,No,No,No,No,No,No,Yes,No,No,No,No,No" bitfld.long 0x00 8. " ECC_WR_EN ,ECC memory write enable" "Disabled,Enabled" newline bitfld.long 0x00 0.--3. " ECC_DETECT_EN ,ECC detect enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" line.long 0x04 "RAMTHRESHOLD,TCRAM Module Single-Bit Error Correction Threshold Register" hexmask.long.word 0x04 0.--15. 1. " THRESHOLD ,Single-bit error threshold count" line.long 0x08 "RAMOCCUR,TCRAM Module Single-Bit Error Occurrences Counter Register" hexmask.long.word 0x08 0.--15. 1. " SINGLE_ERROR_OCCURRENCES ,Single-bit error correction occurrences" line.long 0x0C "RAMINTCTRL,TCRAM Module Interrupt Control Register" bitfld.long 0x0C 0. " SERR_EN ,Single-bit error correction interrupt enable" "Disabled,Enabled" line.long 0x10 "RAMERRSTATUS,TCRAM Module Error Status Register" eventfld.long 0x10 9. " WADDR_PAR_FAIL ,Write address parity failure" "Not failed,Failed" eventfld.long 0x10 8. " RADDR_PAR_FAIL ,Read address parity failure" "Not failed,Failed" newline eventfld.long 0x10 5. " DERR ,Multi-event error detected by the Cortex-R4F SECDED logic" "No error,Error" eventfld.long 0x10 4. " ADDR_COMP_LOGIC_FAIL ,Address decode logic element failed" "Not failed,Failed" newline eventfld.long 0x10 2. " ADDR_DEC_FAIL ,Address decode failed" "Not failed,Failed" eventfld.long 0x10 0. " SERR ,Single error status" "No error,Error" sif (cpu()!="TMS570LS3137-EP") rgroup.long 0x14++0x07 line.long 0x00 "RAMSERRADDR,TCRAM Module Single-Bit Error Address Register" hexmask.long.word 0x00 3.--17. 0x08 " SINGLE_ERROR_ADDRESS ,Cortex-R4F CPU detects ADDRESS a single-bit error" line.long 0x04 "RAMUERRADDR,TCRAM Module Uncorrectable Error Address Register" hexmask.long.tbyte 0x04 3.--22. 0x08 " UNCORRECTABLE_ERROR_ADDRESS ,Address for which there was an uncorrectable error or an address error" else rgroup.long 0x14++0x03 line.long 0x00 "RAMSERRADDR,TCRAM Module Single-Bit Error Address Register" hexmask.long.tbyte 0x00 3.--17. 0x08 " SINGLE_ERROR_ADDRESS ,Address for which the Cortex-R4F CPU detects a single-bit error" rgroup.long 0x1C++0x03 line.long 0x00 "RAMUERRADDR,TCRAM Module Uncorrectable Error Address Register" hexmask.long.tbyte 0x00 3.--22. 0x08 " UNCORRECTABLE_ERROR_ADDRESS ,Address for which there was an uncorrectable error or an address error" endif group.long 0x30++0x03 line.long 0x00 "RAMTEST,TCRAM Module Test Mode Control Register" bitfld.long 0x00 8. " TRIGGER ,Test trigger" "Low,High" sif (cpu()!="TMS570LS3137-EP") bitfld.long 0x00 6.--7. " TEST_MODE ,Test mode" "Reserved,Inequality check,Equality check,?..." newline bitfld.long 0x00 0.--3. " TEST_ENABLE ,Test enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" else bitfld.long 0x00 6.--7. " TEST_MODE ,Test mode" ",Inequality check,Equality check,?..." newline bitfld.long 0x00 0.--3. " TEST_ENABLE ,Test enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" endif group.long 0x38++0x03 line.long 0x00 "RAMADDRDECVECT,TCRAM Module Test Mode Vector Register" bitfld.long 0x00 26. " ECC_SELECT ,ECC select" "0,1" hexmask.long.word 0x00 0.--15. 1. " RAM_CHIP_SELECT ,RAM chip select" rgroup.long 0x3C++0x03 line.long 0x00 "RAMPERRADDR,TCRAM Module Parity Error Address Register" hexmask.long.tbyte 0x00 3.--22. 0x08 " ADDRESS_PARITY_ERROR_ADDRESS ,Parity error address" sif (cpu()=="TMS570LS3137-EP") group.long 0x40++0x03 line.long 0x00 "INIT_DOMAIN,Auto-Memory Initialization Enable Register" bitfld.long 0x00 7. " AUTO_MEM_INIT_ENABLE[7] ,Auto-memory initialization for power domain 7 enable" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Auto-memory initialization for power domain 6 enable" "Disabled,Enabled" newline bitfld.long 0x00 5. " [5] ,Auto-memory initialization for power domain 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Auto-memory initialization for power domain 4 enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " [3] ,Auto-memory initialization for power domain 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Auto-memory initialization for power domain 2 enable" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,Auto-memory initialization for power domain 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Auto-memory initialization for power domain 0 enable" "Disabled,Enabled" endif width 0x0B tree.end tree.end sif (cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE") tree "PBIST (Programmable Built-In Self-Test)" base ad:0xFFFFE400 width 9. group.long 0x160++0x07 line.long 0x00 "RAMT,RAM Configuration Register" hexmask.long.byte 0x00 24.--31. 1. " RGS ,Ram Group Select" hexmask.long.byte 0x00 16.--23. 1. " RDS ,Return Data Select" textline " " hexmask.long.byte 0x00 8.--15. 1. " DWR ,Data Width Register" bitfld.long 0x00 6.--7. " SMS ,Sense Margin Select Register" "0,1,2,3" textline " " bitfld.long 0x00 2.--5. " PLS ,Pipeline Latency Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. " RLS ,RAM Latency Select" "0,1,2,3" line.long 0x04 "DLR,Datalogger Register" bitfld.long 0x04 4. " DLR4 ,Config access" "No,Yes" bitfld.long 0x04 2. " DLR2 ,ROM-based testing" "No,Yes" group.long 0x180++0x0B line.long 0x00 "PACT,PBIST Activate/ROM Clock Enable Register" bitfld.long 0x00 1. " PACT1 ,PBIST Activate" "Not activated,Activated" bitfld.long 0x00 0. " PACT0 ,ROM Clock Enable Register" "Disabled,Enabled" line.long 0x04 "PBISTID,PBIST ID Register" hexmask.long.byte 0x04 0.--7. 1. " PBIST_ID ,Unique ID assigned to each PBIST controller in a device with multiple PBIST controllers" line.long 0x08 "OVER,Override Register" bitfld.long 0x08 0. " OVER0 ,RINFO Override Bit" "No overridden,Overridden" rgroup.long 0x190++0x1B line.long 0x00 "FSRF0,Fail Status Fail Register 0" bitfld.long 0x00 0. " FSRF0 ,Fail Status 0" "Not occurred,Occurred" line.long 0x04 "FSRF1,Fail Status Fail Register 1" bitfld.long 0x04 0. " FSRF1 ,Fail Status 1" "Not occurred,Occurred" line.long 0x08 "FSRC0,Fail Status Count 0 Register" hexmask.long.byte 0x08 0.--7. 1. " FSRC0 ,Fail Status Count 0 Register" line.long 0x0C "FSRC1,Fail Status Count 0 Register" hexmask.long.byte 0x0C 0.--7. 1. " FSRC1 ,Fail Status Count 1 Register" line.long 0x10 "FSRA0,Fail Status Address Registers" hexmask.long.word 0x10 0.--15. 1. " FSRA0 ,Fail Status Address 0" line.long 0x14 "FSRA1,Fail Status Address Registers" hexmask.long.word 0x14 0.--15. 1. " FSRA1 ,Fail Status Address 0" line.long 0x18 "FSRDL0,Fail Status Data Registers" group.long 0x1B0++0x03 line.long 0x00 "FSRDL1,Fail Status Data Register 1" group.long 0x1C0++0x03 line.long 0x00 "ROM,ROM Mask Register" bitfld.long 0x00 0.--1. " ROM ,ROM Mask" "No information,RAM Group,Algorithm,Algorithm & RAM" group.long 0x1C4++0x07 line.long 0x00 "ALGO,ROM Algorithm Mask Register" bitfld.long 0x00 31. " ALGO32 ,Algorithm powerup_invpowerup" "Not masked,Masked" bitfld.long 0x00 30. " ALGO31 ,Algorithm powerup_invpowerup" "Not masked,Masked" textline " " bitfld.long 0x00 29. " ALGO30 ,Algorithm iddqrowstripe" "Not masked,Masked" bitfld.long 0x00 28. " ALGO29 ,Algorithm iddqrowstripe" "Not masked,Masked" textline " " bitfld.long 0x00 27. " ALGO28 ,Algorithm iddqrowstripe" "Not masked,Masked" bitfld.long 0x00 26. " ALGO27 ,Algorithm iddqrowstripe" "Not masked,Masked" textline " " bitfld.long 0x00 25. " ALGO26 ,Algorithm retention" "Not masked,Masked" bitfld.long 0x00 24. " ALGO25 ,Algorithm retention" "Not masked,Masked" textline " " bitfld.long 0x00 23. " ALGO24 ,Algorithm iddq" "Not masked,Masked" bitfld.long 0x00 22. " ALGO23 ,Algorithm iddq" "Not masked,Masked" textline " " bitfld.long 0x00 21. " ALGO22 ,Algorithm retention" "Not masked,Masked" bitfld.long 0x00 20. " ALGO21 ,Algorithm retention" "Not masked,Masked" textline " " bitfld.long 0x00 19. " ALGO20 ,Algorithm iddq" "Not masked,Masked" bitfld.long 0x00 18. " ALGO19 ,Algorithm iddq" "Not masked,Masked" textline " " bitfld.long 0x00 17. " ALGO18 ,Algorithm flip10" "Not masked,Masked" bitfld.long 0x00 16. " ALGO17 ,Algorithm flip10" "Not masked,Masked" textline " " bitfld.long 0x00 15. " ALGO16 ,Algorithm pmos_open_slice2" "Not masked,Masked" bitfld.long 0x00 14. " ALGO15 ,Algorithm pmos_open_slice1" "Not masked,Masked" textline " " bitfld.long 0x00 13. " ALGO14 ,Algorithm pmos_open" "Not masked,Masked" bitfld.long 0x00 12. " ALGO13 ,Algorithm pmos_open" "Not masked,Masked" textline " " bitfld.long 0x00 11. " ALGO12 ,Algorithm dtxn2" "Not masked,Masked" bitfld.long 0x00 10. " ALGO11 ,Algorithm dtxn2" "Not masked,Masked" textline " " bitfld.long 0x00 9. " ALGO10 ,Algorithm precharge" "Not masked,Masked" bitfld.long 0x00 8. " ALGO9 ,Algorithm precharge" "Not masked,Masked" textline " " bitfld.long 0x00 7. " ALGO8 ,Algorithm mapcolumn" "Not masked,Masked" bitfld.long 0x00 6. " ALGO7 ,Algorithm mapcolumn" "Not masked,Masked" textline " " bitfld.long 0x00 5. " ALGO6 ,Algorithm down1A_red" "Not masked,Masked" bitfld.long 0x00 4. " ALGO5 ,Algorithm down1A_red" "Not masked,Masked" textline " " bitfld.long 0x00 3. " ALGO4 ,Algorithm march13n_red" "Not masked,Masked" bitfld.long 0x00 2. " ALGO3 ,Algorithm march13n_red" "Not masked,Masked" textline " " bitfld.long 0x00 1. " ALGO2 ,Algorithm triple_read_fast_read" "Not masked,Masked" bitfld.long 0x00 0. " ALGO1 ,Algorithm triple_read_slow_read" "Not masked,Masked" line.long 0x04 "RINFOL,RAM Info Mask Lower Register" sif (cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE"||cpu()=="RM46L852-PGE") bitfld.long 0x04 26. " RINFOL27 ,RAM Group USB" "Not masked,Masked" bitfld.long 0x04 25. " RINFOL26 ,RAM Group USB" "Not masked,Masked" textline " " endif sif (cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE") bitfld.long 0x04 24. " RINFOL25 ,RAM Group ETHERNET" "Not masked,Masked" bitfld.long 0x04 23. " RINFOL24 ,RAM Group ETHERNET" "Not masked,Masked" textline " " bitfld.long 0x04 22. " RINFOL23 ,RAM Group ETHERNET" "Not masked,Masked" textline " " endif bitfld.long 0x04 21. " RINFOL22 ,RAM Group ESRAM6" "Not masked,Masked" bitfld.long 0x04 20. " RINFOL21 ,RAM Group ESRAM5" "Not masked,Masked" textline " " bitfld.long 0x04 19. " RINFOL20 ,RAM Group HET TU2" "Not masked,Masked" bitfld.long 0x04 18. " RINFOL19 ,RAM Group N2HET2" "Not masked,Masked" textline " " bitfld.long 0x04 17. " RINFOL18 ,RAM Group MIBADC2" "Not masked,Masked" bitfld.long 0x04 13. " RINFOL14 ,RAM Group HET TU1" "Not masked,Masked" textline " " bitfld.long 0x04 12. " RINFOL13 ,RAM Group N2HET1" "Not masked,Masked" bitfld.long 0x04 11. " RINFOL12 ,RAM Group DMA" "Not masked,Masked" textline " " bitfld.long 0x04 10. " RINFOL11 ,RAM Group MibADC1" "Not masked,Masked" bitfld.long 0x04 9. " RINFOL10 ,RAM Group VIM" "Not masked,Masked" textline " " bitfld.long 0x04 8. " RINFOL9 ,RAM Group MIBSPI5" "Not masked,Masked" bitfld.long 0x04 7. " RINFOL8 ,RAM Group MIBSPI3" "Not masked,Masked" textline " " bitfld.long 0x04 6. " RINFOL7 ,RAM Group MIBSPI1" "Not masked,Masked" bitfld.long 0x04 5. " RINFOL6 ,RAM Group ESRAM1" "Not masked,Masked" textline " " bitfld.long 0x04 4. " RINFOL5 ,RAM Group DCAN3" "Not masked,Masked" bitfld.long 0x04 3. " RINFOL4 ,RAM Group DCAN2" "Not masked,Masked" textline " " bitfld.long 0x04 2. " RINFOL3 ,RAM Group DCAN1" "Not masked,Masked" bitfld.long 0x04 1. " RINFOL2 ,RAM Group STC ROM" "Not masked,Masked" textline " " bitfld.long 0x04 0. " RINFOL1 ,RAM Group PBIST ROM" "Not masked,Masked" hgroup.long 0x1CC++0x03 hide.long 0x00 "RINFOU,RAM Upper Mask Lower Register" width 11. tree.end elif (cpu()=="RM42L432") tree "PBIST (Programmable Built-In Self-Test)" base ad:0xFFFFE400 width 9. group.long 0x160++0x07 line.long 0x00 "RAMT,RAM Configuration Register" hexmask.long.byte 0x00 24.--31. 1. " RGS ,Ram Group Select" hexmask.long.byte 0x00 16.--23. 1. " RDS ,Return Data Select" textline " " hexmask.long.byte 0x00 8.--15. 1. " DWR ,Data Width Register" bitfld.long 0x00 6.--7. " SMS ,Sense Margin Select Register" "0,1,2,3" textline " " bitfld.long 0x00 2.--5. " PLS ,Pipeline Latency Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. " RLS ,RAM Latency Select" "0,1,2,3" line.long 0x04 "DLR,Datalogger Register" bitfld.long 0x04 4. " DLR4 ,Config access" "No,Yes" bitfld.long 0x04 2. " DLR2 ,ROM-based testing" "No,Yes" group.long 0x180++0x0B line.long 0x00 "PACT,PBIST Activate/ROM Clock Enable Register" bitfld.long 0x00 1. " PACT1 ,PBIST Activate" "Not activated,Activated" bitfld.long 0x00 0. " PACT0 ,ROM Clock Enable Register" "Disabled,Enabled" line.long 0x04 "PBISTID,PBIST ID Register" hexmask.long.byte 0x04 0.--7. 1. " PBIST_ID ,Unique ID assigned to each PBIST controller in a device with multiple PBIST controllers" line.long 0x08 "OVER,Override Register" bitfld.long 0x08 0. " OVER0 ,RINFO Override Bit" "No overridden,Overridden" rgroup.long 0x190++0x1B line.long 0x00 "FSRF0,Fail Status Fail Register 0" bitfld.long 0x00 0. " FSRF0 ,Fail Status 0" "Not occurred,Occurred" line.long 0x04 "FSRF1,Fail Status Fail Register 1" bitfld.long 0x04 0. " FSRF1 ,Fail Status 1" "Not occurred,Occurred" line.long 0x08 "FSRC0,Fail Status Count 0 Register" hexmask.long.byte 0x08 0.--7. 1. " FSRC0 ,Fail Status Count 0 Register" line.long 0x0C "FSRC1,Fail Status Count 0 Register" hexmask.long.byte 0x0C 0.--7. 1. " FSRC1 ,Fail Status Count 1 Register" line.long 0x10 "FSRA0,Fail Status Address Registers" hexmask.long.word 0x10 0.--15. 1. " FSRA0 ,Fail Status Address 0" line.long 0x14 "FSRA1,Fail Status Address Registers" hexmask.long.word 0x14 0.--15. 1. " FSRA1 ,Fail Status Address 0" line.long 0x18 "FSRDL0,Fail Status Data Registers" group.long 0x1B0++0x03 line.long 0x00 "FSRDL1,Fail Status Data Register 1" group.long 0x1C0++0x03 line.long 0x00 "ROM,ROM Mask Register" bitfld.long 0x00 0.--1. " ROM ,ROM Mask" "No information,RAM Group,Algorithm,Algorithm & RAM" group.long 0x1C4++0x07 line.long 0x00 "ALGO,ROM Algorithm Mask Register" bitfld.long 0x00 28. " ALGO32 ,Algorithm powerup_invpowerup" "Not masked,Masked" bitfld.long 0x00 30. " ALGO31 ,Algorithm powerup_invpowerup" "Not masked,Masked" textline " " bitfld.long 0x00 29. " ALGO30 ,Algorithm iddqrowstripe" "Not masked,Masked" bitfld.long 0x00 28. " ALGO29 ,Algorithm iddqrowstripe" "Not masked,Masked" textline " " bitfld.long 0x00 27. " ALGO28 ,Algorithm iddqrowstripe" "Not masked,Masked" bitfld.long 0x00 26. " ALGO27 ,Algorithm iddqrowstripe" "Not masked,Masked" textline " " bitfld.long 0x00 25. " ALGO26 ,Algorithm retention" "Not masked,Masked" bitfld.long 0x00 24. " ALGO25 ,Algorithm retention" "Not masked,Masked" textline " " bitfld.long 0x00 23. " ALGO24 ,Algorithm iddq" "Not masked,Masked" bitfld.long 0x00 22. " ALGO23 ,Algorithm iddq" "Not masked,Masked" textline " " bitfld.long 0x00 21. " ALGO22 ,Algorithm retention" "Not masked,Masked" bitfld.long 0x00 20. " ALGO21 ,Algorithm retention" "Not masked,Masked" textline " " bitfld.long 0x00 19. " ALGO20 ,Algorithm iddq" "Not masked,Masked" bitfld.long 0x00 18. " ALGO19 ,Algorithm iddq" "Not masked,Masked" textline " " bitfld.long 0x00 17. " ALGO18 ,Algorithm flip10" "Not masked,Masked" bitfld.long 0x00 16. " ALGO17 ,Algorithm flip10" "Not masked,Masked" textline " " bitfld.long 0x00 15. " ALGO16 ,Algorithm pmos_open_slice2" "Not masked,Masked" bitfld.long 0x00 14. " ALGO15 ,Algorithm pmos_open_slice1" "Not masked,Masked" textline " " bitfld.long 0x00 13. " ALGO14 ,Algorithm pmos_open" "Not masked,Masked" bitfld.long 0x00 12. " ALGO13 ,Algorithm pmos_open" "Not masked,Masked" textline " " bitfld.long 0x00 11. " ALGO12 ,Algorithm dtxn2" "Not masked,Masked" bitfld.long 0x00 10. " ALGO11 ,Algorithm dtxn2" "Not masked,Masked" textline " " bitfld.long 0x00 9. " ALGO10 ,Algorithm precharge" "Not masked,Masked" bitfld.long 0x00 8. " ALGO9 ,Algorithm precharge" "Not masked,Masked" textline " " bitfld.long 0x00 7. " ALGO8 ,Algorithm mapcolumn" "Not masked,Masked" bitfld.long 0x00 6. " ALGO7 ,Algorithm mapcolumn" "Not masked,Masked" textline " " bitfld.long 0x00 5. " ALGO6 ,Algorithm down1A_red" "Not masked,Masked" bitfld.long 0x00 4. " ALGO5 ,Algorithm down1A_red" "Not masked,Masked" textline " " bitfld.long 0x00 3. " ALGO4 ,Algorithm march13n_red" "Not masked,Masked" bitfld.long 0x00 2. " ALGO3 ,Algorithm march13n_red" "Not masked,Masked" textline " " bitfld.long 0x00 1. " ALGO2 ,Algorithm triple_read_fast_read" "Not masked,Masked" bitfld.long 0x00 0. " ALGO1 ,Algorithm triple_read_slow_read" "Not masked,Masked" line.long 0x04 "RINFOL,RAM Info Mask Lower Register" bitfld.long 0x04 13. " RINFOL14 ,RAM Group NET TU" "Not masked,Masked" bitfld.long 0x04 12. " RINFOL13 ,RAM Group N2HET" "Not masked,Masked" textline " " bitfld.long 0x04 10. " RINFOL11 ,RAM Group MIBADC" "Not masked,Masked" bitfld.long 0x04 9. " RINFOL10 ,RAM Group VIM" "Not masked,Masked" textline " " bitfld.long 0x04 6. " RINFOL7 ,RAM Group MIBSPI1" "Not masked,Masked" bitfld.long 0x04 5. " RINFOL6 ,RAM Group ESRAM1" "Not masked,Masked" textline " " bitfld.long 0x04 3. " RINFOL4 ,RAM Group DCAN2" "Not masked,Masked" bitfld.long 0x04 2. " RINFOL3 ,RAM Group DCAN1" "Not masked,Masked" textline " " bitfld.long 0x04 1. " RINFOL2 ,RAM Group STC ROM" "Not masked,Masked" bitfld.long 0x04 0. " RINFOL1 ,RAM Group PBIST ROM" "Not masked,Masked" hgroup.long 0x1CC++0x03 hide.long 0x00 "RINFOU,RAM Upper Mask Lower Register" width 11. tree.end else tree "PBIST (Programmable Built-In Self-Test)" base ad:0xFFFFE400 width 9. group.long 0x160++0x07 line.long 0x00 "RAMT,RAM Configuration Register" hexmask.long.byte 0x00 24.--31. 1. " RGS ,Ram Group Select" hexmask.long.byte 0x00 16.--23. 1. " RDS ,Return Data Select" textline " " hexmask.long.byte 0x00 8.--15. 1. " DWR ,Data Width Register" bitfld.long 0x00 6.--7. " SMS ,Sense Margin Select Register" "0,1,2,3" textline " " bitfld.long 0x00 2.--5. " PLS ,Pipeline Latency Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--1. " RLS ,RAM Latency Select" "0,1,2,3" line.long 0x04 "DLR,Datalogger Register" bitfld.long 0x04 4. " DLR4 ,Config access" "No,Yes" bitfld.long 0x04 2. " DLR2 ,ROM-based testing" "No,Yes" group.long 0x180++0x0B line.long 0x00 "PACT,PBIST Activate/ROM Clock Enable Register" bitfld.long 0x00 1. " PACT1 ,PBIST Activate" "Not activated,Activated" bitfld.long 0x00 0. " PACT0 ,ROM Clock Enable Register" "Disabled,Enabled" line.long 0x04 "PBISTID,PBIST ID Register" hexmask.long.byte 0x04 0.--7. 1. " PBIST_ID ,Unique ID assigned to each PBIST controller in a device with multiple PBIST controllers" line.long 0x08 "OVER,Override Register" bitfld.long 0x08 0. " OVER0 ,RINFO Override Bit" "No overridden,Overridden" rgroup.long 0x190++0x1B line.long 0x00 "FSRF0,Fail Status Fail Register 0" bitfld.long 0x00 0. " FSRF0 ,Fail Status 0" "Not occurred,Occurred" line.long 0x04 "FSRF1,Fail Status Fail Register 1" bitfld.long 0x04 0. " FSRF1 ,Fail Status 1" "Not occurred,Occurred" line.long 0x08 "FSRC0,Fail Status Count 0 Register" hexmask.long.byte 0x08 0.--7. 1. " FSRC0 ,Fail Status Count 0 Register" line.long 0x0C "FSRC1,Fail Status Count 0 Register" hexmask.long.byte 0x0C 0.--7. 1. " FSRC1 ,Fail Status Count 1 Register" line.long 0x10 "FSRA0,Fail Status Address Registers" hexmask.long.word 0x10 0.--15. 1. " FSRA0 ,Fail Status Address 0" line.long 0x14 "FSRA1,Fail Status Address Registers" hexmask.long.word 0x14 0.--15. 1. " FSRA1 ,Fail Status Address 0" line.long 0x18 "FSRDL0,Fail Status Data Registers" group.long 0x1B0++0x03 line.long 0x00 "FSRDL1,Fail Status Data Register 1" group.long 0x1C0++0x03 line.long 0x00 "ROM,ROM Mask Register" bitfld.long 0x00 0.--1. " ROM ,ROM Mask" "No information,RAM Group,Algorithm,Algorithm & RAM" group.long 0x1C4++0x07 line.long 0x00 "ALGO,ROM Algorithm Mask Register" bitfld.long 0x00 29. " ALGO30 ,Algorithm iddqrowstripe" "Not masked,Masked" bitfld.long 0x00 28. " ALGO29 ,Algorithm iddqrowstripe" "Not masked,Masked" textline " " bitfld.long 0x00 27. " ALGO28 ,Algorithm iddqrowstripe" "Not masked,Masked" bitfld.long 0x00 26. " ALGO27 ,Algorithm iddqrowstripe" "Not masked,Masked" textline " " bitfld.long 0x00 25. " ALGO26 ,Algorithm retention" "Not masked,Masked" bitfld.long 0x00 24. " ALGO25 ,Algorithm retention" "Not masked,Masked" textline " " bitfld.long 0x00 23. " ALGO24 ,Algorithm iddq" "Not masked,Masked" bitfld.long 0x00 22. " ALGO23 ,Algorithm iddq" "Not masked,Masked" textline " " bitfld.long 0x00 21. " ALGO22 ,Algorithm retention" "Not masked,Masked" bitfld.long 0x00 20. " ALGO21 ,Algorithm retention" "Not masked,Masked" textline " " bitfld.long 0x00 19. " ALGO20 ,Algorithm iddq" "Not masked,Masked" bitfld.long 0x00 18. " ALGO19 ,Algorithm iddq" "Not masked,Masked" textline " " bitfld.long 0x00 17. " ALGO18 ,Algorithm flip10" "Not masked,Masked" bitfld.long 0x00 16. " ALGO17 ,Algorithm flip10" "Not masked,Masked" textline " " bitfld.long 0x00 15. " ALGO16 ,Algorithm pmos_open_slice2" "Not masked,Masked" bitfld.long 0x00 14. " ALGO15 ,Algorithm pmos_open_slice1" "Not masked,Masked" textline " " bitfld.long 0x00 13. " ALGO14 ,Algorithm pmos_open" "Not masked,Masked" bitfld.long 0x00 12. " ALGO13 ,Algorithm pmos_open" "Not masked,Masked" textline " " bitfld.long 0x00 11. " ALGO12 ,Algorithm dtxn2" "Not masked,Masked" bitfld.long 0x00 10. " ALGO11 ,Algorithm dtxn2" "Not masked,Masked" textline " " bitfld.long 0x00 9. " ALGO10 ,Algorithm precharge" "Not masked,Masked" bitfld.long 0x00 8. " ALGO9 ,Algorithm precharge" "Not masked,Masked" textline " " bitfld.long 0x00 7. " ALGO8 ,Algorithm mapcolumn" "Not masked,Masked" bitfld.long 0x00 6. " ALGO7 ,Algorithm mapcolumn" "Not masked,Masked" textline " " bitfld.long 0x00 5. " ALGO6 ,Algorithm down1A_red" "Not masked,Masked" bitfld.long 0x00 4. " ALGO5 ,Algorithm down1A_red" "Not masked,Masked" textline " " bitfld.long 0x00 3. " ALGO4 ,Algorithm march13n_red" "Not masked,Masked" bitfld.long 0x00 2. " ALGO3 ,Algorithm march13n_red" "Not masked,Masked" textline " " bitfld.long 0x00 1. " ALGO2 ,Algorithm triple_read_fast_read" "Not masked,Masked" bitfld.long 0x00 0. " ALGO1 ,Algorithm triple_read_slow_read" "Not masked,Masked" line.long 0x04 "RINFOL,RAM Info Mask Lower Register" bitfld.long 0x04 27. " RINFOL28 ,RAM Group ESRAM8" "Not masked,Masked" sif (cpu()=="RM48L952-PGE"||cpu()=="RM48L952-ZWT"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE"||cpu()=="RM48L550-ZWT") textline " " bitfld.long 0x04 26. " RINFOL27 ,RAM Group USB" "Not masked,Masked" bitfld.long 0x04 25. " RINFOL26 ,RAM Group USB" "Not masked,Masked" endif sif (cpu()=="RM48L952-PGE"||cpu()=="RM48L952-ZWT"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L540-PGE"||cpu()=="RM48L550-ZWT") textline " " bitfld.long 0x04 24. " RINFOL25 ,RAM Group ETHERNET" "Not masked,Masked" bitfld.long 0x04 23. " RINFOL24 ,RAM Group ETHERNET" "Not masked,Masked" textline " " bitfld.long 0x04 22. " RINFOL23 ,RAM Group ETHERNET" "Not masked,Masked" endif textline " " bitfld.long 0x04 21. " RINFOL22 ,RAM Group ESRAM6" "Not masked,Masked" bitfld.long 0x04 20. " RINFOL21 ,RAM Group ESRAM5" "Not masked,Masked" textline " " bitfld.long 0x04 19. " RINFOL20 ,RAM Group HET TU2" "Not masked,Masked" bitfld.long 0x04 18. " RINFOL19 ,RAM Group N2HET2" "Not masked,Masked" textline " " bitfld.long 0x04 17. " RINFOL18 ,RAM Group MIBADC2" "Not masked,Masked" bitfld.long 0x04 14. " RINFOL15 ,RAM Group RTP" "Not masked,Masked" textline " " bitfld.long 0x04 13. " RINFOL14 ,RAM Group HET TU1" "Not masked,Masked" bitfld.long 0x04 12. " RINFOL13 ,RAM Group N2HET1" "Not masked,Masked" textline " " bitfld.long 0x04 11. " RINFOL12 ,RAM Group DMA" "Not masked,Masked" bitfld.long 0x04 10. " RINFOL11 ,RAM Group MibADC1" "Not masked,Masked" textline " " bitfld.long 0x04 9. " RINFOL10 ,RAM Group VIM" "Not masked,Masked" bitfld.long 0x04 8. " RINFOL9 ,RAM Group MIBSPI5" "Not masked,Masked" textline " " bitfld.long 0x04 7. " RINFOL8 ,RAM Group MIBSPI3" "Not masked,Masked" bitfld.long 0x04 6. " RINFOL7 ,RAM Group MIBSPI1" "Not masked,Masked" textline " " bitfld.long 0x04 5. " RINFOL6 ,RAM Group ESRAM1" "Not masked,Masked" bitfld.long 0x04 4. " RINFOL5 ,RAM Group DCAN3" "Not masked,Masked" textline " " bitfld.long 0x04 3. " RINFOL4 ,RAM Group DCAN2" "Not masked,Masked" bitfld.long 0x04 2. " RINFOL3 ,RAM Group DCAN1" "Not masked,Masked" textline " " bitfld.long 0x04 1. " RINFOL2 ,RAM Group STC ROM" "Not masked,Masked" bitfld.long 0x04 0. " RINFOL1 ,RAM Group PBIST ROM" "Not masked,Masked" hgroup.long 0x1CC++0x03 hide.long 0x00 "RINFOU,RAM Upper Mask Lower Register" width 11. tree.end endif tree "STC (Self-Test Controller)" base ad:0xFFFFE600 width 7. group.long 0x00++0x3 line.long 0x0 "GCR0,STC global control register0" hexmask.long.word 0x00 16.--31. 1. " INTCOUNT ,Number of intervals of selftest run" bitfld.long 0x00 0. " RS_CNT ,Restart or Continue" "Continue,Restart" group.long 0x04++0x3 line.long 0x0 "GCR1,STC Global Control Register1" bitfld.long 0x00 0.--3. " STC_ENA ,Self test run enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" group.long 0x08++0x3 line.long 0x0 "TPR,Self Test Run Timeout Counter Preload Register" rgroup.long 0x0C++0x3 line.long 0x0 "CADDR,Current ROM Address Register" rgroup.long 0x10++0x3 line.long 0x0 "CICR,Current Interval Count Register" hexmask.long.word 0x00 0.--15. 1. " N ,Interval Number" group.long 0x14++0x3 line.long 0x0 "GSTAT,SelfTest Global Status Register" bitfld.long 0x00 1. " TEST_FAIL ,Test Fail" "Not failed,Failed" bitfld.long 0x00 0. " TEST_DONE ,Test Done" "Not completed,Completed" group.long 0x18++0x3 line.long 0x0 "FSTAT,SelfTest Fail Status Register" bitfld.long 0x00 2. " TO_ERR ,Timeout Error" "No error,Error" bitfld.long 0x00 1. " CPU2_FAIL ,CPU2 failure info" "Not failed,Failed" bitfld.long 0x00 0. " CPU1_FAIL ,CPU1 failure info" "Not failed,Failed" width 15. sif (cpu()=="RM42L432") rgroup.long 0x2C++0x3 line.long 0x0 "CPU2_CURMISR3,Cpu 2 Current Misr Register" rgroup.long 0x30++0x3 line.long 0x0 "CPU2_CURMISR2,Cpu 2 Current Misr Register" rgroup.long 0x34++0x3 line.long 0x0 "CPU2_CURMISR1,Cpu 2 Current Misr Register" rgroup.long 0x38++0x3 line.long 0x0 "CPU2_CURMISR0,Cpu 2 Current Misr Register" group.long 0x3C++0x03 line.long 0x00 "STCSCSCR,Signature Compare Self Check Register" bitfld.long 0x00 4. " FAULT_INS ,Fault Insertion" "No fault,Fault" bitfld.long 0x00 0.--3. " SELF_CHECK_KEY ,Signature compare logic self-check key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" else rgroup.long 0x2C++0x3 line.long 0x0 "CPU1_CURMISR3,Cpu 1 Current Misr Register" rgroup.long 0x30++0x3 line.long 0x0 "CPU1_CURMISR2,Cpu 1 Current Misr Register" rgroup.long 0x34++0x3 line.long 0x0 "CPU1_CURMISR1,Cpu 1 Current Misr Register" rgroup.long 0x38++0x3 line.long 0x0 "CPU1_CURMISR0,Cpu 1 Current Misr Register" rgroup.long 0x3C++0x3 line.long 0x0 "CPU2_CURMISR3,Cpu 2 Current Misr Register" rgroup.long 0x40++0x3 line.long 0x0 "CPU2_CURMISR2,Cpu 2 Current Misr Register" rgroup.long 0x44++0x3 line.long 0x0 "CPU2_CURMISR1,Cpu 2 Current Misr Register" rgroup.long 0x48++0x3 line.long 0x0 "CPU2_CURMISR0,Cpu 2 Current Misr Register" endif width 11. tree.end tree "CCM-R4F (CPU Compare Module - CortexR4)" base ad:0xFFFFF600 width 9. group.long 0x00++0x07 line.long 0x00 "CCMSR,CCM-R4F Status Register" eventfld.long 0x00 16. " CMPE ,Compare error" "No error,Error" bitfld.long 0x00 8. " STC ,Self-test complete" "Not completed,Completed" bitfld.long 0x00 1. " STET ,Self test error type" "Compare match,Compare mismatch" bitfld.long 0x00 0. " STE ,Self-test error" "No error,Error" line.long 0x04 "CCMKEYR,CCM-R4F Key Register" bitfld.long 0x04 0.--3. " MKEY ,Mode key" "Lockstep,,,,,,Self-test,,,Error Forcing,,,,,,Self-test error forcing" width 0x0B tree.end sif (cpu()=="RM42L432") tree "Oscilator PLL and Clock Monitoring" base ad:0xFFFFFF70 width 0xb tree "PLL Module Registers" group.long 0x00++0x07 line.long 0x00 "PLLCTL1,PLL Control 1 Register" bitfld.long 0x00 31. " ROS ,Reset on PLL Slip" "No reset,Reset" bitfld.long 0x00 29.--30. " MASK_SLIP ,Mask detection of PLL slip" "Bypassed,Bypassed,No action,Bypassed" textline " " bitfld.long 0x00 24.--28. " PLLDIV ,PLL Output Clock Divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" bitfld.long 0x00 23. " ROF ,Reset on Oscillator Fail" "No reset,Reset" textline " " bitfld.long 0x00 16.--21. " REFCLKDIV ,Reference Clock Divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,/64" hexmask.long.word 0x00 0.--15. 1. " PLLMUL ,PLL Multiplication Factor" line.long 0x04 "PLLCTL2,PLL Control 2 Register" bitfld.long 0x04 31. " FMENA ,Frequency Modulation Enable" "Disabled,Enabled" hexmask.long.word 0x04 22.--30. 1. " SPREADINGRATE ,Spreading rate" textline " " hexmask.long.word 0x04 12.--20. 1. " MULMOD ,Multiplier Correction" bitfld.long 0x04 9.--11. " ODPLL ,Internal PLL Output Divider" "/1,/2,/3,/4,/5,/6,/7,/8" textline " " hexmask.long.word 0x04 0.--8. 1. " SPR_AMOUNT ,Spreading Amount" base ad:0xFFFFFF24 group.long 0x00++0x03 line.long 0x00 "SSWPLL1,PLL Modulation Depth Measurement Control Register" hexmask.long.byte 0x00 8.--15. 1. " CAPTURE_WINDOW_INDEX ,Capture counter present in the PLL wrapper" bitfld.long 0x00 6. " COUNTER_READ_READY ,Counter read ready" "Not ready,Ready" textline " " bitfld.long 0x00 5. " COUNTER_RESET ,Counter reset" "No reset,Reset" bitfld.long 0x00 4. " COUNTER_EN ,Counter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1.--3. " TAP_COUNTER_DIS ,Used to program a particular bit in CLKOUT counter" "Bit 16 selected,Bit 18 selected,Bit 20 selected,Bit 22 selected,Bit 24 selected,Bit 26 selected,Bit 28 selected,Bit 30 selected" bitfld.long 0x00 0. " EXT_COUNTER_EN ,Measurement mode select" "Modulation depth,Frequency" rgroup.long 0x04++0x07 line.long 0x00 "SSWPLL2,SSW PLL BIST Control Register 2" line.long 0x04 "SSWPLL3,SSW PLL BIST Control Register 3" tree.end tree "LPOCLKDET Module Registers" base ad:0xFFFFFF88 group.long 0x00++0x07 line.long 0x00 "LPOMONCTL,LPO/Clock Monitor Control Register" bitfld.long 0x00 24. " BIASENABLE ,Bias enable" "Disabled,Enabled" bitfld.long 0x00 16. " OSCFRQCONFIGCNT ,Configures the counter based on OSC frequency" "OSC freq is <= 20MHz,OSC freq is > 20MHz and <= 80MHz" textline " " bitfld.long 0x00 8.--11. " HFTRIM ,High frequency oscillator trim value" "29.52,38.85,47.99,57.02,65.92,74.55,83.17,91.75,100.00,108.17,116.41,124.42,132.24,140.15,148.02,155.50" bitfld.long 0x00 0.--3. " LFTRIM ,Low frequency oscillator trim value" "20.67,30.84,40.93,50.97,60.86,70.75,80.61,90.23,100.00,109.51,119.01,128.62,138.03,147.32,156.63,165.90" line.long 0x04 "CLKTEST,Clock Test Register" bitfld.long 0x04 26. " ALTLIMPCLOCKENABLE ,Alternate limp clock enable" "Disabled,Enabled" bitfld.long 0x04 25. " RANGEDETCTRL ,Range detection control" "Disabled,Enabled" textline " " bitfld.long 0x04 24. " RANGEDETENASSEL ,Selects range detection enable" "Disabled,Enabled" bitfld.long 0x04 16.--19. " CLK_TEST_EN ,Clock test enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" textline " " bitfld.long 0x04 8.--11. " SEL_N2HET_PIN ,N2HET[2] pin clock source valid" "Oscillator,PLL,Reserved,Reserved,Reserved,HF clock LPO,Reserved,Reserved,LF clock LPO,Oscillator,Oscillator,Oscillator,Oscillator,Oscillator,Oscillator,Oscillator" bitfld.long 0x04 0.--3. " SEL_ECP_PIN ,ECLK pin clock source select" "Oscillator clock,PLL clock,Reserved,Reserved,LF LPO,HF LPO,Reserved,Reserved,GCLK,RTI Base,Reserved,VCLKA1,Reserved,Reserved,Reserved,Flash HD Pump Oscillator" tree.end width 0xB tree.end else tree "Oscilator and PLL" base ad:0xFFFFFF70 tree "PLL Module Registers" width 0xb group.long 0x00++0x07 line.long 0x00 "PLLCTL1,PLL Control 1 Register" bitfld.long 0x00 31. " ROS ,Reset on PLL Slip" "No reset,Reset" bitfld.long 0x00 29.--30. " BPOS ,Bypass of PLL Slip" "Enabled,Enabled,Disabled,Enabled" textline " " bitfld.long 0x00 24.--28. " PLLDIV ,PLL Output Clock Divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" bitfld.long 0x00 23. " ROF ,Reset on Oscillator Fail" "Not reset,Reset" textline " " bitfld.long 0x00 16.--21. " REFCLKDIV ,Reference Clock Divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,?..." hexmask.long.word 0x00 0.--15. 1. " PLLMUL ,PLL Multiplication Factor" line.long 0x04 "PLLCTL2,PLL Control 2 Register" bitfld.long 0x04 31. " FMENA ,Frequency Modulation Enable" "Disabled,Enabled" hexmask.long.word 0x04 22.--30. 1. " SPREADINGRATE ,Spreading rate" textline " " hexmask.long.word 0x04 12.--20. 1. " MULMOD ,Multiplier Correction" bitfld.long 0x04 9.--11. " ODPLL ,Internal PLL Output Divider" "/1,/2,/3,/4,/5,/6,/7,/8" textline " " hexmask.long.word 0x04 0.--8. 1. " SPR_AMOUNT ,Spreading Amount" base ad:0xFFFFE100 group.long 0x00++0x03 line.long 0x00 "PLLCTL3,PLL Control 3 Register" bitfld.long 0x00 29.--31. " ODPLL ,Internal PLL Output Divider" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 24.--28. " PLLDIV ,PLL Output Clock Divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32" textline " " bitfld.long 0x00 16.--21. " REFCLK_DIV ,Reference Clock Divider" "/1,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16,/17,/18,/19,/20,/21,/22,/23,/24,/25,/26,/27,/28,/29,/30,/31,/32,/33,/34,/35,/36,/37,/38,/39,/40,/41,/42,/43,/44,/45,/46,/47,/48,/49,/50,/51,/52,/53,/54,/55,/56,/57,/58,/59,/60,/61,/62,/63,?..." hexmask.long.word 0x00 0.--15. 1. " PLLMUL ,PLL Multiplication Factor" group.long 0x70++0x03 line.long 0x00 "CLKSLIP,PLL1 Clock Slip Control Register" bitfld.long 0x00 8.--13. " PLL1_RFSLIP_FILTER_COUNT ,Consecutive cycles of the HF LPO for which RFSLIP from PLL1 must be active in order to be recognized as a slip" "Disabled/Recognized,Enabled/Recognized,Enabled / 2 HF LPO cycles,Enabled / 3 HF LPO cycles,Enabled / 4 HF LPO cycles,Enabled / 5 HF LPO cycles,Enabled / 6 HF LPO cycles,Enabled / 7 HF LPO cycles,Enabled / 8 HF LPO cycles,Enabled / 9 HF LPO cycles,Enabled / 10 HF LPO cycles,Enabled / 11 HF LPO cycles,Enabled / 12 HF LPO cycles,Enabled / 13 HF LPO cycles,Enabled / 14 HF LPO cycles,Enabled / 15 HF LPO cycles,Enabled / 16 HF LPO cycles,Enabled / 17 HF LPO cycles,Enabled / 18 HF LPO cycles,Enabled / 19 HF LPO cycles,Enabled / 20 HF LPO cycles,Enabled / 21 HF LPO cycles,Enabled / 22 HF LPO cycles,Enabled / 23 HF LPO cycles,Enabled / 24 HF LPO cycles,Enabled / 25 HF LPO cycles,Enabled / 26 HF LPO cycles,Enabled / 27 HF LPO cycles,Enabled / 28 HF LPO cycles,Enabled / 29 HF LPO cycles,Enabled / 30 HF LPO cycles,Enabled / 31 HF LPO cycles,Enabled / 32 HF LPO cycles,Enabled / 33 HF LPO cycles,Enabled / 34 HF LPO cycles,Enabled / 35 HF LPO cycles,Enabled / 36 HF LPO cycles,Enabled / 37 HF LPO cycles,Enabled / 38 HF LPO cycles,Enabled / 39 HF LPO cycles,Enabled / 40 HF LPO cycles,Enabled / 41 HF LPO cycles,Enabled / 42 HF LPO cycles,Enabled / 43 HF LPO cycles,Enabled / 44 HF LPO cycles,Enabled / 45 HF LPO cycles,Enabled / 46 HF LPO cycles,Enabled / 47 HF LPO cycles,Enabled / 48 HF LPO cycles,Enabled / 49 HF LPO cycles,Enabled / 50 HF LPO cycles,Enabled / 51 HF LPO cycles,Enabled / 52 HF LPO cycles,Enabled / 53 HF LPO cycles,Enabled / 54 HF LPO cycles,Enabled / 55 HF LPO cycles,Enabled / 56 HF LPO cycles,Enabled / 57 HF LPO cycles,Enabled / 58 HF LPO cycles,Enabled / 59 HF LPO cycles,Enabled / 60 HF LPO cycles,Enabled / 61 HF LPO cycles,Enabled / 62 HF LPO cycles,Enabled / 63 HF LPO cycles" bitfld.long 0x00 0.--3. " PLL1_RFSLIP_FILTER_KEY ,Key to enable slip filtering for RFSLIP from PLL1" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Not used" base ad:0xFFFFFFA0 group.long 0x00++0x03 line.long 0x00 "GPREG1,General Purpose Register1" bitfld.long 0x00 20.--25. " PLL1_FBSLIP_FILTER_COUNT ,Consecutive cycles of the HF LPO for which FBSLIP from PLL1 must be active in order to be recognized as a slip" "Disabled/Recognized,Enabled/Recognized,Enabled / 2 HF LPO cycles,Enabled / 3 HF LPO cycles,Enabled / 4 HF LPO cycles,Enabled / 5 HF LPO cycles,Enabled / 6 HF LPO cycles,Enabled / 7 HF LPO cycles,Enabled / 8 HF LPO cycles,Enabled / 9 HF LPO cycles,Enabled / 10 HF LPO cycles,Enabled / 11 HF LPO cycles,Enabled / 12 HF LPO cycles,Enabled / 13 HF LPO cycles,Enabled / 14 HF LPO cycles,Enabled / 15 HF LPO cycles,Enabled / 16 HF LPO cycles,Enabled / 17 HF LPO cycles,Enabled / 18 HF LPO cycles,Enabled / 19 HF LPO cycles,Enabled / 20 HF LPO cycles,Enabled / 21 HF LPO cycles,Enabled / 22 HF LPO cycles,Enabled / 23 HF LPO cycles,Enabled / 24 HF LPO cycles,Enabled / 25 HF LPO cycles,Enabled / 26 HF LPO cycles,Enabled / 27 HF LPO cycles,Enabled / 28 HF LPO cycles,Enabled / 29 HF LPO cycles,Enabled / 30 HF LPO cycles,Enabled / 31 HF LPO cycles,Enabled / 32 HF LPO cycles,Enabled / 33 HF LPO cycles,Enabled / 34 HF LPO cycles,Enabled / 35 HF LPO cycles,Enabled / 36 HF LPO cycles,Enabled / 37 HF LPO cycles,Enabled / 38 HF LPO cycles,Enabled / 39 HF LPO cycles,Enabled / 40 HF LPO cycles,Enabled / 41 HF LPO cycles,Enabled / 42 HF LPO cycles,Enabled / 43 HF LPO cycles,Enabled / 44 HF LPO cycles,Enabled / 45 HF LPO cycles,Enabled / 46 HF LPO cycles,Enabled / 47 HF LPO cycles,Enabled / 48 HF LPO cycles,Enabled / 49 HF LPO cycles,Enabled / 50 HF LPO cycles,Enabled / 51 HF LPO cycles,Enabled / 52 HF LPO cycles,Enabled / 53 HF LPO cycles,Enabled / 54 HF LPO cycles,Enabled / 55 HF LPO cycles,Enabled / 56 HF LPO cycles,Enabled / 57 HF LPO cycles,Enabled / 58 HF LPO cycles,Enabled / 59 HF LPO cycles,Enabled / 60 HF LPO cycles,Enabled / 61 HF LPO cycles,Enabled / 62 HF LPO cycles,Enabled / 63 HF LPO cycles" bitfld.long 0x00 16.--19. " PLL1_FBSLIP_FILTER_KEY ,Key to enable slip filtering for FBSLIP from PLL1" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Not used" base ad:0xFFFFFF24 group.long 0x00++0x03 line.long 0x00 "SSWPLL1,PLL Modulation Depth Measurement Control Register" hexmask.long.byte 0x00 8.--15. 1. " CAPTURE_WINDOW_INDEX ,Capture counter" bitfld.long 0x00 6. " COUNTER_READ_READY ,Counter read ready" "Not ready,Ready" textline " " bitfld.long 0x00 5. " COUNTER_RESET ,Counter reset" "No reset,Reset" bitfld.long 0x00 4. " COUNTER_EN ,Counter enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1.--3. " TAP_COUNTER_DIS ,Used to program a particular bit in CLKOUT counter" "Bit 16 selected,Bit 18 selected,Bit 20 selected,Bit 22 selected,Bit 24 selected,Bit 26 selected,Bit 28 selected,Bit 30 selected" bitfld.long 0x00 0. " EXT_COUNTER_EN ,Measurement mode select" "Modulation depth,Frequency" rgroup.long 0x04++0x07 line.long 0x00 "SSWPLL2,SSW PLL BIST Control Register 2" line.long 0x04 "SSWPLL3,SSW PLL BIST Control Register 3" tree.end tree "LPOCLKDET Module Registers" width 0xb base ad:0xFFFFFF88 group.long 0x00++0x07 line.long 0x00 "LPOMONCTL,LPO/Clock Monitor Control Register" bitfld.long 0x00 24. " BIASENABLE ,Bias enable" "Disabled,Enabled" bitfld.long 0x00 16. " OSCFRQCONFIGCNT ,Configures the counter based on OSC frequency" "OSC freq is <= 20MHz,OSC freq is > 20MHz and <= 80MHz" textline " " bitfld.long 0x00 8.--12. " HFTRIM ,High frequency oscillator trim value" "29.52,34.24,38.85,43.45,47.99,52.55,57.02,61.46,65.92,70.17,74.55,78.92,83.17,87.43,91.75,95.89,100.00% Default at Reset,104.09,108.17,112.32,116.41,120.67,124.42,128.38,132.24,136.15,140.15,143.94,148.02,151.80,155.50,159.35" bitfld.long 0x00 0.--4. " LFTRIM ,Low frequency oscillator trim value" "20.67,25.76,30.84,35.90,40.93,45.95,50.97,55.91,60.86,65.78,70.75,75.63,80.61,85.39,90.23,95.11,100.00% Default at Reset,104.84,109.51,114.31,119.01,123.75,128.62,133.31,138.03,142.75,147.32,152.02,156.63,161.38,165.90,170.42" line.long 0x04 "CLKTEST,Clock Test Register" bitfld.long 0x04 26. " TEST ,Range detection control" "0,1" bitfld.long 0x04 25. " RANGEDETCTRL ,Range detection control" "Disabled,Enabled" textline " " bitfld.long 0x04 24. " RANGEDETENABLE ,Selects range detection enable" "Disabled,Enabled" bitfld.long 0x04 16.--19. " CLK_TEST_EN ,Clock test enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" textline " " bitfld.long 0x04 8.--11. " SEL_GIO_PIN ,Select the clock source" "Oscillator Valid Status,Main PLL Valid status,Reserved,Reserved,Reserved,CLK10M Valid status,Secondary PLL Valid Status,Reserved,CLK80K,?..." bitfld.long 0x04 0.--3. " SEL_ECP_PIN ,Select the clock at ECP Pin" "Oscillator,Main PLL free-running clock output,Reserved,EXTCLKIN1,CLK80K,CLK10M,Secondary PLL free-running clock output,EXTCLKIN2,GCLK,RTI Base,Reserved,VCLKA1,Reserved,VCLKA3,VCLKA4,?..." tree.end width 0xB tree.end endif tree "DCC (Dual-Clock Comparator)" tree "DCC1" base ad:0xFFFFEC00 sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")) endian.be endif width 12. group.long 0x00++0x03 line.long 0x00 "GCTRL,Global Control Register" bitfld.long 0x00 12.--15. " DONE_INT_ENA ,Done interrupt enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" sif cpuis("TMS570LS3137-EP") bitfld.long 0x00 8.--11. " SINGLE_SHOT ,Single-shot mode enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,CNT0_VALID0,CNT1,Disabled,Disabled,Disabled,Disabled" else bitfld.long 0x00 8.--11. " SINGLE_SHOT ,Single-shot mode enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Enabled,Disabled,Disabled,Disabled,Disabled" endif bitfld.long 0x00 4.--7. " ERR_ENA ,Error interrupt enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.long 0x00 0.--3. " DCC_ENA ,DCC enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" rgroup.long 0x04++0x03 line.long 0x00 "REV,Revision ID Register" bitfld.long 0x00 30.--31. " SCHEME ,Scheme" "0,1,2,3" newline hexmask.long.word 0x00 16.--27. 1. " FUNC ,Functional release number" newline bitfld.long 0x00 11.--15. " RTL ,Design release number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--10. " MAJOR ,Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 6.--7. " CUSTOM ,Custom version number" "0,1,2,3" bitfld.long 0x00 0.--5. " MINOR ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x08++0x0F line.long 0x00 "CNTSEED0,DCC Counter 0 Seed Register" hexmask.long.tbyte 0x00 0.--19. 1. " COUNT0_SEED ,Seed value for DCC counter 0" line.long 0x04 "VALIDSEED0,Valid 0 Seed Value" hexmask.long.word 0x04 0.--15. 1. " VALID0_SEED ,Seed value for DCC valid 0" line.long 0x08 "CNTSEED1,DCC Counter 1 Seed Register" hexmask.long.tbyte 0x08 0.--19. 1. " COUNT1_SEED ,Seed value for DCC counter 1" line.long 0x0C "STAT,Status Register" eventfld.long 0x0C 1. " DONE_FLG ,Single-shot sequence done flag" "Not done,Done" eventfld.long 0x0C 0. " ERR_FLG ,Error flag" "No error,Error" rgroup.long 0x18++0x07 line.long 0x00 "CNT0,DCC Counter 0 Value Register" hexmask.long.tbyte 0x00 0.--19. 1. " COUNT0 ,Value of DCC counter 0" line.long 0x04 "VALID0,Valid 0 Value Register" hexmask.long.word 0x04 0.--15. 1. " VALID0 ,Current value for DCC valid 0" group.long 0x20++0x03 line.long 0x00 "CNT1,DCC Counter 1 Value Register" hexmask.long.tbyte 0x00 0.--19. 1. " COUNT1 ,Value of DCC counter 1" sif (cpuis("RM48L950")||cpuis("RM48L952-PGE")||cpuis("RM48L950-PGE")||cpuis("RM48L950-ZWT")||cpuis("RM48L940-ZWT")||cpuis("RM48L940-PGE")||cpuis("RM48L930-ZWT")||cpuis("RM48L930-PGE")||cpuis("RM48L750-ZWT")||cpuis("RM48L750-PGE")||cpuis("RM48L740-ZWT")||cpuis("RM48L740-PGE")||cpuis("RM48L730-ZWT")||cpuis("RM48L730-PGE")||cpuis("RM48L550-PGE")||cpuis("RM48L540-ZWT")||cpuis("RM48L540-PGE")||cpuis("RM48L530-ZWT")||cpuis("RM48L530-PGE")||cpuis("RM46L852-PGE")||cpuis("RM46L852-ZWT")||cpuis("RM46L850-PGE")||cpuis("RM46L850-ZWT")||cpuis("RM46L840-ZWT")||cpuis("RM46L840-PGE")||cpuis("RM46L830-ZWT")||cpuis("RM46L830-PGE")||cpuis("RM46L450-ZWT")||cpuis("RM46L450-PGE")||cpuis("RM46L440-ZWT")||cpuis("RM46L440-PGE")||cpuis("RM46L430-ZWT")||cpuis("RM46L430-PGE")||cpuis("RM42L432")||cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")) if (((per.l(ad:0xFFFFEC00+0x24))&0xF00000)==0xA00000) group.long 0x24++0x3 line.long 0x0 "CNT1CLKSRC,DCC Counter1 Clock Source Selection Register" bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for Counter1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")) bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock Source for Counter1" "PLL Output,,LF LPO,HF LPO,HD pump,EXTCLKIN,,Ring,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK" elif (cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")) bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock Source for Counter1" "PLL1 Output,PLL2 Output,LF LPO,HF LPO,,EXTCLKIN1,EXTCLKIN2,,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK" else bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock Source for Counter1" "PLL1 Output,PLL2 Output,LF LPO,HF LPO,,EXTCLKIN1,EXTCLKIN2,,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK" endif else group.long 0x24++0x3 line.long 0x0 "CNT1CLKSRC,DCC Counter1 Clock Source Selection Register" bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for Counter1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" endif elif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")||cpuis("TMS570LS3137-EP")) if (((per.l.be(ad:0xFFFFEC00+0x24))&0xF000)==0xA000) group.long 0x24++0x03 line.long 0x00 "CNT1CLKSRC,DCC Counter 1 Clock Source Selection Register" bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for counter 1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" sif (cpuis("TMS570LS0232")) bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock source for counter 1" "PLL1 Output,,LF LPO,HF LPO,,EXTCLKIN,,,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK" elif (cpuis("TMS570LS3137-EP")) bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock source for counter 1" "PLL Output,,LF LPO,HF LPO,Flash HD,EXTCLKIN1,,Ring oscillator,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK" elif cpuis("TMS570LS09*")||cpuis("TMS570LS07*") bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock source for counter 1" "OSCIN,PLL1,,EXTCLKIN1,LFLPO,HFLPO,,EXTCLKIN2,?..." endif else group.long 0x24++0x03 line.long 0x00 "CNT1CLKSRC,DCC Counter 1 Clock Source Selection Register" bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for counter 1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" endif else if (((per.l(ad:0xFFFFEC00+0x24))&0xF000)==0xA000) group.long 0x24++0x03 line.long 0x00 "CNT1CLKSRC,DCC Counter 1 Clock Source Selection Register" bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for counter 1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" newline sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")) bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock source for counter 1" "PLL Output,,LF LPO,HF LPO,HD pump,EXTCLKIN,,Ring,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK" elif (cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")) bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock source for counter 1" "PLL1 Output,PLL2 Output,LF LPO,HF LPO,,EXTCLKIN1,EXTCLKIN2,,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK" else bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock source for counter 1" "PLL1 Output,PLL2 Output,LF LPO,HF LPO,,EXTCLKIN1,EXTCLKIN2,,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK" endif else group.long 0x24++0x03 line.long 0x00 "CNT1CLKSRC,DCC Counter 1 Clock Source Selection Register" bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for counter 1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" endif endif sif (!cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*")&&!cpuis("TMS570LS0232")&&!cpuis("TMS570LS3137-EP")) sif (cpuis("RM48L950")||cpuis("RM48L952-PGE")||cpuis("RM48L952-ZWT")||cpuis("RM48L950-PGE")||cpuis("RM48L950-ZWT")||cpuis("RM48L940-ZWT")||cpuis("RM48L940-PGE")||cpuis("RM48L930-ZWT")||cpuis("RM48L930-PGE")||cpuis("RM48L750-ZWT")||cpuis("RM48L750-PGE")||cpuis("RM48L740-ZWT")||cpuis("RM48L740-PGE")||cpuis("RM48L730-ZWT")||cpuis("RM48L730-PGE")||cpuis("RM48L550-PGE")||cpuis("RM48L540-ZWT")||cpuis("RM48L540-PGE")||cpuis("RM48L530-ZWT")||cpuis("RM48L530-PGE")||cpuis("RM46L852-PGE")||cpuis("RM46L852-ZWT")||cpuis("RM46L850-PGE")||cpuis("RM46L850-ZWT")||cpuis("RM46L840-ZWT")||cpuis("RM46L840-PGE")||cpuis("RM46L830-ZWT")||cpuis("RM46L830-PGE")||cpuis("RM46L450-ZWT")||cpuis("RM46L450-PGE")||cpuis("RM46L440-ZWT")||cpuis("RM46L440-PGE")||cpuis("RM46L430-ZWT")||cpuis("RM46L430-PGE")||cpuis("RM42L432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0332")||cpuis("TMS570LS0432")) if (((per.l(ad:0xFFFFEC00+0x24))&0xF00000)==0xA00000) group.long 0x24++0x03 line.long 0x00 "CNT1CLKSRC,DCC Counter 1 Clock Source Selection Register" bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for counter 1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock source for counter 1" ",,,,,,,,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK" else group.long 0x24++0x03 line.long 0x00 "CNT1CLKSRC,DCC Counter 1 Clock Source Selection Register" bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for counter 1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" endif else if (((per.l(ad:0xFFFFEC00+0x24))&0xF000)==0xA000) group.long 0x24++0x03 line.long 0x00 "CNT1CLKSRC,DCC Counter 1 Clock Source Selection Register" bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for Counter1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock source for counter 1" ",,,,,,,,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK" else group.long 0x24++0x03 line.long 0x00 "CNT1CLKSRC,DCC Counter 1 Clock Source Selection Register" bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for counter 1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" endif endif endif group.long 0x28++0x03 line.long 0x00 "CNT0CLKSRC,DCC Counter0 Clock Source Selection Register" sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")||cpuis("TMS570LS3137-EP")||cpuis("RM48L950")||cpuis("RM48L952-PGE")||cpuis("RM48L952-ZWT")||cpuis("RM48L950-PGE")||cpuis("RM48L950-ZWT")||cpuis("RM48L940-ZWT")||cpuis("RM48L940-PGE")||cpuis("RM48L930-ZWT")||cpuis("RM48L930-PGE")||cpuis("RM48L750-ZWT")||cpuis("RM48L750-PGE")||cpuis("RM48L740-ZWT")||cpuis("RM48L740-PGE")||cpuis("RM48L730-ZWT")||cpuis("RM48L730-PGE")||cpuis("RM48L550-PGE")||cpuis("RM48L540-ZWT")||cpuis("RM48L540-PGE")||cpuis("RM48L530-ZWT")||cpuis("RM48L530-PGE") bitfld.long 0x00 0.--3. " CNT0_CLKSRC ,Clock source for counter 0" "OSCIN,OSCIN,OSCIN,OSCIN,OSCIN,HF LPO,OSCIN,OSCIN,OSCIN,OSCIN,TCK,OSCIN,OSCIN,OSCIN,OSCIN,OSCIN" else bitfld.long 0x00 0.--3. " CNT0_CLKSRC ,Clock source for counter 0" "OSCIN,OSCIN,OSCIN,OSCIN,OSCIN,OSCIN,OSCIN,OSCIN,OSCIN,OSCIN,TCK,OSCIN,OSCIN,OSCIN,OSCIN,VCLK" endif sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")) endian.le endif width 0x0B tree.end tree "DCC2" base ad:0xFFFFF400 sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")) endian.be endif width 12. group.long 0x00++0x03 line.long 0x00 "GCTRL,Global Control Register" bitfld.long 0x00 12.--15. " DONE_INT_ENA ,Done interrupt enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" sif cpuis("TMS570LS3137-EP") bitfld.long 0x00 8.--11. " SINGLE_SHOT ,Single-shot mode enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,CNT0_VALID0,CNT1,Disabled,Disabled,Disabled,Disabled" else bitfld.long 0x00 8.--11. " SINGLE_SHOT ,Single-shot mode enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Enabled,Disabled,Disabled,Disabled,Disabled" endif bitfld.long 0x00 4.--7. " ERR_ENA ,Error interrupt enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.long 0x00 0.--3. " DCC_ENA ,DCC enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" rgroup.long 0x04++0x03 line.long 0x00 "REV,Revision ID Register" bitfld.long 0x00 30.--31. " SCHEME ,Scheme" "0,1,2,3" newline hexmask.long.word 0x00 16.--27. 1. " FUNC ,Functional release number" newline bitfld.long 0x00 11.--15. " RTL ,Design release number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--10. " MAJOR ,Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 6.--7. " CUSTOM ,Custom version number" "0,1,2,3" bitfld.long 0x00 0.--5. " MINOR ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x08++0x0F line.long 0x00 "CNTSEED0,DCC Counter 0 Seed Register" hexmask.long.tbyte 0x00 0.--19. 1. " COUNT0_SEED ,Seed value for DCC counter 0" line.long 0x04 "VALIDSEED0,Valid 0 Seed Value" hexmask.long.word 0x04 0.--15. 1. " VALID0_SEED ,Seed value for DCC valid 0" line.long 0x08 "CNTSEED1,DCC Counter 1 Seed Register" hexmask.long.tbyte 0x08 0.--19. 1. " COUNT1_SEED ,Seed value for DCC counter 1" line.long 0x0C "STAT,Status Register" eventfld.long 0x0C 1. " DONE_FLG ,Single-shot sequence done flag" "Not done,Done" eventfld.long 0x0C 0. " ERR_FLG ,Error flag" "No error,Error" rgroup.long 0x18++0x07 line.long 0x00 "CNT0,DCC Counter 0 Value Register" hexmask.long.tbyte 0x00 0.--19. 1. " COUNT0 ,Value of DCC counter 0" line.long 0x04 "VALID0,Valid 0 Value Register" hexmask.long.word 0x04 0.--15. 1. " VALID0 ,Current value for DCC valid 0" group.long 0x20++0x03 line.long 0x00 "CNT1,DCC Counter 1 Value Register" hexmask.long.tbyte 0x00 0.--19. 1. " COUNT1 ,Value of DCC counter 1" sif !cpuis("TMS570LS3137-EP") if (((per.l(ad:0xFFFFF400+0x24))&0xF000)==0xA000) group.long 0x24++0x03 line.long 0x00 "CNT1CLKSRC,DCC Counter1 Clock Source Selection Register" bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for counter 1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")) bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock source for counter 1" "PLL Output,,LF LPO,HF LPO,HD pump,EXTCLKIN,,Ring,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK" elif (cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")) bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock source for counter 1" ",,,,,,,,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK" else bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock source for counter 1" "PLL1 Output,PLL2 Output,LF LPO,HF LPO,,EXTCLKIN1,EXTCLKIN2,,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK" endif else group.long 0x24++0x03 line.long 0x00 "CNT1CLKSRC,DCC Counter 1 Clock Source Selection Register" bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for counter 1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" endif else if (((per.l.be(ad:0xFFFFF400+0x24))&0xF000)==0xA000) group.long 0x24++0x03 line.long 0x00 "CNT1CLKSRC,DCC Counter 1 Clock Source Selection Register" bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for counter 1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock source for counter 1" "PLL Output,,LF LPO,HF LPO,Flash HD,EXTCLKIN1,,Ring oscillator,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK" else group.long 0x24++0x03 line.long 0x00 "CNT1CLKSRC,DCC Counter 1 Clock Source Selection Register" bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for counter 1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" endif endif sif (!cpuis("TMS570LS09*")&&!cpuis("TMS570LS07*")&&!cpuis("TMS570LS0232")&&!cpuis("TMS570LS3137-EP")) sif (cpuis("RM48L950")||cpuis("RM48L952-PGE")||cpuis("RM48L952-ZWT")||cpuis("RM48L950-PGE")||cpuis("RM48L950-ZWT")||cpuis("RM48L940-ZWT")||cpuis("RM48L940-PGE")||cpuis("RM48L930-ZWT")||cpuis("RM48L930-PGE")||cpuis("RM48L750-ZWT")||cpuis("RM48L750-PGE")||cpuis("RM48L740-ZWT")||cpuis("RM48L740-PGE")||cpuis("RM48L730-ZWT")||cpuis("RM48L730-PGE")||cpuis("RM48L550-PGE")||cpuis("RM48L540-ZWT")||cpuis("RM48L540-PGE")||cpuis("RM48L530-ZWT")||cpuis("RM48L530-PGE")||cpuis("RM46L852-PGE")||cpuis("RM46L852-ZWT")||cpuis("RM46L850-PGE")||cpuis("RM46L850-ZWT")||cpuis("RM46L840-ZWT")||cpuis("RM46L840-PGE")||cpuis("RM46L830-ZWT")||cpuis("RM46L830-PGE")||cpuis("RM46L450-ZWT")||cpuis("RM46L450-PGE")||cpuis("RM46L440-ZWT")||cpuis("RM46L440-PGE")||cpuis("RM46L430-ZWT")||cpuis("RM46L430-PGE")||cpuis("RM42L432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0332")||cpuis("TMS570LS0432")) if (((per.l(ad:0xFFFFF400+0x24))&0xF00000)==0xA00000) group.long 0x24++0x03 line.long 0x00 "CNT1CLKSRC,DCC Counter 1 Clock Source Selection Register" bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for counter 1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock source for counter 1" ",,,,,,,,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK" else group.long 0x24++0x03 line.long 0x00 "CNT1CLKSRC,DCC Counter 1 Clock Source Selection Register" bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for counter 1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" endif else if (((per.l(ad:0xFFFFF400+0x24))&0xF000)==0xA000) group.long 0x24++0x03 line.long 0x00 "CNT1CLKSRC,DCC Counter 1 Clock Source Selection Register" bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for Counter1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" bitfld.long 0x00 0.--3. " CNT1_CLKSRC ,Clock source for counter 1" ",,,,,,,,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK,VCLK" else group.long 0x24++0x03 line.long 0x00 "CNT1CLKSRC,DCC Counter 1 Clock Source Selection Register" bitfld.long 0x00 12.--15. " KEY ,Key to enable clock source selection for counter 1" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" endif endif endif group.long 0x28++0x03 line.long 0x00 "CNT0CLKSRC,DCC Counter0 Clock Source Selection Register" sif cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")||cpuis("TMS570LS3137-EP")||cpuis("RM48L950")||cpuis("RM48L952-PGE")||cpuis("RM48L952-ZWT")||cpuis("RM48L950-PGE")||cpuis("RM48L950-ZWT")||cpuis("RM48L940-ZWT")||cpuis("RM48L940-PGE")||cpuis("RM48L930-ZWT")||cpuis("RM48L930-PGE")||cpuis("RM48L750-ZWT")||cpuis("RM48L750-PGE")||cpuis("RM48L740-ZWT")||cpuis("RM48L740-PGE")||cpuis("RM48L730-ZWT")||cpuis("RM48L730-PGE")||cpuis("RM48L550-PGE")||cpuis("RM48L540-ZWT")||cpuis("RM48L540-PGE")||cpuis("RM48L530-ZWT")||cpuis("RM48L530-PGE") bitfld.long 0x00 0.--3. " CNT0_CLKSRC ,Clock source for counter 0" "OSCIN,OSCIN,OSCIN,OSCIN,OSCIN,HF LPO,OSCIN,OSCIN,OSCIN,OSCIN,TCK,OSCIN,OSCIN,OSCIN,OSCIN,OSCIN" else bitfld.long 0x00 0.--3. " CNT0_CLKSRC ,Clock source for counter 0" "OSCIN,OSCIN,OSCIN,OSCIN,OSCIN,OSCIN,OSCIN,OSCIN,OSCIN,OSCIN,TCK,OSCIN,OSCIN,OSCIN,OSCIN,VCLK" endif sif (cpuis("TMS570LS09*")||cpuis("TMS570LS07*")||cpuis("TMS570LS0232")) endian.le endif width 0x0B tree.end tree.end sif (cpu()=="RM42L432") tree "ESM (Error Signaling Module)" base ad:0xFFFFF500 width 8. group.long 0x00++0x3 line.long 0x0 "EEPAPR1,Enable Error Pin Action/Response Register 1" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " IEPSET[31]_set/clr ,Set/Clear Influence on Error Pin 31 (CCM-R4 - selftest)" "No influence,Influence" setclrfld.long 0x00 30. 0x00 30. 0x04 30. " IEPSET[30]_set/clr ,Set/Clear Influence on Error Pin 30 (DCC1 - error)" "No influence,Influence" textline " " setclrfld.long 0x00 28. 0x00 28. 0x04 28. " IEPSET[28]_set/clr ,Set/Clear Influence on Error Pin 28 (RAM odd bank (B1TCM))" "No influence,Influence" setclrfld.long 0x00 27. 0x00 27. 0x04 27. " IEPSET[27]_set/clr ,Set/Clear Influence on Error Pin 27 (CPU - selftest)" "No influence,Influence" textline " " setclrfld.long 0x00 26. 0x00 26. 0x04 26. " IEPSET[26]_set/clr ,Set/Clear Influence on Error Pin 26 (RAM even bank (B0TCM)) - correctable error)" "No influence,Influence" setclrfld.long 0x00 23. 0x00 23. 0x04 23. " IEPSET[23]_set/clr ,Set/Clear Influence on Error Pin 23 (DCAN2 - parity)" "No influence,Influence" textline " " setclrfld.long 0x00 22. 0x00 22. 0x04 22. " IEPSET[22]_set/clr ,Set/Clear Influence on Error Pin 22 (DCAN3 - parity)" "No influence,Influence" setclrfld.long 0x00 21. 0x00 21. 0x04 21. " IEPSET[21]_set/clr ,Set/Clear Influence on Error Pin 21 (DCAN1 - parity)" "No influence,Influence" textline " " setclrfld.long 0x00 19. 0x00 19. 0x04 19. " IEPSET[19]_set/clr ,Set/Clear Influence on Error Pin 19 (MibADC1 - parity)" "No influence,Influence" setclrfld.long 0x00 17. 0x00 17. 0x04 17. " IEPSET[17]_set/clr ,Set/Clear Influence on Error Pin 17 (MibSPI1 - parity)" "No influence,Influence" textline " " setclrfld.long 0x00 15. 0x00 15. 0x04 15. " IEPSET[15]_set/clr ,Set/Clear Influence on Error Pin 15 (VIM RAM - parity)" "No influence,Influence" setclrfld.long 0x00 11. 0x00 11. 0x04 11. " IEPSET[11]_set/clr ,Set/Clear Influence on Error Pin 11 (Clock Monitor - interrupt)" "No influence,Influence" textline " " setclrfld.long 0x00 10. 0x00 10. 0x04 10. " IEPSET[10]_set/clr ,Set/Clear Influence on Error Pin 10 (PLL - Slip)" "No influence,Influence" setclrfld.long 0x00 9. 0x00 9. 0x04 9. " IEPSET[9]_set/clr ,Set/Clear Influence on Error Pin 9 (HET TU - MPU)" "No influence,Influence" textline " " setclrfld.long 0x00 8. 0x00 8. 0x04 8. " IEPSET[8]_set/clr ,Set/Clear Influence on Error Pin 8 (HET TU - parity)" "No influence,Influence" setclrfld.long 0x00 7. 0x00 7. 0x04 7. " IEPSET[7]_set/clr ,Set/Clear Influence on Error Pin 7 (N2HET - parity)" "No influence,Influence" textline " " setclrfld.long 0x00 6. 0x00 6. 0x04 6. " IEPSET[6]_set/clr ,Set/Clear Influence on Error Pin 6 (FMC - correctable error) - correctable error)" "No influence,Influence" width 8. group.long 0x08++0x3 line.long 0x0 "IESR1,Interrupt Enable Set/Status Register 1" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTENSET[31]_set/clr ,Set/Clear Interrupt Enable 31 (CCM-R4 - selftest)" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x04 30. " INTENSET[30]_set/clr ,Set/Clear Interrupt Enable 30 (DCC1 - error)" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x04 28. " INTENSET[28]_set/clr ,Set/Clear Interrupt Enable 28 (RAM odd bank (B1TCM))" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x04 27. " INTENSET[27]_set/clr ,Set/Clear Interrupt Enable 27 (CPU - selftest)" "Disabled,Enabled" textline " " setclrfld.long 0x00 26. 0x00 26. 0x04 26. " INTENSET[26]_set/clr ,Set/Clear Interrupt Enable 26 (RAM even bank (B0TCM))" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x04 23. " INTENSET[23]_set/clr ,Set/Clear Interrupt Enable 23 (DCAN2 - parity)" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x04 22. " INTENSET[22]_set/clr ,Set/Clear Interrupt Enable 22 (DCAN3 - parity)" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x04 21. " INTENSET[21]_set/clr ,Set/Clear Interrupt Enable 21 (DCAN1 - parity)" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x04 19. " INTENSET[19]_set/clr ,Set/Clear Interrupt Enable 19 (MibADC1 - parity)" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x04 17. " INTENSET[17]_set/clr ,Set/Clear Interrupt Enable 17 (MibSPI1 - parity)" "Disabled,Enabled" textline " " setclrfld.long 0x00 15. 0x00 15. 0x04 15. " INTENSET[15]_set/clr ,Set/Clear Interrupt Enable 15 (VIM RAM - parity)" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x04 11. " INTENSET[11]_set/clr ,Set/Clear Interrupt Enable 11 (Clock Monitor - interrupt)" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x04 10. " INTENSET[10]_set/clr ,Set/Clear Interrupt Enable 10 (PLL - slip)" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x04 9. " INTENSET[9]_set/clr ,Set/Clear Interrupt Enable 9 (HET TU1 - MPU)" "Disabled,Enabled" textline " " setclrfld.long 0x00 8. 0x00 8. 0x04 8. " INTENSET[8]_set/clr ,Set/Clear Interrupt Enable 8 (HET TU - parity)" "Disabled,Enabled" setclrfld.long 0x00 7. 0x00 7. 0x04 7. " INTENSET[7]_set/clr ,Set/Clear Interrupt Enable 7 (N2HET - parity)" "Disabled,Enabled" textline " " setclrfld.long 0x00 6. 0x00 6. 0x04 6. " INTENSET[6]_set/clr ,Set/Clear Interrupt Enable 6 (FMC - correctable error) - correctable error)" "Disabled,Enabled" width 8. group.long 0x10++0x3 line.long 0x0 "ILSR1,Interrupt Level Set/Status Register 1" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTLVLSET_set/clr[31] ,Set/Clear Interrupt Level 31 (CCM-R4 - selftest)" "Low,High" setclrfld.long 0x00 30. 0x00 30. 0x04 30. " INTLVLSET_set/clr[30] ,Set/Clear Interrupt Level 30 (DCC1 - error)" "Low,High" textline " " setclrfld.long 0x00 28. 0x00 28. 0x04 28. " INTLVLSET_set/clr[28] ,Set/Clear Interrupt Level 28 (RAM odd bank (B1TCM))" "Low,High" setclrfld.long 0x00 27. 0x00 27. 0x04 27. " INTLVLSET_set/clr[27] ,Set/Clear Interrupt Level 27 (CPU - selftest)" "Low,High" textline " " setclrfld.long 0x00 26. 0x00 26. 0x04 26. " INTLVLSET_set/clr[26] ,Set/Clear Interrupt Level 26 (RAM even bank (B0TCM))" "Low,High" setclrfld.long 0x00 23. 0x00 23. 0x04 23. " INTLVLSET_set/clr[23] ,Set/Clear Interrupt Level 23 (DCAN2 - parity)" "Low,High" textline " " setclrfld.long 0x00 22. 0x00 22. 0x04 22. " INTLVLSET_set/clr[22] ,Set/Clear Interrupt Level 22 (DCAN3 - parity)" "Low,High" setclrfld.long 0x00 21. 0x00 21. 0x04 21. " INTLVLSET_set/clr[21] ,Set/Clear Interrupt Level 21 (DCAN1 - parity)" "Low,High" textline " " setclrfld.long 0x00 19. 0x00 19. 0x04 19. " INTLVLSET_set/clr[19] ,Set/Clear Interrupt Level 19 (MibADC1 - parity)" "Low,High" setclrfld.long 0x00 17. 0x00 17. 0x04 17. " INTLVLSET_set/clr[17] ,Set/Clear Interrupt Level 17 (MibSPI1 - parity)" "Low,High" textline " " setclrfld.long 0x00 15. 0x00 15. 0x04 15. " INTLVLSET_set/clr[15] ,Set/Clear Interrupt Level 15 (VIM RAM - parity)" "Low,High" setclrfld.long 0x00 11. 0x00 11. 0x04 11. " INTLVLSET_set/clr[11] ,Set/Clear Interrupt Level 11 (Clock Monitor - interrupt)" "Low,High" textline " " setclrfld.long 0x00 10. 0x00 10. 0x04 10. " INTLVLSET_set/clr[10] ,Set/Clear Interrupt Level 10 (PLL - slip)" "Low,High" setclrfld.long 0x00 9. 0x00 9. 0x04 9. " INTLVLSET_set/clr[9] ,Set/Clear Interrupt Level 9 (HET TU - MPU)" "Low,High" textline " " setclrfld.long 0x00 8. 0x00 8. 0x04 8. " INTLVLSET_set/clr[8] ,Set/Clear Interrupt Level 8 (HET TU - parity)" "Low,High" setclrfld.long 0x00 7. 0x00 7. 0x04 7. " INTLVLSET_set/clr[7] ,Set/Clear Interrupt Level 7 (N2HET - parity)" "Low,High" textline " " setclrfld.long 0x00 6. 0x00 6. 0x04 6. " INTLVLSET_set/clr[6] ,Set/Clear Interrupt Level 6 (FMC - correctable error)" "Low,High" width 8. group.long 0x18++0x3 line.long 0x0 "SR1,Status Register 1" eventfld.long 0x00 31. " ESF[31] ,Error Status Flag 31 (CCM-R4 - selftest)" "No error,Error" eventfld.long 0x00 30. " ESF[30] ,Error Status Flag 30 (DCC1 - error)" "No error,Error" textline " " eventfld.long 0x00 28. " ESF[28] ,Error Status Flag 28 (RAM odd bank (B1TCM))" "No error,Error" eventfld.long 0x00 26. " ESF[26] ,Error Status Flag 26 (RAM even bank (B0TCM))" "No error,Error" textline " " eventfld.long 0x00 23. " ESF[23] ,Error Status Flag 23 (DCAN2 - parity)" "No error,Error" eventfld.long 0x00 21. " ESF[21] ,Error Status Flag 21 (DCAN1 - parity)" "No error,Error" textline " " eventfld.long 0x00 19. " ESF[19] ,Error Status Flag 19 (MibADC1 - parity)" "No error,Error" eventfld.long 0x00 17. " ESF[17] ,Error Status Flag 17 (MibSPI1 - parity)" "No error,Error" textline " " eventfld.long 0x00 15. " ESF[15] ,Error Status Flag 15 (VIM RAM - parity)" "No error,Error" eventfld.long 0x00 11. " ESF[11] ,Error Status Flag 11 (Clock Monitor - interrupt)" "No error,Error" textline " " eventfld.long 0x00 10. " ESF[10] ,Error Status Flag 10 (PLL - slip)" "No error,Error" eventfld.long 0x00 9. " ESF[9] ,Error Status Flag 9 (HET TU - MPU)" "No error,Error" textline " " eventfld.long 0x00 8. " ESF[8] ,Error Status Flag 8 (HET TU - parity)" "No error,Error" eventfld.long 0x00 7. " ESF[7] ,Error Status Flag 7 (N2HET - parity)" "No error,Error" textline " " eventfld.long 0x00 6. " ESF[6] ,Error Status Flag 6 (FMC - correctable error)" "No error,Error" group.long 0x1C++0x3 line.long 0x0 "SR2,Status Register 2" eventfld.long 0x00 24. " ESF[24] ,Error Status Flag 24 (RTI_WWD_NMI)" "No error,Error" eventfld.long 0x00 16. " ESF[16] ,Error Status Flag 16 (Flash (ATCM) - ECC live lock detect)" "No error,Error" eventfld.long 0x00 12. " ESF[12] ,Error Status Flag 12 (B1TCM - address bus parity error)" "No error,Error" eventfld.long 0x00 10. " ESF[10] ,Error Status Flag 10 (B0TCM - address bus parity error)" "No error,Error" textline " " eventfld.long 0x00 8. " ESF[8] ,Error Status Flag 8 (B1TCM - uncorrectable error)" "No error,Error" eventfld.long 0x00 6. " ESF[6] ,Error Status Flag 6 (B0TCM - uncorrectable error)" "No error,Error" eventfld.long 0x00 4. " ESF[4] ,Error Status Flag 4 (FMC - uncorrectable error)" "No error,Error" eventfld.long 0x00 2. " ESF[2] ,Error Status Flag 2 (CCM-R4 - compare)" "No error,Error" group.long 0x20++0x3 line.long 0x0 "SR3,Status Register 3" eventfld.long 0x00 7. " ESF[7] ,Error Status Flag 7 (FMC - uncorrectable error)" "No error,Error" eventfld.long 0x00 5. " ESF[5] ,Error Status Flag 5 (B1TCM - ECC uncorrectable error)" "No error,Error" eventfld.long 0x00 3. " ESF[3] ,Error Status Flag 3 (B0TCM - ECC uncorrectable error)" "No error,Error" eventfld.long 0x00 1. " ESF[1] ,Error Status Flag 1 (eFuse Controller - autoload error)" "No error,Error" width 8. rgroup.long 0x24++0x3 line.long 0x0 "EPSR,Error Pin Status Register" bitfld.long 0x00 0. " EPSF ,Error Pin Status Flag" "Active,Not active" rgroup.long 0x28++0x3 line.long 0x0 "IOFFHR,Interrupt Offset High Register" hexmask.long.byte 0x00 0.--6. 1. " INTOFFH ,Offset High Level Interrupt" rgroup.long 0x2C++0x3 line.long 0x0 "IOFFLR,Interrupt Offset Low Register" hexmask.long.byte 0x00 0.--6. 1. " INTOFFL ,Offset Low Level Interrupt" rgroup.long 0x30++0x3 line.long 0x0 "LTCR,Low-Time Counter Register" hexmask.long.word 0x00 0.--15. 1. " LTC ,Error Pin Low-Time Counter" group.long 0x34++0x3 line.long 0x0 "LTCPR,Low-Time Counter Preload Register" bitfld.long 0x00 14.--15. " LTCP[15:14] ,Low-Time Counter Pre-load Value [15:14]" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. " LTCP[13:0] ,Low-Time Counter Pre-load Value [13:0]" group.long 0x38++0x3 line.long 0x0 "EKR,Error Key Register" bitfld.long 0x00 0.--3. " EKEY ,Error Key" "Normal,Normal,Normal,Normal,Normal,LTC,Normal,Normal,Normal,Normal,Forced,Normal,Normal,Normal,Normal,Normal" width 8. group.long 0x3C++0x3 line.long 0x0 "SSR2,Status Shadow Register" eventfld.long 0x00 24. " ESF[24] ,Error Status Flag 24 (RTI_WWD_NMI)" "No error,Error" eventfld.long 0x00 16. " ESF[16] ,Error Status Flag 16 (Flash (ATCM) - ECC live lock detect)" "No error,Error" eventfld.long 0x00 12. " ESF[12] ,Error Status Flag 12 (B1TCM - address bus parity error)" "No error,Error" eventfld.long 0x00 10. " ESF[10] ,Error Status Flag 10 (B0TCM - address bus parity error)" "No error,Error" textline " " eventfld.long 0x00 8. " ESF[8] ,Error Status Flag 8 (B1TCM - uncorrectable error)" "No error,Error" eventfld.long 0x00 6. " ESF[6] ,Error Status Flag 6 (B0TCM - uncorrectable error)" "No error,Error" eventfld.long 0x00 4. " ESF[4] ,Error Status Flag 4 (Flash (ATCM) - uncorrectable error)" "No error,Error" eventfld.long 0x00 2. " ESF[2] ,Error Status Flag 2 (CCM-R4 - compare)" "No error,Error" width 8. group.long 0x40++0x3 line.long 0x0 "IEPSR4,Influence Error Pin Set/Status Register 4" setclrfld.long 0x00 9. 0x00 9. 0x04 9. " IEPSET[41]_set/clr ,Set/Clear Influence on Error Pin 41 (eFuse farm - self test error)" "No influence,Influence" setclrfld.long 0x00 8. 0x00 8. 0x04 8. " IEPSET[40]_set/clr ,Set/Clear Influence on Error Pin 40 (eFuse Controller Error)" "No influence,Influence" textline " " setclrfld.long 0x00 5. 0x00 5. 0x04 5. " IEPSET[37]_set/clr ,Set/Clear Influence on Error Pin 37 (IOMM - mux configuration error)" "No influence,Influence" setclrfld.long 0x00 4. 0x00 4. 0x04 4. " IEPSET[36]_set/clr ,Set/Clear Influence on Error Pin 36 (FMC - uncorrectable error)" "No influence,Influence" textline " " setclrfld.long 0x00 3. 0x00 3. 0x04 3. " IEPSET[35]_set/clr ,Set/Clear Influence on Error Pin 35 (FMC - correctable error)" "No influence,Influence" width 8. group.long 0x48++0x3 line.long 0x0 "IESR4,Interrupt Enable Set/Status Register 4" setclrfld.long 0x00 9. 0x00 9. 0x04 9. " INTENSET[41]_set/clr ,Set/Clear Interrupt Enable Pin 41 (eFuse farm - self test error)" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x04 8. " INTENSET[40]_set/clr ,Set/Clear Interrupt Enable Pin 40 (eFuse Controller Error)" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x00 5. 0x04 5. " INTENSET[37]_set/clr ,Set/Clear Interrupt Enable Pin 37 (IOMM - mux configuration error)" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x04 4. " INTENSET[36]_set/clr ,Set/Clear Interrupt Enable Pin 36 (FMC - uncorrectable error)" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. 0x00 3. 0x04 3. " INTENSET[35]_set/clr ,Set/Clear Interrupt Enable Pin 35 (FMC - correctable error)" "Disabled,Enabled" width 8. group.long 0x50++0x3 line.long 0x0 "ILSR4,Interrupt Level Set/Status Register 4" setclrfld.long 0x00 9. 0x00 9. 0x04 9. " INTLVLSET[41]_set/clr ,Set/Clear Interrupt Level Pin 41 (eFuse farm - self test error)" "Low,High" setclrfld.long 0x00 8. 0x00 8. 0x04 8. " INTLVLSET[40]_set/clr ,Set/Clear Interrupt Level Pin 40 (eFuse Controller Error)" "Low,High" textline " " setclrfld.long 0x00 5. 0x00 5. 0x04 5. " INTLVLSET[37]_set/clr ,Set/Clear Interrupt Level Pin 37 (IOMM - mux configuration error)" "Low,High" setclrfld.long 0x00 4. 0x00 4. 0x04 4. " INTLVLSET[36]_set/clr ,Set/Clear Interrupt Level Pin 36 (FMC - uncorrectable error)" "Low,High" textline " " setclrfld.long 0x00 3. 0x00 3. 0x04 3. " INTLVLSET[35]_set/clr ,Set/Clear Interrupt Level Pin 35 (FMC - correctable error)" "Low,High" width 8. group.long 0x58++0x3 line.long 0x0 "SR4,Status Register 4" eventfld.long 0x00 9. " INTLVLSET[41]_set/clr ,Error Status Flag 41 (eFuse farm - self test error)" "No error,Error" eventfld.long 0x00 8. " INTLVLSET[40]_set/clr ,Error Status Flag 40 (eFuse Controller Error)" "No error,Error" textline " " eventfld.long 0x00 5. " INTLVLSET[37]_set/clr ,Error Status Flag 37 (IOMM - mux configuration error)" "No error,Error" eventfld.long 0x00 4. " INTLVLSET[36]_set/clr ,Error Status Flag 36 (FMC - uncorrectable error)" "No error,Error" textline " " eventfld.long 0x00 3. " INTLVLSET[35]_set/clr ,Error Status Flag 35 (FMC - correctable error)" "No error,Error" width 0xb tree.end else tree "ESM (Error Signaling Module)" base ad:0xFFFFF500 width 8. group.long 0x00++0x3 line.long 0x0 "EEPAPR1,Enable Error Pin Action/Response Register 1" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " IEPSET[31]_set/clr ,Set/Clear Influence on Error Pin 31 (CCM-R4 - selftest)" "No influence,Influence" setclrfld.long 0x00 30. 0x00 30. 0x04 30. " IEPSET[30]_set/clr ,Set/Clear Influence on Error Pin 30 (DCC1 - error)" "No influence,Influence" textline " " setclrfld.long 0x00 28. 0x00 28. 0x04 28. " IEPSET[28]_set/clr ,Set/Clear Influence on Error Pin 28 (RAM odd bank (B1TCM))" "No influence,Influence" setclrfld.long 0x00 27. 0x00 27. 0x04 27. " IEPSET[27]_set/clr ,Set/Clear Influence on Error Pin 27 (CPU - selftest)" "No influence,Influence" textline " " setclrfld.long 0x00 26. 0x00 26. 0x04 26. " IEPSET[26]_set/clr ,Set/Clear Influence on Error Pin 26 (RAM even bank (B0TCM)) - correctable error)" "No influence,Influence" setclrfld.long 0x00 24. 0x00 24. 0x04 24. " IEPSET[24]_set/clr ,Set/Clear Influence on Error Pin 24 (MibSPIP5 - parity)" "No influence,Influence" textline " " setclrfld.long 0x00 23. 0x00 23. 0x04 23. " IEPSET[23]_set/clr ,Set/Clear Influence on Error Pin 23 (DCAN2 - parity)" "No influence,Influence" setclrfld.long 0x00 22. 0x00 22. 0x04 22. " IEPSET[22]_set/clr ,Set/Clear Influence on Error Pin 22 (DCAN3 - parity)" "No influence,Influence" textline " " setclrfld.long 0x00 21. 0x00 21. 0x04 21. " IEPSET[21]_set/clr ,Set/Clear Influence on Error Pin 21 (DCAN1 - parity)" "No influence,Influence" setclrfld.long 0x00 19. 0x00 19. 0x04 19. " IEPSET[19]_set/clr ,Set/Clear Influence on Error Pin 19 (MibADC1 - parity)" "No influence,Influence" textline " " setclrfld.long 0x00 18. 0x00 18. 0x04 18. " IEPSET[18]_set/clr ,Set/Clear Influence on Error Pin 18 (MibSPI3 - parity)" "No influence,Influence" setclrfld.long 0x00 17. 0x00 17. 0x04 17. " IEPSET[17]_set/clr ,Set/Clear Influence on Error Pin 17 (MibSPI1 - parity)" "No influence,Influence" textline " " setclrfld.long 0x00 15. 0x00 15. 0x04 15. " IEPSET[15]_set/clr ,Set/Clear Influence on Error Pin 15 (VIM RAM - parity)" "No influence,Influence" setclrfld.long 0x00 13. 0x00 13. 0x04 13. " IEPSET[13]_set/clr ,Set/Clear Influence on Error Pin 13 (DMA - imprecise write error)" "No influence,Influence" textline " " setclrfld.long 0x00 11. 0x00 11. 0x04 11. " IEPSET[11]_set/clr ,Set/Clear Influence on Error Pin 11 (Clock Monitor - interrupt)" "No influence,Influence" setclrfld.long 0x00 10. 0x00 10. 0x04 10. " IEPSET[10]_set/clr ,Set/Clear Influence on Error Pin 10 (PLL - Slip)" "No influence,Influence" textline " " setclrfld.long 0x00 9. 0x00 9. 0x04 9. " IEPSET[9]_set/clr ,Set/Clear Influence on Error Pin 9 (HET TU1/HET TU2 - MPU)" "No influence,Influence" setclrfld.long 0x00 8. 0x00 8. 0x04 8. " IEPSET[8]_set/clr ,Set/Clear Influence on Error Pin 8 (HET TU1/HET TU2 - parity)" "No influence,Influence" textline " " setclrfld.long 0x00 7. 0x00 7. 0x04 7. " IEPSET[7]_set/clr ,Set/Clear Influence on Error Pin 7 (N2HET1/N2HET2 - parity)" "No influence,Influence" setclrfld.long 0x00 6. 0x00 6. 0x04 6. " IEPSET[6]_set/clr ,Set/Clear Influence on Error Pin 6 (FMC - correctable error) - correctable error)" "No influence,Influence" textline " " setclrfld.long 0x00 5. 0x00 5. 0x04 5. " IEPSET[5]_set/clr ,Set/Clear Influence on Error Pin 5 (DMA - imprecise read error)" "No influence,Influence" setclrfld.long 0x00 3. 0x00 3. 0x04 3. " IEPSET[3]_set/clr ,Set/Clear Influence on Error Pin 3 (DMA - parity)" "No influence,Influence" textline " " setclrfld.long 0x00 2. 0x00 2. 0x04 2. " IEPSET[2]_set/clr ,Set/Clear Influence on Error Pin 2 (DMA - MPU)" "No influence,Influence" setclrfld.long 0x00 1. 0x00 1. 0x04 1. " IEPSET[1]_set/clr ,Set/Clear Influence on Error Pin 1 (MibADC2 - parity)" "No influence,Influence" width 8. group.long 0x08++0x3 line.long 0x0 "IESR1,Interrupt Enable Set/Status Register 1" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTENSET[31]_set/clr ,Set/Clear Interrupt Enable 31 (CCM-R4 - selftest)" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x04 30. " INTENSET[30]_set/clr ,Set/Clear Interrupt Enable 30 (DCC1 - error)" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x04 28. " INTENSET[28]_set/clr ,Set/Clear Interrupt Enable 28 (RAM odd bank (B1TCM))" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x04 27. " INTENSET[27]_set/clr ,Set/Clear Interrupt Enable 27 (CPU - selftest)" "Disabled,Enabled" textline " " setclrfld.long 0x00 26. 0x00 26. 0x04 26. " INTENSET[26]_set/clr ,Set/Clear Interrupt Enable 26 (RAM even bank (B0TCM))" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x04 24. " INTENSET[24]_set/clr ,Set/Clear Interrupt Enable 24 (MibSPIP5 - parity)" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. 0x00 23. 0x04 23. " INTENSET[23]_set/clr ,Set/Clear Interrupt Enable 23 (DCAN2 - parity)" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x04 22. " INTENSET[22]_set/clr ,Set/Clear Interrupt Enable 22 (DCAN3 - parity)" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. 0x00 21. 0x04 21. " INTENSET[21]_set/clr ,Set/Clear Interrupt Enable 21 (DCAN1 - parity)" "Disabled,Enabled" setclrfld.long 0x00 19. 0x00 19. 0x04 19. " INTENSET[19]_set/clr ,Set/Clear Interrupt Enable 19 (MibADC1 - parity)" "Disabled,Enabled" textline " " setclrfld.long 0x00 18. 0x00 18. 0x04 18. " INTENSET[18]_set/clr ,Set/Clear Interrupt Enable 18 (MibSPI3 - parity)" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x04 17. " INTENSET[17]_set/clr ,Set/Clear Interrupt Enable 17 (MibSPI1 - parity)" "Disabled,Enabled" textline " " setclrfld.long 0x00 15. 0x00 15. 0x04 15. " INTENSET[15]_set/clr ,Set/Clear Interrupt Enable 15 (VIM RAM - parity)" "Disabled,Enabled" setclrfld.long 0x00 13. 0x00 13. 0x04 13. " INTENSET[13]_set/clr ,Set/Clear Interrupt Enable 13 (DMA - imprecise write error)" "Disabled,Enabled" textline " " setclrfld.long 0x00 11. 0x00 11. 0x04 11. " INTENSET[11]_set/clr ,Set/Clear Interrupt Enable 11 (Clock Monitor - interrupt)" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x04 10. " INTENSET[10]_set/clr ,Set/Clear Interrupt Enable 10 (PLL - slip)" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. 0x00 9. 0x04 9. " INTENSET[9]_set/clr ,Set/Clear Interrupt Enable 9 (HET TU1/HET TU2 - MPU)" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x04 8. " INTENSET[8]_set/clr ,Set/Clear Interrupt Enable 8 (HET TU1/HET TU2 - parity)" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x04 7. " INTENSET[7]_set/clr ,Set/Clear Interrupt Enable 7 (N2HET1/N2HET2 - parity)" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x04 6. " INTENSET[6]_set/clr ,Set/Clear Interrupt Enable 6 (FMC - correctable error) - correctable error)" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x00 5. 0x04 5. " INTENSET[5]_set/clr ,Set/Clear Interrupt Enable 5 (DMA - imprecise read error)" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x04 3. " INTENSET[3]_set/clr ,Set/Clear Interrupt Enable 3 (DMA - parity)" "Disabled,Enabled" textline " " setclrfld.long 0x00 2. 0x00 2. 0x04 2. " INTENSET[2]_set/clr ,Set/Clear Interrupt Enable 2 (DMA - MPU)" "Disabled,Enabled" setclrfld.long 0x00 1. 0x00 1. 0x04 1. " INTENSET[1]_set/clr ,Set/Clear Interrupt Enable 1 (MibADC2 - parity)" "Disabled,Enabled" width 8. group.long 0x10++0x3 line.long 0x0 "ILSR1,Interrupt Level Set/Status Register 1" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTLVLSET_set/clr[31] ,Set/Clear Interrupt Level 31 (CCM-R4 - selftest)" "Low,High" setclrfld.long 0x00 30. 0x00 30. 0x04 30. " INTLVLSET_set/clr[30] ,Set/Clear Interrupt Level 30 (DCC1 - error)" "Low,High" textline " " setclrfld.long 0x00 28. 0x00 28. 0x04 28. " INTLVLSET_set/clr[28] ,Set/Clear Interrupt Level 28 (RAM odd bank (B1TCM))" "Low,High" setclrfld.long 0x00 27. 0x00 27. 0x04 27. " INTLVLSET_set/clr[27] ,Set/Clear Interrupt Level 27 (CPU - selftest)" "Low,High" textline " " setclrfld.long 0x00 26. 0x00 26. 0x04 26. " INTLVLSET_set/clr[26] ,Set/Clear Interrupt Level 26 (RAM even bank (B0TCM))" "Low,High" setclrfld.long 0x00 24. 0x00 24. 0x04 24. " INTLVLSET_set/clr[24] ,Set/Clear Interrupt Level 24 (MibSPIP5 - parity)" "Low,High" textline " " setclrfld.long 0x00 23. 0x00 23. 0x04 23. " INTLVLSET_set/clr[23] ,Set/Clear Interrupt Level 23 (DCAN2 - parity)" "Low,High" setclrfld.long 0x00 22. 0x00 22. 0x04 22. " INTLVLSET_set/clr[22] ,Set/Clear Interrupt Level 22 (DCAN3 - parity)" "Low,High" textline " " setclrfld.long 0x00 21. 0x00 21. 0x04 21. " INTLVLSET_set/clr[21] ,Set/Clear Interrupt Level 21 (DCAN1 - parity)" "Low,High" setclrfld.long 0x00 19. 0x00 19. 0x04 19. " INTLVLSET_set/clr[19] ,Set/Clear Interrupt Level 19 (MibADC1 - parity)" "Low,High" textline " " setclrfld.long 0x00 18. 0x00 18. 0x04 18. " INTLVLSET_set/clr[18] ,Set/Clear Interrupt Level 18 (MibSPI3 - parity)" "Low,High" setclrfld.long 0x00 17. 0x00 17. 0x04 17. " INTLVLSET_set/clr[17] ,Set/Clear Interrupt Level 17 (MibSPI1 - parity)" "Low,High" textline " " setclrfld.long 0x00 15. 0x00 15. 0x04 15. " INTLVLSET_set/clr[15] ,Set/Clear Interrupt Level 15 (VIM RAM - parity)" "Low,High" setclrfld.long 0x00 13. 0x00 13. 0x04 13. " INTLVLSET_set/clr[13] ,Set/Clear Interrupt Level 13 (DMA - imprecise write error)" "Low,High" textline " " setclrfld.long 0x00 11. 0x00 11. 0x04 11. " INTLVLSET_set/clr[11] ,Set/Clear Interrupt Level 11 (Clock Monitor - interrupt)" "Low,High" setclrfld.long 0x00 10. 0x00 10. 0x04 10. " INTLVLSET_set/clr[10] ,Set/Clear Interrupt Level 10 (PLL - slip)" "Low,High" textline " " setclrfld.long 0x00 9. 0x00 9. 0x04 9. " INTLVLSET_set/clr[9] ,Set/Clear Interrupt Level 9 (HET TU1/HET TU2 - MPU)" "Low,High" setclrfld.long 0x00 8. 0x00 8. 0x04 8. " INTLVLSET_set/clr[8] ,Set/Clear Interrupt Level 8 (HET TU1/HET TU2 - parity)" "Low,High" textline " " setclrfld.long 0x00 7. 0x00 7. 0x04 7. " INTLVLSET_set/clr[7] ,Set/Clear Interrupt Level 7 (N2HET1/N2HET2 - parity)" "Low,High" setclrfld.long 0x00 6. 0x00 6. 0x04 6. " INTLVLSET_set/clr[6] ,Set/Clear Interrupt Level 6 (FMC - correctable error)" "Low,High" textline " " setclrfld.long 0x00 5. 0x00 5. 0x04 5. " INTLVLSET_set/clr[5] ,Set/Clear Interrupt Level 5 (DMA - imprecise read error)" "Low,High" setclrfld.long 0x00 3. 0x00 3. 0x04 3. " INTLVLSET_set/clr[3] ,Set/Clear Interrupt Level 3 (DMA - parity)" "Low,High" textline " " setclrfld.long 0x00 2. 0x00 2. 0x04 2. " INTLVLSET_set/clr[2] ,Set/Clear Interrupt Level 2 (DMA - MPU)" "Low,High" setclrfld.long 0x00 1. 0x00 1. 0x04 1. " INTLVLSET_set/clr[1] ,Set/Clear Interrupt Level 1 (MibADC2 - parity)" "Low,High" width 8. group.long 0x18++0x3 line.long 0x0 "SR1,Status Register 1" eventfld.long 0x00 31. " ESF[31] ,Error Status Flag 31 (CCM-R4 - selftest)" "No error,Error" eventfld.long 0x00 30. " ESF[30] ,Error Status Flag 30 (DCC1 - error)" "No error,Error" textline " " eventfld.long 0x00 28. " ESF[28] ,Error Status Flag 28 (RAM odd bank (B1TCM))" "No error,Error" eventfld.long 0x00 27. " ESF[27] ,Error Status Flag 27 (CPU - selftest)" "No error,Error" eventfld.long 0x00 26. " ESF[26] ,Error Status Flag 26 (RAM even bank (B0TCM))" "No error,Error" textline " " eventfld.long 0x00 24. " ESF[24] ,Error Status Flag 24 (MibSPIP5 - parity)" "No error,Error" eventfld.long 0x00 23. " ESF[23] ,Error Status Flag 23 (DCAN2 - parity)" "No error,Error" eventfld.long 0x00 22. " ESF[22] ,Error Status Flag 22 (DCAN3 - parity)" "No error,Error" eventfld.long 0x00 21. " ESF[21] ,Error Status Flag 21 (DCAN1 - parity)" "No error,Error" textline " " eventfld.long 0x00 19. " ESF[19] ,Error Status Flag 19 (MibADC1 - parity)" "No error,Error" eventfld.long 0x00 18. " ESF[18] ,Error Status Flag 18 (MibSPI3 - parity)" "No error,Error" eventfld.long 0x00 17. " ESF[17] ,Error Status Flag 17 (MibSPI1 - parity)" "No error,Error" textline " " eventfld.long 0x00 15. " ESF[15] ,Error Status Flag 15 (VIM RAM - parity)" "No error,Error" eventfld.long 0x00 13. " ESF[13] ,Error Status Flag 13 (DMA - imprecise write error)" "No error,Error" textline " " eventfld.long 0x00 11. " ESF[11] ,Error Status Flag 11 (Clock Monitor - interrupt)" "No error,Error" eventfld.long 0x00 10. " ESF[10] ,Error Status Flag 10 (PLL - slip)" "No error,Error" eventfld.long 0x00 9. " ESF[9] ,Error Status Flag 9 (HET TU1/HET TU2 - MPU)" "No error,Error" eventfld.long 0x00 8. " ESF[8] ,Error Status Flag 8 (HET TU1/HET TU2 - parity)" "No error,Error" textline " " eventfld.long 0x00 7. " ESF[7] ,Error Status Flag 7 (N2HET1/N2HET2 - parity)" "No error,Error" eventfld.long 0x00 6. " ESF[6] ,Error Status Flag 6 (FMC - correctable error)" "No error,Error" eventfld.long 0x00 5. " ESF[5] ,Error Status Flag 5 (DMA - imprecise read error)" "No error,Error" eventfld.long 0x00 3. " ESF[3] ,Error Status Flag 3 (DMA - parity)" "No error,Error" textline " " eventfld.long 0x00 2. " ESF[2] ,Error Status Flag 2 (DMA - MPU)" "No error,Error" eventfld.long 0x00 1. " ESF[1] ,Error Status Flag 1 (MibADC2 - parity)" "No error,Error" group.long 0x1C++0x3 line.long 0x0 "SR2,Status Register 2" eventfld.long 0x00 24. " ESF[24] ,Error Status Flag 24 (RTI_WWD_NMI)" "No error,Error" eventfld.long 0x00 16. " ESF[16] ,Error Status Flag 16 (Flash (ATCM) - ECC live lock detect)" "No error,Error" eventfld.long 0x00 12. " ESF[12] ,Error Status Flag 12 (B1TCM - address bus parity error)" "No error,Error" eventfld.long 0x00 10. " ESF[10] ,Error Status Flag 10 (B0TCM - address bus parity error)" "No error,Error" textline " " eventfld.long 0x00 8. " ESF[8] ,Error Status Flag 8 (B1TCM - uncorrectable error)" "No error,Error" eventfld.long 0x00 6. " ESF[6] ,Error Status Flag 6 (B0TCM - uncorrectable error)" "No error,Error" eventfld.long 0x00 4. " ESF[4] ,Error Status Flag 4 (FMC - uncorrectable error)" "No error,Error" eventfld.long 0x00 2. " ESF[2] ,Error Status Flag 2 (CCM-R4 - compare)" "No error,Error" group.long 0x20++0x3 line.long 0x0 "SR3,Status Register 3" eventfld.long 0x00 7. " ESF[7] ,Error Status Flag 7 (FMC - uncorrectable error)" "No error,Error" eventfld.long 0x00 5. " ESF[5] ,Error Status Flag 5 (B1TCM - ECC uncorrectable error)" "No error,Error" eventfld.long 0x00 3. " ESF[3] ,Error Status Flag 3 (B0TCM - ECC uncorrectable error)" "No error,Error" eventfld.long 0x00 1. " ESF[1] ,Error Status Flag 1 (eFuse Controller - autoload error)" "No error,Error" width 8. rgroup.long 0x24++0x3 line.long 0x0 "EPSR,Error Pin Status Register" bitfld.long 0x00 0. " EPSF ,Error Pin Status Flag" "Active,Not active" rgroup.long 0x28++0x3 line.long 0x0 "IOFFHR,Interrupt Offset High Register" hexmask.long.byte 0x00 0.--6. 1. " INTOFFH ,Offset High Level Interrupt" rgroup.long 0x2C++0x3 line.long 0x0 "IOFFLR,Interrupt Offset Low Register" hexmask.long.byte 0x00 0.--6. 1. " INTOFFL ,Offset Low Level Interrupt" rgroup.long 0x30++0x3 line.long 0x0 "LTCR,Low-Time Counter Register" hexmask.long.word 0x00 0.--15. 1. " LTC ,Error Pin Low-Time Counter" group.long 0x34++0x3 line.long 0x0 "LTCPR,Low-Time Counter Preload Register" bitfld.long 0x00 14.--15. " LTCP[15:14] ,Low-Time Counter Pre-load Value [15:14]" "0,1,2,3" hexmask.long.word 0x00 0.--13. 1. " LTCP[13:0] ,Low-Time Counter Pre-load Value [13:0]" group.long 0x38++0x3 line.long 0x0 "EKR,Error Key Register" bitfld.long 0x00 0.--3. " EKEY ,Error Key" "Normal,Normal,Normal,Normal,Normal,LTC,Normal,Normal,Normal,Normal,Forced,Normal,Normal,Normal,Normal,Normal" width 8. group.long 0x3C++0x3 line.long 0x0 "SSR2,Status Shadow Register" eventfld.long 0x00 24. " ESF[24] ,Error Status Flag 24 (RTI_WWD_NMI)" "No error,Error" eventfld.long 0x00 16. " ESF[16] ,Error Status Flag 16 (Flash (ATCM) - ECC live lock detect)" "No error,Error" eventfld.long 0x00 12. " ESF[12] ,Error Status Flag 12 (B1TCM - address bus parity error)" "No error,Error" eventfld.long 0x00 10. " ESF[10] ,Error Status Flag 10 (B0TCM - address bus parity error)" "No error,Error" textline " " eventfld.long 0x00 8. " ESF[8] ,Error Status Flag 8 (B1TCM - uncorrectable error)" "No error,Error" eventfld.long 0x00 6. " ESF[6] ,Error Status Flag 6 (B0TCM - uncorrectable error)" "No error,Error" eventfld.long 0x00 4. " ESF[4] ,Error Status Flag 4 (Flash (ATCM) - uncorrectable error)" "No error,Error" eventfld.long 0x00 2. " ESF[2] ,Error Status Flag 2 (CCM-R4 - compare)" "No error,Error" width 8. group.long 0x40++0x3 line.long 0x0 "IEPSR4,Influence Error Pin Set/Status Register 4" setclrfld.long 0x00 30. 0x00 30. 0x04 30. " IEPSET[62]_set/clr ,Set/Clear Influence on Error Pin 62 (DCC2 - error)" "No influence,Influence" textline " " sif (cpu()=="RM48L952-PGE"||cpu()=="RM48L952-ZWT"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE"||cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE"||cpu()=="RM48L550-ZWT") setclrfld.long 0x00 12. 0x00 12. 0x04 12. " IEPSET[44]_set/clr ,Set/Clear Influence on Error Pin 44 (USB Host Controller master interface)" "No influence,Influence" textline " " endif setclrfld.long 0x00 11. 0x00 11. 0x04 11. " IEPSET[43]_set/clr ,Set/Clear Influence on Error Pin 43 (Ethernet Controller master interface)" "No influence,Influence" textline " " setclrfld.long 0x00 10. 0x00 10. 0x04 10. " IEPSET[42]_set/clr ,Set/Clear Influence on Error Pin 42 (PLL2 - slip)" "No influence,Influence" setclrfld.long 0x00 9. 0x00 9. 0x04 9. " IEPSET[41]_set/clr ,Set/Clear Influence on Error Pin 41 (eFuse Controller - self test error)" "No influence,Influence" textline " " setclrfld.long 0x00 8. 0x00 8. 0x04 8. " IEPSET[40]_set/clr ,Set/Clear Influence on Error Pin 40 (eFuse Controller Error)" "No influence,Influence" setclrfld.long 0x00 7. 0x00 7. 0x04 7. " IEPSET[39]_set/clr ,Set/Clear Influence on Error Pin 39 (Power domain controller self-test error)" "No influence,Influence" textline " " setclrfld.long 0x00 6. 0x00 6. 0x04 6. " IEPSET[38]_set/clr ,Set/Clear Influence on Error Pin 38 (Power domain controller compare error)" "No influence,Influence" setclrfld.long 0x00 5. 0x00 5. 0x04 5. " IEPSET[37]_set/clr ,Set/Clear Influence on Error Pin 37 (IOMM - mux configuration error)" "No influence,Influence" textline " " setclrfld.long 0x00 4. 0x00 4. 0x04 4. " IEPSET[36]_set/clr ,Set/Clear Influence on Error Pin 36 (FMC - uncorrectable error)" "No influence,Influence" setclrfld.long 0x00 3. 0x00 3. 0x04 3. " IEPSET[35]_set/clr ,Set/Clear Influence on Error Pin 35 (FMC - correctable error)" "No influence,Influence" width 8. group.long 0x48++0x3 line.long 0x0 "IESR4,Interrupt Enable Set/Status Register 4" setclrfld.long 0x00 30. 0x00 30. 0x04 30. " INTENSET[62]_set/clr ,Set/Clear Interrupt Enable Pin 62 (DCC2 - error)" "Disabled,Enabled" textline " " sif (cpu()=="RM48L952-PGE"||cpu()=="RM48L952-ZWT"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE"||cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE"||cpu()=="RM48L550-ZWT") setclrfld.long 0x00 12. 0x00 12. 0x04 12. " INTENSET[44]_set/clr ,Set/Clear Interrupt Enable Pin 44 (USB Host Controller master interface)" "Disabled,Enabled" textline " " endif setclrfld.long 0x00 11. 0x00 11. 0x04 11. " INTENSET[43]_set/clr ,Set/Clear Interrupt Enable Pin 43 (Ethernet Controller master interface)" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x04 10. " INTENSET[42]_set/clr ,Set/Clear Interrupt Enable Pin 42 (PLL2 - slip)" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x04 9. " INTENSET[41]_set/clr ,Set/Clear Interrupt Enable Pin 41 (eFuse Controller - self test error)" "Disabled,Enabled" textline " " setclrfld.long 0x00 8. 0x00 8. 0x04 8. " INTENSET[40]_set/clr ,Set/Clear Interrupt Enable Pin 40 (eFuse Controller Error)" "Disabled,Enabled" setclrfld.long 0x00 7. 0x00 7. 0x04 7. " INTENSET[39]_set/clr ,Set/Clear Interrupt Enable Pin 39 (Power domain controller self-test error)" "Disabled,Enabled" textline " " setclrfld.long 0x00 6. 0x00 6. 0x04 6. " INTENSET[38]_set/clr ,Set/Clear Interrupt Enable Pin 38 (Power domain controller compare error)" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x04 5. " INTENSET[37]_set/clr ,Set/Clear Interrupt Enable Pin 37 (IOMM - mux configuration error)" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x04 4. " INTENSET[36]_set/clr ,Set/Clear Interrupt Enable Pin 36 (FMC - uncorrectable error)" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x04 3. " INTENSET[35]_set/clr ,Set/Clear Interrupt Enable Pin 35 (FMC - correctable error)" "Disabled,Enabled" width 8. group.long 0x50++0x3 line.long 0x0 "ILSR4,Interrupt Level Set/Status Register 4" setclrfld.long 0x00 30. 0x00 30. 0x04 30. " INTLVLSET[62]_set/clr ,Set/Clear Interrupt Level Pin 62 (DCC2 - error)" "Low,High" textline " " sif (cpu()=="RM48L952-PGE"||cpu()=="RM48L952-ZWT"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE"||cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE"||cpu()=="RM48L550-ZWT") setclrfld.long 0x00 12. 0x00 12. 0x04 12. " INTLVLSET[44]_set/clr ,Set/Clear Interrupt Level Pin 44 (USB Host Controller master interface)" "Low,High" textline " " endif sif (cpu()=="RM48L952-PGE"||cpu()=="RM48L952-ZWT"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L540-PGE"||cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM48L550-ZWT") setclrfld.long 0x00 11. 0x00 11. 0x04 11. " INTLVLSET[43]_set/clr ,Set/Clear Interrupt Level Pin 43 (Ethernet Controller master interface)" "Low,High" endif textline " " setclrfld.long 0x00 10. 0x00 10. 0x04 10. " INTLVLSET[42]_set/clr ,Set/Clear Interrupt Level Pin 42 (PLL2 - slip)" "Low,High" setclrfld.long 0x00 9. 0x00 9. 0x04 9. " INTLVLSET[41]_set/clr ,Set/Clear Interrupt Level Pin 41 (eFuse Controller - self test error)" "Low,High" textline " " setclrfld.long 0x00 8. 0x00 8. 0x04 8. " INTLVLSET[40]_set/clr ,Set/Clear Interrupt Level Pin 40 (eFuse Controller Error)" "Low,High" setclrfld.long 0x00 7. 0x00 7. 0x04 7. " INTLVLSET[39]_set/clr ,Set/Clear Interrupt Level Pin 39 (Power domain controller self-test error)" "Low,High" textline " " setclrfld.long 0x00 6. 0x00 6. 0x04 6. " INTLVLSET[38]_set/clr ,Set/Clear Interrupt Level Pin 38 (Power domain controller compare error)" "Low,High" setclrfld.long 0x00 5. 0x00 5. 0x04 5. " INTLVLSET[37]_set/clr ,Set/Clear Interrupt Level Pin 37 (IOMM - mux configuration error)" "Low,High" textline " " setclrfld.long 0x00 4. 0x00 4. 0x04 4. " INTLVLSET[36]_set/clr ,Set/Clear Interrupt Level Pin 36 (FMC - uncorrectable error)" "Low,High" setclrfld.long 0x00 3. 0x00 3. 0x04 3. " INTLVLSET[35]_set/clr ,Set/Clear Interrupt Level Pin 35 (FMC - correctable error)" "Low,High" width 8. group.long 0x58++0x3 line.long 0x0 "SR4,Status Register 4" eventfld.long 0x00 30. " INTLVLSET[62]_set/clr ,Error Status Flag 62 (DCC2 - error)" "No error,Error" textline " " sif (cpu()=="RM48L952-PGE"||cpu()=="RM48L952-ZWT"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE"||cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE"||cpu()=="RM48L550-ZWT") eventfld.long 0x00 11. " INTLVLSET[44]_set/clr ,Error Status Flag 44 (USB Host Controller master interface)" "No error,Error" textline " " endif sif (cpu()=="RM48L952-PGE"||cpu()=="RM48L952-ZWT"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L540-PGE"||cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM48L550-ZWT") eventfld.long 0x00 11. " INTLVLSET[43]_set/clr ,Error Status Flag 43 (Ethernet Controller master interface)" "No error,Error" endif textline " " eventfld.long 0x00 10. " INTLVLSET[42]_set/clr ,Error Status Flag 42 (PLL2 - slip)" "No error,Error" eventfld.long 0x00 9. " INTLVLSET[41]_set/clr ,Error Status Flag 41 (eFuse Controller - self test error)" "No error,Error" textline " " eventfld.long 0x00 8. " INTLVLSET[40]_set/clr ,Error Status Flag 40 (eFuse Controller Error)" "No error,Error" eventfld.long 0x00 7. " INTLVLSET[39]_set/clr ,Error Status Flag 39 (Power domain controller self-test error)" "No error,Error" textline " " eventfld.long 0x00 6. " INTLVLSET[38]_set/clr ,Error Status Flag 38 (Power domain controller compare error)" "No error,Error" eventfld.long 0x00 5. " INTLVLSET[37]_set/clr ,Error Status Flag 37 (IOMM - mux configuration error)" "No error,Error" textline " " eventfld.long 0x00 4. " INTLVLSET[36]_set/clr ,Error Status Flag 36 (FMC - uncorrectable error)" "No error,Error" eventfld.long 0x00 3. " INTLVLSET[35]_set/clr ,Error Status Flag 35 (FMC - correctable error)" "No error,Error" width 0xb tree.end endif tree "RTI (Real Time Interrupt)" base ad:0xFFFFFC00 width 14. group.long 0x00++0x0F line.long 0x00 "GCTRL,Global Control Register" bitfld.long 0x00 16.--19. " NTUSEL ,Select NTU signal" "NTU0,0,0,0,0,NTU1,0,0,0,0,NTU2,0,0,0,0,NTU3" bitfld.long 0x00 15. " COS ,Continue on suspend" "Stopped,Continued" bitfld.long 0x00 1. " CNT1EN ,Counter 1 enable" "Stopped,Enabled" textline " " bitfld.long 0x00 0. " CNT0EN ,Counter 0 enable" "Stopped,Enabled" line.long 0x04 "TBCTRL,Timebase Control Register" bitfld.long 0x04 1. " INC ,Increment free running counter" "Not incremented,Incremented" bitfld.long 0x04 0. " TBEXT ,Time base external" "UC0,NTU" line.long 0x08 "CAPCTRL,Capture Control Register" bitfld.long 0x08 1. " CAPCNTR1 ,Capture counter 1" "CES 0,CES 1" bitfld.long 0x08 0. " CAPCNTR0 ,Capture counter 0" "CES 0,CES 1" line.long 0x0C "COMPCTRL,Compare Control Register" bitfld.long 0x0C 12. " COMPSEL3 ,Compare select 3" "FRC 0,FRC 1" bitfld.long 0x0C 8. " COMPSEL2 ,Compare select 2" "FRC 0,FRC 1" bitfld.long 0x0C 4. " COMPSEL1 ,Compare select 1" "FRC 0,FRC 1" textline " " bitfld.long 0x0C 0. " COMPSEL0 ,Compare select 0" "FRC 0,FRC 1" hgroup.long 0x10++0x03 hide.long 0x00 "FRC0,Free Running Counter 0 Register" in hgroup.long 0x14++0x03 hide.long 0x00 "UC0,Up Counter 0 Register" in group.long 0x18++0x03 line.long 0x00 "CPUC0,Compare Up Counter 0 Register" rgroup.long 0x20++0x03 line.long 0x00 "CAFRC0,Capture Free Running Counter 0 Register" sif (cpuis("RM57L843-ZWT")) hgroup.long 0x24++0x03 hide.long 0x00 "CAUC0,Capture Up Counter 0 Register" in else rgroup.long 0x24++0x03 line.long 0x00 "CAUC0,Capture Up Counter 0 Register" endif hgroup.long 0x30++0x03 hide.long 0x00 "FRC1,Free Running Counter 1 Register" in group.long 0x34++0x07 line.long 0x00 "UC1,Up Counter 1 Register" line.long 0x04 "CPUC1,Up Counter 1 Register" rgroup.long 0x40++0x03 line.long 0x00 "CAFRC1,Capture Free Running Counter 1 Register" sif (cpuis("RM57L843-ZWT")) rgroup.long 0x44++0x03 line.long 0x00 "CAUC1,Capture Up Counter 1 Register" else rgroup.long 0x44++0x03 line.long 0x00 "CAUC1,Capture Up Counter 1 Register" endif group.long 0x50++0x27 line.long 0x00 "COMP0,Compare 0 Register" line.long 0x04 "UDCP0,Update Compare 0 Register" line.long 0x08 "COMP1,Compare 1 Register" line.long 0x0C "UDCP1,Update Compare 1 Register" line.long 0x10 "COMP2,Compare 2 Register" line.long 0x14 "UDCP2,Update Compare 2 Register" line.long 0x18 "COMP3,Compare 3 Register" line.long 0x1C "UDCP3,Update Compare 3 Register" line.long 0x20 "TBLCOMP,External Clock Timebase Low Compare Register" line.long 0x24 "TBHCOMP,External Clock Timebase High Compare Register" group.long 0x80++0x03 line.long 0x00 "SETINT,Set/status Interrupt Register" setclrfld.long 0x00 18. 0x00 18. 0x04 18. " SETOVL1INT_SET/CLR ,Free running counter 1 overflow interrupt" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x04 17. " SETOVL0INT_SET/CLR ,Free running counter 0 overflow interrupt" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x04 16. " SETTBINT_SET/CLR ,Timebase interrupt" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x04 11. " SETDMA3_SET/CLR ,Compare DMA request 3" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x04 10. " SETDMA2_SET/CLR ,Compare DMA request 2" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x04 9. " SETDMA1_SET/CLR ,Compare DMA request 1" "Disabled,Enabled" textline " " setclrfld.long 0x00 8. 0x00 8. 0x04 8. " SETDMA0_SET/CLR ,Compare DMA request 0" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x04 3. " SETINT3_SET/CLR ,Compare interrupt 3" "Disabled,Enabled" textline " " setclrfld.long 0x00 2. 0x00 2. 0x04 2. " SETINT2_SET/CLR ,Compare interrupt 2" "Disabled,Enabled" setclrfld.long 0x00 1. 0x00 1. 0x04 1. " SETINT1_SET/CLR ,Compare interrupt 1" "Disabled,Enabled" textline " " setclrfld.long 0x00 0. 0x00 0. 0x04 0. " SETINT0_SET/CLR ,Compare interrupt 0" "Disabled,Enabled" group.long 0x88++0x03 line.long 0x00 "INTFLAG,Interrupt Flag Register" eventfld.long 0x00 18. " OVL1INT ,Free running counter 1 overflow interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 17. " OVL0INT ,Free running counter 0 overflow interrupt flag" "No interrupt,Interrupt" eventfld.long 0x00 16. " TBINT ,Timebase interrupt flag" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " INT3 ,Interrupt flag 3" "No interrupt,Interrupt" eventfld.long 0x00 2. " INT2 ,Interrupt flag 2" "No interrupt,Interrupt" eventfld.long 0x00 1. " INT1 ,Interrupt flag 1" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " INT0 ,Interrupt flag 0" "No interrupt,Interrupt" group.long 0x90++0x13 line.long 0x00 "DWDCTRL,Digital Watchdog Control Register" line.long 0x04 "DWDPRLD,Digital Watchdog Preload Register" hexmask.long.word 0x04 0.--11. 1. " DWDPRLD ,Digital watchdog preload value" line.long 0x08 "WDSTATUS,Watchdog Status Register" eventfld.long 0x08 5. " DWWD_ST ,Windowed watchdog status" "No effect,Time-window violation" eventfld.long 0x08 4. " END_TIME_VIOL ,Windowed watchdog end time violation status" "Not occurred,Occurred" eventfld.long 0x08 3. " START_TIME_VIOL ,Windowed watchdog start time violation status" "Not occurred,Occurred" textline " " eventfld.long 0x08 2. " KEYST ,Watchdog key status" "No reset,Reset" eventfld.long 0x08 1. " DWDST ,Digital watchdog status" "No wrong key,Wrong key" line.long 0x0C "WDKEY,Watchdog Key Register" hexmask.long.word 0x0C 0.--15. 1. " WDKEY ,Watchdog key" line.long 0x10 "WDCNTR,Digital Watchdog Down Counter" hexmask.long 0x10 0.--24. 1. " DWDCNTR ,Digital watchdog down counter" group.long 0xA4++0x07 line.long 0x00 "WWDRXNCTRL,Digital Windowed Watchdog Reaction Control" bitfld.long 0x00 0.--3. " WWDRXN ,The DWWD reaction" "Reset,Reset,Reset,Reset,Reset,Reset,Reset,Reset,Reset,Reset,Interrupt,Reset,Reset,Reset,Reset,Reset" line.long 0x04 "WWDSIZECTRL,Digital Windowed Watchdog Window Size Control" sif (cpuis("RM57L843-ZWT")) group.long 0xAC++0x13 line.long 0x00 "INTCLRENABLE,INTCLRENABLE" bitfld.long 0x00 24.--27. " INTCLRENABLE3 ,Auto-clear on the compare 3 interrupt" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.long 0x00 16.--19. " INTCLRENABLE2 ,Auto-clear on the compare 2 interrupt" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" textline " " bitfld.long 0x00 8.--11. " INTCLRENABLE1 ,Auto-clear on the compare 1 interrupt" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" bitfld.long 0x00 0.--3. " INTCLRENABLE0 ,Auto-clear on the compare 0 interrupt" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" line.long 0x04 "COMP0CLR,RTICOMP0CLR" line.long 0x08 "COMP1CLR,RTICOMP1CLR" line.long 0x0C "COMP2CLR,RTICOMP2CLR" line.long 0x10 "COMP3CLR,RTICOMP3CLR" else hgroup.long 0xAC++0x13 hide.long 0x00 "INTCLRENABLE,RTIINTCLRENABLE" hide.long 0x04 "COMP0CLR,RTICOMP0CLR" hide.long 0x08 "COMP1CLR,RTICOMP1CLR" hide.long 0x0C "COMP2CLR,RTICOMP2CLR" hide.long 0x10 "COMP3CLR,RTICOMP3CLR" endif width 0x0B tree.end sif (cpu()=="RM42L432") tree "CRC (Cyclic Redundancy Check Controller)" base ad:0xFE000000 width 20. group.long 0x0++0x3 line.long 0x0 "CRC_CTRL0,CRC Global Control Register 0" bitfld.long 0x00 8. " CH2_PSA_SWREST ,Channel 2 PSA Software Reset" "No reset,Reset" bitfld.long 0x00 0. " CH1_PSA_SWREST ,Channel 1 PSA Software Reset" "No reset,Reset" width 20. group.long 0x8++0x3 line.long 0x0 "CRC_CTRL1,CRC Global Control Register 1" bitfld.long 0x00 0. " PWDN ,Power Down" "Not powered down,Powered down" group.long 0x10++0x3 line.long 0x0 "CRC_CTRL2,CRC Global Control Register 2" bitfld.long 0x00 8.--9. " CH2_MODE ,Channel 2 Mode" "Data capture,Auto,Semi-CPU,Full-CPU" bitfld.long 0x00 4. " CH1_TRACEEN ,Channel 1 Data Trace Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " CH1_MODE ,Channel 1 Mode" "Data capture,Auto,Semi-CPU,Full-CPU" width 20. group.long 0x18++0x3 line.long 0x0 "CRC_INTS,Write One to a bit to Enable a Interrupt" bitfld.long 0x00 12. " CH2_TIMEOUTENS ,Channel 2 Timeout Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 11. " CH2_UNDERENS ,Channel 2 Underrun Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " CH2_OVERENS ,Channel 2 Overrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 9. " CH2_CRCFAILENS ,Channel 2 CRC Fail Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " CH2_CCITENS ,Channel 2 Compression Complete Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " CH1_TIMEOUTENS ,Channel 1 Timeout Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " CH1_UNDERENS ,Channel 1 Underrun Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. " CH1_OVERENS ,Channel 1 Overrun Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " CH1_CRCFAILENS ,Channel 1 CRC Fail Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " CH1_CCITENS ,Channel 1 Compression Complete Interrupt Enable" "Disabled,Enabled" width 20. group.long 0x20++0x3 line.long 0x0 "CRC_INTR,Write One to a bit to Disable a Interrupt" bitfld.long 0x00 12. " CH2_TIMEOUTENR ,Channel 2 Timeout Interrupt Disable" "No,Yes" bitfld.long 0x00 11. " CH2_UNDERENR ,Channel 2 Underrun Interrupt Disable" "No,Yes" textline " " bitfld.long 0x00 10. " CH2_OVERENR ,Channel 2 Overrun Interrupt Disable" "No,Yes" bitfld.long 0x00 9. " CH2_CRCFAILENR ,Channel 2 CRC Fail Interrupt Disable" "No,Yes" textline " " bitfld.long 0x00 8. " CH2_CCITENR ,Channel 2 Compression Complete Interrupt Disable" "No,Yes" bitfld.long 0x00 4. " CH1_TIMEOUTENR ,Channel 1 Timeout Interrupt Disable" "No,Yes" textline " " bitfld.long 0x00 3. " CH1_UNDERENR ,Channel 1 Underrun Interrupt Disable" "No,Yes" bitfld.long 0x00 2. " CH1_OVERENR ,Channel 1 Overrun Interrupt Disable" "No,Yes" textline " " bitfld.long 0x00 1. " CH1_CRCFAILENR ,Channel 1 CRC Fail Interrupt Disable" "No,Yes" bitfld.long 0x00 0. " CH1_CCITENR ,Channel 1 Compression Complete Interrupt Disable" "No,Yes" width 20. group.long 0x28++0x3 line.long 0x0 "CRC_STATUS,CRC Interrupt Status Register" eventfld.long 0x00 12. " CH2_TIMEOUT ,Channel 2 CRC Timeout Status Flag" "No interrupt,Interrupt" eventfld.long 0x00 11. " CH2_UNDER ,Channel 2 CRC Underrun Status Flag" "No interrupt,Interrupt" textline " " eventfld.long 0x00 10. " CH2_OVER ,Channel 2 CRC Overrun Status Flag" "No interrupt,Interrupt" eventfld.long 0x00 9. " CH2_CRCFAIL ,Channel 2 CRC Compare Fail Status Flag" "No interrupt,Interrupt" textline " " eventfld.long 0x00 8. " CH2_CCIT ,Channel 2 CRC Pattern Compression Complete Status Flag" "No interrupt,Interrupt" eventfld.long 0x00 4. " CH1_TIMEOUT ,Channel 1 CRC Timeout Status Flag" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " CH1_UNDER ,Channel 1 CRC Underrun Status Flag" "No interrupt,Interrupt" eventfld.long 0x00 2. " CH1_OVER ,Channel 1 CRC Overrun Status Flag" "No interrupt,Interrupt" textline " " eventfld.long 0x00 1. " CH1_CRCFAIL ,Channel 1 CRC Compare Fail Status Flag" "No interrupt,Interrupt" eventfld.long 0x00 0. " CH1_CCIT ,Channel 1 CRC Pattern Compression Complete Status Flag" "No interrupt,Interrupt" width 20. rgroup.long 0x30++0x3 line.long 0x0 "CRC_INT_OFFSET_REG,CRC Interrupt Offset Register" hexmask.long.byte 0x00 0.--7. 1. " OFSTREG ,CRC Interrupt Offset" rgroup.long 0x38++0x3 line.long 0x0 "CRC_BUSY,CRC Busy Register" bitfld.long 0x00 8. " CH2_BUSY ,Channel 2 Busy Flag" "Not busy,Busy" bitfld.long 0x00 0. " CH1_BUSY ,Channel 1 Busy Flag" "Not busy,Busy" rgroup.long 0x140++0x3 line.long 0x0 "MCRC_TRACE_BUS_SEL,Data Bus Selection Register" bitfld.long 0x00 2. " MEn ,Enable/disables the Tracing of VBUSM" "Disabled,Enabled" bitfld.long 0x00 1. " DTCMEn ,Enable/disables the Tracing of Data TCM" "Disabled,Enabled" bitfld.long 0x00 0. " ITCMEn ,Enable/disables the Tracing of Instruction TCM" "Disabled,Enabled" width 17. tree "CRC Channel 1 Registers" group.long 0x40++0x3 line.long 0x0 "CRC_PCOUNT_REG1,CRC Pattern Counter Preload Register 1" hexmask.long.tbyte 0x00 0.--19. 1. " CRC_PAT_COUNT1[19:0] ,Channel 1 Pattern Counter Preload" group.long 0x44++0x3 line.long 0x0 "CRC_SCOUNT_REG1,CRC Sector Counter Preload Register 1" hexmask.long.word 0x00 0.--15. 1. " CRC_SEC_COUNT1[15:0] ,Channel 1 Sector Counter Preload" hgroup.long 0x48++0x3 hide.long 0x0 "CRC_CURSEC_REG1,CRC Current Sector Register 1" in group.long 0x4C++0x3 line.long 0x0 "CRC_WDTOPLD1,Watchdog Timeout Preload Register" hexmask.long.tbyte 0x00 0.--23. 1. " CRC_WDTOPLD1[23:0] ,Channel 1 Watchdog Timeout Counter Preload" group.long 0x50++0x3 line.long 0x0 "CRC_BCTOPLD1,CRC Channel 1 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x00 0.--23. 1. " CRC_BCTOPLD1[23:0] ,Channel 1 Block Complete Timeout Counter Preload" group.long 0x60++0x3 line.long 0x0 "PSA_SIGREGL1,Channel 1 PSA Signature Low Register" group.long 0x64++0x3 line.long 0x0 "PSA_SIGREGH1,Channel 1 PSA Signature High Register" group.long 0x68++0x3 line.long 0x0 "CRC_REGL1,Channel 1 CRC Value Low Register" group.long 0x6C++0x3 line.long 0x0 "CRC_REGH1,Channel 1 CRC Value High Register" rgroup.long 0x70++0x3 line.long 0x0 "PSA_SECSIGREGL1,PSA Sector Signature Low Register 1" rgroup.long 0x74++0x3 line.long 0x0 "PSA_SECSIGREGH1,PSA Sector Signature High Register 1" rgroup.long 0x78++0x3 line.long 0x0 "RAW_DATAREGL1,Raw Data Low Register 1" rgroup.long 0x7C++0x3 line.long 0x0 "RAW_DATAREGH1,Raw Data High Register 1" tree.end width 17. tree "CRC Channel 2 Registers" group.long 0x80++0x3 line.long 0x0 "CRC_PCOUNT_REG2,CRC Pattern Counter Preload Register 2" hexmask.long.tbyte 0x00 0.--19. 1. " CRC_PAT_COUNT2[19:0] ,Channel 2 Pattern Counter Preload" group.long 0x84++0x3 line.long 0x0 "CRC_SCOUNT_REG2,CRC Sector Counter Preload Register 2" hexmask.long.word 0x00 0.--15. 1. " CRC_SEC_COUNT2[15:0] ,Channel 2 Sector Counter Preload" hgroup.long 0x88++0x3 hide.long 0x0 "CRC_CURSEC_REG2,CRC Current Sector Register 2" in group.long 0x8C++0x3 line.long 0x0 "CRC_WDTOPLD2,Watchdog Timeout Preload Register" hexmask.long.tbyte 0x00 0.--23. 1. " CRC_WDTOPLD2[23:0] ,Channel 2 Watchdog Timeout Counter Preload" group.long 0x90++0x3 line.long 0x0 "CRC_BCTOPLD2,CRC Channel 2 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x00 0.--23. 1. " CRC_BCTOPLD2[23:0] ,Channel 2 Block Complete Timeout Counter Preload" group.long 0xA0++0x3 line.long 0x0 "PSA_SIGREGL2,Channel 2 PSA Signature Low Register" group.long 0xA4++0x3 line.long 0x0 "PSA_SIGREGH2,Channel 2 PSA Signature High Register" group.long 0xA8++0x3 line.long 0x0 "CRC_REGL2,Channel 2 CRC Value Low Register" group.long 0xAC++0x3 line.long 0x0 "CRC_REGH2,Channel 2 CRC Value High Register" rgroup.long 0xB0++0x3 line.long 0x0 "PSA_SECSIGREGL2,PSA Sector Signature Low Register 2" rgroup.long 0xB4++0x3 line.long 0x0 "PSA_SECSIGREGH2,PSA Sector Signature High Register 2" rgroup.long 0xB8++0x3 line.long 0x0 "RAW_DATAREGL2,Raw Data Low Register 2" rgroup.long 0xBC++0x3 line.long 0x0 "RAW_DATAREGH2,Raw Data High Register 2" tree.end width 0xb tree.end else tree "CRC (Cyclic Redundancy Check Controller)" base ad:0xFE000000 width 20. group.long 0x00++0x03 line.long 0x00 "CRC_CTRL0,CRC Global Control Register 0" sif (cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&cpu()!="RM48L950"&&cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!="RM48L550-ZWT"&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&cpu()!=("TMS570LS3137-EP")) bitfld.long 0x00 24. " CH4_PSA_SWREST ,Channel 4 PSA software reset" "No reset,Reset" bitfld.long 0x00 16. " CH3_PSA_SWREST ,Channel 3 psa software reset" "No reset,Reset" newline endif bitfld.long 0x00 8. " CH2_PSA_SWREST ,Channel 2 PSA software reset" "No reset,Reset" bitfld.long 0x00 0. " CH1_PSA_SWREST ,Channel 1 PSA software reset" "No reset,Reset" group.long 0x08++0x03 line.long 0x00 "CRC_CTRL1,CRC Global Control Register 1" bitfld.long 0x00 0. " PWDN ,Power down" "Not powered down,Powered down" group.long 0x10++0x03 line.long 0x00 "CRC_CTRL2,CRC Global Control Register 2" sif (cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&cpu()!="RM48L950"&&cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!="RM48L550-ZWT"&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&cpu()!=("TMS570LS3137-EP")) bitfld.long 0x00 24.--25. " CH4_MODE ,Channel 4 mode" "Data capture,Auto,,Full-CPU" bitfld.long 0x00 16.--17. " CH3_MODE ,Channel 3 mode" "Data capture,Auto,,Full-CPU" newline endif sif !cpuis("TMS570LS3137-EP") bitfld.long 0x00 8.--9. " CH2_MODE ,Channel 2 mode" "Data capture,Auto,,Full-CPU" bitfld.long 0x00 4. " CH1_TRACEEN ,Channel 1 data trace Enable" "Disabled,Enabled" newline bitfld.long 0x00 0.--1. " CH1_MODE ,Channel 1 mode" "Data capture,Auto,,Full-CPU" else bitfld.long 0x00 8.--9. " CH2_MODE ,Channel 2 mode" "Data capture,Auto,Semi-CPU,Full-CPU" bitfld.long 0x00 4. " CH1_TRACEEN ,Channel 1 data trace Enable" "Disabled,Enabled" newline bitfld.long 0x00 0.--1. " CH1_MODE ,Channel 1 mode" "Data capture,Auto,Semi-CPU,Full-CPU" endif sif (cpu()==("TMS570LS3137-EP")) group.long 0x18++0x03 line.long 0x00 "CRC_INT_SET/CLR,CRC Interrupt Enable Set/Reset Register" setclrfld.long 0x00 12. 0x08 12. 0x10 12. " CH2_TIMEOUTEN ,Channel 2 timeout interrupt" "Disabled,Enabled" setclrfld.long 0x00 11. 0x08 11. 0x10 11. " CH2_UNDEREN ,Channel 2 underrun interrupt" "Disabled,Enabled" newline setclrfld.long 0x00 10. 0x08 10. 0x10 10. " CH2_OVEREN ,Channel 2 overrun interrupt" "Disabled,Enabled" setclrfld.long 0x00 9. 0x08 9. 0x10 9. " CH2_CRCFAILEN ,Channel 2 CRC fail interrupt" "Disabled,Enabled" newline setclrfld.long 0x00 8. 0x08 8. 0x10 8. " CH2_CCITEN ,Channel 2 compression complete interrupt" "Disabled,Enabled" setclrfld.long 0x00 4. 0x08 4. 0x10 4. " CH1_TIMEOUTEN ,Channel 1 timeout interrupt" "Disabled,Enabled" newline setclrfld.long 0x00 3. 0x08 3. 0x10 3. " CH1_UNDEREN ,Channel 1 underrun interrupt" "Disabled,Enabled" setclrfld.long 0x00 2. 0x08 2. 0x10 2. " CH1_OVEREN ,Channel 1 overrun interrupt" "Disabled,Enabled" newline setclrfld.long 0x00 1. 0x08 1. 0x10 1. " CH1_CRCFAILEN ,Channel 1 CRC fail interrupt" "Disabled,Enabled" setclrfld.long 0x00 0. 0x08 0. 0x10 0. " CH1_CCITEN ,Channel 1 compression complete interrupt" "Disabled,Enabled" else group.long 0x18++0x03 line.long 0x00 "CRC_INTS,CRC Interrupt Enable Set Register" sif (!cpuis("RM48L952-PGE")&&!cpuis("RM48L952-ZWT")&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&cpu()!="RM48L950"&&cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!="RM48L550-ZWT"&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")) bitfld.long 0x00 28. " CH4_TIMEOUTEN ,Channel 4 timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x00 27. " CH4_UNDEREN ,Channel 4 underrun interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 26. " CH4_OVEREN ,Channel 4 overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 25. " CH4_CRCFAILEN ,Channel 4 CRC fail interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 20. " CH3_TIMEOUTEN ,Channel 3 timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x00 19. " CH3_UNDEREN ,Channel 3 underrun interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 18. " CH3_OVEREN ,Channel 3 overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 17. " CH3_CRCFAILEN ,Channel 3 CRC fail interrupt enable" "Disabled,Enabled" newline endif bitfld.long 0x00 12. " CH2_TIMEOUTENS ,Channel 2 timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x00 11. " CH2_UNDERENS ,Channel 2 underrun interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 10. " CH2_OVERENS ,Channel 2 overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 9. " CH2_CRCFAILENS ,Channel 2 CRC fail interrupt enable" "Disabled,Enabled" newline sif (!cpuis("RM48L950*")&&cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")) bitfld.long 0x00 8. " CH2_CCITEN ,Channel 2 compression complete interrupt enable" "Disabled,Enabled" newline endif bitfld.long 0x00 4. " CH1_TIMEOUTENS ,Channel 1 timeout interrupt enable" "Disabled,Enabled" bitfld.long 0x00 3. " CH1_UNDERENS ,Channel 1 underrun interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 2. " CH1_OVERENS ,Channel 1 overrun interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " CH1_CRCFAILENS ,Channel 1 CRC fail interrupt enable" "Disabled,Enabled" sif (!cpuis("RM48L950*")&&cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!="RM48L550-ZWT") newline bitfld.long 0x00 0. " CH1_CCITEN ,Channel 1 compression complete interrupt enable" "Disabled,Enabled" endif group.long 0x20++0x03 line.long 0x00 "CRC_INTR,CRC Interrupt Enable Reset Register" sif (cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&cpu()!="RM48L950"&&cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!="RM48L550-ZWT"&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")) bitfld.long 0x00 28. " CH4_TIMEOUTEN ,Channel 4 timeout interrupt disable" "No,Yes" bitfld.long 0x00 27. " CH4_UNDEREN ,Channel 4 underrun interrupt Disable" "No,Yes" newline bitfld.long 0x00 26. " CH4_OVEREN ,Channel 4 overrun interrupt disable" "No,Yes" bitfld.long 0x00 25. " CH4_CRCFAILEN ,Channel 4 CRC fail interrupt Disable" "No,Yes" newline bitfld.long 0x00 20. " CH3_TIMEOUTEN ,Channel 3 Timeout interrupt disable" "No,Yes" bitfld.long 0x00 19. " CH3_UNDEREN ,Channel 3 underrun interrupt disable" "No,Yes" newline bitfld.long 0x00 18. " CH3_OVEREN ,Channel 3 overrun interrupt disable" "No,Yes" bitfld.long 0x00 17. " CH3_CRCFAILEN ,Channel 3 CRC fail interrupt disable" "No,Yes" newline endif bitfld.long 0x00 12. " CH2_TIMEOUTENR ,Channel 2 timeout interrupt disable" "No,Yes" bitfld.long 0x00 11. " CH2_UNDERENR ,Channel 2 underrun interrupt disable" "No,Yes" newline bitfld.long 0x00 10. " CH2_OVERENR ,Channel 2 overrun interrupt disable" "No,Yes" bitfld.long 0x00 9. " CH2_CRCFAILENR ,Channel 2 CRC fail interrupt disable" "No,Yes" newline sif (!cpuis("RM48L950*")&&cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!="RM48L550-ZWT") bitfld.long 0x00 8. " CH2_CCITEN ,Channel 2 compression complete interrupt disable" "No,Yes" newline endif bitfld.long 0x00 4. " CH1_TIMEOUTENR ,Channel 1 timeout interrupt disable" "No,Yes" bitfld.long 0x00 3. " CH1_UNDERENR ,Channel 1 underrun interrupt disable" "No,Yes" newline bitfld.long 0x00 2. " CH1_OVERENR ,Channel 1 overrun interrupt disable" "No,Yes" bitfld.long 0x00 1. " CH1_CRCFAILENR ,Channel 1 CRC fail interrupt disable" "No,Yes" sif (!cpuis("RM48L950*")&&cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!="RM48L550-ZWT") newline bitfld.long 0x00 0. " CH1_CCITEN ,Channel 1 compression complete interrupt disable" "No,Yes" endif endif group.long 0x28++0x03 line.long 0x00 "CRC_STATUS,CRC Interrupt Status Register" sif (cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&cpu()!="RM48L950"&&cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!="RM48L550-ZWT"&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS3137-EP")) eventfld.long 0x00 28. " CH4_TIMEOUT ,Channel 4 CRC timeout status flag" "No interrupt,Interrupt" eventfld.long 0x00 27. " CH4_UNDER ,Channel 4 CRC underrun status flag" "No interrupt,Interrupt" newline eventfld.long 0x00 26. " CH4_OVER ,Channel 4 CRC overrun status flag" "No interrupt,Interrupt" eventfld.long 0x00 25. " CH4_CRCFAIL ,Channel 4 CRC compare fail status flag" "No interrupt,Interrupt" newline eventfld.long 0x00 20. " CH3_TIMEOUT ,Channel 3 CRC timeout status flag" "No interrupt,Interrupt" eventfld.long 0x00 19. " CH3_UNDER ,Channel 3 CRC underrun status flag" "No interrupt,Interrupt" newline eventfld.long 0x00 18. " CH3_OVER ,Channel 3 CRC overrun status flag" "No interrupt,Interrupt" eventfld.long 0x00 17. " CH3_CRCFAIL ,Channel 3 CRC compare fail status flag" "No interrupt,Interrupt" newline endif eventfld.long 0x00 12. " CH2_TIMEOUT ,Channel 2 CRC timeout status flag" "No interrupt,Interrupt" eventfld.long 0x00 11. " CH2_UNDER ,Channel 2 CRC underrun status flag" "No interrupt,Interrupt" newline eventfld.long 0x00 10. " CH2_OVER ,Channel 2 CRC overrun status flag" "No interrupt,Interrupt" eventfld.long 0x00 9. " CH2_CRCFAIL ,Channel 2 CRC compare fail status flag" "No interrupt,Interrupt" newline sif (!cpuis("RM48L950*")&&cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")) eventfld.long 0x00 8. " CH2_CCIT ,Channel 2 CRC pattern compression complete status flag" "No interrupt,Interrupt" newline endif eventfld.long 0x00 4. " CH1_TIMEOUT ,Channel 1 CRC timeout status flag" "No interrupt,Interrupt" eventfld.long 0x00 3. " CH1_UNDER ,Channel 1 CRC underrun status flag" "No interrupt,Interrupt" newline eventfld.long 0x00 2. " CH1_OVER ,Channel 1 CRC overrun status flag" "No interrupt,Interrupt" eventfld.long 0x00 1. " CH1_CRCFAIL ,Channel 1 CRC compare fail status flag" "No interrupt,Interrupt" sif (!cpuis("RM48L950*")&&cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")) newline eventfld.long 0x00 0. " CH1_CCIT ,Channel 1 CRC pattern compression complete status flag" "No interrupt,Interrupt" endif sif !cpuis("TMS570LS3137-EP") rgroup.long 0x30++0x03 line.long 0x00 "CRC_INT_OFFSET_REG,CRC Interrupt Offset Register" hexmask.long.byte 0x00 0.--7. 1. " OFSTREG ,CRC interrupt offset" else hgroup.long 0x30++0x03 hide.long 0x00 "CRC_INT_OFFSET_REG,CRC Interrupt Offset Register" in endif rgroup.long 0x38++0x03 line.long 0x00 "CRC_BUSY,CRC Busy Register" sif (cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&cpu()!="RM48L950"&&cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!="RM48L550-ZWT"&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&!cpuis("TMS570LS3137-EP")) bitfld.long 0x00 24. " CH4_BUSY ,Channel 4 busy flag" "Not busy,Busy" bitfld.long 0x00 16. " CH3_BUSY ,Channel 3 busy flag" "Not busy,Busy" newline endif bitfld.long 0x00 8. " CH2_BUSY ,Channel 2 busy flag" "Not busy,Busy" bitfld.long 0x00 0. " CH1_BUSY ,Channel 1 busy flag" "Not busy,Busy" sif !cpuis("TMS570LS3137-EP") rgroup.long 0x140++0x03 line.long 0x00 "MCRC_TRACE_BUS_SEL,Data Bus Selection Register" bitfld.long 0x00 2. " MEN ,Enable/disables the tracing of VBUSM" "Disabled,Enabled" bitfld.long 0x00 1. " DTCMEN ,Enable/disables the tracing of data TCM" "Disabled,Enabled" newline bitfld.long 0x00 0. " ITCMEN ,Enable/disables the tracing of instruction TCM" "Disabled,Enabled" else group.long 0x140++0x03 line.long 0x00 "CRC_TRACE_BUS_SEL,Data Bus Selection Register" bitfld.long 0x00 2. " MEn ,Enable/disables the tracing of VBUSM" "Disabled,Enabled" bitfld.long 0x00 1. " DTCMEn ,Enable/disables the tracing of data TCM" "Disabled,Enabled" newline bitfld.long 0x00 0. " ITCMEn ,Enable/disables the tracing of instruction TCM" "Disabled,Enabled" endif tree "Channel 1 Registers" group.long 0x40++0x07 line.long 0x00 "CRC_PCOUNT_REG1,CRC Pattern Counter Preload Register 1" hexmask.long.tbyte 0x00 0.--19. 1. " CRC_PAT_COUNT1 ,Channel 1 pattern counter preload" line.long 0x04 "CRC_SCOUNT_REG1,CRC Sector Counter Preload Register 1" hexmask.long.word 0x04 0.--15. 1. " CRC_SEC_COUNT1 ,Channel 1 sector counter preload" hgroup.long 0x48++0x03 hide.long 0x00 "CRC_CURSEC_REG1,CRC Current Sector Register 1" in group.long 0x4C++0x07 line.long 0x00 "CRC_WDTOPLD1,Watchdog Timeout Preload Register" hexmask.long.tbyte 0x00 0.--23. 1. " CRC_WDTOPLD1 ,Channel 1 watchdog timeout counter preload" line.long 0x04 "CRC_BCTOPLD1,CRC channel 1 block complete timeout preload register" hexmask.long.tbyte 0x04 0.--23. 1. " CRC_BCTOPLD1 ,Channel 1 block complete timeout counter preload" group.long 0x60++0x0F line.long 0x00 "PSA_SIGREGL1,Channel 1 PSA Signature Low Register" line.long 0x04 "PSA_SIGREGH1,Channel 1 PSA Signature High Register" line.long 0x08 "CRC_REGL1,Channel 1 CRC Value Low Register" line.long 0x0C "CRC_REGH1,Channel 1 CRC Value High Register" rgroup.long 0x70++0x0F line.long 0x00 "PSA_SECSIGREGL1,Channel 1 PSA Sector Signature Low Register 1" line.long 0x04 "PSA_SECSIGREGH1,Channel 1 PSA Sector Signature High Register 1" line.long 0x08 "RAW_DATAREGL1,Channel 1 Raw Data Low Register 1" line.long 0x0C "RAW_DATAREGH1,Channel 1 Raw Data High Register 1" tree.end tree "Channel 2 Registers" group.long 0x80++0x07 line.long 0x00 "CRC_PCOUNT_REG2,CRC Pattern Counter Preload Register 2" hexmask.long.tbyte 0x00 0.--19. 1. " CRC_PAT_COUNT2 ,Channel 2 pattern counter preload" line.long 0x04 "CRC_SCOUNT_REG2,CRC Sector Counter Preload Register 2" hexmask.long.word 0x04 0.--15. 1. " CRC_SEC_COUNT2 ,Channel 2 sector counter preload" hgroup.long 0x88++0x03 hide.long 0x00 "CRC_CURSEC_REG2,CRC Current Sector Register 2" in group.long 0x8C++0x07 line.long 0x00 "CRC_WDTOPLD2,Watchdog Timeout Preload Register" hexmask.long.tbyte 0x00 0.--23. 1. " CRC_WDTOPLD2 ,Channel 2 watchdog timeout counter preload" line.long 0x04 "CRC_BCTOPLD2,CRC Channel 2 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x04 0.--23. 1. " CRC_BCTOPLD2 ,Channel 2 block complete timeout counter preload" group.long 0xA0++0x0F line.long 0x00 "PSA_SIGREGL2,Channel 2 PSA Signature Low Register" line.long 0x04 "PSA_SIGREGH2,Channel 2 PSA Signature High Register" line.long 0x08 "CRC_REGL2,Channel 2 CRC Value Low Register" line.long 0x0C "CRC_REGH2,Channel 2 CRC Value High Register" rgroup.long 0xB0++0x0F line.long 0x00 "PSA_SECSIGREGL2,Channel 2 PSA Sector Signature Low Register 2" line.long 0x04 "PSA_SECSIGREGH2,Channel 2 PSA Sector Signature High Register 2" line.long 0x08 "RAW_DATAREGL2,Channel 2 Raw Data Low Register 2" line.long 0x0C "RAW_DATAREGH2,Channel 2 Raw Data High Register 2" tree.end sif (cpu()!="TMS570PSFC61"&&cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&cpu()!="RM48L550-ZWT"&&!cpuis("TMS570LS1114*")&&!cpuis("TMS570LS1115*")&&!cpuis("TMS570LS1224*")&&!cpuis("TMS570LS1225*")&&!cpuis("TMS570LS1227*")&&cpu()!=("TMS570LS3137-EP")) tree "Channel 3 Registers" group.long 0xC0++0x07 line.long 0x00 "CRC_PCOUNT_REG3,CRC Pattern Counter Preload Register 3" hexmask.long.tbyte 0x00 0.--19. 1. " CRC_PAT_COUNT3[19:0] ,Channel 3 pattern counter preload" line.long 0x04 "CRC_SCOUNT_REG3,CRC Sector Counter Preload Register 3" hexmask.long.word 0x04 0.--15. 1. " CRC_SEC_COUNT3[15:0] ,Channel 3 sector counter preload" hgroup.long 0xC8++0x03 hide.long 0x00 "CRC_CURSEC_REG3,CRC Current Sector Register 3" in group.long 0xCC++0x07 line.long 0x00 "CRC_WDTOPLD3,Watchdog Timeout Preload Register" hexmask.long.tbyte 0x00 0.--23. 1. " CRC_WDTOPLD3[23:0] ,Channel 3 watchdog timeout counter preload" line.long 0x04 "CRC_BCTOPLD3,CRC Channel 3 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x04 0.--23. 1. " CRC_BCTOPLD3[23:0] ,Channel 3 block complete timeout counter preload" group.long 0xE0++0x0F line.long 0x00 "PSA_SIGREGL3,Channel 3 PSA Signature Low Register" line.long 0x04 "PSA_SIGREGH3,Channel 3 PSA Signature High Register" line.long 0x08 "CRC_REGL3,Channel 3 CRC Value Low Register" line.long 0x0C "CRC_REGH3,Channel 3 CRC Value High Register" rgroup.long 0xF0++0x0F line.long 0x00 "PSA_SECSIGREGL3,Channel 3 PSA Sector Signature Low Register 3" line.long 0x04 "PSA_SECSIGREGH3,Channel 3 PSA Sector Signature High Register 3" line.long 0x08 "RAW_DATAREGL3,Channel 3 Raw Data Low Register 3" line.long 0x0C "RAW_DATAREGH3,Channel 3 Raw Data High Register 3" tree.end tree "Channel 4 Registers" group.long 0x100++0x07 line.long 0x00 "CRC_PCOUNT_REG4,CRC Pattern Counter Preload Register 4" hexmask.long.tbyte 0x00 0.--19. 1. " CRC_PAT_COUNT4 ,Channel 4 pattern counter preload" line.long 0x04 "CRC_SCOUNT_REG4,CRC Sector Counter Preload Register 4" hexmask.long.word 0x04 0.--15. 1. " CRC_SEC_COUNT4 ,Channel 4 sector counter preload" hgroup.long 0x108++0x03 hide.long 0x00 "CRC_CURSEC_REG4,CRC Current Sector Register 4" in group.long 0x10C++0x07 line.long 0x00 "CRC_WDTOPLD4,Watchdog Timeout Preload Register" hexmask.long.tbyte 0x00 0.--23. 1. " CRC_WDTOPLD4[23:0] ,Channel 4 watchdog timeout counter preload" line.long 0x04 "CRC_BCTOPLD4,CRC Channel 4 Block Complete Timeout Preload Register" hexmask.long.tbyte 0x04 0.--23. 1. " CRC_BCTOPLD4[23:0] ,Channel 4 block complete timeout counter preload" group.long 0x120++0x0F line.long 0x00 "PSA_SIGREGL4,Channel 4 PSA Signature Low Register" line.long 0x04 "PSA_SIGREGH4,Channel 4 PSA Signature High Register" line.long 0x08 "CRC_REGL4,Channel 4 CRC Value Low Register" line.long 0x0C "CRC_REGH4,Channel 4 CRC Value High Register" rgroup.long 0x130++0x0F line.long 0x00 "PSA_SECSIGREGL4,Channel 4 PSA Sector Signature Low Register 4" line.long 0x04 "PSA_SECSIGREGH4,Channel 4 PSA Sector Signature High Register 4" line.long 0x08 "RAW_DATAREGL4,Channel 4 Raw Data Low Register 4" line.long 0x0C "RAW_DATAREGH4,Channel 4 Raw Data High Register 4" tree.end endif width 0x0B tree.end endif tree "VIM (Vectored Interrupt Manager)" tree "VIMPAR" base ad:0xFFFFFD00 width 10. group.long 0xEC++0x3 line.long 0x0 "PARFLAG,parity Flag register" eventfld.long 0x00 0. " PARFLG ,Parity Error Flag" "No error,Error" group.long 0xF0++0x3 line.long 0x0 "PARCTL,parity control register" bitfld.long 0x00 8. " TEST ,Maps the Parity Bits Into the VIM RAM Frame to Make Them Accessible" "Not mapped,Mapped" bitfld.long 0x00 0.--3. " PARENA ,VIM Parity Enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" if (((data.long(ad:0xFFFFFD00+0xEC000000))&0x01000000)==0x01000000) rgroup.long 0xF4++0x3 line.long 0x0 "ADDERR,Address Parity Error Register" hexmask.long.tbyte 0x00 9.--31. 1. " VRO ,VIM RAM Offset" hexmask.long.byte 0x00 2.--8. 0x4 " ADDERR[6:0] ,Address Parity Error" hexmask.long.byte 0x00 0.--1. 1. " WO ,Word Offset" else rgroup.long 0xF4++0x3 line.long 0x0 "ADDERR,Address Parity Error Register" hexmask.long.tbyte 0x00 9.--31. 1. " VRO ,VIM RAM Offset" hexmask.long.byte 0x00 0.--1. 1. " WO ,Word Offset" endif group.long 0xF8++0x3 line.long 0x0 "FBPARERR,Fall back Address Parity Error Register" width 0xb tree.end sif (cpu()=="RM42L432") tree "VIM" base ad:0xFFFFFE00 width 9. tree "VIM Offset Vector Registers" rgroup.long 0x00++0x3 line.long 0x0 "IRQINDEX,IRQ Index Offset Vector Register" hexmask.long.byte 0x00 0.--7. 1. " IRQINDEX ,IRQ index vector" rgroup.long 0x04++0x3 line.long 0x0 "FIQINDEX,FIQ Index Offset Vector Register" hexmask.long.byte 0x00 0.--7. 1. " FIQINDEX ,FIQ index offset vector" tree.end width 9. group.long 0x10++0x3 line.long 0x0 "FIRQPR0,Program Control 0 Register" bitfld.long 0x00 31. " FIRQPR_MIBADC1 ,FIQ/IRQ Program Control 31 - MIBADC magnitude compare interrupt" "IRQ,FIQ" bitfld.long 0x00 30. " FIRQPR_SPI2 ,FIQ/IRQ Program Control 30 - SPI2 level 1 interrupt" "IRQ,FIQ" bitfld.long 0x00 29. " FIRQPR_DCAN1 ,FIQ/IRQ Program Control 29 - DCAN1 level 1 interrupt" "IRQ,FIQ" bitfld.long 0x00 28. " FIRQPR_MIBADC ,FIQ/IRQ Program Control 28 - MIBADC sw group 2 interrupt" "IRQ,FIQ" textline " " bitfld.long 0x00 27. " FIRQPR_LIN ,FIQ/IRQ Program Control 27 - LIN level 1 interrupt" "IRQ,FIQ" bitfld.long 0x00 26. " FIRQPR_MIBSPI ,FIQ/IRQ Program Control 26 - MIBSPI1 level 1 interrupt" "IRQ,FIQ" bitfld.long 0x00 25. " FIRQPR_HET_TU ,FIQ/IRQ Program Control 25 - HET TU level 1 interrupt" "IRQ,FIQ" bitfld.long 0x00 24. " FIRQPR_N2HET ,FIQ/IRQ Program Control 24 - N2HET level 1 interrupt" "IRQ,FIQ" textline " " bitfld.long 0x00 23. " FIRQPR_GIO ,FIQ/IRQ Program Control 23 - GIO interrupt B" "IRQ,FIQ" bitfld.long 0x00 22. " FIRQPR_CPU ,FIQ/IRQ Program Control 22 - PMU interrupt" "IRQ,FIQ" bitfld.long 0x00 21. " FIRQPR_SYSTEM ,FIQ/IRQ Program Control 21 - Software interrupt (SSI)" "IRQ,FIQ" bitfld.long 0x00 20. " FIRQPR_ESM ,FIQ/IRQ Program Control 20 - ESM Low level interrupt" "IRQ,FIQ" textline " " bitfld.long 0x00 17. " FIRQPR_SPI2 ,FIQ/IRQ Program Control 17 - SPI2 level 0 interrupt" "IRQ,FIQ" bitfld.long 0x00 16. " FIRQPR_DCAN1 ,FIQ/IRQ Program Control 16 - DCAN1 level 0 interrupt" "IRQ,FIQ" bitfld.long 0x00 15. " FIRQPR_MIBADC1 ,FIQ/IRQ Program Control 15 - MIBADC sw group 1 interrupt" "IRQ,FIQ" bitfld.long 0x00 14. " FIRQPR_MIBADC1 ,FIQ/IRQ Program Control 14 - MIBADC event group interrupt" "IRQ,FIQ" textline " " bitfld.long 0x00 13. " FIRQPR_LIN ,FIQ/IRQ Program Control 13 - LIN level 0 interrupt" "IRQ,FIQ" bitfld.long 0x00 12. " FIRQPR_MIBSPI1 ,FIQ/IRQ Program Control 12 - MIBSPI1 level 0 interrupt" "IRQ,FIQ" bitfld.long 0x00 11. " FIRQPR_HET_TU ,FIQ/IRQ Program Control 11 - HET TU level 0 interrupt" "IRQ,FIQ" bitfld.long 0x00 10. " FIRQPR_N2HET ,FIQ/IRQ Program Control 10 - N2HET level 0 interrupt" "IRQ,FIQ" textline " " bitfld.long 0x00 9. " FIRQPR_GIO ,FIQ/IRQ Program Control 9 - GIO interrupt A" "IRQ,FIQ" bitfld.long 0x00 7. " FIRQPR_RTI ,FIQ/IRQ Program Control 7 - RTI overflow interrupt 1" "IRQ,FIQ" bitfld.long 0x00 6. " FIRQPR_RTI ,FIQ/IRQ Program Control 6 - RTI overflow interrupt 0" "IRQ,FIQ" textline " " bitfld.long 0x00 5. " FIRQPR_RTI ,FIQ/IRQ Program Control 5 - RTI overflow interrupt 3" "IRQ,FIQ" bitfld.long 0x00 4. " FIRQPR_RTI ,FIQ/IRQ Program Control 4 - RTI compare interrupt 3" "IRQ,FIQ" bitfld.long 0x00 3. " FIRQPR_RTI ,FIQ/IRQ Program Control 3 - RTI compare interrupt 2" "IRQ,FIQ" bitfld.long 0x00 2. " FIRQPR_RTI ,FIQ/IRQ Program Control 2 - RTI compare interrupt 1" "IRQ,FIQ" textline " " bitfld.long 0x00 0. " FIRQPR_ESM ,FIQ/IRQ Program Control 0 - RTI compare interrupt 0" "IRQ,FIQ" group.long 0x14++0x3 line.long 0x0 "FIRQPR1,Program Control 1 Register" bitfld.long 0x00 29. " FIRQPR_FMC ,FIQ/IRQ Program Control 61 - FSM_DONE interrupt" "IRQ,FIQ" bitfld.long 0x00 10. " FIRQPR_DCAN2 ,FIQ/IRQ Program Control 42 - DCAN2 level 1 interrupt" "IRQ,FIQ" bitfld.long 0x00 6. " FIRQPR_SPI3 ,FIQ/IRQ Program Control 38 - SPI3 level 1 interrupt" "IRQ,FIQ" bitfld.long 0x00 5. " FIRQPR_SPI3 ,FIQ/IRQ Program Control 37 - SPI3 level 0 interrupt" "IRQ,FIQ" textline " " bitfld.long 0x00 3. " FIRQPR_DCAN2 ,FIQ/IRQ Program Control 35 - DCAN2 level 0 interrupt" "IRQ,FIQ" group.long 0x18++0x3 line.long 0x0 "FIRQPR2,Program Control 2 Register" bitfld.long 0x00 24. " FIRQPR_HWAG1 ,FIQ/IRQ Program Control 88 - HWA_INT_REQ_L" "IRQ,FIQ" bitfld.long 0x00 21. " FIRQPR_PBIST ,FIQ/IRQ Program Control 85 - PBIST Done Interrupt" "IRQ,FIQ" bitfld.long 0x00 20. " FIRQPR_eQEPINTn ,FIQ/IRQ Program Control 84 - eQEP Interrupt" "IRQ,FIQ" bitfld.long 0x00 18. " FIRQPR_DCC ,FIQ/IRQ Program Control 82 - DCC done interrupt" "IRQ,FIQ" textline " " bitfld.long 0x00 16. " FIRQPR_HWAG ,FIQ/IRQ Program Control 80 - HWA_INT_REQ_H" "IRQ,FIQ" width 9. tree "VIM Pending Interrupt Read Location Registers" rgroup.long 0x20++0x3 line.long 0x0 "INTREQ0,Pending Interrupt Read Location 0" bitfld.long 0x00 31. " INTREQ_MIBADC1 ,MIBADC1 magnitude compare interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 30. " INTREQ_SPI2 ,SPI2 level 1 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 29. " INTREQ_DCAN1 ,DCAN1 level 1 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 28. " INTREQ_MIBADC ,MIBADC sw group 2 interrupt Pending" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " INTREQ_LIN ,LIN level 1 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 26. " INTREQ_MIBSPI ,MIBSPI level 1 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 25. " INTREQ_HET_TU ,HET TU level 1 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 24. " INTREQ_N2HET ,N2HET level 1 interrupt Pending" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " INTREQ_GIO ,GIO interrupt B Pending" "No interrupt,Interrupt" bitfld.long 0x00 22. " INTREQ_CPU ,PMU Interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 21. " INTREQ_SYSTEM ,Software interrupt (SSI) Pending" "No interrupt,Interrupt" bitfld.long 0x00 20. " INTREQ_ESM ,ESM Low level interrupt Pending" "No interrupt,Interrupt" textline " " bitfld.long 0x00 17. " INTREQ_SPI2 ,SPI2 level 0 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 16. " INTREQ_DCAN1 ,DCAN1 level 0 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 15. " INTREQ_MIBADC1 ,MIBADC1 sw group 1 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 14. " INTREQ_MIBADC1 ,MIBADC1 event group interrupt Pending" "No interrupt,Interrupt" textline " " bitfld.long 0x00 13. " INTREQ_LIN ,LIN level 0 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 12. " INTREQ_MIBSPI1 ,MIBSPI1 level 0 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 11. " INTREQ_HET_TU1 ,HET TU1 level 0 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 10. " INTREQ_N2HET1 ,N2HET1 level 0 interrupt Pending" "No interrupt,Interrupt" textline " " bitfld.long 0x00 9. " INTREQ_GIO ,GIO interrupt A Pending" "No interrupt,Interrupt" bitfld.long 0x00 7. " INTREQ_RTI ,RTI overflow interrupt 1 Pending" "No interrupt,Interrupt" bitfld.long 0x00 6. " INTREQ_RTI ,RTI overflow interrupt 0 Pending" "No interrupt,Interrupt" bitfld.long 0x00 5. " INTREQ_RTI ,RTI compare interrupt 3 Pending" "No interrupt,Interrupt" textline " " bitfld.long 0x00 4. " INTREQ_RTI ,RTI compare interrupt 2 Pending" "No interrupt,Interrupt" bitfld.long 0x00 3. " INTREQ_RTI ,RTI compare interrupt 1 Pending" "No interrupt,Interrupt" bitfld.long 0x00 2. " INTREQ_RTI ,RTI compare interrupt 0 Pending" "No interrupt,Interrupt" bitfld.long 0x00 0. " INTREQ_ESM ,ESM High level interrupt (NMI) Pending" "No interrupt,Interrupt" rgroup.long 0x24++0x3 line.long 0x0 "INTREQ1,Pending Interrupt Read Location 1" bitfld.long 0x00 29. " INTREQ_FMC ,FSM_DONE interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 10. " INTREQ_DCAN2 ,DCAN2 level 1 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 6. " INTREQ_SPI3 ,SPI3 level 1 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 5. " INTREQ_SPI3 ,SPI3 level 0 interrupt Pending" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " INTREQ_DCAN2 ,DCAN2 level 0 interrupt Pending" "No interrupt,Interrupt" rgroup.long 0x28++0x3 line.long 0x0 "INTREQ2,Pending Interrupt Read Location 2" bitfld.long 0x00 24. " INTREQ_HWAG ,HWA_INT_REQ_L Pending" "No interrupt,Interrupt" bitfld.long 0x00 21. " INTREQ_PBIST ,PBIST Done Interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 20. " INTREQ_eQEPINTn ,eQEP Interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 18. " INTREQ_DCC1 ,DCC done interrupt Pending" "No interrupt,Interrupt" textline " " bitfld.long 0x00 16. " INTREQ_HWAG ,HWA_INT_REQ_H Pending" "No interrupt,Interrupt" tree.end width 13. tree "VIM Interrupt Mask Registers" group.long 0x30++0x3 line.long 0x0 "REQENASET0,Interrupt Enable Set/Clr Register 0" setclrfld.long 0x00 31. 0x00 31. 0x10 31. " REQENA_31_set/clr ,MIBADC magnitude compare Request enable set bit 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x10 30. " REQENA_30_set/clr ,SPI2 level 1 Request enable set bit 30" "Disabled,Enabled" textline " " setclrfld.long 0x00 29. 0x00 29. 0x10 29. " REQENA_29_set/clr ,DCAN1 level 1 Request enable set bit 29" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x10 28. " REQENA_28_set/clr ,MIBADC sw group 2 Request enable set bit 28" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. 0x00 27. 0x10 27. " REQENA_27_set/clr ,LIN level 1 Request enable set bit 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x10 26. " REQENA_26_set/clr ,MIBSPI level 1 Request enable set bit 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x10 25. " REQENA_25_set/clr ,HET TU level 1 Request enable set bit 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x10 24. " REQENA_24_set/clr ,N2HET1 level 1 Request enable set bit 24" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. 0x00 23. 0x10 23. " REQENA_23_set/clr ,GIO interrupt B Request enable set bit 23" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x10 22. " REQENA_22_set/clr ,PMU Request enable set bit 22" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. 0x00 21. 0x10 21. " REQENA_21_set/clr ,Software interrupt (SSI) Request enable set bit 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x10 20. " REQENA_20_set/clr ,ESM Low level Request enable set bit 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. 0x00 17. 0x10 17. " REQENA_17_set/clr ,SPI2 level 0 Request enable set bit 17" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x10 16. " REQENA_16_set/clr ,DCAN1 level 0 Request enable set bit 16" "Disabled,Enabled" textline " " setclrfld.long 0x00 15. 0x00 15. 0x10 15. " REQENA_15_set/clr ,MIBADC1 sw group 1 Request enable set bit 15" "Disabled,Enabled" textline " " setclrfld.long 0x00 14. 0x00 14. 0x10 14. " REQENA_14_set/clr ,MIBADC1 event group Request enable set bit 14" "Disabled,Enabled" setclrfld.long 0x00 13. 0x00 13. 0x10 13. " REQENA_13_set/clr ,LIN level 0 Request enable set bit 13" "Disabled,Enabled" textline " " setclrfld.long 0x00 12. 0x00 12. 0x10 12. " REQENA_12_set/clr ,MIBSPI1 level 0 Request enable set bit 12" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x10 11. " REQENA_11_set/clr ,HET TU level 0 Request enable set bit 11" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x10 10. " REQENA_10_set/clr ,N2HET level 0 Request enable set bit 10" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x10 9. " REQENA_9_set/clr ,GIO interrupt A Request enable set bit 9" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x10 7. " REQENA_7_set/clr ,RTI overflow 1 Request enable set bit 7" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x10 5. " REQENA_5_set/clr ,RTI compare 3 Request enable set bit 5" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. 0x00 3. 0x10 3. " REQENA_3_set/clr ,RTI compare 1 Request enable set bit 3" "Disabled,Enabled" group.long 0x34++0x3 line.long 0x0 "REQENASET1,Interrupt Enable Set/Clr Register 1" setclrfld.long 0x00 29. 0x00 29. 0x10 29. " REQENA_61_set/clr ,FSM_DONE Request enable set bit 61" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x10 10. " REQENA_42_set/clr ,DCAN2 level 1 Request enable set bit 42" "Disabled,Enabled" textline " " setclrfld.long 0x00 6. 0x00 6. 0x10 6. " REQENA_38_set/clr ,SPI3 level 1 Request enable set bit 38" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x10 5. " REQENA_37_set/clr ,SPI3 level 0 Request enable set bit 37" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. 0x00 3. 0x10 3. " REQENA_35_set/clr ,DCAN2 level 0 Request enable set bit 35" "Disabled,Enabled" group.long 0x38++0x3 line.long 0x0 "REQENASET2,Interrupt Enable Set/Clr Register 2" setclrfld.long 0x00 24. 0x00 24. 0x10 24. " REQENA_88_set/clr ,HWA_INT_REQ_L Request enable set bit 88" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x10 21. " REQENA_85_set/clr ,PBIST Done Request enable set bit 85" "Disabled,Enabled" textline " " setclrfld.long 0x00 20. 0x00 20. 0x10 20. " REQENA_84_set/clr ,eQEP Request enable set bit 84" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x10 18. " REQENA_82_set/clr ,DCC done Request enable set bit 82" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x10 16. " REQENA_80_set/clr ,HWA_INT_REQ_H Request enable set bit 80" "Disabled,Enabled" tree.end width 14. tree "VIM Wake Up Mask Registers" group.long 0x50++0x3 line.long 0x0 "WAKEENASET0,Wake-up Enable Set Register 0" setclrfld.long 0x00 31. 0x00 31. 0x10 31. " WAKEENA_31_set/clr ,MIBADC1 magnitude compare interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x10 30. " WAKEENA_30_set/clr ,SPI2 level 1 interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 29. 0x00 29. 0x10 29. " WAKEENA_29_set/clr ,DCAN1 level 1 interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x10 28. " WAKEENA_28_set/clr ,MIBADC sw group 2 interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. 0x00 27. 0x10 27. " WAKEENA_27_set/clr ,LIN level 1 interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x10 26. " WAKEENA_26_set/clr ,MIBSPI level 1 interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x10 25. " WAKEENA_25_set/clr ,HET TU level 1 interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x10 24. " WAKEENA_24_set/clr ,N2HET1 level 1 interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. 0x00 23. 0x10 23. " WAKEENA_23_set/clr ,GIO interrupt B Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x10 22. " WAKEENA_22_set/clr ,PMU Interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. 0x00 21. 0x10 21. " WAKEENA_21_set/clr ,Software interrupt (SSI) Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x10 20. " WAKEENA_20_set/clr ,ESM Low level interrupt Wake-up" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. 0x00 17. 0x10 17. " WAKEENA_17_set/clr ,SPI2 level 0 interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x10 16. " WAKEENA_16_set/clr ,DCAN1 level 0 interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 15. 0x00 15. 0x10 15. " WAKEENA_15_set/clr ,MIBADC1 sw group 1 interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x10 14. " WAKEENA_14_set/clr ,MIBADC1 event group interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x10 13. " WAKEENA_13_set/clr ,LIN level 0 interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x10 12. " WAKEENA_12_set/clr ,MIBSPI1 level 0 interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 11. 0x00 11. 0x10 11. " WAKEENA_11_set/clr ,HET TU level 0 interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x10 10. " WAKEENA_10_set/clr ,N2HET level 0 interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. 0x00 9. 0x10 9. " WAKEENA_9_set/clr ,GIO interrupt A Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 7. 0x00 7. 0x10 7. " WAKEENA_7_set/clr ,RTI overflow interrupt 1 Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 6. 0x00 6. 0x10 6. " WAKEENA_6_set/clr ,RTI overflow interrupt 0 Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x10 5. " WAKEENA_5_set/clr ,RTI compare interrupt 3 Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x10 4. " WAKEENA_4_set/clr ,RTI compare interrupt 2 Wake-up" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x10 3. " WAKEENA_3_set/clr ,RTI compare interrupt 1 Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 2. 0x00 2. 0x10 2. " WAKEENA_2_set/clr ,RTI compare interrupt 0 Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x10 0. " WAKEENA_0_set/clr ,ESM High level interrupt (NMI) Wake-up enable" "Disabled,Enabled" group.long 0x54++0x3 line.long 0x0 "WAKEENASET1,Wake-up Enable Set Register 1" setclrfld.long 0x00 29. 0x00 29. 0x10 29. " WAKEENA_61_set/clr ,FSM_DONE interrupt Wake-up enable set" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x10 10. " WAKEENA_42_set/clr ,DCAN2 level 1 interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 6. 0x00 6. 0x10 6. " WAKEENA_38_set/clr ,SPI3 level 1 interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x10 5. " WAKEENA_37_set/clr ,SPI3 level 0 interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. 0x00 3. 0x10 3. " WAKEENA_35_set/clr ,DCAN2 level 0 interrupt Wake-up enable" "Disabled,Enabled" group.long 0x58++0x3 line.long 0x0 "WAKEENASET2,Wake-up Enable Set Register 2" setclrfld.long 0x00 24. 0x00 24. 0x10 24. " WAKEENA_88_set/clr ,HWA_INT_REQ_L Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x10 21. " WAKEENA_85_set/clr ,PBIST Done enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 20. 0x00 20. 0x10 20. " WAKEENA_84_set/clr ,eQEP enable" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x10 18. " WAKEENA_82_set/clr ,DCC done interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x10 16. " WAKEENA_80_set/clr ,HWA_INT_REQ_H Wake-up enable" "Disabled,Enabled" tree.end width 11. tree "VIM Interrupt Vector Registers" rgroup.long 0x70++0x3 line.long 0x0 "IRQVECREG,IRQ Interrupt Vector Register" rgroup.long 0x74++0x3 line.long 0x0 "FIQVECREG,FIQ Interrupt Vector Register" tree.end width 11. group.long 0x78++0x3 line.long 0x0 "CAPEVTSRC,Capture Event register" hexmask.long.byte 0x00 16.--22. 1. " CAPEVTSRC1[6:0] ,Capture Event Source 1 Mapping Control" hexmask.long.byte 0x00 0.--6. 1. " CAPEVTSRC0[6:0] ,Capture Event Source 0 Mapping Control" width 12. tree "VIM Interrupt Control Registers" group.long 0x80++0x3 line.long 0x0 "CHANCTRL0,VIM Interrupt Control Register 0" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP0[6:0] ,ESM High level interrupt (NMI) CHAN0 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP2[6:0] ,RTI compare interrupt 0 CHAN2 Mapping Control" hexmask.long.byte 0x00 0.--6. 1. " CHANMAP3[6:0] ,RTI compare interrupt 1 CHAN3 Mapping Control" group.long 0x84++0x3 line.long 0x0 "CHANCTRL1,VIM Interrupt Control Register 1" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP4[6:0] ,RTI compare interrupt 2 CHAN4 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP5[6:0] ,RTI compare interrupt 3 CHAN5 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP6[6:0] ,RTI overflow interrupt 0 CHAN6 Mapping Control" textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP7[6:0] ,RTI overflow interrupt 1 CHAN7 Mapping Control" group.long 0x88++0x3 line.long 0x0 "CHANCTRL2,VIM Interrupt Control Register 2" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP9[6:0] ,GIO interrupt A CHAN9 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP10[6:0] ,N2HET level 0 interrupt CHAN10 Mapping Control" hexmask.long.byte 0x00 0.--6. 1. " CHANMAP11[6:0] ,HET TU level 0 interrupt CHAN11 Mapping Control" group.long 0x8C++0x3 line.long 0x0 "CHANCTRL3,VIM Interrupt Control Register 3" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP12[6:0] ,MIBSPI1 level 0 interrupt CHAN12 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP13[6:0] ,LIN level 0 interrupt CHAN13 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP14[6:0] ,MIBADC event group interrupt CHAN14 Mapping Control" textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP15[6:0] ,MIBADC sw group 1 interrupt CHAN15 Mapping Control" group.long 0x90++0x3 line.long 0x0 "CHANCTRL4,VIM Interrupt Control Register 4" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP16[6:0] ,DCAN1 level 0 interrupt CHAN16 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP17[6:0] ,SPI2 level 0 interrupt CHAN17 Mapping Control" group.long 0x94++0x3 line.long 0x0 "CHANCTRL5,VIM Interrupt Control Register 5" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP20[6:0] ,ESM Low level interrupt CHAN20 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP21[6:0] ,Software interrupt (SSI) CHAN21 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP22[6:0] ,PMU Interrupt CHAN22 Mapping Control" textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP23[6:0] ,GIO interrupt B CHAN23 Mapping Control" group.long 0x98++0x3 line.long 0x0 "CHANCTRL6,VIM Interrupt Control Register 6" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP24[6:0] ,N2HET1 level 1 interrupt CHAN24 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP25[6:0] ,HET TU level 1 interrupt CHAN25 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP26[6:0] ,MIBSPI level 1 interrupt CHAN26 Mapping Control" textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP27[6:0] ,LIN level 1 interrupt CHAN27 Mapping Control" group.long 0x9C++0x3 line.long 0x0 "CHANCTRL7,VIM Interrupt Control Register 7" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP28[6:0] ,MIBADC sw group 2 interrupt CHAN28 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP29[6:0] ,DCAN1 level 1 interrupt CHAN29 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP30[6:0] ,SPI2 level 1 interrupt CHAN30 Mapping Control" textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP31[6:0] ,MIBADC1 magnitude compare interrupt CHAN31 Mapping Control" group.long 0xA0++0x3 line.long 0x0 "CHANCTRL8,VIM Interrupt Control Register 8" hexmask.long.byte 0x00 0.--6. 1. " CHANMAP35[6:0] ,DCAN2 level 0 interrupt CHAN35 Mapping Control" group.long 0xA4++0x3 line.long 0x0 "CHANCTRL9,VIM Interrupt Control Register 9" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP37[6:0] ,SPI3 level 0 interrupt CHAN37 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP38[6:0] ,SPI3 level 1 interrupt CHAN38 Mapping Control" group.long 0xA8++0x3 line.long 0x0 "CHANCTRL10,VIM Interrupt Control Register 10" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP42[6:0] ,DCAN2 level 1 interrupt CHAN42 Mapping Control" group.long 0xBC++0x3 line.long 0x0 "CHANCTRL15,VIM Interrupt Control Register 15" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP61[6:0] ,FSM_DONE interrupt CHAN61 Mapping Control" group.long 0xD0++0x3 line.long 0x0 "CHANCTRL20,VIM Interrupt Control Register 20" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP80[6:0] ,HWA_INT_REQ_H Interrupt CHAN80 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP82[6:0] ,DCC done interrupt CHAN82 Mapping Control" group.long 0xD4++0x3 line.long 0x0 "CHANCTRL21,Channel Mapping Register" hexmask.long.byte 0x00 14.--30. 1. " CHANMAP84[6:0] ,eQEP Interrupt CHAN83 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP85[6:0] ,PBIST Done Interrupt CHAN83 Mapping Control" group.long 0xD8++0x3 line.long 0x0 "CHANCTRL22,VIM Interrupt Control Register 22" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP88[6:0] ,HWA_INT_REQ_L Interrupt CHAN88 Mapping Control" group.long 0xDC++0x3 line.long 0x0 "CHANCTRL23,Channel Mapping Register" tree.end width 0xb tree.end elif (cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE") tree "VIM" base ad:0xFFFFFE00 width 9. tree "VIM Offset Vector Registers" rgroup.long 0x00++0x3 line.long 0x0 "IRQINDEX,IRQ Index Offset Vector Register" hexmask.long.byte 0x00 0.--7. 1. " IRQINDEX ,IRQ index vector" rgroup.long 0x04++0x3 line.long 0x0 "FIQINDEX,FIQ Index Offset Vector Register" hexmask.long.byte 0x00 0.--7. 1. " FIQINDEX ,FIQ index offset vector" tree.end width 9. group.long 0x10++0x3 line.long 0x0 "FIRQPR0,Program Control 0 Register" bitfld.long 0x00 31. " FIRQPR_MIBADC1 ,FIQ/IRQ Program Control 31 - MIBADC1 magnitude compare interrupt" "IRQ,FIQ" bitfld.long 0x00 30. " FIRQPR_SPI2 ,FIQ/IRQ Program Control 30 - SPI2 level 1 interrupt" "IRQ,FIQ" bitfld.long 0x00 29. " FIRQPR_DCAN1 ,FIQ/IRQ Program Control 29 - DCAN1 level 1 interrupt" "IRQ,FIQ" bitfld.long 0x00 28. " FIRQPR_MIBADC ,FIQ/IRQ Program Control 28 - MIBADC sw group 2 interrupt" "IRQ,FIQ" textline " " bitfld.long 0x00 27. " FIRQPR_LIN ,FIQ/IRQ Program Control 27 - LIN level 1 interrupt" "IRQ,FIQ" bitfld.long 0x00 26. " FIRQPR_MIBSPI ,FIQ/IRQ Program Control 26 - MIBSPI level 1 interrupt" "IRQ,FIQ" bitfld.long 0x00 25. " FIRQPR_HET_TU ,FIQ/IRQ Program Control 25 - HET TU level 1 interrupt" "IRQ,FIQ" bitfld.long 0x00 24. " FIRQPR_N2HET1 ,FIQ/IRQ Program Control 24 - N2HET1 level 1 interrupt" "IRQ,FIQ" textline " " bitfld.long 0x00 23. " FIRQPR_GIO ,FIQ/IRQ Program Control 23 - GIO interrupt B" "IRQ,FIQ" bitfld.long 0x00 22. " FIRQPR_CPU ,FIQ/IRQ Program Control 22 - PMU Interrupt" "IRQ,FIQ" bitfld.long 0x00 21. " FIRQPR_SYSTEM ,FIQ/IRQ Program Control 21 - Software interrupt (SSI)" "IRQ,FIQ" bitfld.long 0x00 20. " FIRQPR_ESM ,FIQ/IRQ Program Control 20 - ESM Low level interrupt" "IRQ,FIQ" textline " " bitfld.long 0x00 19. " FIRQPR_CRC ,FIQ/IRQ Program Control 19 - CRC Interrupt" "IRQ,FIQ" bitfld.long 0x00 17. " FIRQPR_SPI2 ,FIQ/IRQ Program Control 17 - SPI2 level 0 interrupt" "IRQ,FIQ" bitfld.long 0x00 16. " FIRQPR_DCAN1 ,FIQ/IRQ Program Control 16 - DCAN1 level 0 interrupt" "IRQ,FIQ" bitfld.long 0x00 15. " FIRQPR_MIBADC1 ,FIQ/IRQ Program Control 15 - MIBADC1 sw group 1" "IRQ,FIQ" textline " " bitfld.long 0x00 14. " FIRQPR_MIBADC1 ,FIQ/IRQ Program Control 14 - MIBADC1 event group" "IRQ,FIQ" bitfld.long 0x00 13. " FIRQPR_LIN ,FIQ/IRQ Program Control 13 - LIN level 0" "IRQ,FIQ" bitfld.long 0x00 12. " FIRQPR_MIBSPI1 ,FIQ/IRQ Program Control 12 - MIBSPI1 level 0" "IRQ,FIQ" bitfld.long 0x00 11. " FIRQPR_HET_TU1 ,FIQ/IRQ Program Control 11 - HET TU1 level 0" "IRQ,FIQ" textline " " bitfld.long 0x00 10. " FIRQPR_N2HET1 ,FIQ/IRQ Program Control 10 - N2HET1 level 0" "IRQ,FIQ" bitfld.long 0x00 9. " FIRQPR_GIO ,FIQ/IRQ Program Control 9 - GIO interrupt A" "IRQ,FIQ" bitfld.long 0x00 8. " FIRQPR_RTI ,FIQ/IRQ Program Control 8 - RTI timebase interrupt" "IRQ,FIQ" bitfld.long 0x00 7. " FIRQPR_RTI ,FIQ/IRQ Program Control 7 - RTI overflow interrupt 1" "IRQ,FIQ" textline " " bitfld.long 0x00 6. " FIRQPR_RTI ,FIQ/IRQ Program Control 6 - RTI compare interrupt 0" "IRQ,FIQ" bitfld.long 0x00 5. " FIRQPR_RTI ,FIQ/IRQ Program Control 5 - RTI compare interrupt 3" "IRQ,FIQ" bitfld.long 0x00 4. " FIRQPR_RTI ,FIQ/IRQ Program Control 4 - RTI compare interrupt 2" "IRQ,FIQ" bitfld.long 0x00 3. " FIRQPR_RTI ,FIQ/IRQ Program Control 3 - RTI compare interrupt 1" "IRQ,FIQ" textline " " bitfld.long 0x00 2. " FIRQPR_RTI ,FIQ/IRQ Program Control 2 - RTI compare interrupt 0" "IRQ,FIQ" group.long 0x14++0x3 line.long 0x0 "FIRQPR1,Program Control 1 Register" bitfld.long 0x00 31. " FIRQPR_N2HET2 ,FIQ/IRQ Program Control 63 - N2HET2 level 0 interrupt" "IRQ,FIQ" bitfld.long 0x00 29. " FIRQPR_FMC ,FIQ/IRQ Program Control 61 - FSM_DONE interrupt" "IRQ,FIQ" bitfld.long 0x00 28. " FIRQPR_DCAN3 ,FIQ/IRQ Program Control 60 - DCAN3 IF3 interrupt" "IRQ,FIQ" bitfld.long 0x00 27. " FIRQPR_MIBADC2 ,FIQ/IRQ Program Control 59 - MibADC2 magnitude compare interrupt" "IRQ,FIQ" textline " " bitfld.long 0x00 25. " FIRQPR_MIBADC2 ,FIQ/IRQ Program Control 57 - MibADC2 sw group2 interrupt" "IRQ,FIQ" bitfld.long 0x00 24. " FIRQPR_MIBSPI5 ,FIQ/IRQ Program Control 56 - MIBSPI5 level 1 interrupt" "IRQ,FIQ" bitfld.long 0x00 23. " FIRQPR_DCAN3 ,FIQ/IRQ Program Control 55 - DCAN3 level 1 interrupt" "IRQ,FIQ" bitfld.long 0x00 22. " FIRQPR_SPI4 ,FIQ/IRQ Program Control 54 - SPI4 level 1 interrupt" "IRQ,FIQ" textline " " bitfld.long 0x00 21. " FIRQPR_MIBSPI5 ,FIQ/IRQ Program Control 53 - MIBSPI5 level 0 interrupt" "IRQ,FIQ" bitfld.long 0x00 19. " FIRQPR_MIBADC2 ,FIQ/IRQ Program Control 51 - MibADC2 sw group1 interrupt" "IRQ,FIQ" bitfld.long 0x00 18. " FIRQPR_MIBADC2 ,FIQ/IRQ Program Control 50 - MibADC2 event group interrupt" "IRQ,FIQ" bitfld.long 0x00 17. " FIRQPR_SPI4 ,FIQ/IRQ Program Control 49 - SPI4 level 0 interrupt" "IRQ,FIQ" textline " " bitfld.long 0x00 14. " FIRQPR_DCAN2 ,FIQ/IRQ Program Control 46 - DCAN1 IF3 interrupt" "IRQ,FIQ" bitfld.long 0x00 13. " FIRQPR_DCAN3 ,FIQ/IRQ Program Control 45 - DCAN3 level 0 interrupt" "IRQ,FIQ" bitfld.long 0x00 12. " FIRQPR_DCAN1 ,FIQ/IRQ Program Control 44 - DCAN1 IF3 interrupt" "IRQ,FIQ" textline " " bitfld.long 0x00 10. " FIRQPR_DCAN2 ,FIQ/IRQ Program Control 42 - DCAN2 level 1 interrupt" "IRQ,FIQ" bitfld.long 0x00 9. " FIRQPR_EMIF ,FIQ/IRQ Program Control 41 - AEMIFINT3" "IRQ,FIQ" bitfld.long 0x00 8. " FIRQPR_DMA ,FIQ/IRQ Program Control 40 - BTCA interrupt" "IRQ,FIQ" bitfld.long 0x00 7. " FIRQPR_DMA ,FIQ/IRQ Program Control 39 - HBCA interrupt" "IRQ,FIQ" textline " " bitfld.long 0x00 6. " FIRQPR_MIBSPI3 ,FIQ/IRQ Program Control 38 - MIBSPI3 level 1 interrupt" "IRQ,FIQ" bitfld.long 0x00 5. " FIRQPR_MIBSPI3 ,FIQ/IRQ Program Control 37 - MIBSPI3 level 0 interrupt" "IRQ,FIQ" bitfld.long 0x00 3. " FIRQPR_DCAN2 ,FIQ/IRQ Program Control 35 - DCAN2 level 0 interrupt" "IRQ,FIQ" bitfld.long 0x00 2. " FIRQPR_DMA ,FIQ/IRQ Program Control 34 - LFSA interrupt" "IRQ,FIQ" textline " " bitfld.long 0x00 1. " FIRQPR_DMA ,FIQ/IRQ Program Control 33 - FTCA interrupt" "IRQ,FIQ" group.long 0x18++0x3 line.long 0x0 "FIRQPR2,Program Control 2 Register" bitfld.long 0x00 31. " FIRQPR_ePWM3TZINTn ,FIQ/IRQ Program Control 95 - ePWM3 Trip Zone Interrupt" "IRQ,FIQ" bitfld.long 0x00 30. " FIRQPR_ePWM3INTn ,FIQ/IRQ Program Control 94 - ePWM3 Interrupt" "IRQ,FIQ" bitfld.long 0x00 29. " FIRQPR_ePWM2TZINTn ,FIQ/IRQ Program Control 93 - ePWM2 Trip Zone Interrupt" "IRQ,FIQ" bitfld.long 0x00 28. " FIRQPR_ePWM2INTn ,FIQ/IRQ Program Control 92 - ePWM2 Interrupt" "IRQ,FIQ" textline " " bitfld.long 0x00 27. " FIRQPR_ePWM1TZINTn ,FIQ/IRQ Program Control 91 - ePWM1 Trip Zone Interrupt" "IRQ,FIQ" bitfld.long 0x00 26. " FIRQPR_ePWM1INTn ,FIQ/IRQ Program Control 90 - ePWM1 Interrupt" "IRQ,FIQ" bitfld.long 0x00 25. " FIRQPR_HWAG2 ,FIQ/IRQ Program Control 89 - HWA_INT_REQ_L" "IRQ,FIQ" bitfld.long 0x00 24. " FIRQPR_HWAG1 ,FIQ/IRQ Program Control 88 - HWA_INT_REQ_L" "IRQ,FIQ" textline " " bitfld.long 0x00 21. " FIRQPR_PBIST ,FIQ/IRQ Program Control 85 - PBIST Done Interrupt" "IRQ,FIQ" bitfld.long 0x00 19. " FIRQPR_DCC2 ,FIQ/IRQ Program Control 83 - DCC2 done interrupt" "IRQ,FIQ" bitfld.long 0x00 18. " FIRQPR_DCC1 ,FIQ/IRQ Program Control 82 - DCC done interrupt" "IRQ,FIQ" bitfld.long 0x00 17. " FIRQPR_HWAG2 ,FIQ/IRQ Program Control 81 - HWA_INT_REQ_H" "IRQ,FIQ" textline " " bitfld.long 0x00 16. " FIRQPR_HWAG1 ,FIQ/IRQ Program Control 80 - HWA_INT_REQ_H" "IRQ,FIQ" textline " " sif (cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE") bitfld.long 0x00 15. " FIRQPR_ETHERNET ,FIQ/IRQ Program Control 79 - C0_RX_PULSE" "IRQ,FIQ" bitfld.long 0x00 14. " FIRQPR_ETHERNET ,FIQ/IRQ Program Control 78 - C0_THRESH_PULSE" "IRQ,FIQ" bitfld.long 0x00 13. " FIRQPR_ETHERNET ,FIQ/IRQ Program Control 77 - C0_TX_PULSE" "IRQ,FIQ" bitfld.long 0x00 12. " FIRQPR_ETHERNET ,FIQ/IRQ Program Control 76 - C0_MISC_PULSE" "IRQ,FIQ" textline " " endif bitfld.long 0x00 11. " FIRQPR_HET_TU2 ,FIQ/IRQ Program Control 75 - HET TU2 level 1 interrupt" "IRQ,FIQ" bitfld.long 0x00 10. " FIRQPR_SCI ,FIQ/IRQ Program Control 74 - C0_MISC_PULSE" "IRQ,FIQ" bitfld.long 0x00 9. " FIRQPR_N2HET2 ,FIQ/IRQ Program Control 73 - C0_TX_PULSE" "IRQ,FIQ" textline " " sif (cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE") bitfld.long 0x00 8. " FIRQPR_USBDEV ,FIQ/IRQ Program Control 72 - USB_FUNC.USBRESETO" "IRQ,FIQ" bitfld.long 0x00 7. " FIRQPR_USBDEV ,FIQ/IRQ Program Control 71 - not (USB_FUNC.DSWAKEREQON)" "IRQ,FIQ" bitfld.long 0x00 6. " FIRQPR_USBDEV ,FIQ/IRQ Program Control 70 - USB_FUNC.IRQNONISOON" "IRQ,FIQ" bitfld.long 0x00 5. " FIRQPR_USBDEV ,FIQ/IRQ Program Control 69 - USB_FUNC.IRQGENION" "IRQ,FIQ" textline " " bitfld.long 0x00 4. " FIRQPR_USBDEV ,FIQ/IRQ Program Control 68 - USB_FUNC.IRQISOON" "IRQ,FIQ" bitfld.long 0x00 3. " FIRQPR_HOST ,FIQ/IRQ Program Control 67 - OHCI_INT" "IRQ,FIQ" textline " " endif bitfld.long 0x00 2. " FIRQPR_I2C ,FIQ/IRQ Program Control 66 - I2C level 0 interrupt" "IRQ,FIQ" bitfld.long 0x00 1. " FIRQPR_HET_TU2 ,FIQ/IRQ Program Control 65 - HET TU2 level 0 interrupt" "IRQ,FIQ" bitfld.long 0x00 0. " FIRQPR_SCI ,FIQ/IRQ Program Control 64 - SCI level 0 interrupt" "IRQ,FIQ" width 9. tree "VIM Pending Interrupt Read Location Registers" rgroup.long 0x20++0x3 line.long 0x0 "INTREQ0,Pending Interrupt Read Location 0" bitfld.long 0x00 31. " INTREQ_MIBADC1 ,MIBADC1 magnitude compare interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 30. " INTREQ_SPI2 ,SPI2 level 1 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 29. " INTREQ_DCAN1 ,DCAN1 level 1 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 28. " INTREQ_MIBADC1 ,MIBADC1 sw group 2 interrupt Pending" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " INTREQ_LIN ,LIN level 1 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 26. " INTREQ_MIBSPI ,MIBSPI level 1 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 25. " INTREQ_HET_TU ,HET TU level 1 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 24. " INTREQ_N2HET1 ,N2HET1 level 1 interrupt Pending" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " INTREQ_GIO ,GIO interrupt B Pending" "No interrupt,Interrupt" bitfld.long 0x00 22. " INTREQ_CPU ,PMU Interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 21. " INTREQ_SYSTEM ,Software interrupt (SSI) Pending" "No interrupt,Interrupt" bitfld.long 0x00 20. " INTREQ_ESM ,ESM Low level interrupt Pending" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " INTREQ_CRC ,CRC Interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 17. " INTREQ_SPI2 ,SPI2 level 0 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 16. " INTREQ_DCAN1 ,DCAN1 level 0 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 15. " INTREQ_MIBADC1 ,MIBADC1 sw group 1 interrupt Pending" "No interrupt,Interrupt" textline " " bitfld.long 0x00 14. " INTREQ_MIBADC1 ,MIBADC1 event group interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 13. " INTREQ_LIN ,LIN level 0 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 12. " INTREQ_MIBSPI1 ,MIBSPI1 level 0 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 11. " INTREQ_HET_TU1 ,HET TU1 level 0 interrupt Pending" "No interrupt,Interrupt" textline " " bitfld.long 0x00 10. " INTREQ_N2HET1 ,N2HET1 level 0 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 9. " INTREQ_GIO ,GIO interrupt A Pending" "No interrupt,Interrupt" bitfld.long 0x00 8. " INTREQ_RTI ,RTI timebase interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 7. " INTREQ_RTI ,RTI overflow interrupt 1 Pending" "No interrupt,Interrupt" textline " " bitfld.long 0x00 6. " INTREQ_RTI ,RTI overflow interrupt 0 Pending" "No interrupt,Interrupt" bitfld.long 0x00 5. " INTREQ_RTI ,RTI compare interrupt 3 Pending" "No interrupt,Interrupt" bitfld.long 0x00 4. " INTREQ_RTI ,RTI compare interrupt 2 Pending" "No interrupt,Interrupt" bitfld.long 0x00 3. " INTREQ_RTI ,RTI compare interrupt 1 Pending" "No interrupt,Interrupt" textline " " bitfld.long 0x00 2. " INTREQ_RTI ,RTI compare interrupt 0 Pending" "No interrupt,Interrupt" bitfld.long 0x00 0. " INTREQ_ESM ,ESM High level interrupt (NMI) Pending" "No interrupt,Interrupt" rgroup.long 0x24++0x3 line.long 0x0 "INTREQ1,Pending Interrupt Read Location 1" bitfld.long 0x00 31. " INTREQ_N2HET2 ,N2HET2 level 0 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 29. " INTREQ_FMC ,FSM_DONE interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 28. " INTREQ_DCAN3 ,DCAN3 IF3 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 27. " INTREQ_MIBADC2 ,MibADC2 magnitude compare interrupt Pending" "No interrupt,Interrupt" textline " " bitfld.long 0x00 25. " INTREQ_MIBADC2 ,MibADC2 sw group2 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 24. " INTREQ_MIBSPI5 ,MIBSPI5 level 1 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 23. " INTREQ_DCAN3 ,DCAN3 level 1 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 22. " INTREQ_SPI4 ,SPI4 level 1 interrupt Pending" "No interrupt,Interrupt" textline " " bitfld.long 0x00 21. " INTREQ_MIBSPI5 ,MIBSPI5 level 0 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 19. " INTREQ_MIBADC2 ,MibADC2 sw group1 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 18. " INTREQ_MIBADC2 ,MibADC2 event group interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 17. " INTREQ_SPI4 ,SPI4 level 0 interrupt Pending" "No interrupt,Interrupt" textline " " bitfld.long 0x00 14. " INTREQ_DCAN2 ,DCAN2 IF3 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 13. " INTREQ_DCAN3 ,DCAN3 level 0 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 12. " INTREQ_DCAN1 ,DCAN1 IF3 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 10. " INTREQ_DCAN2 ,DCAN2 level 1 interrupt Pending" "No interrupt,Interrupt" textline " " bitfld.long 0x00 9. " INTREQ_EMIF ,AEMIFINT3 Pending" "No interrupt,Interrupt" bitfld.long 0x00 8. " INTREQ_DMA ,BTCA interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 7. " INTREQ_DMA ,HBCA interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 6. " INTREQ_MIBSPI3 ,MIBSPI3 level 1 interrupt Pending" "No interrupt,Interrupt" textline " " bitfld.long 0x00 5. " INTREQ_MIBSPI3 ,MIBSPI3 level 0 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 3. " INTREQ_DCAN2 ,DCAN2 level 0 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 2. " INTREQ_DMA ,LFSA interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 1. " INTREQ_DMA ,FTCA interrupt Pending" "No interrupt,Interrupt" rgroup.long 0x28++0x3 line.long 0x0 "INTREQ2,Pending Interrupt Read Location 2" bitfld.long 0x00 31. " INTREQ_ePWM3TZINTn ,ePWM3 Trip Zone Interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 30. " INTREQ_ePWM3INTn ,ePWM3 Interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 29. " INTREQ_ePWM2TZINTn ,ePWM2 Trip Zone Interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 28. " INTREQ_ePWM2INTn ,ePWM2 Interrupt Pending" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " INTREQ_ePWM1TZINTn ,ePWM1 Trip Zone Interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 26. " INTREQ_ePWM1INTn ,ePWM1 Interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 25. " INTREQ_HWAG2 ,HWA_INT_REQ_L Pending" "No interrupt,Interrupt" bitfld.long 0x00 24. " INTREQ_HWAG1 ,HWA_INT_REQ_L Pending" "No interrupt,Interrupt" textline " " bitfld.long 0x00 21. " INTREQ_PBIST ,PBIST Controller Pending" "No interrupt,Interrupt" bitfld.long 0x00 19. " INTREQ_DCC2 ,DCC2 done interrupt Pending " "No interrupt,Interrupt" bitfld.long 0x00 18. " INTREQ_DCC1 ,DCC done interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 17. " INTREQ_HWAG2 ,HWA_INT_REQ_H Pending" "No interrupt,Interrupt" textline " " bitfld.long 0x00 16. " INTREQ_HWAG1 ,HWA_INT_REQ_H Pending" "No interrupt,Interrupt" textline " " sif (cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE") bitfld.long 0x00 15. " INTREQ_ETHERNET ,C0_RX_PULSE Pending" "No interrupt,Interrupt" bitfld.long 0x00 14. " INTREQ_ETHERNET ,C0_THRESH_PULSE Pending" "No interrupt,Interrupt" bitfld.long 0x00 13. " INTREQ_ETHERNET ,C0_TX_PULSE Pending" "No interrupt,Interrupt" bitfld.long 0x00 12. " INTREQ_ETHERNET ,C0_MISC_PULSE Pending" "No interrupt,Interrupt" textline " " endif bitfld.long 0x00 11. " INTREQ_HET_TU2 ,HET TU2 level 1 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 10. " INTREQ_SCI ,SCI level 1 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 9. " INTREQ_N2HET2 ,N2HET2 level 1 interrupt Pending" "No interrupt,Interrupt" textline " " sif (cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE") bitfld.long 0x00 8. " INTREQ_USBDEV ,USB_FUNC.USBRESETO Pending" "No interrupt,Interrupt" bitfld.long 0x00 7. " INTREQ_USBDEV ,not (USB_FUNC.DSWAKEREQON) Pending" "No interrupt,Interrupt" bitfld.long 0x00 6. " INTREQ_USBDEV ,USB_FUNC.IRQNONISOON Pending" "No interrupt,Interrupt" bitfld.long 0x00 5. " INTREQ_USBDEV ,USB_FUNC.IRQGENION Pending" "No interrupt,Interrupt" textline " " bitfld.long 0x00 4. " INTREQ_USBDEV ,USB_FUNC.IRQISOON Pending" "No interrupt,Interrupt" bitfld.long 0x00 3. " INTREQ_USBHOST ,OHCI_INT Pending" "No interrupt,Interrupt" textline " " endif bitfld.long 0x00 2. " INTREQ_I2C ,I2C level 0 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 1. " INTREQ_HET_TU2 ,HET TU2 level 0 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 0. " INTREQ_SCI ,SCI level 0 interrupt Pending" "No interrupt,Interrupt" tree.end width 13. tree "VIM Interrupt Mask Registers" group.long 0x30++0x3 line.long 0x0 "REQENASET0,Interrupt Enable Set/Clr Register 0" setclrfld.long 0x00 31. 0x00 31. 0x10 31. " REQENA_31_set/clr ,MIBADC1 magnitude compare Request enable set bit 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x10 30. " REQENA_30_set/clr ,SPI2 level 1 Request enable set bit 30" "Disabled,Enabled" textline " " setclrfld.long 0x00 29. 0x00 29. 0x10 29. " REQENA_29_set/clr ,DCAN1 level 1 Request enable set bit 29" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x10 28. " REQENA_28_set/clr ,MIBADC sw group 2 Request enable set bit 28" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. 0x00 27. 0x10 27. " REQENA_27_set/clr ,LIN level 1 Request enable set bit 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x10 26. " REQENA_26_set/clr ,MIBSPI level 1 Request enable set bit 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x10 25. " REQENA_25_set/clr ,HET TU level 1 Request enable set bit 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x10 24. " REQENA_24_set/clr ,N2HET1 level 1 Request enable set bit 24" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. 0x00 23. 0x10 23. " REQENA_23_set/clr ,GIO interrupt B Request enable set bit 23" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x10 22. " REQENA_22_set/clr ,PMU Request enable set bit 22" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. 0x00 21. 0x10 21. " REQENA_21_set/clr ,Software interrupt (SSI) Request enable set bit 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x10 20. " REQENA_20_set/clr ,ESM Low level Request enable set bit 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x10 19. " REQENA_19_set/clr ,CRC Request enable set bit 19" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x10 17. " REQENA_17_set/clr ,SPI2 level 0 Request enable set bit 17" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x10 16. " REQENA_16_set/clr ,DCAN1 level 0 Request enable set bit 16" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x10 15. " REQENA_15_set/clr ,MIBADC1 sw group 1 Request enable set bit 15" "Disabled,Enabled" textline " " setclrfld.long 0x00 14. 0x00 14. 0x10 14. " REQENA_14_set/clr ,MIBADC1 event group Request enable set bit 14" "Disabled,Enabled" setclrfld.long 0x00 13. 0x00 13. 0x10 13. " REQENA_13_set/clr ,LIN level 0 Request enable set bit 13" "Disabled,Enabled" textline " " setclrfld.long 0x00 12. 0x00 12. 0x10 12. " REQENA_12_set/clr ,MIBSPI1 level 0 Request enable set bit 12" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x10 11. " REQENA_11_set/clr ,HET TU1 level 0 Request enable set bit 11" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x10 10. " REQENA_10_set/clr ,N2HET1 level 0 Request enable set bit 10" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x10 9. " REQENA_9_set/clr ,GIO interrupt A Request enable set bit 9" "Disabled,Enabled" textline " " setclrfld.long 0x00 8. 0x00 8. 0x10 8. " REQENA_8_set/clr ,RTI timebase Request enable set bit 8" "Disabled,Enabled" setclrfld.long 0x00 7. 0x00 7. 0x10 7. " REQENA_7_set/clr ,RTI overflow 1 Request enable set bit 7" "Disabled,Enabled" textline " " setclrfld.long 0x00 6. 0x00 6. 0x10 6. " REQENA_6_set/clr ,RTI overflow 0 Request enable set bit 6" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x10 5. " REQENA_5_set/clr ,RTI compare 3 Request enable set bit 5" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x10 4. " REQENA_4_set/clr ,RTI compare 2 Request enable set bit 4" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x10 3. " REQENA_3_set/clr ,RTI compare 1 Request enable set bit 3" "Disabled,Enabled" textline " " setclrfld.long 0x00 2. 0x00 2. 0x10 2. " REQENA_2_set/clr ,RTI compare 0 Request enable set bit 2" "Disabled,Enabled" group.long 0x34++0x3 line.long 0x0 "REQENASET1,Interrupt Enable Set/Clr Register 1" setclrfld.long 0x00 31. 0x00 31. 0x10 31. " REQENA_63_set/clr ,N2HET2 level 0 Request enable set bit 63" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x10 29. " REQENA_61_set/clr ,FSM_DONE Request enable set bit 61" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x10 28. " REQENA_60_set/clr ,DCAN3 IF3 Request enable set bit 60" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x10 27. " REQENA_59_set/clr ,MibADC2 magnitude compare Request enable set bit 59" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x10 25. " REQENA_57_set/clr ,MibADC2 sw group2 Request enable set bit 57" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x10 24. " REQENA_56_set/clr ,MIBSPI5 level 1 Request enable set bit 56" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. 0x00 23. 0x10 23. " REQENA_55_set/clr ,DCAN3 level 1 Request enable set bit 55" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x10 22. " REQENA_54_set/clr ,SPI4 level 1 Request enable set bit 54" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. 0x00 21. 0x10 21. " REQENA_53_set/clr ,MIBSPI5 level 0 Request enable set bit 53" "Disabled,Enabled" setclrfld.long 0x00 19. 0x00 19. 0x10 19. " REQENA_51_set/clr ,MibADC2 sw group1 Request enable set bit 51" "Disabled,Enabled" textline " " setclrfld.long 0x00 18. 0x00 18. 0x10 18. " REQENA_50_set/clr ,MibADC2 event group Request enable set bit 50" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x10 17. " REQENA_49_set/clr ,SPI4 level 0 Request enable set bit 49" "Disabled,Enabled" textline " " setclrfld.long 0x00 14. 0x00 14. 0x10 14. " REQENA_46_set/clr ,DCAN2 IF3 Request enable set bit 46" "Disabled,Enabled" setclrfld.long 0x00 13. 0x00 13. 0x10 13. " REQENA_45_set/clr ,DCAN3 level 0 Request enable set bit 45" "Disabled,Enabled" textline " " setclrfld.long 0x00 12. 0x00 12. 0x10 12. " REQENA_44_set/clr ,DCAN1 IF3 Request enable set bit 44" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x10 10. " REQENA_42_set/clr ,DCAN2 level 1 Request enable set bit 42" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. 0x00 9. 0x10 9. " REQENA_41_set/clr ,AEMIFINT3 Request enable set bit 41" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x10 8. " REQENA_40_set/clr ,BTCA Request enable set bit 40" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x10 7. " REQENA_39_set/clr ,HBCA Request enable set bit 39" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x10 6. " REQENA_38_set/clr ,MIBSPI3 level 1 Request enable set bit 38" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x00 5. 0x10 5. " REQENA_37_set/clr ,MIBSPI3 level 0 Request enable set bit 37" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x10 3. " REQENA_35_set/clr ,DCAN2 level 0 Request enable set bit 35" "Disabled,Enabled" textline " " setclrfld.long 0x00 2. 0x00 2. 0x10 2. " REQENA_34_set/clr ,LFSA Request enable set bit 34" "Disabled,Enabled" setclrfld.long 0x00 1. 0x00 1. 0x10 1. " REQENA_33_set/clr ,FTCA Request enable set bit 33" "Disabled,Enabled" group.long 0x38++0x3 line.long 0x0 "REQENASET2,Interrupt Enable Set/Clr Register 2" setclrfld.long 0x00 31. 0x00 31. 0x10 31. " REQENA_95_set/clr ,ePWM3 Trip Zone Interrupt Request enable set bit 95" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x10 30. " REQENA_94_set/clr ,ePWM3 Interrupt Request enable set bit 94" "Disabled,Enabled" textline " " setclrfld.long 0x00 29. 0x00 29. 0x10 29. " REQENA_94_set/clr ,ePWM3 Interrupt enable set bit 94" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x10 28. " REQENA_92_set/clr ,ePWM2 Interrupt Request enable set bit 92" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. 0x00 27. 0x10 27. " REQENA_91_set/clr ,ePWM1 Trip Zone Interrupt Request enable set bit 91" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x10 26. " REQENA_90_set/clr ,ePWM1 Interrupt Request enable set bit 90" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x10 25. " REQENA_89_set/clr ,HWA_INT_REQ_L Request enable set bit 89" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x10 24. " REQENA_88_set/clr ,HWA_INT_REQ_L Request enable set bit 88" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. 0x00 21. 0x10 21. " REQENA_85_set/clr ,PBIST Done Interrupt Request enable set bit 83" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x10 19. " REQENA_83_set/clr ,DCC2 done interrupt Request enable set bit 83" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x10 18. " REQENA_82_set/clr ,DCC done Request enable set bit 82" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. 0x00 17. 0x10 17. " REQENA_81_set/clr ,HWA_INT_REQ_H Request enable set bit 81" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x10 16. " REQENA_80_set/clr ,HWA_INT_REQ_H Request enable set bit 80" "Disabled,Enabled" textline " " sif (cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE") setclrfld.long 0x00 15. 0x00 15. 0x10 15. " REQENA_79_set/clr ,C0_RX_PULSE Request enable set bit 89" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x10 14. " REQENA_78_set/clr ,C0_THRESH_PULSE Request enable set bit 88" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x10 13. " REQENA_77_set/clr ,C0_TX_PULSE Request enable set bit 83" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x10 12. " REQENA_76_set/clr ,C0_MISC_PULSE Request enable set bit 82" "Disabled,Enabled" textline " " endif setclrfld.long 0x00 11. 0x00 11. 0x10 11. " REQENA_75_set/clr ,HET TU2 level 1 Request enable set bit 75" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x10 10. " REQENA_74_set/clr ,SCI level 1 Request enable set bit 74" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. 0x00 9. 0x10 9. " REQENA_73_set/clr ,N2HET2 level 1 Request enable set bit 73" "Disabled,Enabled" textline " " sif (cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE") setclrfld.long 0x00 8. 0x00 8. 0x10 8. " REQENA_72_set/clr ,USB_FUNC.USBRESETO Request enable set bit 89" "Disabled,Enabled" setclrfld.long 0x00 7. 0x00 7. 0x10 7. " REQENA_71_set/clr ,not (USB_FUNC.DSWAKEREQON) Request enable set bit 88" "Disabled,Enabled" textline " " setclrfld.long 0x00 6. 0x00 6. 0x10 6. " REQENA_70_set/clr ,USB_FUNC.IRQNONISOON Request enable set bit 83" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x10 5. " REQENA_69_set/clr ,USB_FUNC.IRQGENION Request enable set bit 82" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x10 4. " REQENA_68_set/clr ,USB_FUNC.IRQISOON Request enable set bit 83" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x10 3. " REQENA_67_set/clr ,OHCI_INT Request enable set bit 82" "Disabled,Enabled" textline " " endif setclrfld.long 0x00 2. 0x00 2. 0x10 2. " REQENA_66_set/clr ,I2C level 0 Request enable set bit 66" "Disabled,Enabled" setclrfld.long 0x00 1. 0x00 1. 0x10 1. " REQENA_65_set/clr ,HET TU2 level 0 Request enable set bit 65" "Disabled,Enabled" textline " " setclrfld.long 0x00 0. 0x00 0. 0x10 0. " REQENA_64_set/clr ,SCI level 0 Request enable set bit 64" "Disabled,Enabled" tree.end width 14. tree "VIM Wake Up Mask Registers" group.long 0x50++0x3 line.long 0x0 "WAKEENASET0,Wake-up Enable Set Register 0" setclrfld.long 0x00 31. 0x00 31. 0x10 31. " WAKEENA_31_set/clr ,MIBADC1 magnitude compare interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x10 30. " WAKEENA_30_set/clr ,SPI2 level 1 interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 29. 0x00 29. 0x10 29. " WAKEENA_29_set/clr ,DCAN1 level 1 interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x10 28. " WAKEENA_28_set/clr ,MIBADC sw group 2 interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. 0x00 27. 0x10 27. " WAKEENA_27_set/clr ,LIN level 1 interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x10 26. " WAKEENA_26_set/clr ,MIBSPI level 1 interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x10 25. " WAKEENA_25_set/clr ,HET TU level 1 interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x10 24. " WAKEENA_24_set/clr ,N2HET1 level 1 interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. 0x00 23. 0x10 23. " WAKEENA_23_set/clr ,GIO interrupt B Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x10 22. " WAKEENA_22_set/clr ,PMU Interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. 0x00 21. 0x10 21. " WAKEENA_21_set/clr ,Software interrupt (SSI) Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x10 20. " WAKEENA_20_set/clr ,ESM Low level interrupt Wake-up" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x10 19. " WAKEENA_19_set/clr ,CRC Interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x10 17. " WAKEENA_17_set/clr ,SPI2 level 0 interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x10 16. " WAKEENA_16_set/clr ,DCAN1 level 0 interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x10 15. " WAKEENA_15_set/clr ,MIBADC1 sw group 1 interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 14. 0x00 14. 0x10 14. " WAKEENA_14_set/clr ,MIBADC1 event group interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 13. 0x00 13. 0x10 13. " WAKEENA_13_set/clr ,LIN level 0 interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 12. 0x00 12. 0x10 12. " WAKEENA_12_set/clr ,MIBSPI1 level 0 interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x10 11. " WAKEENA_11_set/clr ,HET TU1 level 0 interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x10 10. " WAKEENA_10_set/clr ,N2HET1 level 0 interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x10 9. " WAKEENA_9_set/clr ,GIO interrupt A Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 8. 0x00 8. 0x10 8. " WAKEENA_8_set/clr ,RTI timebase interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 7. 0x00 7. 0x10 7. " WAKEENA_7_set/clr ,RTI overflow interrupt 1 Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 6. 0x00 6. 0x10 6. " WAKEENA_6_set/clr ,RTI overflow interrupt 0 Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x10 5. " WAKEENA_5_set/clr ,RTI compare interrupt 3 Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x10 4. " WAKEENA_4_set/clr ,RTI compare interrupt 2 Wake-up" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x10 3. " WAKEENA_3_set/clr ,RTI compare interrupt 1 Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 2. 0x00 2. 0x10 2. " WAKEENA_2_set/clr ,RTI compare interrupt 0 Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x10 0. " WAKEENA_0_set/clr ,ESM High level interrupt (NMI) Wake-up enable" "Disabled,Enabled" group.long 0x54++0x3 line.long 0x0 "WAKEENASET1,Wake-up Enable Set Register 1" setclrfld.long 0x00 31. 0x00 31. 0x10 31. " WAKEENA_63_set/clr ,N2HET2 level 0 interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x10 29. " WAKEENA_61_set/clr ,FSM_DONE interrupt Wake-up enable set" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x10 28. " WAKEENA_60_set/clr ,DCAN3 IF3 interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x10 27. " WAKEENA_59_set/clr ,MibADC2 magnitude compare interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x10 25. " WAKEENA_57_set/clr ,MibADC2 sw group2 interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x10 24. " WAKEENA_56_set/clr ,MIBSPI5 level 1 interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. 0x00 23. 0x10 23. " WAKEENA_55_set/clr ,DCAN3 level 1 interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x10 22. " WAKEENA_54_set/clr ,SPI4 level 1 interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. 0x00 21. 0x10 21. " WAKEENA_53_set/clr ,MIBSPI5 level 0 interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 19. 0x00 19. 0x10 19. " WAKEENA_51_set/clr ,MibADC2 sw group1 interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 18. 0x00 18. 0x10 18. " WAKEENA_50_set/clr ,MibADC2 event group interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x10 17. " WAKEENA_49_set/clr ,SPI4 level 0 interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 14. 0x00 14. 0x10 14. " WAKEENA_46_set/clr ,DCAN2 IF3 interrupt Wake-up enable set bit 46" "Disabled,Enabled" setclrfld.long 0x00 13. 0x00 13. 0x10 13. " WAKEENA_45_set/clr ,DCAN3 level 0 interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 12. 0x00 12. 0x10 12. " WAKEENA_44_set/clr ,DCAN1 IF3 interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x10 10. " WAKEENA_42_set/clr ,DCAN2 level 1 interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. 0x00 9. 0x10 9. " WAKEENA_41_set/clr ,AEMIFINT3 Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x10 8. " WAKEENA_40_set/clr ,BTCA interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x10 7. " WAKEENA_39_set/clr ,HBCA interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x10 6. " WAKEENA_38_set/clr ,MIBSPI3 level 1 interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x00 5. 0x10 5. " WAKEENA_37_set/clr ,MIBSPI3 level 0 interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x10 3. " WAKEENA_35_set/clr ,DCAN2 level 0 interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 2. 0x00 2. 0x10 2. " WAKEENA_34_set/clr ,LFSA interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 1. 0x00 1. 0x10 1. " WAKEENA_33_set/clr ,FTCA interrupt Wake-up enable" "Disabled,Enabled" group.long 0x58++0x3 line.long 0x0 "WAKEENASET2,Wake-up Enable Set Register 2" setclrfld.long 0x00 31. 0x00 31. 0x10 31. " WAKEENA_95_set/clr ,ePWM3 Trip Zone Interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x10 30. " WAKEENA_94_set/clr ,ePWM3 Interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 29. 0x00 29. 0x10 29. " WAKEENA_93_set/clr ,ePWM2 Trip Zone Interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x10 28. " WAKEENA_92_set/clr ,ePWM2 Interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. 0x00 27. 0x10 27. " WAKEENA_91_set/clr ,ePWM1 Trip Zone Interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x10 26. " WAKEENA_90_set/clr ,ePWM1 Interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x10 25. " WAKEENA_89_set/clr ,HWA_INT_REQ_L Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x10 24. " WAKEENA_88_set/clr ,HWA_INT_REQ_L Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. 0x00 21. 0x10 21. " WAKEENA_85_set/clr ,PBIST Done Interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x10 19. " WAKEENA_83_set/clr ,Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x10 18. " WAKEENA_82_set/clr ,DCC done interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. 0x00 17. 0x10 17. " WAKEENA_81_set/clr ,HWA_INT_REQ_H Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x10 16. " WAKEENA_80_set/clr ,HWA_INT_REQ_H Wake-up enable" "Disabled,Enabled" textline " " sif (cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE") setclrfld.long 0x00 15. 0x00 15. 0x10 15. " WAKEENA_79_set/clr ,C0_RX_PULSE Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x10 14. " WAKEENA_78_set/clr ,C0_THRESH_PULSE interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x10 13. " WAKEENA_77_set/clr ,C0_TX_PULSE Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x10 12. " WAKEENA_76_set/clr ,C0_MISC_PULSE Wake-up enable" "Disabled,Enabled" textline " " endif setclrfld.long 0x00 11. 0x00 11. 0x10 11. " WAKEENA_75_set/clr ,HET TU2 level 1 interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x10 10. " WAKEENA_74_set/clr ,SCI level 1 interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. 0x00 9. 0x10 9. " WAKEENA_73_set/clr ,N2HET2 level 1 interrupt Wake-up enable" "Disabled,Enabled" textline " " sif (cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE") setclrfld.long 0x00 8. 0x00 8. 0x10 8. " WAKEENA_72_set/clr ,USB_FUNC.USBRESETO interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 7. 0x00 7. 0x10 7. " WAKEENA_71_set/clr ,not (USB_FUNC.DSWAKEREQON) interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 6. 0x00 6. 0x10 6. " WAKEENA_70_set/clr ,USB_FUNC.IRQNONISOON interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x10 5. " WAKEENA_69_set/clr ,USB_FUNC.IRQGENION interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x10 4. " WAKEENA_68_set/clr ,USB_FUNC.IRQISOON interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x10 3. " WAKEENA_67_set/clr ,OHCI_INT interrupt Wake-up enable" "Disabled,Enabled" textline " " endif setclrfld.long 0x00 2. 0x00 2. 0x10 2. " WAKEENA_66_set/clr ,I2C level 0 interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 1. 0x00 1. 0x10 1. " WAKEENA_65_set/clr ,HET TU2 level 0 interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 0. 0x00 0. 0x10 0. " WAKEENA_64_set/clr ,SCI level 0 interrupt Wake-up enable" "Disabled,Enabled" tree.end width 11. tree "VIM Interrupt Vector Registers" rgroup.long 0x70++0x3 line.long 0x0 "IRQVECREG,IRQ Interrupt Vector Register" rgroup.long 0x74++0x3 line.long 0x0 "FIQVECREG,FIQ Interrupt Vector Register" tree.end width 11. group.long 0x78++0x3 line.long 0x0 "CAPEVTSRC,Capture Event register" hexmask.long.byte 0x00 16.--22. 1. " CAPEVTSRC1[6:0] ,Capture Event Source 1 Mapping Control" hexmask.long.byte 0x00 0.--6. 1. " CAPEVTSRC0[6:0] ,Capture Event Source 0 Mapping Control" width 12. tree "VIM Interrupt Control Registers" group.long 0x80++0x3 line.long 0x0 "CHANCTRL0,VIM Interrupt Control Register 0" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP0[6:0] ,ESM High level interrupt (NMI) CHAN0 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP2[6:0] ,RTI compare interrupt 0 CHAN2 Mapping Control" hexmask.long.byte 0x00 0.--6. 1. " CHANMAP3[6:0] ,RTI compare interrupt 1 CHAN3 Mapping Control" group.long 0x84++0x3 line.long 0x0 "CHANCTRL1,VIM Interrupt Control Register 1" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP4[6:0] ,RTI compare interrupt 2 CHAN4 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP5[6:0] ,RTI compare interrupt 3 CHAN5 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP6[6:0] ,RTI overflow interrupt 0 CHAN6 Mapping Control" textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP7[6:0] ,RTI overflow interrupt 1 CHAN7 Mapping Control" group.long 0x88++0x3 line.long 0x0 "CHANCTRL2,VIM Interrupt Control Register 2" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP8[6:0] ,RTI timebase interrupt CHAN8 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP9[6:0] ,GIO interrupt A CHAN9 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP10[6:0] ,N2HET1 level 0 interrupt CHAN10 Mapping Control" textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP11[6:0] ,HET TU1 level 0 interrupt CHAN11 Mapping Control" group.long 0x8C++0x3 line.long 0x0 "CHANCTRL3,VIM Interrupt Control Register 3" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP12[6:0] ,MIBSPI1 level 0 interrupt CHAN12 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP13[6:0] ,LIN level 0 interrupt CHAN13 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP14[6:0] ,MIBADC1 event group interrupt CHAN14 Mapping Control" textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP15[6:0] ,MIBADC1 sw group 1 interrupt CHAN15 Mapping Control" group.long 0x90++0x3 line.long 0x0 "CHANCTRL4,VIM Interrupt Control Register 4" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP16[6:0] ,DCAN1 level 0 interrupt CHAN16 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP17[6:0] ,SPI2 level 0 interrupt CHAN17 Mapping Control" hexmask.long.byte 0x00 0.--6. 1. " CHANMAP19[6:0] ,CRC Interrupt CHAN19 Mapping Control" group.long 0x94++0x3 line.long 0x0 "CHANCTRL5,VIM Interrupt Control Register 5" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP20[6:0] ,ESM Low level interrupt CHAN20 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP21[6:0] ,Software interrupt (SSI) CHAN21 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP22[6:0] ,PMU Interrupt CHAN22 Mapping Control" textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP23[6:0] ,GIO interrupt B CHAN23 Mapping Control" group.long 0x98++0x3 line.long 0x0 "CHANCTRL6,VIM Interrupt Control Register 6" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP24[6:0] ,N2HET1 level 1 interrupt CHAN24 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP25[6:0] ,HET TU level 1 interrupt CHAN25 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP26[6:0] ,MIBSPI level 1 interrupt CHAN26 Mapping Control" textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP27[6:0] ,LIN level 1 interrupt CHAN27 Mapping Control" group.long 0x9C++0x3 line.long 0x0 "CHANCTRL7,VIM Interrupt Control Register 7" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP28[6:0] ,MIBADC sw group 2 interrupt CHAN28 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP29[6:0] ,DCAN1 level 1 interrupt CHAN29 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP30[6:0] ,SPI2 level 1 interrupt CHAN30 Mapping Control" textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP31[6:0] ,MIBADC1 magnitude compare interrupt CHAN31 Mapping Control" group.long 0xA0++0x3 line.long 0x0 "CHANCTRL8,VIM Interrupt Control Register 8" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP33[6:0] ,FTCA interrupt CHAN33 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP34[6:0] ,LFSA interrupt CHAN34 Mapping Control" textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP35[6:0] ,DCAN2 level 0 interrupt CHAN35 Mapping Control" group.long 0xA4++0x3 line.long 0x0 "CHANCTRL9,VIM Interrupt Control Register 9" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP36[6:0] ,DMM level 0 interrupt CHAN36 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP37[6:0] ,MIBSPI3 level 0 interrupt CHAN37 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP38[6:0] ,MIBSPI3 level 1 interrupt CHAN38 Mapping Control" textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP39[6:0] ,HBCA interrupt CHAN39 Mapping Control" group.long 0xA8++0x3 line.long 0x0 "CHANCTRL10,VIM Interrupt Control Register 10" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP40[6:0] ,BTCA interrupt CHAN40 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP41[6:0] ,AEMIFINT3 interrupt CHAN41 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP42[6:0] ,DCAN2 level 1 interrupt CHAN42 Mapping Control" textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP43[6:0] ,DMM level 1 interrupt CHAN43 Mapping Control" group.long 0xAC++0x3 line.long 0x0 "CHANCTRL11,VIM Interrupt Control Register 11" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP44[6:0] ,DCAN1 IF3 interrupt CHAN44 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP45[6:0] ,DCAN3 level 0 interrupt CHAN45 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP46[6:0] ,DCAN2 IF3 interrupt CHAN46 Mapping Control" textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP47[6:0] ,FPU interrupt CHAN47 Mapping Control" group.long 0xB0++0x3 line.long 0x0 "CHANCTRL12,VIM Interrupt Control Register 12" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP49[6:0] ,SPI4 level 0 interrupt CHAN49 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP50[6:0] ,MibADC2 event group interrupt CHAN50 Mapping Control" textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP51[6:0] ,MibADC2 sw group1 interrupt CHAN51 Mapping Control" group.long 0xB4++0x3 line.long 0x0 "CHANCTRL13,VIM Interrupt Control Register 13" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP53[6:0] ,MIBSPI5 level 0 interrupt CHAN53 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP54[6:0] ,SPI4 level 1 interrupt CHAN54 Mapping Control" textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP55[6:0] ,DCAN3 level 1 interrupt CHAN55 Mapping Control" group.long 0xB8++0x3 line.long 0x0 "CHANCTRL14,VIM Interrupt Control Register 14" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP56[6:0] ,MIBSPI5 level 1 interrupt CHAN56 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP57[6:0] ,MibADC2 sw group2 interrupt CHAN57 Mapping Control" hexmask.long.byte 0x00 0.--6. 1. " CHANMAP59[6:0] ,MibADC2 magnitude compare interrupt CHAN59 Mapping Control" group.long 0xBC++0x3 line.long 0x0 "CHANCTRL15,VIM Interrupt Control Register 15" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP60[6:0] ,DCAN3 IF3 interrupt CHAN60 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP61[6:0] ,FSM_DONE interrupt CHAN61 Mapping Control" hexmask.long.byte 0x00 0.--6. 1. " CHANMAP63[6:0] ,N2HET2 level 0 interrupt CHAN63 Mapping Control" group.long 0xC0++0x3 line.long 0x0 "CHANCTRL16,VIM Interrupt Control Register 16" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP64[6:0] ,SCI level 0 interrupt CHAN64 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP65[6:0] ,HET TU2 level 0 interrupt CHAN65 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP66[6:0] ,I2C level 0 interrupt CHAN66 Mapping Control" sif (cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE") textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP67[6:0] ,OHCI_INT interrupt CHAN67 Mapping Control" endif group.long 0xC4++0x3 line.long 0x0 "CHANCTRL17,Channel Mapping Register" sif (cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE") hexmask.long.byte 0x00 24.--30. 1. " CHANMAP68[6:0] ,USB_FUNC.IRQISOON CHAN68 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP69[6:0] ,USB_FUNC.IRQGENION interrupt CHAN69 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP70[6:0] ,USB_FUNC.IRQNONISOON interrupt CHAN70 Mapping Control" textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP71[6:0] ,not (USB_FUNC.DSWAKEREQON) interrupt CHAN71 Mapping Control" endif group.long 0xC8++0x3 line.long 0x0 "CHANCTRL18,VIM Interrupt Control Register 18" sif (cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE") hexmask.long.byte 0x00 24.--30. 1. " CHANMAP72[6:0] ,USB_FUNC.USBRESETO interrupt CHAN72 Mapping Control" textline " " endif hexmask.long.byte 0x00 16.--22. 1. " CHANMAP73[6:0] ,N2HET2 level 1 interrupt CHAN73 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP74[6:0] ,SCI level 1 interrupt CHAN74 Mapping Control" hexmask.long.byte 0x00 0.--6. 1. " CHANMAP75[6:0] ,HET TU2 level 1 interrupt CHAN75 Mapping Control" group.long 0xCC++0x3 line.long 0x0 "CHANCTRL19,VIM Interrupt Control Register 19" sif (cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE") hexmask.long.byte 0x00 24.--30. 1. " CHANMAP76[6:0] ,C0_MISC_PULSE interrupt CHAN76 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP77[6:0] ,C0_TX_PULSE interrupt CHAN77 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP78[6:0] ,C0_THRESH_PULSE interrupt CHAN78 Mapping Control" textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP79[6:0] ,C0_RX_PULSE interrupt CHAN79 Mapping Control" endif group.long 0xD0++0x3 line.long 0x0 "CHANCTRL20,VIM Interrupt Control Register 20" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP80[6:0] ,HWA_INT_REQ_H Interrupt CHAN80 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP81[6:0] ,HWA_INT_REQ_H Interrupt CHAN81 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP82[6:0] ,DCC done interrupt CHAN82 Mapping Control" textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP83[6:0] ,DCC2 done interrupt CHAN83 Mapping Control" group.long 0xD4++0x3 line.long 0x0 "CHANCTRL21,Channel Mapping Register" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP81[6:0] ,PBIST Done Interrupt CHAN85 Mapping Control" group.long 0xD8++0x3 line.long 0x0 "CHANCTRL22,VIM Interrupt Control Register 22" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP88[6:0] ,HWA_INT_REQ_L Interrupt CHAN88 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP89[6:0] ,HWA_INT_REQ_L Interrupt CHAN89 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP90[6:0] ,ePWM1 Interrupt CHAN90 Mapping Control" textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP91[6:0] ,ePWM1 Trip Zone Interrupt CHAN91 Mapping Control" group.long 0xDC++0x3 line.long 0x0 "CHANCTRL23,Channel Mapping Register" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP92[6:0] ,ePWM2 Interrupt CHAN92 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP93[6:0] ,ePWM2 Trip Zone Interrupt CHAN93 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP94[6:0] ,ePWM3 Interrupt CHAN94 Mapping Control" textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP95[6:0] ,ePWM3 Trip Zone Interrupt CHAN95 Mapping Control" tree.end width 0xb tree.end else tree "VIM" base ad:0xFFFFFE00 width 9. tree "VIM Offset Vector Registers" rgroup.long 0x00++0x3 line.long 0x0 "IRQINDEX,IRQ Index Offset Vector Register" hexmask.long.byte 0x00 0.--7. 1. " IRQINDEX ,IRQ index vector" rgroup.long 0x04++0x3 line.long 0x0 "FIQINDEX,FIQ Index Offset Vector Register" hexmask.long.byte 0x00 0.--7. 1. " FIQINDEX ,FIQ index offset vector" tree.end width 9. group.long 0x10++0x3 line.long 0x0 "FIRQPR0,Program Control 0 Register" bitfld.long 0x00 31. " FIRQPR_MIBADC1 ,FIQ/IRQ Program Control 31 - MIBADC1 magnitude compare interrupt" "IRQ,FIQ" bitfld.long 0x00 30. " FIRQPR_SPI2 ,FIQ/IRQ Program Control 30 - SPI2 level 1 interrupt" "IRQ,FIQ" bitfld.long 0x00 29. " FIRQPR_DCAN1 ,FIQ/IRQ Program Control 29 - DCAN1 level 1 interrupt" "IRQ,FIQ" bitfld.long 0x00 28. " FIRQPR_MIBADC ,FIQ/IRQ Program Control 28 - MIBADC sw group 2 interrupt" "IRQ,FIQ" textline " " bitfld.long 0x00 27. " FIRQPR_LIN ,FIQ/IRQ Program Control 27 - LIN level 1 interrupt" "IRQ,FIQ" bitfld.long 0x00 26. " FIRQPR_MIBSPI ,FIQ/IRQ Program Control 26 - MIBSPI level 1 interrupt" "IRQ,FIQ" bitfld.long 0x00 25. " FIRQPR_HET_TU ,FIQ/IRQ Program Control 25 - HET TU level 1 interrupt" "IRQ,FIQ" bitfld.long 0x00 24. " FIRQPR_N2HET1 ,FIQ/IRQ Program Control 24 - N2HET1 level 1 interrupt" "IRQ,FIQ" textline " " bitfld.long 0x00 23. " FIRQPR_GIO ,FIQ/IRQ Program Control 23 - GIO interrupt B" "IRQ,FIQ" bitfld.long 0x00 22. " FIRQPR_CPU ,FIQ/IRQ Program Control 22 - PMU Interrupt" "IRQ,FIQ" bitfld.long 0x00 21. " FIRQPR_SYSTEM ,FIQ/IRQ Program Control 21 - Software interrupt (SSI)" "IRQ,FIQ" bitfld.long 0x00 20. " FIRQPR_ESM ,FIQ/IRQ Program Control 20 - ESM Low level interrupt" "IRQ,FIQ" textline " " bitfld.long 0x00 19. " FIRQPR_CRC ,FIQ/IRQ Program Control 19 - CRC Interrupt" "IRQ,FIQ" bitfld.long 0x00 17. " FIRQPR_SPI2 ,FIQ/IRQ Program Control 17 - SPI2 level 0 interrupt" "IRQ,FIQ" bitfld.long 0x00 16. " FIRQPR_DCAN1 ,FIQ/IRQ Program Control 16 - DCAN1 level 0 interrupt" "IRQ,FIQ" bitfld.long 0x00 15. " FIRQPR_MIBADC1 ,FIQ/IRQ Program Control 15 - MIBADC1 sw group 1" "IRQ,FIQ" textline " " bitfld.long 0x00 14. " FIRQPR_MIBADC1 ,FIQ/IRQ Program Control 14 - MIBADC1 event group" "IRQ,FIQ" bitfld.long 0x00 13. " FIRQPR_LIN ,FIQ/IRQ Program Control 13 - LIN level 0" "IRQ,FIQ" bitfld.long 0x00 12. " FIRQPR_MIBSPI1 ,FIQ/IRQ Program Control 12 - MIBSPI1 level 0" "IRQ,FIQ" bitfld.long 0x00 11. " FIRQPR_HET_TU1 ,FIQ/IRQ Program Control 11 - HET TU1 level 0" "IRQ,FIQ" textline " " bitfld.long 0x00 10. " FIRQPR_N2HET1 ,FIQ/IRQ Program Control 10 - N2HET1 level 0" "IRQ,FIQ" bitfld.long 0x00 9. " FIRQPR_GIO ,FIQ/IRQ Program Control 9 - GIO interrupt A" "IRQ,FIQ" bitfld.long 0x00 8. " FIRQPR_RTI ,FIQ/IRQ Program Control 8 - RTI timebase interrupt" "IRQ,FIQ" bitfld.long 0x00 7. " FIRQPR_RTI ,FIQ/IRQ Program Control 7 - RTI overflow interrupt 1" "IRQ,FIQ" textline " " bitfld.long 0x00 6. " FIRQPR_RTI ,FIQ/IRQ Program Control 6 - RTI compare interrupt 0" "IRQ,FIQ" bitfld.long 0x00 5. " FIRQPR_RTI ,FIQ/IRQ Program Control 5 - RTI compare interrupt 3" "IRQ,FIQ" bitfld.long 0x00 4. " FIRQPR_RTI ,FIQ/IRQ Program Control 4 - RTI compare interrupt 2" "IRQ,FIQ" bitfld.long 0x00 3. " FIRQPR_RTI ,FIQ/IRQ Program Control 3 - RTI compare interrupt 1" "IRQ,FIQ" textline " " bitfld.long 0x00 2. " FIRQPR_RTI ,FIQ/IRQ Program Control 2 - RTI compare interrupt 0" "IRQ,FIQ" group.long 0x14++0x3 line.long 0x0 "FIRQPR1,Program Control 1 Register" bitfld.long 0x00 31. " FIRQPR_N2HET2 ,FIQ/IRQ Program Control 63 - N2HET2 level 0 interrupt" "IRQ,FIQ" bitfld.long 0x00 29. " FIRQPR_FMC ,FIQ/IRQ Program Control 61 - FSM_DONE interrupt" "IRQ,FIQ" bitfld.long 0x00 28. " FIRQPR_DCAN3 ,FIQ/IRQ Program Control 60 - DCAN3 IF3 interrupt" "IRQ,FIQ" bitfld.long 0x00 27. " FIRQPR_MIBADC2 ,FIQ/IRQ Program Control 59 - MibADC2 magnitude compare interrupt" "IRQ,FIQ" textline " " bitfld.long 0x00 25. " FIRQPR_MIBADC2 ,FIQ/IRQ Program Control 57 - MibADC2 sw group2 interrupt" "IRQ,FIQ" bitfld.long 0x00 24. " FIRQPR_MIBSPI5 ,FIQ/IRQ Program Control 56 - MIBSPI5 level 1 interrupt" "IRQ,FIQ" bitfld.long 0x00 23. " FIRQPR_DCAN3 ,FIQ/IRQ Program Control 55 - DCAN3 level 1 interrupt" "IRQ,FIQ" bitfld.long 0x00 22. " FIRQPR_SPI4 ,FIQ/IRQ Program Control 54 - SPI4 level 1 interrupt" "IRQ,FIQ" textline " " bitfld.long 0x00 21. " FIRQPR_MIBSPI5 ,FIQ/IRQ Program Control 53 - MIBSPI5 level 0 interrupt" "IRQ,FIQ" bitfld.long 0x00 19. " FIRQPR_MIBADC2 ,FIQ/IRQ Program Control 51 - MibADC2 sw group1 interrupt" "IRQ,FIQ" bitfld.long 0x00 18. " FIRQPR_MIBADC2 ,FIQ/IRQ Program Control 50 - MibADC2 event group interrupt" "IRQ,FIQ" bitfld.long 0x00 17. " FIRQPR_SPI4 ,FIQ/IRQ Program Control 49 - SPI4 level 0 interrupt" "IRQ,FIQ" textline " " bitfld.long 0x00 15. " FIRQPR_FPU ,FIQ/IRQ Program Control 47 - DMM level 1 interrupt" "IRQ,FIQ" bitfld.long 0x00 14. " FIRQPR_DCAN2 ,FIQ/IRQ Program Control 46 - DCAN1 IF3 interrupt" "IRQ,FIQ" bitfld.long 0x00 13. " FIRQPR_DCAN3 ,FIQ/IRQ Program Control 45 - DCAN3 level 0 interrupt" "IRQ,FIQ" bitfld.long 0x00 12. " FIRQPR_DCAN1 ,FIQ/IRQ Program Control 44 - DCAN1 IF3 interrupt" "IRQ,FIQ" textline " " bitfld.long 0x00 11. " FIRQPR_DMM ,FIQ/IRQ Program Control 43 - DMM level 1 interrupt" "IRQ,FIQ" bitfld.long 0x00 10. " FIRQPR_EMIF ,FIQ/IRQ Program Control 42 - AEMIFINT3" "IRQ,FIQ" bitfld.long 0x00 8. " FIRQPR_DMA ,FIQ/IRQ Program Control 40 - BTCA interrupt" "IRQ,FIQ" bitfld.long 0x00 7. " FIRQPR_DMA ,FIQ/IRQ Program Control 39 - HBCA interrupt" "IRQ,FIQ" textline " " bitfld.long 0x00 6. " FIRQPR_MIBSPI3 ,FIQ/IRQ Program Control 38 - MIBSPI3 level 1 interrupt" "IRQ,FIQ" bitfld.long 0x00 5. " FIRQPR_MIBSPI3 ,FIQ/IRQ Program Control 37 - MIBSPI3 level 0 interrupt" "IRQ,FIQ" bitfld.long 0x00 4. " FIRQPR_DMM ,FIQ/IRQ Program Control 36 - DMM level 0 interrupt" "IRQ,FIQ" bitfld.long 0x00 3. " FIRQPR_DCAN2 ,FIQ/IRQ Program Control 35 - DCAN2 level 0 interrupt" "IRQ,FIQ" textline " " bitfld.long 0x00 2. " FIRQPR_DMA ,FIQ/IRQ Program Control 34 - LFSA interrupt" "IRQ,FIQ" bitfld.long 0x00 1. " FIRQPR_DMA ,FIQ/IRQ Program Control 33 - FTCA interrupt" "IRQ,FIQ" group.long 0x18++0x3 line.long 0x0 "FIRQPR2,Program Control 2 Register" bitfld.long 0x00 25. " FIRQPR_HWAG2 ,FIQ/IRQ Program Control 89 - HWA_INT_REQ_L" "IRQ,FIQ" bitfld.long 0x00 24. " FIRQPR_HWAG1 ,FIQ/IRQ Program Control 88 - HWA_INT_REQ_L" "IRQ,FIQ" bitfld.long 0x00 19. " FIRQPR_DCC2 ,FIQ/IRQ Program Control 83 - DCC2 done interrupt" "IRQ,FIQ" bitfld.long 0x00 18. " FIRQPR_DCC1 ,FIQ/IRQ Program Control 82 - DCC done interrupt" "IRQ,FIQ" textline " " bitfld.long 0x00 17. " FIRQPR_HWAG2 ,FIQ/IRQ Program Control 81 - HWA_INT_REQ_H" "IRQ,FIQ" bitfld.long 0x00 16. " FIRQPR_HWAG1 ,FIQ/IRQ Program Control 80 - HWA_INT_REQ_H" "IRQ,FIQ" textline " " sif (cpu()=="RM48L952-ZWT"||cpu()=="RM48L952-PGE"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L540-PGE") bitfld.long 0x00 15. " FIRQPR_ETHERNET ,FIQ/IRQ Program Control 79 - C0_RX_PULSE" "IRQ,FIQ" bitfld.long 0x00 14. " FIRQPR_ETHERNET ,FIQ/IRQ Program Control 78 - C0_THRESH_PULSE" "IRQ,FIQ" bitfld.long 0x00 13. " FIRQPR_ETHERNET ,FIQ/IRQ Program Control 77 - C0_TX_PULSE" "IRQ,FIQ" bitfld.long 0x00 12. " FIRQPR_ETHERNET ,FIQ/IRQ Program Control 76 - C0_MISC_PULSE" "IRQ,FIQ" textline " " endif bitfld.long 0x00 11. " FIRQPR_HET_TU2 ,FIQ/IRQ Program Control 75 - HET TU2 level 1 interrupt" "IRQ,FIQ" bitfld.long 0x00 10. " FIRQPR_SCI ,FIQ/IRQ Program Control 74 - C0_MISC_PULSE" "IRQ,FIQ" bitfld.long 0x00 9. " FIRQPR_N2HET2 ,FIQ/IRQ Program Control 73 - C0_TX_PULSE" "IRQ,FIQ" textline " " sif (cpu()=="RM48L952-ZWT"||cpu()=="RM48L952-PGE"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE") bitfld.long 0x00 8. " FIRQPR_USBDEV ,FIQ/IRQ Program Control 72 - USB_FUNC.USBRESETO" "IRQ,FIQ" bitfld.long 0x00 7. " FIRQPR_USBDEV ,FIQ/IRQ Program Control 71 - not (USB_FUNC.DSWAKEREQON)" "IRQ,FIQ" bitfld.long 0x00 6. " FIRQPR_USBDEV ,FIQ/IRQ Program Control 70 - USB_FUNC.IRQNONISOON" "IRQ,FIQ" bitfld.long 0x00 5. " FIRQPR_USBDEV ,FIQ/IRQ Program Control 69 - USB_FUNC.IRQGENION" "IRQ,FIQ" textline " " bitfld.long 0x00 4. " FIRQPR_USBDEV ,FIQ/IRQ Program Control 68 - USB_FUNC.IRQISOON" "IRQ,FIQ" bitfld.long 0x00 3. " FIRQPR_HOST ,FIQ/IRQ Program Control 67 - OHCI_INT" "IRQ,FIQ" textline " " endif bitfld.long 0x00 2. " FIRQPR_I2C ,FIQ/IRQ Program Control 66 - I2C level 0 interrupt" "IRQ,FIQ" bitfld.long 0x00 1. " FIRQPR_HET_TU2 ,FIQ/IRQ Program Control 65 - HET TU2 level 0 interrupt" "IRQ,FIQ" bitfld.long 0x00 0. " FIRQPR_SCI ,FIQ/IRQ Program Control 64 - SCI level 0 interrupt" "IRQ,FIQ" width 9. tree "VIM Pending Interrupt Read Location Registers" rgroup.long 0x20++0x3 line.long 0x0 "INTREQ0,Pending Interrupt Read Location 0" bitfld.long 0x00 31. " INTREQ_MIBADC1 ,MIBADC1 magnitude compare interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 30. " INTREQ_SPI2 ,SPI2 level 1 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 29. " INTREQ_DCAN1 ,DCAN1 level 1 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 28. " INTREQ_MIBADC ,MIBADC sw group 2 interrupt Pending" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " INTREQ_LIN ,LIN level 1 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 26. " INTREQ_MIBSPI ,MIBSPI level 1 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 25. " INTREQ_HET_TU ,HET TU level 1 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 24. " INTREQ_N2HET1 ,N2HET1 level 1 interrupt Pending" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " INTREQ_GIO ,GIO interrupt B Pending" "No interrupt,Interrupt" bitfld.long 0x00 22. " INTREQ_CPU ,PMU Interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 21. " INTREQ_SYSTEM ,Software interrupt (SSI) Pending" "No interrupt,Interrupt" bitfld.long 0x00 20. " INTREQ_ESM ,ESM Low level interrupt Pending" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " INTREQ_CRC ,CRC Interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 17. " INTREQ_SPI2 ,SPI2 level 0 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 16. " INTREQ_DCAN1 ,DCAN1 level 0 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 15. " INTREQ_MIBADC1 ,MIBADC1 sw group 1 interrupt Pending" "No interrupt,Interrupt" textline " " bitfld.long 0x00 14. " INTREQ_MIBADC1 ,MIBADC1 event group interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 13. " INTREQ_LIN ,LIN level 0 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 12. " INTREQ_MIBSPI1 ,MIBSPI1 level 0 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 11. " INTREQ_HET_TU1 ,HET TU1 level 0 interrupt Pending" "No interrupt,Interrupt" textline " " bitfld.long 0x00 10. " INTREQ_N2HET1 ,N2HET1 level 0 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 9. " INTREQ_GIO ,GIO interrupt A Pending" "No interrupt,Interrupt" bitfld.long 0x00 8. " INTREQ_RTI ,RTI timebase interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 7. " INTREQ_RTI ,RTI overflow interrupt 1 Pending" "No interrupt,Interrupt" textline " " bitfld.long 0x00 6. " INTREQ_RTI ,RTI overflow interrupt 0 Pending" "No interrupt,Interrupt" bitfld.long 0x00 5. " INTREQ_RTI ,RTI compare interrupt 3 Pending" "No interrupt,Interrupt" bitfld.long 0x00 4. " INTREQ_RTI ,RTI compare interrupt 2 Pending" "No interrupt,Interrupt" bitfld.long 0x00 3. " INTREQ_RTI ,RTI compare interrupt 1 Pending" "No interrupt,Interrupt" textline " " bitfld.long 0x00 2. " INTREQ_RTI ,RTI compare interrupt 0 Pending" "No interrupt,Interrupt" bitfld.long 0x00 0. " INTREQ_ESM ,ESM High level interrupt (NMI) Pending" "No interrupt,Interrupt" rgroup.long 0x24++0x3 line.long 0x0 "INTREQ1,Pending Interrupt Read Location 1" bitfld.long 0x00 31. " INTREQ_N2HET2 ,N2HET2 level 0 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 29. " INTREQ_FMC ,FSM_DONE interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 28. " INTREQ_DCAN3 ,DCAN3 IF3 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 27. " INTREQ_MIBADC2 ,MibADC2 magnitude compare interrupt Pending" "No interrupt,Interrupt" textline " " bitfld.long 0x00 25. " INTREQ_MIBADC2 ,MibADC2 sw group2 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 24. " INTREQ_MIBSPI5 ,MIBSPI5 level 1 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 23. " INTREQ_DCAN3 ,DCAN3 level 1 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 22. " INTREQ_SPI4 ,SPI4 level 1 interrupt Pending" "No interrupt,Interrupt" textline " " bitfld.long 0x00 21. " INTREQ_MIBSPI5 ,MIBSPI5 level 0 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 20. " INTREQ_52 ,Interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 19. " INTREQ_MIBADC2 ,MibADC2 sw group1 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 18. " INTREQ_MIBADC2 ,MibADC2 event group interrupt Pending" "No interrupt,Interrupt" textline " " bitfld.long 0x00 17. " INTREQ_SPI4 ,SPI4 level 0 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 15. " INTREQ_FPU ,FPU interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 14. " INTREQ_DCAN2 ,DCAN2 IF3 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 13. " INTREQ_DCAN3 ,DCAN3 level 0 interrupt Pending" "No interrupt,Interrupt" textline " " bitfld.long 0x00 12. " INTREQ_DCAN1 ,DCAN1 IF3 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 11. " INTREQ_DMM ,DMM level 1 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 10. " INTREQ_DCAN2 ,DCAN2 level 1 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 9. " INTREQ_EMIF ,AEMIFINT3 Pending" "No interrupt,Interrupt" textline " " bitfld.long 0x00 8. " INTREQ_DMA ,BTCA interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 7. " INTREQ_DMA ,HBCA interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 6. " INTREQ_MIBSPI3 ,MIBSPI3 level 1 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 5. " INTREQ_MIBSPI3 ,MIBSPI3 level 0 interrupt Pending" "No interrupt,Interrupt" textline " " bitfld.long 0x00 4. " INTREQ_DMM ,DMM level 0 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 3. " INTREQ_DCAN2 ,DCAN2 level 0 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 2. " INTREQ_DMA ,LFSA interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 1. " INTREQ_DMA ,FTCA interrupt Pending" "No interrupt,Interrupt" rgroup.long 0x28++0x3 line.long 0x0 "INTREQ2,Pending Interrupt Read Location 2" bitfld.long 0x00 25. " INTREQ_HWAG2 ,HWA_INT_REQ_L Pending" "No interrupt,Interrupt" bitfld.long 0x00 24. " INTREQ_HWAG1 ,HWA_INT_REQ_L Pending" "No interrupt,Interrupt" bitfld.long 0x00 19. " INTREQ_DCC2 ,DCC2 done interrupt Pending 83" "No interrupt,Interrupt" bitfld.long 0x00 18. " INTREQ_DCC1 ,DCC1 done interrupt Pending" "No interrupt,Interrupt" textline " " bitfld.long 0x00 17. " INTREQ_HWAG2 ,HWA_INT_REQ_H Pending" "No interrupt,Interrupt" bitfld.long 0x00 16. " INTREQ_HWAG1 ,HWA_INT_REQ_H Pending" "No interrupt,Interrupt" textline " " sif (cpu()=="RM48L952-ZWT"||cpu()=="RM48L952-PGE"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L540-PGE") bitfld.long 0x00 15. " INTREQ_ETHERNET ,C0_RX_PULSE Pending" "No interrupt,Interrupt" bitfld.long 0x00 14. " INTREQ_ETHERNET ,C0_THRESH_PULSE Pending" "No interrupt,Interrupt" bitfld.long 0x00 13. " INTREQ_ETHERNET ,C0_TX_PULSE Pending" "No interrupt,Interrupt" bitfld.long 0x00 12. " INTREQ_ETHERNET ,C0_MISC_PULSE Pending" "No interrupt,Interrupt" textline " " endif bitfld.long 0x00 11. " INTREQ_HET_TU2 ,HET TU2 level 1 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 10. " INTREQ_SCI ,SCI level 1 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 9. " INTREQ_N2HET2 ,N2HET2 level 1 interrupt Pending" "No interrupt,Interrupt" textline " " sif (cpu()=="RM48L952-ZWT"||cpu()=="RM48L952-PGE"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE") bitfld.long 0x00 8. " INTREQ_USBDEV ,USB_FUNC.USBRESETO Pending" "No interrupt,Interrupt" bitfld.long 0x00 7. " INTREQ_USBDEV ,not (USB_FUNC.DSWAKEREQON) Pending" "No interrupt,Interrupt" bitfld.long 0x00 6. " INTREQ_USBDEV ,USB_FUNC.IRQNONISOON Pending" "No interrupt,Interrupt" bitfld.long 0x00 5. " INTREQ_USBDEV ,USB_FUNC.IRQGENION Pending" "No interrupt,Interrupt" textline " " bitfld.long 0x00 4. " INTREQ_USBDEV ,USB_FUNC.IRQISOON Pending" "No interrupt,Interrupt" bitfld.long 0x00 3. " INTREQ_USBHOST ,OHCI_INT Pending" "No interrupt,Interrupt" textline " " endif bitfld.long 0x00 2. " INTREQ_I2C ,I2C level 0 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 1. " INTREQ_HET_TU2 ,HET TU2 level 0 interrupt Pending" "No interrupt,Interrupt" bitfld.long 0x00 0. " INTREQ_SCI ,SCI level 0 interrupt Pending" "No interrupt,Interrupt" tree.end width 13. tree "VIM Interrupt Mask Registers" group.long 0x30++0x3 line.long 0x0 "REQENASET0,Interrupt Enable Set/Clr Register 0" setclrfld.long 0x00 31. 0x00 31. 0x10 31. " REQENA_31_set/clr ,MIBADC1 magnitude compare Request enable set bit 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x10 30. " REQENA_30_set/clr ,SPI2 level 1 Request enable set bit 30" "Disabled,Enabled" textline " " setclrfld.long 0x00 29. 0x00 29. 0x10 29. " REQENA_29_set/clr ,DCAN1 level 1 Request enable set bit 29" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x10 28. " REQENA_28_set/clr ,MIBADC sw group 2 Request enable set bit 28" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. 0x00 27. 0x10 27. " REQENA_27_set/clr ,LIN level 1 Request enable set bit 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x10 26. " REQENA_26_set/clr ,MIBSPI level 1 Request enable set bit 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x10 25. " REQENA_25_set/clr ,HET TU level 1 Request enable set bit 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x10 24. " REQENA_24_set/clr ,N2HET1 level 1 Request enable set bit 24" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. 0x00 23. 0x10 23. " REQENA_23_set/clr ,GIO interrupt B Request enable set bit 23" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x10 22. " REQENA_22_set/clr ,PMU Request enable set bit 22" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. 0x00 21. 0x10 21. " REQENA_21_set/clr ,Software interrupt (SSI) Request enable set bit 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x10 20. " REQENA_20_set/clr ,ESM Low level Request enable set bit 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x10 19. " REQENA_19_set/clr ,CRC Request enable set bit 19" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x10 17. " REQENA_17_set/clr ,SPI2 level 0 Request enable set bit 17" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x10 16. " REQENA_16_set/clr ,DCAN1 level 0 Request enable set bit 16" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x10 15. " REQENA_15_set/clr ,MIBADC1 sw group 1 Request enable set bit 15" "Disabled,Enabled" textline " " setclrfld.long 0x00 14. 0x00 14. 0x10 14. " REQENA_14_set/clr ,MIBADC1 event group Request enable set bit 14" "Disabled,Enabled" setclrfld.long 0x00 13. 0x00 13. 0x10 13. " REQENA_13_set/clr ,LIN level 0 Request enable set bit 13" "Disabled,Enabled" textline " " setclrfld.long 0x00 12. 0x00 12. 0x10 12. " REQENA_12_set/clr ,MIBSPI1 level 0 Request enable set bit 12" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x10 11. " REQENA_11_set/clr ,HET TU1 level 0 Request enable set bit 11" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x10 10. " REQENA_10_set/clr ,N2HET1 level 0 Request enable set bit 10" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x10 9. " REQENA_9_set/clr ,GIO interrupt A Request enable set bit 9" "Disabled,Enabled" textline " " setclrfld.long 0x00 8. 0x00 8. 0x10 8. " REQENA_8_set/clr ,RTI timebase Request enable set bit 8" "Disabled,Enabled" setclrfld.long 0x00 7. 0x00 7. 0x10 7. " REQENA_7_set/clr ,RTI overflow 1 Request enable set bit 7" "Disabled,Enabled" textline " " setclrfld.long 0x00 6. 0x00 6. 0x10 6. " REQENA_6_set/clr ,RTI overflow 0 Request enable set bit 6" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x10 5. " REQENA_5_set/clr ,RTI compare 3 Request enable set bit 5" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x10 4. " REQENA_4_set/clr ,RTI compare 2 Request enable set bit 4" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x10 3. " REQENA_3_set/clr ,RTI compare 1 Request enable set bit 3" "Disabled,Enabled" textline " " setclrfld.long 0x00 2. 0x00 2. 0x10 2. " REQENA_2_set/clr ,RTI compare 0 Request enable set bit 2" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x10 0. " REQENA_0_set/clr ,ESM High level (NMI) Request enable set bit 2" "Disabled,Enabled" group.long 0x34++0x3 line.long 0x0 "REQENASET1,Interrupt Enable Set/Clr Register 1" setclrfld.long 0x00 31. 0x00 31. 0x10 31. " REQENA_63_set/clr ,N2HET2 level 0 Request enable set bit 63" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x10 29. " REQENA_61_set/clr ,FSM_DONE Request enable set bit 61" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x10 28. " REQENA_60_set/clr ,DCAN3 IF3 Request enable set bit 60" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x10 27. " REQENA_59_set/clr ,MibADC2 magnitude compare Request enable set bit 59" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x10 25. " REQENA_57_set/clr ,MibADC2 sw group2 Request enable set bit 57" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x10 24. " REQENA_56_set/clr ,MIBSPI5 level 1 Request enable set bit 56" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. 0x00 23. 0x10 23. " REQENA_55_set/clr ,DCAN3 level 1 Request enable set bit 55" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x10 22. " REQENA_54_set/clr ,SPI4 level 1 Request enable set bit 54" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. 0x00 21. 0x10 21. " REQENA_53_set/clr ,MIBSPI5 level 0 Request enable set bit 53" "Disabled,Enabled" setclrfld.long 0x00 19. 0x00 19. 0x10 19. " REQENA_51_set/clr ,MibADC2 sw group1 Request enable set bit 51" "Disabled,Enabled" textline " " setclrfld.long 0x00 18. 0x00 18. 0x10 18. " REQENA_50_set/clr ,MibADC2 event group Request enable set bit 50" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x10 17. " REQENA_49_set/clr ,SPI4 level 0 Request enable set bit 49" "Disabled,Enabled" textline " " setclrfld.long 0x00 15. 0x00 15. 0x10 15. " REQENA_47_set/clr ,FPU Request enable set bit 47" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x10 14. " REQENA_46_set/clr ,DCAN2 IF3 Request enable set bit 46" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x10 13. " REQENA_45_set/clr ,DCAN3 level 0 Request enable set bit 45" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x10 12. " REQENA_44_set/clr ,DCAN1 IF3 Request enable set bit 44" "Disabled,Enabled" textline " " setclrfld.long 0x00 11. 0x00 11. 0x10 11. " REQENA_43_set/clr ,DMM level 1 Request enable set bit 43" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x10 10. " REQENA_42_set/clr ,DCAN2 level 1 Request enable set bit 42" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. 0x00 9. 0x10 9. " REQENA_41_set/clr ,AEMIFINT3 Request enable set bit 41" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x10 8. " REQENA_40_set/clr ,BTCA Request enable set bit 40" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x10 7. " REQENA_39_set/clr ,HBCA Request enable set bit 39" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x10 6. " REQENA_38_set/clr ,MIBSPI3 level 1 Request enable set bit 38" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x00 5. 0x10 5. " REQENA_37_set/clr ,MIBSPI3 level 0 Request enable set bit 37" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x10 4. " REQENA_36_set/clr ,DMM level 0 Request enable set bit 36" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. 0x00 3. 0x10 3. " REQENA_35_set/clr ,DCAN2 level 0 Request enable set bit 35" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x10 2. " REQENA_34_set/clr ,LFSA Request enable set bit 34" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x10 1. " REQENA_33_set/clr ,FTCA Request enable set bit 33" "Disabled,Enabled" group.long 0x38++0x3 line.long 0x0 "REQENASET2,Interrupt Enable Set/Clr Register 2" setclrfld.long 0x00 25. 0x00 25. 0x10 25. " REQENA_89_set/clr ,HWA_INT_REQ_L Request enable set bit 89" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x10 24. " REQENA_88_set/clr ,HWA_INT_REQ_L Request enable set bit 88" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x10 19. " REQENA_83_set/clr , DCC2 done Request enable set bit 83" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x10 18. " REQENA_82_set/clr ,DCC done Request enable set bit 82" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. 0x00 17. 0x10 17. " REQENA_81_set/clr ,HWA_INT_REQ_H Request enable set bit 81" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x10 16. " REQENA_80_set/clr ,HWA_INT_REQ_H Request enable set bit 80" "Disabled,Enabled" textline " " sif (cpu()=="RM48L952-ZWT"||cpu()=="RM48L952-PGE"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L540-PGE") setclrfld.long 0x00 15. 0x00 15. 0x10 15. " REQENA_79_set/clr ,C0_RX_PULSE Request enable set bit 89" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x10 14. " REQENA_78_set/clr ,C0_THRESH_PULSE Request enable set bit 88" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x10 13. " REQENA_77_set/clr ,C0_TX_PULSE Request enable set bit 83" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x10 12. " REQENA_76_set/clr ,C0_MISC_PULSE Request enable set bit 82" "Disabled,Enabled" textline " " endif setclrfld.long 0x00 11. 0x00 11. 0x10 11. " REQENA_75_set/clr ,HET TU2 level 1 Request enable set bit 75" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x10 10. " REQENA_74_set/clr ,SCI level 1 Request enable set bit 74" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. 0x00 9. 0x10 9. " REQENA_73_set/clr ,N2HET2 level 1 Request enable set bit 73" "Disabled,Enabled" textline " " sif (cpu()=="RM48L952-ZWT"||cpu()=="RM48L952-PGE"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE") setclrfld.long 0x00 8. 0x00 8. 0x10 8. " REQENA_72_set/clr ,USB_FUNC.USBRESETO Request enable set bit 89" "Disabled,Enabled" setclrfld.long 0x00 7. 0x00 7. 0x10 7. " REQENA_71_set/clr ,not (USB_FUNC.DSWAKEREQON) Request enable set bit 88" "Disabled,Enabled" textline " " setclrfld.long 0x00 6. 0x00 6. 0x10 6. " REQENA_70_set/clr ,USB_FUNC.IRQNONISOON Request enable set bit 83" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x10 5. " REQENA_69_set/clr ,USB_FUNC.IRQGENION Request enable set bit 82" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x10 4. " REQENA_68_set/clr ,USB_FUNC.IRQISOON Request enable set bit 83" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x10 3. " REQENA_67_set/clr ,OHCI_INT Request enable set bit 82" "Disabled,Enabled" textline " " endif setclrfld.long 0x00 2. 0x00 2. 0x10 2. " REQENA_66_set/clr ,I2C level 0 Request enable set bit 66" "Disabled,Enabled" setclrfld.long 0x00 1. 0x00 1. 0x10 1. " REQENA_65_set/clr ,HET TU2 level 0 Request enable set bit 65" "Disabled,Enabled" textline " " setclrfld.long 0x00 0. 0x00 0. 0x10 0. " REQENA_64_set/clr ,SCI level 0 Request enable set bit 64" "Disabled,Enabled" tree.end width 14. tree "VIM Wake Up Mask Registers" group.long 0x50++0x3 line.long 0x0 "WAKEENASET0,Wake-up Enable Set Register 0" setclrfld.long 0x00 31. 0x00 31. 0x10 31. " WAKEENA_31_set/clr ,MIBADC1 magnitude compare interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x10 30. " WAKEENA_30_set/clr ,SPI2 level 1 interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 29. 0x00 29. 0x10 29. " WAKEENA_29_set/clr ,DCAN1 level 1 interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x10 28. " WAKEENA_28_set/clr ,MIBADC sw group 2 interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. 0x00 27. 0x10 27. " WAKEENA_27_set/clr ,LIN level 1 interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x10 26. " WAKEENA_26_set/clr ,MIBSPI level 1 interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x10 25. " WAKEENA_25_set/clr ,HET TU level 1 interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x10 24. " WAKEENA_24_set/clr ,N2HET1 level 1 interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. 0x00 23. 0x10 23. " WAKEENA_23_set/clr ,GIO interrupt B Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x10 22. " WAKEENA_22_set/clr ,PMU Interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. 0x00 21. 0x10 21. " WAKEENA_21_set/clr ,Software interrupt (SSI) Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x10 20. " WAKEENA_20_set/clr ,ESM Low level interrupt Wake-up" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x10 19. " WAKEENA_19_set/clr ,CRC Interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x10 17. " WAKEENA_17_set/clr ,SPI2 level 0 interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x10 16. " WAKEENA_16_set/clr ,DCAN1 level 0 interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x10 15. " WAKEENA_15_set/clr ,MIBADC1 sw group 1 interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 14. 0x00 14. 0x10 14. " WAKEENA_14_set/clr ,MIBADC1 event group interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 13. 0x00 13. 0x10 13. " WAKEENA_13_set/clr ,LIN level 0 interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 12. 0x00 12. 0x10 12. " WAKEENA_12_set/clr ,MIBSPI1 level 0 interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x10 11. " WAKEENA_11_set/clr ,HET TU1 level 0 interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x10 10. " WAKEENA_10_set/clr ,N2HET1 level 0 interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x10 9. " WAKEENA_9_set/clr ,GIO interrupt A Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 8. 0x00 8. 0x10 8. " WAKEENA_8_set/clr ,RTI timebase interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 7. 0x00 7. 0x10 7. " WAKEENA_7_set/clr ,RTI overflow interrupt 1 Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 6. 0x00 6. 0x10 6. " WAKEENA_6_set/clr ,RTI overflow interrupt 0 Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x10 5. " WAKEENA_5_set/clr ,RTI compare interrupt 3 Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x10 4. " WAKEENA_4_set/clr ,RTI compare interrupt 2 Wake-up" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x10 3. " WAKEENA_3_set/clr ,RTI compare interrupt 1 Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 2. 0x00 2. 0x10 2. " WAKEENA_2_set/clr ,RTI compare interrupt 0 Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x10 0. " WAKEENA_0_set/clr ,ESM High level interrupt (NMI) Wake-up enable" "Disabled,Enabled" group.long 0x54++0x3 line.long 0x0 "WAKEENASET1,Wake-up Enable Set Register 1" setclrfld.long 0x00 31. 0x00 31. 0x10 31. " WAKEENA_63_set/clr ,N2HET2 level 0 interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x10 29. " WAKEENA_61_set/clr ,FSM_DONE interrupt Wake-up enable set" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x10 28. " WAKEENA_60_set/clr ,DCAN3 IF3 interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x10 27. " WAKEENA_59_set/clr ,MibADC2 magnitude compare interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x10 25. " WAKEENA_57_set/clr ,MibADC2 sw group2 interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x10 24. " WAKEENA_56_set/clr ,MIBSPI5 level 1 interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. 0x00 23. 0x10 23. " WAKEENA_55_set/clr ,DCAN3 level 1 interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x10 22. " WAKEENA_54_set/clr ,SPI4 level 1 interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. 0x00 21. 0x10 21. " WAKEENA_53_set/clr ,MIBSPI5 level 0 interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 19. 0x00 19. 0x10 19. " WAKEENA_51_set/clr ,MibADC2 sw group1 interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 18. 0x00 18. 0x10 18. " WAKEENA_50_set/clr ,MibADC2 event group interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x10 17. " WAKEENA_49_set/clr ,SPI4 level 0 interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 15. 0x00 15. 0x10 15. " WAKEENA_47_set/clr ,FPU interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x10 14. " WAKEENA_46_set/clr ,DCAN2 IF3 interrupt Wake-up enable set bit 46" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x10 13. " WAKEENA_45_set/clr ,DCAN3 level 0 interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x10 12. " WAKEENA_44_set/clr ,DCAN1 IF3 interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 11. 0x00 11. 0x10 11. " WAKEENA_43_set/clr ,DMM level 1 interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x10 10. " WAKEENA_42_set/clr ,DCAN2 level 1 interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. 0x00 9. 0x10 9. " WAKEENA_41_set/clr ,AEMIFINT3 Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x10 8. " WAKEENA_40_set/clr ,BTCA interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x10 7. " WAKEENA_39_set/clr ,HBCA interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x10 6. " WAKEENA_38_set/clr ,MIBSPI3 level 1 interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x00 5. 0x10 5. " WAKEENA_37_set/clr ,MIBSPI3 level 0 interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x10 4. " WAKEENA_36_set/clr ,DMM level 0 interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. 0x00 3. 0x10 3. " WAKEENA_35_set/clr ,DCAN2 level 0 interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x10 2. " WAKEENA_34_set/clr ,LFSA interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x10 1. " WAKEENA_33_set/clr ,FTCA interrupt Wake-up enable" "Disabled,Enabled" group.long 0x58++0x3 line.long 0x0 "WAKEENASET2,Wake-up Enable Set Register 2" setclrfld.long 0x00 25. 0x00 25. 0x10 25. " WAKEENA_89_set/clr ,HWA_INT_REQ_L Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x10 24. " WAKEENA_88_set/clr ,HWA_INT_REQ_L Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x10 19. " WAKEENA_83_set/clr ,Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x10 18. " WAKEENA_82_set/clr ,DCC done interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. 0x00 17. 0x10 17. " WAKEENA_81_set/clr ,HWA_INT_REQ_H Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x10 16. " WAKEENA_80_set/clr ,HWA_INT_REQ_H Wake-up enable" "Disabled,Enabled" textline " " sif (cpu()=="RM48L952-ZWT"||cpu()=="RM48L952-PGE"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L540-PGE") setclrfld.long 0x00 15. 0x00 15. 0x10 15. " WAKEENA_79_set/clr ,C0_RX_PULSE Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x10 14. " WAKEENA_78_set/clr ,C0_THRESH_PULSE interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x10 13. " WAKEENA_77_set/clr ,C0_TX_PULSE Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x10 12. " WAKEENA_76_set/clr ,C0_MISC_PULSE Wake-up enable" "Disabled,Enabled" textline " " endif setclrfld.long 0x00 11. 0x00 11. 0x10 11. " WAKEENA_75_set/clr ,HET TU2 level 1 interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x10 10. " WAKEENA_74_set/clr ,SCI level 1 interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. 0x00 9. 0x10 9. " WAKEENA_73_set/clr ,N2HET2 level 1 interrupt Wake-up enable" "Disabled,Enabled" textline " " sif (cpu()=="RM48L952-ZWT"||cpu()=="RM48L952-PGE"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE") setclrfld.long 0x00 8. 0x00 8. 0x10 8. " WAKEENA_72_set/clr ,USB_FUNC.USBRESETO interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 7. 0x00 7. 0x10 7. " WAKEENA_71_set/clr ,not (USB_FUNC.DSWAKEREQON) interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 6. 0x00 6. 0x10 6. " WAKEENA_70_set/clr ,USB_FUNC.IRQNONISOON interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x10 5. " WAKEENA_69_set/clr ,USB_FUNC.IRQGENION interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x10 4. " WAKEENA_68_set/clr ,USB_FUNC.IRQISOON interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x10 3. " WAKEENA_67_set/clr ,OHCI_INT interrupt Wake-up enable" "Disabled,Enabled" textline " " endif setclrfld.long 0x00 2. 0x00 2. 0x10 2. " WAKEENA_66_set/clr ,I2C level 0 interrupt Wake-up enable" "Disabled,Enabled" setclrfld.long 0x00 1. 0x00 1. 0x10 1. " WAKEENA_65_set/clr ,HET TU2 level 0 interrupt Wake-up enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 0. 0x00 0. 0x10 0. " WAKEENA_64_set/clr ,SCI level 0 interrupt Wake-up enable" "Disabled,Enabled" tree.end width 11. tree "VIM Interrupt Vector Registers" rgroup.long 0x70++0x3 line.long 0x0 "IRQVECREG,IRQ Interrupt Vector Register" rgroup.long 0x74++0x3 line.long 0x0 "FIQVECREG,FIQ Interrupt Vector Register" tree.end width 11. group.long 0x78++0x3 line.long 0x0 "CAPEVTSRC,Capture Event register" hexmask.long.byte 0x00 16.--22. 1. " CAPEVTSRC1[6:0] ,Capture Event Source 1 Mapping Control" hexmask.long.byte 0x00 0.--6. 1. " CAPEVTSRC0[6:0] ,Capture Event Source 0 Mapping Control" width 12. tree "VIM Interrupt Control Registers" group.long 0x80++0x3 line.long 0x0 "CHANCTRL0,VIM Interrupt Control Register 0" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP0[6:0] ,ESM High level interrupt (NMI) CHAN0 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP2[6:0] ,RTI compare interrupt 0 CHAN2 Mapping Control" hexmask.long.byte 0x00 0.--6. 1. " CHANMAP3[6:0] ,RTI compare interrupt 1 CHAN3 Mapping Control" group.long 0x84++0x3 line.long 0x0 "CHANCTRL1,VIM Interrupt Control Register 1" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP4[6:0] ,RTI compare interrupt 2 CHAN4 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP5[6:0] ,RTI compare interrupt 3 CHAN5 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP6[6:0] ,RTI overflow interrupt 0 CHAN6 Mapping Control" textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP7[6:0] ,RTI overflow interrupt 1 CHAN7 Mapping Control" group.long 0x88++0x3 line.long 0x0 "CHANCTRL2,VIM Interrupt Control Register 2" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP8[6:0] ,RTI timebase interrupt CHAN8 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP9[6:0] ,GIO interrupt A CHAN9 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP10[6:0] ,N2HET1 level 0 interrupt CHAN10 Mapping Control" textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP11[6:0] ,HET TU1 level 0 interrupt CHAN11 Mapping Control" group.long 0x8C++0x3 line.long 0x0 "CHANCTRL3,VIM Interrupt Control Register 3" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP12[6:0] ,MIBSPI1 level 0 interrupt CHAN12 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP13[6:0] ,LIN level 0 interrupt CHAN13 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP14[6:0] ,MIBADC1 event group interrupt CHAN14 Mapping Control" textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP15[6:0] ,MIBADC1 sw group 1 interrupt CHAN15 Mapping Control" group.long 0x90++0x3 line.long 0x0 "CHANCTRL4,VIM Interrupt Control Register 4" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP16[6:0] ,DCAN1 level 0 interrupt CHAN16 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP17[6:0] ,SPI2 level 0 interrupt CHAN17 Mapping Control" hexmask.long.byte 0x00 0.--6. 1. " CHANMAP19[6:0] ,CRC Interrupt CHAN19 Mapping Control" group.long 0x94++0x3 line.long 0x0 "CHANCTRL5,VIM Interrupt Control Register 5" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP20[6:0] ,ESM Low level interrupt CHAN20 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP21[6:0] ,Software interrupt (SSI) CHAN21 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP22[6:0] ,PMU Interrupt CHAN22 Mapping Control" textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP23[6:0] ,GIO interrupt B CHAN23 Mapping Control" group.long 0x98++0x3 line.long 0x0 "CHANCTRL6,VIM Interrupt Control Register 6" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP24[6:0] ,N2HET1 level 1 interrupt CHAN24 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP25[6:0] ,HET TU level 1 interrupt CHAN25 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP26[6:0] ,MIBSPI level 1 interrupt CHAN26 Mapping Control" textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP27[6:0] ,LIN level 1 interrupt CHAN27 Mapping Control" group.long 0x9C++0x3 line.long 0x0 "CHANCTRL7,VIM Interrupt Control Register 7" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP28[6:0] ,MIBADC sw group 2 interrupt CHAN28 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP29[6:0] ,DCAN1 level 1 interrupt CHAN29 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP30[6:0] ,SPI2 level 1 interrupt CHAN30 Mapping Control" textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP31[6:0] ,MIBADC1 magnitude compare interrupt CHAN31 Mapping Control" group.long 0xA0++0x3 line.long 0x0 "CHANCTRL8,VIM Interrupt Control Register 8" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP33[6:0] ,FTCA interrupt CHAN33 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP34[6:0] ,LFSA interrupt CHAN34 Mapping Control" textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP35[6:0] ,DCAN2 level 0 interrupt CHAN35 Mapping Control" group.long 0xA4++0x3 line.long 0x0 "CHANCTRL9,VIM Interrupt Control Register 9" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP36[6:0] ,DMM level 0 interrupt CHAN36 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP37[6:0] ,MIBSPI3 level 0 interrupt CHAN37 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP38[6:0] ,MIBSPI3 level 1 interrupt CHAN38 Mapping Control" textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP39[6:0] ,HBCA interrupt CHAN39 Mapping Control" group.long 0xA8++0x3 line.long 0x0 "CHANCTRL10,VIM Interrupt Control Register 10" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP40[6:0] ,BTCA interrupt CHAN40 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP41[6:0] ,AEMIFINT3 interrupt CHAN41 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP42[6:0] ,DCAN2 level 1 interrupt CHAN42 Mapping Control" textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP43[6:0] ,DMM level 1 interrupt CHAN43 Mapping Control" group.long 0xAC++0x3 line.long 0x0 "CHANCTRL11,VIM Interrupt Control Register 11" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP44[6:0] ,DCAN1 IF3 interrupt CHAN44 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP45[6:0] ,DCAN3 level 0 interrupt CHAN45 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP46[6:0] ,DCAN2 IF3 interrupt CHAN46 Mapping Control" textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP47[6:0] ,FPU interrupt CHAN47 Mapping Control" group.long 0xB0++0x3 line.long 0x0 "CHANCTRL12,VIM Interrupt Control Register 12" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP49[6:0] ,SPI4 level 0 interrupt CHAN49 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP50[6:0] ,MibADC2 event group interrupt CHAN50 Mapping Control" textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP51[6:0] ,MibADC2 sw group1 interrupt CHAN51 Mapping Control" group.long 0xB4++0x3 line.long 0x0 "CHANCTRL13,VIM Interrupt Control Register 13" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP53[6:0] ,MIBSPI5 level 0 interrupt CHAN53 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP54[6:0] ,SPI4 level 1 interrupt CHAN54 Mapping Control" textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP55[6:0] ,DCAN3 level 1 interrupt CHAN55 Mapping Control" group.long 0xB8++0x3 line.long 0x0 "CHANCTRL14,VIM Interrupt Control Register 14" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP56[6:0] ,MIBSPI5 level 1 interrupt CHAN56 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP57[6:0] ,MibADC2 sw group2 interrupt CHAN57 Mapping Control" hexmask.long.byte 0x00 0.--6. 1. " CHANMAP59[6:0] ,MibADC2 magnitude compare interrupt CHAN59 Mapping Control" group.long 0xBC++0x3 line.long 0x0 "CHANCTRL15,VIM Interrupt Control Register 15" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP60[6:0] ,DCAN3 IF3 interrupt CHAN60 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP61[6:0] ,FSM_DONE interrupt CHAN61 Mapping Control" hexmask.long.byte 0x00 0.--6. 1. " CHANMAP63[6:0] ,N2HET2 level 0 interrupt CHAN63 Mapping Control" group.long 0xC0++0x3 line.long 0x0 "CHANCTRL16,VIM Interrupt Control Register 16" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP64[6:0] ,SCI level 0 interrupt CHAN64 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP65[6:0] ,HET TU2 level 0 interrupt CHAN65 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP66[6:0] ,I2C level 0 interrupt CHAN66 Mapping Control" sif (cpu()=="RM48L952-ZWT"||cpu()=="RM48L952-PGE"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE") textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP67[6:0] ,OHCI_INT interrupt CHAN67 Mapping Control" endif group.long 0xC4++0x3 line.long 0x0 "CHANCTRL17,Channel Mapping Register" sif (cpu()=="RM48L952-ZWT"||cpu()=="RM48L952-PGE"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE") hexmask.long.byte 0x00 24.--30. 1. " CHANMAP68[6:0] ,USB_FUNC.IRQISOON CHAN68 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP69[6:0] ,USB_FUNC.IRQGENION interrupt CHAN69 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP70[6:0] ,USB_FUNC.IRQNONISOON interrupt CHAN70 Mapping Control" textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP71[6:0] ,not (USB_FUNC.DSWAKEREQON) interrupt CHAN71 Mapping Control" endif group.long 0xC8++0x3 line.long 0x0 "CHANCTRL18,VIM Interrupt Control Register 18" sif (cpu()=="RM48L952-ZWT"||cpu()=="RM48L952-PGE"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE") hexmask.long.byte 0x00 24.--30. 1. " CHANMAP72[6:0] ,USB_FUNC.USBRESETO interrupt CHAN72 Mapping Control" textline " " endif hexmask.long.byte 0x00 16.--22. 1. " CHANMAP73[6:0] ,N2HET2 level 1 interrupt CHAN73 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP74[6:0] ,SCI level 1 interrupt CHAN74 Mapping Control" hexmask.long.byte 0x00 0.--6. 1. " CHANMAP75[6:0] ,HET TU2 level 1 interrupt CHAN75 Mapping Control" group.long 0xCC++0x3 line.long 0x0 "CHANCTRL19,VIM Interrupt Control Register 19" sif (cpu()=="RM48L952-ZWT"||cpu()=="RM48L952-PGE"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L540-PGE") hexmask.long.byte 0x00 24.--30. 1. " CHANMAP76[6:0] ,C0_MISC_PULSE interrupt CHAN76 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP77[6:0] ,C0_TX_PULSE interrupt CHAN77 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP78[6:0] ,C0_THRESH_PULSE interrupt CHAN78 Mapping Control" textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP79[6:0] ,C0_RX_PULSE interrupt CHAN79 Mapping Control" endif group.long 0xD0++0x3 line.long 0x0 "CHANCTRL20,VIM Interrupt Control Register 20" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP80[6:0] ,HWA_INT_REQ_H Interrupt CHAN80 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP81[6:0] ,HWA_INT_REQ_H Interrupt CHAN81 Mapping Control" hexmask.long.byte 0x00 8.--14. 1. " CHANMAP82[6:0] ,DCC done interrupt CHAN82 Mapping Control" textline " " hexmask.long.byte 0x00 0.--6. 1. " CHANMAP83[6:0] ,DCC2 done interrupt CHAN83 Mapping Control" group.long 0xD4++0x3 line.long 0x0 "CHANCTRL21,Channel Mapping Register" group.long 0xD8++0x3 line.long 0x0 "CHANCTRL22,VIM Interrupt Control Register 22" hexmask.long.byte 0x00 24.--30. 1. " CHANMAP88[6:0] ,HWA_INT_REQ_L Interrupt CHAN88 Mapping Control" hexmask.long.byte 0x00 16.--22. 1. " CHANMAP89[6:0] ,HWA_INT_REQ_L Interrupt CHAN89 Mapping Control" group.long 0xDC++0x3 line.long 0x0 "CHANCTRL23,Channel Mapping Register" tree.end width 0xb tree.end endif tree.end sif (cpu()!="RM42L432") tree "DMA (Direct Memory Access)" base ad:0xFFFFF000 width 9. group.long 0x00++0x3 line.long 0x0 "GCTRL,GLOBAL CONTROL Register" bitfld.long 0x00 16. " DMA_EN ,DMA Enable" "Disabled,Enabled" bitfld.long 0x00 14. " BUS_BUSY ,DMA External AHB Bus Status" "Not busy,Busy" bitfld.long 0x00 8.--9. " DEBUG_MODE[1:0] ,Debug Mode" "Suspend ignored,Block finished,Frame finished,Immediate stop" textline " " bitfld.long 0x00 0. " DMA_RES ,DMA Software Reset" "No reset,Reset" width 9. rgroup.long 0x04++0x3 line.long 0x0 "PEND,CHANNEL PENDING Register" bitfld.long 0x00 15. " PEND15 ,Channel Pending 15 Register" "Inactive,Pending" bitfld.long 0x00 14. " PEND14 ,Channel Pending 14 Register" "Inactive,Pending" bitfld.long 0x00 13. " PEND13 ,Channel Pending 13 Register" "Inactive,Pending" bitfld.long 0x00 12. " PEND12 ,Channel Pending 12 Register" "Inactive,Pending" textline " " bitfld.long 0x00 11. " PEND11 ,Channel Pending 11 Register" "Inactive,Pending" bitfld.long 0x00 10. " PEND10 ,Channel Pending 10 Register" "Inactive,Pending" bitfld.long 0x00 9. " PEND9 ,Channel Pending 9 Register" "Inactive,Pending" bitfld.long 0x00 8. " PEND8 ,Channel Pending 8 Register" "Inactive,Pending" textline " " bitfld.long 0x00 7. " PEND7 ,Channel Pending 7 Register" "Inactive,Pending" bitfld.long 0x00 6. " PEND6 ,Channel Pending 6 Register" "Inactive,Pending" bitfld.long 0x00 5. " PEND5 ,Channel Pending 5 Register" "Inactive,Pending" bitfld.long 0x00 4. " PEND4 ,Channel Pending 4 Register" "Inactive,Pending" textline " " bitfld.long 0x00 3. " PEND3 ,Channel Pending 3 Register" "Inactive,Pending" bitfld.long 0x00 2. " PEND2 ,Channel Pending 2 Register" "Inactive,Pending" bitfld.long 0x00 1. " PEND1 ,Channel Pending 1 Register" "Inactive,Pending" bitfld.long 0x00 0. " PEND0 ,Channel Pending 0 Register" "Inactive,Pending" width 9. rgroup.long 0x0C++0x3 line.long 0x0 "DMASTAT,DMA STATUS Register" bitfld.long 0x00 15. " STCH15 ,Status of DMA Channel 15" "Inactive,Active" bitfld.long 0x00 14. " STCH14 ,Status of DMA Channel 14" "Inactive,Active" bitfld.long 0x00 13. " STCH13 ,Status of DMA Channel 13" "Inactive,Active" bitfld.long 0x00 12. " STCH12 ,Status of DMA Channel 12" "Inactive,Active" textline " " bitfld.long 0x00 11. " STCH11 ,Status of DMA Channel 11" "Inactive,Active" bitfld.long 0x00 10. " STCH10 ,Status of DMA Channel 10" "Inactive,Active" bitfld.long 0x00 9. " STCH9 ,Status of DMA Channel 9" "Inactive,Active" bitfld.long 0x00 8. " STCH8 ,Status of DMA Channel 8" "Inactive,Active" textline " " bitfld.long 0x00 7. " STCH7 ,Status of DMA Channel 7" "Inactive,Active" bitfld.long 0x00 6. " STCH6 ,Status of DMA Channel 6" "Inactive,Active" bitfld.long 0x00 5. " STCH5 ,Status of DMA Channel 5" "Inactive,Active" bitfld.long 0x00 4. " STCH4 ,Status of DMA Channel 4" "Inactive,Active" textline " " bitfld.long 0x00 3. " STCH3 ,Status of DMA Channel 3" "Inactive,Active" bitfld.long 0x00 2. " STCH2 ,Status of DMA Channel 2" "Inactive,Active" bitfld.long 0x00 1. " STCH1 ,Status of DMA Channel 1" "Inactive,Active" bitfld.long 0x00 0. " STCH0 ,Status of DMA Channel 0" "Inactive,Active" tree "Channel Enable Status Registers" width 10. group.long 0x14++0x3 line.long 0x0 "HWCHENAS,HWCHANNEL ENABLE SET and STATUS Register" bitfld.long 0x00 15. " HWCHENA15 ,HW Channel 15 Enable Status" "Disabled,Enabled" bitfld.long 0x00 14. " HWCHENA14 ,HW Channel 14 Enable Status" "Disabled,Enabled" bitfld.long 0x00 13. " HWCHENA13 ,HW Channel 13 Enable Status" "Disabled,Enabled" bitfld.long 0x00 12. " HWCHENA12 ,HW Channel 12 Enable Status" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " HWCHENA11 ,HW Channel 11 Enable Status" "Disabled,Enabled" bitfld.long 0x00 10. " HWCHENA10 ,HW Channel 10 Enable Status" "Disabled,Enabled" bitfld.long 0x00 9. " HWCHENA9 ,HW Channel 9 Enable Status" "Disabled,Enabled" bitfld.long 0x00 8. " HWCHENA8 ,HW Channel 8 Enable Status" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " HWCHENA7 ,HW Channel 7 Enable Status" "Disabled,Enabled" bitfld.long 0x00 6. " HWCHENA6 ,HW Channel 6 Enable Status" "Disabled,Enabled" bitfld.long 0x00 5. " HWCHENA5 ,HW Channel 5 Enable Status" "Disabled,Enabled" bitfld.long 0x00 4. " HWCHENA4 ,HW Channel 4 Enable Status" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " HWCHENA3 ,HW Channel 3 Enable Status" "Disabled,Enabled" bitfld.long 0x00 2. " HWCHENA2 ,HW Channel 2 Enable Status" "Disabled,Enabled" bitfld.long 0x00 1. " HWCHENA1 ,HW Channel 1 Enable Status" "Disabled,Enabled" bitfld.long 0x00 0. " HWCHENA0 ,HW Channel 0 Enable Status" "Disabled,Enabled" width 10. group.long 0x1C++0x3 line.long 0x0 "HWCHENAR,HWCHANNEL ENABLE RESET and STATUS Register" bitfld.long 0x00 15. " HWCHDIS15 ,HW Channel 15 Disable" "No effect,Reset" bitfld.long 0x00 14. " HWCHDIS14 ,HW Channel 14 Disable" "No effect,Reset" bitfld.long 0x00 13. " HWCHDIS13 ,HW Channel 13 Disable" "No effect,Reset" bitfld.long 0x00 12. " HWCHDIS12 ,HW Channel 12 Disable" "No effect,Reset" textline " " bitfld.long 0x00 11. " HWCHDIS11 ,HW Channel 11 Disable" "No effect,Reset" bitfld.long 0x00 10. " HWCHDIS10 ,HW Channel 10 Disable" "No effect,Reset" bitfld.long 0x00 9. " HWCHDIS9 ,HW Channel 9 Disable" "No effect,Reset" bitfld.long 0x00 8. " HWCHDIS8 ,HW Channel 8 Disable" "No effect,Reset" textline " " bitfld.long 0x00 7. " HWCHDIS7 ,HW Channel 7 Disable" "No effect,Reset" bitfld.long 0x00 6. " HWCHDIS6 ,HW Channel 6 Disable" "No effect,Reset" bitfld.long 0x00 5. " HWCHDIS5 ,HW Channel 5 Disable" "No effect,Reset" bitfld.long 0x00 4. " HWCHDIS4 ,HW Channel 4 Disable" "No effect,Reset" textline " " bitfld.long 0x00 3. " HWCHDIS3 ,HW Channel 3 Disable" "No effect,Reset" bitfld.long 0x00 2. " HWCHDIS2 ,HW Channel 2 Disable" "No effect,Reset" bitfld.long 0x00 1. " HWCHDIS1 ,HW Channel 1 Disable" "No effect,Reset" bitfld.long 0x00 0. " HWCHDIS0 ,HW Channel 0 Disable" "No effect,Reset" width 10. group.long 0x24++0x3 line.long 0x0 "SWCHENAS,SWCHANNEL ENABLE SET and STATUS Register" bitfld.long 0x00 15. " SWCHENA15 ,SW Channel 15 Enable Status" "Not triggered,Triggered" bitfld.long 0x00 14. " SWCHENA14 ,SW Channel 14 Enable Status" "Not triggered,Triggered" bitfld.long 0x00 13. " SWCHENA13 ,SW Channel 13 Enable Status" "Not triggered,Triggered" bitfld.long 0x00 12. " SWCHENA12 ,SW Channel 12 Enable Status" "Not triggered,Triggered" textline " " bitfld.long 0x00 11. " SWCHENA11 ,SW Channel 11 Enable Status" "Not triggered,Triggered" bitfld.long 0x00 10. " SWCHENA10 ,SW Channel 10 Enable Status" "Not triggered,Triggered" bitfld.long 0x00 9. " SWCHENA9 ,SW Channel 9 Enable Status" "Not triggered,Triggered" bitfld.long 0x00 8. " SWCHENA8 ,SW Channel 8 Enable Status" "Not triggered,Triggered" textline " " bitfld.long 0x00 7. " SWCHENA7 ,SW Channel 7 Enable Status" "Not triggered,Triggered" bitfld.long 0x00 6. " SWCHENA6 ,SW Channel 6 Enable Status" "Not triggered,Triggered" bitfld.long 0x00 5. " SWCHENA5 ,SW Channel 5 Enable Status" "Not triggered,Triggered" bitfld.long 0x00 4. " SWCHENA4 ,SW Channel 4 Enable Status" "Not triggered,Triggered" textline " " bitfld.long 0x00 3. " SWCHENA3 ,SW Channel 3 Enable Status" "Not triggered,Triggered" bitfld.long 0x00 2. " SWCHENA2 ,SW Channel 2 Enable Status" "Not triggered,Triggered" bitfld.long 0x00 1. " SWCHENA1 ,SW Channel 1 Enable Status" "Not triggered,Triggered" bitfld.long 0x00 0. " SWCHENA0 ,SW Channel 0 Enable Status" "Not triggered,Triggered" width 10. group.long 0x2c++0x3 line.long 0x0 "SWCHENAR,SWCHANNEL ENABLE RESET and STATUS Register" bitfld.long 0x00 15. " SWCHDIS15 ,SW Channel 15 Disable" "No effect,Reset" bitfld.long 0x00 14. " SWCHDIS14 ,SW Channel 14 Disable" "No effect,Reset" bitfld.long 0x00 13. " SWCHDIS13 ,SW Channel 13 Disable" "No effect,Reset" bitfld.long 0x00 12. " SWCHDIS12 ,SW Channel 12 Disable" "No effect,Reset" textline " " bitfld.long 0x00 11. " SWCHDIS11 ,SW Channel 11 Disable" "No effect,Reset" bitfld.long 0x00 10. " SWCHDIS10 ,SW Channel 10 Disable" "No effect,Reset" bitfld.long 0x00 9. " SWCHDIS9 ,SW Channel 9 Disable" "No effect,Reset" bitfld.long 0x00 8. " SWCHDIS8 ,SW Channel 8 Disable" "No effect,Reset" textline " " bitfld.long 0x00 7. " SWCHDIS7 ,SW Channel 7 Disable" "No effect,Reset" bitfld.long 0x00 6. " SWCHDIS6 ,SW Channel 6 Disable" "No effect,Reset" bitfld.long 0x00 5. " SWCHDIS5 ,SW Channel 5 Disable" "No effect,Reset" bitfld.long 0x00 4. " SWCHDIS4 ,SW Channel 4 Disable" "No effect,Reset" textline " " bitfld.long 0x00 3. " SWCHDIS3 ,SW Channel 3 Disable" "No effect,Reset" bitfld.long 0x00 2. " SWCHDIS2 ,SW Channel 2 Disable" "No effect,Reset" bitfld.long 0x00 1. " SWCHDIS1 ,SW Channel 1 Disable" "No effect,Reset" bitfld.long 0x00 0. " SWCHDIS0 ,SW Channel 0 Disable" "No effect,Reset" tree.end textline " " width 10. group.long 0x34++0x3 line.long 0x0 "CHPRIOS,CHANNEL PRIORITY SET Register" bitfld.long 0x00 15. " CPS15 ,Channel Priority 15 Set" "Low,High" bitfld.long 0x00 14. " CPS14 ,Channel Priority 14 Set" "Low,High" bitfld.long 0x00 13. " CPS13 ,Channel Priority 13 Set" "Low,High" bitfld.long 0x00 12. " CPS12 ,Channel Priority 12 Set" "Low,High" textline " " bitfld.long 0x00 11. " CPS11 ,Channel Priority 11 Set" "Low,High" bitfld.long 0x00 10. " CPS10 ,Channel Priority 10 Set" "Low,High" bitfld.long 0x00 9. " CPS9 ,Channel Priority 9 Set" "Low,High" bitfld.long 0x00 8. " CPS8 ,Channel Priority 8 Set" "Low,High" textline " " bitfld.long 0x00 7. " CPS7 ,Channel Priority 7 Set" "Low,High" bitfld.long 0x00 6. " CPS6 ,Channel Priority 6 Set" "Low,High" bitfld.long 0x00 5. " CPS5 ,Channel Priority 5 Set" "Low,High" bitfld.long 0x00 4. " CPS4 ,Channel Priority 4 Set" "Low,High" textline " " bitfld.long 0x00 3. " CPS3 ,Channel Priority 3 Set" "Low,High" bitfld.long 0x00 2. " CPS2 ,Channel Priority 2 Set" "Low,High" bitfld.long 0x00 1. " CPS1 ,Channel Priority 1 Set" "Low,High" bitfld.long 0x00 0. " CPS0 ,Channel Priority 0 Set" "Low,High" width 10. group.long 0x3C++0x3 line.long 0x0 "CHPRIOR,CHANNEL PRIORITY RESET" bitfld.long 0x00 15. " CPR15 ,Channel Priority 15" "No effect,Reset" bitfld.long 0x00 14. " CPR14 ,Channel Priority 14" "No effect,Reset" bitfld.long 0x00 13. " CPR13 ,Channel Priority 13" "No effect,Reset" bitfld.long 0x00 12. " CPR12 ,Channel Priority 12" "No effect,Reset" textline " " bitfld.long 0x00 11. " CPR11 ,Channel Priority 11" "No effect,Reset" bitfld.long 0x00 10. " CPR10 ,Channel Priority 10" "No effect,Reset" bitfld.long 0x00 9. " CPR9 ,Channel Priority 9" "No effect,Reset" bitfld.long 0x00 8. " CPR8 ,Channel Priority 8" "No effect,Reset" textline " " bitfld.long 0x00 7. " CPR7 ,Channel Priority 7" "No effect,Reset" bitfld.long 0x00 6. " CPR6 ,Channel Priority 6" "No effect,Reset" bitfld.long 0x00 5. " CPR5 ,Channel Priority 5" "No effect,Reset" bitfld.long 0x00 4. " CPR4 ,Channel Priority 4" "No effect,Reset" textline " " bitfld.long 0x00 3. " CPR3 ,Channel Priority 3" "No effect,Reset" bitfld.long 0x00 2. " CPR2 ,Channel Priority 2" "No effect,Reset" bitfld.long 0x00 1. " CPR1 ,Channel Priority 1" "No effect,Reset" bitfld.long 0x00 0. " CPR0 ,Channel Priority 0" "No effect,Reset" width 10. group.long 0x44++0x3 line.long 0x0 "GCHIENAS,GLOBAL CHANNEL INTERRUPT ENABLE SET" bitfld.long 0x00 15. " GCHIE15 ,Global Channel Interrupt Enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " GCHIE14 ,Global Channel Interrupt Enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " GCHIE13 ,Global Channel Interrupt Enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " GCHIE12 ,Global Channel Interrupt Enable 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " GCHIE11 ,Global Channel Interrupt Enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " GCHIE10 ,Global Channel Interrupt Enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " GCHIE9 ,Global Channel Interrupt Enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " GCHIE8 ,Global Channel Interrupt Enable 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " GCHIE7 ,Global Channel Interrupt Enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " GCHIE6 ,Global Channel Interrupt Enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " GCHIE5 ,Global Channel Interrupt Enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " GCHIE4 ,Global Channel Interrupt Enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " GCHIE3 ,Global Channel Interrupt Enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " GCHIE2 ,Global Channel Interrupt Enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " GCHIE1 ,Global Channel Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " GCHIE0 ,Global Channel Interrupt Enable 0" "Disabled,Enabled" width 10. group.long 0x4C++0x3 line.long 0x0 "GCHIENAR,GLOBAL CHANNEL INTERRUPT ENABLE RESET" bitfld.long 0x00 15. " GCHID15 ,Global Channel Interrupt Disable 15" "No effect,Reset" bitfld.long 0x00 14. " GCHID14 ,Global Channel Interrupt Disable 14" "No effect,Reset" bitfld.long 0x00 13. " GCHID13 ,Global Channel Interrupt Disable 13" "No effect,Reset" bitfld.long 0x00 12. " GCHID12 ,Global Channel Interrupt Disable 12" "No effect,Reset" textline " " bitfld.long 0x00 11. " GCHID11 ,Global Channel Interrupt Disable 11" "No effect,Reset" bitfld.long 0x00 10. " GCHID10 ,Global Channel Interrupt Disable 10" "No effect,Reset" bitfld.long 0x00 9. " GCHID9 ,Global Channel Interrupt Disable 9" "No effect,Reset" bitfld.long 0x00 8. " GCHID8 ,Global Channel Interrupt Disable 8" "No effect,Reset" textline " " bitfld.long 0x00 7. " GCHID7 ,Global Channel Interrupt Disable 7" "No effect,Reset" bitfld.long 0x00 6. " GCHID6 ,Global Channel Interrupt Disable 6" "No effect,Reset" bitfld.long 0x00 5. " GCHID5 ,Global Channel Interrupt Disable 5" "No effect,Reset" bitfld.long 0x00 4. " GCHID4 ,Global Channel Interrupt Disable 4" "No effect,Reset" textline " " bitfld.long 0x00 3. " GCHID3 ,Global Channel Interrupt Disable 3" "No effect,Reset" bitfld.long 0x00 2. " GCHID2 ,Global Channel Interrupt Disable 2" "No effect,Reset" bitfld.long 0x00 1. " GCHID1 ,Global Channel Interrupt Disable 1" "No effect,Reset" bitfld.long 0x00 0. " GCHID0 ,Global Channel Interrupt Disable 0" "No effect,Reset" width 10. tree "DMA Request Assignment Registers" group.long 0x54++0x3 line.long 0x0 "DREQASI0,DMA REQUEST ASSIGNMENT Register 0" sif (cpu()==("RM48L950-ZWT")||cpu()==("RM48L950-PGE")||cpu()==("RM48L750-ZWT")||cpu()==("RM48L750-PGE")||cpu()==("RM48L550-ZWT")||cpu()==("RM48L550-PGE")||cpu()=="RM48L952-PGE"||cpu()=="RM48L952-ZWT"||cpu()==("RM46L852-ZWT")||cpu()==("RM46L852-PGE")||cpu()==("RM46L850-ZWT")||cpu()==("RM46L850-PGE")||cpu()==("RM46L450-ZWT")||cpu()==("RM46L450-PGE")) bitfld.long 0x00 24.--29. " CH0ASI ,Channel 0 Assignment" "MIBSPI1[1],MIBSPI1,SPI2 receive,SPI2 transmit,MIBSPI1[2] / MIBSPI3[2] / DCAN2 IF3,MIBSPI1[3] / MIBSPI3[3] / DCAN2 IF2,DCAN1 IF2 / MIBSPI5[2],MIBADC1 event / MIBSPI5[3],MIBSPI1[4] / MIBSPI3[4] / DCAN1 IF1,MIBSPI1[5] / MIBSPI3[5] / DCAN2 IF1,MIBADC1 G1 / I2C receive / MIBSPI5[4],MIBADC1 G2 / I2C transmit / MIBSPI5[5],RTI DMAREQ0 / MIBSPI1[6] / MIBSPI3[6],RTI DMAREQ1 / MIBSPI1[7] / MIBSPI3[7],MIBSPI3[1](1) / USB_FUNC_DMATXREQ_ON[0] / MibADC2 event / MIBSPI5[6],MIBSPI3[0](2) / USB_FUNC_DMARXREQ_ON[0] /MIBSPI5[7],MIBSPI1[8] / MIBSPI3[8] / DCAN1 IF3 / MibADC2 G1,MIBSPI1[9] / MIBSPI3[9] / DCAN3 IF1 / MibADC2 G2,RTI DMAREQ2 / USB_FUNC_DMATXREQ_ON[1] /MIBSPI5[8],RTI DMAREQ3 / USB_FUNC_DMARXREQ_ON[1] /MIBSPI5[9],N2HET1 DMAREQ[4] / N2HET2 DMAREQ[4] / DCAN3 IF2,N2HET1 DMAREQ[5] / N2HET2 DMAREQ[5] / DCAN3 IF3,MIBSPI1[10] / MIBSPI3[10] / MIBSPI5[10],MIBSPI1[11] / MIBSPI3[11] / MIBSPI5[11],N2HET1 DMAREQ[6] / N2HET2 DMAREQ[6] / SPI4 receive / MIBSPI5[12],N2HET1 DMAREQ[7] / N2HET2 DMAREQ[7] / SPI4 transmit / MIBSPI5[13],CRC DMAREQ[0] / MIBSPI1[12] / MIBSPI3[12],CRC DMAREQ[1] / MIBSPI1[13] / MIBSPI3[13],LIN receive / USB_FUNC_DMATXREQ_ON[2] / MIBSPI5[14],LIN transmit / USB_FUNC_DMARXREQ_ON[2] / MIBSPI5[15],MIBSPI1[14] / MIBSPI3[14] / SCI receive /MIBSPI5[1],MIBSPI1[15] / MIBSPI3[15] / SCI transmit /MIBSPI5[0],?..." textline " " bitfld.long 0x00 16.--21. " CH1ASI ,Channel 1 Assignment" "MIBSPI1[1],MIBSPI1,SPI2 receive,SPI2 transmit,MIBSPI1[2] / MIBSPI3[2] / DCAN2 IF3,MIBSPI1[3] / MIBSPI3[3] / DCAN2 IF2,DCAN1 IF2 / MIBSPI5[2],MIBADC1 event / MIBSPI5[3],MIBSPI1[4] / MIBSPI3[4] / DCAN1 IF1,MIBSPI1[5] / MIBSPI3[5] / DCAN2 IF1,MIBADC1 G1 / I2C receive / MIBSPI5[4],MIBADC1 G2 / I2C transmit / MIBSPI5[5],RTI DMAREQ0 / MIBSPI1[6] / MIBSPI3[6],RTI DMAREQ1 / MIBSPI1[7] / MIBSPI3[7],MIBSPI3[1](1) / USB_FUNC_DMATXREQ_ON[0] / MibADC2 event / MIBSPI5[6],MIBSPI3[0](2) / USB_FUNC_DMARXREQ_ON[0] /MIBSPI5[7],MIBSPI1[8] / MIBSPI3[8] / DCAN1 IF3 / MibADC2 G1,MIBSPI1[9] / MIBSPI3[9] / DCAN3 IF1 / MibADC2 G2,RTI DMAREQ2 / USB_FUNC_DMATXREQ_ON[1] /MIBSPI5[8],RTI DMAREQ3 / USB_FUNC_DMARXREQ_ON[1] /MIBSPI5[9],N2HET1 DMAREQ[4] / N2HET2 DMAREQ[4] / DCAN3 IF2,N2HET1 DMAREQ[5] / N2HET2 DMAREQ[5] / DCAN3 IF3,MIBSPI1[10] / MIBSPI3[10] / MIBSPI5[10],MIBSPI1[11] / MIBSPI3[11] / MIBSPI5[11],N2HET1 DMAREQ[6] / N2HET2 DMAREQ[6] / SPI4 receive / MIBSPI5[12],N2HET1 DMAREQ[7] / N2HET2 DMAREQ[7] / SPI4 transmit / MIBSPI5[13],CRC DMAREQ[0] / MIBSPI1[12] / MIBSPI3[12],CRC DMAREQ[1] / MIBSPI1[13] / MIBSPI3[13],LIN receive / USB_FUNC_DMATXREQ_ON[2] / MIBSPI5[14],LIN transmit / USB_FUNC_DMARXREQ_ON[2] / MIBSPI5[15],MIBSPI1[14] / MIBSPI3[14] / SCI receive /MIBSPI5[1],MIBSPI1[15] / MIBSPI3[15] / SCI transmit /MIBSPI5[0],?..." textline " " bitfld.long 0x00 8.--13. " CH2ASI ,Channel 2 Assignment" "MIBSPI1[1],MIBSPI1,SPI2 receive,SPI2 transmit,MIBSPI1[2] / MIBSPI3[2] / DCAN2 IF3,MIBSPI1[3] / MIBSPI3[3] / DCAN2 IF2,DCAN1 IF2 / MIBSPI5[2],MIBADC1 event / MIBSPI5[3],MIBSPI1[4] / MIBSPI3[4] / DCAN1 IF1,MIBSPI1[5] / MIBSPI3[5] / DCAN2 IF1,MIBADC1 G1 / I2C receive / MIBSPI5[4],MIBADC1 G2 / I2C transmit / MIBSPI5[5],RTI DMAREQ0 / MIBSPI1[6] / MIBSPI3[6],RTI DMAREQ1 / MIBSPI1[7] / MIBSPI3[7],MIBSPI3[1](1) / USB_FUNC_DMATXREQ_ON[0] / MibADC2 event / MIBSPI5[6],MIBSPI3[0](2) / USB_FUNC_DMARXREQ_ON[0] /MIBSPI5[7],MIBSPI1[8] / MIBSPI3[8] / DCAN1 IF3 / MibADC2 G1,MIBSPI1[9] / MIBSPI3[9] / DCAN3 IF1 / MibADC2 G2,RTI DMAREQ2 / USB_FUNC_DMATXREQ_ON[1] /MIBSPI5[8],RTI DMAREQ3 / USB_FUNC_DMARXREQ_ON[1] /MIBSPI5[9],N2HET1 DMAREQ[4] / N2HET2 DMAREQ[4] / DCAN3 IF2,N2HET1 DMAREQ[5] / N2HET2 DMAREQ[5] / DCAN3 IF3,MIBSPI1[10] / MIBSPI3[10] / MIBSPI5[10],MIBSPI1[11] / MIBSPI3[11] / MIBSPI5[11],N2HET1 DMAREQ[6] / N2HET2 DMAREQ[6] / SPI4 receive / MIBSPI5[12],N2HET1 DMAREQ[7] / N2HET2 DMAREQ[7] / SPI4 transmit / MIBSPI5[13],CRC DMAREQ[0] / MIBSPI1[12] / MIBSPI3[12],CRC DMAREQ[1] / MIBSPI1[13] / MIBSPI3[13],LIN receive / USB_FUNC_DMATXREQ_ON[2] / MIBSPI5[14],LIN transmit / USB_FUNC_DMARXREQ_ON[2] / MIBSPI5[15],MIBSPI1[14] / MIBSPI3[14] / SCI receive /MIBSPI5[1],MIBSPI1[15] / MIBSPI3[15] / SCI transmit /MIBSPI5[0],?..." textline " " bitfld.long 0x00 0.--5. " CH3ASI ,Channel 3 Assignment" "MIBSPI1[1],MIBSPI1,SPI2 receive,SPI2 transmit,MIBSPI1[2] / MIBSPI3[2] / DCAN2 IF3,MIBSPI1[3] / MIBSPI3[3] / DCAN2 IF2,DCAN1 IF2 / MIBSPI5[2],MIBADC1 event / MIBSPI5[3],MIBSPI1[4] / MIBSPI3[4] / DCAN1 IF1,MIBSPI1[5] / MIBSPI3[5] / DCAN2 IF1,MIBADC1 G1 / I2C receive / MIBSPI5[4],MIBADC1 G2 / I2C transmit / MIBSPI5[5],RTI DMAREQ0 / MIBSPI1[6] / MIBSPI3[6],RTI DMAREQ1 / MIBSPI1[7] / MIBSPI3[7],MIBSPI3[1](1) / USB_FUNC_DMATXREQ_ON[0] / MibADC2 event / MIBSPI5[6],MIBSPI3[0](2) / USB_FUNC_DMARXREQ_ON[0] /MIBSPI5[7],MIBSPI1[8] / MIBSPI3[8] / DCAN1 IF3 / MibADC2 G1,MIBSPI1[9] / MIBSPI3[9] / DCAN3 IF1 / MibADC2 G2,RTI DMAREQ2 / USB_FUNC_DMATXREQ_ON[1] /MIBSPI5[8],RTI DMAREQ3 / USB_FUNC_DMARXREQ_ON[1] /MIBSPI5[9],N2HET1 DMAREQ[4] / N2HET2 DMAREQ[4] / DCAN3 IF2,N2HET1 DMAREQ[5] / N2HET2 DMAREQ[5] / DCAN3 IF3,MIBSPI1[10] / MIBSPI3[10] / MIBSPI5[10],MIBSPI1[11] / MIBSPI3[11] / MIBSPI5[11],N2HET1 DMAREQ[6] / N2HET2 DMAREQ[6] / SPI4 receive / MIBSPI5[12],N2HET1 DMAREQ[7] / N2HET2 DMAREQ[7] / SPI4 transmit / MIBSPI5[13],CRC DMAREQ[0] / MIBSPI1[12] / MIBSPI3[12],CRC DMAREQ[1] / MIBSPI1[13] / MIBSPI3[13],LIN receive / USB_FUNC_DMATXREQ_ON[2] / MIBSPI5[14],LIN transmit / USB_FUNC_DMARXREQ_ON[2] / MIBSPI5[15],MIBSPI1[14] / MIBSPI3[14] / SCI receive /MIBSPI5[1],MIBSPI1[15] / MIBSPI3[15] / SCI transmit /MIBSPI5[0],?..." else bitfld.long 0x00 24.--29. " CH0ASI ,Channel 0 Assignment" "MIBSPI1[1],MIBSPI1[0],SPI2 receive,SPI2 transmit,MIBSPI1[2] / MIBSPI3[2] / DCAN2 IF3,MIBSPI1[3] / MIBSPI3[3] / DCAN2 IF2,DCAN1 IF2 / MIBSPI5[2],MIBADC1 event / MIBSPI5[3],MIBSPI1[4] / MIBSPI3[4] / DCAN1 IF1,MIBSPI1[5] / MIBSPI3[5] / DCAN2 IF1,MIBADC1 G1 / I2C receive / MIBSPI5[4],MIBADC1 G2 / I2C transmit / MIBSPI5[5],RTI DMAREQ0 / MIBSPI1[6] / MIBSPI3[6],RTI DMAREQ1 / MIBSPI1[7] / MIBSPI3[7],MIBSPI3[1] / MibADC2 event / MIBSPI5[6],MIBSPI3[0] / MIBSPI5[7],MIBSPI1[8] / MIBSPI3[8] / DCAN1 IF3 / MibADC2 G1,MIBSPI1[9] / MIBSPI3[9] / DCAN3 IF1 / MibADC2 G2,RTI DMAREQ2 / MIBSPI5[8],RTI DMAREQ3 / MIBSPI5[9],N2HET1 DMAREQ[4] / N2HET2 DMAREQ[4] / DCAN3IF2,N2HET1 DMAREQ[5] / N2HET2 DMAREQ[5] / DCAN3IF3,MIBSPI1[10] / MIBSPI3[10] / MIBSPI5[10],MIBSPI1[11] / MIBSPI3[11] / MIBSPI5[11],N2HET1 DMAREQ[6] / N2HET2 DMAREQ[6] / SPI4 receive / MIBSPI5[12],N2HET1 DMAREQ[7] / N2HET2 DMAREQ[7] / SPI4 transmit / MIBSPI5[13],CRC DMAREQ[0] / MIBSPI1[12] / MIBSPI3[12],CRC DMAREQ[1] / MIBSPI1[13] / MIBSPI3[13],LIN receive / MIBSPI5[14],LIN transmit / MIBSPI5[15],MIBSPI1[14] / MIBSPI3[14] / SCI receive /MIBSPI5[1],MIBSPI1[15] / MIBSPI3[15] / SCI transmit /MIBSPI5[0],?..." textline " " bitfld.long 0x00 16.--21. " CH1ASI ,Channel 1 Assignment" "MIBSPI1[1],MIBSPI1[0],SPI2 receive,SPI2 transmit,MIBSPI1[2] / MIBSPI3[2] / DCAN2 IF3,MIBSPI1[3] / MIBSPI3[3] / DCAN2 IF2,DCAN1 IF2 / MIBSPI5[2],MIBADC1 event / MIBSPI5[3],MIBSPI1[4] / MIBSPI3[4] / DCAN1 IF1,MIBSPI1[5] / MIBSPI3[5] / DCAN2 IF1,MIBADC1 G1 / I2C receive / MIBSPI5[4],MIBADC1 G2 / I2C transmit / MIBSPI5[5],RTI DMAREQ0 / MIBSPI1[6] / MIBSPI3[6],RTI DMAREQ1 / MIBSPI1[7] / MIBSPI3[7],MIBSPI3[1] / MibADC2 event / MIBSPI5[6],MIBSPI3[0] / MIBSPI5[7],MIBSPI1[8] / MIBSPI3[8] / DCAN1 IF3 / MibADC2 G1,MIBSPI1[9] / MIBSPI3[9] / DCAN3 IF1 / MibADC2 G2,RTI DMAREQ2 / MIBSPI5[8],RTI DMAREQ3 / MIBSPI5[9],N2HET1 DMAREQ[4] / N2HET2 DMAREQ[4] / DCAN3IF2,N2HET1 DMAREQ[5] / N2HET2 DMAREQ[5] / DCAN3IF3,MIBSPI1[10] / MIBSPI3[10] / MIBSPI5[10],MIBSPI1[11] / MIBSPI3[11] / MIBSPI5[11],N2HET1 DMAREQ[6] / N2HET2 DMAREQ[6] / SPI4 receive / MIBSPI5[12],N2HET1 DMAREQ[7] / N2HET2 DMAREQ[7] / SPI4 transmit / MIBSPI5[13],CRC DMAREQ[0] / MIBSPI1[12] / MIBSPI3[12],CRC DMAREQ[1] / MIBSPI1[13] / MIBSPI3[13],LIN receive / MIBSPI5[14],LIN transmit / MIBSPI5[15],MIBSPI1[14] / MIBSPI3[14] / SCI receive /MIBSPI5[1],MIBSPI1[15] / MIBSPI3[15] / SCI transmit /MIBSPI5[0],?..." textline " " bitfld.long 0x00 8.--13. " CH2ASI ,Channel 2 Assignment" "MIBSPI1[1],MIBSPI1[0],SPI2 receive,SPI2 transmit,MIBSPI1[2] / MIBSPI3[2] / DCAN2 IF3,MIBSPI1[3] / MIBSPI3[3] / DCAN2 IF2,DCAN1 IF2 / MIBSPI5[2],MIBADC1 event / MIBSPI5[3],MIBSPI1[4] / MIBSPI3[4] / DCAN1 IF1,MIBSPI1[5] / MIBSPI3[5] / DCAN2 IF1,MIBADC1 G1 / I2C receive / MIBSPI5[4],MIBADC1 G2 / I2C transmit / MIBSPI5[5],RTI DMAREQ0 / MIBSPI1[6] / MIBSPI3[6],RTI DMAREQ1 / MIBSPI1[7] / MIBSPI3[7],MIBSPI3[1] / MibADC2 event / MIBSPI5[6],MIBSPI3[0] / MIBSPI5[7],MIBSPI1[8] / MIBSPI3[8] / DCAN1 IF3 / MibADC2 G1,MIBSPI1[9] / MIBSPI3[9] / DCAN3 IF1 / MibADC2 G2,RTI DMAREQ2 / MIBSPI5[8],RTI DMAREQ3 / MIBSPI5[9],N2HET1 DMAREQ[4] / N2HET2 DMAREQ[4] / DCAN3IF2,N2HET1 DMAREQ[5] / N2HET2 DMAREQ[5] / DCAN3IF3,MIBSPI1[10] / MIBSPI3[10] / MIBSPI5[10],MIBSPI1[11] / MIBSPI3[11] / MIBSPI5[11],N2HET1 DMAREQ[6] / N2HET2 DMAREQ[6] / SPI4 receive / MIBSPI5[12],N2HET1 DMAREQ[7] / N2HET2 DMAREQ[7] / SPI4 transmit / MIBSPI5[13],CRC DMAREQ[0] / MIBSPI1[12] / MIBSPI3[12],CRC DMAREQ[1] / MIBSPI1[13] / MIBSPI3[13],LIN receive / MIBSPI5[14],LIN transmit / MIBSPI5[15],MIBSPI1[14] / MIBSPI3[14] / SCI receive /MIBSPI5[1],MIBSPI1[15] / MIBSPI3[15] / SCI transmit /MIBSPI5[0],?..." textline " " bitfld.long 0x00 0.--5. " CH3ASI ,Channel 3 Assignment" "MIBSPI1[1],MIBSPI1[0],SPI2 receive,SPI2 transmit,MIBSPI1[2] / MIBSPI3[2] / DCAN2 IF3,MIBSPI1[3] / MIBSPI3[3] / DCAN2 IF2,DCAN1 IF2 / MIBSPI5[2],MIBADC1 event / MIBSPI5[3],MIBSPI1[4] / MIBSPI3[4] / DCAN1 IF1,MIBSPI1[5] / MIBSPI3[5] / DCAN2 IF1,MIBADC1 G1 / I2C receive / MIBSPI5[4],MIBADC1 G2 / I2C transmit / MIBSPI5[5],RTI DMAREQ0 / MIBSPI1[6] / MIBSPI3[6],RTI DMAREQ1 / MIBSPI1[7] / MIBSPI3[7],MIBSPI3[1] / MibADC2 event / MIBSPI5[6],MIBSPI3[0] / MIBSPI5[7],MIBSPI1[8] / MIBSPI3[8] / DCAN1 IF3 / MibADC2 G1,MIBSPI1[9] / MIBSPI3[9] / DCAN3 IF1 / MibADC2 G2,RTI DMAREQ2 / MIBSPI5[8],RTI DMAREQ3 / MIBSPI5[9],N2HET1 DMAREQ[4] / N2HET2 DMAREQ[4] / DCAN3IF2,N2HET1 DMAREQ[5] / N2HET2 DMAREQ[5] / DCAN3IF3,MIBSPI1[10] / MIBSPI3[10] / MIBSPI5[10],MIBSPI1[11] / MIBSPI3[11] / MIBSPI5[11],N2HET1 DMAREQ[6] / N2HET2 DMAREQ[6] / SPI4 receive / MIBSPI5[12],N2HET1 DMAREQ[7] / N2HET2 DMAREQ[7] / SPI4 transmit / MIBSPI5[13],CRC DMAREQ[0] / MIBSPI1[12] / MIBSPI3[12],CRC DMAREQ[1] / MIBSPI1[13] / MIBSPI3[13],LIN receive / MIBSPI5[14],LIN transmit / MIBSPI5[15],MIBSPI1[14] / MIBSPI3[14] / SCI receive /MIBSPI5[1],MIBSPI1[15] / MIBSPI3[15] / SCI transmit /MIBSPI5[0],?..." endif group.long 0x58++0x3 line.long 0x0 "DREQASI1,DMA REQUEST ASSIGNMENT Register 1" sif (cpu()==("RM48L950-ZWT")||cpu()==("RM48L950-PGE")||cpu()==("RM48L750-ZWT")||cpu()==("RM48L750-PGE")||cpu()==("RM48L550-ZWT")||cpu()==("RM48L550-PGE")||cpu()=="RM48L952-PGE"||cpu()=="RM48L952-ZWT"||cpu()==("RM46L852-ZWT")||cpu()==("RM46L852-PGE")||cpu()==("RM46L850-ZWT")||cpu()==("RM46L850-PGE")||cpu()==("RM46L450-ZWT")||cpu()==("RM46L450-PGE")) bitfld.long 0x00 24.--29. " CH4ASI ,Channel 4 Assignment" "MIBSPI1[1],MIBSPI1,SPI2 receive,SPI2 transmit,MIBSPI1[2] / MIBSPI3[2] / DCAN2 IF3,MIBSPI1[3] / MIBSPI3[3] / DCAN2 IF2,DCAN1 IF2 / MIBSPI5[2],MIBADC1 event / MIBSPI5[3],MIBSPI1[4] / MIBSPI3[4] / DCAN1 IF1,MIBSPI1[5] / MIBSPI3[5] / DCAN2 IF1,MIBADC1 G1 / I2C receive / MIBSPI5[4],MIBADC1 G2 / I2C transmit / MIBSPI5[5],RTI DMAREQ0 / MIBSPI1[6] / MIBSPI3[6],RTI DMAREQ1 / MIBSPI1[7] / MIBSPI3[7],MIBSPI3[1](1) / USB_FUNC_DMATXREQ_ON[0] / MibADC2 event / MIBSPI5[6],MIBSPI3[0](2) / USB_FUNC_DMARXREQ_ON[0] /MIBSPI5[7],MIBSPI1[8] / MIBSPI3[8] / DCAN1 IF3 / MibADC2 G1,MIBSPI1[9] / MIBSPI3[9] / DCAN3 IF1 / MibADC2 G2,RTI DMAREQ2 / USB_FUNC_DMATXREQ_ON[1] /MIBSPI5[8],RTI DMAREQ3 / USB_FUNC_DMARXREQ_ON[1] /MIBSPI5[9],N2HET1 DMAREQ[4] / N2HET2 DMAREQ[4] / DCAN3 IF2,N2HET1 DMAREQ[5] / N2HET2 DMAREQ[5] / DCAN3 IF3,MIBSPI1[10] / MIBSPI3[10] / MIBSPI5[10],MIBSPI1[11] / MIBSPI3[11] / MIBSPI5[11],N2HET1 DMAREQ[6] / N2HET2 DMAREQ[6] / SPI4 receive / MIBSPI5[12],N2HET1 DMAREQ[7] / N2HET2 DMAREQ[7] / SPI4 transmit / MIBSPI5[13],CRC DMAREQ[0] / MIBSPI1[12] / MIBSPI3[12],CRC DMAREQ[1] / MIBSPI1[13] / MIBSPI3[13],LIN receive / USB_FUNC_DMATXREQ_ON[2] / MIBSPI5[14],LIN transmit / USB_FUNC_DMARXREQ_ON[2] / MIBSPI5[15],MIBSPI1[14] / MIBSPI3[14] / SCI receive /MIBSPI5[1],MIBSPI1[15] / MIBSPI3[15] / SCI transmit /MIBSPI5[0],?..." textline " " bitfld.long 0x00 16.--21. " CH5ASI ,Channel 5 Assignment" "MIBSPI1[1],MIBSPI1,SPI2 receive,SPI2 transmit,MIBSPI1[2] / MIBSPI3[2] / DCAN2 IF3,MIBSPI1[3] / MIBSPI3[3] / DCAN2 IF2,DCAN1 IF2 / MIBSPI5[2],MIBADC1 event / MIBSPI5[3],MIBSPI1[4] / MIBSPI3[4] / DCAN1 IF1,MIBSPI1[5] / MIBSPI3[5] / DCAN2 IF1,MIBADC1 G1 / I2C receive / MIBSPI5[4],MIBADC1 G2 / I2C transmit / MIBSPI5[5],RTI DMAREQ0 / MIBSPI1[6] / MIBSPI3[6],RTI DMAREQ1 / MIBSPI1[7] / MIBSPI3[7],MIBSPI3[1](1) / USB_FUNC_DMATXREQ_ON[0] / MibADC2 event / MIBSPI5[6],MIBSPI3[0](2) / USB_FUNC_DMARXREQ_ON[0] /MIBSPI5[7],MIBSPI1[8] / MIBSPI3[8] / DCAN1 IF3 / MibADC2 G1,MIBSPI1[9] / MIBSPI3[9] / DCAN3 IF1 / MibADC2 G2,RTI DMAREQ2 / USB_FUNC_DMATXREQ_ON[1] /MIBSPI5[8],RTI DMAREQ3 / USB_FUNC_DMARXREQ_ON[1] /MIBSPI5[9],N2HET1 DMAREQ[4] / N2HET2 DMAREQ[4] / DCAN3 IF2,N2HET1 DMAREQ[5] / N2HET2 DMAREQ[5] / DCAN3 IF3,MIBSPI1[10] / MIBSPI3[10] / MIBSPI5[10],MIBSPI1[11] / MIBSPI3[11] / MIBSPI5[11],N2HET1 DMAREQ[6] / N2HET2 DMAREQ[6] / SPI4 receive / MIBSPI5[12],N2HET1 DMAREQ[7] / N2HET2 DMAREQ[7] / SPI4 transmit / MIBSPI5[13],CRC DMAREQ[0] / MIBSPI1[12] / MIBSPI3[12],CRC DMAREQ[1] / MIBSPI1[13] / MIBSPI3[13],LIN receive / USB_FUNC_DMATXREQ_ON[2] / MIBSPI5[14],LIN transmit / USB_FUNC_DMARXREQ_ON[2] / MIBSPI5[15],MIBSPI1[14] / MIBSPI3[14] / SCI receive /MIBSPI5[1],MIBSPI1[15] / MIBSPI3[15] / SCI transmit /MIBSPI5[0],?..." textline " " bitfld.long 0x00 8.--13. " CH6ASI ,Channel 6 Assignment" "MIBSPI1[1],MIBSPI1,SPI2 receive,SPI2 transmit,MIBSPI1[2] / MIBSPI3[2] / DCAN2 IF3,MIBSPI1[3] / MIBSPI3[3] / DCAN2 IF2,DCAN1 IF2 / MIBSPI5[2],MIBADC1 event / MIBSPI5[3],MIBSPI1[4] / MIBSPI3[4] / DCAN1 IF1,MIBSPI1[5] / MIBSPI3[5] / DCAN2 IF1,MIBADC1 G1 / I2C receive / MIBSPI5[4],MIBADC1 G2 / I2C transmit / MIBSPI5[5],RTI DMAREQ0 / MIBSPI1[6] / MIBSPI3[6],RTI DMAREQ1 / MIBSPI1[7] / MIBSPI3[7],MIBSPI3[1](1) / USB_FUNC_DMATXREQ_ON[0] / MibADC2 event / MIBSPI5[6],MIBSPI3[0](2) / USB_FUNC_DMARXREQ_ON[0] /MIBSPI5[7],MIBSPI1[8] / MIBSPI3[8] / DCAN1 IF3 / MibADC2 G1,MIBSPI1[9] / MIBSPI3[9] / DCAN3 IF1 / MibADC2 G2,RTI DMAREQ2 / USB_FUNC_DMATXREQ_ON[1] /MIBSPI5[8],RTI DMAREQ3 / USB_FUNC_DMARXREQ_ON[1] /MIBSPI5[9],N2HET1 DMAREQ[4] / N2HET2 DMAREQ[4] / DCAN3 IF2,N2HET1 DMAREQ[5] / N2HET2 DMAREQ[5] / DCAN3 IF3,MIBSPI1[10] / MIBSPI3[10] / MIBSPI5[10],MIBSPI1[11] / MIBSPI3[11] / MIBSPI5[11],N2HET1 DMAREQ[6] / N2HET2 DMAREQ[6] / SPI4 receive / MIBSPI5[12],N2HET1 DMAREQ[7] / N2HET2 DMAREQ[7] / SPI4 transmit / MIBSPI5[13],CRC DMAREQ[0] / MIBSPI1[12] / MIBSPI3[12],CRC DMAREQ[1] / MIBSPI1[13] / MIBSPI3[13],LIN receive / USB_FUNC_DMATXREQ_ON[2] / MIBSPI5[14],LIN transmit / USB_FUNC_DMARXREQ_ON[2] / MIBSPI5[15],MIBSPI1[14] / MIBSPI3[14] / SCI receive /MIBSPI5[1],MIBSPI1[15] / MIBSPI3[15] / SCI transmit /MIBSPI5[0],?..." textline " " bitfld.long 0x00 0.--5. " CH7ASI ,Channel 7 Assignment" "MIBSPI1[1],MIBSPI1,SPI2 receive,SPI2 transmit,MIBSPI1[2] / MIBSPI3[2] / DCAN2 IF3,MIBSPI1[3] / MIBSPI3[3] / DCAN2 IF2,DCAN1 IF2 / MIBSPI5[2],MIBADC1 event / MIBSPI5[3],MIBSPI1[4] / MIBSPI3[4] / DCAN1 IF1,MIBSPI1[5] / MIBSPI3[5] / DCAN2 IF1,MIBADC1 G1 / I2C receive / MIBSPI5[4],MIBADC1 G2 / I2C transmit / MIBSPI5[5],RTI DMAREQ0 / MIBSPI1[6] / MIBSPI3[6],RTI DMAREQ1 / MIBSPI1[7] / MIBSPI3[7],MIBSPI3[1](1) / USB_FUNC_DMATXREQ_ON[0] / MibADC2 event / MIBSPI5[6],MIBSPI3[0](2) / USB_FUNC_DMARXREQ_ON[0] /MIBSPI5[7],MIBSPI1[8] / MIBSPI3[8] / DCAN1 IF3 / MibADC2 G1,MIBSPI1[9] / MIBSPI3[9] / DCAN3 IF1 / MibADC2 G2,RTI DMAREQ2 / USB_FUNC_DMATXREQ_ON[1] /MIBSPI5[8],RTI DMAREQ3 / USB_FUNC_DMARXREQ_ON[1] /MIBSPI5[9],N2HET1 DMAREQ[4] / N2HET2 DMAREQ[4] / DCAN3 IF2,N2HET1 DMAREQ[5] / N2HET2 DMAREQ[5] / DCAN3 IF3,MIBSPI1[10] / MIBSPI3[10] / MIBSPI5[10],MIBSPI1[11] / MIBSPI3[11] / MIBSPI5[11],N2HET1 DMAREQ[6] / N2HET2 DMAREQ[6] / SPI4 receive / MIBSPI5[12],N2HET1 DMAREQ[7] / N2HET2 DMAREQ[7] / SPI4 transmit / MIBSPI5[13],CRC DMAREQ[0] / MIBSPI1[12] / MIBSPI3[12],CRC DMAREQ[1] / MIBSPI1[13] / MIBSPI3[13],LIN receive / USB_FUNC_DMATXREQ_ON[2] / MIBSPI5[14],LIN transmit / USB_FUNC_DMARXREQ_ON[2] / MIBSPI5[15],MIBSPI1[14] / MIBSPI3[14] / SCI receive /MIBSPI5[1],MIBSPI1[15] / MIBSPI3[15] / SCI transmit /MIBSPI5[0],?..." else bitfld.long 0x00 24.--29. " CH4ASI ,Channel 4 Assignment" "MIBSPI1[1],MIBSPI1[0],SPI2 receive,SPI2 transmit,MIBSPI1[2] / MIBSPI3[2] / DCAN2 IF3,MIBSPI1[3] / MIBSPI3[3] / DCAN2 IF2,DCAN1 IF2 / MIBSPI5[2],MIBADC1 event / MIBSPI5[3],MIBSPI1[4] / MIBSPI3[4] / DCAN1 IF1,MIBSPI1[5] / MIBSPI3[5] / DCAN2 IF1,MIBADC1 G1 / I2C receive / MIBSPI5[4],MIBADC1 G2 / I2C transmit / MIBSPI5[5],RTI DMAREQ0 / MIBSPI1[6] / MIBSPI3[6],RTI DMAREQ1 / MIBSPI1[7] / MIBSPI3[7],MIBSPI3[1] / MibADC2 event / MIBSPI5[6],MIBSPI3[0] / MIBSPI5[7],MIBSPI1[8] / MIBSPI3[8] / DCAN1 IF3 / MibADC2 G1,MIBSPI1[9] / MIBSPI3[9] / DCAN3 IF1 / MibADC2 G2,RTI DMAREQ2 / MIBSPI5[8],RTI DMAREQ3 / MIBSPI5[9],N2HET1 DMAREQ[4] / N2HET2 DMAREQ[4] / DCAN3IF2,N2HET1 DMAREQ[5] / N2HET2 DMAREQ[5] / DCAN3IF3,MIBSPI1[10] / MIBSPI3[10] / MIBSPI5[10],MIBSPI1[11] / MIBSPI3[11] / MIBSPI5[11],N2HET1 DMAREQ[6] / N2HET2 DMAREQ[6] / SPI4 receive / MIBSPI5[12],N2HET1 DMAREQ[7] / N2HET2 DMAREQ[7] / SPI4 transmit / MIBSPI5[13],CRC DMAREQ[0] / MIBSPI1[12] / MIBSPI3[12],CRC DMAREQ[1] / MIBSPI1[13] / MIBSPI3[13],LIN receive / MIBSPI5[14],LIN transmit / MIBSPI5[15],MIBSPI1[14] / MIBSPI3[14] / SCI receive /MIBSPI5[1],MIBSPI1[15] / MIBSPI3[15] / SCI transmit /MIBSPI5[0],?..." textline " " bitfld.long 0x00 16.--21. " CH5ASI ,Channel 5 Assignment" "MIBSPI1[1],MIBSPI1[0],SPI2 receive,SPI2 transmit,MIBSPI1[2] / MIBSPI3[2] / DCAN2 IF3,MIBSPI1[3] / MIBSPI3[3] / DCAN2 IF2,DCAN1 IF2 / MIBSPI5[2],MIBADC1 event / MIBSPI5[3],MIBSPI1[4] / MIBSPI3[4] / DCAN1 IF1,MIBSPI1[5] / MIBSPI3[5] / DCAN2 IF1,MIBADC1 G1 / I2C receive / MIBSPI5[4],MIBADC1 G2 / I2C transmit / MIBSPI5[5],RTI DMAREQ0 / MIBSPI1[6] / MIBSPI3[6],RTI DMAREQ1 / MIBSPI1[7] / MIBSPI3[7],MIBSPI3[1] / MibADC2 event / MIBSPI5[6],MIBSPI3[0] / MIBSPI5[7],MIBSPI1[8] / MIBSPI3[8] / DCAN1 IF3 / MibADC2 G1,MIBSPI1[9] / MIBSPI3[9] / DCAN3 IF1 / MibADC2 G2,RTI DMAREQ2 / MIBSPI5[8],RTI DMAREQ3 / MIBSPI5[9],N2HET1 DMAREQ[4] / N2HET2 DMAREQ[4] / DCAN3IF2,N2HET1 DMAREQ[5] / N2HET2 DMAREQ[5] / DCAN3IF3,MIBSPI1[10] / MIBSPI3[10] / MIBSPI5[10],MIBSPI1[11] / MIBSPI3[11] / MIBSPI5[11],N2HET1 DMAREQ[6] / N2HET2 DMAREQ[6] / SPI4 receive / MIBSPI5[12],N2HET1 DMAREQ[7] / N2HET2 DMAREQ[7] / SPI4 transmit / MIBSPI5[13],CRC DMAREQ[0] / MIBSPI1[12] / MIBSPI3[12],CRC DMAREQ[1] / MIBSPI1[13] / MIBSPI3[13],LIN receive / MIBSPI5[14],LIN transmit / MIBSPI5[15],MIBSPI1[14] / MIBSPI3[14] / SCI receive /MIBSPI5[1],MIBSPI1[15] / MIBSPI3[15] / SCI transmit /MIBSPI5[0],?..." textline " " bitfld.long 0x00 8.--13. " CH6ASI ,Channel 6 Assignment" "MIBSPI1[1],MIBSPI1[0],SPI2 receive,SPI2 transmit,MIBSPI1[2] / MIBSPI3[2] / DCAN2 IF3,MIBSPI1[3] / MIBSPI3[3] / DCAN2 IF2,DCAN1 IF2 / MIBSPI5[2],MIBADC1 event / MIBSPI5[3],MIBSPI1[4] / MIBSPI3[4] / DCAN1 IF1,MIBSPI1[5] / MIBSPI3[5] / DCAN2 IF1,MIBADC1 G1 / I2C receive / MIBSPI5[4],MIBADC1 G2 / I2C transmit / MIBSPI5[5],RTI DMAREQ0 / MIBSPI1[6] / MIBSPI3[6],RTI DMAREQ1 / MIBSPI1[7] / MIBSPI3[7],MIBSPI3[1] / MibADC2 event / MIBSPI5[6],MIBSPI3[0] / MIBSPI5[7],MIBSPI1[8] / MIBSPI3[8] / DCAN1 IF3 / MibADC2 G1,MIBSPI1[9] / MIBSPI3[9] / DCAN3 IF1 / MibADC2 G2,RTI DMAREQ2 / MIBSPI5[8],RTI DMAREQ3 / MIBSPI5[9],N2HET1 DMAREQ[4] / N2HET2 DMAREQ[4] / DCAN3IF2,N2HET1 DMAREQ[5] / N2HET2 DMAREQ[5] / DCAN3IF3,MIBSPI1[10] / MIBSPI3[10] / MIBSPI5[10],MIBSPI1[11] / MIBSPI3[11] / MIBSPI5[11],N2HET1 DMAREQ[6] / N2HET2 DMAREQ[6] / SPI4 receive / MIBSPI5[12],N2HET1 DMAREQ[7] / N2HET2 DMAREQ[7] / SPI4 transmit / MIBSPI5[13],CRC DMAREQ[0] / MIBSPI1[12] / MIBSPI3[12],CRC DMAREQ[1] / MIBSPI1[13] / MIBSPI3[13],LIN receive / MIBSPI5[14],LIN transmit / MIBSPI5[15],MIBSPI1[14] / MIBSPI3[14] / SCI receive /MIBSPI5[1],MIBSPI1[15] / MIBSPI3[15] / SCI transmit /MIBSPI5[0],?..." textline " " bitfld.long 0x00 0.--5. " CH7ASI ,Channel 7 Assignment" "MIBSPI1[1],MIBSPI1[0],SPI2 receive,SPI2 transmit,MIBSPI1[2] / MIBSPI3[2] / DCAN2 IF3,MIBSPI1[3] / MIBSPI3[3] / DCAN2 IF2,DCAN1 IF2 / MIBSPI5[2],MIBADC1 event / MIBSPI5[3],MIBSPI1[4] / MIBSPI3[4] / DCAN1 IF1,MIBSPI1[5] / MIBSPI3[5] / DCAN2 IF1,MIBADC1 G1 / I2C receive / MIBSPI5[4],MIBADC1 G2 / I2C transmit / MIBSPI5[5],RTI DMAREQ0 / MIBSPI1[6] / MIBSPI3[6],RTI DMAREQ1 / MIBSPI1[7] / MIBSPI3[7],MIBSPI3[1] / MibADC2 event / MIBSPI5[6],MIBSPI3[0] / MIBSPI5[7],MIBSPI1[8] / MIBSPI3[8] / DCAN1 IF3 / MibADC2 G1,MIBSPI1[9] / MIBSPI3[9] / DCAN3 IF1 / MibADC2 G2,RTI DMAREQ2 / MIBSPI5[8],RTI DMAREQ3 / MIBSPI5[9],N2HET1 DMAREQ[4] / N2HET2 DMAREQ[4] / DCAN3IF2,N2HET1 DMAREQ[5] / N2HET2 DMAREQ[5] / DCAN3IF3,MIBSPI1[10] / MIBSPI3[10] / MIBSPI5[10],MIBSPI1[11] / MIBSPI3[11] / MIBSPI5[11],N2HET1 DMAREQ[6] / N2HET2 DMAREQ[6] / SPI4 receive / MIBSPI5[12],N2HET1 DMAREQ[7] / N2HET2 DMAREQ[7] / SPI4 transmit / MIBSPI5[13],CRC DMAREQ[0] / MIBSPI1[12] / MIBSPI3[12],CRC DMAREQ[1] / MIBSPI1[13] / MIBSPI3[13],LIN receive / MIBSPI5[14],LIN transmit / MIBSPI5[15],MIBSPI1[14] / MIBSPI3[14] / SCI receive /MIBSPI5[1],MIBSPI1[15] / MIBSPI3[15] / SCI transmit /MIBSPI5[0],?..." endif group.long 0x5C++0x3 line.long 0x0 "DREQASI2,DMA REQUEST ASSIGNMENT Register 2" sif (cpu()==("RM48L950-ZWT")||cpu()==("RM48L950-PGE")||cpu()==("RM48L750-ZWT")||cpu()==("RM48L750-PGE")||cpu()==("RM48L550-ZWT")||cpu()==("RM48L550-PGE")||cpu()=="RM48L952-PGE"||cpu()=="RM48L952-ZWT"||cpu()==("RM46L852-ZWT")||cpu()==("RM46L852-PGE")||cpu()==("RM46L850-ZWT")||cpu()==("RM46L850-PGE")||cpu()==("RM46L450-ZWT")||cpu()==("RM46L450-PGE")) bitfld.long 0x00 24.--29. " CH8ASI ,Channel 8 Assignment" "MIBSPI1[1],MIBSPI1,SPI2 receive,SPI2 transmit,MIBSPI1[2] / MIBSPI3[2] / DCAN2 IF3,MIBSPI1[3] / MIBSPI3[3] / DCAN2 IF2,DCAN1 IF2 / MIBSPI5[2],MIBADC1 event / MIBSPI5[3],MIBSPI1[4] / MIBSPI3[4] / DCAN1 IF1,MIBSPI1[5] / MIBSPI3[5] / DCAN2 IF1,MIBADC1 G1 / I2C receive / MIBSPI5[4],MIBADC1 G2 / I2C transmit / MIBSPI5[5],RTI DMAREQ0 / MIBSPI1[6] / MIBSPI3[6],RTI DMAREQ1 / MIBSPI1[7] / MIBSPI3[7],MIBSPI3[1](1) / USB_FUNC_DMATXREQ_ON[0] / MibADC2 event / MIBSPI5[6],MIBSPI3[0](2) / USB_FUNC_DMARXREQ_ON[0] /MIBSPI5[7],MIBSPI1[8] / MIBSPI3[8] / DCAN1 IF3 / MibADC2 G1,MIBSPI1[9] / MIBSPI3[9] / DCAN3 IF1 / MibADC2 G2,RTI DMAREQ2 / USB_FUNC_DMATXREQ_ON[1] /MIBSPI5[8],RTI DMAREQ3 / USB_FUNC_DMARXREQ_ON[1] /MIBSPI5[9],N2HET1 DMAREQ[4] / N2HET2 DMAREQ[4] / DCAN3 IF2,N2HET1 DMAREQ[5] / N2HET2 DMAREQ[5] / DCAN3 IF3,MIBSPI1[10] / MIBSPI3[10] / MIBSPI5[10],MIBSPI1[11] / MIBSPI3[11] / MIBSPI5[11],N2HET1 DMAREQ[6] / N2HET2 DMAREQ[6] / SPI4 receive / MIBSPI5[12],N2HET1 DMAREQ[7] / N2HET2 DMAREQ[7] / SPI4 transmit / MIBSPI5[13],CRC DMAREQ[0] / MIBSPI1[12] / MIBSPI3[12],CRC DMAREQ[1] / MIBSPI1[13] / MIBSPI3[13],LIN receive / USB_FUNC_DMATXREQ_ON[2] / MIBSPI5[14],LIN transmit / USB_FUNC_DMARXREQ_ON[2] / MIBSPI5[15],MIBSPI1[14] / MIBSPI3[14] / SCI receive /MIBSPI5[1],MIBSPI1[15] / MIBSPI3[15] / SCI transmit /MIBSPI5[0],?..." textline " " bitfld.long 0x00 16.--21. " CH9ASI ,Channel 9 Assignment" "MIBSPI1[1],MIBSPI1,SPI2 receive,SPI2 transmit,MIBSPI1[2] / MIBSPI3[2] / DCAN2 IF3,MIBSPI1[3] / MIBSPI3[3] / DCAN2 IF2,DCAN1 IF2 / MIBSPI5[2],MIBADC1 event / MIBSPI5[3],MIBSPI1[4] / MIBSPI3[4] / DCAN1 IF1,MIBSPI1[5] / MIBSPI3[5] / DCAN2 IF1,MIBADC1 G1 / I2C receive / MIBSPI5[4],MIBADC1 G2 / I2C transmit / MIBSPI5[5],RTI DMAREQ0 / MIBSPI1[6] / MIBSPI3[6],RTI DMAREQ1 / MIBSPI1[7] / MIBSPI3[7],MIBSPI3[1](1) / USB_FUNC_DMATXREQ_ON[0] / MibADC2 event / MIBSPI5[6],MIBSPI3[0](2) / USB_FUNC_DMARXREQ_ON[0] /MIBSPI5[7],MIBSPI1[8] / MIBSPI3[8] / DCAN1 IF3 / MibADC2 G1,MIBSPI1[9] / MIBSPI3[9] / DCAN3 IF1 / MibADC2 G2,RTI DMAREQ2 / USB_FUNC_DMATXREQ_ON[1] /MIBSPI5[8],RTI DMAREQ3 / USB_FUNC_DMARXREQ_ON[1] /MIBSPI5[9],N2HET1 DMAREQ[4] / N2HET2 DMAREQ[4] / DCAN3 IF2,N2HET1 DMAREQ[5] / N2HET2 DMAREQ[5] / DCAN3 IF3,MIBSPI1[10] / MIBSPI3[10] / MIBSPI5[10],MIBSPI1[11] / MIBSPI3[11] / MIBSPI5[11],N2HET1 DMAREQ[6] / N2HET2 DMAREQ[6] / SPI4 receive / MIBSPI5[12],N2HET1 DMAREQ[7] / N2HET2 DMAREQ[7] / SPI4 transmit / MIBSPI5[13],CRC DMAREQ[0] / MIBSPI1[12] / MIBSPI3[12],CRC DMAREQ[1] / MIBSPI1[13] / MIBSPI3[13],LIN receive / USB_FUNC_DMATXREQ_ON[2] / MIBSPI5[14],LIN transmit / USB_FUNC_DMARXREQ_ON[2] / MIBSPI5[15],MIBSPI1[14] / MIBSPI3[14] / SCI receive /MIBSPI5[1],MIBSPI1[15] / MIBSPI3[15] / SCI transmit /MIBSPI5[0],?..." textline " " bitfld.long 0x00 8.--13. " CH10ASI ,Channel 10 Assignment" "MIBSPI1[1],MIBSPI1,SPI2 receive,SPI2 transmit,MIBSPI1[2] / MIBSPI3[2] / DCAN2 IF3,MIBSPI1[3] / MIBSPI3[3] / DCAN2 IF2,DCAN1 IF2 / MIBSPI5[2],MIBADC1 event / MIBSPI5[3],MIBSPI1[4] / MIBSPI3[4] / DCAN1 IF1,MIBSPI1[5] / MIBSPI3[5] / DCAN2 IF1,MIBADC1 G1 / I2C receive / MIBSPI5[4],MIBADC1 G2 / I2C transmit / MIBSPI5[5],RTI DMAREQ0 / MIBSPI1[6] / MIBSPI3[6],RTI DMAREQ1 / MIBSPI1[7] / MIBSPI3[7],MIBSPI3[1](1) / USB_FUNC_DMATXREQ_ON[0] / MibADC2 event / MIBSPI5[6],MIBSPI3[0](2) / USB_FUNC_DMARXREQ_ON[0] /MIBSPI5[7],MIBSPI1[8] / MIBSPI3[8] / DCAN1 IF3 / MibADC2 G1,MIBSPI1[9] / MIBSPI3[9] / DCAN3 IF1 / MibADC2 G2,RTI DMAREQ2 / USB_FUNC_DMATXREQ_ON[1] /MIBSPI5[8],RTI DMAREQ3 / USB_FUNC_DMARXREQ_ON[1] /MIBSPI5[9],N2HET1 DMAREQ[4] / N2HET2 DMAREQ[4] / DCAN3 IF2,N2HET1 DMAREQ[5] / N2HET2 DMAREQ[5] / DCAN3 IF3,MIBSPI1[10] / MIBSPI3[10] / MIBSPI5[10],MIBSPI1[11] / MIBSPI3[11] / MIBSPI5[11],N2HET1 DMAREQ[6] / N2HET2 DMAREQ[6] / SPI4 receive / MIBSPI5[12],N2HET1 DMAREQ[7] / N2HET2 DMAREQ[7] / SPI4 transmit / MIBSPI5[13],CRC DMAREQ[0] / MIBSPI1[12] / MIBSPI3[12],CRC DMAREQ[1] / MIBSPI1[13] / MIBSPI3[13],LIN receive / USB_FUNC_DMATXREQ_ON[2] / MIBSPI5[14],LIN transmit / USB_FUNC_DMARXREQ_ON[2] / MIBSPI5[15],MIBSPI1[14] / MIBSPI3[14] / SCI receive /MIBSPI5[1],MIBSPI1[15] / MIBSPI3[15] / SCI transmit /MIBSPI5[0],?..." textline " " bitfld.long 0x00 0.--5. " CH11ASI ,Channel 11 Assignment" "MIBSPI1[1],MIBSPI1,SPI2 receive,SPI2 transmit,MIBSPI1[2] / MIBSPI3[2] / DCAN2 IF3,MIBSPI1[3] / MIBSPI3[3] / DCAN2 IF2,DCAN1 IF2 / MIBSPI5[2],MIBADC1 event / MIBSPI5[3],MIBSPI1[4] / MIBSPI3[4] / DCAN1 IF1,MIBSPI1[5] / MIBSPI3[5] / DCAN2 IF1,MIBADC1 G1 / I2C receive / MIBSPI5[4],MIBADC1 G2 / I2C transmit / MIBSPI5[5],RTI DMAREQ0 / MIBSPI1[6] / MIBSPI3[6],RTI DMAREQ1 / MIBSPI1[7] / MIBSPI3[7],MIBSPI3[1](1) / USB_FUNC_DMATXREQ_ON[0] / MibADC2 event / MIBSPI5[6],MIBSPI3[0](2) / USB_FUNC_DMARXREQ_ON[0] /MIBSPI5[7],MIBSPI1[8] / MIBSPI3[8] / DCAN1 IF3 / MibADC2 G1,MIBSPI1[9] / MIBSPI3[9] / DCAN3 IF1 / MibADC2 G2,RTI DMAREQ2 / USB_FUNC_DMATXREQ_ON[1] /MIBSPI5[8],RTI DMAREQ3 / USB_FUNC_DMARXREQ_ON[1] /MIBSPI5[9],N2HET1 DMAREQ[4] / N2HET2 DMAREQ[4] / DCAN3 IF2,N2HET1 DMAREQ[5] / N2HET2 DMAREQ[5] / DCAN3 IF3,MIBSPI1[10] / MIBSPI3[10] / MIBSPI5[10],MIBSPI1[11] / MIBSPI3[11] / MIBSPI5[11],N2HET1 DMAREQ[6] / N2HET2 DMAREQ[6] / SPI4 receive / MIBSPI5[12],N2HET1 DMAREQ[7] / N2HET2 DMAREQ[7] / SPI4 transmit / MIBSPI5[13],CRC DMAREQ[0] / MIBSPI1[12] / MIBSPI3[12],CRC DMAREQ[1] / MIBSPI1[13] / MIBSPI3[13],LIN receive / USB_FUNC_DMATXREQ_ON[2] / MIBSPI5[14],LIN transmit / USB_FUNC_DMARXREQ_ON[2] / MIBSPI5[15],MIBSPI1[14] / MIBSPI3[14] / SCI receive /MIBSPI5[1],MIBSPI1[15] / MIBSPI3[15] / SCI transmit /MIBSPI5[0],?..." else bitfld.long 0x00 24.--29. " CH8ASI ,Channel 8 Assignment" "MIBSPI1[1],MIBSPI1[0],SPI2 receive,SPI2 transmit,MIBSPI1[2] / MIBSPI3[2] / DCAN2 IF3,MIBSPI1[3] / MIBSPI3[3] / DCAN2 IF2,DCAN1 IF2 / MIBSPI5[2],MIBADC1 event / MIBSPI5[3],MIBSPI1[4] / MIBSPI3[4] / DCAN1 IF1,MIBSPI1[5] / MIBSPI3[5] / DCAN2 IF1,MIBADC1 G1 / I2C receive / MIBSPI5[4],MIBADC1 G2 / I2C transmit / MIBSPI5[5],RTI DMAREQ0 / MIBSPI1[6] / MIBSPI3[6],RTI DMAREQ1 / MIBSPI1[7] / MIBSPI3[7],MIBSPI3[1] / MibADC2 event / MIBSPI5[6],MIBSPI3[0] / MIBSPI5[7],MIBSPI1[8] / MIBSPI3[8] / DCAN1 IF3 / MibADC2 G1,MIBSPI1[9] / MIBSPI3[9] / DCAN3 IF1 / MibADC2 G2,RTI DMAREQ2 / MIBSPI5[8],RTI DMAREQ3 / MIBSPI5[9],N2HET1 DMAREQ[4] / N2HET2 DMAREQ[4] / DCAN3IF2,N2HET1 DMAREQ[5] / N2HET2 DMAREQ[5] / DCAN3IF3,MIBSPI1[10] / MIBSPI3[10] / MIBSPI5[10],MIBSPI1[11] / MIBSPI3[11] / MIBSPI5[11],N2HET1 DMAREQ[6] / N2HET2 DMAREQ[6] / SPI4 receive / MIBSPI5[12],N2HET1 DMAREQ[7] / N2HET2 DMAREQ[7] / SPI4 transmit / MIBSPI5[13],CRC DMAREQ[0] / MIBSPI1[12] / MIBSPI3[12],CRC DMAREQ[1] / MIBSPI1[13] / MIBSPI3[13],LIN receive / MIBSPI5[14],LIN transmit / MIBSPI5[15],MIBSPI1[14] / MIBSPI3[14] / SCI receive /MIBSPI5[1],MIBSPI1[15] / MIBSPI3[15] / SCI transmit /MIBSPI5[0],?..." textline " " bitfld.long 0x00 16.--21. " CH9ASI ,Channel 9 Assignment" "MIBSPI1[1],MIBSPI1[0],SPI2 receive,SPI2 transmit,MIBSPI1[2] / MIBSPI3[2] / DCAN2 IF3,MIBSPI1[3] / MIBSPI3[3] / DCAN2 IF2,DCAN1 IF2 / MIBSPI5[2],MIBADC1 event / MIBSPI5[3],MIBSPI1[4] / MIBSPI3[4] / DCAN1 IF1,MIBSPI1[5] / MIBSPI3[5] / DCAN2 IF1,MIBADC1 G1 / I2C receive / MIBSPI5[4],MIBADC1 G2 / I2C transmit / MIBSPI5[5],RTI DMAREQ0 / MIBSPI1[6] / MIBSPI3[6],RTI DMAREQ1 / MIBSPI1[7] / MIBSPI3[7],MIBSPI3[1] / MibADC2 event / MIBSPI5[6],MIBSPI3[0] / MIBSPI5[7],MIBSPI1[8] / MIBSPI3[8] / DCAN1 IF3 / MibADC2 G1,MIBSPI1[9] / MIBSPI3[9] / DCAN3 IF1 / MibADC2 G2,RTI DMAREQ2 / MIBSPI5[8],RTI DMAREQ3 / MIBSPI5[9],N2HET1 DMAREQ[4] / N2HET2 DMAREQ[4] / DCAN3IF2,N2HET1 DMAREQ[5] / N2HET2 DMAREQ[5] / DCAN3IF3,MIBSPI1[10] / MIBSPI3[10] / MIBSPI5[10],MIBSPI1[11] / MIBSPI3[11] / MIBSPI5[11],N2HET1 DMAREQ[6] / N2HET2 DMAREQ[6] / SPI4 receive / MIBSPI5[12],N2HET1 DMAREQ[7] / N2HET2 DMAREQ[7] / SPI4 transmit / MIBSPI5[13],CRC DMAREQ[0] / MIBSPI1[12] / MIBSPI3[12],CRC DMAREQ[1] / MIBSPI1[13] / MIBSPI3[13],LIN receive / MIBSPI5[14],LIN transmit / MIBSPI5[15],MIBSPI1[14] / MIBSPI3[14] / SCI receive /MIBSPI5[1],MIBSPI1[15] / MIBSPI3[15] / SCI transmit /MIBSPI5[0],?..." textline " " bitfld.long 0x00 8.--13. " CH10ASI ,Channel 10 Assignment" "MIBSPI1[1],MIBSPI1[0],SPI2 receive,SPI2 transmit,MIBSPI1[2] / MIBSPI3[2] / DCAN2 IF3,MIBSPI1[3] / MIBSPI3[3] / DCAN2 IF2,DCAN1 IF2 / MIBSPI5[2],MIBADC1 event / MIBSPI5[3],MIBSPI1[4] / MIBSPI3[4] / DCAN1 IF1,MIBSPI1[5] / MIBSPI3[5] / DCAN2 IF1,MIBADC1 G1 / I2C receive / MIBSPI5[4],MIBADC1 G2 / I2C transmit / MIBSPI5[5],RTI DMAREQ0 / MIBSPI1[6] / MIBSPI3[6],RTI DMAREQ1 / MIBSPI1[7] / MIBSPI3[7],MIBSPI3[1] / MibADC2 event / MIBSPI5[6],MIBSPI3[0] / MIBSPI5[7],MIBSPI1[8] / MIBSPI3[8] / DCAN1 IF3 / MibADC2 G1,MIBSPI1[9] / MIBSPI3[9] / DCAN3 IF1 / MibADC2 G2,RTI DMAREQ2 / MIBSPI5[8],RTI DMAREQ3 / MIBSPI5[9],N2HET1 DMAREQ[4] / N2HET2 DMAREQ[4] / DCAN3IF2,N2HET1 DMAREQ[5] / N2HET2 DMAREQ[5] / DCAN3IF3,MIBSPI1[10] / MIBSPI3[10] / MIBSPI5[10],MIBSPI1[11] / MIBSPI3[11] / MIBSPI5[11],N2HET1 DMAREQ[6] / N2HET2 DMAREQ[6] / SPI4 receive / MIBSPI5[12],N2HET1 DMAREQ[7] / N2HET2 DMAREQ[7] / SPI4 transmit / MIBSPI5[13],CRC DMAREQ[0] / MIBSPI1[12] / MIBSPI3[12],CRC DMAREQ[1] / MIBSPI1[13] / MIBSPI3[13],LIN receive / MIBSPI5[14],LIN transmit / MIBSPI5[15],MIBSPI1[14] / MIBSPI3[14] / SCI receive /MIBSPI5[1],MIBSPI1[15] / MIBSPI3[15] / SCI transmit /MIBSPI5[0],?..." textline " " bitfld.long 0x00 0.--5. " CH11ASI ,Channel 11 Assignment" "MIBSPI1[1],MIBSPI1[0],SPI2 receive,SPI2 transmit,MIBSPI1[2] / MIBSPI3[2] / DCAN2 IF3,MIBSPI1[3] / MIBSPI3[3] / DCAN2 IF2,DCAN1 IF2 / MIBSPI5[2],MIBADC1 event / MIBSPI5[3],MIBSPI1[4] / MIBSPI3[4] / DCAN1 IF1,MIBSPI1[5] / MIBSPI3[5] / DCAN2 IF1,MIBADC1 G1 / I2C receive / MIBSPI5[4],MIBADC1 G2 / I2C transmit / MIBSPI5[5],RTI DMAREQ0 / MIBSPI1[6] / MIBSPI3[6],RTI DMAREQ1 / MIBSPI1[7] / MIBSPI3[7],MIBSPI3[1] / MibADC2 event / MIBSPI5[6],MIBSPI3[0] / MIBSPI5[7],MIBSPI1[8] / MIBSPI3[8] / DCAN1 IF3 / MibADC2 G1,MIBSPI1[9] / MIBSPI3[9] / DCAN3 IF1 / MibADC2 G2,RTI DMAREQ2 / MIBSPI5[8],RTI DMAREQ3 / MIBSPI5[9],N2HET1 DMAREQ[4] / N2HET2 DMAREQ[4] / DCAN3IF2,N2HET1 DMAREQ[5] / N2HET2 DMAREQ[5] / DCAN3IF3,MIBSPI1[10] / MIBSPI3[10] / MIBSPI5[10],MIBSPI1[11] / MIBSPI3[11] / MIBSPI5[11],N2HET1 DMAREQ[6] / N2HET2 DMAREQ[6] / SPI4 receive / MIBSPI5[12],N2HET1 DMAREQ[7] / N2HET2 DMAREQ[7] / SPI4 transmit / MIBSPI5[13],CRC DMAREQ[0] / MIBSPI1[12] / MIBSPI3[12],CRC DMAREQ[1] / MIBSPI1[13] / MIBSPI3[13],LIN receive / MIBSPI5[14],LIN transmit / MIBSPI5[15],MIBSPI1[14] / MIBSPI3[14] / SCI receive /MIBSPI5[1],MIBSPI1[15] / MIBSPI3[15] / SCI transmit /MIBSPI5[0],?..." endif group.long 0x60++0x3 line.long 0x0 "DREQASI3,DMA REQUEST ASSIGNMENT Register 3" sif (cpu()==("RM48L950-ZWT")||cpu()==("RM48L950-PGE")||cpu()==("RM48L750-ZWT")||cpu()==("RM48L750-PGE")||cpu()==("RM48L550-ZWT")||cpu()==("RM48L550-PGE")||cpu()=="RM48L952-PGE"||cpu()=="RM48L952-ZWT"||cpu()==("RM46L852-ZWT")||cpu()==("RM46L852-PGE")||cpu()==("RM46L850-ZWT")||cpu()==("RM46L850-PGE")||cpu()==("RM46L450-ZWT")||cpu()==("RM46L450-PGE")) bitfld.long 0x00 24.--29. " CH12ASI ,Channel 12 Assignment" "MIBSPI1[1],MIBSPI1,SPI2 receive,SPI2 transmit,MIBSPI1[2] / MIBSPI3[2] / DCAN2 IF3,MIBSPI1[3] / MIBSPI3[3] / DCAN2 IF2,DCAN1 IF2 / MIBSPI5[2],MIBADC1 event / MIBSPI5[3],MIBSPI1[4] / MIBSPI3[4] / DCAN1 IF1,MIBSPI1[5] / MIBSPI3[5] / DCAN2 IF1,MIBADC1 G1 / I2C receive / MIBSPI5[4],MIBADC1 G2 / I2C transmit / MIBSPI5[5],RTI DMAREQ0 / MIBSPI1[6] / MIBSPI3[6],RTI DMAREQ1 / MIBSPI1[7] / MIBSPI3[7],MIBSPI3[1](1) / USB_FUNC_DMATXREQ_ON[0] / MibADC2 event / MIBSPI5[6],MIBSPI3[0](2) / USB_FUNC_DMARXREQ_ON[0] /MIBSPI5[7],MIBSPI1[8] / MIBSPI3[8] / DCAN1 IF3 / MibADC2 G1,MIBSPI1[9] / MIBSPI3[9] / DCAN3 IF1 / MibADC2 G2,RTI DMAREQ2 / USB_FUNC_DMATXREQ_ON[1] /MIBSPI5[8],RTI DMAREQ3 / USB_FUNC_DMARXREQ_ON[1] /MIBSPI5[9],N2HET1 DMAREQ[4] / N2HET2 DMAREQ[4] / DCAN3 IF2,N2HET1 DMAREQ[5] / N2HET2 DMAREQ[5] / DCAN3 IF3,MIBSPI1[10] / MIBSPI3[10] / MIBSPI5[10],MIBSPI1[11] / MIBSPI3[11] / MIBSPI5[11],N2HET1 DMAREQ[6] / N2HET2 DMAREQ[6] / SPI4 receive / MIBSPI5[12],N2HET1 DMAREQ[7] / N2HET2 DMAREQ[7] / SPI4 transmit / MIBSPI5[13],CRC DMAREQ[0] / MIBSPI1[12] / MIBSPI3[12],CRC DMAREQ[1] / MIBSPI1[13] / MIBSPI3[13],LIN receive / USB_FUNC_DMATXREQ_ON[2] / MIBSPI5[14],LIN transmit / USB_FUNC_DMARXREQ_ON[2] / MIBSPI5[15],MIBSPI1[14] / MIBSPI3[14] / SCI receive /MIBSPI5[1],MIBSPI1[15] / MIBSPI3[15] / SCI transmit /MIBSPI5[0],?..." textline " " bitfld.long 0x00 16.--21. " CH13ASI ,Channel 13 Assignment" "MIBSPI1[1],MIBSPI1,SPI2 receive,SPI2 transmit,MIBSPI1[2] / MIBSPI3[2] / DCAN2 IF3,MIBSPI1[3] / MIBSPI3[3] / DCAN2 IF2,DCAN1 IF2 / MIBSPI5[2],MIBADC1 event / MIBSPI5[3],MIBSPI1[4] / MIBSPI3[4] / DCAN1 IF1,MIBSPI1[5] / MIBSPI3[5] / DCAN2 IF1,MIBADC1 G1 / I2C receive / MIBSPI5[4],MIBADC1 G2 / I2C transmit / MIBSPI5[5],RTI DMAREQ0 / MIBSPI1[6] / MIBSPI3[6],RTI DMAREQ1 / MIBSPI1[7] / MIBSPI3[7],MIBSPI3[1](1) / USB_FUNC_DMATXREQ_ON[0] / MibADC2 event / MIBSPI5[6],MIBSPI3[0](2) / USB_FUNC_DMARXREQ_ON[0] /MIBSPI5[7],MIBSPI1[8] / MIBSPI3[8] / DCAN1 IF3 / MibADC2 G1,MIBSPI1[9] / MIBSPI3[9] / DCAN3 IF1 / MibADC2 G2,RTI DMAREQ2 / USB_FUNC_DMATXREQ_ON[1] /MIBSPI5[8],RTI DMAREQ3 / USB_FUNC_DMARXREQ_ON[1] /MIBSPI5[9],N2HET1 DMAREQ[4] / N2HET2 DMAREQ[4] / DCAN3 IF2,N2HET1 DMAREQ[5] / N2HET2 DMAREQ[5] / DCAN3 IF3,MIBSPI1[10] / MIBSPI3[10] / MIBSPI5[10],MIBSPI1[11] / MIBSPI3[11] / MIBSPI5[11],N2HET1 DMAREQ[6] / N2HET2 DMAREQ[6] / SPI4 receive / MIBSPI5[12],N2HET1 DMAREQ[7] / N2HET2 DMAREQ[7] / SPI4 transmit / MIBSPI5[13],CRC DMAREQ[0] / MIBSPI1[12] / MIBSPI3[12],CRC DMAREQ[1] / MIBSPI1[13] / MIBSPI3[13],LIN receive / USB_FUNC_DMATXREQ_ON[2] / MIBSPI5[14],LIN transmit / USB_FUNC_DMARXREQ_ON[2] / MIBSPI5[15],MIBSPI1[14] / MIBSPI3[14] / SCI receive /MIBSPI5[1],MIBSPI1[15] / MIBSPI3[15] / SCI transmit /MIBSPI5[0],?..." textline " " bitfld.long 0x00 8.--13. " CH14ASI ,Channel 14 Assignment" "MIBSPI1[1],MIBSPI1,SPI2 receive,SPI2 transmit,MIBSPI1[2] / MIBSPI3[2] / DCAN2 IF3,MIBSPI1[3] / MIBSPI3[3] / DCAN2 IF2,DCAN1 IF2 / MIBSPI5[2],MIBADC1 event / MIBSPI5[3],MIBSPI1[4] / MIBSPI3[4] / DCAN1 IF1,MIBSPI1[5] / MIBSPI3[5] / DCAN2 IF1,MIBADC1 G1 / I2C receive / MIBSPI5[4],MIBADC1 G2 / I2C transmit / MIBSPI5[5],RTI DMAREQ0 / MIBSPI1[6] / MIBSPI3[6],RTI DMAREQ1 / MIBSPI1[7] / MIBSPI3[7],MIBSPI3[1](1) / USB_FUNC_DMATXREQ_ON[0] / MibADC2 event / MIBSPI5[6],MIBSPI3[0](2) / USB_FUNC_DMARXREQ_ON[0] /MIBSPI5[7],MIBSPI1[8] / MIBSPI3[8] / DCAN1 IF3 / MibADC2 G1,MIBSPI1[9] / MIBSPI3[9] / DCAN3 IF1 / MibADC2 G2,RTI DMAREQ2 / USB_FUNC_DMATXREQ_ON[1] /MIBSPI5[8],RTI DMAREQ3 / USB_FUNC_DMARXREQ_ON[1] /MIBSPI5[9],N2HET1 DMAREQ[4] / N2HET2 DMAREQ[4] / DCAN3 IF2,N2HET1 DMAREQ[5] / N2HET2 DMAREQ[5] / DCAN3 IF3,MIBSPI1[10] / MIBSPI3[10] / MIBSPI5[10],MIBSPI1[11] / MIBSPI3[11] / MIBSPI5[11],N2HET1 DMAREQ[6] / N2HET2 DMAREQ[6] / SPI4 receive / MIBSPI5[12],N2HET1 DMAREQ[7] / N2HET2 DMAREQ[7] / SPI4 transmit / MIBSPI5[13],CRC DMAREQ[0] / MIBSPI1[12] / MIBSPI3[12],CRC DMAREQ[1] / MIBSPI1[13] / MIBSPI3[13],LIN receive / USB_FUNC_DMATXREQ_ON[2] / MIBSPI5[14],LIN transmit / USB_FUNC_DMARXREQ_ON[2] / MIBSPI5[15],MIBSPI1[14] / MIBSPI3[14] / SCI receive /MIBSPI5[1],MIBSPI1[15] / MIBSPI3[15] / SCI transmit /MIBSPI5[0],?..." textline " " bitfld.long 0x00 0.--5. " CH15ASI ,Channel 15 Assignment" "MIBSPI1[1],MIBSPI1,SPI2 receive,SPI2 transmit,MIBSPI1[2] / MIBSPI3[2] / DCAN2 IF3,MIBSPI1[3] / MIBSPI3[3] / DCAN2 IF2,DCAN1 IF2 / MIBSPI5[2],MIBADC1 event / MIBSPI5[3],MIBSPI1[4] / MIBSPI3[4] / DCAN1 IF1,MIBSPI1[5] / MIBSPI3[5] / DCAN2 IF1,MIBADC1 G1 / I2C receive / MIBSPI5[4],MIBADC1 G2 / I2C transmit / MIBSPI5[5],RTI DMAREQ0 / MIBSPI1[6] / MIBSPI3[6],RTI DMAREQ1 / MIBSPI1[7] / MIBSPI3[7],MIBSPI3[1](1) / USB_FUNC_DMATXREQ_ON[0] / MibADC2 event / MIBSPI5[6],MIBSPI3[0](2) / USB_FUNC_DMARXREQ_ON[0] /MIBSPI5[7],MIBSPI1[8] / MIBSPI3[8] / DCAN1 IF3 / MibADC2 G1,MIBSPI1[9] / MIBSPI3[9] / DCAN3 IF1 / MibADC2 G2,RTI DMAREQ2 / USB_FUNC_DMATXREQ_ON[1] /MIBSPI5[8],RTI DMAREQ3 / USB_FUNC_DMARXREQ_ON[1] /MIBSPI5[9],N2HET1 DMAREQ[4] / N2HET2 DMAREQ[4] / DCAN3 IF2,N2HET1 DMAREQ[5] / N2HET2 DMAREQ[5] / DCAN3 IF3,MIBSPI1[10] / MIBSPI3[10] / MIBSPI5[10],MIBSPI1[11] / MIBSPI3[11] / MIBSPI5[11],N2HET1 DMAREQ[6] / N2HET2 DMAREQ[6] / SPI4 receive / MIBSPI5[12],N2HET1 DMAREQ[7] / N2HET2 DMAREQ[7] / SPI4 transmit / MIBSPI5[13],CRC DMAREQ[0] / MIBSPI1[12] / MIBSPI3[12],CRC DMAREQ[1] / MIBSPI1[13] / MIBSPI3[13],LIN receive / USB_FUNC_DMATXREQ_ON[2] / MIBSPI5[14],LIN transmit / USB_FUNC_DMARXREQ_ON[2] / MIBSPI5[15],MIBSPI1[14] / MIBSPI3[14] / SCI receive /MIBSPI5[1],MIBSPI1[15] / MIBSPI3[15] / SCI transmit /MIBSPI5[0],?..." else bitfld.long 0x00 24.--29. " CH12ASI ,Channel 12 Assignment" "MIBSPI1[1],MIBSPI1[0],SPI2 receive,SPI2 transmit,MIBSPI1[2] / MIBSPI3[2] / DCAN2 IF3,MIBSPI1[3] / MIBSPI3[3] / DCAN2 IF2,DCAN1 IF2 / MIBSPI5[2],MIBADC1 event / MIBSPI5[3],MIBSPI1[4] / MIBSPI3[4] / DCAN1 IF1,MIBSPI1[5] / MIBSPI3[5] / DCAN2 IF1,MIBADC1 G1 / I2C receive / MIBSPI5[4],MIBADC1 G2 / I2C transmit / MIBSPI5[5],RTI DMAREQ0 / MIBSPI1[6] / MIBSPI3[6],RTI DMAREQ1 / MIBSPI1[7] / MIBSPI3[7],MIBSPI3[1] / MibADC2 event / MIBSPI5[6],MIBSPI3[0] / MIBSPI5[7],MIBSPI1[8] / MIBSPI3[8] / DCAN1 IF3 / MibADC2 G1,MIBSPI1[9] / MIBSPI3[9] / DCAN3 IF1 / MibADC2 G2,RTI DMAREQ2 / MIBSPI5[8],RTI DMAREQ3 / MIBSPI5[9],N2HET1 DMAREQ[4] / N2HET2 DMAREQ[4] / DCAN3IF2,N2HET1 DMAREQ[5] / N2HET2 DMAREQ[5] / DCAN3IF3,MIBSPI1[10] / MIBSPI3[10] / MIBSPI5[10],MIBSPI1[11] / MIBSPI3[11] / MIBSPI5[11],N2HET1 DMAREQ[6] / N2HET2 DMAREQ[6] / SPI4 receive / MIBSPI5[12],N2HET1 DMAREQ[7] / N2HET2 DMAREQ[7] / SPI4 transmit / MIBSPI5[13],CRC DMAREQ[0] / MIBSPI1[12] / MIBSPI3[12],CRC DMAREQ[1] / MIBSPI1[13] / MIBSPI3[13],LIN receive / MIBSPI5[14],LIN transmit / MIBSPI5[15],MIBSPI1[14] / MIBSPI3[14] / SCI receive /MIBSPI5[1],MIBSPI1[15] / MIBSPI3[15] / SCI transmit /MIBSPI5[0],?..." textline " " bitfld.long 0x00 16.--21. " CH13ASI ,Channel 13 Assignment" "MIBSPI1[1],MIBSPI1[0],SPI2 receive,SPI2 transmit,MIBSPI1[2] / MIBSPI3[2] / DCAN2 IF3,MIBSPI1[3] / MIBSPI3[3] / DCAN2 IF2,DCAN1 IF2 / MIBSPI5[2],MIBADC1 event / MIBSPI5[3],MIBSPI1[4] / MIBSPI3[4] / DCAN1 IF1,MIBSPI1[5] / MIBSPI3[5] / DCAN2 IF1,MIBADC1 G1 / I2C receive / MIBSPI5[4],MIBADC1 G2 / I2C transmit / MIBSPI5[5],RTI DMAREQ0 / MIBSPI1[6] / MIBSPI3[6],RTI DMAREQ1 / MIBSPI1[7] / MIBSPI3[7],MIBSPI3[1] / MibADC2 event / MIBSPI5[6],MIBSPI3[0] / MIBSPI5[7],MIBSPI1[8] / MIBSPI3[8] / DCAN1 IF3 / MibADC2 G1,MIBSPI1[9] / MIBSPI3[9] / DCAN3 IF1 / MibADC2 G2,RTI DMAREQ2 / MIBSPI5[8],RTI DMAREQ3 / MIBSPI5[9],N2HET1 DMAREQ[4] / N2HET2 DMAREQ[4] / DCAN3IF2,N2HET1 DMAREQ[5] / N2HET2 DMAREQ[5] / DCAN3IF3,MIBSPI1[10] / MIBSPI3[10] / MIBSPI5[10],MIBSPI1[11] / MIBSPI3[11] / MIBSPI5[11],N2HET1 DMAREQ[6] / N2HET2 DMAREQ[6] / SPI4 receive / MIBSPI5[12],N2HET1 DMAREQ[7] / N2HET2 DMAREQ[7] / SPI4 transmit / MIBSPI5[13],CRC DMAREQ[0] / MIBSPI1[12] / MIBSPI3[12],CRC DMAREQ[1] / MIBSPI1[13] / MIBSPI3[13],LIN receive / MIBSPI5[14],LIN transmit / MIBSPI5[15],MIBSPI1[14] / MIBSPI3[14] / SCI receive /MIBSPI5[1],MIBSPI1[15] / MIBSPI3[15] / SCI transmit /MIBSPI5[0],?..." textline " " bitfld.long 0x00 8.--13. " CH14ASI ,Channel 14 Assignment" "MIBSPI1[1],MIBSPI1[0],SPI2 receive,SPI2 transmit,MIBSPI1[2] / MIBSPI3[2] / DCAN2 IF3,MIBSPI1[3] / MIBSPI3[3] / DCAN2 IF2,DCAN1 IF2 / MIBSPI5[2],MIBADC1 event / MIBSPI5[3],MIBSPI1[4] / MIBSPI3[4] / DCAN1 IF1,MIBSPI1[5] / MIBSPI3[5] / DCAN2 IF1,MIBADC1 G1 / I2C receive / MIBSPI5[4],MIBADC1 G2 / I2C transmit / MIBSPI5[5],RTI DMAREQ0 / MIBSPI1[6] / MIBSPI3[6],RTI DMAREQ1 / MIBSPI1[7] / MIBSPI3[7],MIBSPI3[1] / MibADC2 event / MIBSPI5[6],MIBSPI3[0] / MIBSPI5[7],MIBSPI1[8] / MIBSPI3[8] / DCAN1 IF3 / MibADC2 G1,MIBSPI1[9] / MIBSPI3[9] / DCAN3 IF1 / MibADC2 G2,RTI DMAREQ2 / MIBSPI5[8],RTI DMAREQ3 / MIBSPI5[9],N2HET1 DMAREQ[4] / N2HET2 DMAREQ[4] / DCAN3IF2,N2HET1 DMAREQ[5] / N2HET2 DMAREQ[5] / DCAN3IF3,MIBSPI1[10] / MIBSPI3[10] / MIBSPI5[10],MIBSPI1[11] / MIBSPI3[11] / MIBSPI5[11],N2HET1 DMAREQ[6] / N2HET2 DMAREQ[6] / SPI4 receive / MIBSPI5[12],N2HET1 DMAREQ[7] / N2HET2 DMAREQ[7] / SPI4 transmit / MIBSPI5[13],CRC DMAREQ[0] / MIBSPI1[12] / MIBSPI3[12],CRC DMAREQ[1] / MIBSPI1[13] / MIBSPI3[13],LIN receive / MIBSPI5[14],LIN transmit / MIBSPI5[15],MIBSPI1[14] / MIBSPI3[14] / SCI receive /MIBSPI5[1],MIBSPI1[15] / MIBSPI3[15] / SCI transmit /MIBSPI5[0],?..." textline " " bitfld.long 0x00 0.--5. " CH15ASI ,Channel 15 Assignment" "MIBSPI1[1],MIBSPI1[0],SPI2 receive,SPI2 transmit,MIBSPI1[2] / MIBSPI3[2] / DCAN2 IF3,MIBSPI1[3] / MIBSPI3[3] / DCAN2 IF2,DCAN1 IF2 / MIBSPI5[2],MIBADC1 event / MIBSPI5[3],MIBSPI1[4] / MIBSPI3[4] / DCAN1 IF1,MIBSPI1[5] / MIBSPI3[5] / DCAN2 IF1,MIBADC1 G1 / I2C receive / MIBSPI5[4],MIBADC1 G2 / I2C transmit / MIBSPI5[5],RTI DMAREQ0 / MIBSPI1[6] / MIBSPI3[6],RTI DMAREQ1 / MIBSPI1[7] / MIBSPI3[7],MIBSPI3[1] / MibADC2 event / MIBSPI5[6],MIBSPI3[0] / MIBSPI5[7],MIBSPI1[8] / MIBSPI3[8] / DCAN1 IF3 / MibADC2 G1,MIBSPI1[9] / MIBSPI3[9] / DCAN3 IF1 / MibADC2 G2,RTI DMAREQ2 / MIBSPI5[8],RTI DMAREQ3 / MIBSPI5[9],N2HET1 DMAREQ[4] / N2HET2 DMAREQ[4] / DCAN3IF2,N2HET1 DMAREQ[5] / N2HET2 DMAREQ[5] / DCAN3IF3,MIBSPI1[10] / MIBSPI3[10] / MIBSPI5[10],MIBSPI1[11] / MIBSPI3[11] / MIBSPI5[11],N2HET1 DMAREQ[6] / N2HET2 DMAREQ[6] / SPI4 receive / MIBSPI5[12],N2HET1 DMAREQ[7] / N2HET2 DMAREQ[7] / SPI4 transmit / MIBSPI5[13],CRC DMAREQ[0] / MIBSPI1[12] / MIBSPI3[12],CRC DMAREQ[1] / MIBSPI1[13] / MIBSPI3[13],LIN receive / MIBSPI5[14],LIN transmit / MIBSPI5[15],MIBSPI1[14] / MIBSPI3[14] / SCI receive /MIBSPI5[1],MIBSPI1[15] / MIBSPI3[15] / SCI transmit /MIBSPI5[0],?..." endif tree.end width 6. tree "Port Assignment Registers" sif (cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE") group.long 0x94++0x3 line.long 0x0 "PAR0,PORT Assignment Register 0" bitfld.long 0x00 28.--30. " CH0PA ,Port Channel 0 Assignment" "Reserved,Reserved,Reserved,Reserved,B,B,B,B" bitfld.long 0x00 24.--26. " CH1PA ,Port Channel 1 Assignment" "Reserved,Reserved,Reserved,Reserved,B,B,B,B" bitfld.long 0x00 20.--22. " CH2PA ,Port Channel 2 Assignment" "Reserved,Reserved,Reserved,Reserved,B,B,B,B" textline " " bitfld.long 0x00 16.--18. " CH3PA ,Port Channel 3 Assignment" "Reserved,Reserved,Reserved,Reserved,B,B,B,B" bitfld.long 0x00 12.--14. " CH4PA ,Port Channel 4 Assignment" "Reserved,Reserved,Reserved,Reserved,B,B,B,B" bitfld.long 0x00 8.--10. " CH5PA ,Port Channel 5 Assignment" "Reserved,Reserved,Reserved,Reserved,B,B,B,B" textline " " bitfld.long 0x00 4.--6. " CH6PA ,Port Channel 6 Assignment" "Reserved,Reserved,Reserved,Reserved,B,B,B,B" bitfld.long 0x00 0.--2. " CH7PA ,Port Channel 7 Assignment" "Reserved,Reserved,Reserved,Reserved,B,B,B,B" else group.long 0x94++0x3 line.long 0x0 "PAR0,PORT Assignment Register 0" bitfld.long 0x00 28.--30. " CH0PA ,Port Channel 0 Assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B" bitfld.long 0x00 24.--26. " CH1PA ,Port Channel 1 Assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B" bitfld.long 0x00 20.--22. " CH2PA ,Port Channel 2 Assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B" textline " " bitfld.long 0x00 16.--18. " CH3PA ,Port Channel 3 Assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B" bitfld.long 0x00 12.--14. " CH4PA ,Port Channel 4 Assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B" bitfld.long 0x00 8.--10. " CH5PA ,Port Channel 5 Assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B" textline " " bitfld.long 0x00 4.--6. " CH6PA ,Port Channel 6 Assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B" bitfld.long 0x00 0.--2. " CH7PA ,Port Channel 7 Assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B" endif sif (cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE") group.long 0x98++0x3 line.long 0x0 "PAR1,PORT Assignment Register 1" bitfld.long 0x00 28.--30. " CH8PA ,Port Channel 8 Assignment" "Reserved,Reserved,Reserved,Reserved,B,B,B,B" bitfld.long 0x00 24.--26. " CH9PA ,Port Channel 9 Assignment" "Reserved,Reserved,Reserved,Reserved,B,B,B,B" bitfld.long 0x00 20.--22. " CH10PA ,Port Channel 10 Assignment" "Reserved,Reserved,Reserved,Reserved,B,B,B,B" textline " " bitfld.long 0x00 16.--18. " CH11PA ,Port Channel 11 Assignment" "Reserved,Reserved,Reserved,Reserved,B,B,B,B" bitfld.long 0x00 12.--14. " CH12PA ,Port Channel 12 Assignment" "Reserved,Reserved,Reserved,Reserved,B,B,B,B" bitfld.long 0x00 8.--10. " CH13PA ,Port Channel 13 Assignment" "Reserved,Reserved,Reserved,Reserved,B,B,B,B" textline " " bitfld.long 0x00 4.--6. " CH14PA ,Port Channel 14 Assignment" "Reserved,Reserved,Reserved,Reserved,B,B,B,B" bitfld.long 0x00 0.--2. " CH15PA ,Port Channel 15 Assignment" "Reserved,Reserved,Reserved,Reserved,B,B,B,B" else group.long 0x98++0x3 line.long 0x0 "PAR1,PORT Assignment Register 1" bitfld.long 0x00 28.--30. " CH8PA ,Port Channel 8 Assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B" bitfld.long 0x00 24.--26. " CH9PA ,Port Channel 9 Assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B" bitfld.long 0x00 20.--22. " CH10PA ,Port Channel 10 Assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B" textline " " bitfld.long 0x00 16.--18. " CH11PA ,Port Channel 11 Assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B" bitfld.long 0x00 12.--14. " CH12PA ,Port Channel 12 Assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B" bitfld.long 0x00 8.--10. " CH13PA ,Port Channel 13 Assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B" textline " " bitfld.long 0x00 4.--6. " CH14PA ,Port Channel 14 Assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B" bitfld.long 0x00 0.--2. " CH15PA ,Port Channel 15 Assignment" "A1(R)/A2(W),A2(R)/A1(W),A1,A2,B,B,B,B" endif tree.end width 8. tree "Interrupt Mapping Registers" group.long 0xB4++0x3 line.long 0x0 "FTCMAP,FTC INTERRUPT MAPPING Register" bitfld.long 0x00 15. " FTCAB15 ,Frame Transfer Complete Interrupt of Channel 15 to group A/B" "A,B" bitfld.long 0x00 14. " FTCAB14 ,Frame Transfer Complete Interrupt of Channel 14 to group A/B" "A,B" bitfld.long 0x00 13. " FTCAB13 ,Frame Transfer Complete Interrupt of Channel 13 to group A/B" "A,B" bitfld.long 0x00 12. " FTCAB12 ,Frame Transfer Complete Interrupt of Channel 12 to group A/B" "A,B" textline " " bitfld.long 0x00 11. " FTCAB11 ,Frame Transfer Complete Interrupt of Channel 11 to group A/B" "A,B" bitfld.long 0x00 10. " FTCAB10 ,Frame Transfer Complete Interrupt of Channel 10 to group A/B" "A,B" bitfld.long 0x00 9. " FTCAB9 ,Frame Transfer Complete Interrupt of Channel 9 to group A/B" "A,B" bitfld.long 0x00 8. " FTCAB8 ,Frame Transfer Complete Interrupt of Channel 8 to group A/B" "A,B" textline " " bitfld.long 0x00 7. " FTCAB7 ,Frame Transfer Complete Interrupt of Channel 7 to group A/B" "A,B" bitfld.long 0x00 6. " FTCAB6 ,Frame Transfer Complete Interrupt of Channel 6 to group A/B" "A,B" bitfld.long 0x00 5. " FTCAB5 ,Frame Transfer Complete Interrupt of Channel 5 to group A/B" "A,B" bitfld.long 0x00 4. " FTCAB4 ,Frame Transfer Complete Interrupt of Channel 4 to group A/B" "A,B" textline " " bitfld.long 0x00 3. " FTCAB3 ,Frame Transfer Complete Interrupt of Channel 3 to group A/B" "A,B" bitfld.long 0x00 2. " FTCAB2 ,Frame Transfer Complete Interrupt of Channel 2 to group A/B" "A,B" bitfld.long 0x00 1. " FTCAB1 ,Frame Transfer Complete Interrupt of Channel 1 to group A/B" "A,B" bitfld.long 0x00 0. " FTCAB0 ,Frame Transfer Complete Interrupt of Channel 0 to group A/B" "A,B" group.long 0xBC++0x3 line.long 0x0 "LFSMAP,LFS INTERRUPT MAPPING Register" bitfld.long 0x00 15. " LFSAB15 ,Last Frame Started Interrupt of Channel 15 to group A/B" "A,B" bitfld.long 0x00 14. " LFSAB14 ,Last Frame Started Interrupt of Channel 14 to group A/B" "A,B" bitfld.long 0x00 13. " LFSAB13 ,Last Frame Started Interrupt of Channel 13 to group A/B" "A,B" bitfld.long 0x00 12. " LFSAB12 ,Last Frame Started Interrupt of Channel 12 to group A/B" "A,B" textline " " bitfld.long 0x00 11. " LFSAB11 ,Last Frame Started Interrupt of Channel 11 to group A/B" "A,B" bitfld.long 0x00 10. " LFSAB10 ,Last Frame Started Interrupt of Channel 10 to group A/B" "A,B" bitfld.long 0x00 9. " LFSAB9 ,Last Frame Started Interrupt of Channel 9 to group A/B" "A,B" bitfld.long 0x00 8. " LFSAB8 ,Last Frame Started Interrupt of Channel 8 to group A/B" "A,B" textline " " bitfld.long 0x00 7. " LFSAB7 ,Last Frame Started Interrupt of Channel 7 to group A/B" "A,B" bitfld.long 0x00 6. " LFSAB6 ,Last Frame Started Interrupt of Channel 6 to group A/B" "A,B" bitfld.long 0x00 5. " LFSAB5 ,Last Frame Started Interrupt of Channel 5 to group A/B" "A,B" bitfld.long 0x00 4. " LFSAB4 ,Last Frame Started Interrupt of Channel 4 to group A/B" "A,B" textline " " bitfld.long 0x00 3. " LFSAB3 ,Last Frame Started Interrupt of Channel 3 to group A/B" "A,B" bitfld.long 0x00 2. " LFSAB2 ,Last Frame Started Interrupt of Channel 2 to group A/B" "A,B" bitfld.long 0x00 1. " LFSAB1 ,Last Frame Started Interrupt of Channel 1 to group A/B" "A,B" bitfld.long 0x00 0. " LFSAB0 ,Last Frame Started Interrupt of Channel 0 to group A/B" "A,B" group.long 0xC4++0x3 line.long 0x0 "HBCMAP,HBC INTERRUPT MAPPING Register" bitfld.long 0x00 15. " HBCAB15 ,Half Block Complete Interrupt of Channel 15 to group A/B" "A,B" bitfld.long 0x00 14. " HBCAB14 ,Half Block Complete Interrupt of Channel 14 to group A/B" "A,B" bitfld.long 0x00 13. " HBCAB13 ,Half Block Complete Interrupt of Channel 13 to group A/B" "A,B" bitfld.long 0x00 12. " HBCAB12 ,Half Block Complete Interrupt of Channel 12 to group A/B" "A,B" textline " " bitfld.long 0x00 11. " HBCAB11 ,Half Block Complete Interrupt of Channel 11 to group A/B" "A,B" bitfld.long 0x00 10. " HBCAB10 ,Half Block Complete Interrupt of Channel 10 to group A/B" "A,B" bitfld.long 0x00 9. " HBCAB9 ,Half Block Complete Interrupt of Channel 9 to group A/B" "A,B" bitfld.long 0x00 8. " HBCAB8 ,Half Block Complete Interrupt of Channel 8 to group A/B" "A,B" textline " " bitfld.long 0x00 7. " HBCAB7 ,Half Block Complete Interrupt of Channel 7 to group A/B" "A,B" bitfld.long 0x00 6. " HBCAB6 ,Half Block Complete Interrupt of Channel 6 to group A/B" "A,B" bitfld.long 0x00 5. " HBCAB5 ,Half Block Complete Interrupt of Channel 5 to group A/B" "A,B" bitfld.long 0x00 4. " HBCAB4 ,Half Block Complete Interrupt of Channel 4 to group A/B" "A,B" textline " " bitfld.long 0x00 3. " HBCAB3 ,Half Block Complete Interrupt of Channel 3 to group A/B" "A,B" bitfld.long 0x00 2. " HBCAB2 ,Half Block Complete Interrupt of Channel 2 to group A/B" "A,B" bitfld.long 0x00 1. " HBCAB1 ,Half Block Complete Interrupt of Channel 1 to group A/B" "A,B" bitfld.long 0x00 0. " HBCAB0 ,Half Block Complete Interrupt of Channel 0 to group A/B" "A,B" group.long 0xCC++0x3 line.long 0x0 "BTCMAP,BTC INTERRUPT MAPPING Register" bitfld.long 0x00 15. " BTCAB15 ,Block Transfer Complete Interrupt of Channel 15 to group A/B" "A,B" bitfld.long 0x00 14. " BTCAB14 ,Block Transfer Complete Interrupt of Channel 14 to group A/B" "A,B" bitfld.long 0x00 13. " BTCAB13 ,Block Transfer Complete Interrupt of Channel 13 to group A/B" "A,B" bitfld.long 0x00 12. " BTCAB12 ,Block Transfer Complete Interrupt of Channel 12 to group A/B" "A,B" textline " " bitfld.long 0x00 11. " BTCAB11 ,Block Transfer Complete Interrupt of Channel 11 to group A/B" "A,B" bitfld.long 0x00 10. " BTCAB10 ,Block Transfer Complete Interrupt of Channel 10 to group A/B" "A,B" bitfld.long 0x00 9. " BTCAB9 ,Block Transfer Complete Interrupt of Channel 9 to group A/B" "A,B" bitfld.long 0x00 8. " BTCAB8 ,Block Transfer Complete Interrupt of Channel 8 to group A/B" "A,B" textline " " bitfld.long 0x00 7. " BTCAB7 ,Block Transfer Complete Interrupt of Channel 7 to group A/B" "A,B" bitfld.long 0x00 6. " BTCAB6 ,Block Transfer Complete Interrupt of Channel 6 to group A/B" "A,B" bitfld.long 0x00 5. " BTCAB5 ,Block Transfer Complete Interrupt of Channel 5 to group A/B" "A,B" bitfld.long 0x00 4. " BTCAB4 ,Block Transfer Complete Interrupt of Channel 4 to group A/B" "A,B" textline " " bitfld.long 0x00 3. " BTCAB3 ,Block Transfer Complete Interrupt of Channel 3 to group A/B" "A,B" bitfld.long 0x00 2. " BTCAB2 ,Block Transfer Complete Interrupt of Channel 2 to group A/B" "A,B" bitfld.long 0x00 1. " BTCAB1 ,Block Transfer Complete Interrupt of Channel 1 to group A/B" "A,B" bitfld.long 0x00 0. " BTCAB0 ,Block Transfer Complete Interrupt of Channel 0 to group A/B" "A,B" group.long 0xD4++0x3 line.long 0x0 "BERMAP,BER INTERRUPT MAPPING Register" bitfld.long 0x00 15. " BERAB15 ,Bus Error Interrupt of Channel 15 to group A/B" "A,B" bitfld.long 0x00 14. " BERAB14 ,Bus Error Interrupt of Channel 14 to group A/B" "A,B" bitfld.long 0x00 13. " BERAB13 ,Bus Error Interrupt of Channel 13 to group A/B" "A,B" bitfld.long 0x00 12. " BERAB12 ,Bus Error Interrupt of Channel 12 to group A/B" "A,B" textline " " bitfld.long 0x00 11. " BERAB11 ,Bus Error Interrupt of Channel 11 to group A/B" "A,B" bitfld.long 0x00 10. " BERAB10 ,Bus Error Interrupt of Channel 10 to group A/B" "A,B" bitfld.long 0x00 9. " BERAB9 ,Bus Error Interrupt of Channel 9 to group A/B" "A,B" bitfld.long 0x00 8. " BERAB8 ,Bus Error Interrupt of Channel 8 to group A/B" "A,B" textline " " bitfld.long 0x00 7. " BERAB7 ,Bus Error Interrupt of Channel 7 to group A/B" "A,B" bitfld.long 0x00 6. " BERAB6 ,Bus Error Interrupt of Channel 6 to group A/B" "A,B" bitfld.long 0x00 5. " BERAB5 ,Bus Error Interrupt of Channel 5 to group A/B" "A,B" bitfld.long 0x00 4. " BERAB4 ,Bus Error Interrupt of Channel 4 to group A/B" "A,B" textline " " bitfld.long 0x00 3. " BERAB3 ,Bus Error Interrupt of Channel 3 to group A/B" "A,B" bitfld.long 0x00 2. " BERAB2 ,Bus Error Interrupt of Channel 2 to group A/B" "A,B" bitfld.long 0x00 1. " BERAB1 ,Bus Error Interrupt of Channel 1 to group A/B" "A,B" bitfld.long 0x00 0. " BERAB0 ,Bus Error Interrupt of Channel 0 to group A/B" "A,B" tree.end width 0xc tree "Interrupt Enable Registers" group.long 0xDC++0x3 line.long 0x0 "FTCINTENAS,FTC INTERRUPT ENABLE SET" bitfld.long 0x00 15. " FTCINTENA15 ,FTC (Frame Transfer Complete) Interrupt Enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " FTCINTENA14 ,FTC (Frame Transfer Complete) Interrupt Enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " FTCINTENA13 ,FTC (Frame Transfer Complete) Interrupt Enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " FTCINTENA12 ,FTC (Frame Transfer Complete) Interrupt Enable 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " FTCINTENA11 ,FTC (Frame Transfer Complete) Interrupt Enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " FTCINTENA10 ,FTC (Frame Transfer Complete) Interrupt Enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " FTCINTENA9 ,FTC (Frame Transfer Complete) Interrupt Enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " FTCINTENA8 ,FTC (Frame Transfer Complete) Interrupt Enable 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " FTCINTENA7 ,FTC (Frame Transfer Complete) Interrupt Enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " FTCINTENA6 ,FTC (Frame Transfer Complete) Interrupt Enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " FTCINTENA5 ,FTC (Frame Transfer Complete) Interrupt Enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " FTCINTENA4 ,FTC (Frame Transfer Complete) Interrupt Enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " FTCINTENA3 ,FTC (Frame Transfer Complete) Interrupt Enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " FTCINTENA2 ,FTC (Frame Transfer Complete) Interrupt Enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " FTCINTENA1 ,FTC (Frame Transfer Complete) Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " FTCINTENA0 ,FTC (Frame Transfer Complete) Interrupt Enable 0" "Disabled,Enabled" width 0xc group.long 0xE4++0x3 line.long 0x0 "FTCINTENAR,FTC INTERRUPT ENABLE RESET" bitfld.long 0x00 15. " FTCINTDIS15 ,FTC (Frame Transfer Complete) Interrupt Disable 15" "No,Yes" bitfld.long 0x00 14. " FTCINTDIS14 ,FTC (Frame Transfer Complete) Interrupt Disable 14" "No,Yes" bitfld.long 0x00 13. " FTCINTDIS13 ,FTC (Frame Transfer Complete) Interrupt Disable 13" "No,Yes" bitfld.long 0x00 12. " FTCINTDIS12 ,FTC (Frame Transfer Complete) Interrupt Disable 12" "No,Yes" textline " " bitfld.long 0x00 11. " FTCINTDIS11 ,FTC (Frame Transfer Complete) Interrupt Disable 11" "No,Yes" bitfld.long 0x00 10. " FTCINTDIS10 ,FTC (Frame Transfer Complete) Interrupt Disable 10" "No,Yes" bitfld.long 0x00 9. " FTCINTDIS9 ,FTC (Frame Transfer Complete) Interrupt Disable 9" "No,Yes" bitfld.long 0x00 8. " FTCINTDIS8 ,FTC (Frame Transfer Complete) Interrupt Disable 8" "No,Yes" textline " " bitfld.long 0x00 7. " FTCINTDIS7 ,FTC (Frame Transfer Complete) Interrupt Disable 7" "No,Yes" bitfld.long 0x00 6. " FTCINTDIS6 ,FTC (Frame Transfer Complete) Interrupt Disable 6" "No,Yes" bitfld.long 0x00 5. " FTCINTDIS5 ,FTC (Frame Transfer Complete) Interrupt Disable 5" "No,Yes" bitfld.long 0x00 4. " FTCINTDIS4 ,FTC (Frame Transfer Complete) Interrupt Disable 4" "No,Yes" textline " " bitfld.long 0x00 3. " FTCINTDIS3 ,FTC (Frame Transfer Complete) Interrupt Disable 3" "No,Yes" bitfld.long 0x00 2. " FTCINTDIS2 ,FTC (Frame Transfer Complete) Interrupt Disable 2" "No,Yes" bitfld.long 0x00 1. " FTCINTDIS1 ,FTC (Frame Transfer Complete) Interrupt Disable 1" "No,Yes" bitfld.long 0x00 0. " FTCINTDIS0 ,FTC (Frame Transfer Complete) Interrupt Disable 0" "No,Yes" width 0xc group.long 0xEC++0x3 line.long 0x0 "LFSINTENAS,LFS INTERRUPT ENABLE SET" bitfld.long 0x00 15. " LFSINTENA15 ,LFS (Last Frame Started) Interrupt Enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " LFSINTENA14 ,LFS (Last Frame Started) Interrupt Enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " LFSINTENA13 ,LFS (Last Frame Started) Interrupt Enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " LFSINTENA12 ,LFS (Last Frame Started) Interrupt Enable 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " LFSINTENA11 ,LFS (Last Frame Started) Interrupt Enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " LFSINTENA10 ,LFS (Last Frame Started) Interrupt Enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " LFSINTENA9 ,LFS (Last Frame Started) Interrupt Enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " LFSINTENA8 ,LFS (Last Frame Started) Interrupt Enable 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " LFSINTENA7 ,LFS (Last Frame Started) Interrupt Enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " LFSINTENA6 ,LFS (Last Frame Started) Interrupt Enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " LFSINTENA5 ,LFS (Last Frame Started) Interrupt Enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " LFSINTENA4 ,LFS (Last Frame Started) Interrupt Enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " LFSINTENA3 ,LFS (Last Frame Started) Interrupt Enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " LFSINTENA2 ,LFS (Last Frame Started) Interrupt Enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " LFSINTENA1 ,LFS (Last Frame Started) Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " LFSINTENA0 ,LFS (Last Frame Started) Interrupt Enable 0" "Disabled,Enabled" width 0xc group.long 0xF4++0x3 line.long 0x0 "LFSINTENAR,LFS INTERRUPT ENABLE RESET" bitfld.long 0x00 15. " LFSINTDIS15 ,LFS (Last Frame Started) Interrupt Disable 15" "No,Yes" bitfld.long 0x00 14. " LFSINTDIS14 ,LFS (Last Frame Started) Interrupt Disable 14" "No,Yes" bitfld.long 0x00 13. " LFSINTDIS13 ,LFS (Last Frame Started) Interrupt Disable 13" "No,Yes" bitfld.long 0x00 12. " LFSINTDIS12 ,LFS (Last Frame Started) Interrupt Disable 12" "No,Yes" textline " " bitfld.long 0x00 11. " LFSINTDIS11 ,LFS (Last Frame Started) Interrupt Disable 11" "No,Yes" bitfld.long 0x00 10. " LFSINTDIS10 ,LFS (Last Frame Started) Interrupt Disable 10" "No,Yes" bitfld.long 0x00 9. " LFSINTDIS9 ,LFS (Last Frame Started) Interrupt Disable 9" "No,Yes" bitfld.long 0x00 8. " LFSINTDIS8 ,LFS (Last Frame Started) Interrupt Disable 8" "No,Yes" textline " " bitfld.long 0x00 7. " LFSINTDIS7 ,LFS (Last Frame Started) Interrupt Disable 7" "No,Yes" bitfld.long 0x00 6. " LFSINTDIS6 ,LFS (Last Frame Started) Interrupt Disable 6" "No,Yes" bitfld.long 0x00 5. " LFSINTDIS5 ,LFS (Last Frame Started) Interrupt Disable 5" "No,Yes" bitfld.long 0x00 4. " LFSINTDIS4 ,LFS (Last Frame Started) Interrupt Disable 4" "No,Yes" textline " " bitfld.long 0x00 3. " LFSINTDIS3 ,LFS (Last Frame Started) Interrupt Disable 3" "No,Yes" bitfld.long 0x00 2. " LFSINTDIS2 ,LFS (Last Frame Started) Interrupt Disable 2" "No,Yes" bitfld.long 0x00 1. " LFSINTDIS1 ,LFS (Last Frame Started) Interrupt Disable 1" "No,Yes" bitfld.long 0x00 0. " LFSINTDIS0 ,LFS (Last Frame Started) Interrupt Disable 0" "No,Yes" width 0xc group.long 0xFC++0x3 line.long 0x0 "HBCINTENAS,HBC INTERRUPT ENABLE SET" bitfld.long 0x00 15. " HBCINTENA15 ,HBC (Half Block Complete) Interrupt Enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " HBCINTENA14 ,HBC (Half Block Complete) Interrupt Enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " HBCINTENA13 ,HBC (Half Block Complete) Interrupt Enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " HBCINTENA12 ,HBC (Half Block Complete) Interrupt Enable 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " HBCINTENA11 ,HBC (Half Block Complete) Interrupt Enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " HBCINTENA10 ,HBC (Half Block Complete) Interrupt Enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " HBCINTENA9 ,HBC (Half Block Complete) Interrupt Enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " HBCINTENA8 ,HBC (Half Block Complete) Interrupt Enable 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " HBCINTENA7 ,HBC (Half Block Complete) Interrupt Enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " HBCINTENA6 ,HBC (Half Block Complete) Interrupt Enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " HBCINTENA5 ,HBC (Half Block Complete) Interrupt Enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " HBCINTENA4 ,HBC (Half Block Complete) Interrupt Enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " HBCINTENA3 ,HBC (Half Block Complete) Interrupt Enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " HBCINTENA2 ,HBC (Half Block Complete) Interrupt Enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " HBCINTENA1 ,HBC (Half Block Complete) Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " HBCINTENA0 ,HBC (Half Block Complete) Interrupt Enable 0" "Disabled,Enabled" width 0xc group.long 0x104++0x3 line.long 0x0 "HBCINTENAR,HBC INTERRUPT ENABLE RESET" bitfld.long 0x00 15. " HBCINTENA15 ,HBC (Half Block Complete) Interrupt Disable 15" "No effect,Reset" bitfld.long 0x00 14. " HBCINTENA14 ,HBC (Half Block Complete) Interrupt Disable 14" "No effect,Reset" bitfld.long 0x00 13. " HBCINTENA13 ,HBC (Half Block Complete) Interrupt Disable 13" "No effect,Reset" bitfld.long 0x00 12. " HBCINTENA12 ,HBC (Half Block Complete) Interrupt Disable 12" "No effect,Reset" textline " " bitfld.long 0x00 11. " HBCINTENA11 ,HBC (Half Block Complete) Interrupt Disable 11" "No effect,Reset" bitfld.long 0x00 10. " HBCINTENA10 ,HBC (Half Block Complete) Interrupt Disable 10" "No effect,Reset" bitfld.long 0x00 9. " HBCINTENA9 ,HBC (Half Block Complete) Interrupt Disable 9" "No effect,Reset" bitfld.long 0x00 8. " HBCINTENA8 ,HBC (Half Block Complete) Interrupt Disable 8" "No effect,Reset" textline " " bitfld.long 0x00 7. " HBCINTENA7 ,HBC (Half Block Complete) Interrupt Disable 7" "No effect,Reset" bitfld.long 0x00 6. " HBCINTENA6 ,HBC (Half Block Complete) Interrupt Disable 6" "No effect,Reset" bitfld.long 0x00 5. " HBCINTENA5 ,HBC (Half Block Complete) Interrupt Disable 5" "No effect,Reset" bitfld.long 0x00 4. " HBCINTENA4 ,HBC (Half Block Complete) Interrupt Disable 4" "No effect,Reset" textline " " bitfld.long 0x00 3. " HBCINTENA3 ,HBC (Half Block Complete) Interrupt Disable 3" "No effect,Reset" bitfld.long 0x00 2. " HBCINTENA2 ,HBC (Half Block Complete) Interrupt Disable 2" "No effect,Reset" bitfld.long 0x00 1. " HBCINTENA1 ,HBC (Half Block Complete) Interrupt Disable 1" "No effect,Reset" bitfld.long 0x00 0. " HBCINTENA0 ,HBC (Half Block Complete) Interrupt Disable 0" "No effect,Reset" width 0xc group.long 0x10C++0x3 line.long 0x0 "BTCINTENAS,BTC INTERRUPT ENABLE SET" bitfld.long 0x00 15. " BTCINTENA15 ,BTC (Block Transfer Complete) Interrupt Enable 15" "Disabled,Enabled" bitfld.long 0x00 14. " BTCINTENA14 ,BTC (Block Transfer Complete) Interrupt Enable 14" "Disabled,Enabled" bitfld.long 0x00 13. " BTCINTENA13 ,BTC (Block Transfer Complete) Interrupt Enable 13" "Disabled,Enabled" bitfld.long 0x00 12. " BTCINTENA12 ,BTC (Block Transfer Complete) Interrupt Enable 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " BTCINTENA11 ,BTC (Block Transfer Complete) Interrupt Enable 11" "Disabled,Enabled" bitfld.long 0x00 10. " BTCINTENA10 ,BTC (Block Transfer Complete) Interrupt Enable 10" "Disabled,Enabled" bitfld.long 0x00 9. " BTCINTENA9 ,BTC (Block Transfer Complete) Interrupt Enable 9" "Disabled,Enabled" bitfld.long 0x00 8. " BTCINTENA8 ,BTC (Block Transfer Complete) Interrupt Enable 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " BTCINTENA7 ,BTC (Block Transfer Complete) Interrupt Enable 7" "Disabled,Enabled" bitfld.long 0x00 6. " BTCINTENA6 ,BTC (Block Transfer Complete) Interrupt Enable 6" "Disabled,Enabled" bitfld.long 0x00 5. " BTCINTENA5 ,BTC (Block Transfer Complete) Interrupt Enable 5" "Disabled,Enabled" bitfld.long 0x00 4. " BTCINTENA4 ,BTC (Block Transfer Complete) Interrupt Enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " BTCINTENA3 ,BTC (Block Transfer Complete) Interrupt Enable 3" "Disabled,Enabled" bitfld.long 0x00 2. " BTCINTENA2 ,BTC (Block Transfer Complete) Interrupt Enable 2" "Disabled,Enabled" bitfld.long 0x00 1. " BTCINTENA1 ,BTC (Block Transfer Complete) Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x00 0. " BTCINTENA0 ,BTC (Block Transfer Complete) Interrupt Enable 0" "Disabled,Enabled" width 0xc group.long 0x114++0x3 line.long 0x0 "BTCINTENAR,BTC INTERRUPT ENABLE RESET" bitfld.long 0x00 15. " BTCINTENA15 ,BTC (Block Transfer Complete) Interrupt Disable 15" "No effect,Reset" bitfld.long 0x00 14. " BTCINTENA14 ,BTC (Block Transfer Complete) Interrupt Disable 14" "No effect,Reset" bitfld.long 0x00 13. " BTCINTENA13 ,BTC (Block Transfer Complete) Interrupt Disable 13" "No effect,Reset" bitfld.long 0x00 12. " BTCINTENA12 ,BTC (Block Transfer Complete) Interrupt Disable 12" "No effect,Reset" textline " " bitfld.long 0x00 11. " BTCINTENA11 ,BTC (Block Transfer Complete) Interrupt Disable 11" "No effect,Reset" bitfld.long 0x00 10. " BTCINTENA10 ,BTC (Block Transfer Complete) Interrupt Disable 10" "No effect,Reset" bitfld.long 0x00 9. " BTCINTENA9 ,BTC (Block Transfer Complete) Interrupt Disable 9" "No effect,Reset" bitfld.long 0x00 8. " BTCINTENA8 ,BTC (Block Transfer Complete) Interrupt Disable 8" "No effect,Reset" textline " " bitfld.long 0x00 7. " BTCINTENA7 ,BTC (Block Transfer Complete) Interrupt Disable 7" "No effect,Reset" bitfld.long 0x00 6. " BTCINTENA6 ,BTC (Block Transfer Complete) Interrupt Disable 6" "No effect,Reset" bitfld.long 0x00 5. " BTCINTENA5 ,BTC (Block Transfer Complete) Interrupt Disable 5" "No effect,Reset" bitfld.long 0x00 4. " BTCINTENA4 ,BTC (Block Transfer Complete) Interrupt Disable 4" "No effect,Reset" textline " " bitfld.long 0x00 3. " BTCINTENA3 ,BTC (Block Transfer Complete) Interrupt Disable 3" "No effect,Reset" bitfld.long 0x00 2. " BTCINTENA2 ,BTC (Block Transfer Complete) Interrupt Disable 2" "No effect,Reset" bitfld.long 0x00 1. " BTCINTENA1 ,BTC (Block Transfer Complete) Interrupt Disable 1" "No effect,Reset" bitfld.long 0x00 0. " BTCINTENA0 ,BTC (Block Transfer Complete) Interrupt Disable 0" "No effect,Reset" tree.end width 0x9 tree "Interrupt Flag Registers" group.long 0x11C++0x3 line.long 0x0 "GINTFLAG,GLOBAL INTERRUPT FLAG Register" bitfld.long 0x00 15. " GINT15 ,Global Interrupt Flag 15" "Not pending,Pending" bitfld.long 0x00 14. " GINT14 ,Global Interrupt Flag 14" "Not pending,Pending" bitfld.long 0x00 13. " GINT13 ,Global Interrupt Flag 13" "Not pending,Pending" bitfld.long 0x00 12. " GINT12 ,Global Interrupt Flag 12" "Not pending,Pending" textline " " bitfld.long 0x00 11. " GINT11 ,Global Interrupt Flag 11" "Not pending,Pending" bitfld.long 0x00 10. " GINT10 ,Global Interrupt Flag 10" "Not pending,Pending" bitfld.long 0x00 9. " GINT9 ,Global Interrupt Flag 9" "Not pending,Pending" bitfld.long 0x00 8. " GINT8 ,Global Interrupt Flag 8" "Not pending,Pending" textline " " bitfld.long 0x00 7. " GINT7 ,Global Interrupt Flag 7" "Not pending,Pending" bitfld.long 0x00 6. " GINT6 ,Global Interrupt Flag 6" "Not pending,Pending" bitfld.long 0x00 5. " GINT5 ,Global Interrupt Flag 5" "Not pending,Pending" bitfld.long 0x00 4. " GINT4 ,Global Interrupt Flag 4" "Not pending,Pending" textline " " bitfld.long 0x00 3. " GINT3 ,Global Interrupt Flag 3" "Not pending,Pending" bitfld.long 0x00 2. " GINT2 ,Global Interrupt Flag 2" "Not pending,Pending" bitfld.long 0x00 1. " GINT1 ,Global Interrupt Flag 1" "Not pending,Pending" bitfld.long 0x00 0. " GINT0 ,Global Interrupt Flag 0" "Not pending,Pending" width 0x9 group.long 0x124++0x3 line.long 0x0 "FTCFLAG,FTC INTERRUPT FLAG Register" eventfld.long 0x00 15. " FTCI15 ,Frame Transfer Complete Flag 15" "Not pending,Pending" eventfld.long 0x00 14. " FTCI14 ,Frame Transfer Complete Flag 14" "Not pending,Pending" eventfld.long 0x00 13. " FTCI13 ,Frame Transfer Complete Flag 13" "Not pending,Pending" eventfld.long 0x00 12. " FTCI12 ,Frame Transfer Complete Flag 12" "Not pending,Pending" textline " " eventfld.long 0x00 11. " FTCI11 ,Frame Transfer Complete Flag 11" "Not pending,Pending" eventfld.long 0x00 10. " FTCI10 ,Frame Transfer Complete Flag 10" "Not pending,Pending" eventfld.long 0x00 9. " FTCI9 ,Frame Transfer Complete Flag 9" "Not pending,Pending" eventfld.long 0x00 8. " FTCI8 ,Frame Transfer Complete Flag 8" "Not pending,Pending" textline " " eventfld.long 0x00 7. " FTCI7 ,Frame Transfer Complete Flag 7" "Not pending,Pending" eventfld.long 0x00 6. " FTCI6 ,Frame Transfer Complete Flag 6" "Not pending,Pending" eventfld.long 0x00 5. " FTCI5 ,Frame Transfer Complete Flag 5" "Not pending,Pending" eventfld.long 0x00 4. " FTCI4 ,Frame Transfer Complete Flag 4" "Not pending,Pending" textline " " eventfld.long 0x00 3. " FTCI3 ,Frame Transfer Complete Flag 3" "Not pending,Pending" eventfld.long 0x00 2. " FTCI2 ,Frame Transfer Complete Flag 2" "Not pending,Pending" eventfld.long 0x00 1. " FTCI1 ,Frame Transfer Complete Flag 1" "Not pending,Pending" eventfld.long 0x00 0. " FTCI0 ,Frame Transfer Complete Flag 0" "Not pending,Pending" group.long 0x12C++0x3 line.long 0x0 "LFSFLAG,LFS INTERRUPT FLAG Register" eventfld.long 0x00 15. " LFSI15 ,Last Frame Transfer Started Flag 15" "Not pending,Pending" eventfld.long 0x00 14. " LFSI14 ,Last Frame Transfer Started Flag 14" "Not pending,Pending" eventfld.long 0x00 13. " LFSI13 ,Last Frame Transfer Started Flag 13" "Not pending,Pending" eventfld.long 0x00 12. " LFSI12 ,Last Frame Transfer Started Flag 12" "Not pending,Pending" textline " " eventfld.long 0x00 11. " LFSI11 ,Last Frame Transfer Started Flag 11" "Not pending,Pending" eventfld.long 0x00 10. " LFSI10 ,Last Frame Transfer Started Flag 10" "Not pending,Pending" eventfld.long 0x00 9. " LFSI9 ,Last Frame Transfer Started Flag 9" "Not pending,Pending" eventfld.long 0x00 8. " LFSI8 ,Last Frame Transfer Started Flag 8" "Not pending,Pending" textline " " eventfld.long 0x00 7. " LFSI7 ,Last Frame Transfer Started Flag 7" "Not pending,Pending" eventfld.long 0x00 6. " LFSI6 ,Last Frame Transfer Started Flag 6" "Not pending,Pending" eventfld.long 0x00 5. " LFSI5 ,Last Frame Transfer Started Flag 5" "Not pending,Pending" eventfld.long 0x00 4. " LFSI4 ,Last Frame Transfer Started Flag 4" "Not pending,Pending" textline " " eventfld.long 0x00 3. " LFSI3 ,Last Frame Transfer Started Flag 3" "Not pending,Pending" eventfld.long 0x00 2. " LFSI2 ,Last Frame Transfer Started Flag 2" "Not pending,Pending" eventfld.long 0x00 1. " LFSI1 ,Last Frame Transfer Started Flag 1" "Not pending,Pending" eventfld.long 0x00 0. " LFSI0 ,Last Frame Transfer Started Flag 0" "Not pending,Pending" group.long 0x134++0x3 line.long 0x0 "HBCFLAG,HBC INTERRUPT FLAG Register" eventfld.long 0x00 15. " HBCI15 ,Half of Block Transfer Complete Flag 15" "Not pending,Pending" eventfld.long 0x00 14. " HBCI14 ,Half of Block Transfer Complete Flag 14" "Not pending,Pending" eventfld.long 0x00 13. " HBCI13 ,Half of Block Transfer Complete Flag 13" "Not pending,Pending" eventfld.long 0x00 12. " HBCI12 ,Half of Block Transfer Complete Flag 12" "Not pending,Pending" textline " " eventfld.long 0x00 11. " HBCI11 ,Half of Block Transfer Complete Flag 11" "Not pending,Pending" eventfld.long 0x00 10. " HBCI10 ,Half of Block Transfer Complete Flag 10" "Not pending,Pending" eventfld.long 0x00 9. " HBCI9 ,Half of Block Transfer Complete Flag 9" "Not pending,Pending" eventfld.long 0x00 8. " HBCI8 ,Half of Block Transfer Complete Flag 8" "Not pending,Pending" textline " " eventfld.long 0x00 7. " HBCI7 ,Half of Block Transfer Complete Flag 7" "Not pending,Pending" eventfld.long 0x00 6. " HBCI6 ,Half of Block Transfer Complete Flag 6" "Not pending,Pending" eventfld.long 0x00 5. " HBCI5 ,Half of Block Transfer Complete Flag 5" "Not pending,Pending" eventfld.long 0x00 4. " HBCI4 ,Half of Block Transfer Complete Flag 4" "Not pending,Pending" textline " " eventfld.long 0x00 3. " HBCI3 ,Half of Block Transfer Complete Flag 3" "Not pending,Pending" eventfld.long 0x00 2. " HBCI2 ,Half of Block Transfer Complete Flag 2" "Not pending,Pending" eventfld.long 0x00 1. " HBCI1 ,Half of Block Transfer Complete Flag 1" "Not pending,Pending" eventfld.long 0x00 0. " HBCI0 ,Half of Block Transfer Complete Flag 0" "Not pending,Pending" group.long 0x13C++0x3 line.long 0x0 "BTCFLAG,BER INTERRUPT FLAG Register" eventfld.long 0x00 15. " BTCI15 ,Block Transfer Complete Flag 15" "Not pending,Pending" eventfld.long 0x00 14. " BTCI14 ,Block Transfer Complete Flag 14" "Not pending,Pending" eventfld.long 0x00 13. " BTCI13 ,Block Transfer Complete Flag 13" "Not pending,Pending" eventfld.long 0x00 12. " BTCI12 ,Block Transfer Complete Flag 12" "Not pending,Pending" textline " " eventfld.long 0x00 11. " BTCI11 ,Block Transfer Complete Flag 11" "Not pending,Pending" eventfld.long 0x00 10. " BTCI10 ,Block Transfer Complete Flag 10" "Not pending,Pending" eventfld.long 0x00 9. " BTCI9 ,Block Transfer Complete Flag 9" "Not pending,Pending" eventfld.long 0x00 8. " BTCI8 ,Block Transfer Complete Flag 8" "Not pending,Pending" textline " " eventfld.long 0x00 7. " BTCI7 ,Block Transfer Complete Flag 7" "Not pending,Pending" eventfld.long 0x00 6. " BTCI6 ,Block Transfer Complete Flag 6" "Not pending,Pending" eventfld.long 0x00 5. " BTCI5 ,Block Transfer Complete Flag 5" "Not pending,Pending" eventfld.long 0x00 4. " BTCI4 ,Block Transfer Complete Flag 4" "Not pending,Pending" textline " " eventfld.long 0x00 3. " BTCI3 ,Block Transfer Complete Flag 3" "Not pending,Pending" eventfld.long 0x00 2. " BTCI2 ,Block Transfer Complete Flag 2" "Not pending,Pending" eventfld.long 0x00 1. " BTCI1 ,Block Transfer Complete Flag 1" "Not pending,Pending" eventfld.long 0x00 0. " BTCI0 ,Block Transfer Complete Flag 0" "Not pending,Pending" group.long 0x144++0x3 line.long 0x0 "BERFLAG,BER INTERRUPT FLAG Register" eventfld.long 0x00 15. " BERI15 ,Bus Error Flag 15" "Not pending,Pending" eventfld.long 0x00 14. " BERI14 ,Bus Error Flag 14" "Not pending,Pending" eventfld.long 0x00 13. " BERI13 ,Bus Error Flag 13" "Not pending,Pending" eventfld.long 0x00 12. " BERI12 ,Bus Error Flag 12" "Not pending,Pending" textline " " eventfld.long 0x00 11. " BERI11 ,Bus Error Flag 11" "Not pending,Pending" eventfld.long 0x00 10. " BERI10 ,Bus Error Flag 10" "Not pending,Pending" eventfld.long 0x00 9. " BERI9 ,Bus Error Flag 9" "Not pending,Pending" eventfld.long 0x00 8. " BERI8 ,Bus Error Flag 8" "Not pending,Pending" textline " " eventfld.long 0x00 7. " BERI7 ,Bus Error Flag 7" "Not pending,Pending" eventfld.long 0x00 6. " BERI6 ,Bus Error Flag 6" "Not pending,Pending" eventfld.long 0x00 5. " BERI5 ,Bus Error Flag 5" "Not pending,Pending" eventfld.long 0x00 4. " BERI4 ,Bus Error Flag 4" "Not pending,Pending" textline " " eventfld.long 0x00 3. " BERI3 ,Bus Error Flag 3" "Not pending,Pending" eventfld.long 0x00 2. " BERI2 ,Bus Error Flag 2" "Not pending,Pending" eventfld.long 0x00 1. " BERI1 ,Bus Error Flag 1" "Not pending,Pending" eventfld.long 0x00 0. " BERI0 ,Bus Error Flag 0" "Not pending,Pending" tree.end width 0xc tree "Interrupt Channel Offset Registers" hgroup.long 0x14C++0x3 hide.long 0x0 "FTCAOFFSET,FTCA INTERRUPT CHANNEL OFFSET Register" in hgroup.long 0x150++0x3 hide.long 0x0 "LFSAOFFSET,LFSA INTERRUPT CHANNEL OFFSET Register" in hgroup.long 0x154++0x3 hide.long 0x0 "HBCAOFFSET,HBCA INTERRUPT CHANNEL OFFSET Register" in hgroup.long 0x158++0x3 hide.long 0x0 "BTCAOFFSET,BTCA INTERRUPT CHANNEL OFFSET Register" in hgroup.long 0x15C++0x3 hide.long 0x0 "BERAOFFSET,BERA INTERRUPT CHANNEL OFFSET Register" in hgroup.long 0x160++0x3 hide.long 0x0 "FTCBOFFSET,FTCB INTERRUPT CHANNEL OFFSET Register" in hgroup.long 0x164++0x3 hide.long 0x0 "LSFBOFFSET,LFSB INTERRUPT CHANNEL OFFSET Register" in hgroup.long 0x168++0x3 hide.long 0x0 "HBCBOFFSET,HBCB INTERRUPT CHANNEL OFFSET Register" in hgroup.long 0x16C++0x3 hide.long 0x0 "BTCBOFFSET,BTCB INTERRUPT CHANNEL OFFSET Register" in hgroup.long 0x170++0x3 hide.long 0x0 "BERBOFFSET,BERB INTERRUPT CHANNEL OFFSET Register" in tree.end width 0x8 textline " " group.long 0x178++0x3 line.long 0x0 "PTCRL,PORT CONTROL Register" bitfld.long 0x00 24. " PENDB ,Port B Transactions Pending" "Not pending,Pending" bitfld.long 0x00 18. " BYB ,Bypass FIFO B" "Not bypassed,Bypassed" bitfld.long 0x00 17. " PSFRHQPB ,Port B High Priority Queue Priority Scheme" "Fixed,Rotated" textline " " bitfld.long 0x00 16. " PSFRLQPB ,Port B Low Priority Queue Priority Scheme" "Fixed,Rotated" group.long 0x17C++0x3 line.long 0x0 "RTCTRL,RAM TEST CONTROL" bitfld.long 0x00 0. " RTC ,RAM Test Control" "Not accessed,Accessed" group.long 0x180++0x3 line.long 0x0 "DCTRL,DEBUG CONTROL" bitfld.long 0x00 24.--28. " CHNUM ,Channel Number" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,?..." eventfld.long 0x00 16. " DMADBGS ,DMA Debug Status" "Not detected,Detected" bitfld.long 0x00 0. " DBGEN ,Debug Enable" "Disabled,Enabled" group.long 0x184++0x3 line.long 0x0 "WPR,Watch Point Register" width 0x8 group.long 0x188++0x3 line.long 0x0 "WMR,WATCH MASK Register" bitfld.long 0x00 31. " WM ,Watch Mask 31" "0,1" bitfld.long 0x00 30. ",Watch Mask 30" "0,1" bitfld.long 0x00 29. ",Watch Mask 29" "0,1" bitfld.long 0x00 28. ",Watch Mask 28" "0 ,1 " bitfld.long 0x00 27. ",Watch Mask 27" "0,1" bitfld.long 0x00 26. ",Watch Mask 26" "0,1" bitfld.long 0x00 25. ",Watch Mask 25" "0,1" bitfld.long 0x00 24. ",Watch Mask 24" "0 ,1 " bitfld.long 0x00 23. ",Watch Mask 23" "0,1" bitfld.long 0x00 22. ",Watch Mask 22" "0,1" bitfld.long 0x00 21. ",Watch Mask 21" "0,1" bitfld.long 0x00 20. ",Watch Mask 20" "0 ,1 " bitfld.long 0x00 19. ",Watch Mask 19" "0,1" bitfld.long 0x00 18. ",Watch Mask 18" "0,1" bitfld.long 0x00 17. ",Watch Mask 17" "0,1" bitfld.long 0x00 16. ",Watch Mask 16" "0 ,1 " bitfld.long 0x00 15. ",Watch Mask 15" "0,1" bitfld.long 0x00 14. ",Watch Mask 14" "0,1" bitfld.long 0x00 13. ",Watch Mask 13" "0,1" bitfld.long 0x00 12. ",Watch Mask 12" "0 ,1 " bitfld.long 0x00 11. ",Watch Mask 11" "0,1" bitfld.long 0x00 10. ",Watch Mask 10" "0,1" bitfld.long 0x00 9. ",Watch Mask 9" "0,1" bitfld.long 0x00 8. ",Watch Mask 8" "0 ,1 " bitfld.long 0x00 7. ",Watch Mask 7" "0,1" bitfld.long 0x00 6. ",Watch Mask 6" "0,1" bitfld.long 0x00 5. ",Watch Mask 5" "0,1" bitfld.long 0x00 4. ",Watch Mask 4" "0 ,1 " bitfld.long 0x00 3. ",Watch Mask 3" "0,1" bitfld.long 0x00 2. ",Watch Mask 2" "0,1" bitfld.long 0x00 1. ",Watch Mask 1" "0,1" bitfld.long 0x00 0. ",Watch Mask 0" "0,1" width 16. tree "Active Channel Registers" sif (cpu()=="RM48L952-PGE"||cpu()=="RM48L952-ZWT"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L540-PGE"||cpu()=="RM46L852-PGE") group.long 0x18C++0x3 line.long 0x0 "PAACSADDR,Port A Active Channel Source Address Register" group.long 0x190++0x3 line.long 0x0 "PAACDADDR,Port A Active Channel Destination Address Register" group.long 0x194++0x3 line.long 0x0 "PAACTC,Port A Active Channel Transfer Count Register" hexmask.long.word 0x00 16.--28. 1. " PBFTCOUNT ,Port A active channel frame count" hexmask.long.word 0x00 0.--12. 1. " PBETCOUNT ,Port A active channel element count" endif group.long 0x198++0x3 line.long 0x0 "PBACDADDR,PORTB ACTIVE CHANNEL SOURCE ADDRESS Register" group.long 0x19C++0x3 line.long 0x0 "PBACDADDR,PORTB ACTIVE CHANNEL DESTINATION ADDRESS Register" group.long 0x1A0++0x3 line.long 0x0 "PBACTC,PORTB ACTIVE CHANNEL TRANSFER COUNT Register" hexmask.long.word 0x00 16.--28. 1. " PBFTCOUNT ,Port B Active Channel Frame Count" hexmask.long.word 0x00 0.--12. 1. " PBETCOUNT ,Port B Active Channel Element Count" tree.end width 8. textline " " group.long 0x1A8++0x3 line.long 0x0 "DMAPCR,PARITY CONTROL Register" bitfld.long 0x00 16. " ERRA ,Error Action" "Unchanged,Disabled" bitfld.long 0x00 8. " TEST ,Test" "Not mapped,Mapped" bitfld.long 0x00 0.--3. " PARITY_ENA ,Parity Error Detection Enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" group.long 0x1AC++0x3 line.long 0x0 "DMAPAR,Parity Error Address Register" eventfld.long 0x00 24. " EDFLG ,Parity Error Detection Flag" "No error,Error" hexmask.long.word 0x00 0.--11. 1. " ERRORADDRESS ,Error Address" width 0xb tree "DMA Memory Protection Registers" group.long 0x1B0++0x3 line.long 0x0 "DMAMPCTRL,Memory Protection Control Register" bitfld.long 0x00 28. " INT3AB ,Interrupt Assignment of Region 3 to group A/B" "VIM,Second CPU" bitfld.long 0x00 27. " INT3ENA ,Interrupt Enable of Region 3" "Disabled,Enabled" bitfld.long 0x00 25.--26. " REG3AP ,Region 3 Access Permission" "R/W,Read,Write,Not allowed" bitfld.long 0x00 24. " REG3ENA ,Region 3 Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " INT2AB ,Interrupt Assignment of Region 2 to group A/B" "VIM,Second CPU" bitfld.long 0x00 19. " INT2ENA ,Interrupt Enable of Region 2" "Disabled,Enabled" bitfld.long 0x00 17.--18. " REG2AP ,Region 2 Access Permission" "R/W,Read,Write,Not allowed" bitfld.long 0x00 16. " REG2ENA ,Region 2 Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " INT1AB ,Interrupt Assignment of Region 1 to group A/B" "VIM,Second CPU" bitfld.long 0x00 11. " INT1ENA ,Interrupt Enable of Region 1" "Disabled,Enabled" bitfld.long 0x00 9.--10. " REG1AP ,Region 1 Access Permission" "R/W,Read,Write,Not allowed" bitfld.long 0x00 8. " REG1ENA ,Region 1 Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " INT0AB ,Interrupt Assignment of Region 0 to group A/B" "VIM,Second CPU" bitfld.long 0x00 3. " INT0ENA ,Interrupt Enable of Region 0" "Disabled,Enabled" bitfld.long 0x00 1.--2. " REG0AP ,Region 0 Access Permission" "R/W,Read,Write,Not allowed" bitfld.long 0x00 0. " REG0ENA ,Region 0 Enable" "Disabled,Enabled" group.long 0x1B4++0x3 line.long 0x0 "DMAMPST,Memory Protection Status Register" eventfld.long 0x00 24. " REG3FT ,Region 3 Fault" "Not detected,Detected" eventfld.long 0x00 16. " REG2FT ,Region 2 Fault" "Not detected,Detected" eventfld.long 0x00 8. " REG1FT ,Region 1 Fault" "Not detected,Detected" textline " " eventfld.long 0x00 0. " REG0FT ,Region 0 Fault" "Not detected,Detected" group.long 0x1B8++0x3 line.long 0x0 "DMAPR0S,Defines Starting Address of Region 0" group.long 0x1BC++0x3 line.long 0x0 "DMAPR0E,Defines end Address of Region 0" group.long 0x1C0++0x3 line.long 0x0 "DMAPR1S,Defines Starting Address of Region 0" group.long 0x1C4++0x3 line.long 0x0 "DMAPR1E,Defines end Address of Region 1" group.long 0x1C8++0x3 line.long 0x0 "DMAPR2S,Defines Starting Address of Region 2" group.long 0x1CC++0x3 line.long 0x0 "DMAPR2E,Defines end Address of Region 2" group.long 0x1D0++0x3 line.long 0x0 "DMAPR3S,Defines Starting Address of Region 3" group.long 0x1D4++0x3 line.long 0x0 "DMAPR3E,Defines end Address of Region 3" tree.end base ad:0xFFF80000 tree "Channel Configuration" width 9. tree.open "Primary Control Packet Registers" tree "Primary Control Packet 0" group.long (0x0)++0x0b line.long 0x00 "ISADDR,Initial Source Address Register" line.long 0x04 "IDADDR,Initial Destination Address Register" line.long 0x08 "ITCOUNT,Initial Transfer Count Register" hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial Frame Transfer Count" hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial Element Transfer Count" group.long (0x0+0x10)++0x0b line.long 0x00 "CHCTRL,Channel Control Register" bitfld.long 0x00 16.--21. " CHAIN ,Next Channel to be Triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,?..." bitfld.long 0x00 14.--15. " RES ,Read Element Size" "8 bits,16 bits,32 bits,64 bits" bitfld.long 0x00 12.--13. " WES ,Write Element Size" "8 bits,16 bits,32 bits,64 bits" textline " " bitfld.long 0x00 8. " TTYPE ,Transfer Type" "Frame,Block" bitfld.long 0x00 3.--4. " ADDMR ,Addressing Mode Read" "Constant,Post-increment,Reserved,Indexed" textline " " bitfld.long 0x00 1.--2. " ADDMW ,Addressing Mode Write" "Constant,Post-increment,Reserved,Indexed" bitfld.long 0x00 0. " AIM ,Autoinitiation Mode" "Single block,Autoinitiation" line.long 0x04 "EIOFF,Element Index Offset Register" hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination Address Element Index" hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source Address Element Index" line.long 0x08 "FIOFF,Frame Index Offset Register" hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination Address Frame Index" hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source Address Frame Index" tree.end tree "Primary Control Packet 1" group.long (0x20)++0x0b line.long 0x00 "ISADDR,Initial Source Address Register" line.long 0x04 "IDADDR,Initial Destination Address Register" line.long 0x08 "ITCOUNT,Initial Transfer Count Register" hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial Frame Transfer Count" hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial Element Transfer Count" group.long (0x20+0x10)++0x0b line.long 0x00 "CHCTRL,Channel Control Register" bitfld.long 0x00 16.--21. " CHAIN ,Next Channel to be Triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,?..." bitfld.long 0x00 14.--15. " RES ,Read Element Size" "8 bits,16 bits,32 bits,64 bits" bitfld.long 0x00 12.--13. " WES ,Write Element Size" "8 bits,16 bits,32 bits,64 bits" textline " " bitfld.long 0x00 8. " TTYPE ,Transfer Type" "Frame,Block" bitfld.long 0x00 3.--4. " ADDMR ,Addressing Mode Read" "Constant,Post-increment,Reserved,Indexed" textline " " bitfld.long 0x00 1.--2. " ADDMW ,Addressing Mode Write" "Constant,Post-increment,Reserved,Indexed" bitfld.long 0x00 0. " AIM ,Autoinitiation Mode" "Single block,Autoinitiation" line.long 0x04 "EIOFF,Element Index Offset Register" hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination Address Element Index" hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source Address Element Index" line.long 0x08 "FIOFF,Frame Index Offset Register" hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination Address Frame Index" hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source Address Frame Index" tree.end tree "Primary Control Packet 2" group.long (0x40)++0x0b line.long 0x00 "ISADDR,Initial Source Address Register" line.long 0x04 "IDADDR,Initial Destination Address Register" line.long 0x08 "ITCOUNT,Initial Transfer Count Register" hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial Frame Transfer Count" hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial Element Transfer Count" group.long (0x40+0x10)++0x0b line.long 0x00 "CHCTRL,Channel Control Register" bitfld.long 0x00 16.--21. " CHAIN ,Next Channel to be Triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,?..." bitfld.long 0x00 14.--15. " RES ,Read Element Size" "8 bits,16 bits,32 bits,64 bits" bitfld.long 0x00 12.--13. " WES ,Write Element Size" "8 bits,16 bits,32 bits,64 bits" textline " " bitfld.long 0x00 8. " TTYPE ,Transfer Type" "Frame,Block" bitfld.long 0x00 3.--4. " ADDMR ,Addressing Mode Read" "Constant,Post-increment,Reserved,Indexed" textline " " bitfld.long 0x00 1.--2. " ADDMW ,Addressing Mode Write" "Constant,Post-increment,Reserved,Indexed" bitfld.long 0x00 0. " AIM ,Autoinitiation Mode" "Single block,Autoinitiation" line.long 0x04 "EIOFF,Element Index Offset Register" hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination Address Element Index" hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source Address Element Index" line.long 0x08 "FIOFF,Frame Index Offset Register" hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination Address Frame Index" hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source Address Frame Index" tree.end tree "Primary Control Packet 3" group.long (0x60)++0x0b line.long 0x00 "ISADDR,Initial Source Address Register" line.long 0x04 "IDADDR,Initial Destination Address Register" line.long 0x08 "ITCOUNT,Initial Transfer Count Register" hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial Frame Transfer Count" hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial Element Transfer Count" group.long (0x60+0x10)++0x0b line.long 0x00 "CHCTRL,Channel Control Register" bitfld.long 0x00 16.--21. " CHAIN ,Next Channel to be Triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,?..." bitfld.long 0x00 14.--15. " RES ,Read Element Size" "8 bits,16 bits,32 bits,64 bits" bitfld.long 0x00 12.--13. " WES ,Write Element Size" "8 bits,16 bits,32 bits,64 bits" textline " " bitfld.long 0x00 8. " TTYPE ,Transfer Type" "Frame,Block" bitfld.long 0x00 3.--4. " ADDMR ,Addressing Mode Read" "Constant,Post-increment,Reserved,Indexed" textline " " bitfld.long 0x00 1.--2. " ADDMW ,Addressing Mode Write" "Constant,Post-increment,Reserved,Indexed" bitfld.long 0x00 0. " AIM ,Autoinitiation Mode" "Single block,Autoinitiation" line.long 0x04 "EIOFF,Element Index Offset Register" hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination Address Element Index" hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source Address Element Index" line.long 0x08 "FIOFF,Frame Index Offset Register" hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination Address Frame Index" hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source Address Frame Index" tree.end tree "Primary Control Packet 4" group.long (0x80)++0x0b line.long 0x00 "ISADDR,Initial Source Address Register" line.long 0x04 "IDADDR,Initial Destination Address Register" line.long 0x08 "ITCOUNT,Initial Transfer Count Register" hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial Frame Transfer Count" hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial Element Transfer Count" group.long (0x80+0x10)++0x0b line.long 0x00 "CHCTRL,Channel Control Register" bitfld.long 0x00 16.--21. " CHAIN ,Next Channel to be Triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,?..." bitfld.long 0x00 14.--15. " RES ,Read Element Size" "8 bits,16 bits,32 bits,64 bits" bitfld.long 0x00 12.--13. " WES ,Write Element Size" "8 bits,16 bits,32 bits,64 bits" textline " " bitfld.long 0x00 8. " TTYPE ,Transfer Type" "Frame,Block" bitfld.long 0x00 3.--4. " ADDMR ,Addressing Mode Read" "Constant,Post-increment,Reserved,Indexed" textline " " bitfld.long 0x00 1.--2. " ADDMW ,Addressing Mode Write" "Constant,Post-increment,Reserved,Indexed" bitfld.long 0x00 0. " AIM ,Autoinitiation Mode" "Single block,Autoinitiation" line.long 0x04 "EIOFF,Element Index Offset Register" hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination Address Element Index" hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source Address Element Index" line.long 0x08 "FIOFF,Frame Index Offset Register" hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination Address Frame Index" hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source Address Frame Index" tree.end tree "Primary Control Packet 5" group.long (0xA0)++0x0b line.long 0x00 "ISADDR,Initial Source Address Register" line.long 0x04 "IDADDR,Initial Destination Address Register" line.long 0x08 "ITCOUNT,Initial Transfer Count Register" hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial Frame Transfer Count" hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial Element Transfer Count" group.long (0xA0+0x10)++0x0b line.long 0x00 "CHCTRL,Channel Control Register" bitfld.long 0x00 16.--21. " CHAIN ,Next Channel to be Triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,?..." bitfld.long 0x00 14.--15. " RES ,Read Element Size" "8 bits,16 bits,32 bits,64 bits" bitfld.long 0x00 12.--13. " WES ,Write Element Size" "8 bits,16 bits,32 bits,64 bits" textline " " bitfld.long 0x00 8. " TTYPE ,Transfer Type" "Frame,Block" bitfld.long 0x00 3.--4. " ADDMR ,Addressing Mode Read" "Constant,Post-increment,Reserved,Indexed" textline " " bitfld.long 0x00 1.--2. " ADDMW ,Addressing Mode Write" "Constant,Post-increment,Reserved,Indexed" bitfld.long 0x00 0. " AIM ,Autoinitiation Mode" "Single block,Autoinitiation" line.long 0x04 "EIOFF,Element Index Offset Register" hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination Address Element Index" hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source Address Element Index" line.long 0x08 "FIOFF,Frame Index Offset Register" hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination Address Frame Index" hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source Address Frame Index" tree.end tree "Primary Control Packet 6" group.long (0xC0)++0x0b line.long 0x00 "ISADDR,Initial Source Address Register" line.long 0x04 "IDADDR,Initial Destination Address Register" line.long 0x08 "ITCOUNT,Initial Transfer Count Register" hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial Frame Transfer Count" hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial Element Transfer Count" group.long (0xC0+0x10)++0x0b line.long 0x00 "CHCTRL,Channel Control Register" bitfld.long 0x00 16.--21. " CHAIN ,Next Channel to be Triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,?..." bitfld.long 0x00 14.--15. " RES ,Read Element Size" "8 bits,16 bits,32 bits,64 bits" bitfld.long 0x00 12.--13. " WES ,Write Element Size" "8 bits,16 bits,32 bits,64 bits" textline " " bitfld.long 0x00 8. " TTYPE ,Transfer Type" "Frame,Block" bitfld.long 0x00 3.--4. " ADDMR ,Addressing Mode Read" "Constant,Post-increment,Reserved,Indexed" textline " " bitfld.long 0x00 1.--2. " ADDMW ,Addressing Mode Write" "Constant,Post-increment,Reserved,Indexed" bitfld.long 0x00 0. " AIM ,Autoinitiation Mode" "Single block,Autoinitiation" line.long 0x04 "EIOFF,Element Index Offset Register" hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination Address Element Index" hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source Address Element Index" line.long 0x08 "FIOFF,Frame Index Offset Register" hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination Address Frame Index" hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source Address Frame Index" tree.end tree "Primary Control Packet 7" group.long (0xE0)++0x0b line.long 0x00 "ISADDR,Initial Source Address Register" line.long 0x04 "IDADDR,Initial Destination Address Register" line.long 0x08 "ITCOUNT,Initial Transfer Count Register" hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial Frame Transfer Count" hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial Element Transfer Count" group.long (0xE0+0x10)++0x0b line.long 0x00 "CHCTRL,Channel Control Register" bitfld.long 0x00 16.--21. " CHAIN ,Next Channel to be Triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,?..." bitfld.long 0x00 14.--15. " RES ,Read Element Size" "8 bits,16 bits,32 bits,64 bits" bitfld.long 0x00 12.--13. " WES ,Write Element Size" "8 bits,16 bits,32 bits,64 bits" textline " " bitfld.long 0x00 8. " TTYPE ,Transfer Type" "Frame,Block" bitfld.long 0x00 3.--4. " ADDMR ,Addressing Mode Read" "Constant,Post-increment,Reserved,Indexed" textline " " bitfld.long 0x00 1.--2. " ADDMW ,Addressing Mode Write" "Constant,Post-increment,Reserved,Indexed" bitfld.long 0x00 0. " AIM ,Autoinitiation Mode" "Single block,Autoinitiation" line.long 0x04 "EIOFF,Element Index Offset Register" hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination Address Element Index" hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source Address Element Index" line.long 0x08 "FIOFF,Frame Index Offset Register" hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination Address Frame Index" hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source Address Frame Index" tree.end tree "Primary Control Packet 8" group.long (0x100)++0x0b line.long 0x00 "ISADDR,Initial Source Address Register" line.long 0x04 "IDADDR,Initial Destination Address Register" line.long 0x08 "ITCOUNT,Initial Transfer Count Register" hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial Frame Transfer Count" hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial Element Transfer Count" group.long (0x100+0x10)++0x0b line.long 0x00 "CHCTRL,Channel Control Register" bitfld.long 0x00 16.--21. " CHAIN ,Next Channel to be Triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,?..." bitfld.long 0x00 14.--15. " RES ,Read Element Size" "8 bits,16 bits,32 bits,64 bits" bitfld.long 0x00 12.--13. " WES ,Write Element Size" "8 bits,16 bits,32 bits,64 bits" textline " " bitfld.long 0x00 8. " TTYPE ,Transfer Type" "Frame,Block" bitfld.long 0x00 3.--4. " ADDMR ,Addressing Mode Read" "Constant,Post-increment,Reserved,Indexed" textline " " bitfld.long 0x00 1.--2. " ADDMW ,Addressing Mode Write" "Constant,Post-increment,Reserved,Indexed" bitfld.long 0x00 0. " AIM ,Autoinitiation Mode" "Single block,Autoinitiation" line.long 0x04 "EIOFF,Element Index Offset Register" hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination Address Element Index" hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source Address Element Index" line.long 0x08 "FIOFF,Frame Index Offset Register" hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination Address Frame Index" hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source Address Frame Index" tree.end tree "Primary Control Packet 9" group.long (0x120)++0x0b line.long 0x00 "ISADDR,Initial Source Address Register" line.long 0x04 "IDADDR,Initial Destination Address Register" line.long 0x08 "ITCOUNT,Initial Transfer Count Register" hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial Frame Transfer Count" hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial Element Transfer Count" group.long (0x120+0x10)++0x0b line.long 0x00 "CHCTRL,Channel Control Register" bitfld.long 0x00 16.--21. " CHAIN ,Next Channel to be Triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,?..." bitfld.long 0x00 14.--15. " RES ,Read Element Size" "8 bits,16 bits,32 bits,64 bits" bitfld.long 0x00 12.--13. " WES ,Write Element Size" "8 bits,16 bits,32 bits,64 bits" textline " " bitfld.long 0x00 8. " TTYPE ,Transfer Type" "Frame,Block" bitfld.long 0x00 3.--4. " ADDMR ,Addressing Mode Read" "Constant,Post-increment,Reserved,Indexed" textline " " bitfld.long 0x00 1.--2. " ADDMW ,Addressing Mode Write" "Constant,Post-increment,Reserved,Indexed" bitfld.long 0x00 0. " AIM ,Autoinitiation Mode" "Single block,Autoinitiation" line.long 0x04 "EIOFF,Element Index Offset Register" hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination Address Element Index" hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source Address Element Index" line.long 0x08 "FIOFF,Frame Index Offset Register" hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination Address Frame Index" hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source Address Frame Index" tree.end tree "Primary Control Packet 10" group.long (0x140)++0x0b line.long 0x00 "ISADDR,Initial Source Address Register" line.long 0x04 "IDADDR,Initial Destination Address Register" line.long 0x08 "ITCOUNT,Initial Transfer Count Register" hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial Frame Transfer Count" hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial Element Transfer Count" group.long (0x140+0x10)++0x0b line.long 0x00 "CHCTRL,Channel Control Register" bitfld.long 0x00 16.--21. " CHAIN ,Next Channel to be Triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,?..." bitfld.long 0x00 14.--15. " RES ,Read Element Size" "8 bits,16 bits,32 bits,64 bits" bitfld.long 0x00 12.--13. " WES ,Write Element Size" "8 bits,16 bits,32 bits,64 bits" textline " " bitfld.long 0x00 8. " TTYPE ,Transfer Type" "Frame,Block" bitfld.long 0x00 3.--4. " ADDMR ,Addressing Mode Read" "Constant,Post-increment,Reserved,Indexed" textline " " bitfld.long 0x00 1.--2. " ADDMW ,Addressing Mode Write" "Constant,Post-increment,Reserved,Indexed" bitfld.long 0x00 0. " AIM ,Autoinitiation Mode" "Single block,Autoinitiation" line.long 0x04 "EIOFF,Element Index Offset Register" hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination Address Element Index" hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source Address Element Index" line.long 0x08 "FIOFF,Frame Index Offset Register" hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination Address Frame Index" hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source Address Frame Index" tree.end tree "Primary Control Packet 11" group.long (0x160)++0x0b line.long 0x00 "ISADDR,Initial Source Address Register" line.long 0x04 "IDADDR,Initial Destination Address Register" line.long 0x08 "ITCOUNT,Initial Transfer Count Register" hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial Frame Transfer Count" hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial Element Transfer Count" group.long (0x160+0x10)++0x0b line.long 0x00 "CHCTRL,Channel Control Register" bitfld.long 0x00 16.--21. " CHAIN ,Next Channel to be Triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,?..." bitfld.long 0x00 14.--15. " RES ,Read Element Size" "8 bits,16 bits,32 bits,64 bits" bitfld.long 0x00 12.--13. " WES ,Write Element Size" "8 bits,16 bits,32 bits,64 bits" textline " " bitfld.long 0x00 8. " TTYPE ,Transfer Type" "Frame,Block" bitfld.long 0x00 3.--4. " ADDMR ,Addressing Mode Read" "Constant,Post-increment,Reserved,Indexed" textline " " bitfld.long 0x00 1.--2. " ADDMW ,Addressing Mode Write" "Constant,Post-increment,Reserved,Indexed" bitfld.long 0x00 0. " AIM ,Autoinitiation Mode" "Single block,Autoinitiation" line.long 0x04 "EIOFF,Element Index Offset Register" hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination Address Element Index" hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source Address Element Index" line.long 0x08 "FIOFF,Frame Index Offset Register" hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination Address Frame Index" hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source Address Frame Index" tree.end tree "Primary Control Packet 12" group.long (0x180)++0x0b line.long 0x00 "ISADDR,Initial Source Address Register" line.long 0x04 "IDADDR,Initial Destination Address Register" line.long 0x08 "ITCOUNT,Initial Transfer Count Register" hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial Frame Transfer Count" hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial Element Transfer Count" group.long (0x180+0x10)++0x0b line.long 0x00 "CHCTRL,Channel Control Register" bitfld.long 0x00 16.--21. " CHAIN ,Next Channel to be Triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,?..." bitfld.long 0x00 14.--15. " RES ,Read Element Size" "8 bits,16 bits,32 bits,64 bits" bitfld.long 0x00 12.--13. " WES ,Write Element Size" "8 bits,16 bits,32 bits,64 bits" textline " " bitfld.long 0x00 8. " TTYPE ,Transfer Type" "Frame,Block" bitfld.long 0x00 3.--4. " ADDMR ,Addressing Mode Read" "Constant,Post-increment,Reserved,Indexed" textline " " bitfld.long 0x00 1.--2. " ADDMW ,Addressing Mode Write" "Constant,Post-increment,Reserved,Indexed" bitfld.long 0x00 0. " AIM ,Autoinitiation Mode" "Single block,Autoinitiation" line.long 0x04 "EIOFF,Element Index Offset Register" hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination Address Element Index" hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source Address Element Index" line.long 0x08 "FIOFF,Frame Index Offset Register" hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination Address Frame Index" hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source Address Frame Index" tree.end tree "Primary Control Packet 13" group.long (0x1A0)++0x0b line.long 0x00 "ISADDR,Initial Source Address Register" line.long 0x04 "IDADDR,Initial Destination Address Register" line.long 0x08 "ITCOUNT,Initial Transfer Count Register" hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial Frame Transfer Count" hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial Element Transfer Count" group.long (0x1A0+0x10)++0x0b line.long 0x00 "CHCTRL,Channel Control Register" bitfld.long 0x00 16.--21. " CHAIN ,Next Channel to be Triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,?..." bitfld.long 0x00 14.--15. " RES ,Read Element Size" "8 bits,16 bits,32 bits,64 bits" bitfld.long 0x00 12.--13. " WES ,Write Element Size" "8 bits,16 bits,32 bits,64 bits" textline " " bitfld.long 0x00 8. " TTYPE ,Transfer Type" "Frame,Block" bitfld.long 0x00 3.--4. " ADDMR ,Addressing Mode Read" "Constant,Post-increment,Reserved,Indexed" textline " " bitfld.long 0x00 1.--2. " ADDMW ,Addressing Mode Write" "Constant,Post-increment,Reserved,Indexed" bitfld.long 0x00 0. " AIM ,Autoinitiation Mode" "Single block,Autoinitiation" line.long 0x04 "EIOFF,Element Index Offset Register" hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination Address Element Index" hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source Address Element Index" line.long 0x08 "FIOFF,Frame Index Offset Register" hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination Address Frame Index" hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source Address Frame Index" tree.end tree "Primary Control Packet 14" group.long (0x1C0)++0x0b line.long 0x00 "ISADDR,Initial Source Address Register" line.long 0x04 "IDADDR,Initial Destination Address Register" line.long 0x08 "ITCOUNT,Initial Transfer Count Register" hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial Frame Transfer Count" hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial Element Transfer Count" group.long (0x1C0+0x10)++0x0b line.long 0x00 "CHCTRL,Channel Control Register" bitfld.long 0x00 16.--21. " CHAIN ,Next Channel to be Triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,?..." bitfld.long 0x00 14.--15. " RES ,Read Element Size" "8 bits,16 bits,32 bits,64 bits" bitfld.long 0x00 12.--13. " WES ,Write Element Size" "8 bits,16 bits,32 bits,64 bits" textline " " bitfld.long 0x00 8. " TTYPE ,Transfer Type" "Frame,Block" bitfld.long 0x00 3.--4. " ADDMR ,Addressing Mode Read" "Constant,Post-increment,Reserved,Indexed" textline " " bitfld.long 0x00 1.--2. " ADDMW ,Addressing Mode Write" "Constant,Post-increment,Reserved,Indexed" bitfld.long 0x00 0. " AIM ,Autoinitiation Mode" "Single block,Autoinitiation" line.long 0x04 "EIOFF,Element Index Offset Register" hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination Address Element Index" hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source Address Element Index" line.long 0x08 "FIOFF,Frame Index Offset Register" hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination Address Frame Index" hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source Address Frame Index" tree.end tree "Primary Control Packet 15" group.long (0x1E0)++0x0b line.long 0x00 "ISADDR,Initial Source Address Register" line.long 0x04 "IDADDR,Initial Destination Address Register" line.long 0x08 "ITCOUNT,Initial Transfer Count Register" hexmask.long.word 0x08 16.--28. 1. " IFTCOUNT ,Initial Frame Transfer Count" hexmask.long.word 0x08 0.--12. 1. " IETCOUNT ,Initial Element Transfer Count" group.long (0x1E0+0x10)++0x0b line.long 0x00 "CHCTRL,Channel Control Register" bitfld.long 0x00 16.--21. " CHAIN ,Next Channel to be Triggered" "No channel,Ch0,Ch1,Ch2,Ch3,Ch4,Ch5,Ch6,Ch7,Ch8,Ch9,Ch10,Ch11,Ch12,Ch13,Ch14,Ch15,?..." bitfld.long 0x00 14.--15. " RES ,Read Element Size" "8 bits,16 bits,32 bits,64 bits" bitfld.long 0x00 12.--13. " WES ,Write Element Size" "8 bits,16 bits,32 bits,64 bits" textline " " bitfld.long 0x00 8. " TTYPE ,Transfer Type" "Frame,Block" bitfld.long 0x00 3.--4. " ADDMR ,Addressing Mode Read" "Constant,Post-increment,Reserved,Indexed" textline " " bitfld.long 0x00 1.--2. " ADDMW ,Addressing Mode Write" "Constant,Post-increment,Reserved,Indexed" bitfld.long 0x00 0. " AIM ,Autoinitiation Mode" "Single block,Autoinitiation" line.long 0x04 "EIOFF,Element Index Offset Register" hexmask.long.word 0x04 16.--28. 1. " EIDXD ,Destination Address Element Index" hexmask.long.word 0x04 0.--12. 1. " EIDXS ,Source Address Element Index" line.long 0x08 "FIOFF,Frame Index Offset Register" hexmask.long.word 0x08 16.--28. 1. " FIDXD ,Destination Address Frame Index" hexmask.long.word 0x08 0.--12. 1. " FIDXS ,Source Address Frame Index" tree.end tree.end width 9. tree.open "Working Control Packet Registers" tree "Working Control Packet 0" group.long (0x0800+0x0)++0x07 line.long 0x00 "CSADDR,Current Source Address Register" line.long 0x04 "CDADDR,Current Destination Address Register" rgroup.long (0x0808+0x0)++0x03 line.long 0x00 "CTCOUNT,Current Transfer Count Register" hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current Frame Transfer Count" hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current Element Transfer Count" tree.end tree "Working Control Packet 1" group.long (0x0800+0x10)++0x07 line.long 0x00 "CSADDR,Current Source Address Register" line.long 0x04 "CDADDR,Current Destination Address Register" rgroup.long (0x0808+0x10)++0x03 line.long 0x00 "CTCOUNT,Current Transfer Count Register" hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current Frame Transfer Count" hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current Element Transfer Count" tree.end tree "Working Control Packet 2" group.long (0x0800+0x20)++0x07 line.long 0x00 "CSADDR,Current Source Address Register" line.long 0x04 "CDADDR,Current Destination Address Register" rgroup.long (0x0808+0x20)++0x03 line.long 0x00 "CTCOUNT,Current Transfer Count Register" hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current Frame Transfer Count" hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current Element Transfer Count" tree.end tree "Working Control Packet 3" group.long (0x0800+0x30)++0x07 line.long 0x00 "CSADDR,Current Source Address Register" line.long 0x04 "CDADDR,Current Destination Address Register" rgroup.long (0x0808+0x30)++0x03 line.long 0x00 "CTCOUNT,Current Transfer Count Register" hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current Frame Transfer Count" hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current Element Transfer Count" tree.end tree "Working Control Packet 4" group.long (0x0800+0x40)++0x07 line.long 0x00 "CSADDR,Current Source Address Register" line.long 0x04 "CDADDR,Current Destination Address Register" rgroup.long (0x0808+0x40)++0x03 line.long 0x00 "CTCOUNT,Current Transfer Count Register" hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current Frame Transfer Count" hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current Element Transfer Count" tree.end tree "Working Control Packet 5" group.long (0x0800+0x50)++0x07 line.long 0x00 "CSADDR,Current Source Address Register" line.long 0x04 "CDADDR,Current Destination Address Register" rgroup.long (0x0808+0x50)++0x03 line.long 0x00 "CTCOUNT,Current Transfer Count Register" hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current Frame Transfer Count" hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current Element Transfer Count" tree.end tree "Working Control Packet 6" group.long (0x0800+0x60)++0x07 line.long 0x00 "CSADDR,Current Source Address Register" line.long 0x04 "CDADDR,Current Destination Address Register" rgroup.long (0x0808+0x60)++0x03 line.long 0x00 "CTCOUNT,Current Transfer Count Register" hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current Frame Transfer Count" hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current Element Transfer Count" tree.end tree "Working Control Packet 7" group.long (0x0800+0x70)++0x07 line.long 0x00 "CSADDR,Current Source Address Register" line.long 0x04 "CDADDR,Current Destination Address Register" rgroup.long (0x0808+0x70)++0x03 line.long 0x00 "CTCOUNT,Current Transfer Count Register" hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current Frame Transfer Count" hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current Element Transfer Count" tree.end tree "Working Control Packet 8" group.long (0x0800+0x80)++0x07 line.long 0x00 "CSADDR,Current Source Address Register" line.long 0x04 "CDADDR,Current Destination Address Register" rgroup.long (0x0808+0x80)++0x03 line.long 0x00 "CTCOUNT,Current Transfer Count Register" hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current Frame Transfer Count" hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current Element Transfer Count" tree.end tree "Working Control Packet 9" group.long (0x0800+0x90)++0x07 line.long 0x00 "CSADDR,Current Source Address Register" line.long 0x04 "CDADDR,Current Destination Address Register" rgroup.long (0x0808+0x90)++0x03 line.long 0x00 "CTCOUNT,Current Transfer Count Register" hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current Frame Transfer Count" hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current Element Transfer Count" tree.end tree "Working Control Packet 10" group.long (0x0800+0xA0)++0x07 line.long 0x00 "CSADDR,Current Source Address Register" line.long 0x04 "CDADDR,Current Destination Address Register" rgroup.long (0x0808+0xA0)++0x03 line.long 0x00 "CTCOUNT,Current Transfer Count Register" hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current Frame Transfer Count" hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current Element Transfer Count" tree.end tree "Working Control Packet 11" group.long (0x0800+0xB0)++0x07 line.long 0x00 "CSADDR,Current Source Address Register" line.long 0x04 "CDADDR,Current Destination Address Register" rgroup.long (0x0808+0xB0)++0x03 line.long 0x00 "CTCOUNT,Current Transfer Count Register" hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current Frame Transfer Count" hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current Element Transfer Count" tree.end tree "Working Control Packet 12" group.long (0x0800+0xC0)++0x07 line.long 0x00 "CSADDR,Current Source Address Register" line.long 0x04 "CDADDR,Current Destination Address Register" rgroup.long (0x0808+0xC0)++0x03 line.long 0x00 "CTCOUNT,Current Transfer Count Register" hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current Frame Transfer Count" hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current Element Transfer Count" tree.end tree "Working Control Packet 13" group.long (0x0800+0xD0)++0x07 line.long 0x00 "CSADDR,Current Source Address Register" line.long 0x04 "CDADDR,Current Destination Address Register" rgroup.long (0x0808+0xD0)++0x03 line.long 0x00 "CTCOUNT,Current Transfer Count Register" hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current Frame Transfer Count" hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current Element Transfer Count" tree.end tree "Working Control Packet 14" group.long (0x0800+0xE0)++0x07 line.long 0x00 "CSADDR,Current Source Address Register" line.long 0x04 "CDADDR,Current Destination Address Register" rgroup.long (0x0808+0xE0)++0x03 line.long 0x00 "CTCOUNT,Current Transfer Count Register" hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current Frame Transfer Count" hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current Element Transfer Count" tree.end tree "Working Control Packet 15" group.long (0x0800+0xF0)++0x07 line.long 0x00 "CSADDR,Current Source Address Register" line.long 0x04 "CDADDR,Current Destination Address Register" rgroup.long (0x0808+0xF0)++0x03 line.long 0x00 "CTCOUNT,Current Transfer Count Register" hexmask.long.word 0x00 16.--28. 1. " CFTCOUNT ,Current Frame Transfer Count" hexmask.long.word 0x00 0.--12. 1. " CETCOUNT ,Current Element Transfer Count" tree.end tree.end tree.end width 0xb tree.end tree "EMIF (External Memory Interface)" base ad:0xFCFFE800 width 14. rgroup.long 0x00++0x03 line.long 0x00 "MIDR,Module ID Register" group.long 0x04++0x0B line.long 0x00 "AWCC,Asynchronous Wait Cycle Configuration Register" bitfld.long 0x00 29. " WP1 ,EMIF_nWAIT[1] polarity bit" "Low,High" bitfld.long 0x00 28. " WP0 ,EMIF_nWAIT[0] polarity bit" "Low,High" textline " " bitfld.long 0x00 20.--21. " CS4_WAIT ,Chip Select 4 WAIT signal selection" "nWAIT[0] pin,nWAIT[1] pin,?..." bitfld.long 0x00 18.--19. " CS3_WAIT ,Chip Select 3 WAIT signal selection" "nWAIT[0] pin,nWAIT[1] pin,?..." textline " " bitfld.long 0x00 16.--17. " CS2_WAIT ,Chip Select 2 WAIT signal selection" "nWAIT[0] pin,nWAIT[1] pin,?..." hexmask.long.byte 0x00 0.--7. 1. " MAX_EXT_WAIT ,Maximum extended wait cycles" line.long 0x04 "SDCR,SDRAM Configuration Register" bitfld.long 0x04 31. " SR ,Self-Refresh mode bit" "Disabled,Enabled" bitfld.long 0x04 30. " PD ,Power Down bit mode" "Disabled,Enabled" textline " " bitfld.long 0x04 29. " PDWR ,Perform refreshes during power down" "Not performed,Performed" bitfld.long 0x04 14. " NM ,Narrow mode bit" "32-bit,16-bit" textline " " bitfld.long 0x04 9.--11. " CL ,CAS Latency" ",2 EMIF_CLK,3 EMIF_CLK,?..." bitfld.long 0x04 8. " BIT11_9LOCK ,Bits 11 to 9 lock" "Not locked,Locked" textline " " bitfld.long 0x04 4.--6. " IBANK ,Internal SDRAM Bank size" "1 bank,2 bank,4 bank,?..." bitfld.long 0x04 0.--2. " PAGESIZE ,Internal page size of connected SDRAM devices" "8 column 256 elements,9 column 512 elements,10 column 1024 elements,11 column 2048 elements,?..." line.long 0x08 "SDRCR,SDRAM Refresh Control Register" hexmask.long.word 0x08 0.--12. 1. " RR ,Refresh Rate" group.long 0x10++0x0B line.long 0x0 "CE2CFG,Asynchronous 2 Configuration Registers" bitfld.long 0x0 31. " SS ,Select Strobe bit" "Normal,Strobe" bitfld.long 0x0 30. " EW ,Extend Wait bit" "Disabled,Enabled" textline " " bitfld.long 0x0 26.--29. " W_SETUP ,Write setup width in EMIF_CLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 20.--25. " W_STROBE ,Write strobe width in EMIF_CLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x0 17.--19. " W_HOLD ,Write hold width in EMIF_CLK cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x0 13.--16. " R_SETUP ,Read setup width in EMIF_CLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0 7.--12. " R_STROBE ,Read strobe width in EMIF_CLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x0 4.--6. " R_HOLD ,Read hold width in EMIF_CLK cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 2.--3. " TA ,Minimum Turn-Around time -" "0,1,2,3" bitfld.long 0x0 0.--1. " ASIZE ,Asynchronous Data Bus Width" "8-bit,16-bit,?..." line.long 0x4 "CE3CFG,Asynchronous 3 Configuration Registers" bitfld.long 0x4 31. " SS ,Select Strobe bit" "Normal,Strobe" bitfld.long 0x4 30. " EW ,Extend Wait bit" "Disabled,Enabled" textline " " bitfld.long 0x4 26.--29. " W_SETUP ,Write setup width in EMIF_CLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x4 20.--25. " W_STROBE ,Write strobe width in EMIF_CLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x4 17.--19. " W_HOLD ,Write hold width in EMIF_CLK cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x4 13.--16. " R_SETUP ,Read setup width in EMIF_CLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x4 7.--12. " R_STROBE ,Read strobe width in EMIF_CLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x4 4.--6. " R_HOLD ,Read hold width in EMIF_CLK cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x4 2.--3. " TA ,Minimum Turn-Around time -" "0,1,2,3" bitfld.long 0x4 0.--1. " ASIZE ,Asynchronous Data Bus Width" "8-bit,16-bit,?..." line.long 0x8 "CE4CFG,Asynchronous 4 Configuration Registers" bitfld.long 0x8 31. " SS ,Select Strobe bit" "Normal,Strobe" bitfld.long 0x8 30. " EW ,Extend Wait bit" "Disabled,Enabled" textline " " bitfld.long 0x8 26.--29. " W_SETUP ,Write setup width in EMIF_CLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x8 20.--25. " W_STROBE ,Write strobe width in EMIF_CLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x8 17.--19. " W_HOLD ,Write hold width in EMIF_CLK cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x8 13.--16. " R_SETUP ,Read setup width in EMIF_CLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x8 7.--12. " R_STROBE ,Read strobe width in EMIF_CLK cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x8 4.--6. " R_HOLD ,Read hold width in EMIF_CLK cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x8 2.--3. " TA ,Minimum Turn-Around time -" "0,1,2,3" bitfld.long 0x8 0.--1. " ASIZE ,Asynchronous Data Bus Width" "8-bit,16-bit,?..." group.long 0x20++0x03 line.long 0x00 "SDTIMR,SDRAM Timing Register" bitfld.long 0x00 27.--31. " T_RFC ,Specifies the Trfc value of the SDRAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 24.--26. " T_RP ,Specifies the Trp value of the SDRAM" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 20.--22. " T_RCD ,Specifies the Trcd value of the SDRAM" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " T_WR ,Specifies the Twr value of the SDRAM" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 12.--15. " T_RAS ,Specifies the Tras value of the SDRAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " T_RC ,Specifies the Trc value of the SDRAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 4.--6. " T_RRD ,Specifies the Trrd value of the SDRAM" "0,1,2,3,4,5,6,7" group.long 0x3C++0x07 line.long 0x00 "SDSRETR,SDRAM Self Refresh Exit Timing Register" bitfld.long 0x00 0.--4. " T_XS ,Specifies the minimum number of ECLKOUT cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "INTRAW,EMIF Interrupt Raw Register" eventfld.long 0x04 2. " WR ,Wait Rise" "Not occurred,Occurred" eventfld.long 0x04 1. " LT ,Line Trap" "No effect,Occurred" textline " " eventfld.long 0x04 0. " AT ,Asynchronous Timeout" "Not occurred,Occurred" group.long 0x44++0x03 line.long 0x00 "INTMSK,EMIF Interrupt Masked Register" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " WR_MASKED_set/clr ,Wait Rise Masked" "Not masked,Masked" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " WR_MASKED_set/clr ,Masked Line Trap" "Not masked,Masked" textline " " setclrfld.long 0x00 0. 0x04 0. 0x08 0. " WR_MASKED_set/clr ,Asynchronous Timeout Masked" "Not masked,Masked" group.long 0x68++0x03 line.long 0x00 "PMCR,Page Mode Control Register" bitfld.long 0x00 18.--23. " CS4_PG_DEL ,Page access delay for NOR Flash connected on CS4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 17. " CS4_PG_SIZE ,Page Size for NOR Flash connected on CS4" "4 words,8 words" textline " " bitfld.long 0x00 16. " CS4_PG_MD_EN ,Page Mode enable for NOR Flash connected on CS4" "Disabled,Enabled" bitfld.long 0x00 10.--15. " CS3_PG_DEL ,Page access delay for NOR Flash connected on CS3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 9. " CS3_PG_SIZE ,Page Size for NOR Flash connected on CS3" "4 words,8 words" bitfld.long 0x00 8. " CS3_PG_MD_EN ,Page Mode enable for NOR Flash connected on CS3" "Disabled,Enabled" textline " " bitfld.long 0x00 2.--7. " CS2_PG_DEL ,Page access delay for NOR Flash connected on CS2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 1. " CS2_PG_SIZE ,Page Size for NOR Flash connected on C2" "4 words,8 words" textline " " bitfld.long 0x00 0. " CS2_PG_MD_EN ,Page Mode enable for NOR Flash connected on CS2" "Disabled,Enabled" width 0xb tree.end endif sif (cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE") tree "POM (Parameter Overlay Module)" base ad:0xFFA04000 width 15. group.long 0x00++0x03 line.long 0x0 "GLBCTRL,Global Control Register" hexmask.long.word 0x00 23.--31. 0x80 " OTADDR ,Overlay target address" bitfld.long 0x00 8.--11. " ETO ,Enable timeout" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" newline sif cpuis("TMS570LS3137-EP") bitfld.long 0x00 0.--3. " ON/OFF ,Turn functionality on or off" "Off,Off,Off,Off,Off,On,Off,Off,Off,Off,On,Off,Off,Off,Off,Off" else bitfld.long 0x00 0.--3. " ON/OFF ,Turn functionality on or off" "Off,Off,Off,Off,Off,On,Off,Off,Off,Off,Off,Off,Off,Off,Off,Off" endif rgroup.long 0x04++0x03 line.long 0x0 "REV,Revision Id" bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between different ID schemes" "0,1,2,3" hexmask.long.word 0x00 16.--27. 1. " FUNC ,Indicates the SW compatible module family" newline bitfld.long 0x00 11.--15. " RTL ,RTL version number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 8.--10. " MAJOR ,Major revision number" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a device specific implementation" "0,1,2,3" bitfld.long 0x00 0.--5. " MINOR ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x08++0x07 line.long 0x00 "CLKCTRL,Clock Gate Control Register" bitfld.long 0x00 0. " CLK_GATE_OFF ,CLK gate off" "On,Off" line.long 0x04 "POMFLG,Flag Register" eventfld.long 0x04 0. " TO ,Timeout" "Not occurred,Occurred" group.long 0x200++0x0B line.long 0x00 "PROGSTART0,Program Region Start Address Register 0" hexmask.long.tbyte 0x00 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the program memory region" line.long 0x04 "OVLSTART0,Overlay Region Start Address Register 0" hexmask.long.tbyte 0x04 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the overlay memory region" sif cpuis("TMS570LS3137-EP") line.long 0x08 "REGSIZE0,Region Size Register 0" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB,?..." else line.long 0x08 "REGSIZE0,Region Size Register 0" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,,,,,,,,128kB,256kB,?..." endif group.long 0x210++0x0B line.long 0x00 "PROGSTART1,Program Region Start Address Register 1" hexmask.long.tbyte 0x00 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the program memory region" line.long 0x04 "OVLSTART1,Overlay Region Start Address Register 1" hexmask.long.tbyte 0x04 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the overlay memory region" sif cpuis("TMS570LS3137-EP") line.long 0x08 "REGSIZE1,Region Size Register 1" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB,?..." else line.long 0x08 "REGSIZE1,Region Size Register 1" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,,,,,,,,128kB,256kB,?..." endif group.long 0x220++0x0B line.long 0x00 "PROGSTART2,Program Region Start Address Register 2" hexmask.long.tbyte 0x00 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the program memory region" line.long 0x04 "OVLSTART2,Overlay Region Start Address Register 2" hexmask.long.tbyte 0x04 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the overlay memory region" sif cpuis("TMS570LS3137-EP") line.long 0x08 "REGSIZE2,Region Size Register 2" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB,?..." else line.long 0x08 "REGSIZE2,Region Size Register 2" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,,,,,,,,128kB,256kB,?..." endif group.long 0x230++0x0B line.long 0x00 "PROGSTART3,Program Region Start Address Register 3" hexmask.long.tbyte 0x00 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the program memory region" line.long 0x04 "OVLSTART3,Overlay Region Start Address Register 3" hexmask.long.tbyte 0x04 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the overlay memory region" sif cpuis("TMS570LS3137-EP") line.long 0x08 "REGSIZE3,Region Size Register 3" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB,?..." else line.long 0x08 "REGSIZE3,Region Size Register 3" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,,,,,,,,128kB,256kB,?..." endif group.long 0x240++0x0B line.long 0x00 "PROGSTART4,Program Region Start Address Register 4" hexmask.long.tbyte 0x00 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the program memory region" line.long 0x04 "OVLSTART4,Overlay Region Start Address Register 4" hexmask.long.tbyte 0x04 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the overlay memory region" sif cpuis("TMS570LS3137-EP") line.long 0x08 "REGSIZE4,Region Size Register 4" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB,?..." else line.long 0x08 "REGSIZE4,Region Size Register 4" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,,,,,,,,128kB,256kB,?..." endif group.long 0x250++0x0B line.long 0x00 "PROGSTART5,Program Region Start Address Register 5" hexmask.long.tbyte 0x00 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the program memory region" line.long 0x04 "OVLSTART5,Overlay Region Start Address Register 5" hexmask.long.tbyte 0x04 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the overlay memory region" sif cpuis("TMS570LS3137-EP") line.long 0x08 "REGSIZE5,Region Size Register 5" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB,?..." else line.long 0x08 "REGSIZE5,Region Size Register 5" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,,,,,,,,128kB,256kB,?..." endif group.long 0x260++0x0B line.long 0x00 "PROGSTART6,Program Region Start Address Register 6" hexmask.long.tbyte 0x00 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the program memory region" line.long 0x04 "OVLSTART6,Overlay Region Start Address Register 6" hexmask.long.tbyte 0x04 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the overlay memory region" sif cpuis("TMS570LS3137-EP") line.long 0x08 "REGSIZE6,Region Size Register 6" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB,?..." else line.long 0x08 "REGSIZE6,Region Size Register 6" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,,,,,,,,128kB,256kB,?..." endif group.long 0x270++0x0B line.long 0x00 "PROGSTART7,Program Region Start Address Register 7" hexmask.long.tbyte 0x00 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the program memory region" line.long 0x04 "OVLSTART7,Overlay Region Start Address Register 7" hexmask.long.tbyte 0x04 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the overlay memory region" sif cpuis("TMS570LS3137-EP") line.long 0x08 "REGSIZE7,Region Size Register 7" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB,?..." else line.long 0x08 "REGSIZE7,Region Size Register 7" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,,,,,,,,128kB,256kB,?..." endif group.long 0x280++0x0B line.long 0x00 "PROGSTART8,Program Region Start Address Register 8" hexmask.long.tbyte 0x00 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the program memory region" line.long 0x04 "OVLSTART8,Overlay Region Start Address Register 8" hexmask.long.tbyte 0x04 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the overlay memory region" sif cpuis("TMS570LS3137-EP") line.long 0x08 "REGSIZE8,Region Size Register 8" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB,?..." else line.long 0x08 "REGSIZE8,Region Size Register 8" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,,,,,,,,128kB,256kB,?..." endif group.long 0x290++0x0B line.long 0x00 "PROGSTART9,Program Region Start Address Register 9" hexmask.long.tbyte 0x00 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the program memory region" line.long 0x04 "OVLSTART9,Overlay Region Start Address Register 9" hexmask.long.tbyte 0x04 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the overlay memory region" sif cpuis("TMS570LS3137-EP") line.long 0x08 "REGSIZE9,Region Size Register 9" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB,?..." else line.long 0x08 "REGSIZE9,Region Size Register 9" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,,,,,,,,128kB,256kB,?..." endif group.long 0x2A0++0x0B line.long 0x00 "PROGSTART10,Program Region Start Address Register 10" hexmask.long.tbyte 0x00 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the program memory region" line.long 0x04 "OVLSTART10,Overlay Region Start Address Register 10" hexmask.long.tbyte 0x04 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the overlay memory region" sif cpuis("TMS570LS3137-EP") line.long 0x08 "REGSIZE10,Region Size Register 10" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB,?..." else line.long 0x08 "REGSIZE10,Region Size Register 10" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,,,,,,,,128kB,256kB,?..." endif group.long 0x2B0++0x0B line.long 0x00 "PROGSTART11,Program Region Start Address Register 11" hexmask.long.tbyte 0x00 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the program memory region" line.long 0x04 "OVLSTART11,Overlay Region Start Address Register 11" hexmask.long.tbyte 0x04 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the overlay memory region" sif cpuis("TMS570LS3137-EP") line.long 0x08 "REGSIZE11,Region Size Register 11" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB,?..." else line.long 0x08 "REGSIZE11,Region Size Register 11" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,,,,,,,,128kB,256kB,?..." endif group.long 0x2C0++0x0B line.long 0x00 "PROGSTART12,Program Region Start Address Register 12" hexmask.long.tbyte 0x00 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the program memory region" line.long 0x04 "OVLSTART12,Overlay Region Start Address Register 12" hexmask.long.tbyte 0x04 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the overlay memory region" sif cpuis("TMS570LS3137-EP") line.long 0x08 "REGSIZE12,Region Size Register 12" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB,?..." else line.long 0x08 "REGSIZE12,Region Size Register 12" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,,,,,,,,128kB,256kB,?..." endif group.long 0x2D0++0x0B line.long 0x00 "PROGSTART13,Program Region Start Address Register 13" hexmask.long.tbyte 0x00 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the program memory region" line.long 0x04 "OVLSTART13,Overlay Region Start Address Register 13" hexmask.long.tbyte 0x04 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the overlay memory region" sif cpuis("TMS570LS3137-EP") line.long 0x08 "REGSIZE13,Region Size Register 13" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB,?..." else line.long 0x08 "REGSIZE13,Region Size Register 13" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,,,,,,,,128kB,256kB,?..." endif group.long 0x2E0++0x0B line.long 0x00 "PROGSTART14,Program Region Start Address Register 14" hexmask.long.tbyte 0x00 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the program memory region" line.long 0x04 "OVLSTART14,Overlay Region Start Address Register 14" hexmask.long.tbyte 0x04 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the overlay memory region" sif cpuis("TMS570LS3137-EP") line.long 0x08 "REGSIZE14,Region Size Register 14" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB,?..." else line.long 0x08 "REGSIZE14,Region Size Register 14" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,,,,,,,,128kB,256kB,?..." endif group.long 0x2F0++0x0B line.long 0x00 "PROGSTART15,Program Region Start Address Register 15" hexmask.long.tbyte 0x00 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the program memory region" line.long 0x04 "OVLSTART15,Overlay Region Start Address Register 15" hexmask.long.tbyte 0x04 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the overlay memory region" sif cpuis("TMS570LS3137-EP") line.long 0x08 "REGSIZE15,Region Size Register 15" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB,?..." else line.long 0x08 "REGSIZE15,Region Size Register 15" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,,,,,,,,128kB,256kB,?..." endif group.long 0x300++0x0B line.long 0x00 "PROGSTART16,Program Region Start Address Register 16" hexmask.long.tbyte 0x00 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the program memory region" line.long 0x04 "OVLSTART16,Overlay Region Start Address Register 16" hexmask.long.tbyte 0x04 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the overlay memory region" sif cpuis("TMS570LS3137-EP") line.long 0x08 "REGSIZE16,Region Size Register 16" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB,?..." else line.long 0x08 "REGSIZE16,Region Size Register 16" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,,,,,,,,128kB,256kB,?..." endif group.long 0x310++0x0B line.long 0x00 "PROGSTART17,Program Region Start Address Register 17" hexmask.long.tbyte 0x00 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the program memory region" line.long 0x04 "OVLSTART17,Overlay Region Start Address Register 17" hexmask.long.tbyte 0x04 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the overlay memory region" sif cpuis("TMS570LS3137-EP") line.long 0x08 "REGSIZE17,Region Size Register 17" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB,?..." else line.long 0x08 "REGSIZE17,Region Size Register 17" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,,,,,,,,128kB,256kB,?..." endif group.long 0x320++0x0B line.long 0x00 "PROGSTART18,Program Region Start Address Register 18" hexmask.long.tbyte 0x00 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the program memory region" line.long 0x04 "OVLSTART18,Overlay Region Start Address Register 18" hexmask.long.tbyte 0x04 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the overlay memory region" sif cpuis("TMS570LS3137-EP") line.long 0x08 "REGSIZE18,Region Size Register 18" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB,?..." else line.long 0x08 "REGSIZE18,Region Size Register 18" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,,,,,,,,128kB,256kB,?..." endif group.long 0x330++0x0B line.long 0x00 "PROGSTART19,Program Region Start Address Register 19" hexmask.long.tbyte 0x00 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the program memory region" line.long 0x04 "OVLSTART19,Overlay Region Start Address Register 19" hexmask.long.tbyte 0x04 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the overlay memory region" sif cpuis("TMS570LS3137-EP") line.long 0x08 "REGSIZE19,Region Size Register 19" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB,?..." else line.long 0x08 "REGSIZE19,Region Size Register 19" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,,,,,,,,128kB,256kB,?..." endif group.long 0x340++0x0B line.long 0x00 "PROGSTART20,Program Region Start Address Register 20" hexmask.long.tbyte 0x00 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the program memory region" line.long 0x04 "OVLSTART20,Overlay Region Start Address Register 20" hexmask.long.tbyte 0x04 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the overlay memory region" sif cpuis("TMS570LS3137-EP") line.long 0x08 "REGSIZE20,Region Size Register 20" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB,?..." else line.long 0x08 "REGSIZE20,Region Size Register 20" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,,,,,,,,128kB,256kB,?..." endif group.long 0x350++0x0B line.long 0x00 "PROGSTART21,Program Region Start Address Register 21" hexmask.long.tbyte 0x00 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the program memory region" line.long 0x04 "OVLSTART21,Overlay Region Start Address Register 21" hexmask.long.tbyte 0x04 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the overlay memory region" sif cpuis("TMS570LS3137-EP") line.long 0x08 "REGSIZE21,Region Size Register 21" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB,?..." else line.long 0x08 "REGSIZE21,Region Size Register 21" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,,,,,,,,128kB,256kB,?..." endif group.long 0x360++0x0B line.long 0x00 "PROGSTART22,Program Region Start Address Register 22" hexmask.long.tbyte 0x00 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the program memory region" line.long 0x04 "OVLSTART22,Overlay Region Start Address Register 22" hexmask.long.tbyte 0x04 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the overlay memory region" sif cpuis("TMS570LS3137-EP") line.long 0x08 "REGSIZE22,Region Size Register 22" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB,?..." else line.long 0x08 "REGSIZE22,Region Size Register 22" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,,,,,,,,128kB,256kB,?..." endif group.long 0x370++0x0B line.long 0x00 "PROGSTART23,Program Region Start Address Register 23" hexmask.long.tbyte 0x00 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the program memory region" line.long 0x04 "OVLSTART23,Overlay Region Start Address Register 23" hexmask.long.tbyte 0x04 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the overlay memory region" sif cpuis("TMS570LS3137-EP") line.long 0x08 "REGSIZE23,Region Size Register 23" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB,?..." else line.long 0x08 "REGSIZE23,Region Size Register 23" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,,,,,,,,128kB,256kB,?..." endif group.long 0x380++0x0B line.long 0x00 "PROGSTART24,Program Region Start Address Register 24" hexmask.long.tbyte 0x00 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the program memory region" line.long 0x04 "OVLSTART24,Overlay Region Start Address Register 24" hexmask.long.tbyte 0x04 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the overlay memory region" sif cpuis("TMS570LS3137-EP") line.long 0x08 "REGSIZE24,Region Size Register 24" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB,?..." else line.long 0x08 "REGSIZE24,Region Size Register 24" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,,,,,,,,128kB,256kB,?..." endif group.long 0x390++0x0B line.long 0x00 "PROGSTART25,Program Region Start Address Register 25" hexmask.long.tbyte 0x00 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the program memory region" line.long 0x04 "OVLSTART25,Overlay Region Start Address Register 25" hexmask.long.tbyte 0x04 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the overlay memory region" sif cpuis("TMS570LS3137-EP") line.long 0x08 "REGSIZE25,Region Size Register 25" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB,?..." else line.long 0x08 "REGSIZE25,Region Size Register 25" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,,,,,,,,128kB,256kB,?..." endif group.long 0x3A0++0x0B line.long 0x00 "PROGSTART26,Program Region Start Address Register 26" hexmask.long.tbyte 0x00 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the program memory region" line.long 0x04 "OVLSTART26,Overlay Region Start Address Register 26" hexmask.long.tbyte 0x04 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the overlay memory region" sif cpuis("TMS570LS3137-EP") line.long 0x08 "REGSIZE26,Region Size Register 26" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB,?..." else line.long 0x08 "REGSIZE26,Region Size Register 26" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,,,,,,,,128kB,256kB,?..." endif group.long 0x3B0++0x0B line.long 0x00 "PROGSTART27,Program Region Start Address Register 27" hexmask.long.tbyte 0x00 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the program memory region" line.long 0x04 "OVLSTART27,Overlay Region Start Address Register 27" hexmask.long.tbyte 0x04 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the overlay memory region" sif cpuis("TMS570LS3137-EP") line.long 0x08 "REGSIZE27,Region Size Register 27" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB,?..." else line.long 0x08 "REGSIZE27,Region Size Register 27" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,,,,,,,,128kB,256kB,?..." endif group.long 0x3C0++0x0B line.long 0x00 "PROGSTART28,Program Region Start Address Register 28" hexmask.long.tbyte 0x00 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the program memory region" line.long 0x04 "OVLSTART28,Overlay Region Start Address Register 28" hexmask.long.tbyte 0x04 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the overlay memory region" sif cpuis("TMS570LS3137-EP") line.long 0x08 "REGSIZE28,Region Size Register 28" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB,?..." else line.long 0x08 "REGSIZE28,Region Size Register 28" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,,,,,,,,128kB,256kB,?..." endif group.long 0x3D0++0x0B line.long 0x00 "PROGSTART29,Program Region Start Address Register 29" hexmask.long.tbyte 0x00 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the program memory region" line.long 0x04 "OVLSTART29,Overlay Region Start Address Register 29" hexmask.long.tbyte 0x04 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the overlay memory region" sif cpuis("TMS570LS3137-EP") line.long 0x08 "REGSIZE29,Region Size Register 29" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB,?..." else line.long 0x08 "REGSIZE29,Region Size Register 29" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,,,,,,,,128kB,256kB,?..." endif group.long 0x3E0++0x0B line.long 0x00 "PROGSTART30,Program Region Start Address Register 30" hexmask.long.tbyte 0x00 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the program memory region" line.long 0x04 "OVLSTART30,Overlay Region Start Address Register 30" hexmask.long.tbyte 0x04 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the overlay memory region" sif cpuis("TMS570LS3137-EP") line.long 0x08 "REGSIZE30,Region Size Register 30" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB,?..." else line.long 0x08 "REGSIZE30,Region Size Register 30" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,,,,,,,,128kB,256kB,?..." endif group.long 0x3F0++0x0B line.long 0x00 "PROGSTART31,Program Region Start Address Register 31" hexmask.long.tbyte 0x00 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the program memory region" line.long 0x04 "OVLSTART31,Overlay Region Start Address Register 31" hexmask.long.tbyte 0x04 0.--22. 0x01 " STARTADDRESS ,Defines the start address of the overlay memory region" sif cpuis("TMS570LS3137-EP") line.long 0x08 "REGSIZE31,Region Size Register 31" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,1kB,2kB,4kB,8kB,16kB,32kB,64kB,128kB,256kB,?..." else line.long 0x08 "REGSIZE31,Region Size Register 31" bitfld.long 0x08 0.--3. " SIZE ,Region size" "Disabled,64B,128B,256B,512B,,,,,,,,128kB,256kB,?..." endif hgroup.long 0xF00++0x03 hide.long 0x00 "ITCTRL,Integration Control Register" group.long 0xFA0++0x03 line.long 0x00 "CLAIMSET,Claim Set Register" setclrfld.long 0x00 1. 0x00 1. 0x04 1. " SET1/CLR1 ,The module is claimed" "No,Yes" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " SET0/CLR0 ,The module is claimed" "No,Yes" hgroup.long 0xFB0++0x03 hide.long 0x00 "LOCKACCESS,Lock Access Register" hgroup.long 0xFB4++0x03 hide.long 0x00 "LOCKSTATUS,Lock Status Register" hgroup.long 0xFB8++0x03 hide.long 0x00 "AUTHSTATUS,Authentication Status Register" hgroup.long 0xFC8++0x03 hide.long 0x00 "DEVID,Device ID Register" rgroup.long 0xFCC++0x07 line.long 0x00 "DEVTYPE,Device Type Register" bitfld.long 0x00 4.--7. " SUB_TYPE ,Sub type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " MAJOR_TYPE ,Major type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "PERIPHERALID4,Peripheral ID 4 Register" bitfld.long 0x04 4.--7. " 4KB_COUNT ,4KB count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " JEP106_CC ,JEP106 continuation code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hgroup.long 0xFD4++0x03 hide.long 0x00 "PERIPHERALID5,Peripheral ID 5 Register" hgroup.long 0xFD8++0x03 hide.long 0x00 "PERIPHERALID6,Peripheral ID 6 Register" hgroup.long 0xFDC++0x03 hide.long 0x00 "PERIPHERALID7,Peripheral ID 7 Register" rgroup.long 0xFE0++0x0B line.long 0x00 "PERIPHERALID0,POM Peripheral ID 0 Register" hexmask.long.byte 0x00 0.--7. 1. " PART_NO ,Part number" line.long 0x04 "PERIPHERALID1,POM Peripheral ID 1 Register" bitfld.long 0x04 4.--7. " JEP106_ID_C ,Part of TI JEDEC number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " PART_NO ,Part number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "PERIPHERALID2,POM Peripheral ID 2 Register" bitfld.long 0x08 3. " JEDEC ,Indicates JEDEC assigned value" "Not indicated,Indicated" bitfld.long 0x08 0.--2. " JEP106_ID_C ,JEDEC+JEP106 identity code" "0,1,2,3,4,5,6,7" hgroup.long 0xFEC++0x03 hide.long 0x00 "PERIPHERALID3,Peripheral ID 3 Register" rgroup.long 0xFF0++0x0F line.long 0x00 "COMPONENTID0,Component ID 0 Register" hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble" line.long 0x04 "COMPONENTID1,Component ID 1 Register" bitfld.long 0x04 4.--7. " COMPONENT_CLASS ,CoreSight component" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " PREAMBLE ,Preamble" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "COMPONENTID2,Component ID 2 Register" hexmask.long.byte 0x08 0.--7. 1. " PREAMBLE ,Preamble" line.long 0x0C "COMPONENTID3,Component ID 3 Register" hexmask.long.byte 0x0C 0.--7. 1. " PREAMBLE ,Preamble" width 0x0B tree.end tree.open "ePWM (Enhanced Pulse Width Modulator)" tree "ePWM 1" base ad:0xFCF78C00 width 14. tree "Time-Base Submodule Registers" group.word 0x0A++0x01 line.word 0x00 "TBPRD,Time-Base Period Register" group.word 0x06++0x03 line.word 0x00 "TBPHS,Time-Base Phase Register" line.word 0x02 "TBCTR,Time-Base Counter Register" group.word 0x00++0x03 line.word 0x00 "TBCTL,Time-Base Control Register" bitfld.word 0x00 14.--15. " FREE/SOFT ,Emulation Mode Bits" "Stop after the next time-base counter INC or DEC,Stop when counter completes a whole cycle,Free run,Free run" textline " " bitfld.word 0x00 13. " PHSDIR ,Phase Direction Bit" "Count down,Count up" bitfld.word 0x00 10.--12. " CLKDIV ,Time-base Clock Prescale Bits" "/1,/2,/4,/8,/16,/32,/64,/128" textline " " bitfld.word 0x00 7.--9. " HSPCLKDIV ,High Speed Time-base Clock Prescale Bits" "/1,/2,/4,/8,/8,/10,/12,/14" bitfld.word 0x00 6. " SWFSYNC ,Software Forced Synchronization Pulse" "No effect,Generated" textline " " bitfld.word 0x00 4.--5. " SYNCOSEL ,Synchronization Output Select" "EPWMxSYNC,CTR = zero,CTR = CMPB,EPWMxSYNCO disable" bitfld.word 0x00 3. " PRDLD ,Active Period Register Load From Shadow Register Select" "Not selected,Selected" bitfld.word 0x00 2. " PHSEN ,Counter Register Load From Phase Register Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0.--1. " CTRMODE ,Counter Mode" "Up-count,Down-count,Up-down-count,Stop-freeze counter operation" line.word 0x02 "TBSTS,Time-Base Status Register" bitfld.word 0x02 2. " CTRMAX ,Time-Base Counter Max Latched Status Bit time-base counter maximum value" "Not reached,Reached" bitfld.word 0x02 1. " SYNCI ,Input Synchronization Latched Status Bit external synchronization event" "Not occurred,Occurred" textline " " bitfld.word 0x02 0. " CTRDIR ,Time-Base Counter Direction Status Bit" "Down,Up" tree.end width 8. tree "Counter-Compare Submodule Registers" group.word 0x12++0x03 line.word 0x00 "CMPA,Counter-Compare A Register" line.word 0x02 "CMPB,Counter-Compare B Register" group.word 0x0E++0x1 line.word 0x00 "CMPCTL,Counter-Compare Control Register" bitfld.word 0x00 9. " SHDWBFULL ,Counter-compare B CMPB Shadow Register Full Status Flag" "Not full,Full" bitfld.word 0x00 8. " SHDWAFULL ,Counter-compare A CMPA Shadow Register Full Status Flag" "Not full,Full" textline " " bitfld.word 0x00 6. " SHDWBMODE ,Counter-compare B CMPB Register Operating Mode" "Shadow,Immediate" bitfld.word 0x00 4. " SHDWAMODE ,Counter-compare A CMPA Register Operating Mode" "Shadow,Immediate" textline " " bitfld.word 0x00 2.--3. " LOADBMODE ,Active Counter-Compare B CMPB Load From Shadow Select Mode" "CTR = Zero,CTR = PRD,CTR = Zero or CTR = PRD,Freeze" bitfld.word 0x00 0.--1. " LOADAMODE ,Active Counter-Compare A CMPA Load From Shadow Select Mode" "CTR = Zero,CTR = PRD,CTR = Zero or CTR = PRD,Freeze" tree.end width 9. tree "Action-Qualifier Submodule Registers" group.word 0x16++0x07 line.word 0x00 "AQCTLA,Action-Qualifier Output A Control Register" bitfld.word 0x00 10.--11. " CBD ,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "Disabled,Cleared,Set,Toggled" bitfld.word 0x00 8.--9. " CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,Cleared,Set,Toggled" textline " " bitfld.word 0x00 6.--7. " CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,Cleared,Set,Toggled" bitfld.word 0x00 4.--5. " CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,Cleared,Set,Toggled" textline " " bitfld.word 0x00 2.--3. " PRD ,Action when the counter equals the period" "Disabled,Cleared,Set,Toggled" bitfld.word 0x00 0.--1. " ZRO ,Action when counter equals zero" "Disabled,Cleared,Set,Toggled" line.word 0x02 "AQCTLB,Action-Qualifier Output B Control Register" bitfld.word 0x02 10.--11. " CBD ,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "Disabled,Cleared,Set,Toggled" bitfld.word 0x02 8.--9. " CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,Cleared,Set,Toggled" textline " " bitfld.word 0x02 6.--7. " CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,Cleared,Set,Toggled" bitfld.word 0x02 4.--5. " CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,Cleared,Set,Toggled" textline " " bitfld.word 0x02 2.--3. " PRD ,Action when the counter equals the period" "Disabled,Cleared,Set,Toggled" bitfld.word 0x02 0.--1. " ZRO ,Action when counter equals zero" "Disabled,Cleared,Set,Toggled" line.word 0x04 "AQSFRC,Action-Qualifier Software Force Register" bitfld.word 0x04 6.--7. " RLDCSF ,AQCSFRC Active Register Reload From Shadow Options" "Zero,Period,Zero or Period,Immediately" bitfld.word 0x04 5. " OTSFB ,One-Time Software Forced Event on Output B" "No effect,Forced" textline " " bitfld.word 0x04 3.--4. " ACTSFB ,Action when One-Time Software Force B Is invoked" "Disabled,Cleared,Set,Toggled" bitfld.word 0x04 2. " OTSFA ,One-Time Software Forced Event on Output A" "No effect,Forced" textline " " bitfld.word 0x04 0.--1. " ACTSFA ,Action When One-Time Software Force A Is Invoked" "Disabled,Cleared,Set,Toggled" line.word 0x06 "AQCSFRC,Action-Qualifier Continuous Software Force Register" bitfld.word 0x06 2.--3. " CSFB ,Continuous Software Force on Output B" "Forced disabled,Continued low,Continued high,Soft forced disabled" bitfld.word 0x06 0.--1. " CSFA ,Continuous Software Force on Output A" "Forced disabled,Continued low,Continued high,Soft forced disabled" tree.end width 7. tree "Dead-Band Submodule Registers" group.word 0x1E++0x05 line.word 0x00 "DBCTL,Dead-Band Generator Control Register" bitfld.word 0x00 15. " HALFCYCLE ,Half Cycle Clocking Enable Bit" "Disabled,Enabled" textline " " bitfld.word 0x00 4.--5. " IN_MODE ,Dead Band Input Mode Control" "EPWMxA Faling/rising,EPWMxB rising / EPWMxA falling,EPWMxA rising / EPWMxB falling,EPWMxB both rising & falling" textline " " bitfld.word 0x00 2.--3. " POLSEL ,Polarity Select Control" "AH,ALC,AHC,AL" textline " " bitfld.word 0x00 0.--1. " OUT_MODE ,Dead-band Output Mode Control" "Dead-band generation bypassed,Disabled rising-edge delay,Rising-edge delayed signal on EPWMxA,Dead-band fully enabled" line.word 0x02 "DBRED,Dead-Band Generator Rising Edge Delay Register" hexmask.word 0x02 0.--9. 1. " DEL ,Rising Edge Delay Count" line.word 0x04 "DBFED,Dead-Band Generator Falling Edge Delay Register" hexmask.word 0x04 0.--9. 1. " DEL ,Falling Edge Delay Count" tree.end width 0x7 tree "PWM-Chopper Submodule Control Register" group.word 0x3C++0x01 line.word 0x00 "PCCTL,PWM-Chopper Control Register" bitfld.word 0x00 8.--10. " CHPDUTY ,Chopping Clock Duty Cycle" "1/8 (12.5%),2/8 (25.0%),3/8 (37.5%),4/8 (50.0%),5/8 (62.5%),6/8 (75.0%),7/8 (87.5%),?..." textline " " bitfld.word 0x00 5.--7. " CHPFREQ ,Chopping Clock Frequency" "/1 (no prescale = 12.5 MHz at 100 MHz VCLK4),/2 (6.25 MHz at 100 MHz VCLK4),/3 (4.16 MHz at 100 MHz VCLK4),/4 (3.12 MHz at 100 MHz VCLK4),/5 (2.50 MHz at 100 MHz VCLK4),/6 (2.08 MHz at 100 MHz VCLK4),/7 (1.78 MHz at 100 MHz VCLK4),/8 (1.56 MHz at 100 MHz VCLK4)" textline " " bitfld.word 0x00 1.--4. " OSHTWTH ,One-Shot Pulse Width" "1 x VCLK4 / 8 wide ( = 80 nS at 100 MHz VCLK4),2 x VCLK4 / 8 wide ( = 160 nS at 100 MHz VCLK4),3 x VCLK4 / 8 wide ( = 240 nS at 100 MHz VCLK4),4 x VCLK4 / 8 wide ( = 320 nS at 100 MHz VCLK4),5 x VCLK4 / 8 wide ( = 400 nS at 100 MHz VCLK4),6 x VCLK4 / 8 wide ( = 480 nS at 100 MHz VCLK4),7 x VCLK4 / 8 wide ( = 560 nS at 100 MHz VCLK4),8 x VCLK4 / 8 wide ( = 640 nS at 100 MHz VCLK4),9 x VCLK4 / 8 wide ( = 720 nS at 100 MHz VCLK4),10 x VCLK4 / 8 wide ( = 800 nS at 100 MHz VCLK4),11 x VCLK4 / 8 wide ( = 880 nS at 100 MHz VCLK4),12 x VCLK4 / 8 wide ( = 960 nS at 100 MHz VCLK4),13 x VCLK4 / 8 wide ( = 1040 nS at 100 MHz VCLK4),14 x VCLK4 / 8 wide ( = 1120 nS at 100 MHz VCLK4),15 x VCLK4 / 8 wide ( = 1200 nS at 100 MHz VCLK4),16 x VCLK4 / 8 wide ( = 1280 nS at 100 MHz VCLK4)" textline " " bitfld.word 0x00 0. " CHPEN ,PWM-chopping Enable" "Disabled,Enabled" tree.end width 9. tree "Trip-Zone Select Register" group.word 0x24++0x01 line.word 0x00 "TZSEL,Trip-Zone Submodule Control and Status Registers" bitfld.word 0x00 15. " DCBEVT1 ,Digital Compare Output B Event 1 Select" "Disabled,Enabled" bitfld.word 0x00 14. " DCAEVT1 ,Digital Compare Output A Event 1 Select" "Disabled,Enabled" bitfld.word 0x00 13. " OSHT6 ,Trip-zone 6 TZ6 Select" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " OSHT5 ,Trip-zone 5 TZ5 Select" "Disabled,Enabled" bitfld.word 0x00 11. " OSHT4 ,Trip-zone 4 TZ4 Select" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OSHT3 ,Trip-zone 3 TZ3 Select" "Disabled,Enabled" bitfld.word 0x00 9. " OSHT2 ,Trip-zone 2 TZ2 Select" "Disabled,Enabled" bitfld.word 0x00 8. " OSHT1 ,Trip-zone 1 TZ) Select" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " DCBEVT2 ,Digital Compare Output B Event 2 Select" "Disabled,Enabled" bitfld.word 0x00 6. " DCAEVT2 ,Digital Compare Output A Event 2 Select" "Disabled,Enabled" bitfld.word 0x00 5. " CBC6 ,Trip-zone 6 TZ6 Select" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " CBC5 ,Trip-zone 5 TZ5 Select" "Disabled,Enabled" bitfld.word 0x00 3. " CBC4 ,Trip-zone 4 TZ4 Select" "Disabled,Enabled" bitfld.word 0x00 2. " CBC3 ,Trip-zone 3 TZ3 Select" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " CBC2 ,Trip-zone 2 TZ2 Select" "Disabled,Enabled" bitfld.word 0x00 0. " CBC1 ,Trip-zone 1 TZ1 Select" "Disabled,Enabled" group.word 0x28++0x01 line.word 0x00 "TZCTL,Trip-Zone Control Register" bitfld.word 0x00 10.--11. " DCBEVT2 ,Digital Compare Output B Event 2 Action On EPWMxB" "High-impedance,High state,Low state,Disabled" bitfld.word 0x00 8.--9. " DCBEVT1 ,Digital Compare Output B Event 1 Action On EPWMxB" "High-impedance,Forced high state,Forced low state,Disabled" textline " " bitfld.word 0x00 6.--7. " DCAEVT2 ,Digital Compare Output A Event 2 Action On EPWMxA" "High-impedance,Forced high state,Forced low state,Disabled" bitfld.word 0x00 4.--5. " DCAEVT1 ,Digital Compare Output A Event 1 Action On EPWMxA" "High-impedance,Forced high state,Forced low state,Disabled" textline " " bitfld.word 0x00 2.--3. " TZB ,When a trip event occurs the following action is taken on output EPWMxB" "High-impedance,Forced high state,Forced low state,Disabled" bitfld.word 0x00 0.--1. " TZA ,When a trip event occurs the following action is taken on output EPWMxA" "High-impedance,Forced high state,Forced low state,Disabled" group.word 0x2C++0x01 line.word 0x00 "TZFLG,Trip-Zone Flag Register Field Descriptions" setclrfld.word 0x00 6. -0x02 6. 0x02 6. " DCBEVT2_set/clr ,Digital Comparator Output B Event 2 Interrupt" "Not occurred,Occurred" setclrfld.word 0x00 5. -0x02 5. 0x02 5. " DCBEVT1_set/clr ,Digital Comparator Output B Event 1 Interrupt" "Not occurred,Occurred" textline " " setclrfld.word 0x00 4. -0x02 4. 0x02 4. " DCAEVT2_set/clr ,Digital Comparator Output A Event 2 Interrupt" "Not occurred,Occurred" setclrfld.word 0x00 3. -0x02 3. 0x02 3. " DCAEVT1_set/clr ,Digital Comparator Output A Event 1 Interrupt" "Not occurred,Occurred" textline " " setclrfld.word 0x00 2. -0x02 2. 0x02 2. " OST_set/clr ,Trip-zone One-Shot Interrupt" "Not occurred,Occurred" setclrfld.word 0x00 1. -0x02 1. 0x02 1. " CBC_set/clr ,Trip-zone Cycle-by-Cycle Interrupt" "Not occurred,Occurred" textline " " setclrfld.word 0x00 0. 0x00 0. 0x02 0. " INT_set/clr ,Latched Trip Interrupt Status Flag" "Not generated,Generated" group.word 0x30++0x01 line.word 0x00 "TZFRC,Trip-Zone Force Register" bitfld.word 0x00 6. " DCBEVT2 ,Force Flag for Digital Compare Output B Event 2" "No effect,Forced" bitfld.word 0x00 5. " DCBEVT1 ,Force Flag for Digital Compare Output B Event 1" "No effect,Forced" textline " " bitfld.word 0x00 4. " DCAEVT2 ,Force Flag for Digital Compare Output A Event 2" "No effect,Forced" bitfld.word 0x00 3. " DCAEVT1 ,Force Flag for Digital Compare Output A Event 1" "No effect,Forced" textline " " bitfld.word 0x00 2. " OST ,Force a One-Shot Trip Event via Software" "No effect,Forced" bitfld.word 0x00 1. " CBC ,Force a Cycle-by-Cycle Trip Event via Software" "No effect,Forced" group.word 0x26++0x01 line.word 0x00 "TZDCSEL,Trip Zone Digital Compare Event Select Register" bitfld.word 0x00 9.--11. " DCBEVT2 ,Digital Compare Output B Event 2 Selection" "Event disabled,DCBH = low,DCBH = high,DCBL = low,DCBL = high,DCBL = high - DCBH = low,?..." bitfld.word 0x00 6.--8. " DCBEVT1 ,Digital Compare Output B Event 1 Selection" "Event disabled,DCBH = low,DCBH = high,DCBL = low,DCBL = high,DCBL = high - DCBH = low,?..." textline " " bitfld.word 0x00 3.--5. " DCAEVT2 ,Digital Compare Output A Event 2 Selection" "Event disabled,DCAH = low,DCAH = high,DCAL = low,DCAL = high,DCAL = high - DCAH = low,?..." bitfld.word 0x00 0.--2. " DCAEVT1 ,Digital Compare Output A Event 1 Selection" "Event disabled,DCAH = low,DCAH = high,DCAL = low,DCAL = high,DCAL = high,?..." tree.end width 11. tree "Digital Compare Submodule Registers" group.word 0x60++0x09 line.word 0x00 "DCTRIPSEL,Digital Compare Trip Select" bitfld.word 0x00 12.--15. " DCBLCOMPSEL ,Digital Compare B Low Input Select" "TZ1 input,TZ2 input,TZ3 input,?..." bitfld.word 0x00 8.--11. " DCBHCOMPSEL ,Digital Compare B High Input Select" "TZ1 input,TZ2 input,TZ3 input,?..." textline " " bitfld.word 0x00 4.--7. " DCALCOMPSEL ,Digital Compare A Low Input Select" "TZ1 input,TZ2 input,TZ3 input,?..." bitfld.word 0x00 0.--3. " DCAHCOMPSEL ,Digital Compare A High Input Select" "TZ1 input,TZ2 input,TZ3 input,?..." line.word 0x02 "DCACTL,Digital Compare A Control Register" bitfld.word 0x02 9. " EVT2FRC_SYNCSEL ,DCAEVT2 Force Synchronization Signal Select" "Synchronous,Asynchronous" bitfld.word 0x02 8. " EVT2SRCSEL ,DCAEVT2 Source Signal Select" "DCAEVT2,DCEVTFILT" textline " " bitfld.word 0x02 3. " EVT1SYNCE ,DCAEVT1 SYNC Generation" "Disabled,Enabled" bitfld.word 0x02 2. " EVT1SOCE ,DCAEVT1 SOC Generation" "Disabled,Enabled" textline " " bitfld.word 0x02 1. " EVT1FRC_SYNCSEL ,DCAEVT1 Force Synchronization Signal Select" "Synchronous,Asynchronous" bitfld.word 0x02 0. " EVT1SRCSEL ,DCAEVT1 Source Signal Select" "DCAEVT,DCEVTFILT" line.word 0x04 "DCBCTL,Digital Compare B Control Register" bitfld.word 0x04 9. " EVT2FRC_SYNCSEL ,DCBEVT2 Force Synchronization Signal Select" "Synchronous,Asynchronous" bitfld.word 0x04 8. " EVT2SRCSEL ,DCBEVT2 Source Signal Select" "DCBEVT2,DCEVTFILT" textline " " bitfld.word 0x04 3. " EVT1SYNCE ,DCBEVT1 SYNC Generation" "Disabled,Enabled" bitfld.word 0x04 2. " EVT1SOCE ,DCBEVT1 SOC Generation" "Disabled,Enabled" textline " " bitfld.word 0x04 1. " EVT1FRC_SYNCSEL ,DCBEVT1 Force Synchronization Signal Select" "Synchronous,Asynchronous" bitfld.word 0x04 0. " EVT1SRCSEL ,DCBEVT1 Source Signal Select" "DCBEVT,DCEVTFILT" line.word 0x06 "DBFCTL,Digital Compare Filter Control Register" bitfld.word 0x06 4.--5. " PULSESEL ,Pulse Select For Blanking & Capture Alignment" "TB CNT Equal to period,TB CNT Equal to zero,?..." textline " " bitfld.word 0x06 3. " BLANKINV ,Blanking Window Inversion" "Not inverted,Inverted" bitfld.word 0x06 2. " BLANKE ,Blanking Window Enable/Disable" "Disabled,Enabled" textline " " bitfld.word 0x06 0.--1. " SRCSEL ,Filter Block Signal Source Select" "DCAEVT1,DCAEVT2,DCBEVT1,DCBEVT2" line.word 0x08 "DBCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x08 1. " SHDWMODE ,TBCTR Counter Capture Shadow Select Mode" "Shadow mode,Active Mode" bitfld.word 0x08 0. " CAPE ,TBCTR Counter Capture Enable/Disable" "Disabled,Enabled" width 14. rgroup.word 0x72++0x01 line.word 0x00 "DCCAP,Digital Compare Counter Capture Register" rgroup.word 0x6A++0x01 line.word 0x00 "DCFOFFSET,Digital Compare Filter Offset Register" group.word 0x6E++0x01 line.word 0x00 "DCFWINDOW,Digital Compare Filter Window Register" hexmask.word.byte 0x00 0.--7. 1. " WINDOW ,Blanking Window Width" rgroup.word 0x70++0x01 line.word 0x00 "DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word.byte 0x00 0.--7. 1. " WINDOWCNT ,Digital Compare Filter Window Counter Register" tree.end width 7. tree "Event-Trigger Submodule Registers" group.word 0x32++0x09 line.word 0x00 "ETSEL,Event-Trigger Selection Register" bitfld.word 0x00 15. " SOCBEN ,Enable the ADC Start of Conversion B EPWMxSOCB Pulse" "Disabled,Enabled" bitfld.word 0x00 12.--14. " SOCBSEL ,EPWMxSOCB Selection Options" "DCBEVT1_soc,TB CNT equal to zero,TB CNT equal to period,TB CNT equal to zero or period,TB CNT equal to CMPA - Timer INC,TB CNT equal to CMPA - Timer DEC,TB CNT equal to CMPB - Timer INC,TB CNT equal to CMPB - Timer DEC" textline " " bitfld.word 0x00 11. " SOCAEN ,Enable the ADC Start of Conversion A EPWMxSOCA Pulse" "Disabled,Enabled" bitfld.word 0x00 8.--10. " SOCASEL ,EPWMxSOCA Selection Options" "DCAEVT1_soc,TB CNT equal to zero,TB CNT equal to period,TB CNT equal to zero or period,TB CNT equal to CMPA - Timer INC,TB CNT equal to CMPA - Timer DEC,TB CNT equal to CMPB - Timer INC,TB CNT equal to CMPB - Timer DEC" textline " " bitfld.word 0x00 3. " INTEN ,Enable ePWM Interrupt EPWMx_INT Generation" "Disabled,Enabled" bitfld.word 0x00 0.--2. " INTSEL ,ePWM Interrupt EPWMx_INT Selection Options" "Reserved,TB CNT equal to zero,TB CNT equal to period,TB CNT equal to zero or period,TB CNT equal to CMPA - Timer INC,TB CNT equal to CMPA - Timer DEC,TB CNT equal to CMPB - Timer INC,TB CNT equal to CMPB - Timer DEC" line.word 0x02 "ETPS,Event-Trigger Prescale Register" bitfld.word 0x02 14.--15. " SOCBCNT ,ePWM ADC Start-of-Conversion B Event EPWMxSOCB Counter Register" "No events,1 event,2 events,3 events" bitfld.word 0x02 12.--13. " SOCBPRD ,ePWM ADC Start-of-Conversion B Event EPWMxSOCB Period Select" "Disabled,1st event,2nd event,3th event" textline " " bitfld.word 0x02 10.--11. " SOCACNT ,ePWM ADC Start-of-Conversion A Event EPWMxSOCA Counter Register" "No events,1 event,2 events,3 events" bitfld.word 0x02 8.--9. " SOCAPRD ,ePWM ADC Start-of-Conversion A Event EPWMxSOCA Period Select" "Disabled,1st event,2nd event,3th event" textline " " bitfld.word 0x02 2.--3. " INTCNT ,ePWM Interrupt Event EPWMx_INT Counter Register" "No events,1 event,2 events,3 events" bitfld.word 0x02 0.--1. " INTPRD ,ePWM Interrupt EPWMx_INT Period Select" "Disabled,1st event,2nd event,3th event" line.word 0x04 "ETFLG,Event-Trigger Flag Register" bitfld.word 0x04 3. " SOCB ,Latched ePWM ADC Start-of-Conversion B EPWMxSOCB Status Flag" "Not occurred,Occurred" bitfld.word 0x04 2. " SOCA ,Latched ePWM ADC Start-of-Conversion A EPWMxSOCA Status Flag" "Not occurred,Occurred" textline " " bitfld.word 0x04 0. " INT ,Latched ePWM Interrupt EPWMx_INT Status Flag" "Not occurred,Occurred" line.word 0x06 "ETCLR,Event-Trigger Clear Register" bitfld.word 0x06 3. " SOCB ,ePWM ADC Start-of-Conversion B EPWMxSOCB Flag Clear Bit" "No effect,Cleared" bitfld.word 0x06 2. " SOCA ,ePWM ADC Start-of-Conversion A EPWMxSOCB Flag Clear Bit" "No effect,Cleared" textline " " bitfld.word 0x06 0. " INT ,ePWM Interrupt EPWMx_INT Flag Clear Bit" "No effect,Cleared" line.word 0x08 "ETFRC,Event-Trigger Force Register" bitfld.word 0x08 3. " SOCB ,SOCB Force Bit" "No effect,Forced" bitfld.word 0x08 2. " SOCA ,SOCA Force Bit" "No effect,Forced" textline " " bitfld.word 0x08 0. " INT ,INT Force Bit" "No effect,Forced" tree.end width 0xB tree.end tree "ePWM 2" base ad:0xFCF78D00 width 14. tree "Time-Base Submodule Registers" group.word 0x0A++0x01 line.word 0x00 "TBPRD,Time-Base Period Register" group.word 0x06++0x03 line.word 0x00 "TBPHS,Time-Base Phase Register" line.word 0x02 "TBCTR,Time-Base Counter Register" group.word 0x00++0x03 line.word 0x00 "TBCTL,Time-Base Control Register" bitfld.word 0x00 14.--15. " FREE/SOFT ,Emulation Mode Bits" "Stop after the next time-base counter INC or DEC,Stop when counter completes a whole cycle,Free run,Free run" textline " " bitfld.word 0x00 13. " PHSDIR ,Phase Direction Bit" "Count down,Count up" bitfld.word 0x00 10.--12. " CLKDIV ,Time-base Clock Prescale Bits" "/1,/2,/4,/8,/16,/32,/64,/128" textline " " bitfld.word 0x00 7.--9. " HSPCLKDIV ,High Speed Time-base Clock Prescale Bits" "/1,/2,/4,/8,/8,/10,/12,/14" bitfld.word 0x00 6. " SWFSYNC ,Software Forced Synchronization Pulse" "No effect,Generated" textline " " bitfld.word 0x00 4.--5. " SYNCOSEL ,Synchronization Output Select" "EPWMxSYNC,CTR = zero,CTR = CMPB,EPWMxSYNCO disable" bitfld.word 0x00 3. " PRDLD ,Active Period Register Load From Shadow Register Select" "Not selected,Selected" bitfld.word 0x00 2. " PHSEN ,Counter Register Load From Phase Register Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0.--1. " CTRMODE ,Counter Mode" "Up-count,Down-count,Up-down-count,Stop-freeze counter operation" line.word 0x02 "TBSTS,Time-Base Status Register" bitfld.word 0x02 2. " CTRMAX ,Time-Base Counter Max Latched Status Bit time-base counter maximum value" "Not reached,Reached" bitfld.word 0x02 1. " SYNCI ,Input Synchronization Latched Status Bit external synchronization event" "Not occurred,Occurred" textline " " bitfld.word 0x02 0. " CTRDIR ,Time-Base Counter Direction Status Bit" "Down,Up" tree.end width 8. tree "Counter-Compare Submodule Registers" group.word 0x12++0x03 line.word 0x00 "CMPA,Counter-Compare A Register" line.word 0x02 "CMPB,Counter-Compare B Register" group.word 0x0E++0x1 line.word 0x00 "CMPCTL,Counter-Compare Control Register" bitfld.word 0x00 9. " SHDWBFULL ,Counter-compare B CMPB Shadow Register Full Status Flag" "Not full,Full" bitfld.word 0x00 8. " SHDWAFULL ,Counter-compare A CMPA Shadow Register Full Status Flag" "Not full,Full" textline " " bitfld.word 0x00 6. " SHDWBMODE ,Counter-compare B CMPB Register Operating Mode" "Shadow,Immediate" bitfld.word 0x00 4. " SHDWAMODE ,Counter-compare A CMPA Register Operating Mode" "Shadow,Immediate" textline " " bitfld.word 0x00 2.--3. " LOADBMODE ,Active Counter-Compare B CMPB Load From Shadow Select Mode" "CTR = Zero,CTR = PRD,CTR = Zero or CTR = PRD,Freeze" bitfld.word 0x00 0.--1. " LOADAMODE ,Active Counter-Compare A CMPA Load From Shadow Select Mode" "CTR = Zero,CTR = PRD,CTR = Zero or CTR = PRD,Freeze" tree.end width 9. tree "Action-Qualifier Submodule Registers" group.word 0x16++0x07 line.word 0x00 "AQCTLA,Action-Qualifier Output A Control Register" bitfld.word 0x00 10.--11. " CBD ,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "Disabled,Cleared,Set,Toggled" bitfld.word 0x00 8.--9. " CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,Cleared,Set,Toggled" textline " " bitfld.word 0x00 6.--7. " CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,Cleared,Set,Toggled" bitfld.word 0x00 4.--5. " CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,Cleared,Set,Toggled" textline " " bitfld.word 0x00 2.--3. " PRD ,Action when the counter equals the period" "Disabled,Cleared,Set,Toggled" bitfld.word 0x00 0.--1. " ZRO ,Action when counter equals zero" "Disabled,Cleared,Set,Toggled" line.word 0x02 "AQCTLB,Action-Qualifier Output B Control Register" bitfld.word 0x02 10.--11. " CBD ,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "Disabled,Cleared,Set,Toggled" bitfld.word 0x02 8.--9. " CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,Cleared,Set,Toggled" textline " " bitfld.word 0x02 6.--7. " CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,Cleared,Set,Toggled" bitfld.word 0x02 4.--5. " CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,Cleared,Set,Toggled" textline " " bitfld.word 0x02 2.--3. " PRD ,Action when the counter equals the period" "Disabled,Cleared,Set,Toggled" bitfld.word 0x02 0.--1. " ZRO ,Action when counter equals zero" "Disabled,Cleared,Set,Toggled" line.word 0x04 "AQSFRC,Action-Qualifier Software Force Register" bitfld.word 0x04 6.--7. " RLDCSF ,AQCSFRC Active Register Reload From Shadow Options" "Zero,Period,Zero or Period,Immediately" bitfld.word 0x04 5. " OTSFB ,One-Time Software Forced Event on Output B" "No effect,Forced" textline " " bitfld.word 0x04 3.--4. " ACTSFB ,Action when One-Time Software Force B Is invoked" "Disabled,Cleared,Set,Toggled" bitfld.word 0x04 2. " OTSFA ,One-Time Software Forced Event on Output A" "No effect,Forced" textline " " bitfld.word 0x04 0.--1. " ACTSFA ,Action When One-Time Software Force A Is Invoked" "Disabled,Cleared,Set,Toggled" line.word 0x06 "AQCSFRC,Action-Qualifier Continuous Software Force Register" bitfld.word 0x06 2.--3. " CSFB ,Continuous Software Force on Output B" "Forced disabled,Continued low,Continued high,Soft forced disabled" bitfld.word 0x06 0.--1. " CSFA ,Continuous Software Force on Output A" "Forced disabled,Continued low,Continued high,Soft forced disabled" tree.end width 7. tree "Dead-Band Submodule Registers" group.word 0x1E++0x05 line.word 0x00 "DBCTL,Dead-Band Generator Control Register" bitfld.word 0x00 15. " HALFCYCLE ,Half Cycle Clocking Enable Bit" "Disabled,Enabled" textline " " bitfld.word 0x00 4.--5. " IN_MODE ,Dead Band Input Mode Control" "EPWMxA Faling/rising,EPWMxB rising / EPWMxA falling,EPWMxA rising / EPWMxB falling,EPWMxB both rising & falling" textline " " bitfld.word 0x00 2.--3. " POLSEL ,Polarity Select Control" "AH,ALC,AHC,AL" textline " " bitfld.word 0x00 0.--1. " OUT_MODE ,Dead-band Output Mode Control" "Dead-band generation bypassed,Disabled rising-edge delay,Rising-edge delayed signal on EPWMxA,Dead-band fully enabled" line.word 0x02 "DBRED,Dead-Band Generator Rising Edge Delay Register" hexmask.word 0x02 0.--9. 1. " DEL ,Rising Edge Delay Count" line.word 0x04 "DBFED,Dead-Band Generator Falling Edge Delay Register" hexmask.word 0x04 0.--9. 1. " DEL ,Falling Edge Delay Count" tree.end width 0x7 tree "PWM-Chopper Submodule Control Register" group.word 0x3C++0x01 line.word 0x00 "PCCTL,PWM-Chopper Control Register" bitfld.word 0x00 8.--10. " CHPDUTY ,Chopping Clock Duty Cycle" "1/8 (12.5%),2/8 (25.0%),3/8 (37.5%),4/8 (50.0%),5/8 (62.5%),6/8 (75.0%),7/8 (87.5%),?..." textline " " bitfld.word 0x00 5.--7. " CHPFREQ ,Chopping Clock Frequency" "/1 (no prescale = 12.5 MHz at 100 MHz VCLK4),/2 (6.25 MHz at 100 MHz VCLK4),/3 (4.16 MHz at 100 MHz VCLK4),/4 (3.12 MHz at 100 MHz VCLK4),/5 (2.50 MHz at 100 MHz VCLK4),/6 (2.08 MHz at 100 MHz VCLK4),/7 (1.78 MHz at 100 MHz VCLK4),/8 (1.56 MHz at 100 MHz VCLK4)" textline " " bitfld.word 0x00 1.--4. " OSHTWTH ,One-Shot Pulse Width" "1 x VCLK4 / 8 wide ( = 80 nS at 100 MHz VCLK4),2 x VCLK4 / 8 wide ( = 160 nS at 100 MHz VCLK4),3 x VCLK4 / 8 wide ( = 240 nS at 100 MHz VCLK4),4 x VCLK4 / 8 wide ( = 320 nS at 100 MHz VCLK4),5 x VCLK4 / 8 wide ( = 400 nS at 100 MHz VCLK4),6 x VCLK4 / 8 wide ( = 480 nS at 100 MHz VCLK4),7 x VCLK4 / 8 wide ( = 560 nS at 100 MHz VCLK4),8 x VCLK4 / 8 wide ( = 640 nS at 100 MHz VCLK4),9 x VCLK4 / 8 wide ( = 720 nS at 100 MHz VCLK4),10 x VCLK4 / 8 wide ( = 800 nS at 100 MHz VCLK4),11 x VCLK4 / 8 wide ( = 880 nS at 100 MHz VCLK4),12 x VCLK4 / 8 wide ( = 960 nS at 100 MHz VCLK4),13 x VCLK4 / 8 wide ( = 1040 nS at 100 MHz VCLK4),14 x VCLK4 / 8 wide ( = 1120 nS at 100 MHz VCLK4),15 x VCLK4 / 8 wide ( = 1200 nS at 100 MHz VCLK4),16 x VCLK4 / 8 wide ( = 1280 nS at 100 MHz VCLK4)" textline " " bitfld.word 0x00 0. " CHPEN ,PWM-chopping Enable" "Disabled,Enabled" tree.end width 9. tree "Trip-Zone Select Register" group.word 0x24++0x01 line.word 0x00 "TZSEL,Trip-Zone Submodule Control and Status Registers" bitfld.word 0x00 15. " DCBEVT1 ,Digital Compare Output B Event 1 Select" "Disabled,Enabled" bitfld.word 0x00 14. " DCAEVT1 ,Digital Compare Output A Event 1 Select" "Disabled,Enabled" bitfld.word 0x00 13. " OSHT6 ,Trip-zone 6 TZ6 Select" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " OSHT5 ,Trip-zone 5 TZ5 Select" "Disabled,Enabled" bitfld.word 0x00 11. " OSHT4 ,Trip-zone 4 TZ4 Select" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OSHT3 ,Trip-zone 3 TZ3 Select" "Disabled,Enabled" bitfld.word 0x00 9. " OSHT2 ,Trip-zone 2 TZ2 Select" "Disabled,Enabled" bitfld.word 0x00 8. " OSHT1 ,Trip-zone 1 TZ) Select" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " DCBEVT2 ,Digital Compare Output B Event 2 Select" "Disabled,Enabled" bitfld.word 0x00 6. " DCAEVT2 ,Digital Compare Output A Event 2 Select" "Disabled,Enabled" bitfld.word 0x00 5. " CBC6 ,Trip-zone 6 TZ6 Select" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " CBC5 ,Trip-zone 5 TZ5 Select" "Disabled,Enabled" bitfld.word 0x00 3. " CBC4 ,Trip-zone 4 TZ4 Select" "Disabled,Enabled" bitfld.word 0x00 2. " CBC3 ,Trip-zone 3 TZ3 Select" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " CBC2 ,Trip-zone 2 TZ2 Select" "Disabled,Enabled" bitfld.word 0x00 0. " CBC1 ,Trip-zone 1 TZ1 Select" "Disabled,Enabled" group.word 0x28++0x01 line.word 0x00 "TZCTL,Trip-Zone Control Register" bitfld.word 0x00 10.--11. " DCBEVT2 ,Digital Compare Output B Event 2 Action On EPWMxB" "High-impedance,High state,Low state,Disabled" bitfld.word 0x00 8.--9. " DCBEVT1 ,Digital Compare Output B Event 1 Action On EPWMxB" "High-impedance,Forced high state,Forced low state,Disabled" textline " " bitfld.word 0x00 6.--7. " DCAEVT2 ,Digital Compare Output A Event 2 Action On EPWMxA" "High-impedance,Forced high state,Forced low state,Disabled" bitfld.word 0x00 4.--5. " DCAEVT1 ,Digital Compare Output A Event 1 Action On EPWMxA" "High-impedance,Forced high state,Forced low state,Disabled" textline " " bitfld.word 0x00 2.--3. " TZB ,When a trip event occurs the following action is taken on output EPWMxB" "High-impedance,Forced high state,Forced low state,Disabled" bitfld.word 0x00 0.--1. " TZA ,When a trip event occurs the following action is taken on output EPWMxA" "High-impedance,Forced high state,Forced low state,Disabled" group.word 0x2C++0x01 line.word 0x00 "TZFLG,Trip-Zone Flag Register Field Descriptions" setclrfld.word 0x00 6. -0x02 6. 0x02 6. " DCBEVT2_set/clr ,Digital Comparator Output B Event 2 Interrupt" "Not occurred,Occurred" setclrfld.word 0x00 5. -0x02 5. 0x02 5. " DCBEVT1_set/clr ,Digital Comparator Output B Event 1 Interrupt" "Not occurred,Occurred" textline " " setclrfld.word 0x00 4. -0x02 4. 0x02 4. " DCAEVT2_set/clr ,Digital Comparator Output A Event 2 Interrupt" "Not occurred,Occurred" setclrfld.word 0x00 3. -0x02 3. 0x02 3. " DCAEVT1_set/clr ,Digital Comparator Output A Event 1 Interrupt" "Not occurred,Occurred" textline " " setclrfld.word 0x00 2. -0x02 2. 0x02 2. " OST_set/clr ,Trip-zone One-Shot Interrupt" "Not occurred,Occurred" setclrfld.word 0x00 1. -0x02 1. 0x02 1. " CBC_set/clr ,Trip-zone Cycle-by-Cycle Interrupt" "Not occurred,Occurred" textline " " setclrfld.word 0x00 0. 0x00 0. 0x02 0. " INT_set/clr ,Latched Trip Interrupt Status Flag" "Not generated,Generated" group.word 0x30++0x01 line.word 0x00 "TZFRC,Trip-Zone Force Register" bitfld.word 0x00 6. " DCBEVT2 ,Force Flag for Digital Compare Output B Event 2" "No effect,Forced" bitfld.word 0x00 5. " DCBEVT1 ,Force Flag for Digital Compare Output B Event 1" "No effect,Forced" textline " " bitfld.word 0x00 4. " DCAEVT2 ,Force Flag for Digital Compare Output A Event 2" "No effect,Forced" bitfld.word 0x00 3. " DCAEVT1 ,Force Flag for Digital Compare Output A Event 1" "No effect,Forced" textline " " bitfld.word 0x00 2. " OST ,Force a One-Shot Trip Event via Software" "No effect,Forced" bitfld.word 0x00 1. " CBC ,Force a Cycle-by-Cycle Trip Event via Software" "No effect,Forced" group.word 0x26++0x01 line.word 0x00 "TZDCSEL,Trip Zone Digital Compare Event Select Register" bitfld.word 0x00 9.--11. " DCBEVT2 ,Digital Compare Output B Event 2 Selection" "Event disabled,DCBH = low,DCBH = high,DCBL = low,DCBL = high,DCBL = high - DCBH = low,?..." bitfld.word 0x00 6.--8. " DCBEVT1 ,Digital Compare Output B Event 1 Selection" "Event disabled,DCBH = low,DCBH = high,DCBL = low,DCBL = high,DCBL = high - DCBH = low,?..." textline " " bitfld.word 0x00 3.--5. " DCAEVT2 ,Digital Compare Output A Event 2 Selection" "Event disabled,DCAH = low,DCAH = high,DCAL = low,DCAL = high,DCAL = high - DCAH = low,?..." bitfld.word 0x00 0.--2. " DCAEVT1 ,Digital Compare Output A Event 1 Selection" "Event disabled,DCAH = low,DCAH = high,DCAL = low,DCAL = high,DCAL = high,?..." tree.end width 11. tree "Digital Compare Submodule Registers" group.word 0x60++0x09 line.word 0x00 "DCTRIPSEL,Digital Compare Trip Select" bitfld.word 0x00 12.--15. " DCBLCOMPSEL ,Digital Compare B Low Input Select" "TZ1 input,TZ2 input,TZ3 input,?..." bitfld.word 0x00 8.--11. " DCBHCOMPSEL ,Digital Compare B High Input Select" "TZ1 input,TZ2 input,TZ3 input,?..." textline " " bitfld.word 0x00 4.--7. " DCALCOMPSEL ,Digital Compare A Low Input Select" "TZ1 input,TZ2 input,TZ3 input,?..." bitfld.word 0x00 0.--3. " DCAHCOMPSEL ,Digital Compare A High Input Select" "TZ1 input,TZ2 input,TZ3 input,?..." line.word 0x02 "DCACTL,Digital Compare A Control Register" bitfld.word 0x02 9. " EVT2FRC_SYNCSEL ,DCAEVT2 Force Synchronization Signal Select" "Synchronous,Asynchronous" bitfld.word 0x02 8. " EVT2SRCSEL ,DCAEVT2 Source Signal Select" "DCAEVT2,DCEVTFILT" textline " " bitfld.word 0x02 3. " EVT1SYNCE ,DCAEVT1 SYNC Generation" "Disabled,Enabled" bitfld.word 0x02 2. " EVT1SOCE ,DCAEVT1 SOC Generation" "Disabled,Enabled" textline " " bitfld.word 0x02 1. " EVT1FRC_SYNCSEL ,DCAEVT1 Force Synchronization Signal Select" "Synchronous,Asynchronous" bitfld.word 0x02 0. " EVT1SRCSEL ,DCAEVT1 Source Signal Select" "DCAEVT,DCEVTFILT" line.word 0x04 "DCBCTL,Digital Compare B Control Register" bitfld.word 0x04 9. " EVT2FRC_SYNCSEL ,DCBEVT2 Force Synchronization Signal Select" "Synchronous,Asynchronous" bitfld.word 0x04 8. " EVT2SRCSEL ,DCBEVT2 Source Signal Select" "DCBEVT2,DCEVTFILT" textline " " bitfld.word 0x04 3. " EVT1SYNCE ,DCBEVT1 SYNC Generation" "Disabled,Enabled" bitfld.word 0x04 2. " EVT1SOCE ,DCBEVT1 SOC Generation" "Disabled,Enabled" textline " " bitfld.word 0x04 1. " EVT1FRC_SYNCSEL ,DCBEVT1 Force Synchronization Signal Select" "Synchronous,Asynchronous" bitfld.word 0x04 0. " EVT1SRCSEL ,DCBEVT1 Source Signal Select" "DCBEVT,DCEVTFILT" line.word 0x06 "DBFCTL,Digital Compare Filter Control Register" bitfld.word 0x06 4.--5. " PULSESEL ,Pulse Select For Blanking & Capture Alignment" "TB CNT Equal to period,TB CNT Equal to zero,?..." textline " " bitfld.word 0x06 3. " BLANKINV ,Blanking Window Inversion" "Not inverted,Inverted" bitfld.word 0x06 2. " BLANKE ,Blanking Window Enable/Disable" "Disabled,Enabled" textline " " bitfld.word 0x06 0.--1. " SRCSEL ,Filter Block Signal Source Select" "DCAEVT1,DCAEVT2,DCBEVT1,DCBEVT2" line.word 0x08 "DBCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x08 1. " SHDWMODE ,TBCTR Counter Capture Shadow Select Mode" "Shadow mode,Active Mode" bitfld.word 0x08 0. " CAPE ,TBCTR Counter Capture Enable/Disable" "Disabled,Enabled" width 14. rgroup.word 0x72++0x01 line.word 0x00 "DCCAP,Digital Compare Counter Capture Register" rgroup.word 0x6A++0x01 line.word 0x00 "DCFOFFSET,Digital Compare Filter Offset Register" group.word 0x6E++0x01 line.word 0x00 "DCFWINDOW,Digital Compare Filter Window Register" hexmask.word.byte 0x00 0.--7. 1. " WINDOW ,Blanking Window Width" rgroup.word 0x70++0x01 line.word 0x00 "DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word.byte 0x00 0.--7. 1. " WINDOWCNT ,Digital Compare Filter Window Counter Register" tree.end width 7. tree "Event-Trigger Submodule Registers" group.word 0x32++0x09 line.word 0x00 "ETSEL,Event-Trigger Selection Register" bitfld.word 0x00 15. " SOCBEN ,Enable the ADC Start of Conversion B EPWMxSOCB Pulse" "Disabled,Enabled" bitfld.word 0x00 12.--14. " SOCBSEL ,EPWMxSOCB Selection Options" "DCBEVT1_soc,TB CNT equal to zero,TB CNT equal to period,TB CNT equal to zero or period,TB CNT equal to CMPA - Timer INC,TB CNT equal to CMPA - Timer DEC,TB CNT equal to CMPB - Timer INC,TB CNT equal to CMPB - Timer DEC" textline " " bitfld.word 0x00 11. " SOCAEN ,Enable the ADC Start of Conversion A EPWMxSOCA Pulse" "Disabled,Enabled" bitfld.word 0x00 8.--10. " SOCASEL ,EPWMxSOCA Selection Options" "DCAEVT1_soc,TB CNT equal to zero,TB CNT equal to period,TB CNT equal to zero or period,TB CNT equal to CMPA - Timer INC,TB CNT equal to CMPA - Timer DEC,TB CNT equal to CMPB - Timer INC,TB CNT equal to CMPB - Timer DEC" textline " " bitfld.word 0x00 3. " INTEN ,Enable ePWM Interrupt EPWMx_INT Generation" "Disabled,Enabled" bitfld.word 0x00 0.--2. " INTSEL ,ePWM Interrupt EPWMx_INT Selection Options" "Reserved,TB CNT equal to zero,TB CNT equal to period,TB CNT equal to zero or period,TB CNT equal to CMPA - Timer INC,TB CNT equal to CMPA - Timer DEC,TB CNT equal to CMPB - Timer INC,TB CNT equal to CMPB - Timer DEC" line.word 0x02 "ETPS,Event-Trigger Prescale Register" bitfld.word 0x02 14.--15. " SOCBCNT ,ePWM ADC Start-of-Conversion B Event EPWMxSOCB Counter Register" "No events,1 event,2 events,3 events" bitfld.word 0x02 12.--13. " SOCBPRD ,ePWM ADC Start-of-Conversion B Event EPWMxSOCB Period Select" "Disabled,1st event,2nd event,3th event" textline " " bitfld.word 0x02 10.--11. " SOCACNT ,ePWM ADC Start-of-Conversion A Event EPWMxSOCA Counter Register" "No events,1 event,2 events,3 events" bitfld.word 0x02 8.--9. " SOCAPRD ,ePWM ADC Start-of-Conversion A Event EPWMxSOCA Period Select" "Disabled,1st event,2nd event,3th event" textline " " bitfld.word 0x02 2.--3. " INTCNT ,ePWM Interrupt Event EPWMx_INT Counter Register" "No events,1 event,2 events,3 events" bitfld.word 0x02 0.--1. " INTPRD ,ePWM Interrupt EPWMx_INT Period Select" "Disabled,1st event,2nd event,3th event" line.word 0x04 "ETFLG,Event-Trigger Flag Register" bitfld.word 0x04 3. " SOCB ,Latched ePWM ADC Start-of-Conversion B EPWMxSOCB Status Flag" "Not occurred,Occurred" bitfld.word 0x04 2. " SOCA ,Latched ePWM ADC Start-of-Conversion A EPWMxSOCA Status Flag" "Not occurred,Occurred" textline " " bitfld.word 0x04 0. " INT ,Latched ePWM Interrupt EPWMx_INT Status Flag" "Not occurred,Occurred" line.word 0x06 "ETCLR,Event-Trigger Clear Register" bitfld.word 0x06 3. " SOCB ,ePWM ADC Start-of-Conversion B EPWMxSOCB Flag Clear Bit" "No effect,Cleared" bitfld.word 0x06 2. " SOCA ,ePWM ADC Start-of-Conversion A EPWMxSOCB Flag Clear Bit" "No effect,Cleared" textline " " bitfld.word 0x06 0. " INT ,ePWM Interrupt EPWMx_INT Flag Clear Bit" "No effect,Cleared" line.word 0x08 "ETFRC,Event-Trigger Force Register" bitfld.word 0x08 3. " SOCB ,SOCB Force Bit" "No effect,Forced" bitfld.word 0x08 2. " SOCA ,SOCA Force Bit" "No effect,Forced" textline " " bitfld.word 0x08 0. " INT ,INT Force Bit" "No effect,Forced" tree.end width 0xB tree.end tree "ePWM 3" base ad:0xFCF78E00 width 14. tree "Time-Base Submodule Registers" group.word 0x0A++0x01 line.word 0x00 "TBPRD,Time-Base Period Register" group.word 0x06++0x03 line.word 0x00 "TBPHS,Time-Base Phase Register" line.word 0x02 "TBCTR,Time-Base Counter Register" group.word 0x00++0x03 line.word 0x00 "TBCTL,Time-Base Control Register" bitfld.word 0x00 14.--15. " FREE/SOFT ,Emulation Mode Bits" "Stop after the next time-base counter INC or DEC,Stop when counter completes a whole cycle,Free run,Free run" textline " " bitfld.word 0x00 13. " PHSDIR ,Phase Direction Bit" "Count down,Count up" bitfld.word 0x00 10.--12. " CLKDIV ,Time-base Clock Prescale Bits" "/1,/2,/4,/8,/16,/32,/64,/128" textline " " bitfld.word 0x00 7.--9. " HSPCLKDIV ,High Speed Time-base Clock Prescale Bits" "/1,/2,/4,/8,/8,/10,/12,/14" bitfld.word 0x00 6. " SWFSYNC ,Software Forced Synchronization Pulse" "No effect,Generated" textline " " bitfld.word 0x00 4.--5. " SYNCOSEL ,Synchronization Output Select" "EPWMxSYNC,CTR = zero,CTR = CMPB,EPWMxSYNCO disable" bitfld.word 0x00 3. " PRDLD ,Active Period Register Load From Shadow Register Select" "Not selected,Selected" bitfld.word 0x00 2. " PHSEN ,Counter Register Load From Phase Register Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0.--1. " CTRMODE ,Counter Mode" "Up-count,Down-count,Up-down-count,Stop-freeze counter operation" line.word 0x02 "TBSTS,Time-Base Status Register" bitfld.word 0x02 2. " CTRMAX ,Time-Base Counter Max Latched Status Bit time-base counter maximum value" "Not reached,Reached" bitfld.word 0x02 1. " SYNCI ,Input Synchronization Latched Status Bit external synchronization event" "Not occurred,Occurred" textline " " bitfld.word 0x02 0. " CTRDIR ,Time-Base Counter Direction Status Bit" "Down,Up" tree.end width 8. tree "Counter-Compare Submodule Registers" group.word 0x12++0x03 line.word 0x00 "CMPA,Counter-Compare A Register" line.word 0x02 "CMPB,Counter-Compare B Register" group.word 0x0E++0x1 line.word 0x00 "CMPCTL,Counter-Compare Control Register" bitfld.word 0x00 9. " SHDWBFULL ,Counter-compare B CMPB Shadow Register Full Status Flag" "Not full,Full" bitfld.word 0x00 8. " SHDWAFULL ,Counter-compare A CMPA Shadow Register Full Status Flag" "Not full,Full" textline " " bitfld.word 0x00 6. " SHDWBMODE ,Counter-compare B CMPB Register Operating Mode" "Shadow,Immediate" bitfld.word 0x00 4. " SHDWAMODE ,Counter-compare A CMPA Register Operating Mode" "Shadow,Immediate" textline " " bitfld.word 0x00 2.--3. " LOADBMODE ,Active Counter-Compare B CMPB Load From Shadow Select Mode" "CTR = Zero,CTR = PRD,CTR = Zero or CTR = PRD,Freeze" bitfld.word 0x00 0.--1. " LOADAMODE ,Active Counter-Compare A CMPA Load From Shadow Select Mode" "CTR = Zero,CTR = PRD,CTR = Zero or CTR = PRD,Freeze" tree.end width 9. tree "Action-Qualifier Submodule Registers" group.word 0x16++0x07 line.word 0x00 "AQCTLA,Action-Qualifier Output A Control Register" bitfld.word 0x00 10.--11. " CBD ,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "Disabled,Cleared,Set,Toggled" bitfld.word 0x00 8.--9. " CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,Cleared,Set,Toggled" textline " " bitfld.word 0x00 6.--7. " CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,Cleared,Set,Toggled" bitfld.word 0x00 4.--5. " CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,Cleared,Set,Toggled" textline " " bitfld.word 0x00 2.--3. " PRD ,Action when the counter equals the period" "Disabled,Cleared,Set,Toggled" bitfld.word 0x00 0.--1. " ZRO ,Action when counter equals zero" "Disabled,Cleared,Set,Toggled" line.word 0x02 "AQCTLB,Action-Qualifier Output B Control Register" bitfld.word 0x02 10.--11. " CBD ,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "Disabled,Cleared,Set,Toggled" bitfld.word 0x02 8.--9. " CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,Cleared,Set,Toggled" textline " " bitfld.word 0x02 6.--7. " CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,Cleared,Set,Toggled" bitfld.word 0x02 4.--5. " CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,Cleared,Set,Toggled" textline " " bitfld.word 0x02 2.--3. " PRD ,Action when the counter equals the period" "Disabled,Cleared,Set,Toggled" bitfld.word 0x02 0.--1. " ZRO ,Action when counter equals zero" "Disabled,Cleared,Set,Toggled" line.word 0x04 "AQSFRC,Action-Qualifier Software Force Register" bitfld.word 0x04 6.--7. " RLDCSF ,AQCSFRC Active Register Reload From Shadow Options" "Zero,Period,Zero or Period,Immediately" bitfld.word 0x04 5. " OTSFB ,One-Time Software Forced Event on Output B" "No effect,Forced" textline " " bitfld.word 0x04 3.--4. " ACTSFB ,Action when One-Time Software Force B Is invoked" "Disabled,Cleared,Set,Toggled" bitfld.word 0x04 2. " OTSFA ,One-Time Software Forced Event on Output A" "No effect,Forced" textline " " bitfld.word 0x04 0.--1. " ACTSFA ,Action When One-Time Software Force A Is Invoked" "Disabled,Cleared,Set,Toggled" line.word 0x06 "AQCSFRC,Action-Qualifier Continuous Software Force Register" bitfld.word 0x06 2.--3. " CSFB ,Continuous Software Force on Output B" "Forced disabled,Continued low,Continued high,Soft forced disabled" bitfld.word 0x06 0.--1. " CSFA ,Continuous Software Force on Output A" "Forced disabled,Continued low,Continued high,Soft forced disabled" tree.end width 7. tree "Dead-Band Submodule Registers" group.word 0x1E++0x05 line.word 0x00 "DBCTL,Dead-Band Generator Control Register" bitfld.word 0x00 15. " HALFCYCLE ,Half Cycle Clocking Enable Bit" "Disabled,Enabled" textline " " bitfld.word 0x00 4.--5. " IN_MODE ,Dead Band Input Mode Control" "EPWMxA Faling/rising,EPWMxB rising / EPWMxA falling,EPWMxA rising / EPWMxB falling,EPWMxB both rising & falling" textline " " bitfld.word 0x00 2.--3. " POLSEL ,Polarity Select Control" "AH,ALC,AHC,AL" textline " " bitfld.word 0x00 0.--1. " OUT_MODE ,Dead-band Output Mode Control" "Dead-band generation bypassed,Disabled rising-edge delay,Rising-edge delayed signal on EPWMxA,Dead-band fully enabled" line.word 0x02 "DBRED,Dead-Band Generator Rising Edge Delay Register" hexmask.word 0x02 0.--9. 1. " DEL ,Rising Edge Delay Count" line.word 0x04 "DBFED,Dead-Band Generator Falling Edge Delay Register" hexmask.word 0x04 0.--9. 1. " DEL ,Falling Edge Delay Count" tree.end width 0x7 tree "PWM-Chopper Submodule Control Register" group.word 0x3C++0x01 line.word 0x00 "PCCTL,PWM-Chopper Control Register" bitfld.word 0x00 8.--10. " CHPDUTY ,Chopping Clock Duty Cycle" "1/8 (12.5%),2/8 (25.0%),3/8 (37.5%),4/8 (50.0%),5/8 (62.5%),6/8 (75.0%),7/8 (87.5%),?..." textline " " bitfld.word 0x00 5.--7. " CHPFREQ ,Chopping Clock Frequency" "/1 (no prescale = 12.5 MHz at 100 MHz VCLK4),/2 (6.25 MHz at 100 MHz VCLK4),/3 (4.16 MHz at 100 MHz VCLK4),/4 (3.12 MHz at 100 MHz VCLK4),/5 (2.50 MHz at 100 MHz VCLK4),/6 (2.08 MHz at 100 MHz VCLK4),/7 (1.78 MHz at 100 MHz VCLK4),/8 (1.56 MHz at 100 MHz VCLK4)" textline " " bitfld.word 0x00 1.--4. " OSHTWTH ,One-Shot Pulse Width" "1 x VCLK4 / 8 wide ( = 80 nS at 100 MHz VCLK4),2 x VCLK4 / 8 wide ( = 160 nS at 100 MHz VCLK4),3 x VCLK4 / 8 wide ( = 240 nS at 100 MHz VCLK4),4 x VCLK4 / 8 wide ( = 320 nS at 100 MHz VCLK4),5 x VCLK4 / 8 wide ( = 400 nS at 100 MHz VCLK4),6 x VCLK4 / 8 wide ( = 480 nS at 100 MHz VCLK4),7 x VCLK4 / 8 wide ( = 560 nS at 100 MHz VCLK4),8 x VCLK4 / 8 wide ( = 640 nS at 100 MHz VCLK4),9 x VCLK4 / 8 wide ( = 720 nS at 100 MHz VCLK4),10 x VCLK4 / 8 wide ( = 800 nS at 100 MHz VCLK4),11 x VCLK4 / 8 wide ( = 880 nS at 100 MHz VCLK4),12 x VCLK4 / 8 wide ( = 960 nS at 100 MHz VCLK4),13 x VCLK4 / 8 wide ( = 1040 nS at 100 MHz VCLK4),14 x VCLK4 / 8 wide ( = 1120 nS at 100 MHz VCLK4),15 x VCLK4 / 8 wide ( = 1200 nS at 100 MHz VCLK4),16 x VCLK4 / 8 wide ( = 1280 nS at 100 MHz VCLK4)" textline " " bitfld.word 0x00 0. " CHPEN ,PWM-chopping Enable" "Disabled,Enabled" tree.end width 9. tree "Trip-Zone Select Register" group.word 0x24++0x01 line.word 0x00 "TZSEL,Trip-Zone Submodule Control and Status Registers" bitfld.word 0x00 15. " DCBEVT1 ,Digital Compare Output B Event 1 Select" "Disabled,Enabled" bitfld.word 0x00 14. " DCAEVT1 ,Digital Compare Output A Event 1 Select" "Disabled,Enabled" bitfld.word 0x00 13. " OSHT6 ,Trip-zone 6 TZ6 Select" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " OSHT5 ,Trip-zone 5 TZ5 Select" "Disabled,Enabled" bitfld.word 0x00 11. " OSHT4 ,Trip-zone 4 TZ4 Select" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OSHT3 ,Trip-zone 3 TZ3 Select" "Disabled,Enabled" bitfld.word 0x00 9. " OSHT2 ,Trip-zone 2 TZ2 Select" "Disabled,Enabled" bitfld.word 0x00 8. " OSHT1 ,Trip-zone 1 TZ) Select" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " DCBEVT2 ,Digital Compare Output B Event 2 Select" "Disabled,Enabled" bitfld.word 0x00 6. " DCAEVT2 ,Digital Compare Output A Event 2 Select" "Disabled,Enabled" bitfld.word 0x00 5. " CBC6 ,Trip-zone 6 TZ6 Select" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " CBC5 ,Trip-zone 5 TZ5 Select" "Disabled,Enabled" bitfld.word 0x00 3. " CBC4 ,Trip-zone 4 TZ4 Select" "Disabled,Enabled" bitfld.word 0x00 2. " CBC3 ,Trip-zone 3 TZ3 Select" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " CBC2 ,Trip-zone 2 TZ2 Select" "Disabled,Enabled" bitfld.word 0x00 0. " CBC1 ,Trip-zone 1 TZ1 Select" "Disabled,Enabled" group.word 0x28++0x01 line.word 0x00 "TZCTL,Trip-Zone Control Register" bitfld.word 0x00 10.--11. " DCBEVT2 ,Digital Compare Output B Event 2 Action On EPWMxB" "High-impedance,High state,Low state,Disabled" bitfld.word 0x00 8.--9. " DCBEVT1 ,Digital Compare Output B Event 1 Action On EPWMxB" "High-impedance,Forced high state,Forced low state,Disabled" textline " " bitfld.word 0x00 6.--7. " DCAEVT2 ,Digital Compare Output A Event 2 Action On EPWMxA" "High-impedance,Forced high state,Forced low state,Disabled" bitfld.word 0x00 4.--5. " DCAEVT1 ,Digital Compare Output A Event 1 Action On EPWMxA" "High-impedance,Forced high state,Forced low state,Disabled" textline " " bitfld.word 0x00 2.--3. " TZB ,When a trip event occurs the following action is taken on output EPWMxB" "High-impedance,Forced high state,Forced low state,Disabled" bitfld.word 0x00 0.--1. " TZA ,When a trip event occurs the following action is taken on output EPWMxA" "High-impedance,Forced high state,Forced low state,Disabled" group.word 0x2C++0x01 line.word 0x00 "TZFLG,Trip-Zone Flag Register Field Descriptions" setclrfld.word 0x00 6. -0x02 6. 0x02 6. " DCBEVT2_set/clr ,Digital Comparator Output B Event 2 Interrupt" "Not occurred,Occurred" setclrfld.word 0x00 5. -0x02 5. 0x02 5. " DCBEVT1_set/clr ,Digital Comparator Output B Event 1 Interrupt" "Not occurred,Occurred" textline " " setclrfld.word 0x00 4. -0x02 4. 0x02 4. " DCAEVT2_set/clr ,Digital Comparator Output A Event 2 Interrupt" "Not occurred,Occurred" setclrfld.word 0x00 3. -0x02 3. 0x02 3. " DCAEVT1_set/clr ,Digital Comparator Output A Event 1 Interrupt" "Not occurred,Occurred" textline " " setclrfld.word 0x00 2. -0x02 2. 0x02 2. " OST_set/clr ,Trip-zone One-Shot Interrupt" "Not occurred,Occurred" setclrfld.word 0x00 1. -0x02 1. 0x02 1. " CBC_set/clr ,Trip-zone Cycle-by-Cycle Interrupt" "Not occurred,Occurred" textline " " setclrfld.word 0x00 0. 0x00 0. 0x02 0. " INT_set/clr ,Latched Trip Interrupt Status Flag" "Not generated,Generated" group.word 0x30++0x01 line.word 0x00 "TZFRC,Trip-Zone Force Register" bitfld.word 0x00 6. " DCBEVT2 ,Force Flag for Digital Compare Output B Event 2" "No effect,Forced" bitfld.word 0x00 5. " DCBEVT1 ,Force Flag for Digital Compare Output B Event 1" "No effect,Forced" textline " " bitfld.word 0x00 4. " DCAEVT2 ,Force Flag for Digital Compare Output A Event 2" "No effect,Forced" bitfld.word 0x00 3. " DCAEVT1 ,Force Flag for Digital Compare Output A Event 1" "No effect,Forced" textline " " bitfld.word 0x00 2. " OST ,Force a One-Shot Trip Event via Software" "No effect,Forced" bitfld.word 0x00 1. " CBC ,Force a Cycle-by-Cycle Trip Event via Software" "No effect,Forced" group.word 0x26++0x01 line.word 0x00 "TZDCSEL,Trip Zone Digital Compare Event Select Register" bitfld.word 0x00 9.--11. " DCBEVT2 ,Digital Compare Output B Event 2 Selection" "Event disabled,DCBH = low,DCBH = high,DCBL = low,DCBL = high,DCBL = high - DCBH = low,?..." bitfld.word 0x00 6.--8. " DCBEVT1 ,Digital Compare Output B Event 1 Selection" "Event disabled,DCBH = low,DCBH = high,DCBL = low,DCBL = high,DCBL = high - DCBH = low,?..." textline " " bitfld.word 0x00 3.--5. " DCAEVT2 ,Digital Compare Output A Event 2 Selection" "Event disabled,DCAH = low,DCAH = high,DCAL = low,DCAL = high,DCAL = high - DCAH = low,?..." bitfld.word 0x00 0.--2. " DCAEVT1 ,Digital Compare Output A Event 1 Selection" "Event disabled,DCAH = low,DCAH = high,DCAL = low,DCAL = high,DCAL = high,?..." tree.end width 11. tree "Digital Compare Submodule Registers" group.word 0x60++0x09 line.word 0x00 "DCTRIPSEL,Digital Compare Trip Select" bitfld.word 0x00 12.--15. " DCBLCOMPSEL ,Digital Compare B Low Input Select" "TZ1 input,TZ2 input,TZ3 input,?..." bitfld.word 0x00 8.--11. " DCBHCOMPSEL ,Digital Compare B High Input Select" "TZ1 input,TZ2 input,TZ3 input,?..." textline " " bitfld.word 0x00 4.--7. " DCALCOMPSEL ,Digital Compare A Low Input Select" "TZ1 input,TZ2 input,TZ3 input,?..." bitfld.word 0x00 0.--3. " DCAHCOMPSEL ,Digital Compare A High Input Select" "TZ1 input,TZ2 input,TZ3 input,?..." line.word 0x02 "DCACTL,Digital Compare A Control Register" bitfld.word 0x02 9. " EVT2FRC_SYNCSEL ,DCAEVT2 Force Synchronization Signal Select" "Synchronous,Asynchronous" bitfld.word 0x02 8. " EVT2SRCSEL ,DCAEVT2 Source Signal Select" "DCAEVT2,DCEVTFILT" textline " " bitfld.word 0x02 3. " EVT1SYNCE ,DCAEVT1 SYNC Generation" "Disabled,Enabled" bitfld.word 0x02 2. " EVT1SOCE ,DCAEVT1 SOC Generation" "Disabled,Enabled" textline " " bitfld.word 0x02 1. " EVT1FRC_SYNCSEL ,DCAEVT1 Force Synchronization Signal Select" "Synchronous,Asynchronous" bitfld.word 0x02 0. " EVT1SRCSEL ,DCAEVT1 Source Signal Select" "DCAEVT,DCEVTFILT" line.word 0x04 "DCBCTL,Digital Compare B Control Register" bitfld.word 0x04 9. " EVT2FRC_SYNCSEL ,DCBEVT2 Force Synchronization Signal Select" "Synchronous,Asynchronous" bitfld.word 0x04 8. " EVT2SRCSEL ,DCBEVT2 Source Signal Select" "DCBEVT2,DCEVTFILT" textline " " bitfld.word 0x04 3. " EVT1SYNCE ,DCBEVT1 SYNC Generation" "Disabled,Enabled" bitfld.word 0x04 2. " EVT1SOCE ,DCBEVT1 SOC Generation" "Disabled,Enabled" textline " " bitfld.word 0x04 1. " EVT1FRC_SYNCSEL ,DCBEVT1 Force Synchronization Signal Select" "Synchronous,Asynchronous" bitfld.word 0x04 0. " EVT1SRCSEL ,DCBEVT1 Source Signal Select" "DCBEVT,DCEVTFILT" line.word 0x06 "DBFCTL,Digital Compare Filter Control Register" bitfld.word 0x06 4.--5. " PULSESEL ,Pulse Select For Blanking & Capture Alignment" "TB CNT Equal to period,TB CNT Equal to zero,?..." textline " " bitfld.word 0x06 3. " BLANKINV ,Blanking Window Inversion" "Not inverted,Inverted" bitfld.word 0x06 2. " BLANKE ,Blanking Window Enable/Disable" "Disabled,Enabled" textline " " bitfld.word 0x06 0.--1. " SRCSEL ,Filter Block Signal Source Select" "DCAEVT1,DCAEVT2,DCBEVT1,DCBEVT2" line.word 0x08 "DBCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x08 1. " SHDWMODE ,TBCTR Counter Capture Shadow Select Mode" "Shadow mode,Active Mode" bitfld.word 0x08 0. " CAPE ,TBCTR Counter Capture Enable/Disable" "Disabled,Enabled" width 14. rgroup.word 0x72++0x01 line.word 0x00 "DCCAP,Digital Compare Counter Capture Register" rgroup.word 0x6A++0x01 line.word 0x00 "DCFOFFSET,Digital Compare Filter Offset Register" group.word 0x6E++0x01 line.word 0x00 "DCFWINDOW,Digital Compare Filter Window Register" hexmask.word.byte 0x00 0.--7. 1. " WINDOW ,Blanking Window Width" rgroup.word 0x70++0x01 line.word 0x00 "DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word.byte 0x00 0.--7. 1. " WINDOWCNT ,Digital Compare Filter Window Counter Register" tree.end width 7. tree "Event-Trigger Submodule Registers" group.word 0x32++0x09 line.word 0x00 "ETSEL,Event-Trigger Selection Register" bitfld.word 0x00 15. " SOCBEN ,Enable the ADC Start of Conversion B EPWMxSOCB Pulse" "Disabled,Enabled" bitfld.word 0x00 12.--14. " SOCBSEL ,EPWMxSOCB Selection Options" "DCBEVT1_soc,TB CNT equal to zero,TB CNT equal to period,TB CNT equal to zero or period,TB CNT equal to CMPA - Timer INC,TB CNT equal to CMPA - Timer DEC,TB CNT equal to CMPB - Timer INC,TB CNT equal to CMPB - Timer DEC" textline " " bitfld.word 0x00 11. " SOCAEN ,Enable the ADC Start of Conversion A EPWMxSOCA Pulse" "Disabled,Enabled" bitfld.word 0x00 8.--10. " SOCASEL ,EPWMxSOCA Selection Options" "DCAEVT1_soc,TB CNT equal to zero,TB CNT equal to period,TB CNT equal to zero or period,TB CNT equal to CMPA - Timer INC,TB CNT equal to CMPA - Timer DEC,TB CNT equal to CMPB - Timer INC,TB CNT equal to CMPB - Timer DEC" textline " " bitfld.word 0x00 3. " INTEN ,Enable ePWM Interrupt EPWMx_INT Generation" "Disabled,Enabled" bitfld.word 0x00 0.--2. " INTSEL ,ePWM Interrupt EPWMx_INT Selection Options" "Reserved,TB CNT equal to zero,TB CNT equal to period,TB CNT equal to zero or period,TB CNT equal to CMPA - Timer INC,TB CNT equal to CMPA - Timer DEC,TB CNT equal to CMPB - Timer INC,TB CNT equal to CMPB - Timer DEC" line.word 0x02 "ETPS,Event-Trigger Prescale Register" bitfld.word 0x02 14.--15. " SOCBCNT ,ePWM ADC Start-of-Conversion B Event EPWMxSOCB Counter Register" "No events,1 event,2 events,3 events" bitfld.word 0x02 12.--13. " SOCBPRD ,ePWM ADC Start-of-Conversion B Event EPWMxSOCB Period Select" "Disabled,1st event,2nd event,3th event" textline " " bitfld.word 0x02 10.--11. " SOCACNT ,ePWM ADC Start-of-Conversion A Event EPWMxSOCA Counter Register" "No events,1 event,2 events,3 events" bitfld.word 0x02 8.--9. " SOCAPRD ,ePWM ADC Start-of-Conversion A Event EPWMxSOCA Period Select" "Disabled,1st event,2nd event,3th event" textline " " bitfld.word 0x02 2.--3. " INTCNT ,ePWM Interrupt Event EPWMx_INT Counter Register" "No events,1 event,2 events,3 events" bitfld.word 0x02 0.--1. " INTPRD ,ePWM Interrupt EPWMx_INT Period Select" "Disabled,1st event,2nd event,3th event" line.word 0x04 "ETFLG,Event-Trigger Flag Register" bitfld.word 0x04 3. " SOCB ,Latched ePWM ADC Start-of-Conversion B EPWMxSOCB Status Flag" "Not occurred,Occurred" bitfld.word 0x04 2. " SOCA ,Latched ePWM ADC Start-of-Conversion A EPWMxSOCA Status Flag" "Not occurred,Occurred" textline " " bitfld.word 0x04 0. " INT ,Latched ePWM Interrupt EPWMx_INT Status Flag" "Not occurred,Occurred" line.word 0x06 "ETCLR,Event-Trigger Clear Register" bitfld.word 0x06 3. " SOCB ,ePWM ADC Start-of-Conversion B EPWMxSOCB Flag Clear Bit" "No effect,Cleared" bitfld.word 0x06 2. " SOCA ,ePWM ADC Start-of-Conversion A EPWMxSOCB Flag Clear Bit" "No effect,Cleared" textline " " bitfld.word 0x06 0. " INT ,ePWM Interrupt EPWMx_INT Flag Clear Bit" "No effect,Cleared" line.word 0x08 "ETFRC,Event-Trigger Force Register" bitfld.word 0x08 3. " SOCB ,SOCB Force Bit" "No effect,Forced" bitfld.word 0x08 2. " SOCA ,SOCA Force Bit" "No effect,Forced" textline " " bitfld.word 0x08 0. " INT ,INT Force Bit" "No effect,Forced" tree.end width 0xB tree.end tree "ePWM 4" base ad:0xFCF78F00 width 14. tree "Time-Base Submodule Registers" group.word 0x0A++0x01 line.word 0x00 "TBPRD,Time-Base Period Register" group.word 0x06++0x03 line.word 0x00 "TBPHS,Time-Base Phase Register" line.word 0x02 "TBCTR,Time-Base Counter Register" group.word 0x00++0x03 line.word 0x00 "TBCTL,Time-Base Control Register" bitfld.word 0x00 14.--15. " FREE/SOFT ,Emulation Mode Bits" "Stop after the next time-base counter INC or DEC,Stop when counter completes a whole cycle,Free run,Free run" textline " " bitfld.word 0x00 13. " PHSDIR ,Phase Direction Bit" "Count down,Count up" bitfld.word 0x00 10.--12. " CLKDIV ,Time-base Clock Prescale Bits" "/1,/2,/4,/8,/16,/32,/64,/128" textline " " bitfld.word 0x00 7.--9. " HSPCLKDIV ,High Speed Time-base Clock Prescale Bits" "/1,/2,/4,/8,/8,/10,/12,/14" bitfld.word 0x00 6. " SWFSYNC ,Software Forced Synchronization Pulse" "No effect,Generated" textline " " bitfld.word 0x00 4.--5. " SYNCOSEL ,Synchronization Output Select" "EPWMxSYNC,CTR = zero,CTR = CMPB,EPWMxSYNCO disable" bitfld.word 0x00 3. " PRDLD ,Active Period Register Load From Shadow Register Select" "Not selected,Selected" bitfld.word 0x00 2. " PHSEN ,Counter Register Load From Phase Register Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0.--1. " CTRMODE ,Counter Mode" "Up-count,Down-count,Up-down-count,Stop-freeze counter operation" line.word 0x02 "TBSTS,Time-Base Status Register" bitfld.word 0x02 2. " CTRMAX ,Time-Base Counter Max Latched Status Bit time-base counter maximum value" "Not reached,Reached" bitfld.word 0x02 1. " SYNCI ,Input Synchronization Latched Status Bit external synchronization event" "Not occurred,Occurred" textline " " bitfld.word 0x02 0. " CTRDIR ,Time-Base Counter Direction Status Bit" "Down,Up" tree.end width 8. tree "Counter-Compare Submodule Registers" group.word 0x12++0x03 line.word 0x00 "CMPA,Counter-Compare A Register" line.word 0x02 "CMPB,Counter-Compare B Register" group.word 0x0E++0x1 line.word 0x00 "CMPCTL,Counter-Compare Control Register" bitfld.word 0x00 9. " SHDWBFULL ,Counter-compare B CMPB Shadow Register Full Status Flag" "Not full,Full" bitfld.word 0x00 8. " SHDWAFULL ,Counter-compare A CMPA Shadow Register Full Status Flag" "Not full,Full" textline " " bitfld.word 0x00 6. " SHDWBMODE ,Counter-compare B CMPB Register Operating Mode" "Shadow,Immediate" bitfld.word 0x00 4. " SHDWAMODE ,Counter-compare A CMPA Register Operating Mode" "Shadow,Immediate" textline " " bitfld.word 0x00 2.--3. " LOADBMODE ,Active Counter-Compare B CMPB Load From Shadow Select Mode" "CTR = Zero,CTR = PRD,CTR = Zero or CTR = PRD,Freeze" bitfld.word 0x00 0.--1. " LOADAMODE ,Active Counter-Compare A CMPA Load From Shadow Select Mode" "CTR = Zero,CTR = PRD,CTR = Zero or CTR = PRD,Freeze" tree.end width 9. tree "Action-Qualifier Submodule Registers" group.word 0x16++0x07 line.word 0x00 "AQCTLA,Action-Qualifier Output A Control Register" bitfld.word 0x00 10.--11. " CBD ,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "Disabled,Cleared,Set,Toggled" bitfld.word 0x00 8.--9. " CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,Cleared,Set,Toggled" textline " " bitfld.word 0x00 6.--7. " CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,Cleared,Set,Toggled" bitfld.word 0x00 4.--5. " CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,Cleared,Set,Toggled" textline " " bitfld.word 0x00 2.--3. " PRD ,Action when the counter equals the period" "Disabled,Cleared,Set,Toggled" bitfld.word 0x00 0.--1. " ZRO ,Action when counter equals zero" "Disabled,Cleared,Set,Toggled" line.word 0x02 "AQCTLB,Action-Qualifier Output B Control Register" bitfld.word 0x02 10.--11. " CBD ,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "Disabled,Cleared,Set,Toggled" bitfld.word 0x02 8.--9. " CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,Cleared,Set,Toggled" textline " " bitfld.word 0x02 6.--7. " CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,Cleared,Set,Toggled" bitfld.word 0x02 4.--5. " CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,Cleared,Set,Toggled" textline " " bitfld.word 0x02 2.--3. " PRD ,Action when the counter equals the period" "Disabled,Cleared,Set,Toggled" bitfld.word 0x02 0.--1. " ZRO ,Action when counter equals zero" "Disabled,Cleared,Set,Toggled" line.word 0x04 "AQSFRC,Action-Qualifier Software Force Register" bitfld.word 0x04 6.--7. " RLDCSF ,AQCSFRC Active Register Reload From Shadow Options" "Zero,Period,Zero or Period,Immediately" bitfld.word 0x04 5. " OTSFB ,One-Time Software Forced Event on Output B" "No effect,Forced" textline " " bitfld.word 0x04 3.--4. " ACTSFB ,Action when One-Time Software Force B Is invoked" "Disabled,Cleared,Set,Toggled" bitfld.word 0x04 2. " OTSFA ,One-Time Software Forced Event on Output A" "No effect,Forced" textline " " bitfld.word 0x04 0.--1. " ACTSFA ,Action When One-Time Software Force A Is Invoked" "Disabled,Cleared,Set,Toggled" line.word 0x06 "AQCSFRC,Action-Qualifier Continuous Software Force Register" bitfld.word 0x06 2.--3. " CSFB ,Continuous Software Force on Output B" "Forced disabled,Continued low,Continued high,Soft forced disabled" bitfld.word 0x06 0.--1. " CSFA ,Continuous Software Force on Output A" "Forced disabled,Continued low,Continued high,Soft forced disabled" tree.end width 7. tree "Dead-Band Submodule Registers" group.word 0x1E++0x05 line.word 0x00 "DBCTL,Dead-Band Generator Control Register" bitfld.word 0x00 15. " HALFCYCLE ,Half Cycle Clocking Enable Bit" "Disabled,Enabled" textline " " bitfld.word 0x00 4.--5. " IN_MODE ,Dead Band Input Mode Control" "EPWMxA Faling/rising,EPWMxB rising / EPWMxA falling,EPWMxA rising / EPWMxB falling,EPWMxB both rising & falling" textline " " bitfld.word 0x00 2.--3. " POLSEL ,Polarity Select Control" "AH,ALC,AHC,AL" textline " " bitfld.word 0x00 0.--1. " OUT_MODE ,Dead-band Output Mode Control" "Dead-band generation bypassed,Disabled rising-edge delay,Rising-edge delayed signal on EPWMxA,Dead-band fully enabled" line.word 0x02 "DBRED,Dead-Band Generator Rising Edge Delay Register" hexmask.word 0x02 0.--9. 1. " DEL ,Rising Edge Delay Count" line.word 0x04 "DBFED,Dead-Band Generator Falling Edge Delay Register" hexmask.word 0x04 0.--9. 1. " DEL ,Falling Edge Delay Count" tree.end width 0x7 tree "PWM-Chopper Submodule Control Register" group.word 0x3C++0x01 line.word 0x00 "PCCTL,PWM-Chopper Control Register" bitfld.word 0x00 8.--10. " CHPDUTY ,Chopping Clock Duty Cycle" "1/8 (12.5%),2/8 (25.0%),3/8 (37.5%),4/8 (50.0%),5/8 (62.5%),6/8 (75.0%),7/8 (87.5%),?..." textline " " bitfld.word 0x00 5.--7. " CHPFREQ ,Chopping Clock Frequency" "/1 (no prescale = 12.5 MHz at 100 MHz VCLK4),/2 (6.25 MHz at 100 MHz VCLK4),/3 (4.16 MHz at 100 MHz VCLK4),/4 (3.12 MHz at 100 MHz VCLK4),/5 (2.50 MHz at 100 MHz VCLK4),/6 (2.08 MHz at 100 MHz VCLK4),/7 (1.78 MHz at 100 MHz VCLK4),/8 (1.56 MHz at 100 MHz VCLK4)" textline " " bitfld.word 0x00 1.--4. " OSHTWTH ,One-Shot Pulse Width" "1 x VCLK4 / 8 wide ( = 80 nS at 100 MHz VCLK4),2 x VCLK4 / 8 wide ( = 160 nS at 100 MHz VCLK4),3 x VCLK4 / 8 wide ( = 240 nS at 100 MHz VCLK4),4 x VCLK4 / 8 wide ( = 320 nS at 100 MHz VCLK4),5 x VCLK4 / 8 wide ( = 400 nS at 100 MHz VCLK4),6 x VCLK4 / 8 wide ( = 480 nS at 100 MHz VCLK4),7 x VCLK4 / 8 wide ( = 560 nS at 100 MHz VCLK4),8 x VCLK4 / 8 wide ( = 640 nS at 100 MHz VCLK4),9 x VCLK4 / 8 wide ( = 720 nS at 100 MHz VCLK4),10 x VCLK4 / 8 wide ( = 800 nS at 100 MHz VCLK4),11 x VCLK4 / 8 wide ( = 880 nS at 100 MHz VCLK4),12 x VCLK4 / 8 wide ( = 960 nS at 100 MHz VCLK4),13 x VCLK4 / 8 wide ( = 1040 nS at 100 MHz VCLK4),14 x VCLK4 / 8 wide ( = 1120 nS at 100 MHz VCLK4),15 x VCLK4 / 8 wide ( = 1200 nS at 100 MHz VCLK4),16 x VCLK4 / 8 wide ( = 1280 nS at 100 MHz VCLK4)" textline " " bitfld.word 0x00 0. " CHPEN ,PWM-chopping Enable" "Disabled,Enabled" tree.end width 9. tree "Trip-Zone Select Register" group.word 0x24++0x01 line.word 0x00 "TZSEL,Trip-Zone Submodule Control and Status Registers" bitfld.word 0x00 15. " DCBEVT1 ,Digital Compare Output B Event 1 Select" "Disabled,Enabled" bitfld.word 0x00 14. " DCAEVT1 ,Digital Compare Output A Event 1 Select" "Disabled,Enabled" bitfld.word 0x00 13. " OSHT6 ,Trip-zone 6 TZ6 Select" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " OSHT5 ,Trip-zone 5 TZ5 Select" "Disabled,Enabled" bitfld.word 0x00 11. " OSHT4 ,Trip-zone 4 TZ4 Select" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OSHT3 ,Trip-zone 3 TZ3 Select" "Disabled,Enabled" bitfld.word 0x00 9. " OSHT2 ,Trip-zone 2 TZ2 Select" "Disabled,Enabled" bitfld.word 0x00 8. " OSHT1 ,Trip-zone 1 TZ) Select" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " DCBEVT2 ,Digital Compare Output B Event 2 Select" "Disabled,Enabled" bitfld.word 0x00 6. " DCAEVT2 ,Digital Compare Output A Event 2 Select" "Disabled,Enabled" bitfld.word 0x00 5. " CBC6 ,Trip-zone 6 TZ6 Select" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " CBC5 ,Trip-zone 5 TZ5 Select" "Disabled,Enabled" bitfld.word 0x00 3. " CBC4 ,Trip-zone 4 TZ4 Select" "Disabled,Enabled" bitfld.word 0x00 2. " CBC3 ,Trip-zone 3 TZ3 Select" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " CBC2 ,Trip-zone 2 TZ2 Select" "Disabled,Enabled" bitfld.word 0x00 0. " CBC1 ,Trip-zone 1 TZ1 Select" "Disabled,Enabled" group.word 0x28++0x01 line.word 0x00 "TZCTL,Trip-Zone Control Register" bitfld.word 0x00 10.--11. " DCBEVT2 ,Digital Compare Output B Event 2 Action On EPWMxB" "High-impedance,High state,Low state,Disabled" bitfld.word 0x00 8.--9. " DCBEVT1 ,Digital Compare Output B Event 1 Action On EPWMxB" "High-impedance,Forced high state,Forced low state,Disabled" textline " " bitfld.word 0x00 6.--7. " DCAEVT2 ,Digital Compare Output A Event 2 Action On EPWMxA" "High-impedance,Forced high state,Forced low state,Disabled" bitfld.word 0x00 4.--5. " DCAEVT1 ,Digital Compare Output A Event 1 Action On EPWMxA" "High-impedance,Forced high state,Forced low state,Disabled" textline " " bitfld.word 0x00 2.--3. " TZB ,When a trip event occurs the following action is taken on output EPWMxB" "High-impedance,Forced high state,Forced low state,Disabled" bitfld.word 0x00 0.--1. " TZA ,When a trip event occurs the following action is taken on output EPWMxA" "High-impedance,Forced high state,Forced low state,Disabled" group.word 0x2C++0x01 line.word 0x00 "TZFLG,Trip-Zone Flag Register Field Descriptions" setclrfld.word 0x00 6. -0x02 6. 0x02 6. " DCBEVT2_set/clr ,Digital Comparator Output B Event 2 Interrupt" "Not occurred,Occurred" setclrfld.word 0x00 5. -0x02 5. 0x02 5. " DCBEVT1_set/clr ,Digital Comparator Output B Event 1 Interrupt" "Not occurred,Occurred" textline " " setclrfld.word 0x00 4. -0x02 4. 0x02 4. " DCAEVT2_set/clr ,Digital Comparator Output A Event 2 Interrupt" "Not occurred,Occurred" setclrfld.word 0x00 3. -0x02 3. 0x02 3. " DCAEVT1_set/clr ,Digital Comparator Output A Event 1 Interrupt" "Not occurred,Occurred" textline " " setclrfld.word 0x00 2. -0x02 2. 0x02 2. " OST_set/clr ,Trip-zone One-Shot Interrupt" "Not occurred,Occurred" setclrfld.word 0x00 1. -0x02 1. 0x02 1. " CBC_set/clr ,Trip-zone Cycle-by-Cycle Interrupt" "Not occurred,Occurred" textline " " setclrfld.word 0x00 0. 0x00 0. 0x02 0. " INT_set/clr ,Latched Trip Interrupt Status Flag" "Not generated,Generated" group.word 0x30++0x01 line.word 0x00 "TZFRC,Trip-Zone Force Register" bitfld.word 0x00 6. " DCBEVT2 ,Force Flag for Digital Compare Output B Event 2" "No effect,Forced" bitfld.word 0x00 5. " DCBEVT1 ,Force Flag for Digital Compare Output B Event 1" "No effect,Forced" textline " " bitfld.word 0x00 4. " DCAEVT2 ,Force Flag for Digital Compare Output A Event 2" "No effect,Forced" bitfld.word 0x00 3. " DCAEVT1 ,Force Flag for Digital Compare Output A Event 1" "No effect,Forced" textline " " bitfld.word 0x00 2. " OST ,Force a One-Shot Trip Event via Software" "No effect,Forced" bitfld.word 0x00 1. " CBC ,Force a Cycle-by-Cycle Trip Event via Software" "No effect,Forced" group.word 0x26++0x01 line.word 0x00 "TZDCSEL,Trip Zone Digital Compare Event Select Register" bitfld.word 0x00 9.--11. " DCBEVT2 ,Digital Compare Output B Event 2 Selection" "Event disabled,DCBH = low,DCBH = high,DCBL = low,DCBL = high,DCBL = high - DCBH = low,?..." bitfld.word 0x00 6.--8. " DCBEVT1 ,Digital Compare Output B Event 1 Selection" "Event disabled,DCBH = low,DCBH = high,DCBL = low,DCBL = high,DCBL = high - DCBH = low,?..." textline " " bitfld.word 0x00 3.--5. " DCAEVT2 ,Digital Compare Output A Event 2 Selection" "Event disabled,DCAH = low,DCAH = high,DCAL = low,DCAL = high,DCAL = high - DCAH = low,?..." bitfld.word 0x00 0.--2. " DCAEVT1 ,Digital Compare Output A Event 1 Selection" "Event disabled,DCAH = low,DCAH = high,DCAL = low,DCAL = high,DCAL = high,?..." tree.end width 11. tree "Digital Compare Submodule Registers" group.word 0x60++0x09 line.word 0x00 "DCTRIPSEL,Digital Compare Trip Select" bitfld.word 0x00 12.--15. " DCBLCOMPSEL ,Digital Compare B Low Input Select" "TZ1 input,TZ2 input,TZ3 input,?..." bitfld.word 0x00 8.--11. " DCBHCOMPSEL ,Digital Compare B High Input Select" "TZ1 input,TZ2 input,TZ3 input,?..." textline " " bitfld.word 0x00 4.--7. " DCALCOMPSEL ,Digital Compare A Low Input Select" "TZ1 input,TZ2 input,TZ3 input,?..." bitfld.word 0x00 0.--3. " DCAHCOMPSEL ,Digital Compare A High Input Select" "TZ1 input,TZ2 input,TZ3 input,?..." line.word 0x02 "DCACTL,Digital Compare A Control Register" bitfld.word 0x02 9. " EVT2FRC_SYNCSEL ,DCAEVT2 Force Synchronization Signal Select" "Synchronous,Asynchronous" bitfld.word 0x02 8. " EVT2SRCSEL ,DCAEVT2 Source Signal Select" "DCAEVT2,DCEVTFILT" textline " " bitfld.word 0x02 3. " EVT1SYNCE ,DCAEVT1 SYNC Generation" "Disabled,Enabled" bitfld.word 0x02 2. " EVT1SOCE ,DCAEVT1 SOC Generation" "Disabled,Enabled" textline " " bitfld.word 0x02 1. " EVT1FRC_SYNCSEL ,DCAEVT1 Force Synchronization Signal Select" "Synchronous,Asynchronous" bitfld.word 0x02 0. " EVT1SRCSEL ,DCAEVT1 Source Signal Select" "DCAEVT,DCEVTFILT" line.word 0x04 "DCBCTL,Digital Compare B Control Register" bitfld.word 0x04 9. " EVT2FRC_SYNCSEL ,DCBEVT2 Force Synchronization Signal Select" "Synchronous,Asynchronous" bitfld.word 0x04 8. " EVT2SRCSEL ,DCBEVT2 Source Signal Select" "DCBEVT2,DCEVTFILT" textline " " bitfld.word 0x04 3. " EVT1SYNCE ,DCBEVT1 SYNC Generation" "Disabled,Enabled" bitfld.word 0x04 2. " EVT1SOCE ,DCBEVT1 SOC Generation" "Disabled,Enabled" textline " " bitfld.word 0x04 1. " EVT1FRC_SYNCSEL ,DCBEVT1 Force Synchronization Signal Select" "Synchronous,Asynchronous" bitfld.word 0x04 0. " EVT1SRCSEL ,DCBEVT1 Source Signal Select" "DCBEVT,DCEVTFILT" line.word 0x06 "DBFCTL,Digital Compare Filter Control Register" bitfld.word 0x06 4.--5. " PULSESEL ,Pulse Select For Blanking & Capture Alignment" "TB CNT Equal to period,TB CNT Equal to zero,?..." textline " " bitfld.word 0x06 3. " BLANKINV ,Blanking Window Inversion" "Not inverted,Inverted" bitfld.word 0x06 2. " BLANKE ,Blanking Window Enable/Disable" "Disabled,Enabled" textline " " bitfld.word 0x06 0.--1. " SRCSEL ,Filter Block Signal Source Select" "DCAEVT1,DCAEVT2,DCBEVT1,DCBEVT2" line.word 0x08 "DBCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x08 1. " SHDWMODE ,TBCTR Counter Capture Shadow Select Mode" "Shadow mode,Active Mode" bitfld.word 0x08 0. " CAPE ,TBCTR Counter Capture Enable/Disable" "Disabled,Enabled" width 14. rgroup.word 0x72++0x01 line.word 0x00 "DCCAP,Digital Compare Counter Capture Register" rgroup.word 0x6A++0x01 line.word 0x00 "DCFOFFSET,Digital Compare Filter Offset Register" group.word 0x6E++0x01 line.word 0x00 "DCFWINDOW,Digital Compare Filter Window Register" hexmask.word.byte 0x00 0.--7. 1. " WINDOW ,Blanking Window Width" rgroup.word 0x70++0x01 line.word 0x00 "DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word.byte 0x00 0.--7. 1. " WINDOWCNT ,Digital Compare Filter Window Counter Register" tree.end width 7. tree "Event-Trigger Submodule Registers" group.word 0x32++0x09 line.word 0x00 "ETSEL,Event-Trigger Selection Register" bitfld.word 0x00 15. " SOCBEN ,Enable the ADC Start of Conversion B EPWMxSOCB Pulse" "Disabled,Enabled" bitfld.word 0x00 12.--14. " SOCBSEL ,EPWMxSOCB Selection Options" "DCBEVT1_soc,TB CNT equal to zero,TB CNT equal to period,TB CNT equal to zero or period,TB CNT equal to CMPA - Timer INC,TB CNT equal to CMPA - Timer DEC,TB CNT equal to CMPB - Timer INC,TB CNT equal to CMPB - Timer DEC" textline " " bitfld.word 0x00 11. " SOCAEN ,Enable the ADC Start of Conversion A EPWMxSOCA Pulse" "Disabled,Enabled" bitfld.word 0x00 8.--10. " SOCASEL ,EPWMxSOCA Selection Options" "DCAEVT1_soc,TB CNT equal to zero,TB CNT equal to period,TB CNT equal to zero or period,TB CNT equal to CMPA - Timer INC,TB CNT equal to CMPA - Timer DEC,TB CNT equal to CMPB - Timer INC,TB CNT equal to CMPB - Timer DEC" textline " " bitfld.word 0x00 3. " INTEN ,Enable ePWM Interrupt EPWMx_INT Generation" "Disabled,Enabled" bitfld.word 0x00 0.--2. " INTSEL ,ePWM Interrupt EPWMx_INT Selection Options" "Reserved,TB CNT equal to zero,TB CNT equal to period,TB CNT equal to zero or period,TB CNT equal to CMPA - Timer INC,TB CNT equal to CMPA - Timer DEC,TB CNT equal to CMPB - Timer INC,TB CNT equal to CMPB - Timer DEC" line.word 0x02 "ETPS,Event-Trigger Prescale Register" bitfld.word 0x02 14.--15. " SOCBCNT ,ePWM ADC Start-of-Conversion B Event EPWMxSOCB Counter Register" "No events,1 event,2 events,3 events" bitfld.word 0x02 12.--13. " SOCBPRD ,ePWM ADC Start-of-Conversion B Event EPWMxSOCB Period Select" "Disabled,1st event,2nd event,3th event" textline " " bitfld.word 0x02 10.--11. " SOCACNT ,ePWM ADC Start-of-Conversion A Event EPWMxSOCA Counter Register" "No events,1 event,2 events,3 events" bitfld.word 0x02 8.--9. " SOCAPRD ,ePWM ADC Start-of-Conversion A Event EPWMxSOCA Period Select" "Disabled,1st event,2nd event,3th event" textline " " bitfld.word 0x02 2.--3. " INTCNT ,ePWM Interrupt Event EPWMx_INT Counter Register" "No events,1 event,2 events,3 events" bitfld.word 0x02 0.--1. " INTPRD ,ePWM Interrupt EPWMx_INT Period Select" "Disabled,1st event,2nd event,3th event" line.word 0x04 "ETFLG,Event-Trigger Flag Register" bitfld.word 0x04 3. " SOCB ,Latched ePWM ADC Start-of-Conversion B EPWMxSOCB Status Flag" "Not occurred,Occurred" bitfld.word 0x04 2. " SOCA ,Latched ePWM ADC Start-of-Conversion A EPWMxSOCA Status Flag" "Not occurred,Occurred" textline " " bitfld.word 0x04 0. " INT ,Latched ePWM Interrupt EPWMx_INT Status Flag" "Not occurred,Occurred" line.word 0x06 "ETCLR,Event-Trigger Clear Register" bitfld.word 0x06 3. " SOCB ,ePWM ADC Start-of-Conversion B EPWMxSOCB Flag Clear Bit" "No effect,Cleared" bitfld.word 0x06 2. " SOCA ,ePWM ADC Start-of-Conversion A EPWMxSOCB Flag Clear Bit" "No effect,Cleared" textline " " bitfld.word 0x06 0. " INT ,ePWM Interrupt EPWMx_INT Flag Clear Bit" "No effect,Cleared" line.word 0x08 "ETFRC,Event-Trigger Force Register" bitfld.word 0x08 3. " SOCB ,SOCB Force Bit" "No effect,Forced" bitfld.word 0x08 2. " SOCA ,SOCA Force Bit" "No effect,Forced" textline " " bitfld.word 0x08 0. " INT ,INT Force Bit" "No effect,Forced" tree.end width 0xB tree.end tree "ePWM 5" base ad:0xFCF79000 width 14. tree "Time-Base Submodule Registers" group.word 0x0A++0x01 line.word 0x00 "TBPRD,Time-Base Period Register" group.word 0x06++0x03 line.word 0x00 "TBPHS,Time-Base Phase Register" line.word 0x02 "TBCTR,Time-Base Counter Register" group.word 0x00++0x03 line.word 0x00 "TBCTL,Time-Base Control Register" bitfld.word 0x00 14.--15. " FREE/SOFT ,Emulation Mode Bits" "Stop after the next time-base counter INC or DEC,Stop when counter completes a whole cycle,Free run,Free run" textline " " bitfld.word 0x00 13. " PHSDIR ,Phase Direction Bit" "Count down,Count up" bitfld.word 0x00 10.--12. " CLKDIV ,Time-base Clock Prescale Bits" "/1,/2,/4,/8,/16,/32,/64,/128" textline " " bitfld.word 0x00 7.--9. " HSPCLKDIV ,High Speed Time-base Clock Prescale Bits" "/1,/2,/4,/8,/8,/10,/12,/14" bitfld.word 0x00 6. " SWFSYNC ,Software Forced Synchronization Pulse" "No effect,Generated" textline " " bitfld.word 0x00 4.--5. " SYNCOSEL ,Synchronization Output Select" "EPWMxSYNC,CTR = zero,CTR = CMPB,EPWMxSYNCO disable" bitfld.word 0x00 3. " PRDLD ,Active Period Register Load From Shadow Register Select" "Not selected,Selected" bitfld.word 0x00 2. " PHSEN ,Counter Register Load From Phase Register Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0.--1. " CTRMODE ,Counter Mode" "Up-count,Down-count,Up-down-count,Stop-freeze counter operation" line.word 0x02 "TBSTS,Time-Base Status Register" bitfld.word 0x02 2. " CTRMAX ,Time-Base Counter Max Latched Status Bit time-base counter maximum value" "Not reached,Reached" bitfld.word 0x02 1. " SYNCI ,Input Synchronization Latched Status Bit external synchronization event" "Not occurred,Occurred" textline " " bitfld.word 0x02 0. " CTRDIR ,Time-Base Counter Direction Status Bit" "Down,Up" tree.end width 8. tree "Counter-Compare Submodule Registers" group.word 0x12++0x03 line.word 0x00 "CMPA,Counter-Compare A Register" line.word 0x02 "CMPB,Counter-Compare B Register" group.word 0x0E++0x1 line.word 0x00 "CMPCTL,Counter-Compare Control Register" bitfld.word 0x00 9. " SHDWBFULL ,Counter-compare B CMPB Shadow Register Full Status Flag" "Not full,Full" bitfld.word 0x00 8. " SHDWAFULL ,Counter-compare A CMPA Shadow Register Full Status Flag" "Not full,Full" textline " " bitfld.word 0x00 6. " SHDWBMODE ,Counter-compare B CMPB Register Operating Mode" "Shadow,Immediate" bitfld.word 0x00 4. " SHDWAMODE ,Counter-compare A CMPA Register Operating Mode" "Shadow,Immediate" textline " " bitfld.word 0x00 2.--3. " LOADBMODE ,Active Counter-Compare B CMPB Load From Shadow Select Mode" "CTR = Zero,CTR = PRD,CTR = Zero or CTR = PRD,Freeze" bitfld.word 0x00 0.--1. " LOADAMODE ,Active Counter-Compare A CMPA Load From Shadow Select Mode" "CTR = Zero,CTR = PRD,CTR = Zero or CTR = PRD,Freeze" tree.end width 9. tree "Action-Qualifier Submodule Registers" group.word 0x16++0x07 line.word 0x00 "AQCTLA,Action-Qualifier Output A Control Register" bitfld.word 0x00 10.--11. " CBD ,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "Disabled,Cleared,Set,Toggled" bitfld.word 0x00 8.--9. " CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,Cleared,Set,Toggled" textline " " bitfld.word 0x00 6.--7. " CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,Cleared,Set,Toggled" bitfld.word 0x00 4.--5. " CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,Cleared,Set,Toggled" textline " " bitfld.word 0x00 2.--3. " PRD ,Action when the counter equals the period" "Disabled,Cleared,Set,Toggled" bitfld.word 0x00 0.--1. " ZRO ,Action when counter equals zero" "Disabled,Cleared,Set,Toggled" line.word 0x02 "AQCTLB,Action-Qualifier Output B Control Register" bitfld.word 0x02 10.--11. " CBD ,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "Disabled,Cleared,Set,Toggled" bitfld.word 0x02 8.--9. " CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,Cleared,Set,Toggled" textline " " bitfld.word 0x02 6.--7. " CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,Cleared,Set,Toggled" bitfld.word 0x02 4.--5. " CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,Cleared,Set,Toggled" textline " " bitfld.word 0x02 2.--3. " PRD ,Action when the counter equals the period" "Disabled,Cleared,Set,Toggled" bitfld.word 0x02 0.--1. " ZRO ,Action when counter equals zero" "Disabled,Cleared,Set,Toggled" line.word 0x04 "AQSFRC,Action-Qualifier Software Force Register" bitfld.word 0x04 6.--7. " RLDCSF ,AQCSFRC Active Register Reload From Shadow Options" "Zero,Period,Zero or Period,Immediately" bitfld.word 0x04 5. " OTSFB ,One-Time Software Forced Event on Output B" "No effect,Forced" textline " " bitfld.word 0x04 3.--4. " ACTSFB ,Action when One-Time Software Force B Is invoked" "Disabled,Cleared,Set,Toggled" bitfld.word 0x04 2. " OTSFA ,One-Time Software Forced Event on Output A" "No effect,Forced" textline " " bitfld.word 0x04 0.--1. " ACTSFA ,Action When One-Time Software Force A Is Invoked" "Disabled,Cleared,Set,Toggled" line.word 0x06 "AQCSFRC,Action-Qualifier Continuous Software Force Register" bitfld.word 0x06 2.--3. " CSFB ,Continuous Software Force on Output B" "Forced disabled,Continued low,Continued high,Soft forced disabled" bitfld.word 0x06 0.--1. " CSFA ,Continuous Software Force on Output A" "Forced disabled,Continued low,Continued high,Soft forced disabled" tree.end width 7. tree "Dead-Band Submodule Registers" group.word 0x1E++0x05 line.word 0x00 "DBCTL,Dead-Band Generator Control Register" bitfld.word 0x00 15. " HALFCYCLE ,Half Cycle Clocking Enable Bit" "Disabled,Enabled" textline " " bitfld.word 0x00 4.--5. " IN_MODE ,Dead Band Input Mode Control" "EPWMxA Faling/rising,EPWMxB rising / EPWMxA falling,EPWMxA rising / EPWMxB falling,EPWMxB both rising & falling" textline " " bitfld.word 0x00 2.--3. " POLSEL ,Polarity Select Control" "AH,ALC,AHC,AL" textline " " bitfld.word 0x00 0.--1. " OUT_MODE ,Dead-band Output Mode Control" "Dead-band generation bypassed,Disabled rising-edge delay,Rising-edge delayed signal on EPWMxA,Dead-band fully enabled" line.word 0x02 "DBRED,Dead-Band Generator Rising Edge Delay Register" hexmask.word 0x02 0.--9. 1. " DEL ,Rising Edge Delay Count" line.word 0x04 "DBFED,Dead-Band Generator Falling Edge Delay Register" hexmask.word 0x04 0.--9. 1. " DEL ,Falling Edge Delay Count" tree.end width 0x7 tree "PWM-Chopper Submodule Control Register" group.word 0x3C++0x01 line.word 0x00 "PCCTL,PWM-Chopper Control Register" bitfld.word 0x00 8.--10. " CHPDUTY ,Chopping Clock Duty Cycle" "1/8 (12.5%),2/8 (25.0%),3/8 (37.5%),4/8 (50.0%),5/8 (62.5%),6/8 (75.0%),7/8 (87.5%),?..." textline " " bitfld.word 0x00 5.--7. " CHPFREQ ,Chopping Clock Frequency" "/1 (no prescale = 12.5 MHz at 100 MHz VCLK4),/2 (6.25 MHz at 100 MHz VCLK4),/3 (4.16 MHz at 100 MHz VCLK4),/4 (3.12 MHz at 100 MHz VCLK4),/5 (2.50 MHz at 100 MHz VCLK4),/6 (2.08 MHz at 100 MHz VCLK4),/7 (1.78 MHz at 100 MHz VCLK4),/8 (1.56 MHz at 100 MHz VCLK4)" textline " " bitfld.word 0x00 1.--4. " OSHTWTH ,One-Shot Pulse Width" "1 x VCLK4 / 8 wide ( = 80 nS at 100 MHz VCLK4),2 x VCLK4 / 8 wide ( = 160 nS at 100 MHz VCLK4),3 x VCLK4 / 8 wide ( = 240 nS at 100 MHz VCLK4),4 x VCLK4 / 8 wide ( = 320 nS at 100 MHz VCLK4),5 x VCLK4 / 8 wide ( = 400 nS at 100 MHz VCLK4),6 x VCLK4 / 8 wide ( = 480 nS at 100 MHz VCLK4),7 x VCLK4 / 8 wide ( = 560 nS at 100 MHz VCLK4),8 x VCLK4 / 8 wide ( = 640 nS at 100 MHz VCLK4),9 x VCLK4 / 8 wide ( = 720 nS at 100 MHz VCLK4),10 x VCLK4 / 8 wide ( = 800 nS at 100 MHz VCLK4),11 x VCLK4 / 8 wide ( = 880 nS at 100 MHz VCLK4),12 x VCLK4 / 8 wide ( = 960 nS at 100 MHz VCLK4),13 x VCLK4 / 8 wide ( = 1040 nS at 100 MHz VCLK4),14 x VCLK4 / 8 wide ( = 1120 nS at 100 MHz VCLK4),15 x VCLK4 / 8 wide ( = 1200 nS at 100 MHz VCLK4),16 x VCLK4 / 8 wide ( = 1280 nS at 100 MHz VCLK4)" textline " " bitfld.word 0x00 0. " CHPEN ,PWM-chopping Enable" "Disabled,Enabled" tree.end width 9. tree "Trip-Zone Select Register" group.word 0x24++0x01 line.word 0x00 "TZSEL,Trip-Zone Submodule Control and Status Registers" bitfld.word 0x00 15. " DCBEVT1 ,Digital Compare Output B Event 1 Select" "Disabled,Enabled" bitfld.word 0x00 14. " DCAEVT1 ,Digital Compare Output A Event 1 Select" "Disabled,Enabled" bitfld.word 0x00 13. " OSHT6 ,Trip-zone 6 TZ6 Select" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " OSHT5 ,Trip-zone 5 TZ5 Select" "Disabled,Enabled" bitfld.word 0x00 11. " OSHT4 ,Trip-zone 4 TZ4 Select" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OSHT3 ,Trip-zone 3 TZ3 Select" "Disabled,Enabled" bitfld.word 0x00 9. " OSHT2 ,Trip-zone 2 TZ2 Select" "Disabled,Enabled" bitfld.word 0x00 8. " OSHT1 ,Trip-zone 1 TZ) Select" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " DCBEVT2 ,Digital Compare Output B Event 2 Select" "Disabled,Enabled" bitfld.word 0x00 6. " DCAEVT2 ,Digital Compare Output A Event 2 Select" "Disabled,Enabled" bitfld.word 0x00 5. " CBC6 ,Trip-zone 6 TZ6 Select" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " CBC5 ,Trip-zone 5 TZ5 Select" "Disabled,Enabled" bitfld.word 0x00 3. " CBC4 ,Trip-zone 4 TZ4 Select" "Disabled,Enabled" bitfld.word 0x00 2. " CBC3 ,Trip-zone 3 TZ3 Select" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " CBC2 ,Trip-zone 2 TZ2 Select" "Disabled,Enabled" bitfld.word 0x00 0. " CBC1 ,Trip-zone 1 TZ1 Select" "Disabled,Enabled" group.word 0x28++0x01 line.word 0x00 "TZCTL,Trip-Zone Control Register" bitfld.word 0x00 10.--11. " DCBEVT2 ,Digital Compare Output B Event 2 Action On EPWMxB" "High-impedance,High state,Low state,Disabled" bitfld.word 0x00 8.--9. " DCBEVT1 ,Digital Compare Output B Event 1 Action On EPWMxB" "High-impedance,Forced high state,Forced low state,Disabled" textline " " bitfld.word 0x00 6.--7. " DCAEVT2 ,Digital Compare Output A Event 2 Action On EPWMxA" "High-impedance,Forced high state,Forced low state,Disabled" bitfld.word 0x00 4.--5. " DCAEVT1 ,Digital Compare Output A Event 1 Action On EPWMxA" "High-impedance,Forced high state,Forced low state,Disabled" textline " " bitfld.word 0x00 2.--3. " TZB ,When a trip event occurs the following action is taken on output EPWMxB" "High-impedance,Forced high state,Forced low state,Disabled" bitfld.word 0x00 0.--1. " TZA ,When a trip event occurs the following action is taken on output EPWMxA" "High-impedance,Forced high state,Forced low state,Disabled" group.word 0x2C++0x01 line.word 0x00 "TZFLG,Trip-Zone Flag Register Field Descriptions" setclrfld.word 0x00 6. -0x02 6. 0x02 6. " DCBEVT2_set/clr ,Digital Comparator Output B Event 2 Interrupt" "Not occurred,Occurred" setclrfld.word 0x00 5. -0x02 5. 0x02 5. " DCBEVT1_set/clr ,Digital Comparator Output B Event 1 Interrupt" "Not occurred,Occurred" textline " " setclrfld.word 0x00 4. -0x02 4. 0x02 4. " DCAEVT2_set/clr ,Digital Comparator Output A Event 2 Interrupt" "Not occurred,Occurred" setclrfld.word 0x00 3. -0x02 3. 0x02 3. " DCAEVT1_set/clr ,Digital Comparator Output A Event 1 Interrupt" "Not occurred,Occurred" textline " " setclrfld.word 0x00 2. -0x02 2. 0x02 2. " OST_set/clr ,Trip-zone One-Shot Interrupt" "Not occurred,Occurred" setclrfld.word 0x00 1. -0x02 1. 0x02 1. " CBC_set/clr ,Trip-zone Cycle-by-Cycle Interrupt" "Not occurred,Occurred" textline " " setclrfld.word 0x00 0. 0x00 0. 0x02 0. " INT_set/clr ,Latched Trip Interrupt Status Flag" "Not generated,Generated" group.word 0x30++0x01 line.word 0x00 "TZFRC,Trip-Zone Force Register" bitfld.word 0x00 6. " DCBEVT2 ,Force Flag for Digital Compare Output B Event 2" "No effect,Forced" bitfld.word 0x00 5. " DCBEVT1 ,Force Flag for Digital Compare Output B Event 1" "No effect,Forced" textline " " bitfld.word 0x00 4. " DCAEVT2 ,Force Flag for Digital Compare Output A Event 2" "No effect,Forced" bitfld.word 0x00 3. " DCAEVT1 ,Force Flag for Digital Compare Output A Event 1" "No effect,Forced" textline " " bitfld.word 0x00 2. " OST ,Force a One-Shot Trip Event via Software" "No effect,Forced" bitfld.word 0x00 1. " CBC ,Force a Cycle-by-Cycle Trip Event via Software" "No effect,Forced" group.word 0x26++0x01 line.word 0x00 "TZDCSEL,Trip Zone Digital Compare Event Select Register" bitfld.word 0x00 9.--11. " DCBEVT2 ,Digital Compare Output B Event 2 Selection" "Event disabled,DCBH = low,DCBH = high,DCBL = low,DCBL = high,DCBL = high - DCBH = low,?..." bitfld.word 0x00 6.--8. " DCBEVT1 ,Digital Compare Output B Event 1 Selection" "Event disabled,DCBH = low,DCBH = high,DCBL = low,DCBL = high,DCBL = high - DCBH = low,?..." textline " " bitfld.word 0x00 3.--5. " DCAEVT2 ,Digital Compare Output A Event 2 Selection" "Event disabled,DCAH = low,DCAH = high,DCAL = low,DCAL = high,DCAL = high - DCAH = low,?..." bitfld.word 0x00 0.--2. " DCAEVT1 ,Digital Compare Output A Event 1 Selection" "Event disabled,DCAH = low,DCAH = high,DCAL = low,DCAL = high,DCAL = high,?..." tree.end width 11. tree "Digital Compare Submodule Registers" group.word 0x60++0x09 line.word 0x00 "DCTRIPSEL,Digital Compare Trip Select" bitfld.word 0x00 12.--15. " DCBLCOMPSEL ,Digital Compare B Low Input Select" "TZ1 input,TZ2 input,TZ3 input,?..." bitfld.word 0x00 8.--11. " DCBHCOMPSEL ,Digital Compare B High Input Select" "TZ1 input,TZ2 input,TZ3 input,?..." textline " " bitfld.word 0x00 4.--7. " DCALCOMPSEL ,Digital Compare A Low Input Select" "TZ1 input,TZ2 input,TZ3 input,?..." bitfld.word 0x00 0.--3. " DCAHCOMPSEL ,Digital Compare A High Input Select" "TZ1 input,TZ2 input,TZ3 input,?..." line.word 0x02 "DCACTL,Digital Compare A Control Register" bitfld.word 0x02 9. " EVT2FRC_SYNCSEL ,DCAEVT2 Force Synchronization Signal Select" "Synchronous,Asynchronous" bitfld.word 0x02 8. " EVT2SRCSEL ,DCAEVT2 Source Signal Select" "DCAEVT2,DCEVTFILT" textline " " bitfld.word 0x02 3. " EVT1SYNCE ,DCAEVT1 SYNC Generation" "Disabled,Enabled" bitfld.word 0x02 2. " EVT1SOCE ,DCAEVT1 SOC Generation" "Disabled,Enabled" textline " " bitfld.word 0x02 1. " EVT1FRC_SYNCSEL ,DCAEVT1 Force Synchronization Signal Select" "Synchronous,Asynchronous" bitfld.word 0x02 0. " EVT1SRCSEL ,DCAEVT1 Source Signal Select" "DCAEVT,DCEVTFILT" line.word 0x04 "DCBCTL,Digital Compare B Control Register" bitfld.word 0x04 9. " EVT2FRC_SYNCSEL ,DCBEVT2 Force Synchronization Signal Select" "Synchronous,Asynchronous" bitfld.word 0x04 8. " EVT2SRCSEL ,DCBEVT2 Source Signal Select" "DCBEVT2,DCEVTFILT" textline " " bitfld.word 0x04 3. " EVT1SYNCE ,DCBEVT1 SYNC Generation" "Disabled,Enabled" bitfld.word 0x04 2. " EVT1SOCE ,DCBEVT1 SOC Generation" "Disabled,Enabled" textline " " bitfld.word 0x04 1. " EVT1FRC_SYNCSEL ,DCBEVT1 Force Synchronization Signal Select" "Synchronous,Asynchronous" bitfld.word 0x04 0. " EVT1SRCSEL ,DCBEVT1 Source Signal Select" "DCBEVT,DCEVTFILT" line.word 0x06 "DBFCTL,Digital Compare Filter Control Register" bitfld.word 0x06 4.--5. " PULSESEL ,Pulse Select For Blanking & Capture Alignment" "TB CNT Equal to period,TB CNT Equal to zero,?..." textline " " bitfld.word 0x06 3. " BLANKINV ,Blanking Window Inversion" "Not inverted,Inverted" bitfld.word 0x06 2. " BLANKE ,Blanking Window Enable/Disable" "Disabled,Enabled" textline " " bitfld.word 0x06 0.--1. " SRCSEL ,Filter Block Signal Source Select" "DCAEVT1,DCAEVT2,DCBEVT1,DCBEVT2" line.word 0x08 "DBCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x08 1. " SHDWMODE ,TBCTR Counter Capture Shadow Select Mode" "Shadow mode,Active Mode" bitfld.word 0x08 0. " CAPE ,TBCTR Counter Capture Enable/Disable" "Disabled,Enabled" width 14. rgroup.word 0x72++0x01 line.word 0x00 "DCCAP,Digital Compare Counter Capture Register" rgroup.word 0x6A++0x01 line.word 0x00 "DCFOFFSET,Digital Compare Filter Offset Register" group.word 0x6E++0x01 line.word 0x00 "DCFWINDOW,Digital Compare Filter Window Register" hexmask.word.byte 0x00 0.--7. 1. " WINDOW ,Blanking Window Width" rgroup.word 0x70++0x01 line.word 0x00 "DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word.byte 0x00 0.--7. 1. " WINDOWCNT ,Digital Compare Filter Window Counter Register" tree.end width 7. tree "Event-Trigger Submodule Registers" group.word 0x32++0x09 line.word 0x00 "ETSEL,Event-Trigger Selection Register" bitfld.word 0x00 15. " SOCBEN ,Enable the ADC Start of Conversion B EPWMxSOCB Pulse" "Disabled,Enabled" bitfld.word 0x00 12.--14. " SOCBSEL ,EPWMxSOCB Selection Options" "DCBEVT1_soc,TB CNT equal to zero,TB CNT equal to period,TB CNT equal to zero or period,TB CNT equal to CMPA - Timer INC,TB CNT equal to CMPA - Timer DEC,TB CNT equal to CMPB - Timer INC,TB CNT equal to CMPB - Timer DEC" textline " " bitfld.word 0x00 11. " SOCAEN ,Enable the ADC Start of Conversion A EPWMxSOCA Pulse" "Disabled,Enabled" bitfld.word 0x00 8.--10. " SOCASEL ,EPWMxSOCA Selection Options" "DCAEVT1_soc,TB CNT equal to zero,TB CNT equal to period,TB CNT equal to zero or period,TB CNT equal to CMPA - Timer INC,TB CNT equal to CMPA - Timer DEC,TB CNT equal to CMPB - Timer INC,TB CNT equal to CMPB - Timer DEC" textline " " bitfld.word 0x00 3. " INTEN ,Enable ePWM Interrupt EPWMx_INT Generation" "Disabled,Enabled" bitfld.word 0x00 0.--2. " INTSEL ,ePWM Interrupt EPWMx_INT Selection Options" "Reserved,TB CNT equal to zero,TB CNT equal to period,TB CNT equal to zero or period,TB CNT equal to CMPA - Timer INC,TB CNT equal to CMPA - Timer DEC,TB CNT equal to CMPB - Timer INC,TB CNT equal to CMPB - Timer DEC" line.word 0x02 "ETPS,Event-Trigger Prescale Register" bitfld.word 0x02 14.--15. " SOCBCNT ,ePWM ADC Start-of-Conversion B Event EPWMxSOCB Counter Register" "No events,1 event,2 events,3 events" bitfld.word 0x02 12.--13. " SOCBPRD ,ePWM ADC Start-of-Conversion B Event EPWMxSOCB Period Select" "Disabled,1st event,2nd event,3th event" textline " " bitfld.word 0x02 10.--11. " SOCACNT ,ePWM ADC Start-of-Conversion A Event EPWMxSOCA Counter Register" "No events,1 event,2 events,3 events" bitfld.word 0x02 8.--9. " SOCAPRD ,ePWM ADC Start-of-Conversion A Event EPWMxSOCA Period Select" "Disabled,1st event,2nd event,3th event" textline " " bitfld.word 0x02 2.--3. " INTCNT ,ePWM Interrupt Event EPWMx_INT Counter Register" "No events,1 event,2 events,3 events" bitfld.word 0x02 0.--1. " INTPRD ,ePWM Interrupt EPWMx_INT Period Select" "Disabled,1st event,2nd event,3th event" line.word 0x04 "ETFLG,Event-Trigger Flag Register" bitfld.word 0x04 3. " SOCB ,Latched ePWM ADC Start-of-Conversion B EPWMxSOCB Status Flag" "Not occurred,Occurred" bitfld.word 0x04 2. " SOCA ,Latched ePWM ADC Start-of-Conversion A EPWMxSOCA Status Flag" "Not occurred,Occurred" textline " " bitfld.word 0x04 0. " INT ,Latched ePWM Interrupt EPWMx_INT Status Flag" "Not occurred,Occurred" line.word 0x06 "ETCLR,Event-Trigger Clear Register" bitfld.word 0x06 3. " SOCB ,ePWM ADC Start-of-Conversion B EPWMxSOCB Flag Clear Bit" "No effect,Cleared" bitfld.word 0x06 2. " SOCA ,ePWM ADC Start-of-Conversion A EPWMxSOCB Flag Clear Bit" "No effect,Cleared" textline " " bitfld.word 0x06 0. " INT ,ePWM Interrupt EPWMx_INT Flag Clear Bit" "No effect,Cleared" line.word 0x08 "ETFRC,Event-Trigger Force Register" bitfld.word 0x08 3. " SOCB ,SOCB Force Bit" "No effect,Forced" bitfld.word 0x08 2. " SOCA ,SOCA Force Bit" "No effect,Forced" textline " " bitfld.word 0x08 0. " INT ,INT Force Bit" "No effect,Forced" tree.end width 0xB tree.end tree "ePWM 6" base ad:0xFCF79100 width 14. tree "Time-Base Submodule Registers" group.word 0x0A++0x01 line.word 0x00 "TBPRD,Time-Base Period Register" group.word 0x06++0x03 line.word 0x00 "TBPHS,Time-Base Phase Register" line.word 0x02 "TBCTR,Time-Base Counter Register" group.word 0x00++0x03 line.word 0x00 "TBCTL,Time-Base Control Register" bitfld.word 0x00 14.--15. " FREE/SOFT ,Emulation Mode Bits" "Stop after the next time-base counter INC or DEC,Stop when counter completes a whole cycle,Free run,Free run" textline " " bitfld.word 0x00 13. " PHSDIR ,Phase Direction Bit" "Count down,Count up" bitfld.word 0x00 10.--12. " CLKDIV ,Time-base Clock Prescale Bits" "/1,/2,/4,/8,/16,/32,/64,/128" textline " " bitfld.word 0x00 7.--9. " HSPCLKDIV ,High Speed Time-base Clock Prescale Bits" "/1,/2,/4,/8,/8,/10,/12,/14" bitfld.word 0x00 6. " SWFSYNC ,Software Forced Synchronization Pulse" "No effect,Generated" textline " " bitfld.word 0x00 4.--5. " SYNCOSEL ,Synchronization Output Select" "EPWMxSYNC,CTR = zero,CTR = CMPB,EPWMxSYNCO disable" bitfld.word 0x00 3. " PRDLD ,Active Period Register Load From Shadow Register Select" "Not selected,Selected" bitfld.word 0x00 2. " PHSEN ,Counter Register Load From Phase Register Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0.--1. " CTRMODE ,Counter Mode" "Up-count,Down-count,Up-down-count,Stop-freeze counter operation" line.word 0x02 "TBSTS,Time-Base Status Register" bitfld.word 0x02 2. " CTRMAX ,Time-Base Counter Max Latched Status Bit time-base counter maximum value" "Not reached,Reached" bitfld.word 0x02 1. " SYNCI ,Input Synchronization Latched Status Bit external synchronization event" "Not occurred,Occurred" textline " " bitfld.word 0x02 0. " CTRDIR ,Time-Base Counter Direction Status Bit" "Down,Up" tree.end width 8. tree "Counter-Compare Submodule Registers" group.word 0x12++0x03 line.word 0x00 "CMPA,Counter-Compare A Register" line.word 0x02 "CMPB,Counter-Compare B Register" group.word 0x0E++0x1 line.word 0x00 "CMPCTL,Counter-Compare Control Register" bitfld.word 0x00 9. " SHDWBFULL ,Counter-compare B CMPB Shadow Register Full Status Flag" "Not full,Full" bitfld.word 0x00 8. " SHDWAFULL ,Counter-compare A CMPA Shadow Register Full Status Flag" "Not full,Full" textline " " bitfld.word 0x00 6. " SHDWBMODE ,Counter-compare B CMPB Register Operating Mode" "Shadow,Immediate" bitfld.word 0x00 4. " SHDWAMODE ,Counter-compare A CMPA Register Operating Mode" "Shadow,Immediate" textline " " bitfld.word 0x00 2.--3. " LOADBMODE ,Active Counter-Compare B CMPB Load From Shadow Select Mode" "CTR = Zero,CTR = PRD,CTR = Zero or CTR = PRD,Freeze" bitfld.word 0x00 0.--1. " LOADAMODE ,Active Counter-Compare A CMPA Load From Shadow Select Mode" "CTR = Zero,CTR = PRD,CTR = Zero or CTR = PRD,Freeze" tree.end width 9. tree "Action-Qualifier Submodule Registers" group.word 0x16++0x07 line.word 0x00 "AQCTLA,Action-Qualifier Output A Control Register" bitfld.word 0x00 10.--11. " CBD ,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "Disabled,Cleared,Set,Toggled" bitfld.word 0x00 8.--9. " CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,Cleared,Set,Toggled" textline " " bitfld.word 0x00 6.--7. " CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,Cleared,Set,Toggled" bitfld.word 0x00 4.--5. " CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,Cleared,Set,Toggled" textline " " bitfld.word 0x00 2.--3. " PRD ,Action when the counter equals the period" "Disabled,Cleared,Set,Toggled" bitfld.word 0x00 0.--1. " ZRO ,Action when counter equals zero" "Disabled,Cleared,Set,Toggled" line.word 0x02 "AQCTLB,Action-Qualifier Output B Control Register" bitfld.word 0x02 10.--11. " CBD ,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "Disabled,Cleared,Set,Toggled" bitfld.word 0x02 8.--9. " CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,Cleared,Set,Toggled" textline " " bitfld.word 0x02 6.--7. " CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,Cleared,Set,Toggled" bitfld.word 0x02 4.--5. " CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,Cleared,Set,Toggled" textline " " bitfld.word 0x02 2.--3. " PRD ,Action when the counter equals the period" "Disabled,Cleared,Set,Toggled" bitfld.word 0x02 0.--1. " ZRO ,Action when counter equals zero" "Disabled,Cleared,Set,Toggled" line.word 0x04 "AQSFRC,Action-Qualifier Software Force Register" bitfld.word 0x04 6.--7. " RLDCSF ,AQCSFRC Active Register Reload From Shadow Options" "Zero,Period,Zero or Period,Immediately" bitfld.word 0x04 5. " OTSFB ,One-Time Software Forced Event on Output B" "No effect,Forced" textline " " bitfld.word 0x04 3.--4. " ACTSFB ,Action when One-Time Software Force B Is invoked" "Disabled,Cleared,Set,Toggled" bitfld.word 0x04 2. " OTSFA ,One-Time Software Forced Event on Output A" "No effect,Forced" textline " " bitfld.word 0x04 0.--1. " ACTSFA ,Action When One-Time Software Force A Is Invoked" "Disabled,Cleared,Set,Toggled" line.word 0x06 "AQCSFRC,Action-Qualifier Continuous Software Force Register" bitfld.word 0x06 2.--3. " CSFB ,Continuous Software Force on Output B" "Forced disabled,Continued low,Continued high,Soft forced disabled" bitfld.word 0x06 0.--1. " CSFA ,Continuous Software Force on Output A" "Forced disabled,Continued low,Continued high,Soft forced disabled" tree.end width 7. tree "Dead-Band Submodule Registers" group.word 0x1E++0x05 line.word 0x00 "DBCTL,Dead-Band Generator Control Register" bitfld.word 0x00 15. " HALFCYCLE ,Half Cycle Clocking Enable Bit" "Disabled,Enabled" textline " " bitfld.word 0x00 4.--5. " IN_MODE ,Dead Band Input Mode Control" "EPWMxA Faling/rising,EPWMxB rising / EPWMxA falling,EPWMxA rising / EPWMxB falling,EPWMxB both rising & falling" textline " " bitfld.word 0x00 2.--3. " POLSEL ,Polarity Select Control" "AH,ALC,AHC,AL" textline " " bitfld.word 0x00 0.--1. " OUT_MODE ,Dead-band Output Mode Control" "Dead-band generation bypassed,Disabled rising-edge delay,Rising-edge delayed signal on EPWMxA,Dead-band fully enabled" line.word 0x02 "DBRED,Dead-Band Generator Rising Edge Delay Register" hexmask.word 0x02 0.--9. 1. " DEL ,Rising Edge Delay Count" line.word 0x04 "DBFED,Dead-Band Generator Falling Edge Delay Register" hexmask.word 0x04 0.--9. 1. " DEL ,Falling Edge Delay Count" tree.end width 0x7 tree "PWM-Chopper Submodule Control Register" group.word 0x3C++0x01 line.word 0x00 "PCCTL,PWM-Chopper Control Register" bitfld.word 0x00 8.--10. " CHPDUTY ,Chopping Clock Duty Cycle" "1/8 (12.5%),2/8 (25.0%),3/8 (37.5%),4/8 (50.0%),5/8 (62.5%),6/8 (75.0%),7/8 (87.5%),?..." textline " " bitfld.word 0x00 5.--7. " CHPFREQ ,Chopping Clock Frequency" "/1 (no prescale = 12.5 MHz at 100 MHz VCLK4),/2 (6.25 MHz at 100 MHz VCLK4),/3 (4.16 MHz at 100 MHz VCLK4),/4 (3.12 MHz at 100 MHz VCLK4),/5 (2.50 MHz at 100 MHz VCLK4),/6 (2.08 MHz at 100 MHz VCLK4),/7 (1.78 MHz at 100 MHz VCLK4),/8 (1.56 MHz at 100 MHz VCLK4)" textline " " bitfld.word 0x00 1.--4. " OSHTWTH ,One-Shot Pulse Width" "1 x VCLK4 / 8 wide ( = 80 nS at 100 MHz VCLK4),2 x VCLK4 / 8 wide ( = 160 nS at 100 MHz VCLK4),3 x VCLK4 / 8 wide ( = 240 nS at 100 MHz VCLK4),4 x VCLK4 / 8 wide ( = 320 nS at 100 MHz VCLK4),5 x VCLK4 / 8 wide ( = 400 nS at 100 MHz VCLK4),6 x VCLK4 / 8 wide ( = 480 nS at 100 MHz VCLK4),7 x VCLK4 / 8 wide ( = 560 nS at 100 MHz VCLK4),8 x VCLK4 / 8 wide ( = 640 nS at 100 MHz VCLK4),9 x VCLK4 / 8 wide ( = 720 nS at 100 MHz VCLK4),10 x VCLK4 / 8 wide ( = 800 nS at 100 MHz VCLK4),11 x VCLK4 / 8 wide ( = 880 nS at 100 MHz VCLK4),12 x VCLK4 / 8 wide ( = 960 nS at 100 MHz VCLK4),13 x VCLK4 / 8 wide ( = 1040 nS at 100 MHz VCLK4),14 x VCLK4 / 8 wide ( = 1120 nS at 100 MHz VCLK4),15 x VCLK4 / 8 wide ( = 1200 nS at 100 MHz VCLK4),16 x VCLK4 / 8 wide ( = 1280 nS at 100 MHz VCLK4)" textline " " bitfld.word 0x00 0. " CHPEN ,PWM-chopping Enable" "Disabled,Enabled" tree.end width 9. tree "Trip-Zone Select Register" group.word 0x24++0x01 line.word 0x00 "TZSEL,Trip-Zone Submodule Control and Status Registers" bitfld.word 0x00 15. " DCBEVT1 ,Digital Compare Output B Event 1 Select" "Disabled,Enabled" bitfld.word 0x00 14. " DCAEVT1 ,Digital Compare Output A Event 1 Select" "Disabled,Enabled" bitfld.word 0x00 13. " OSHT6 ,Trip-zone 6 TZ6 Select" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " OSHT5 ,Trip-zone 5 TZ5 Select" "Disabled,Enabled" bitfld.word 0x00 11. " OSHT4 ,Trip-zone 4 TZ4 Select" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OSHT3 ,Trip-zone 3 TZ3 Select" "Disabled,Enabled" bitfld.word 0x00 9. " OSHT2 ,Trip-zone 2 TZ2 Select" "Disabled,Enabled" bitfld.word 0x00 8. " OSHT1 ,Trip-zone 1 TZ) Select" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " DCBEVT2 ,Digital Compare Output B Event 2 Select" "Disabled,Enabled" bitfld.word 0x00 6. " DCAEVT2 ,Digital Compare Output A Event 2 Select" "Disabled,Enabled" bitfld.word 0x00 5. " CBC6 ,Trip-zone 6 TZ6 Select" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " CBC5 ,Trip-zone 5 TZ5 Select" "Disabled,Enabled" bitfld.word 0x00 3. " CBC4 ,Trip-zone 4 TZ4 Select" "Disabled,Enabled" bitfld.word 0x00 2. " CBC3 ,Trip-zone 3 TZ3 Select" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " CBC2 ,Trip-zone 2 TZ2 Select" "Disabled,Enabled" bitfld.word 0x00 0. " CBC1 ,Trip-zone 1 TZ1 Select" "Disabled,Enabled" group.word 0x28++0x01 line.word 0x00 "TZCTL,Trip-Zone Control Register" bitfld.word 0x00 10.--11. " DCBEVT2 ,Digital Compare Output B Event 2 Action On EPWMxB" "High-impedance,High state,Low state,Disabled" bitfld.word 0x00 8.--9. " DCBEVT1 ,Digital Compare Output B Event 1 Action On EPWMxB" "High-impedance,Forced high state,Forced low state,Disabled" textline " " bitfld.word 0x00 6.--7. " DCAEVT2 ,Digital Compare Output A Event 2 Action On EPWMxA" "High-impedance,Forced high state,Forced low state,Disabled" bitfld.word 0x00 4.--5. " DCAEVT1 ,Digital Compare Output A Event 1 Action On EPWMxA" "High-impedance,Forced high state,Forced low state,Disabled" textline " " bitfld.word 0x00 2.--3. " TZB ,When a trip event occurs the following action is taken on output EPWMxB" "High-impedance,Forced high state,Forced low state,Disabled" bitfld.word 0x00 0.--1. " TZA ,When a trip event occurs the following action is taken on output EPWMxA" "High-impedance,Forced high state,Forced low state,Disabled" group.word 0x2C++0x01 line.word 0x00 "TZFLG,Trip-Zone Flag Register Field Descriptions" setclrfld.word 0x00 6. -0x02 6. 0x02 6. " DCBEVT2_set/clr ,Digital Comparator Output B Event 2 Interrupt" "Not occurred,Occurred" setclrfld.word 0x00 5. -0x02 5. 0x02 5. " DCBEVT1_set/clr ,Digital Comparator Output B Event 1 Interrupt" "Not occurred,Occurred" textline " " setclrfld.word 0x00 4. -0x02 4. 0x02 4. " DCAEVT2_set/clr ,Digital Comparator Output A Event 2 Interrupt" "Not occurred,Occurred" setclrfld.word 0x00 3. -0x02 3. 0x02 3. " DCAEVT1_set/clr ,Digital Comparator Output A Event 1 Interrupt" "Not occurred,Occurred" textline " " setclrfld.word 0x00 2. -0x02 2. 0x02 2. " OST_set/clr ,Trip-zone One-Shot Interrupt" "Not occurred,Occurred" setclrfld.word 0x00 1. -0x02 1. 0x02 1. " CBC_set/clr ,Trip-zone Cycle-by-Cycle Interrupt" "Not occurred,Occurred" textline " " setclrfld.word 0x00 0. 0x00 0. 0x02 0. " INT_set/clr ,Latched Trip Interrupt Status Flag" "Not generated,Generated" group.word 0x30++0x01 line.word 0x00 "TZFRC,Trip-Zone Force Register" bitfld.word 0x00 6. " DCBEVT2 ,Force Flag for Digital Compare Output B Event 2" "No effect,Forced" bitfld.word 0x00 5. " DCBEVT1 ,Force Flag for Digital Compare Output B Event 1" "No effect,Forced" textline " " bitfld.word 0x00 4. " DCAEVT2 ,Force Flag for Digital Compare Output A Event 2" "No effect,Forced" bitfld.word 0x00 3. " DCAEVT1 ,Force Flag for Digital Compare Output A Event 1" "No effect,Forced" textline " " bitfld.word 0x00 2. " OST ,Force a One-Shot Trip Event via Software" "No effect,Forced" bitfld.word 0x00 1. " CBC ,Force a Cycle-by-Cycle Trip Event via Software" "No effect,Forced" group.word 0x26++0x01 line.word 0x00 "TZDCSEL,Trip Zone Digital Compare Event Select Register" bitfld.word 0x00 9.--11. " DCBEVT2 ,Digital Compare Output B Event 2 Selection" "Event disabled,DCBH = low,DCBH = high,DCBL = low,DCBL = high,DCBL = high - DCBH = low,?..." bitfld.word 0x00 6.--8. " DCBEVT1 ,Digital Compare Output B Event 1 Selection" "Event disabled,DCBH = low,DCBH = high,DCBL = low,DCBL = high,DCBL = high - DCBH = low,?..." textline " " bitfld.word 0x00 3.--5. " DCAEVT2 ,Digital Compare Output A Event 2 Selection" "Event disabled,DCAH = low,DCAH = high,DCAL = low,DCAL = high,DCAL = high - DCAH = low,?..." bitfld.word 0x00 0.--2. " DCAEVT1 ,Digital Compare Output A Event 1 Selection" "Event disabled,DCAH = low,DCAH = high,DCAL = low,DCAL = high,DCAL = high,?..." tree.end width 11. tree "Digital Compare Submodule Registers" group.word 0x60++0x09 line.word 0x00 "DCTRIPSEL,Digital Compare Trip Select" bitfld.word 0x00 12.--15. " DCBLCOMPSEL ,Digital Compare B Low Input Select" "TZ1 input,TZ2 input,TZ3 input,?..." bitfld.word 0x00 8.--11. " DCBHCOMPSEL ,Digital Compare B High Input Select" "TZ1 input,TZ2 input,TZ3 input,?..." textline " " bitfld.word 0x00 4.--7. " DCALCOMPSEL ,Digital Compare A Low Input Select" "TZ1 input,TZ2 input,TZ3 input,?..." bitfld.word 0x00 0.--3. " DCAHCOMPSEL ,Digital Compare A High Input Select" "TZ1 input,TZ2 input,TZ3 input,?..." line.word 0x02 "DCACTL,Digital Compare A Control Register" bitfld.word 0x02 9. " EVT2FRC_SYNCSEL ,DCAEVT2 Force Synchronization Signal Select" "Synchronous,Asynchronous" bitfld.word 0x02 8. " EVT2SRCSEL ,DCAEVT2 Source Signal Select" "DCAEVT2,DCEVTFILT" textline " " bitfld.word 0x02 3. " EVT1SYNCE ,DCAEVT1 SYNC Generation" "Disabled,Enabled" bitfld.word 0x02 2. " EVT1SOCE ,DCAEVT1 SOC Generation" "Disabled,Enabled" textline " " bitfld.word 0x02 1. " EVT1FRC_SYNCSEL ,DCAEVT1 Force Synchronization Signal Select" "Synchronous,Asynchronous" bitfld.word 0x02 0. " EVT1SRCSEL ,DCAEVT1 Source Signal Select" "DCAEVT,DCEVTFILT" line.word 0x04 "DCBCTL,Digital Compare B Control Register" bitfld.word 0x04 9. " EVT2FRC_SYNCSEL ,DCBEVT2 Force Synchronization Signal Select" "Synchronous,Asynchronous" bitfld.word 0x04 8. " EVT2SRCSEL ,DCBEVT2 Source Signal Select" "DCBEVT2,DCEVTFILT" textline " " bitfld.word 0x04 3. " EVT1SYNCE ,DCBEVT1 SYNC Generation" "Disabled,Enabled" bitfld.word 0x04 2. " EVT1SOCE ,DCBEVT1 SOC Generation" "Disabled,Enabled" textline " " bitfld.word 0x04 1. " EVT1FRC_SYNCSEL ,DCBEVT1 Force Synchronization Signal Select" "Synchronous,Asynchronous" bitfld.word 0x04 0. " EVT1SRCSEL ,DCBEVT1 Source Signal Select" "DCBEVT,DCEVTFILT" line.word 0x06 "DBFCTL,Digital Compare Filter Control Register" bitfld.word 0x06 4.--5. " PULSESEL ,Pulse Select For Blanking & Capture Alignment" "TB CNT Equal to period,TB CNT Equal to zero,?..." textline " " bitfld.word 0x06 3. " BLANKINV ,Blanking Window Inversion" "Not inverted,Inverted" bitfld.word 0x06 2. " BLANKE ,Blanking Window Enable/Disable" "Disabled,Enabled" textline " " bitfld.word 0x06 0.--1. " SRCSEL ,Filter Block Signal Source Select" "DCAEVT1,DCAEVT2,DCBEVT1,DCBEVT2" line.word 0x08 "DBCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x08 1. " SHDWMODE ,TBCTR Counter Capture Shadow Select Mode" "Shadow mode,Active Mode" bitfld.word 0x08 0. " CAPE ,TBCTR Counter Capture Enable/Disable" "Disabled,Enabled" width 14. rgroup.word 0x72++0x01 line.word 0x00 "DCCAP,Digital Compare Counter Capture Register" rgroup.word 0x6A++0x01 line.word 0x00 "DCFOFFSET,Digital Compare Filter Offset Register" group.word 0x6E++0x01 line.word 0x00 "DCFWINDOW,Digital Compare Filter Window Register" hexmask.word.byte 0x00 0.--7. 1. " WINDOW ,Blanking Window Width" rgroup.word 0x70++0x01 line.word 0x00 "DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word.byte 0x00 0.--7. 1. " WINDOWCNT ,Digital Compare Filter Window Counter Register" tree.end width 7. tree "Event-Trigger Submodule Registers" group.word 0x32++0x09 line.word 0x00 "ETSEL,Event-Trigger Selection Register" bitfld.word 0x00 15. " SOCBEN ,Enable the ADC Start of Conversion B EPWMxSOCB Pulse" "Disabled,Enabled" bitfld.word 0x00 12.--14. " SOCBSEL ,EPWMxSOCB Selection Options" "DCBEVT1_soc,TB CNT equal to zero,TB CNT equal to period,TB CNT equal to zero or period,TB CNT equal to CMPA - Timer INC,TB CNT equal to CMPA - Timer DEC,TB CNT equal to CMPB - Timer INC,TB CNT equal to CMPB - Timer DEC" textline " " bitfld.word 0x00 11. " SOCAEN ,Enable the ADC Start of Conversion A EPWMxSOCA Pulse" "Disabled,Enabled" bitfld.word 0x00 8.--10. " SOCASEL ,EPWMxSOCA Selection Options" "DCAEVT1_soc,TB CNT equal to zero,TB CNT equal to period,TB CNT equal to zero or period,TB CNT equal to CMPA - Timer INC,TB CNT equal to CMPA - Timer DEC,TB CNT equal to CMPB - Timer INC,TB CNT equal to CMPB - Timer DEC" textline " " bitfld.word 0x00 3. " INTEN ,Enable ePWM Interrupt EPWMx_INT Generation" "Disabled,Enabled" bitfld.word 0x00 0.--2. " INTSEL ,ePWM Interrupt EPWMx_INT Selection Options" "Reserved,TB CNT equal to zero,TB CNT equal to period,TB CNT equal to zero or period,TB CNT equal to CMPA - Timer INC,TB CNT equal to CMPA - Timer DEC,TB CNT equal to CMPB - Timer INC,TB CNT equal to CMPB - Timer DEC" line.word 0x02 "ETPS,Event-Trigger Prescale Register" bitfld.word 0x02 14.--15. " SOCBCNT ,ePWM ADC Start-of-Conversion B Event EPWMxSOCB Counter Register" "No events,1 event,2 events,3 events" bitfld.word 0x02 12.--13. " SOCBPRD ,ePWM ADC Start-of-Conversion B Event EPWMxSOCB Period Select" "Disabled,1st event,2nd event,3th event" textline " " bitfld.word 0x02 10.--11. " SOCACNT ,ePWM ADC Start-of-Conversion A Event EPWMxSOCA Counter Register" "No events,1 event,2 events,3 events" bitfld.word 0x02 8.--9. " SOCAPRD ,ePWM ADC Start-of-Conversion A Event EPWMxSOCA Period Select" "Disabled,1st event,2nd event,3th event" textline " " bitfld.word 0x02 2.--3. " INTCNT ,ePWM Interrupt Event EPWMx_INT Counter Register" "No events,1 event,2 events,3 events" bitfld.word 0x02 0.--1. " INTPRD ,ePWM Interrupt EPWMx_INT Period Select" "Disabled,1st event,2nd event,3th event" line.word 0x04 "ETFLG,Event-Trigger Flag Register" bitfld.word 0x04 3. " SOCB ,Latched ePWM ADC Start-of-Conversion B EPWMxSOCB Status Flag" "Not occurred,Occurred" bitfld.word 0x04 2. " SOCA ,Latched ePWM ADC Start-of-Conversion A EPWMxSOCA Status Flag" "Not occurred,Occurred" textline " " bitfld.word 0x04 0. " INT ,Latched ePWM Interrupt EPWMx_INT Status Flag" "Not occurred,Occurred" line.word 0x06 "ETCLR,Event-Trigger Clear Register" bitfld.word 0x06 3. " SOCB ,ePWM ADC Start-of-Conversion B EPWMxSOCB Flag Clear Bit" "No effect,Cleared" bitfld.word 0x06 2. " SOCA ,ePWM ADC Start-of-Conversion A EPWMxSOCB Flag Clear Bit" "No effect,Cleared" textline " " bitfld.word 0x06 0. " INT ,ePWM Interrupt EPWMx_INT Flag Clear Bit" "No effect,Cleared" line.word 0x08 "ETFRC,Event-Trigger Force Register" bitfld.word 0x08 3. " SOCB ,SOCB Force Bit" "No effect,Forced" bitfld.word 0x08 2. " SOCA ,SOCA Force Bit" "No effect,Forced" textline " " bitfld.word 0x08 0. " INT ,INT Force Bit" "No effect,Forced" tree.end width 0xB tree.end tree "ePWM 7" base ad:0xFCF79200 width 14. tree "Time-Base Submodule Registers" group.word 0x0A++0x01 line.word 0x00 "TBPRD,Time-Base Period Register" group.word 0x06++0x03 line.word 0x00 "TBPHS,Time-Base Phase Register" line.word 0x02 "TBCTR,Time-Base Counter Register" group.word 0x00++0x03 line.word 0x00 "TBCTL,Time-Base Control Register" bitfld.word 0x00 14.--15. " FREE/SOFT ,Emulation Mode Bits" "Stop after the next time-base counter INC or DEC,Stop when counter completes a whole cycle,Free run,Free run" textline " " bitfld.word 0x00 13. " PHSDIR ,Phase Direction Bit" "Count down,Count up" bitfld.word 0x00 10.--12. " CLKDIV ,Time-base Clock Prescale Bits" "/1,/2,/4,/8,/16,/32,/64,/128" textline " " bitfld.word 0x00 7.--9. " HSPCLKDIV ,High Speed Time-base Clock Prescale Bits" "/1,/2,/4,/8,/8,/10,/12,/14" bitfld.word 0x00 6. " SWFSYNC ,Software Forced Synchronization Pulse" "No effect,Generated" textline " " bitfld.word 0x00 4.--5. " SYNCOSEL ,Synchronization Output Select" "EPWMxSYNC,CTR = zero,CTR = CMPB,EPWMxSYNCO disable" bitfld.word 0x00 3. " PRDLD ,Active Period Register Load From Shadow Register Select" "Not selected,Selected" bitfld.word 0x00 2. " PHSEN ,Counter Register Load From Phase Register Enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0.--1. " CTRMODE ,Counter Mode" "Up-count,Down-count,Up-down-count,Stop-freeze counter operation" line.word 0x02 "TBSTS,Time-Base Status Register" bitfld.word 0x02 2. " CTRMAX ,Time-Base Counter Max Latched Status Bit time-base counter maximum value" "Not reached,Reached" bitfld.word 0x02 1. " SYNCI ,Input Synchronization Latched Status Bit external synchronization event" "Not occurred,Occurred" textline " " bitfld.word 0x02 0. " CTRDIR ,Time-Base Counter Direction Status Bit" "Down,Up" tree.end width 8. tree "Counter-Compare Submodule Registers" group.word 0x12++0x03 line.word 0x00 "CMPA,Counter-Compare A Register" line.word 0x02 "CMPB,Counter-Compare B Register" group.word 0x0E++0x1 line.word 0x00 "CMPCTL,Counter-Compare Control Register" bitfld.word 0x00 9. " SHDWBFULL ,Counter-compare B CMPB Shadow Register Full Status Flag" "Not full,Full" bitfld.word 0x00 8. " SHDWAFULL ,Counter-compare A CMPA Shadow Register Full Status Flag" "Not full,Full" textline " " bitfld.word 0x00 6. " SHDWBMODE ,Counter-compare B CMPB Register Operating Mode" "Shadow,Immediate" bitfld.word 0x00 4. " SHDWAMODE ,Counter-compare A CMPA Register Operating Mode" "Shadow,Immediate" textline " " bitfld.word 0x00 2.--3. " LOADBMODE ,Active Counter-Compare B CMPB Load From Shadow Select Mode" "CTR = Zero,CTR = PRD,CTR = Zero or CTR = PRD,Freeze" bitfld.word 0x00 0.--1. " LOADAMODE ,Active Counter-Compare A CMPA Load From Shadow Select Mode" "CTR = Zero,CTR = PRD,CTR = Zero or CTR = PRD,Freeze" tree.end width 9. tree "Action-Qualifier Submodule Registers" group.word 0x16++0x07 line.word 0x00 "AQCTLA,Action-Qualifier Output A Control Register" bitfld.word 0x00 10.--11. " CBD ,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "Disabled,Cleared,Set,Toggled" bitfld.word 0x00 8.--9. " CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,Cleared,Set,Toggled" textline " " bitfld.word 0x00 6.--7. " CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,Cleared,Set,Toggled" bitfld.word 0x00 4.--5. " CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,Cleared,Set,Toggled" textline " " bitfld.word 0x00 2.--3. " PRD ,Action when the counter equals the period" "Disabled,Cleared,Set,Toggled" bitfld.word 0x00 0.--1. " ZRO ,Action when counter equals zero" "Disabled,Cleared,Set,Toggled" line.word 0x02 "AQCTLB,Action-Qualifier Output B Control Register" bitfld.word 0x02 10.--11. " CBD ,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "Disabled,Cleared,Set,Toggled" bitfld.word 0x02 8.--9. " CBU ,Action when the counter equals the active CMPB register and the counter is incrementing" "Disabled,Cleared,Set,Toggled" textline " " bitfld.word 0x02 6.--7. " CAD ,Action when the counter equals the active CMPA register and the counter is decrementing" "Disabled,Cleared,Set,Toggled" bitfld.word 0x02 4.--5. " CAU ,Action when the counter equals the active CMPA register and the counter is incrementing" "Disabled,Cleared,Set,Toggled" textline " " bitfld.word 0x02 2.--3. " PRD ,Action when the counter equals the period" "Disabled,Cleared,Set,Toggled" bitfld.word 0x02 0.--1. " ZRO ,Action when counter equals zero" "Disabled,Cleared,Set,Toggled" line.word 0x04 "AQSFRC,Action-Qualifier Software Force Register" bitfld.word 0x04 6.--7. " RLDCSF ,AQCSFRC Active Register Reload From Shadow Options" "Zero,Period,Zero or Period,Immediately" bitfld.word 0x04 5. " OTSFB ,One-Time Software Forced Event on Output B" "No effect,Forced" textline " " bitfld.word 0x04 3.--4. " ACTSFB ,Action when One-Time Software Force B Is invoked" "Disabled,Cleared,Set,Toggled" bitfld.word 0x04 2. " OTSFA ,One-Time Software Forced Event on Output A" "No effect,Forced" textline " " bitfld.word 0x04 0.--1. " ACTSFA ,Action When One-Time Software Force A Is Invoked" "Disabled,Cleared,Set,Toggled" line.word 0x06 "AQCSFRC,Action-Qualifier Continuous Software Force Register" bitfld.word 0x06 2.--3. " CSFB ,Continuous Software Force on Output B" "Forced disabled,Continued low,Continued high,Soft forced disabled" bitfld.word 0x06 0.--1. " CSFA ,Continuous Software Force on Output A" "Forced disabled,Continued low,Continued high,Soft forced disabled" tree.end width 7. tree "Dead-Band Submodule Registers" group.word 0x1E++0x05 line.word 0x00 "DBCTL,Dead-Band Generator Control Register" bitfld.word 0x00 15. " HALFCYCLE ,Half Cycle Clocking Enable Bit" "Disabled,Enabled" textline " " bitfld.word 0x00 4.--5. " IN_MODE ,Dead Band Input Mode Control" "EPWMxA Faling/rising,EPWMxB rising / EPWMxA falling,EPWMxA rising / EPWMxB falling,EPWMxB both rising & falling" textline " " bitfld.word 0x00 2.--3. " POLSEL ,Polarity Select Control" "AH,ALC,AHC,AL" textline " " bitfld.word 0x00 0.--1. " OUT_MODE ,Dead-band Output Mode Control" "Dead-band generation bypassed,Disabled rising-edge delay,Rising-edge delayed signal on EPWMxA,Dead-band fully enabled" line.word 0x02 "DBRED,Dead-Band Generator Rising Edge Delay Register" hexmask.word 0x02 0.--9. 1. " DEL ,Rising Edge Delay Count" line.word 0x04 "DBFED,Dead-Band Generator Falling Edge Delay Register" hexmask.word 0x04 0.--9. 1. " DEL ,Falling Edge Delay Count" tree.end width 0x7 tree "PWM-Chopper Submodule Control Register" group.word 0x3C++0x01 line.word 0x00 "PCCTL,PWM-Chopper Control Register" bitfld.word 0x00 8.--10. " CHPDUTY ,Chopping Clock Duty Cycle" "1/8 (12.5%),2/8 (25.0%),3/8 (37.5%),4/8 (50.0%),5/8 (62.5%),6/8 (75.0%),7/8 (87.5%),?..." textline " " bitfld.word 0x00 5.--7. " CHPFREQ ,Chopping Clock Frequency" "/1 (no prescale = 12.5 MHz at 100 MHz VCLK4),/2 (6.25 MHz at 100 MHz VCLK4),/3 (4.16 MHz at 100 MHz VCLK4),/4 (3.12 MHz at 100 MHz VCLK4),/5 (2.50 MHz at 100 MHz VCLK4),/6 (2.08 MHz at 100 MHz VCLK4),/7 (1.78 MHz at 100 MHz VCLK4),/8 (1.56 MHz at 100 MHz VCLK4)" textline " " bitfld.word 0x00 1.--4. " OSHTWTH ,One-Shot Pulse Width" "1 x VCLK4 / 8 wide ( = 80 nS at 100 MHz VCLK4),2 x VCLK4 / 8 wide ( = 160 nS at 100 MHz VCLK4),3 x VCLK4 / 8 wide ( = 240 nS at 100 MHz VCLK4),4 x VCLK4 / 8 wide ( = 320 nS at 100 MHz VCLK4),5 x VCLK4 / 8 wide ( = 400 nS at 100 MHz VCLK4),6 x VCLK4 / 8 wide ( = 480 nS at 100 MHz VCLK4),7 x VCLK4 / 8 wide ( = 560 nS at 100 MHz VCLK4),8 x VCLK4 / 8 wide ( = 640 nS at 100 MHz VCLK4),9 x VCLK4 / 8 wide ( = 720 nS at 100 MHz VCLK4),10 x VCLK4 / 8 wide ( = 800 nS at 100 MHz VCLK4),11 x VCLK4 / 8 wide ( = 880 nS at 100 MHz VCLK4),12 x VCLK4 / 8 wide ( = 960 nS at 100 MHz VCLK4),13 x VCLK4 / 8 wide ( = 1040 nS at 100 MHz VCLK4),14 x VCLK4 / 8 wide ( = 1120 nS at 100 MHz VCLK4),15 x VCLK4 / 8 wide ( = 1200 nS at 100 MHz VCLK4),16 x VCLK4 / 8 wide ( = 1280 nS at 100 MHz VCLK4)" textline " " bitfld.word 0x00 0. " CHPEN ,PWM-chopping Enable" "Disabled,Enabled" tree.end width 9. tree "Trip-Zone Select Register" group.word 0x24++0x01 line.word 0x00 "TZSEL,Trip-Zone Submodule Control and Status Registers" bitfld.word 0x00 15. " DCBEVT1 ,Digital Compare Output B Event 1 Select" "Disabled,Enabled" bitfld.word 0x00 14. " DCAEVT1 ,Digital Compare Output A Event 1 Select" "Disabled,Enabled" bitfld.word 0x00 13. " OSHT6 ,Trip-zone 6 TZ6 Select" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " OSHT5 ,Trip-zone 5 TZ5 Select" "Disabled,Enabled" bitfld.word 0x00 11. " OSHT4 ,Trip-zone 4 TZ4 Select" "Disabled,Enabled" textline " " bitfld.word 0x00 10. " OSHT3 ,Trip-zone 3 TZ3 Select" "Disabled,Enabled" bitfld.word 0x00 9. " OSHT2 ,Trip-zone 2 TZ2 Select" "Disabled,Enabled" bitfld.word 0x00 8. " OSHT1 ,Trip-zone 1 TZ) Select" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " DCBEVT2 ,Digital Compare Output B Event 2 Select" "Disabled,Enabled" bitfld.word 0x00 6. " DCAEVT2 ,Digital Compare Output A Event 2 Select" "Disabled,Enabled" bitfld.word 0x00 5. " CBC6 ,Trip-zone 6 TZ6 Select" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " CBC5 ,Trip-zone 5 TZ5 Select" "Disabled,Enabled" bitfld.word 0x00 3. " CBC4 ,Trip-zone 4 TZ4 Select" "Disabled,Enabled" bitfld.word 0x00 2. " CBC3 ,Trip-zone 3 TZ3 Select" "Disabled,Enabled" textline " " bitfld.word 0x00 1. " CBC2 ,Trip-zone 2 TZ2 Select" "Disabled,Enabled" bitfld.word 0x00 0. " CBC1 ,Trip-zone 1 TZ1 Select" "Disabled,Enabled" group.word 0x28++0x01 line.word 0x00 "TZCTL,Trip-Zone Control Register" bitfld.word 0x00 10.--11. " DCBEVT2 ,Digital Compare Output B Event 2 Action On EPWMxB" "High-impedance,High state,Low state,Disabled" bitfld.word 0x00 8.--9. " DCBEVT1 ,Digital Compare Output B Event 1 Action On EPWMxB" "High-impedance,Forced high state,Forced low state,Disabled" textline " " bitfld.word 0x00 6.--7. " DCAEVT2 ,Digital Compare Output A Event 2 Action On EPWMxA" "High-impedance,Forced high state,Forced low state,Disabled" bitfld.word 0x00 4.--5. " DCAEVT1 ,Digital Compare Output A Event 1 Action On EPWMxA" "High-impedance,Forced high state,Forced low state,Disabled" textline " " bitfld.word 0x00 2.--3. " TZB ,When a trip event occurs the following action is taken on output EPWMxB" "High-impedance,Forced high state,Forced low state,Disabled" bitfld.word 0x00 0.--1. " TZA ,When a trip event occurs the following action is taken on output EPWMxA" "High-impedance,Forced high state,Forced low state,Disabled" group.word 0x2C++0x01 line.word 0x00 "TZFLG,Trip-Zone Flag Register Field Descriptions" setclrfld.word 0x00 6. -0x02 6. 0x02 6. " DCBEVT2_set/clr ,Digital Comparator Output B Event 2 Interrupt" "Not occurred,Occurred" setclrfld.word 0x00 5. -0x02 5. 0x02 5. " DCBEVT1_set/clr ,Digital Comparator Output B Event 1 Interrupt" "Not occurred,Occurred" textline " " setclrfld.word 0x00 4. -0x02 4. 0x02 4. " DCAEVT2_set/clr ,Digital Comparator Output A Event 2 Interrupt" "Not occurred,Occurred" setclrfld.word 0x00 3. -0x02 3. 0x02 3. " DCAEVT1_set/clr ,Digital Comparator Output A Event 1 Interrupt" "Not occurred,Occurred" textline " " setclrfld.word 0x00 2. -0x02 2. 0x02 2. " OST_set/clr ,Trip-zone One-Shot Interrupt" "Not occurred,Occurred" setclrfld.word 0x00 1. -0x02 1. 0x02 1. " CBC_set/clr ,Trip-zone Cycle-by-Cycle Interrupt" "Not occurred,Occurred" textline " " setclrfld.word 0x00 0. 0x00 0. 0x02 0. " INT_set/clr ,Latched Trip Interrupt Status Flag" "Not generated,Generated" group.word 0x30++0x01 line.word 0x00 "TZFRC,Trip-Zone Force Register" bitfld.word 0x00 6. " DCBEVT2 ,Force Flag for Digital Compare Output B Event 2" "No effect,Forced" bitfld.word 0x00 5. " DCBEVT1 ,Force Flag for Digital Compare Output B Event 1" "No effect,Forced" textline " " bitfld.word 0x00 4. " DCAEVT2 ,Force Flag for Digital Compare Output A Event 2" "No effect,Forced" bitfld.word 0x00 3. " DCAEVT1 ,Force Flag for Digital Compare Output A Event 1" "No effect,Forced" textline " " bitfld.word 0x00 2. " OST ,Force a One-Shot Trip Event via Software" "No effect,Forced" bitfld.word 0x00 1. " CBC ,Force a Cycle-by-Cycle Trip Event via Software" "No effect,Forced" group.word 0x26++0x01 line.word 0x00 "TZDCSEL,Trip Zone Digital Compare Event Select Register" bitfld.word 0x00 9.--11. " DCBEVT2 ,Digital Compare Output B Event 2 Selection" "Event disabled,DCBH = low,DCBH = high,DCBL = low,DCBL = high,DCBL = high - DCBH = low,?..." bitfld.word 0x00 6.--8. " DCBEVT1 ,Digital Compare Output B Event 1 Selection" "Event disabled,DCBH = low,DCBH = high,DCBL = low,DCBL = high,DCBL = high - DCBH = low,?..." textline " " bitfld.word 0x00 3.--5. " DCAEVT2 ,Digital Compare Output A Event 2 Selection" "Event disabled,DCAH = low,DCAH = high,DCAL = low,DCAL = high,DCAL = high - DCAH = low,?..." bitfld.word 0x00 0.--2. " DCAEVT1 ,Digital Compare Output A Event 1 Selection" "Event disabled,DCAH = low,DCAH = high,DCAL = low,DCAL = high,DCAL = high,?..." tree.end width 11. tree "Digital Compare Submodule Registers" group.word 0x60++0x09 line.word 0x00 "DCTRIPSEL,Digital Compare Trip Select" bitfld.word 0x00 12.--15. " DCBLCOMPSEL ,Digital Compare B Low Input Select" "TZ1 input,TZ2 input,TZ3 input,?..." bitfld.word 0x00 8.--11. " DCBHCOMPSEL ,Digital Compare B High Input Select" "TZ1 input,TZ2 input,TZ3 input,?..." textline " " bitfld.word 0x00 4.--7. " DCALCOMPSEL ,Digital Compare A Low Input Select" "TZ1 input,TZ2 input,TZ3 input,?..." bitfld.word 0x00 0.--3. " DCAHCOMPSEL ,Digital Compare A High Input Select" "TZ1 input,TZ2 input,TZ3 input,?..." line.word 0x02 "DCACTL,Digital Compare A Control Register" bitfld.word 0x02 9. " EVT2FRC_SYNCSEL ,DCAEVT2 Force Synchronization Signal Select" "Synchronous,Asynchronous" bitfld.word 0x02 8. " EVT2SRCSEL ,DCAEVT2 Source Signal Select" "DCAEVT2,DCEVTFILT" textline " " bitfld.word 0x02 3. " EVT1SYNCE ,DCAEVT1 SYNC Generation" "Disabled,Enabled" bitfld.word 0x02 2. " EVT1SOCE ,DCAEVT1 SOC Generation" "Disabled,Enabled" textline " " bitfld.word 0x02 1. " EVT1FRC_SYNCSEL ,DCAEVT1 Force Synchronization Signal Select" "Synchronous,Asynchronous" bitfld.word 0x02 0. " EVT1SRCSEL ,DCAEVT1 Source Signal Select" "DCAEVT,DCEVTFILT" line.word 0x04 "DCBCTL,Digital Compare B Control Register" bitfld.word 0x04 9. " EVT2FRC_SYNCSEL ,DCBEVT2 Force Synchronization Signal Select" "Synchronous,Asynchronous" bitfld.word 0x04 8. " EVT2SRCSEL ,DCBEVT2 Source Signal Select" "DCBEVT2,DCEVTFILT" textline " " bitfld.word 0x04 3. " EVT1SYNCE ,DCBEVT1 SYNC Generation" "Disabled,Enabled" bitfld.word 0x04 2. " EVT1SOCE ,DCBEVT1 SOC Generation" "Disabled,Enabled" textline " " bitfld.word 0x04 1. " EVT1FRC_SYNCSEL ,DCBEVT1 Force Synchronization Signal Select" "Synchronous,Asynchronous" bitfld.word 0x04 0. " EVT1SRCSEL ,DCBEVT1 Source Signal Select" "DCBEVT,DCEVTFILT" line.word 0x06 "DBFCTL,Digital Compare Filter Control Register" bitfld.word 0x06 4.--5. " PULSESEL ,Pulse Select For Blanking & Capture Alignment" "TB CNT Equal to period,TB CNT Equal to zero,?..." textline " " bitfld.word 0x06 3. " BLANKINV ,Blanking Window Inversion" "Not inverted,Inverted" bitfld.word 0x06 2. " BLANKE ,Blanking Window Enable/Disable" "Disabled,Enabled" textline " " bitfld.word 0x06 0.--1. " SRCSEL ,Filter Block Signal Source Select" "DCAEVT1,DCAEVT2,DCBEVT1,DCBEVT2" line.word 0x08 "DBCAPCTL,Digital Compare Capture Control Register" bitfld.word 0x08 1. " SHDWMODE ,TBCTR Counter Capture Shadow Select Mode" "Shadow mode,Active Mode" bitfld.word 0x08 0. " CAPE ,TBCTR Counter Capture Enable/Disable" "Disabled,Enabled" width 14. rgroup.word 0x72++0x01 line.word 0x00 "DCCAP,Digital Compare Counter Capture Register" rgroup.word 0x6A++0x01 line.word 0x00 "DCFOFFSET,Digital Compare Filter Offset Register" group.word 0x6E++0x01 line.word 0x00 "DCFWINDOW,Digital Compare Filter Window Register" hexmask.word.byte 0x00 0.--7. 1. " WINDOW ,Blanking Window Width" rgroup.word 0x70++0x01 line.word 0x00 "DCFWINDOWCNT,Digital Compare Filter Window Counter Register" hexmask.word.byte 0x00 0.--7. 1. " WINDOWCNT ,Digital Compare Filter Window Counter Register" tree.end width 7. tree "Event-Trigger Submodule Registers" group.word 0x32++0x09 line.word 0x00 "ETSEL,Event-Trigger Selection Register" bitfld.word 0x00 15. " SOCBEN ,Enable the ADC Start of Conversion B EPWMxSOCB Pulse" "Disabled,Enabled" bitfld.word 0x00 12.--14. " SOCBSEL ,EPWMxSOCB Selection Options" "DCBEVT1_soc,TB CNT equal to zero,TB CNT equal to period,TB CNT equal to zero or period,TB CNT equal to CMPA - Timer INC,TB CNT equal to CMPA - Timer DEC,TB CNT equal to CMPB - Timer INC,TB CNT equal to CMPB - Timer DEC" textline " " bitfld.word 0x00 11. " SOCAEN ,Enable the ADC Start of Conversion A EPWMxSOCA Pulse" "Disabled,Enabled" bitfld.word 0x00 8.--10. " SOCASEL ,EPWMxSOCA Selection Options" "DCAEVT1_soc,TB CNT equal to zero,TB CNT equal to period,TB CNT equal to zero or period,TB CNT equal to CMPA - Timer INC,TB CNT equal to CMPA - Timer DEC,TB CNT equal to CMPB - Timer INC,TB CNT equal to CMPB - Timer DEC" textline " " bitfld.word 0x00 3. " INTEN ,Enable ePWM Interrupt EPWMx_INT Generation" "Disabled,Enabled" bitfld.word 0x00 0.--2. " INTSEL ,ePWM Interrupt EPWMx_INT Selection Options" "Reserved,TB CNT equal to zero,TB CNT equal to period,TB CNT equal to zero or period,TB CNT equal to CMPA - Timer INC,TB CNT equal to CMPA - Timer DEC,TB CNT equal to CMPB - Timer INC,TB CNT equal to CMPB - Timer DEC" line.word 0x02 "ETPS,Event-Trigger Prescale Register" bitfld.word 0x02 14.--15. " SOCBCNT ,ePWM ADC Start-of-Conversion B Event EPWMxSOCB Counter Register" "No events,1 event,2 events,3 events" bitfld.word 0x02 12.--13. " SOCBPRD ,ePWM ADC Start-of-Conversion B Event EPWMxSOCB Period Select" "Disabled,1st event,2nd event,3th event" textline " " bitfld.word 0x02 10.--11. " SOCACNT ,ePWM ADC Start-of-Conversion A Event EPWMxSOCA Counter Register" "No events,1 event,2 events,3 events" bitfld.word 0x02 8.--9. " SOCAPRD ,ePWM ADC Start-of-Conversion A Event EPWMxSOCA Period Select" "Disabled,1st event,2nd event,3th event" textline " " bitfld.word 0x02 2.--3. " INTCNT ,ePWM Interrupt Event EPWMx_INT Counter Register" "No events,1 event,2 events,3 events" bitfld.word 0x02 0.--1. " INTPRD ,ePWM Interrupt EPWMx_INT Period Select" "Disabled,1st event,2nd event,3th event" line.word 0x04 "ETFLG,Event-Trigger Flag Register" bitfld.word 0x04 3. " SOCB ,Latched ePWM ADC Start-of-Conversion B EPWMxSOCB Status Flag" "Not occurred,Occurred" bitfld.word 0x04 2. " SOCA ,Latched ePWM ADC Start-of-Conversion A EPWMxSOCA Status Flag" "Not occurred,Occurred" textline " " bitfld.word 0x04 0. " INT ,Latched ePWM Interrupt EPWMx_INT Status Flag" "Not occurred,Occurred" line.word 0x06 "ETCLR,Event-Trigger Clear Register" bitfld.word 0x06 3. " SOCB ,ePWM ADC Start-of-Conversion B EPWMxSOCB Flag Clear Bit" "No effect,Cleared" bitfld.word 0x06 2. " SOCA ,ePWM ADC Start-of-Conversion A EPWMxSOCB Flag Clear Bit" "No effect,Cleared" textline " " bitfld.word 0x06 0. " INT ,ePWM Interrupt EPWMx_INT Flag Clear Bit" "No effect,Cleared" line.word 0x08 "ETFRC,Event-Trigger Force Register" bitfld.word 0x08 3. " SOCB ,SOCB Force Bit" "No effect,Forced" bitfld.word 0x08 2. " SOCA ,SOCA Force Bit" "No effect,Forced" textline " " bitfld.word 0x08 0. " INT ,INT Force Bit" "No effect,Forced" tree.end width 0xB tree.end tree.end tree.open "eCAP (Enhanced Capture)" tree "eCAP 1" base ad:0xFCF79300 width 0x8 group.long 0x00++0x17 line.long 0x00 "TSCTR,Time-Stamp Counter Register" line.long 0x04 "CTRPHS,Counter Phase Control Register" line.long 0x08 "CAP1,Capture-1 Register" line.long 0x0C "CAP2,Capture-2 Register" line.long 0x10 "CAP3,Capture-3 Register" line.long 0x14 "CAP4,Capture-4 Register" group.word 0x28++0x01 line.word 0x00 "ECCTL1,ECAP Control Regiser 1" bitfld.word 0x00 14.--15. " FREE/SOFT ,Emulation Control" "Stopped immediately,Run until = 0,Run Free,Run Free" bitfld.word 0x00 9.--13. " PRESCALE ,Event Filter prescale sel" "/1,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32,/34,/36,/38,/40,/42,/44,/46,/48,/50,/52,/54,/56,/58,/60,/62" textline " " bitfld.word 0x00 8. " CAPLDEN ,Enable Loading of CAP1-4 registers on a capture event" "Disabled,Enabled" bitfld.word 0x00 7. " CTRRST4 ,Counter Reset on Capture Event 4" "Not reset,Reset" textline " " bitfld.word 0x00 6. " CAP4POL ,Capture Event 4 Polarity select" "RE,FE" bitfld.word 0x00 5. " CTRRST3 ,Counter Reset on Capture Event 3" "Not reset,Reset" textline " " bitfld.word 0x00 4. " CAP3POL ,Capture Event 3 Polarity select" "RE,FE" bitfld.word 0x00 3. " CTRRST2 ,Counter Reset on Capture Event 2" "Not reset,Reset" textline " " bitfld.word 0x00 2. " CAP2POL ,Capture Event 2 Polarity select" "RE,FE" bitfld.word 0x00 1. " CTRRST1 ,Counter Reset on Capture Event 1" "Not reset,Reset" textline " " bitfld.word 0x00 0. " CAP1POL ,Capture Event 1 Polarity select" "RE,FE" if ((d.w(ad:0xFCF79300+0x2A)&0x200)==0x200) group.word 0x2A++0x01 line.word 0x00 "ECCTL2,ECAP Control Register 2" bitfld.word 0x00 10. " APWMPOL ,APWM output polarity select" "High,Low" bitfld.word 0x00 9. " CAP/APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode" textline " " bitfld.word 0x00 8. " SWSYNC ,Software-forced Counter TSCTR Synchronizing" "No effect,Forced" bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out Select" "Pass through,CTR = PRD,Disabled,Disabled" textline " " bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled" bitfld.word 0x00 4. " TSCTRSTOP ,Time Stamp TSCTR Counter Stop Control" "Stopped,Free-running" textline " " bitfld.word 0x00 3. " RE-ARM ,One-Shot Re-Arming Control" "No effect,One-shot sequence" bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot mode" "Capture Event 1,Capture Event 2,Capture Event 3,Capture Event 4" else group.word 0x2A++0x01 line.word 0x00 "ECCTL2,ECAP Control Register 2" bitfld.word 0x00 9. " CAP/APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode" textline " " bitfld.word 0x00 8. " SWSYNC ,Software-forced Counter TSCTR Synchronizing" "No effect,Forced" bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out Select" "Pass through,CTR = PRD,Disabled,Disabled" textline " " bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled" bitfld.word 0x00 4. " TSCTRSTOP ,Time Stamp TSCTR Counter Stop Control" "Stopped,Free-running" textline " " bitfld.word 0x00 3. " RE-ARM ,One-Shot Re-Arming Control" "No effect,One-shot sequence" bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot mode" "Capture Event 1,Capture Event 2,Capture Event 3,Capture Event 4" textline " " bitfld.word 0x00 0. " CONT/ONESHT ,Continuous or one-shot mode control" "Continuous,One-Shot" endif group.word 0x2E++0x01 line.word 0x00 "ECFLG,ECAP Interrupt Flag Register" setclrfld.word 0x00 7. -0x02 7. 0x02 7. " CTR=CMP_set/clr ,Compare Equal Compare Status Flag" "Not occurred,Occurred" setclrfld.word 0x00 6. -0x02 6. 0x02 6. " CTR=PRD_set/clr ,Counter Equal Period Interrupt Enable" "Not occurred,Occurred" textline " " setclrfld.word 0x00 5. -0x02 5. 0x02 5. " CTROVF_set/clr ,Counter Equal Period Status Flag" "Not occurred,Occurred" setclrfld.word 0x00 4. -0x02 4. 0x02 4. " CEVT4_set/clr ,Counter Overflow Status Flag" "Not occurred,Occurred" textline " " setclrfld.word 0x00 3. -0x02 3. 0x02 3. " CEVT3_set/clr ,Capture Event 4 Status Flag" "Not occurred,Occurred" setclrfld.word 0x00 2. -0x02 2. 0x02 2. " CEVT2_set/clr ,Capture Event 2 Status Flag" "Not occurred,Occurred" textline " " setclrfld.word 0x00 1. -0x02 1. 0x02 1. " CEVT1_set/clr ,Capture Event 1 Interrupt Enable" "Not occurred,Occurred" setclrfld.word 0x00 0. 0x00 0. 0x02 0. " INT_set/clr ,Global Interrupt Status Flag" "Not generated,Generated" group.word 0x32++0x01 line.word 0x00 "ECFRC,ECAP Interrupt Forcing Register" eventfld.word 0x00 7. " CTR_CMP ,Force Counter Equal Compare Interrupt" "No effect,Forced" eventfld.word 0x00 6. " CTR_PRD ,Force Counter Equal Period Interrupt" "No effect,Forced" textline " " eventfld.word 0x00 5. " CTROVF ,Force Counter Overflow" "No effect,Forced" eventfld.word 0x00 4. " CEVT4 ,Force Capture Event 4" "No effect,Forced" textline " " eventfld.word 0x00 3. " CEVT3 ,Force Capture Event 3" "No effect,Forced" eventfld.word 0x00 2. " CEVT2 ,Force Capture Event 2" "No effect,Forced" textline " " eventfld.word 0x00 1. " CEVT1 ,Force Capture Event 1" "No effect,Forced" width 0xB tree.end tree "eCAP 2" base ad:0xFCF79400 width 0x8 group.long 0x00++0x17 line.long 0x00 "TSCTR,Time-Stamp Counter Register" line.long 0x04 "CTRPHS,Counter Phase Control Register" line.long 0x08 "CAP1,Capture-1 Register" line.long 0x0C "CAP2,Capture-2 Register" line.long 0x10 "CAP3,Capture-3 Register" line.long 0x14 "CAP4,Capture-4 Register" group.word 0x28++0x01 line.word 0x00 "ECCTL1,ECAP Control Regiser 1" bitfld.word 0x00 14.--15. " FREE/SOFT ,Emulation Control" "Stopped immediately,Run until = 0,Run Free,Run Free" bitfld.word 0x00 9.--13. " PRESCALE ,Event Filter prescale sel" "/1,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32,/34,/36,/38,/40,/42,/44,/46,/48,/50,/52,/54,/56,/58,/60,/62" textline " " bitfld.word 0x00 8. " CAPLDEN ,Enable Loading of CAP1-4 registers on a capture event" "Disabled,Enabled" bitfld.word 0x00 7. " CTRRST4 ,Counter Reset on Capture Event 4" "Not reset,Reset" textline " " bitfld.word 0x00 6. " CAP4POL ,Capture Event 4 Polarity select" "RE,FE" bitfld.word 0x00 5. " CTRRST3 ,Counter Reset on Capture Event 3" "Not reset,Reset" textline " " bitfld.word 0x00 4. " CAP3POL ,Capture Event 3 Polarity select" "RE,FE" bitfld.word 0x00 3. " CTRRST2 ,Counter Reset on Capture Event 2" "Not reset,Reset" textline " " bitfld.word 0x00 2. " CAP2POL ,Capture Event 2 Polarity select" "RE,FE" bitfld.word 0x00 1. " CTRRST1 ,Counter Reset on Capture Event 1" "Not reset,Reset" textline " " bitfld.word 0x00 0. " CAP1POL ,Capture Event 1 Polarity select" "RE,FE" if ((d.w(ad:0xFCF79400+0x2A)&0x200)==0x200) group.word 0x2A++0x01 line.word 0x00 "ECCTL2,ECAP Control Register 2" bitfld.word 0x00 10. " APWMPOL ,APWM output polarity select" "High,Low" bitfld.word 0x00 9. " CAP/APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode" textline " " bitfld.word 0x00 8. " SWSYNC ,Software-forced Counter TSCTR Synchronizing" "No effect,Forced" bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out Select" "Pass through,CTR = PRD,Disabled,Disabled" textline " " bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled" bitfld.word 0x00 4. " TSCTRSTOP ,Time Stamp TSCTR Counter Stop Control" "Stopped,Free-running" textline " " bitfld.word 0x00 3. " RE-ARM ,One-Shot Re-Arming Control" "No effect,One-shot sequence" bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot mode" "Capture Event 1,Capture Event 2,Capture Event 3,Capture Event 4" else group.word 0x2A++0x01 line.word 0x00 "ECCTL2,ECAP Control Register 2" bitfld.word 0x00 9. " CAP/APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode" textline " " bitfld.word 0x00 8. " SWSYNC ,Software-forced Counter TSCTR Synchronizing" "No effect,Forced" bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out Select" "Pass through,CTR = PRD,Disabled,Disabled" textline " " bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled" bitfld.word 0x00 4. " TSCTRSTOP ,Time Stamp TSCTR Counter Stop Control" "Stopped,Free-running" textline " " bitfld.word 0x00 3. " RE-ARM ,One-Shot Re-Arming Control" "No effect,One-shot sequence" bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot mode" "Capture Event 1,Capture Event 2,Capture Event 3,Capture Event 4" textline " " bitfld.word 0x00 0. " CONT/ONESHT ,Continuous or one-shot mode control" "Continuous,One-Shot" endif group.word 0x2E++0x01 line.word 0x00 "ECFLG,ECAP Interrupt Flag Register" setclrfld.word 0x00 7. -0x02 7. 0x02 7. " CTR=CMP_set/clr ,Compare Equal Compare Status Flag" "Not occurred,Occurred" setclrfld.word 0x00 6. -0x02 6. 0x02 6. " CTR=PRD_set/clr ,Counter Equal Period Interrupt Enable" "Not occurred,Occurred" textline " " setclrfld.word 0x00 5. -0x02 5. 0x02 5. " CTROVF_set/clr ,Counter Equal Period Status Flag" "Not occurred,Occurred" setclrfld.word 0x00 4. -0x02 4. 0x02 4. " CEVT4_set/clr ,Counter Overflow Status Flag" "Not occurred,Occurred" textline " " setclrfld.word 0x00 3. -0x02 3. 0x02 3. " CEVT3_set/clr ,Capture Event 4 Status Flag" "Not occurred,Occurred" setclrfld.word 0x00 2. -0x02 2. 0x02 2. " CEVT2_set/clr ,Capture Event 2 Status Flag" "Not occurred,Occurred" textline " " setclrfld.word 0x00 1. -0x02 1. 0x02 1. " CEVT1_set/clr ,Capture Event 1 Interrupt Enable" "Not occurred,Occurred" setclrfld.word 0x00 0. 0x00 0. 0x02 0. " INT_set/clr ,Global Interrupt Status Flag" "Not generated,Generated" group.word 0x32++0x01 line.word 0x00 "ECFRC,ECAP Interrupt Forcing Register" eventfld.word 0x00 7. " CTR_CMP ,Force Counter Equal Compare Interrupt" "No effect,Forced" eventfld.word 0x00 6. " CTR_PRD ,Force Counter Equal Period Interrupt" "No effect,Forced" textline " " eventfld.word 0x00 5. " CTROVF ,Force Counter Overflow" "No effect,Forced" eventfld.word 0x00 4. " CEVT4 ,Force Capture Event 4" "No effect,Forced" textline " " eventfld.word 0x00 3. " CEVT3 ,Force Capture Event 3" "No effect,Forced" eventfld.word 0x00 2. " CEVT2 ,Force Capture Event 2" "No effect,Forced" textline " " eventfld.word 0x00 1. " CEVT1 ,Force Capture Event 1" "No effect,Forced" width 0xB tree.end tree "eCAP 3" base ad:0xFCF79500 width 0x8 group.long 0x00++0x17 line.long 0x00 "TSCTR,Time-Stamp Counter Register" line.long 0x04 "CTRPHS,Counter Phase Control Register" line.long 0x08 "CAP1,Capture-1 Register" line.long 0x0C "CAP2,Capture-2 Register" line.long 0x10 "CAP3,Capture-3 Register" line.long 0x14 "CAP4,Capture-4 Register" group.word 0x28++0x01 line.word 0x00 "ECCTL1,ECAP Control Regiser 1" bitfld.word 0x00 14.--15. " FREE/SOFT ,Emulation Control" "Stopped immediately,Run until = 0,Run Free,Run Free" bitfld.word 0x00 9.--13. " PRESCALE ,Event Filter prescale sel" "/1,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32,/34,/36,/38,/40,/42,/44,/46,/48,/50,/52,/54,/56,/58,/60,/62" textline " " bitfld.word 0x00 8. " CAPLDEN ,Enable Loading of CAP1-4 registers on a capture event" "Disabled,Enabled" bitfld.word 0x00 7. " CTRRST4 ,Counter Reset on Capture Event 4" "Not reset,Reset" textline " " bitfld.word 0x00 6. " CAP4POL ,Capture Event 4 Polarity select" "RE,FE" bitfld.word 0x00 5. " CTRRST3 ,Counter Reset on Capture Event 3" "Not reset,Reset" textline " " bitfld.word 0x00 4. " CAP3POL ,Capture Event 3 Polarity select" "RE,FE" bitfld.word 0x00 3. " CTRRST2 ,Counter Reset on Capture Event 2" "Not reset,Reset" textline " " bitfld.word 0x00 2. " CAP2POL ,Capture Event 2 Polarity select" "RE,FE" bitfld.word 0x00 1. " CTRRST1 ,Counter Reset on Capture Event 1" "Not reset,Reset" textline " " bitfld.word 0x00 0. " CAP1POL ,Capture Event 1 Polarity select" "RE,FE" if ((d.w(ad:0xFCF79500+0x2A)&0x200)==0x200) group.word 0x2A++0x01 line.word 0x00 "ECCTL2,ECAP Control Register 2" bitfld.word 0x00 10. " APWMPOL ,APWM output polarity select" "High,Low" bitfld.word 0x00 9. " CAP/APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode" textline " " bitfld.word 0x00 8. " SWSYNC ,Software-forced Counter TSCTR Synchronizing" "No effect,Forced" bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out Select" "Pass through,CTR = PRD,Disabled,Disabled" textline " " bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled" bitfld.word 0x00 4. " TSCTRSTOP ,Time Stamp TSCTR Counter Stop Control" "Stopped,Free-running" textline " " bitfld.word 0x00 3. " RE-ARM ,One-Shot Re-Arming Control" "No effect,One-shot sequence" bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot mode" "Capture Event 1,Capture Event 2,Capture Event 3,Capture Event 4" else group.word 0x2A++0x01 line.word 0x00 "ECCTL2,ECAP Control Register 2" bitfld.word 0x00 9. " CAP/APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode" textline " " bitfld.word 0x00 8. " SWSYNC ,Software-forced Counter TSCTR Synchronizing" "No effect,Forced" bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out Select" "Pass through,CTR = PRD,Disabled,Disabled" textline " " bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled" bitfld.word 0x00 4. " TSCTRSTOP ,Time Stamp TSCTR Counter Stop Control" "Stopped,Free-running" textline " " bitfld.word 0x00 3. " RE-ARM ,One-Shot Re-Arming Control" "No effect,One-shot sequence" bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot mode" "Capture Event 1,Capture Event 2,Capture Event 3,Capture Event 4" textline " " bitfld.word 0x00 0. " CONT/ONESHT ,Continuous or one-shot mode control" "Continuous,One-Shot" endif group.word 0x2E++0x01 line.word 0x00 "ECFLG,ECAP Interrupt Flag Register" setclrfld.word 0x00 7. -0x02 7. 0x02 7. " CTR=CMP_set/clr ,Compare Equal Compare Status Flag" "Not occurred,Occurred" setclrfld.word 0x00 6. -0x02 6. 0x02 6. " CTR=PRD_set/clr ,Counter Equal Period Interrupt Enable" "Not occurred,Occurred" textline " " setclrfld.word 0x00 5. -0x02 5. 0x02 5. " CTROVF_set/clr ,Counter Equal Period Status Flag" "Not occurred,Occurred" setclrfld.word 0x00 4. -0x02 4. 0x02 4. " CEVT4_set/clr ,Counter Overflow Status Flag" "Not occurred,Occurred" textline " " setclrfld.word 0x00 3. -0x02 3. 0x02 3. " CEVT3_set/clr ,Capture Event 4 Status Flag" "Not occurred,Occurred" setclrfld.word 0x00 2. -0x02 2. 0x02 2. " CEVT2_set/clr ,Capture Event 2 Status Flag" "Not occurred,Occurred" textline " " setclrfld.word 0x00 1. -0x02 1. 0x02 1. " CEVT1_set/clr ,Capture Event 1 Interrupt Enable" "Not occurred,Occurred" setclrfld.word 0x00 0. 0x00 0. 0x02 0. " INT_set/clr ,Global Interrupt Status Flag" "Not generated,Generated" group.word 0x32++0x01 line.word 0x00 "ECFRC,ECAP Interrupt Forcing Register" eventfld.word 0x00 7. " CTR_CMP ,Force Counter Equal Compare Interrupt" "No effect,Forced" eventfld.word 0x00 6. " CTR_PRD ,Force Counter Equal Period Interrupt" "No effect,Forced" textline " " eventfld.word 0x00 5. " CTROVF ,Force Counter Overflow" "No effect,Forced" eventfld.word 0x00 4. " CEVT4 ,Force Capture Event 4" "No effect,Forced" textline " " eventfld.word 0x00 3. " CEVT3 ,Force Capture Event 3" "No effect,Forced" eventfld.word 0x00 2. " CEVT2 ,Force Capture Event 2" "No effect,Forced" textline " " eventfld.word 0x00 1. " CEVT1 ,Force Capture Event 1" "No effect,Forced" width 0xB tree.end tree "eCAP 4" base ad:0xFCF79600 width 0x8 group.long 0x00++0x17 line.long 0x00 "TSCTR,Time-Stamp Counter Register" line.long 0x04 "CTRPHS,Counter Phase Control Register" line.long 0x08 "CAP1,Capture-1 Register" line.long 0x0C "CAP2,Capture-2 Register" line.long 0x10 "CAP3,Capture-3 Register" line.long 0x14 "CAP4,Capture-4 Register" group.word 0x28++0x01 line.word 0x00 "ECCTL1,ECAP Control Regiser 1" bitfld.word 0x00 14.--15. " FREE/SOFT ,Emulation Control" "Stopped immediately,Run until = 0,Run Free,Run Free" bitfld.word 0x00 9.--13. " PRESCALE ,Event Filter prescale sel" "/1,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32,/34,/36,/38,/40,/42,/44,/46,/48,/50,/52,/54,/56,/58,/60,/62" textline " " bitfld.word 0x00 8. " CAPLDEN ,Enable Loading of CAP1-4 registers on a capture event" "Disabled,Enabled" bitfld.word 0x00 7. " CTRRST4 ,Counter Reset on Capture Event 4" "Not reset,Reset" textline " " bitfld.word 0x00 6. " CAP4POL ,Capture Event 4 Polarity select" "RE,FE" bitfld.word 0x00 5. " CTRRST3 ,Counter Reset on Capture Event 3" "Not reset,Reset" textline " " bitfld.word 0x00 4. " CAP3POL ,Capture Event 3 Polarity select" "RE,FE" bitfld.word 0x00 3. " CTRRST2 ,Counter Reset on Capture Event 2" "Not reset,Reset" textline " " bitfld.word 0x00 2. " CAP2POL ,Capture Event 2 Polarity select" "RE,FE" bitfld.word 0x00 1. " CTRRST1 ,Counter Reset on Capture Event 1" "Not reset,Reset" textline " " bitfld.word 0x00 0. " CAP1POL ,Capture Event 1 Polarity select" "RE,FE" if ((d.w(ad:0xFCF79600+0x2A)&0x200)==0x200) group.word 0x2A++0x01 line.word 0x00 "ECCTL2,ECAP Control Register 2" bitfld.word 0x00 10. " APWMPOL ,APWM output polarity select" "High,Low" bitfld.word 0x00 9. " CAP/APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode" textline " " bitfld.word 0x00 8. " SWSYNC ,Software-forced Counter TSCTR Synchronizing" "No effect,Forced" bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out Select" "Pass through,CTR = PRD,Disabled,Disabled" textline " " bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled" bitfld.word 0x00 4. " TSCTRSTOP ,Time Stamp TSCTR Counter Stop Control" "Stopped,Free-running" textline " " bitfld.word 0x00 3. " RE-ARM ,One-Shot Re-Arming Control" "No effect,One-shot sequence" bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot mode" "Capture Event 1,Capture Event 2,Capture Event 3,Capture Event 4" else group.word 0x2A++0x01 line.word 0x00 "ECCTL2,ECAP Control Register 2" bitfld.word 0x00 9. " CAP/APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode" textline " " bitfld.word 0x00 8. " SWSYNC ,Software-forced Counter TSCTR Synchronizing" "No effect,Forced" bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out Select" "Pass through,CTR = PRD,Disabled,Disabled" textline " " bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled" bitfld.word 0x00 4. " TSCTRSTOP ,Time Stamp TSCTR Counter Stop Control" "Stopped,Free-running" textline " " bitfld.word 0x00 3. " RE-ARM ,One-Shot Re-Arming Control" "No effect,One-shot sequence" bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot mode" "Capture Event 1,Capture Event 2,Capture Event 3,Capture Event 4" textline " " bitfld.word 0x00 0. " CONT/ONESHT ,Continuous or one-shot mode control" "Continuous,One-Shot" endif group.word 0x2E++0x01 line.word 0x00 "ECFLG,ECAP Interrupt Flag Register" setclrfld.word 0x00 7. -0x02 7. 0x02 7. " CTR=CMP_set/clr ,Compare Equal Compare Status Flag" "Not occurred,Occurred" setclrfld.word 0x00 6. -0x02 6. 0x02 6. " CTR=PRD_set/clr ,Counter Equal Period Interrupt Enable" "Not occurred,Occurred" textline " " setclrfld.word 0x00 5. -0x02 5. 0x02 5. " CTROVF_set/clr ,Counter Equal Period Status Flag" "Not occurred,Occurred" setclrfld.word 0x00 4. -0x02 4. 0x02 4. " CEVT4_set/clr ,Counter Overflow Status Flag" "Not occurred,Occurred" textline " " setclrfld.word 0x00 3. -0x02 3. 0x02 3. " CEVT3_set/clr ,Capture Event 4 Status Flag" "Not occurred,Occurred" setclrfld.word 0x00 2. -0x02 2. 0x02 2. " CEVT2_set/clr ,Capture Event 2 Status Flag" "Not occurred,Occurred" textline " " setclrfld.word 0x00 1. -0x02 1. 0x02 1. " CEVT1_set/clr ,Capture Event 1 Interrupt Enable" "Not occurred,Occurred" setclrfld.word 0x00 0. 0x00 0. 0x02 0. " INT_set/clr ,Global Interrupt Status Flag" "Not generated,Generated" group.word 0x32++0x01 line.word 0x00 "ECFRC,ECAP Interrupt Forcing Register" eventfld.word 0x00 7. " CTR_CMP ,Force Counter Equal Compare Interrupt" "No effect,Forced" eventfld.word 0x00 6. " CTR_PRD ,Force Counter Equal Period Interrupt" "No effect,Forced" textline " " eventfld.word 0x00 5. " CTROVF ,Force Counter Overflow" "No effect,Forced" eventfld.word 0x00 4. " CEVT4 ,Force Capture Event 4" "No effect,Forced" textline " " eventfld.word 0x00 3. " CEVT3 ,Force Capture Event 3" "No effect,Forced" eventfld.word 0x00 2. " CEVT2 ,Force Capture Event 2" "No effect,Forced" textline " " eventfld.word 0x00 1. " CEVT1 ,Force Capture Event 1" "No effect,Forced" width 0xB tree.end tree "eCAP 5" base ad:0xFCF79700 width 0x8 group.long 0x00++0x17 line.long 0x00 "TSCTR,Time-Stamp Counter Register" line.long 0x04 "CTRPHS,Counter Phase Control Register" line.long 0x08 "CAP1,Capture-1 Register" line.long 0x0C "CAP2,Capture-2 Register" line.long 0x10 "CAP3,Capture-3 Register" line.long 0x14 "CAP4,Capture-4 Register" group.word 0x28++0x01 line.word 0x00 "ECCTL1,ECAP Control Regiser 1" bitfld.word 0x00 14.--15. " FREE/SOFT ,Emulation Control" "Stopped immediately,Run until = 0,Run Free,Run Free" bitfld.word 0x00 9.--13. " PRESCALE ,Event Filter prescale sel" "/1,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32,/34,/36,/38,/40,/42,/44,/46,/48,/50,/52,/54,/56,/58,/60,/62" textline " " bitfld.word 0x00 8. " CAPLDEN ,Enable Loading of CAP1-4 registers on a capture event" "Disabled,Enabled" bitfld.word 0x00 7. " CTRRST4 ,Counter Reset on Capture Event 4" "Not reset,Reset" textline " " bitfld.word 0x00 6. " CAP4POL ,Capture Event 4 Polarity select" "RE,FE" bitfld.word 0x00 5. " CTRRST3 ,Counter Reset on Capture Event 3" "Not reset,Reset" textline " " bitfld.word 0x00 4. " CAP3POL ,Capture Event 3 Polarity select" "RE,FE" bitfld.word 0x00 3. " CTRRST2 ,Counter Reset on Capture Event 2" "Not reset,Reset" textline " " bitfld.word 0x00 2. " CAP2POL ,Capture Event 2 Polarity select" "RE,FE" bitfld.word 0x00 1. " CTRRST1 ,Counter Reset on Capture Event 1" "Not reset,Reset" textline " " bitfld.word 0x00 0. " CAP1POL ,Capture Event 1 Polarity select" "RE,FE" if ((d.w(ad:0xFCF79700+0x2A)&0x200)==0x200) group.word 0x2A++0x01 line.word 0x00 "ECCTL2,ECAP Control Register 2" bitfld.word 0x00 10. " APWMPOL ,APWM output polarity select" "High,Low" bitfld.word 0x00 9. " CAP/APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode" textline " " bitfld.word 0x00 8. " SWSYNC ,Software-forced Counter TSCTR Synchronizing" "No effect,Forced" bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out Select" "Pass through,CTR = PRD,Disabled,Disabled" textline " " bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled" bitfld.word 0x00 4. " TSCTRSTOP ,Time Stamp TSCTR Counter Stop Control" "Stopped,Free-running" textline " " bitfld.word 0x00 3. " RE-ARM ,One-Shot Re-Arming Control" "No effect,One-shot sequence" bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot mode" "Capture Event 1,Capture Event 2,Capture Event 3,Capture Event 4" else group.word 0x2A++0x01 line.word 0x00 "ECCTL2,ECAP Control Register 2" bitfld.word 0x00 9. " CAP/APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode" textline " " bitfld.word 0x00 8. " SWSYNC ,Software-forced Counter TSCTR Synchronizing" "No effect,Forced" bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out Select" "Pass through,CTR = PRD,Disabled,Disabled" textline " " bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled" bitfld.word 0x00 4. " TSCTRSTOP ,Time Stamp TSCTR Counter Stop Control" "Stopped,Free-running" textline " " bitfld.word 0x00 3. " RE-ARM ,One-Shot Re-Arming Control" "No effect,One-shot sequence" bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot mode" "Capture Event 1,Capture Event 2,Capture Event 3,Capture Event 4" textline " " bitfld.word 0x00 0. " CONT/ONESHT ,Continuous or one-shot mode control" "Continuous,One-Shot" endif group.word 0x2E++0x01 line.word 0x00 "ECFLG,ECAP Interrupt Flag Register" setclrfld.word 0x00 7. -0x02 7. 0x02 7. " CTR=CMP_set/clr ,Compare Equal Compare Status Flag" "Not occurred,Occurred" setclrfld.word 0x00 6. -0x02 6. 0x02 6. " CTR=PRD_set/clr ,Counter Equal Period Interrupt Enable" "Not occurred,Occurred" textline " " setclrfld.word 0x00 5. -0x02 5. 0x02 5. " CTROVF_set/clr ,Counter Equal Period Status Flag" "Not occurred,Occurred" setclrfld.word 0x00 4. -0x02 4. 0x02 4. " CEVT4_set/clr ,Counter Overflow Status Flag" "Not occurred,Occurred" textline " " setclrfld.word 0x00 3. -0x02 3. 0x02 3. " CEVT3_set/clr ,Capture Event 4 Status Flag" "Not occurred,Occurred" setclrfld.word 0x00 2. -0x02 2. 0x02 2. " CEVT2_set/clr ,Capture Event 2 Status Flag" "Not occurred,Occurred" textline " " setclrfld.word 0x00 1. -0x02 1. 0x02 1. " CEVT1_set/clr ,Capture Event 1 Interrupt Enable" "Not occurred,Occurred" setclrfld.word 0x00 0. 0x00 0. 0x02 0. " INT_set/clr ,Global Interrupt Status Flag" "Not generated,Generated" group.word 0x32++0x01 line.word 0x00 "ECFRC,ECAP Interrupt Forcing Register" eventfld.word 0x00 7. " CTR_CMP ,Force Counter Equal Compare Interrupt" "No effect,Forced" eventfld.word 0x00 6. " CTR_PRD ,Force Counter Equal Period Interrupt" "No effect,Forced" textline " " eventfld.word 0x00 5. " CTROVF ,Force Counter Overflow" "No effect,Forced" eventfld.word 0x00 4. " CEVT4 ,Force Capture Event 4" "No effect,Forced" textline " " eventfld.word 0x00 3. " CEVT3 ,Force Capture Event 3" "No effect,Forced" eventfld.word 0x00 2. " CEVT2 ,Force Capture Event 2" "No effect,Forced" textline " " eventfld.word 0x00 1. " CEVT1 ,Force Capture Event 1" "No effect,Forced" width 0xB tree.end tree "eCAP 6" base ad:0xFCF79800 width 0x8 group.long 0x00++0x17 line.long 0x00 "TSCTR,Time-Stamp Counter Register" line.long 0x04 "CTRPHS,Counter Phase Control Register" line.long 0x08 "CAP1,Capture-1 Register" line.long 0x0C "CAP2,Capture-2 Register" line.long 0x10 "CAP3,Capture-3 Register" line.long 0x14 "CAP4,Capture-4 Register" group.word 0x28++0x01 line.word 0x00 "ECCTL1,ECAP Control Regiser 1" bitfld.word 0x00 14.--15. " FREE/SOFT ,Emulation Control" "Stopped immediately,Run until = 0,Run Free,Run Free" bitfld.word 0x00 9.--13. " PRESCALE ,Event Filter prescale sel" "/1,/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32,/34,/36,/38,/40,/42,/44,/46,/48,/50,/52,/54,/56,/58,/60,/62" textline " " bitfld.word 0x00 8. " CAPLDEN ,Enable Loading of CAP1-4 registers on a capture event" "Disabled,Enabled" bitfld.word 0x00 7. " CTRRST4 ,Counter Reset on Capture Event 4" "Not reset,Reset" textline " " bitfld.word 0x00 6. " CAP4POL ,Capture Event 4 Polarity select" "RE,FE" bitfld.word 0x00 5. " CTRRST3 ,Counter Reset on Capture Event 3" "Not reset,Reset" textline " " bitfld.word 0x00 4. " CAP3POL ,Capture Event 3 Polarity select" "RE,FE" bitfld.word 0x00 3. " CTRRST2 ,Counter Reset on Capture Event 2" "Not reset,Reset" textline " " bitfld.word 0x00 2. " CAP2POL ,Capture Event 2 Polarity select" "RE,FE" bitfld.word 0x00 1. " CTRRST1 ,Counter Reset on Capture Event 1" "Not reset,Reset" textline " " bitfld.word 0x00 0. " CAP1POL ,Capture Event 1 Polarity select" "RE,FE" if ((d.w(ad:0xFCF79800+0x2A)&0x200)==0x200) group.word 0x2A++0x01 line.word 0x00 "ECCTL2,ECAP Control Register 2" bitfld.word 0x00 10. " APWMPOL ,APWM output polarity select" "High,Low" bitfld.word 0x00 9. " CAP/APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode" textline " " bitfld.word 0x00 8. " SWSYNC ,Software-forced Counter TSCTR Synchronizing" "No effect,Forced" bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out Select" "Pass through,CTR = PRD,Disabled,Disabled" textline " " bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled" bitfld.word 0x00 4. " TSCTRSTOP ,Time Stamp TSCTR Counter Stop Control" "Stopped,Free-running" textline " " bitfld.word 0x00 3. " RE-ARM ,One-Shot Re-Arming Control" "No effect,One-shot sequence" bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot mode" "Capture Event 1,Capture Event 2,Capture Event 3,Capture Event 4" else group.word 0x2A++0x01 line.word 0x00 "ECCTL2,ECAP Control Register 2" bitfld.word 0x00 9. " CAP/APWM ,CAP/APWM operating mode select" "Capture mode,APWM mode" textline " " bitfld.word 0x00 8. " SWSYNC ,Software-forced Counter TSCTR Synchronizing" "No effect,Forced" bitfld.word 0x00 6.--7. " SYNCO_SEL ,Sync-Out Select" "Pass through,CTR = PRD,Disabled,Disabled" textline " " bitfld.word 0x00 5. " SYNCI_EN ,Counter TSCTR Sync-In select mode" "Disabled,Enabled" bitfld.word 0x00 4. " TSCTRSTOP ,Time Stamp TSCTR Counter Stop Control" "Stopped,Free-running" textline " " bitfld.word 0x00 3. " RE-ARM ,One-Shot Re-Arming Control" "No effect,One-shot sequence" bitfld.word 0x00 1.--2. " STOP_WRAP ,Stop value for one-shot mode" "Capture Event 1,Capture Event 2,Capture Event 3,Capture Event 4" textline " " bitfld.word 0x00 0. " CONT/ONESHT ,Continuous or one-shot mode control" "Continuous,One-Shot" endif group.word 0x2E++0x01 line.word 0x00 "ECFLG,ECAP Interrupt Flag Register" setclrfld.word 0x00 7. -0x02 7. 0x02 7. " CTR=CMP_set/clr ,Compare Equal Compare Status Flag" "Not occurred,Occurred" setclrfld.word 0x00 6. -0x02 6. 0x02 6. " CTR=PRD_set/clr ,Counter Equal Period Interrupt Enable" "Not occurred,Occurred" textline " " setclrfld.word 0x00 5. -0x02 5. 0x02 5. " CTROVF_set/clr ,Counter Equal Period Status Flag" "Not occurred,Occurred" setclrfld.word 0x00 4. -0x02 4. 0x02 4. " CEVT4_set/clr ,Counter Overflow Status Flag" "Not occurred,Occurred" textline " " setclrfld.word 0x00 3. -0x02 3. 0x02 3. " CEVT3_set/clr ,Capture Event 4 Status Flag" "Not occurred,Occurred" setclrfld.word 0x00 2. -0x02 2. 0x02 2. " CEVT2_set/clr ,Capture Event 2 Status Flag" "Not occurred,Occurred" textline " " setclrfld.word 0x00 1. -0x02 1. 0x02 1. " CEVT1_set/clr ,Capture Event 1 Interrupt Enable" "Not occurred,Occurred" setclrfld.word 0x00 0. 0x00 0. 0x02 0. " INT_set/clr ,Global Interrupt Status Flag" "Not generated,Generated" group.word 0x32++0x01 line.word 0x00 "ECFRC,ECAP Interrupt Forcing Register" eventfld.word 0x00 7. " CTR_CMP ,Force Counter Equal Compare Interrupt" "No effect,Forced" eventfld.word 0x00 6. " CTR_PRD ,Force Counter Equal Period Interrupt" "No effect,Forced" textline " " eventfld.word 0x00 5. " CTROVF ,Force Counter Overflow" "No effect,Forced" eventfld.word 0x00 4. " CEVT4 ,Force Capture Event 4" "No effect,Forced" textline " " eventfld.word 0x00 3. " CEVT3 ,Force Capture Event 3" "No effect,Forced" eventfld.word 0x00 2. " CEVT2 ,Force Capture Event 2" "No effect,Forced" textline " " eventfld.word 0x00 1. " CEVT1 ,Force Capture Event 1" "No effect,Forced" width 0xB tree.end tree.end endif sif (cpu()=="RM42L432") tree "eQEP (Enhanced QEP)" base ad:0xFFF79900 width 0xA group.long 0x00++0x0F line.long 0x00 "QPOSCNT,eQEP Position Counter Register" line.long 0x04 "QPOSINIT,eQEP Position Counter Initialization Register" line.long 0x08 "QPOSMAX,eQEP Maximum Position Count Register" line.long 0x0C "QPOSCMP,eQEP Position-Compare Register" rgroup.long 0x10++0x0B line.long 0x00 "QPOSILAT,eQEP Index Position Latch Register" line.long 0x04 "QPOSSLAT,eQEP Strobe Position Latch Register" line.long 0x08 "QPOSLAT,eQEP Position Counter Latch Register" group.long 0x1C++0x07 line.long 0x00 "QUTMR,eQEP Unit Timer Register" line.long 0x04 "QUPRD,eQEP Register Unit Period Register" group.word 0x24++0x03 line.word 0x00 "QWDTMR,eQEP Watchdog Timer Register" line.word 0x02 "QWDPRD,eQEP Watchdog Period Register" group.word 0x28++0x07 line.word 0x00 "QDECCTL,eQEP Decoder Control Register" bitfld.word 0x00 14.--15. " QSRC ,Position-counter source selection" "Quadrature count,Direction-count,UP count,DOWN count" bitfld.word 0x00 13. " SOEN ,Sync output-enable" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " SPSEL ,Sync output pin selection" "Index pin,Strobe pin" bitfld.word 0x00 11. " XCR ,External clock rate" "2x resolution,1x resolution" textline " " bitfld.word 0x00 10. " SWAP ,Swap quadrature clock inputs" "Not swapped,Swapped" bitfld.word 0x00 9. " IGATE ,Index pulse gating option" "Disable gating of Index pulse,Gate the index pin with strobe" textline " " bitfld.word 0x00 8. " QAP ,QEPA input polarity" "No effect,Negates QEPA" bitfld.word 0x00 7. " QBP ,QEPB input polarity" "No effect,Negates QEPB" textline " " bitfld.word 0x00 6. " QIP ,QEPI input polarity" "No effect,Negates QEPI" bitfld.word 0x00 5. " QSP ,QEPS input polarity" "No effect,Negates QEPS" line.word 0x02 "QEPCTL,eQEP Control Register" bitfld.word 0x02 14.--15. " FREE/SOFT ,Emulation Control Bits" "Stopped,Continued,Unaffected,Unaffected" bitfld.word 0x02 12.--13. " PCRM ,Position counter reset mode" "Index event,Maximum position,First index event,Unit time event" textline " " bitfld.word 0x02 10.--11. " SEI ,Strobe event initialization of position counter" "Disabled,Disabled,Initialized position,Clockwise Direction" bitfld.word 0x02 8.--9. " IEI ,Index event initialization of position counter" "Disabled,Disabled,Initialized rising edge,Initialized falling edge" textline " " bitfld.word 0x02 7. " SWI ,Software initialization of position counter" "Disabled,Initialized" bitfld.word 0x02 6. " SEL ,Strobe event latch of position counter" "Latched rising edge,Latched rising/faling edge" textline " " bitfld.word 0x02 4.--5. " IEL ,Index event latch of position counter" "Reserved,Rising edge,Faling edge,Software index marker" bitfld.word 0x02 3. " QPEN ,Quadrature position counter enable/software reset" "Reset,Enabled" textline " " bitfld.word 0x02 2. " QCLM ,eQEP capture latch mode" "Position counter read by CPU,Unit time out" bitfld.word 0x02 1. " UTE ,eQEP unit timer enable" "Disabled,Enabled" textline " " bitfld.word 0x02 0. " WDE ,eQEP watchdog enable" "Disabled,Enabled" line.word 0x04 "QCAPCTL,eQEP Capture Control Register" bitfld.word 0x04 15. " CEN ,Enable eQEP capture" "Disabled,Enabled" bitfld.word 0x04 4.--6. " CCPS ,eQEP capture timer clock prescaler" "VCLK/1,VCLK/2,VCLK/4,VCLK/8,VCLK/16,VCLK/32,VCLK/64,VCLK/128" textline " " bitfld.word 0x04 0.--3. " UPPS ,Unit position event prescaler" "QCLK/1,QCLK/2,QCLK/4,QCLK/8,QCLK/16,QCLK/32,QCLK/64,QCLK/128,QCLK/256,QCLK/512,QCLK/1024,QCLK/2048,?..." line.word 0x06 "QPOSCTL,eQEP Position-Compare Control Register" bitfld.word 0x06 15. " PCSHDW ,Position-compare shadow enable" "Disabled,Enabled" bitfld.word 0x06 14. " PCLOAD ,Position-compare shadow load mode" "QPOSCNT = 0,QPOSCNT = QPOSCMP" textline " " bitfld.word 0x06 13. " PCPOL ,Polarity of sync output" "High,Low" bitfld.word 0x06 12. " PCE ,Position-compare enable/disable" "Disabled,Enabled" textline " " hexmask.word 0x06 0.--11. 1. " PCSPW ,Select-position-compare sync output pulse width" group.word 0x32++0x01 line.word 0x00 "QFLG,eQEP Interrupt Flag Register" setclrfld.word 0x00 11. -0x02 11. 0x02 11. " UTO_set/clr ,Unit time out interrupt" "No interrupt,Interrupt" setclrfld.word 0x00 10. -0x02 10. 0x02 10. " IEL_set/clr ,Index event latch interrupt" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 9. -0x02 9. 0x02 9. " SEL_set/clr ,Strobe event latch interrupt" "No interrupt,Interrupt" setclrfld.word 0x00 8. -0x02 8. 0x02 8. " PCM_set/clr ,Position-compare match interrupt" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. -0x02 7. 0x02 7. " PCR_set/clr ,Position-compare ready interrupt" "No interrupt,Interrupt" setclrfld.word 0x00 6. -0x02 6. 0x02 6. " PCO_set/clr ,Position counter overflow interrupt" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 5. -0x02 5. 0x02 5. " PCU_set/clr ,Position counter underflow interrupt" "No interrupt,Interrupt" setclrfld.word 0x00 4. -0x02 4. 0x02 4. " WTO_set/clr ,Watchdog time out interrupt" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 3. -0x02 3. 0x02 3. " QDC_set/clr ,Quadrature direction change interrupt" "No interrupt,Interrupt" setclrfld.word 0x00 2. -0x02 2. 0x02 2. " PHE_set/clr ,Quadrature phase error interrupt" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 1. -0x02 1. 0x02 1. " PCE_set/clr ,Position counter error interrupt" "No interrupt,Interrupt" setclrfld.word 0x00 0. -0x02 0. 0x02 0. " INT_set/clr ,Global interrupt status flag" "No interrupt,Interrupt" group.word 0x36++0x01 line.word 0x00 "QFRC,eQEP Interrupt Force Register" bitfld.word 0x00 11. " UTO ,Force unit time out interrupt" "No effect,Forced" bitfld.word 0x00 10. " IEL ,Force index event latch interrupt" "No effect,Forced" textline " " bitfld.word 0x00 9. " SEL ,Force strobe event latch interrupt" "No effect,Forced" bitfld.word 0x00 8. " PCM ,Force position-compare match interrupt" "No effect,Forced" textline " " bitfld.word 0x00 7. " PCR ,Force position-compare ready interrupt" "No effect,Forced" bitfld.word 0x00 6. " PCO ,Force position counter overflow interrupt" "No effect,Forced" textline " " bitfld.word 0x00 5. " PCU ,Force position counter underflow interrupt" "No effect,Forced" bitfld.word 0x00 4. " WTO ,Force watchdog time out interrupt" "No effect,Forced" textline " " bitfld.word 0x00 3. " QDC ,Force quadrature direction change interrupt" "No effect,Forced" bitfld.word 0x00 2. " PHE ,Force quadrature phase error interrupt" "No effect,Forced" textline " " bitfld.word 0x00 1. " PCE ,Force position counter error interrupt" "No effect,Forced" group.word 0x38++0x01 line.word 0x00 "QEPSTS,eQEP Status Register" eventfld.word 0x00 7. " UPEVNT ,Unit position event flag" "Not detected,Detected" bitfld.word 0x00 6. " FIDF ,Direction on the first index marker" "Counter-clockwise rotation,Clockwise rotation" textline " " bitfld.word 0x00 5. " QDF ,Quadrature direction flag" "Counter-clockwise rotation,Clockwise rotation" bitfld.word 0x00 4. " QDLF ,eQEP direction latch flag" "Counter-clockwise rotation,Clockwise rotation" textline " " eventfld.word 0x00 3. " COEF ,Capture overflow error flag" "Not occurred,Occurred" eventfld.word 0x00 2. " CDEF ,Capture direction error flag" "Not occurred,Occurred" textline " " eventfld.word 0x00 1. " FIMF ,First index marker flag" "Not occurred,Occurred" bitfld.word 0x00 0. " PCEF ,Position counter error flag" "No error,Error" group.word 0x3A++0x07 line.word 0x00 "QCTMR,eQEP Capture Timer Register" line.word 0x02 "QCPRD,eQEP Capture Period Register" line.word 0x04 "QCTMRLAT,eQEP Capture Timer Latch Register" line.word 0x06 "QCPRDLAT,eQEP Capture Period Latch Register" width 0xb tree "eQEP (Enhanced QEP - Mirrored)" base ad:0xFCF79900 width 0xA group.long 0x00++0x0F line.long 0x00 "QPOSCNT,eQEP Position Counter Register" line.long 0x04 "QPOSINIT,eQEP Position Counter Initialization Register" line.long 0x08 "QPOSMAX,eQEP Maximum Position Count Register" line.long 0x0C "QPOSCMP,eQEP Position-Compare Register" rgroup.long 0x10++0x0B line.long 0x00 "QPOSILAT,eQEP Index Position Latch Register" line.long 0x04 "QPOSSLAT,eQEP Strobe Position Latch Register" line.long 0x08 "QPOSLAT,eQEP Position Counter Latch Register" group.long 0x1C++0x07 line.long 0x00 "QUTMR,eQEP Unit Timer Register" line.long 0x04 "QUPRD,eQEP Register Unit Period Register" group.word 0x24++0x03 line.word 0x00 "QWDTMR,eQEP Watchdog Timer Register" line.word 0x02 "QWDPRD,eQEP Watchdog Period Register" group.word 0x28++0x07 line.word 0x00 "QDECCTL,eQEP Decoder Control Register" bitfld.word 0x00 14.--15. " QSRC ,Position-counter source selection" "Quadrature count,Direction-count,UP count,DOWN count" bitfld.word 0x00 13. " SOEN ,Sync output-enable" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " SPSEL ,Sync output pin selection" "Index pin,Strobe pin" bitfld.word 0x00 11. " XCR ,External clock rate" "2x resolution,1x resolution" textline " " bitfld.word 0x00 10. " SWAP ,Swap quadrature clock inputs" "Not swapped,Swapped" bitfld.word 0x00 9. " IGATE ,Index pulse gating option" "Disable gating of Index pulse,Gate the index pin with strobe" textline " " bitfld.word 0x00 8. " QAP ,QEPA input polarity" "No effect,Negates QEPA" bitfld.word 0x00 7. " QBP ,QEPB input polarity" "No effect,Negates QEPB" textline " " bitfld.word 0x00 6. " QIP ,QEPI input polarity" "No effect,Negates QEPI" bitfld.word 0x00 5. " QSP ,QEPS input polarity" "No effect,Negates QEPS" line.word 0x02 "QEPCTL,eQEP Control Register" bitfld.word 0x02 14.--15. " FREE/SOFT ,Emulation Control Bits" "Stopped,Continued,Unaffected,Unaffected" bitfld.word 0x02 12.--13. " PCRM ,Position counter reset mode" "Index event,Maximum position,First index event,Unit time event" textline " " bitfld.word 0x02 10.--11. " SEI ,Strobe event initialization of position counter" "Disabled,Disabled,Initialized position,Clockwise Direction" bitfld.word 0x02 8.--9. " IEI ,Index event initialization of position counter" "Disabled,Disabled,Initialized rising edge,Initialized falling edge" textline " " bitfld.word 0x02 7. " SWI ,Software initialization of position counter" "Disabled,Initialized" bitfld.word 0x02 6. " SEL ,Strobe event latch of position counter" "Latched rising edge,Latched rising/faling edge" textline " " bitfld.word 0x02 4.--5. " IEL ,Index event latch of position counter" "Reserved,Rising edge,Faling edge,Software index marker" bitfld.word 0x02 3. " QPEN ,Quadrature position counter enable/software reset" "Reset,Enabled" textline " " bitfld.word 0x02 2. " QCLM ,eQEP capture latch mode" "Position counter read by CPU,Unit time out" bitfld.word 0x02 1. " UTE ,eQEP unit timer enable" "Disabled,Enabled" textline " " bitfld.word 0x02 0. " WDE ,eQEP watchdog enable" "Disabled,Enabled" line.word 0x04 "QCAPCTL,eQEP Capture Control Register" bitfld.word 0x04 15. " CEN ,Enable eQEP capture" "Disabled,Enabled" bitfld.word 0x04 4.--6. " CCPS ,eQEP capture timer clock prescaler" "VCLK/1,VCLK/2,VCLK/4,VCLK/8,VCLK/16,VCLK/32,VCLK/64,VCLK/128" textline " " bitfld.word 0x04 0.--3. " UPPS ,Unit position event prescaler" "QCLK/1,QCLK/2,QCLK/4,QCLK/8,QCLK/16,QCLK/32,QCLK/64,QCLK/128,QCLK/256,QCLK/512,QCLK/1024,QCLK/2048,?..." line.word 0x06 "QPOSCTL,eQEP Position-Compare Control Register" bitfld.word 0x06 15. " PCSHDW ,Position-compare shadow enable" "Disabled,Enabled" bitfld.word 0x06 14. " PCLOAD ,Position-compare shadow load mode" "QPOSCNT = 0,QPOSCNT = QPOSCMP" textline " " bitfld.word 0x06 13. " PCPOL ,Polarity of sync output" "High,Low" bitfld.word 0x06 12. " PCE ,Position-compare enable/disable" "Disabled,Enabled" textline " " hexmask.word 0x06 0.--11. 1. " PCSPW ,Select-position-compare sync output pulse width" group.word 0x32++0x01 line.word 0x00 "QFLG,eQEP Interrupt Flag Register" setclrfld.word 0x00 11. -0x02 11. 0x02 11. " UTO_set/clr ,Unit time out interrupt" "No interrupt,Interrupt" setclrfld.word 0x00 10. -0x02 10. 0x02 10. " IEL_set/clr ,Index event latch interrupt" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 9. -0x02 9. 0x02 9. " SEL_set/clr ,Strobe event latch interrupt" "No interrupt,Interrupt" setclrfld.word 0x00 8. -0x02 8. 0x02 8. " PCM_set/clr ,Position-compare match interrupt" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. -0x02 7. 0x02 7. " PCR_set/clr ,Position-compare ready interrupt" "No interrupt,Interrupt" setclrfld.word 0x00 6. -0x02 6. 0x02 6. " PCO_set/clr ,Position counter overflow interrupt" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 5. -0x02 5. 0x02 5. " PCU_set/clr ,Position counter underflow interrupt" "No interrupt,Interrupt" setclrfld.word 0x00 4. -0x02 4. 0x02 4. " WTO_set/clr ,Watchdog time out interrupt" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 3. -0x02 3. 0x02 3. " QDC_set/clr ,Quadrature direction change interrupt" "No interrupt,Interrupt" setclrfld.word 0x00 2. -0x02 2. 0x02 2. " PHE_set/clr ,Quadrature phase error interrupt" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 1. -0x02 1. 0x02 1. " PCE_set/clr ,Position counter error interrupt" "No interrupt,Interrupt" setclrfld.word 0x00 0. -0x02 0. 0x02 0. " INT_set/clr ,Global interrupt status flag" "No interrupt,Interrupt" group.word 0x36++0x01 line.word 0x00 "QFRC,eQEP Interrupt Force Register" bitfld.word 0x00 11. " UTO ,Force unit time out interrupt" "No effect,Forced" bitfld.word 0x00 10. " IEL ,Force index event latch interrupt" "No effect,Forced" textline " " bitfld.word 0x00 9. " SEL ,Force strobe event latch interrupt" "No effect,Forced" bitfld.word 0x00 8. " PCM ,Force position-compare match interrupt" "No effect,Forced" textline " " bitfld.word 0x00 7. " PCR ,Force position-compare ready interrupt" "No effect,Forced" bitfld.word 0x00 6. " PCO ,Force position counter overflow interrupt" "No effect,Forced" textline " " bitfld.word 0x00 5. " PCU ,Force position counter underflow interrupt" "No effect,Forced" bitfld.word 0x00 4. " WTO ,Force watchdog time out interrupt" "No effect,Forced" textline " " bitfld.word 0x00 3. " QDC ,Force quadrature direction change interrupt" "No effect,Forced" bitfld.word 0x00 2. " PHE ,Force quadrature phase error interrupt" "No effect,Forced" textline " " bitfld.word 0x00 1. " PCE ,Force position counter error interrupt" "No effect,Forced" group.word 0x38++0x01 line.word 0x00 "QEPSTS,eQEP Status Register" eventfld.word 0x00 7. " UPEVNT ,Unit position event flag" "Not detected,Detected" bitfld.word 0x00 6. " FIDF ,Direction on the first index marker" "Counter-clockwise rotation,Clockwise rotation" textline " " bitfld.word 0x00 5. " QDF ,Quadrature direction flag" "Counter-clockwise rotation,Clockwise rotation" bitfld.word 0x00 4. " QDLF ,eQEP direction latch flag" "Counter-clockwise rotation,Clockwise rotation" textline " " eventfld.word 0x00 3. " COEF ,Capture overflow error flag" "Not occurred,Occurred" eventfld.word 0x00 2. " CDEF ,Capture direction error flag" "Not occurred,Occurred" textline " " eventfld.word 0x00 1. " FIMF ,First index marker flag" "Not occurred,Occurred" bitfld.word 0x00 0. " PCEF ,Position counter error flag" "No error,Error" group.word 0x3A++0x07 line.word 0x00 "QCTMR,eQEP Capture Timer Register" line.word 0x02 "QCPRD,eQEP Capture Period Register" line.word 0x04 "QCTMRLAT,eQEP Capture Timer Latch Register" line.word 0x06 "QCPRDLAT,eQEP Capture Period Latch Register" width 0xb tree.end tree.end endif sif (cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE") tree.open "eQEP (Enhanced QEP)" tree "eQEP 1 (Enhanced QEP 1)" base ad:0xFCF79900 width 0xA group.long 0x00++0x0F line.long 0x00 "QPOSCNT,eQEP Position Counter Register" line.long 0x04 "QPOSINIT,eQEP Position Counter Initialization Register" line.long 0x08 "QPOSMAX,eQEP Maximum Position Count Register" line.long 0x0C "QPOSCMP,eQEP Position-Compare Register" rgroup.long 0x10++0x0B line.long 0x00 "QPOSILAT,eQEP Index Position Latch Register" line.long 0x04 "QPOSSLAT,eQEP Strobe Position Latch Register" line.long 0x08 "QPOSLAT,eQEP Position Counter Latch Register" group.long 0x1C++0x07 line.long 0x00 "QUTMR,eQEP Unit Timer Register" line.long 0x04 "QUPRD,eQEP Register Unit Period Register" group.word 0x24++0x03 line.word 0x00 "QWDTMR,eQEP Watchdog Timer Register" line.word 0x02 "QWDPRD,eQEP Watchdog Period Register" group.word 0x28++0x07 line.word 0x00 "QDECCTL,eQEP Decoder Control Register" bitfld.word 0x00 14.--15. " QSRC ,Position-counter source selection" "Quadrature count,Direction-count,UP count,DOWN count" bitfld.word 0x00 13. " SOEN ,Sync output-enable" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " SPSEL ,Sync output pin selection" "Index pin,Strobe pin" bitfld.word 0x00 11. " XCR ,External clock rate" "2x resolution,1x resolution" textline " " bitfld.word 0x00 10. " SWAP ,Swap quadrature clock inputs" "Not swapped,Swapped" bitfld.word 0x00 9. " IGATE ,Index pulse gating option" "Disable gating of Index pulse,Gate the index pin with strobe" textline " " bitfld.word 0x00 8. " QAP ,QEPA input polarity" "No effect,Negates QEPA" bitfld.word 0x00 7. " QBP ,QEPB input polarity" "No effect,Negates QEPB" textline " " bitfld.word 0x00 6. " QIP ,QEPI input polarity" "No effect,Negates QEPI" bitfld.word 0x00 5. " QSP ,QEPS input polarity" "No effect,Negates QEPS" line.word 0x02 "QEPCTL,eQEP Control Register" bitfld.word 0x02 14.--15. " FREE/SOFT ,Emulation Control Bits" "Stopped,Continued,Unaffected,Unaffected" bitfld.word 0x02 12.--13. " PCRM ,Position counter reset mode" "Index event,Maximum position,First index event,Unit time event" textline " " bitfld.word 0x02 10.--11. " SEI ,Strobe event initialization of position counter" "Disabled,Disabled,Initialized position,Clockwise Direction" bitfld.word 0x02 8.--9. " IEI ,Index event initialization of position counter" "Disabled,Disabled,Initialized rising edge,Initialized falling edge" textline " " bitfld.word 0x02 7. " SWI ,Software initialization of position counter" "Disabled,Initialized" bitfld.word 0x02 6. " SEL ,Strobe event latch of position counter" "Latched rising edge,Latched rising/faling edge" textline " " bitfld.word 0x02 4.--5. " IEL ,Index event latch of position counter" "Reserved,Rising edge,Faling edge,Software index marker" bitfld.word 0x02 3. " QPEN ,Quadrature position counter enable/software reset" "Reset,Enabled" textline " " bitfld.word 0x02 2. " QCLM ,eQEP capture latch mode" "Position counter read by CPU,Unit time out" bitfld.word 0x02 1. " UTE ,eQEP unit timer enable" "Disabled,Enabled" textline " " bitfld.word 0x02 0. " WDE ,eQEP watchdog enable" "Disabled,Enabled" line.word 0x04 "QCAPCTL,eQEP Capture Control Register" bitfld.word 0x04 15. " CEN ,Enable eQEP capture" "Disabled,Enabled" bitfld.word 0x04 4.--6. " CCPS ,eQEP capture timer clock prescaler" "VCLK/1,VCLK/2,VCLK/4,VCLK/8,VCLK/16,VCLK/32,VCLK/64,VCLK/128" textline " " bitfld.word 0x04 0.--3. " UPPS ,Unit position event prescaler" "QCLK/1,QCLK/2,QCLK/4,QCLK/8,QCLK/16,QCLK/32,QCLK/64,QCLK/128,QCLK/256,QCLK/512,QCLK/1024,QCLK/2048,?..." line.word 0x06 "QPOSCTL,eQEP Position-Compare Control Register" bitfld.word 0x06 15. " PCSHDW ,Position-compare shadow enable" "Disabled,Enabled" bitfld.word 0x06 14. " PCLOAD ,Position-compare shadow load mode" "QPOSCNT = 0,QPOSCNT = QPOSCMP" textline " " bitfld.word 0x06 13. " PCPOL ,Polarity of sync output" "High,Low" bitfld.word 0x06 12. " PCE ,Position-compare enable/disable" "Disabled,Enabled" textline " " hexmask.word 0x06 0.--11. 1. " PCSPW ,Select-position-compare sync output pulse width" group.word 0x32++0x01 line.word 0x00 "QFLG,eQEP Interrupt Flag Register" setclrfld.word 0x00 11. -0x02 11. 0x02 11. " UTO_set/clr ,Unit time out interrupt" "No interrupt,Interrupt" setclrfld.word 0x00 10. -0x02 10. 0x02 10. " IEL_set/clr ,Index event latch interrupt" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 9. -0x02 9. 0x02 9. " SEL_set/clr ,Strobe event latch interrupt" "No interrupt,Interrupt" setclrfld.word 0x00 8. -0x02 8. 0x02 8. " PCM_set/clr ,Position-compare match interrupt" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. -0x02 7. 0x02 7. " PCR_set/clr ,Position-compare ready interrupt" "No interrupt,Interrupt" setclrfld.word 0x00 6. -0x02 6. 0x02 6. " PCO_set/clr ,Position counter overflow interrupt" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 5. -0x02 5. 0x02 5. " PCU_set/clr ,Position counter underflow interrupt" "No interrupt,Interrupt" setclrfld.word 0x00 4. -0x02 4. 0x02 4. " WTO_set/clr ,Watchdog time out interrupt" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 3. -0x02 3. 0x02 3. " QDC_set/clr ,Quadrature direction change interrupt" "No interrupt,Interrupt" setclrfld.word 0x00 2. -0x02 2. 0x02 2. " PHE_set/clr ,Quadrature phase error interrupt" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 1. -0x02 1. 0x02 1. " PCE_set/clr ,Position counter error interrupt" "No interrupt,Interrupt" setclrfld.word 0x00 0. -0x02 0. 0x02 0. " INT_set/clr ,Global interrupt status flag" "No interrupt,Interrupt" group.word 0x36++0x01 line.word 0x00 "QFRC,eQEP Interrupt Force Register" bitfld.word 0x00 11. " UTO ,Force unit time out interrupt" "No effect,Forced" bitfld.word 0x00 10. " IEL ,Force index event latch interrupt" "No effect,Forced" textline " " bitfld.word 0x00 9. " SEL ,Force strobe event latch interrupt" "No effect,Forced" bitfld.word 0x00 8. " PCM ,Force position-compare match interrupt" "No effect,Forced" textline " " bitfld.word 0x00 7. " PCR ,Force position-compare ready interrupt" "No effect,Forced" bitfld.word 0x00 6. " PCO ,Force position counter overflow interrupt" "No effect,Forced" textline " " bitfld.word 0x00 5. " PCU ,Force position counter underflow interrupt" "No effect,Forced" bitfld.word 0x00 4. " WTO ,Force watchdog time out interrupt" "No effect,Forced" textline " " bitfld.word 0x00 3. " QDC ,Force quadrature direction change interrupt" "No effect,Forced" bitfld.word 0x00 2. " PHE ,Force quadrature phase error interrupt" "No effect,Forced" textline " " bitfld.word 0x00 1. " PCE ,Force position counter error interrupt" "No effect,Forced" group.word 0x38++0x01 line.word 0x00 "QEPSTS,eQEP Status Register" eventfld.word 0x00 7. " UPEVNT ,Unit position event flag" "Not detected,Detected" bitfld.word 0x00 6. " FIDF ,Direction on the first index marker" "Counter-clockwise rotation,Clockwise rotation" textline " " bitfld.word 0x00 5. " QDF ,Quadrature direction flag" "Counter-clockwise rotation,Clockwise rotation" bitfld.word 0x00 4. " QDLF ,eQEP direction latch flag" "Counter-clockwise rotation,Clockwise rotation" textline " " eventfld.word 0x00 3. " COEF ,Capture overflow error flag" "Not occurred,Occurred" eventfld.word 0x00 2. " CDEF ,Capture direction error flag" "Not occurred,Occurred" textline " " eventfld.word 0x00 1. " FIMF ,First index marker flag" "Not occurred,Occurred" bitfld.word 0x00 0. " PCEF ,Position counter error flag" "No error,Error" group.word 0x3A++0x07 line.word 0x00 "QCTMR,eQEP Capture Timer Register" line.word 0x02 "QCPRD,eQEP Capture Period Register" line.word 0x04 "QCTMRLAT,eQEP Capture Timer Latch Register" line.word 0x06 "QCPRDLAT,eQEP Capture Period Latch Register" width 0xb tree.end tree "eQEP 2 (Enhanced QEP 2)" base ad:0xFCF79A00 width 0xA group.long 0x00++0x0F line.long 0x00 "QPOSCNT,eQEP Position Counter Register" line.long 0x04 "QPOSINIT,eQEP Position Counter Initialization Register" line.long 0x08 "QPOSMAX,eQEP Maximum Position Count Register" line.long 0x0C "QPOSCMP,eQEP Position-Compare Register" rgroup.long 0x10++0x0B line.long 0x00 "QPOSILAT,eQEP Index Position Latch Register" line.long 0x04 "QPOSSLAT,eQEP Strobe Position Latch Register" line.long 0x08 "QPOSLAT,eQEP Position Counter Latch Register" group.long 0x1C++0x07 line.long 0x00 "QUTMR,eQEP Unit Timer Register" line.long 0x04 "QUPRD,eQEP Register Unit Period Register" group.word 0x24++0x03 line.word 0x00 "QWDTMR,eQEP Watchdog Timer Register" line.word 0x02 "QWDPRD,eQEP Watchdog Period Register" group.word 0x28++0x07 line.word 0x00 "QDECCTL,eQEP Decoder Control Register" bitfld.word 0x00 14.--15. " QSRC ,Position-counter source selection" "Quadrature count,Direction-count,UP count,DOWN count" bitfld.word 0x00 13. " SOEN ,Sync output-enable" "Disabled,Enabled" textline " " bitfld.word 0x00 12. " SPSEL ,Sync output pin selection" "Index pin,Strobe pin" bitfld.word 0x00 11. " XCR ,External clock rate" "2x resolution,1x resolution" textline " " bitfld.word 0x00 10. " SWAP ,Swap quadrature clock inputs" "Not swapped,Swapped" bitfld.word 0x00 9. " IGATE ,Index pulse gating option" "Disable gating of Index pulse,Gate the index pin with strobe" textline " " bitfld.word 0x00 8. " QAP ,QEPA input polarity" "No effect,Negates QEPA" bitfld.word 0x00 7. " QBP ,QEPB input polarity" "No effect,Negates QEPB" textline " " bitfld.word 0x00 6. " QIP ,QEPI input polarity" "No effect,Negates QEPI" bitfld.word 0x00 5. " QSP ,QEPS input polarity" "No effect,Negates QEPS" line.word 0x02 "QEPCTL,eQEP Control Register" bitfld.word 0x02 14.--15. " FREE/SOFT ,Emulation Control Bits" "Stopped,Continued,Unaffected,Unaffected" bitfld.word 0x02 12.--13. " PCRM ,Position counter reset mode" "Index event,Maximum position,First index event,Unit time event" textline " " bitfld.word 0x02 10.--11. " SEI ,Strobe event initialization of position counter" "Disabled,Disabled,Initialized position,Clockwise Direction" bitfld.word 0x02 8.--9. " IEI ,Index event initialization of position counter" "Disabled,Disabled,Initialized rising edge,Initialized falling edge" textline " " bitfld.word 0x02 7. " SWI ,Software initialization of position counter" "Disabled,Initialized" bitfld.word 0x02 6. " SEL ,Strobe event latch of position counter" "Latched rising edge,Latched rising/faling edge" textline " " bitfld.word 0x02 4.--5. " IEL ,Index event latch of position counter" "Reserved,Rising edge,Faling edge,Software index marker" bitfld.word 0x02 3. " QPEN ,Quadrature position counter enable/software reset" "Reset,Enabled" textline " " bitfld.word 0x02 2. " QCLM ,eQEP capture latch mode" "Position counter read by CPU,Unit time out" bitfld.word 0x02 1. " UTE ,eQEP unit timer enable" "Disabled,Enabled" textline " " bitfld.word 0x02 0. " WDE ,eQEP watchdog enable" "Disabled,Enabled" line.word 0x04 "QCAPCTL,eQEP Capture Control Register" bitfld.word 0x04 15. " CEN ,Enable eQEP capture" "Disabled,Enabled" bitfld.word 0x04 4.--6. " CCPS ,eQEP capture timer clock prescaler" "VCLK/1,VCLK/2,VCLK/4,VCLK/8,VCLK/16,VCLK/32,VCLK/64,VCLK/128" textline " " bitfld.word 0x04 0.--3. " UPPS ,Unit position event prescaler" "QCLK/1,QCLK/2,QCLK/4,QCLK/8,QCLK/16,QCLK/32,QCLK/64,QCLK/128,QCLK/256,QCLK/512,QCLK/1024,QCLK/2048,?..." line.word 0x06 "QPOSCTL,eQEP Position-Compare Control Register" bitfld.word 0x06 15. " PCSHDW ,Position-compare shadow enable" "Disabled,Enabled" bitfld.word 0x06 14. " PCLOAD ,Position-compare shadow load mode" "QPOSCNT = 0,QPOSCNT = QPOSCMP" textline " " bitfld.word 0x06 13. " PCPOL ,Polarity of sync output" "High,Low" bitfld.word 0x06 12. " PCE ,Position-compare enable/disable" "Disabled,Enabled" textline " " hexmask.word 0x06 0.--11. 1. " PCSPW ,Select-position-compare sync output pulse width" group.word 0x32++0x01 line.word 0x00 "QFLG,eQEP Interrupt Flag Register" setclrfld.word 0x00 11. -0x02 11. 0x02 11. " UTO_set/clr ,Unit time out interrupt" "No interrupt,Interrupt" setclrfld.word 0x00 10. -0x02 10. 0x02 10. " IEL_set/clr ,Index event latch interrupt" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 9. -0x02 9. 0x02 9. " SEL_set/clr ,Strobe event latch interrupt" "No interrupt,Interrupt" setclrfld.word 0x00 8. -0x02 8. 0x02 8. " PCM_set/clr ,Position-compare match interrupt" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 7. -0x02 7. 0x02 7. " PCR_set/clr ,Position-compare ready interrupt" "No interrupt,Interrupt" setclrfld.word 0x00 6. -0x02 6. 0x02 6. " PCO_set/clr ,Position counter overflow interrupt" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 5. -0x02 5. 0x02 5. " PCU_set/clr ,Position counter underflow interrupt" "No interrupt,Interrupt" setclrfld.word 0x00 4. -0x02 4. 0x02 4. " WTO_set/clr ,Watchdog time out interrupt" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 3. -0x02 3. 0x02 3. " QDC_set/clr ,Quadrature direction change interrupt" "No interrupt,Interrupt" setclrfld.word 0x00 2. -0x02 2. 0x02 2. " PHE_set/clr ,Quadrature phase error interrupt" "No interrupt,Interrupt" textline " " setclrfld.word 0x00 1. -0x02 1. 0x02 1. " PCE_set/clr ,Position counter error interrupt" "No interrupt,Interrupt" setclrfld.word 0x00 0. -0x02 0. 0x02 0. " INT_set/clr ,Global interrupt status flag" "No interrupt,Interrupt" group.word 0x36++0x01 line.word 0x00 "QFRC,eQEP Interrupt Force Register" bitfld.word 0x00 11. " UTO ,Force unit time out interrupt" "No effect,Forced" bitfld.word 0x00 10. " IEL ,Force index event latch interrupt" "No effect,Forced" textline " " bitfld.word 0x00 9. " SEL ,Force strobe event latch interrupt" "No effect,Forced" bitfld.word 0x00 8. " PCM ,Force position-compare match interrupt" "No effect,Forced" textline " " bitfld.word 0x00 7. " PCR ,Force position-compare ready interrupt" "No effect,Forced" bitfld.word 0x00 6. " PCO ,Force position counter overflow interrupt" "No effect,Forced" textline " " bitfld.word 0x00 5. " PCU ,Force position counter underflow interrupt" "No effect,Forced" bitfld.word 0x00 4. " WTO ,Force watchdog time out interrupt" "No effect,Forced" textline " " bitfld.word 0x00 3. " QDC ,Force quadrature direction change interrupt" "No effect,Forced" bitfld.word 0x00 2. " PHE ,Force quadrature phase error interrupt" "No effect,Forced" textline " " bitfld.word 0x00 1. " PCE ,Force position counter error interrupt" "No effect,Forced" group.word 0x38++0x01 line.word 0x00 "QEPSTS,eQEP Status Register" eventfld.word 0x00 7. " UPEVNT ,Unit position event flag" "Not detected,Detected" bitfld.word 0x00 6. " FIDF ,Direction on the first index marker" "Counter-clockwise rotation,Clockwise rotation" textline " " bitfld.word 0x00 5. " QDF ,Quadrature direction flag" "Counter-clockwise rotation,Clockwise rotation" bitfld.word 0x00 4. " QDLF ,eQEP direction latch flag" "Counter-clockwise rotation,Clockwise rotation" textline " " eventfld.word 0x00 3. " COEF ,Capture overflow error flag" "Not occurred,Occurred" eventfld.word 0x00 2. " CDEF ,Capture direction error flag" "Not occurred,Occurred" textline " " eventfld.word 0x00 1. " FIMF ,First index marker flag" "Not occurred,Occurred" bitfld.word 0x00 0. " PCEF ,Position counter error flag" "No error,Error" group.word 0x3A++0x07 line.word 0x00 "QCTMR,eQEP Capture Timer Register" line.word 0x02 "QCPRD,eQEP Capture Period Register" line.word 0x04 "QCTMRLAT,eQEP Capture Timer Latch Register" line.word 0x06 "QCPRDLAT,eQEP Capture Period Latch Register" width 0xb tree.end tree.end endif tree "ADC (Analog to Digital Converter)" sif (cpu()=="RM42L432") tree "MIBADC" base ad:0xFFF7C000 width 12. group.long 0x00++0x03 line.long 0x00 "ADRSTCR,ADC Reset Control Register" bitfld.long 0x00 0. " RESET ,ADC reset" "No reset,Reset" group.long 0x04++0x03 line.long 0x00 "ADOPMODECR,ADC Operating Mode Control Register" bitfld.long 0x00 31. " 10/12BIT ,Resolution of the ADC core select" "10-bit,12-bit" bitfld.long 0x00 24. " COS ,ADCLK halt/continue when the emulation system enters suspend mode" "Halted,Continue" textline " " bitfld.long 0x00 17.--20. " CHNTESTEN ,Enable the input channels impedance measurement mode" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" bitfld.long 0x00 16. " RAMTESTEN ,Enable the ADC results RAM test mode" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " POWERDOWN ,ADC core power down" "Not powered down,Powered down" bitfld.long 0x00 4. " IDLEPWRDN ,ADC power down when idle" "Not powered down,Powered down" textline " " bitfld.long 0x00 0. " ADCEN ,ADC conversions enable" "Disabled,Enabled" group.long 0x08++0x03 line.long 0x00 "CLOCKCR,Clock Prescaler" bitfld.long 0x00 0.--4. " PS[4:0] ,ADC clock prescaler" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles" sif (cpuis("RM48L950*")||cpu()=="RM57L843-ZWT") if (((d.l(ad:0xFFF7C000+0x0C))&0x1020001)==0x1000000) group.long 0x0C++0x03 line.long 0x00 "ADCALCR,Calibration Conversion Register" bitfld.long 0x00 24. " SELF_TEST ,Self-Test enable" "Disabled,Enabled" bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started" textline " " bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full" bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " HILO ,Test and reference source selection" "(AD_REFHI*R1+AD_REFLO*R2)/(R1+R2),(AD_REFLO*R1+AD_REFHI*R2)/(R1+R2)" elif (((d.l(ad:0xFFF7C000+0x0C))&0x1020001)==0x01) group.long 0x0C++0x03 line.long 0x00 "ADCALCR,Calibration Conversion Register" bitfld.long 0x00 24. " SELF_TEST ,Self-Test enable" "Disabled,Enabled" bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started" textline " " bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full" bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " HILO ,Test and reference source selection" "(Ad_reflo via R1)||(R2 to vin),(Ad_refhi via R1)||(R2 to vin)" elif (((d.l(ad:0xFFF7C000+0x0C))&0x1020001)==0x1020000) group.long 0x0C++0x03 line.long 0x00 "ADCALCR,Calibration Conversion Register" bitfld.long 0x00 24. " SELF_TEST ,Self-Test enable" "Disabled,Enabled" bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started" textline " " bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full" bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " HILO ,Test and reference source selection" "AD_REFLO,AD_REFHI" elif (((d.l(ad:0xFFF7C000+0x0C))&0x1020001)==0x20001) group.long 0x0C++0x03 line.long 0x00 "ADCALCR,Calibration Conversion Register" bitfld.long 0x00 24. " SELF_TEST ,Self-Test enable" "Disabled,Enabled" bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started" textline " " bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full" bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " HILO ,Test and reference source selection" "(Ad_reflo via R1)||(R2 to vin),(Ad_refhi via R1)||(R2 to vin)" else group.long 0x0C++0x03 line.long 0x00 "ADCALCR,Calibration Conversion Register" bitfld.long 0x00 24. " SELF_TEST ,Self-Test enable" "Disabled,Enabled" bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started" textline " " bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full" bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled" endif else if (((d.l(ad:0xFFF7C000+0x0C))&0x1000201)==0x01) group.long 0x0C++0x03 line.long 0x00 "ADCALCR,Calibration Conversion Register" bitfld.long 0x00 24. " SELF_TEST ,Self-Test enable" "Disabled,Enabled" bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started" textline " " bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full" textline " " bitfld.long 0x00 8. " HILO ,Test and reference source selection" "(AD_REFHI*R1+AD_REFLO*R2)/(R1+R2),(AD_REFLO*R1+AD_REFHI*R2)/(R1+R2)" textline " " bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled" elif (((d.l(ad:0xFFF7C000+0x0C))&0x1000201)==0x1000000) group.long 0x0C++0x03 line.long 0x00 "ADCALCR,Calibration Conversion Register" bitfld.long 0x00 24. " SELF_TEST ,Self-Test enable" "Disabled,Enabled" bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started" textline " " bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full" textline " " bitfld.long 0x00 8. " HILO ,Test and reference source selection" "(Ad_reflo via R1)||(R2 to vin),(Ad_refhi via R1)||(R2 to vin)" textline " " bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled" elif (((d.l(ad:0xFFF7C000+0x0C))&0x1000201)==0x201) group.long 0x0C++0x03 line.long 0x00 "ADCALCR,Calibration Conversion Register" bitfld.long 0x00 24. " SELF_TEST ,Self-Test enable" "Disabled,Enabled" bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started" textline " " bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full" textline " " bitfld.long 0x00 8. " HILO ,Test and reference source selection" "AD_REFLO,AD_REFHI" textline " " bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled" elif (((d.l(ad:0xFFF7C000+0x0C))&0x1000201)==0x1000200) group.long 0x0C++0x03 line.long 0x00 "ADCALCR,Calibration Conversion Register" bitfld.long 0x00 24. " SELF_TEST ,Self-Test enable" "Disabled,Enabled" bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started" textline " " bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full" textline " " bitfld.long 0x00 8. " HILO ,Test and reference source selection" "(Ad_reflo via R1)||(R2 to vin),(Ad_refhi via R1)||(R2 to vin)" textline " " bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled" else group.long 0x0C++0x03 line.long 0x00 "ADCALCR,Calibration Conversion Register" bitfld.long 0x00 24. " SELF_TEST ,Self-Test enable" "Disabled,Enabled" bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started" textline " " bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full" textline " " textline " " bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled" endif endif group.long 0x10++0x03 line.long 0x00 "ADEVMODECR,EV MODE Control Register" bitfld.long 0x00 16. " NORESETONCHNSEL ,No event group results memory reset on new channel select" "Reset,No reset" bitfld.long 0x00 8.--9. " EV_DATA_FMT ,Event group (Read) data format" "12 bit,10 bit,8 bit,?..." textline " " bitfld.long 0x00 5. " EV_CHID ,Channel ID mode for the event group" "Forced to 0,ID of A/D channel" bitfld.long 0x00 4. " OVR_EV_RAM_IGN ,Overrun event group RAM ignore" "Not ignored,Ignored" textline " " bitfld.long 0x00 2. " EV8BIT ,Event group 8-bit result mode" "10-bit,8-bit" bitfld.long 0x00 1. " EV_MODE ,Event mode" "Single,Continuous" textline " " bitfld.long 0x00 0. " FRZ_EV ,Freeze conversion event group" "Completed,Frozen" group.long 0x14++0x03 line.long 0x00 "ADG1MODECR,G1 MODE Control Register" bitfld.long 0x00 16. " NORESETONCHNSEL ,No group1 results memory reset on new channel select" "Reset,No reset" bitfld.long 0x00 8.--9. " G1_DATA_FMT ,Group1 (Read) data format" "12 bit,10 bit,8 bit,?..." textline " " bitfld.long 0x00 5. " G1_CHID ,Channel ID mode for the group 1" "Forced to 0,ID of A/D channel" bitfld.long 0x00 4. " OVR_G1_RAM_IGN ,Overrun group 1 RAM ignore" "Not ignored,Ignored" textline " " bitfld.long 0x00 3. " G1_HW_TRIG ,Group 1 hardware triggered" "Software,Hardware" bitfld.long 0x00 2. " G1_8BIT ,Group1 8-bit result mode" "10-bit,8-bit" textline " " bitfld.long 0x00 1. " G1_MODE ,Group 1 mode" "Single,Continuous" bitfld.long 0x00 0. " FRZ_G1 ,Freeze conversion group 1" "Completed,Frozen" group.long 0x18++0x03 line.long 0x00 "ADG2MODECR,G2 MODE Control Register" bitfld.long 0x00 16. " NORESETONCHNSEL ,No group2 results memory reset on new channel select" "Reset,No reset" bitfld.long 0x00 8.--9. " G2_DATA_FMT ,Group2 (Read) data format" "12 bit,10 bit,8 bit,?..." textline " " bitfld.long 0x00 5. " G2_CHID ,Channel ID mode for the group 2" "Forced to 0,ID of A/D channel" bitfld.long 0x00 4. " OVR_G2_RAM_IGN ,Overrun group 2 RAM ignore" "Not ignored,Ignored" textline " " bitfld.long 0x00 3. " G2_HW_TRIG ,Group 2 hardware triggered" "Software,Hardware" bitfld.long 0x00 2. " G2_8BIT ,Group2 8-bit result mode" "10-bit,8-bit" textline " " bitfld.long 0x00 1. " G2_MODE ,Group 2 mode" "Single,Continuous" bitfld.long 0x00 0. " FRZ_G2 ,Freeze conversion group 2" "Completed,Frozen" group.long 0x1C++0x03 line.long 0x00 "ADEVSRC,Event Group Trigger Source Select" bitfld.long 0x00 4. " EV_EDG_BOTH ,Event group trigger on both edges" "EV_EDGE_SEL bit,Rising or falling" textline " " bitfld.long 0x00 3. " EV_EDG_SEL ,Event group trigger edge polarity select" "High/low,Low/high" sif (cpu()=="RM42L432") bitfld.long 0x00 0.--2. " EVSRC[2:0] ,Event group trigger source select" "ADEVT,N2HET1[8],N2HET1[10],RTI compare 0,N2HET1[12],N2HET1[14],N2HET1[17],N2HET1[19]" else bitfld.long 0x00 0.--2. " EVSRC[2:0] ,Event group trigger source select" "AD2EVT,N2HET1[8]/[5],N2HET1[10]/[27],RTI compare 0,N2HET1[12]/[17],N2HET1[14]/[19],GIOB[0]/N2HET1[11],GIOB[1]/N2HET2[13]" endif group.long 0x20++0x03 line.long 0x00 "ADG1SRC,Group 1 Trigger Source Select" bitfld.long 0x00 4. " G1_EDG_BOTH ,Group1 trigger on both edges" "G1_EDG_SEL bit,Rising or falling" textline " " bitfld.long 0x00 3. " G1_EDG_SEL ,ADC group 1 trigger edge select" "High/low,Low/high" sif (cpu()=="RM42L432") bitfld.long 0x00 0.--2. " G1SRC[2:0] ,Group 1 trigger source select" "ADEVT,N2HET1[8],N2HET1[10],RTI compare 0,N2HET1[12],N2HET1[14],N2HET1[17],N2HET2[19]" else bitfld.long 0x00 0.--2. " G1SRC[2:0] ,Group 1 trigger source select" "AD2EVT,N2HET1[8]/[5],N2HET1[10]/[27],RTI compare 0,N2HET1[12]/[17],N2HET1[14]/[19],GIOB[0]/N2HET1[11],GIOB[1]/N2HET2[13]" endif group.long 0x24++0x03 line.long 0x00 "ADG2SRC,Group 2 Trigger Source Select" bitfld.long 0x00 4. " G2_EDG_BOTH ,Group2 trigger on both edges" "G2_EDG_SEL bit,Rising or falling" textline " " bitfld.long 0x00 3. " G2_EDG_SEL ,ADC group 2 trigger edge select" "High/low,Low/high" sif (cpu()=="RM42L432") bitfld.long 0x00 0.--2. " G2SRC[2:0] ,Group 2 trigger source select" "ADEVT,N2HET1[8],N2HET1[10],RTI compare 0,N2HET1[12],N2HET1[14],N2HET1[17],N2HET2[19]" else bitfld.long 0x00 0.--2. " G2SRC[2:0] ,Group 2 trigger source select" "AD2EVT,N2HET1[8]/[5],N2HET1[10]/[27],RTI compare 0,N2HET1[12]/[17],N2HET1[14]/[19],GIOB[0]/N2HET1[11],GIOB[1]/N2HET2[13]" endif group.long 0x28++0x03 line.long 0x00 "ADEVINTENA,Event Group Interrupt Enable" bitfld.long 0x00 3. " EV_END_INT_EN ,Event group conversion end interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " EV_OVR_INT_EN ,Event group memory overrun interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " EV_THR_INT_EN ,Event group memory threshold interrupt enable" "Disabled,Enabled" group.long 0x2C++0x03 line.long 0x00 "ADG1INTENA,Group 1 Interrupt Enable" bitfld.long 0x00 3. " G1_END_INT_EN ,Event group conversion end interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " G1_OVR_INT_EN ,Group 1 memory overrun interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " G1_THR_INT_EN ,Group 1 memory threshold interrupt enable" "Disabled,Enabled" group.long 0x30++0x03 line.long 0x00 "ADG2INTENA,Group 2 Interrupt Enable" bitfld.long 0x00 3. " G2_END_INT_EN ,Event group conversion end interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " G2_OVR_INT_EN ,Group 2 memory overrun interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " G2_THR_INT_EN ,Group 2 memory threshold interrupt enable" "Disabled,Enabled" hgroup.long 0x34++0x0B hide.long 0x00 "ADEVINTFLG,Event Group Interrupt Flag" in hide.long 0x04 "ADG1INTFLG,Group 1 Interrupt Flag" in hide.long 0x08 "ADG2INTFLG,Group 2 Interrupt Flag" in group.long 0x40++0x03 line.long 0x00 "ADEVINTCR,Event Group Interrupt Threshold Counter" hexmask.long.byte 0x00 9.--15. 1. " SIGN_EXTENSION ,Sign extension" hexmask.long.word 0x00 0.--8. 1. " EVTHR[8:0] ,Event group interrupt threshold counter" group.long 0x44++0x03 line.long 0x00 "ADG1INTCR,Group 1 Interrupt Threshold Counter" hexmask.long.byte 0x00 9.--15. 1. " SIGN_EXTENSION ,Sign extension" hexmask.long.word 0x00 0.--8. 1. " G1THR[8:0] ,Group 1 interrupt threshold counter" group.long 0x48++0x03 line.long 0x00 "ADG2INTCR,Group 2 Interrupt Threshold Counter" hexmask.long.byte 0x00 9.--15. 1. " SIGN_EXTENSION ,Sign extension" hexmask.long.word 0x00 0.--8. 1. " G2THR[8:0] ,Group 2 interrupt threshold counter" group.long 0x4C++0x03 line.long 0x00 "ADEVDMACR,Event Group DMA Control Register" hexmask.long.word 0x00 16.--24. 1. " EVBLOCKS[8:0] ,Number of event group memory buffers to be transferred" bitfld.long 0x00 3. " DMA_EV_END ,Event group conversion end DMA transfer enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " EV_BLK_XFER ,Event group block DMA transfer enable" "Disabled,Enabled" bitfld.long 0x00 0. " EV_DMA_EN ,Event group DMA transfer enable" "Disabled,Enabled" group.long 0x50++0x03 line.long 0x00 "ADG1DMACR,Group 1 DMA Control Register" hexmask.long.word 0x00 16.--24. 1. " G1BLOCKS[8:0] ,Number of group 1 memory buffers to be transferred" bitfld.long 0x00 3. " DMA_G1_END ,Group1 conversion end DMA transfer enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " G1_BLK_XFER ,Group 1 block DMA transfer enable" "Disabled,Enabled" bitfld.long 0x00 0. " G1_DMA_EN ,Group 1 DMA transfer enable" "Disabled,Enabled" group.long 0x54++0x03 line.long 0x00 "ADG2DMACR,Group 2 DMA Control Register" hexmask.long.word 0x00 16.--24. 1. " G2BLOCKS[8:0] ,Number of group 2 memory buffers to be transferred" bitfld.long 0x00 3. " DMA_G2_END ,Group2 conversion end DMA transfer enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " G2_BLK_XFER ,Group 2 block DMA transfer enable" "Disabled,Enabled" bitfld.long 0x00 0. " G2_DMA_EN ,Group 2 DMA transfer enable" "Disabled,Enabled" group.long 0x58++0x03 line.long 0x00 "ADBNDCR,Buffer Boundary Control Register" hexmask.long.word 0x00 16.--24. 1. " BNDA[8:0] ,Buffer boundary A" hexmask.long.word 0x00 0.--8. 1. " BNDB[8:0] ,Buffer boundary B" group.long 0x5C++0x03 line.long 0x00 "ADBNDEND,Buffer End Boundary" bitfld.long 0x00 16. " BUF_INIT_ACTIVE ,Indicates the status of the ADC RAM intialization process" "Not initialized,Initialized" bitfld.long 0x00 0.--2. " BNDEND[2:0] ,Buffer end boundary" "16 words,32 words,64 words,128 words,192 words,256 words,512 words,1024 words" width 10. tree "ADC Sample Control Registers" group.long 0x60++0x03 line.long 0x00 "ADEVSAMP,Event Group Sampling Time Configuration" hexmask.long.word 0x00 0.--11. 1. " EVACQ[11:0] ,Event group acquisition time" group.long 0x64++0x03 line.long 0x00 "ADG1SAMP,Group1 Sampling Time Configuration" hexmask.long.word 0x00 0.--11. 1. " G1ACQ[11:0] ,Group 1 acquisition time" group.long 0x68++0x03 line.long 0x00 "ADG2SAMP,Group2 Sampling Time Configuration" hexmask.long.word 0x00 0.--11. 1. " G2ACQ[11:0] ,Group 2 acquisition time" tree.end width 8. tree "ADC Status Registers" group.long 0x6C++0x03 line.long 0x00 "ADEVSR,Event Group Status Register" bitfld.long 0x00 3. " EV_MEM_EMPTY ,Event group memory empty" "Not empty,Empty" bitfld.long 0x00 2. " EV_BUSY ,Event group Conversion-Busy flag" "Not active,Busy" bitfld.long 0x00 1. " EV_STOP ,Event group conversion stopped flag" "Not frozen,Frozen" textline " " eventfld.long 0x00 0. " EV_END ,Event Conversion-Ended flag R/W" "Not completed,Completed" group.long 0x70++0x03 line.long 0x00 "ADG1SR,Group 1 Status Register" bitfld.long 0x00 3. " G1_MEM_EMPTY ,Group 1 memory empty" "Not empty,Empty" bitfld.long 0x00 2. " G1_BUSY ,Group 1 Conversion-Busy flag" "Not active,Busy" bitfld.long 0x00 1. " G1_STOP ,Group 1 conversion stopped flag" "Not frozen,Frozen" textline " " eventfld.long 0x00 0. " G1_END ,Group 1 Conversion-Ended flag" "Not completed,Completed" group.long 0x74++0x03 line.long 0x00 "ADG2SR,Group 2 Status Register" bitfld.long 0x00 3. " G2_MEM_EMPTY ,Group 2 memory empty" "Not empty,Empty" bitfld.long 0x00 2. " G2_BUSY ,Group 2 Conversion-Busy flag" "Not active,Busy" bitfld.long 0x00 1. " G2_STOP ,Group 2 conversion stopped flag" "Not frozen,Frozen" textline " " eventfld.long 0x00 0. " G2_END ,Group 2 conversion-ended flag" "Not completed,Completed" tree.end width 9. tree "ADC Selection Control Registers" sif cpu()=="RM57L843-ZWT" group.long 0x78++0x03 line.long 0x00 "ADEVSEL,Event Group Select Register" bitfld.long 0x00 24. " EVCHNSEL[24] ,A/D event channel 24 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 23. " EVCHNSEL[23] ,A/D event channel 23 selection bit" "Not converted,Converted" bitfld.long 0x00 22. " EVCHNSEL[22] ,A/D event channel 22 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 21. " EVCHNSEL[21] ,A/D event channel 21 selection bit" "Not converted,Converted" bitfld.long 0x00 20. " EVCHNSEL[20] ,A/D event channel 20 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 19. " EVCHNSEL[19] ,A/D event channel 19 selection bit" "Not converted,Converted" bitfld.long 0x00 18. " EVCHNSEL[18] ,A/D event channel 18 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 17. " EVCHNSEL[17] ,A/D event channel 17 selection bit" "Not converted,Converted" bitfld.long 0x00 16. " EVCHNSEL[16] ,A/D event channel 16 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 15. " EVCHNSEL[15] ,A/D event channel 15 selection bit" "Not converted,Converted" bitfld.long 0x00 14. " EVCHNSEL[14] ,A/D event channel 14 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 13. " EVCHNSEL[13] ,A/D event channel 13 selection bit" "Not converted,Converted" bitfld.long 0x00 12. " EVCHNSEL[12] ,A/D event channel 12 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 11. " EVCHNSEL[11] ,A/D event channel 11 selection bit" "Not converted,Converted" bitfld.long 0x00 10. " EVCHNSEL[10] ,A/D event channel 10 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 9. " EVCHNSEL[9] ,A/D event channel 9 selection bit" "Not converted,Converted" bitfld.long 0x00 8. " EVCHNSEL[8] ,A/D event channel 8 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 7. " EVCHNSEL[7] ,A/D event channel 7 selection bit" "Not converted,Converted" bitfld.long 0x00 6. " EVCHNSEL[6] ,A/D event channel 6 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 5. " EVCHNSEL[5] ,A/D event channel 5 selection bit" "Not converted,Converted" bitfld.long 0x00 4. " EVCHNSEL[4] ,A/D event channel 4 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 3. " EVCHNSEL[3] ,A/D event channel 3 selection bit" "Not converted,Converted" bitfld.long 0x00 2. " EVCHNSEL[2] ,A/D event channel 2 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 1. " EVCHNSEL[1] ,A/D event channel 1 selection bit" "Not converted,Converted" bitfld.long 0x00 0. " EVCHNSEL[0] ,A/D event channel 0 selection bit" "Not converted,Converted" group.long 0x7C++0x03 line.long 0x00 "ADG1SEL,Group 1 Select Register" bitfld.long 0x00 24. " G1CHNSEL[24] ,A/D channel 24 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 23. " G1CHNSEL[23] ,A/D channel 23 enable bit" "Not converted,Converted" bitfld.long 0x00 22. " G1CHNSEL[22] ,A/D channel 22 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 21. " G1CHNSEL[21] ,A/D channel 21 enable bit" "Not converted,Converted" bitfld.long 0x00 20. " G1CHNSEL[20] ,A/D channel 20 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 19. " G1CHNSEL[19] ,A/D channel 19 enable bit" "Not converted,Converted" bitfld.long 0x00 18. " G1CHNSEL[18] ,A/D channel 18 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 17. " G1CHNSEL[17] ,A/D channel 17 enable bit" "Not converted,Converted" bitfld.long 0x00 16. " G1CHNSEL[16] ,A/D channel 16 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 15. " G1CHNSEL[15] ,A/D channel 15 enable bit" "Not converted,Converted" bitfld.long 0x00 14. " G1CHNSEL[14] ,A/D channel 14 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 13. " G1CHNSEL[13] ,A/D channel 13 enable bit" "Not converted,Converted" bitfld.long 0x00 12. " G1CHNSEL[12] ,A/D channel 12 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 11. " G1CHNSEL[11] ,A/D channel 11 enable bit" "Not converted,Converted" bitfld.long 0x00 10. " G1CHNSEL[10] ,A/D channel 10 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 9. " G1CHNSEL[9] ,A/D channel 9 enable bit" "Not converted,Converted" bitfld.long 0x00 8. " G1CHNSEL[8] ,A/D channel 8 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 7. " G1CHNSEL[7] ,A/D channel 7 enable bit" "Not converted,Converted" bitfld.long 0x00 6. " G1CHNSEL[6] ,A/D channel 6 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 5. " G1CHNSEL[5] ,A/D channel 5 enable bit" "Not converted,Converted" bitfld.long 0x00 4. " G1CHNSEL[4] ,A/D channel 4 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 3. " G1CHNSEL[3] ,A/D channel 3 enable bit" "Not converted,Converted" bitfld.long 0x00 2. " G1CHNSEL[2] ,A/D channel 2 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 1. " G1CHNSEL[1] ,A/D channel 1 enable bit" "Not converted,Converted" bitfld.long 0x00 0. " G1CHNSEL[0] ,A/D channel 0 enable bit" "Not converted,Converted" group.long 0x80++0x03 line.long 0x00 "ADG2SEL,Group 2 Select Register" bitfld.long 0x00 24. " G2CHNSEL[24] ,A/D channel 24 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 23. " G2CHNSEL[23] ,A/D channel 23 enable bit" "Not converted,Converted" bitfld.long 0x00 22. " G2CHNSEL[22] ,A/D channel 22 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 21. " G2CHNSEL[21] ,A/D channel 21 enable bit" "Not converted,Converted" bitfld.long 0x00 20. " G2CHNSEL[20] ,A/D channel 20 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 19. " G2CHNSEL[19] ,A/D channel 19 enable bit" "Not converted,Converted" bitfld.long 0x00 18. " G2CHNSEL[18] ,A/D channel 18 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 17. " G2CHNSEL[17] ,A/D channel 17 enable bit" "Not converted,Converted" bitfld.long 0x00 16. " G2CHNSEL[16] ,A/D channel 16 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 15. " G2CHNSEL[15] ,A/D channel 15 enable bit" "Not converted,Converted" bitfld.long 0x00 14. " G2CHNSEL[14] ,A/D channel 14 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 13. " G2CHNSEL[13] ,A/D channel 13 enable bit" "Not converted,Converted" bitfld.long 0x00 12. " G2CHNSEL[12] ,A/D channel 12 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 11. " G2CHNSEL[11] ,A/D channel 11 enable bit" "Not converted,Converted" bitfld.long 0x00 10. " G2CHNSEL[10] ,A/D channel 10 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 9. " G2CHNSEL[9] ,A/D channel 9 enable bit" "Not converted,Converted" bitfld.long 0x00 8. " G2CHNSEL[8] ,A/D channel 8 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 7. " G2CHNSEL[7] ,A/D channel 7 enable bit" "Not converted,Converted" bitfld.long 0x00 6. " G2CHNSEL[6] ,A/D channel 6 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 5. " G2CHNSEL[5] ,A/D channel 5 enable bit" "Not converted,Converted" bitfld.long 0x00 4. " G2CHNSEL[4] ,A/D channel 4 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 3. " G2CHNSEL[3] ,A/D channel 3 enable bit" "Not converted,Converted" bitfld.long 0x00 2. " G2CHNSEL[2] ,A/D channel 2 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 1. " G2CHNSEL[1] ,A/D channel 1 enable bit" "Not converted,Converted" bitfld.long 0x00 0. " G2CHNSEL[0] ,A/D channel 0 enable bit" "Not converted,Converted" else group.long 0x78++0x03 line.long 0x00 "ADEVSEL,Event Group Select Register" bitfld.long 0x00 15. " EVCHNSEL[15] ,A/D event channel 15 selection bit" "Not converted,Converted" bitfld.long 0x00 14. " EVCHNSEL[14] ,A/D event channel 14 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 13. " EVCHNSEL[13] ,A/D event channel 13 selection bit" "Not converted,Converted" bitfld.long 0x00 12. " EVCHNSEL[12] ,A/D event channel 12 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 11. " EVCHNSEL[11] ,A/D event channel 11 selection bit" "Not converted,Converted" bitfld.long 0x00 10. " EVCHNSEL[10] ,A/D event channel 10 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 9. " EVCHNSEL[9] ,A/D event channel 9 selection bit" "Not converted,Converted" bitfld.long 0x00 8. " EVCHNSEL[8] ,A/D event channel 8 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 7. " EVCHNSEL[7] ,A/D event channel 7 selection bit" "Not converted,Converted" bitfld.long 0x00 6. " EVCHNSEL[6] ,A/D event channel 6 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 5. " EVCHNSEL[5] ,A/D event channel 5 selection bit" "Not converted,Converted" bitfld.long 0x00 4. " EVCHNSEL[4] ,A/D event channel 4 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 3. " EVCHNSEL[3] ,A/D event channel 3 selection bit" "Not converted,Converted" bitfld.long 0x00 2. " EVCHNSEL[2] ,A/D event channel 2 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 1. " EVCHNSEL[1] ,A/D event channel 1 selection bit" "Not converted,Converted" bitfld.long 0x00 0. " EVCHNSEL[0] ,A/D event channel 0 selection bit" "Not converted,Converted" group.long 0x7C++0x03 line.long 0x00 "ADG1SEL,Group 1 Select Register" bitfld.long 0x00 15. " G1CHNSEL[15] ,A/D channel 15 enable bit" "Not converted,Converted" bitfld.long 0x00 14. " G1CHNSEL[14] ,A/D channel 14 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 13. " G1CHNSEL[13] ,A/D channel 13 enable bit" "Not converted,Converted" bitfld.long 0x00 12. " G1CHNSEL[12] ,A/D channel 12 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 11. " G1CHNSEL[11] ,A/D channel 11 enable bit" "Not converted,Converted" bitfld.long 0x00 10. " G1CHNSEL[10] ,A/D channel 10 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 9. " G1CHNSEL[9] ,A/D channel 9 enable bit" "Not converted,Converted" bitfld.long 0x00 8. " G1CHNSEL[8] ,A/D channel 8 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 7. " G1CHNSEL[7] ,A/D channel 7 enable bit" "Not converted,Converted" bitfld.long 0x00 6. " G1CHNSEL[6] ,A/D channel 6 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 5. " G1CHNSEL[5] ,A/D channel 5 enable bit" "Not converted,Converted" bitfld.long 0x00 4. " G1CHNSEL[4] ,A/D channel 4 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 3. " G1CHNSEL[3] ,A/D channel 3 enable bit" "Not converted,Converted" bitfld.long 0x00 2. " G1CHNSEL[2] ,A/D channel 2 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 1. " G1CHNSEL[1] ,A/D channel 1 enable bit" "Not converted,Converted" bitfld.long 0x00 0. " G1CHNSEL[0] ,A/D channel 0 enable bit" "Not converted,Converted" group.long 0x80++0x03 line.long 0x00 "ADG2SEL,Group 2 Select Register" bitfld.long 0x00 15. " G2CHNSEL[15] ,A/D channel 15 enable bit" "Not converted,Converted" bitfld.long 0x00 14. " G2CHNSEL[14] ,A/D channel 14 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 13. " G2CHNSEL[13] ,A/D channel 13 enable bit" "Not converted,Converted" bitfld.long 0x00 12. " G2CHNSEL[12] ,A/D channel 12 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 11. " G2CHNSEL[11] ,A/D channel 11 enable bit" "Not converted,Converted" bitfld.long 0x00 10. " G2CHNSEL[10] ,A/D channel 10 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 9. " G2CHNSEL[9] ,A/D channel 9 enable bit" "Not converted,Converted" bitfld.long 0x00 8. " G2CHNSEL[8] ,A/D channel 8 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 7. " G2CHNSEL[7] ,A/D channel 7 enable bit" "Not converted,Converted" bitfld.long 0x00 6. " G2CHNSEL[6] ,A/D channel 6 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 5. " G2CHNSEL[5] ,A/D channel 5 enable bit" "Not converted,Converted" bitfld.long 0x00 4. " G2CHNSEL[4] ,A/D channel 4 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 3. " G2CHNSEL[3] ,A/D channel 3 enable bit" "Not converted,Converted" bitfld.long 0x00 2. " G2CHNSEL[2] ,A/D channel 2 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 1. " G2CHNSEL[1] ,A/D channel 1 enable bit" "Not converted,Converted" bitfld.long 0x00 0. " G2CHNSEL[0] ,A/D channel 0 enable bit" "Not converted,Converted" endif tree.end width 12. textline " " sif (cpuis("RM48L950*")||cpu()=="RM57L843-ZWT") if (((d.l(ad:0xFFF7C000+0x04))&0x80)==0x80) group.long 0x84++0x03 line.long 0x00 "ADCALR,Calibration Register" hexmask.long.word 0x00 0.--11. 1. " ADCALR[11:0] ,Calibration bits" else group.long 0x84++0x03 line.long 0x00 "ADCALR,Calibration Register" hexmask.long.word 0x00 0.--9. 1. " ADCALR[9:0] ,Calibration bits" endif else if (((d.l(ad:0xFFF7C000+0x04))&0x80000000)==0x80000000) group.long 0x84++0x03 line.long 0x00 "ADCALR,Calibration Register" hexmask.long.word 0x00 0.--11. 1. " ADCALR[11:0] ,Calibration bits" else group.long 0x84++0x03 line.long 0x00 "ADCALR,Calibration Register" hexmask.long.word 0x00 0.--9. 1. " ADCALR[9:0] ,Calibration bits" endif endif rgroup.long 0x88++0x03 line.long 0x00 "ADSMSTATE,State Machine Current State" bitfld.long 0x00 0.--3. " SMSTATE[3:0] ,ADC state machine current state" "Idle,Conv_ev,Conv_sw1,Conv_sw2,Conv_cal,Start_ev,Start_sw1,Start_sw2,Start_cal,Wait_ev,Wait_sw1,Wait_sw2,Wait_cal,?..." width 12. sif (cpu()=="RM57L843-ZWT") rgroup.long 0x8C++0x03 line.long 0x00 "ADLASTCONV,Last Conversion" textline " " bitfld.long 0x00 24. " LAST_CONV[24] ,Digital input channel 24" "Low,High" textline " " bitfld.long 0x00 23. " LAST_CONV[23] ,Digital input channel 23" "Low,High" bitfld.long 0x00 22. " LAST_CONV[22] ,Digital input channel 22" "Low,High" bitfld.long 0x00 21. " LAST_CONV[21] ,Digital input channel 21" "Low,High" bitfld.long 0x00 20. " LAST_CONV[20] ,Digital input channel 20" "Low,High" textline " " bitfld.long 0x00 19. " LAST_CONV[19] ,Digital input channel 19" "Low,High" bitfld.long 0x00 18. " LAST_CONV[18] ,Digital input channel 18" "Low,High" bitfld.long 0x00 17. " LAST_CONV[17] ,Digital input channel 17" "Low,High" bitfld.long 0x00 16. " LAST_CONV[16] ,Digital input channel 16" "Low,High" textline " " bitfld.long 0x00 15. " LAST_CONV[15] ,Digital input channel 15" "Low,High" bitfld.long 0x00 14. " LAST_CONV[14] ,Digital input channel 14" "Low,High" bitfld.long 0x00 13. " LAST_CONV[13] ,Digital input channel 13" "Low,High" bitfld.long 0x00 12. " LAST_CONV[12] ,Digital input channel 12" "Low,High" textline " " bitfld.long 0x00 11. " LAST_CONV[11] ,Digital input channel 11" "Low,High" bitfld.long 0x00 10. " LAST_CONV[10] ,Digital input channel 10" "Low,High" bitfld.long 0x00 9. " LAST_CONV[9] ,Digital input channel 9" "Low,High" bitfld.long 0x00 8. " LAST_CONV[8] ,Digital input channel 8" "Low,High" textline " " bitfld.long 0x00 7. " LAST_CONV[7] ,Digital input channel 7" "Low,High" bitfld.long 0x00 6. " LAST_CONV[6] ,Digital input channel 6" "Low,High" bitfld.long 0x00 5. " LAST_CONV[5] ,Digital input channel 5" "Low,High" bitfld.long 0x00 4. " LAST_CONV[4] ,Digital input channel 4" "Low,High" textline " " bitfld.long 0x00 3. " LAST_CONV[3] ,Digital input channel 3" "Low,High" bitfld.long 0x00 2. " LAST_CONV[2] ,Digital input channel 2" "Low,High" bitfld.long 0x00 1. " LAST_CONV[1] ,Digital input channel 1" "Low,High" bitfld.long 0x00 0. " LAST_CONV[0] ,Digital input channel 0" "Low,High" else rgroup.long 0x8C++0x03 line.long 0x00 "ADLASTCONV,Last Conversion" bitfld.long 0x00 15. " LAST_CONV[15] ,Digital input channel 15" "Low,High" bitfld.long 0x00 14. " LAST_CONV[14] ,Digital input channel 14" "Low,High" bitfld.long 0x00 13. " LAST_CONV[13] ,Digital input channel 13" "Low,High" bitfld.long 0x00 12. " LAST_CONV[12] ,Digital input channel 12" "Low,High" textline " " bitfld.long 0x00 11. " LAST_CONV[11] ,Digital input channel 11" "Low,High" bitfld.long 0x00 10. " LAST_CONV[10] ,Digital input channel 10" "Low,High" bitfld.long 0x00 9. " LAST_CONV[9] ,Digital input channel 9" "Low,High" bitfld.long 0x00 8. " LAST_CONV[8] ,Digital input channel 8" "Low,High" textline " " bitfld.long 0x00 7. " LAST_CONV[7] ,Digital input channel 7" "Low,High" bitfld.long 0x00 6. " LAST_CONV[6] ,Digital input channel 6" "Low,High" bitfld.long 0x00 5. " LAST_CONV[5] ,Digital input channel 5" "Low,High" bitfld.long 0x00 4. " LAST_CONV[4] ,Digital input channel 4" "Low,High" textline " " bitfld.long 0x00 3. " LAST_CONV[3] ,Digital input channel 3" "Low,High" bitfld.long 0x00 2. " LAST_CONV[2] ,Digital input channel 2" "Low,High" bitfld.long 0x00 1. " LAST_CONV[1] ,Digital input channel 1" "Low,High" bitfld.long 0x00 0. " LAST_CONV[0] ,Digital input channel 0" "Low,High" endif width 15. tree "ADC Buffer Control Registers" hgroup.long 0x90++0x1F hide.long 0x00 "ADEVBUFFER0,Event Group Buffer 0" in hide.long 0x04 "ADEVBUFFER1,Event Group Buffer 1" in hide.long 0x08 "ADEVBUFFER2,Event Group Buffer 2" in hide.long 0x0C "ADEVBUFFER3,Event Group Buffer 3" in hide.long 0x10 "ADEVBUFFER4,Event Group Buffer 4" in hide.long 0x14 "ADEVBUFFER5,Event Group Buffer 5" in hide.long 0x18 "ADEVBUFFER6,Event Group Buffer 6" in hide.long 0x1C "ADEVBUFFER7,Event Group Buffer 7" in hgroup.long 0xB0++0x1F hide.long 0x00 "ADG1BUFFER0,Group1 Buffer 0" in hide.long 0x04 "ADG1BUFFER1,Group1 Buffer 1" in hide.long 0x08 "ADG1BUFFER2,Group1 Buffer 2" in hide.long 0x0C "ADG1BUFFER3,Group1 Buffer 3" in hide.long 0x10 "ADG1BUFFER4,Group1 Buffer 4" in hide.long 0x14 "ADG1BUFFER5,Group1 Buffer 5" in hide.long 0x18 "ADG1BUFFER6,Group1 Buffer 6" in hide.long 0x1C "ADG1BUFFER7,Group1 Buffer 7" in hgroup.long 0xD0++0x1F hide.long 0x00 "ADG2BUFFER0,Group2 Buffer 0" in hide.long 0x04 "ADG2BUFFER1,Group2 Buffer 1" in hide.long 0x08 "ADG2BUFFER2,Group2 Buffer 2" in hide.long 0x0C "ADG2BUFFER3,Group2 Buffer 3" in hide.long 0x10 "ADG2BUFFER4,Group2 Buffer 4" in hide.long 0x14 "ADG2BUFFER5,Group2 Buffer 5" in hide.long 0x18 "ADG2BUFFER6,Group2 Buffer 6" in hide.long 0x1C "ADG2BUFFER7,Group2 Buffer 7" in hgroup.long 0xF0++0x03 hide.long 0x00 "ADEVEMUBUFFER,Event Group EMU Buffer" in hgroup.long 0xF4++0x03 hide.long 0x00 "ADG1BUFFER,Group 1 EMU Buffer" in hgroup.long 0xF8++0x03 hide.long 0x00 "ADG2BUFFER,Group 2 EMU Buffer" in tree.end width 11. tree "ADC ADEVT Pin Control Registers" group.long 0xFC++0x03 line.long 0x00 "ADEVTDIR,Event Group Pin Direction Selection" bitfld.long 0x00 0. " EVT_DIR ,ADEVT pin direction selection" "Output disabled,Output enabled" sif (cpu()=="RM48L950"||cpu()=="RM48L952-PGE"||cpu()=="RM48L952-ZWT"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L540-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE"||cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE"||cpu()=="RM42L432") if (((d.l((ad:0xFFF7C000+0xFC)))&0x1000000)==0x1000000) group.long 0x100++0x03 line.long 0x00 "ADEVTOUT,Event Group Pin Data Output" bitfld.long 0x00 0. " EVT_OUT ,ADEVT pin data output" "Low,High" else hgroup.long 0x100++0x03 hide.long 0x00 "ADEVTOUT,Event Group Pin Data Output" endif else if (((d.l((ad:0xFFF7C000+0xFC)))&0x01)==0x01) group.long 0x100++0x03 line.long 0x00 "ADEVTOUT,Event Group Pin Data Output" bitfld.long 0x00 0. " EVT_OUT ,ADEVT pin data output" "Low,High" else hgroup.long 0x100++0x03 hide.long 0x00 "ADEVTOUT,Event Group Pin Data Output" endif endif group.long 0x104++0x03 line.long 0x00 "ADEVTIN,Event Group Pin Input Value" bitfld.long 0x00 0. " EVT_IN ,ADEVT pin input value" "Low,High" group.long 0x108++0x03 line.long 0x00 "ADEVTSET,Event Group Pin Set" bitfld.long 0x00 0. " ADEVT_SET ,ADEVT pin set" "Low/no effect,High/set" group.long 0x10C++0x03 line.long 0x00 "ADEVTCLR,Event Group Pin Clear" bitfld.long 0x00 0. " ADEVT_CLR ,ADEVT pin clear" "Low/no effect,High/clear" sif (cpuis("RM48L950*")) if ((((d.l((ad:0xFFF7C000+0xfc)))&0x01000000)==0x01000000)&&(((d.l((ad:0xFFF7C000+0x0100)))&0x01000000)==0x01000000)) group.long 0x110++0x03 line.long 0x00 "ADEVTPDR,Event Group Pin open-drain Enable" bitfld.long 0x00 0. " ADEVT_PDR ,ADEVT pin Open-Drain enable" "High,Tri-state" else hgroup.long 0x110++0x03 hide.long 0x00 "ADEVTPDR,Event Group Pin open-drain Enable" endif else if ((((d.l((ad:0xFFF7C000+0xfc)))&0x01)==0x01)&&(((d.l((ad:0xFFF7C000+0x0100)))&0x01)==0x01)) group.long 0x110++0x03 line.long 0x00 "ADEVTPDR,Event Group Pin open-drain Enable" bitfld.long 0x00 0. " ADEVT_PDR ,ADEVT pin Open-Drain enable" "High,Tri-state" else hgroup.long 0x110++0x03 hide.long 0x00 "ADEVTPDR,Event Group Pin open-drain Enable" endif endif sif (cpuis("RM48L950*")) if (((d.l((ad:0xFFF7C000+0xFC)))&0x1000000)==0x00) group.long 0x114++0x03 line.long 0x00 "ADEVTPDIS,Event Group Pin Pull Control Enable" bitfld.long 0x00 0. " ADEVT_PDIS ,ADEVT pin pull control enable" "Enabled,Disabled" else hgroup.long 0x114++0x03 hide.long 0x00 "ADEVTPDIS,Event Group Pin Pull Control Enable" endif else if (((d.l((ad:0xFFF7C000+0xFC)))&0x01)==0x00) group.long 0x114++0x03 line.long 0x00 "ADEVTPDIS,Event Group Pin Pull Control Enable" bitfld.long 0x00 0. " ADEVT_PDIS ,ADEVT pin pull control enable" "Enabled,Disabled" else hgroup.long 0x114++0x03 hide.long 0x00 "ADEVTPDIS,Event Group Pin Pull Control Enable" endif endif group.long 0x118++0x03 line.long 0x00 "ADEVTPSEL,Event Group Pull Select" bitfld.long 0x00 0. " ADEVT_PSEL ,ADEVT pull select" "Pull-down,Pull-up" tree.end width 15. tree "ADC Sampling Capacitor Discharge Mode Control Registers" group.long 0x11C++0x03 line.long 0x00 "ADEVSAMPDISEN,Event Group Sampling Capacitor Discharge Mode" hexmask.long.byte 0x00 8.--15. 1. " EV_SAMP_DIS_CYC[7:0] ,ADC sampling capacitor is dicharged cycles" bitfld.long 0x00 0. " EV_SAMP_DIS_EN ,Sampling capacitor discharge mode" "Disabled,Enabled" group.long 0x120++0x03 line.long 0x00 "ADG1SAMPDISEN,Group 1 Sampling Capacitor Discharge Mode" hexmask.long.byte 0x00 8.--15. 1. " G1_SAMP_DIS_CYC[7:0] ,ADC sampling capacitor is dicharged cycles" bitfld.long 0x00 0. " G1_SAMP_DIS_EN ,Sampling capacitor discharge mode" "Disabled,Enabled" group.long 0x124++0x03 line.long 0x00 "ADG2SAMPDISEN,Group 2 Sampling Capacitor Discharge Mode" hexmask.long.byte 0x00 8.--15. 1. " G2_SAMP_DIS_CYC[7:0] ,ADC sampling capacitor is dicharged cycles" bitfld.long 0x00 0. " G2_SAMP_DIS_EN ,Sampling capacitor discharge mode" "Disabled,Enabled" tree.end width 19. tree "ADC Interrupt Control Registers" sif (cpu()=="RM57L843-ZWT") if (((d.l(ad:0xFFF7C000+0x04))&0x80000000)==0x80000000) group.long 0x128++0x03 line.long 0x00 "ADMAGINTCR1,Magnitude Interrupt Control Register 1" hexmask.long.word 0x00 16.--27. 1. " MAG_THR1[11-0] ,12-bit compare value with MAG_CHID1" bitfld.long 0x00 15. " CHN_THR_COMP1 ,Channel OR threshold comparison" "Threshold,Channel" bitfld.long 0x00 14. " CMP_GE_LT1 ,'greater than or equal to' OR 'less than' comparison operator" "Lower,Greater" textline " " bitfld.long 0x00 8.--12. " COMP_CHID1[4-0] ,Channel number compared with MAG_CHID1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " MAG_CHID1[4-0] ,Channel number monitored by ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x12C++0x03 line.long 0x00 "ADMAGINT1MASK,Magnitude Interrupt Mask 1" bitfld.long 0x00 11. " MAG_INT1_MASK[11] ,Comparison for the magnitude compare interrupt 1 mask 11" "Not masked,Masked" bitfld.long 0x00 10. " MAG_INT1_MASK[10] ,Comparison for the magnitude compare interrupt 1 mask 10" "Not masked,Masked" textline " " bitfld.long 0x00 9. " MAG_INT1_MASK[9] ,Comparison for the magnitude compare interrupt 1 mask 9" "Not masked,Masked" bitfld.long 0x00 8. " MAG_INT1_MASK[8] ,Comparison for the magnitude compare interrupt 1 mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MAG_INT1_MASK[7] ,Comparison for the magnitude compare interrupt 1 mask 7" "Not masked,Masked" bitfld.long 0x00 6. " MAG_INT1_MASK[6] ,Comparison for the magnitude compare interrupt 1 mask 6" "Not masked,Masked" textline " " bitfld.long 0x00 5. " MAG_INT1_MASK[5] ,Comparison for the magnitude compare interrupt 1 mask 5" "Not masked,Masked" bitfld.long 0x00 4. " MAG_INT1_MASK[4] ,Comparison for the magnitude compare interrupt 1 mask 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " MAG_INT1_MASK[3] ,Comparison for the magnitude compare interrupt 1 mask 3" "Not masked,Masked" bitfld.long 0x00 2. " MAG_INT1_MASK[2] ,Comparison for the magnitude compare interrupt 1 mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " MAG_INT1_MASK[1] ,Comparison for the magnitude compare interrupt 1 mask 1" "Not masked,Masked" bitfld.long 0x00 0. " MAG_INT1_MASK[0] ,Comparison for the magnitude compare interrupt 1 mask 0" "Not masked,Masked" group.long 0x130++0x03 line.long 0x00 "ADMAGINTCR2,Magnitude Interrupt Control Register 2" hexmask.long.word 0x00 16.--27. 1. " MAG_THR2[11-0] ,12-bit compare value with MAG_CHID2" bitfld.long 0x00 15. " CHN_THR_COMP2 ,Channel OR threshold comparison" "Threshold,Channel" bitfld.long 0x00 14. " CMP_GE_LT2 ,'greater than or equal to' OR 'less than' comparison operator" "Lower,Greater" textline " " bitfld.long 0x00 8.--12. " COMP_CHID2[4-0] ,Channel number compared with MAG_CHID2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " MAG_CHID2[4-0] ,Channel number monitored by ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x134++0x03 line.long 0x00 "ADMAGINT2MASK,Magnitude Interrupt Mask 2" bitfld.long 0x00 11. " MAG_INT2_MASK[11] ,Comparison for the magnitude compare interrupt 2 mask 11" "Not masked,Masked" bitfld.long 0x00 10. " MAG_INT2_MASK[10] ,Comparison for the magnitude compare interrupt 2 mask 10" "Not masked,Masked" textline " " bitfld.long 0x00 9. " MAG_INT2_MASK[9] ,Comparison for the magnitude compare interrupt 2 mask 9" "Not masked,Masked" bitfld.long 0x00 8. " MAG_INT2_MASK[8] ,Comparison for the magnitude compare interrupt 2 mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MAG_INT2_MASK[7] ,Comparison for the magnitude compare interrupt 2 mask 7" "Not masked,Masked" bitfld.long 0x00 6. " MAG_INT2_MASK[6] ,Comparison for the magnitude compare interrupt 2 mask 6" "Not masked,Masked" textline " " bitfld.long 0x00 5. " MAG_INT2_MASK[5] ,Comparison for the magnitude compare interrupt 2 mask 5" "Not masked,Masked" bitfld.long 0x00 4. " MAG_INT2_MASK[4] ,Comparison for the magnitude compare interrupt 2 mask 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " MAG_INT2_MASK[3] ,Comparison for the magnitude compare interrupt 2 mask 3" "Not masked,Masked" bitfld.long 0x00 2. " MAG_INT2_MASK[2] ,Comparison for the magnitude compare interrupt 2 mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " MAG_INT2_MASK[1] ,Comparison for the magnitude compare interrupt 2 mask 1" "Not masked,Masked" bitfld.long 0x00 0. " MAG_INT2_MASK[0] ,Comparison for the magnitude compare interrupt 2 mask 0" "Not masked,Masked" group.long 0x138++0x03 line.long 0x00 "ADMAGINTCR3,Magnitude Interrupt Control Register 3" hexmask.long.word 0x00 16.--27. 1. " MAG_THR3[11-0] ,12-bit compare value with MAG_CHID3" bitfld.long 0x00 15. " CHN_THR_COMP3 ,Channel OR threshold comparison" "Threshold,Channel" bitfld.long 0x00 14. " CMP_GE_LT3 ,'greater than or equal to' OR 'less than' comparison operator" "Lower,Greater" textline " " bitfld.long 0x00 8.--12. " COMP_CHID3[4-0] ,Channel number compared with MAG_CHID3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " MAG_CHID3[4-0] ,Channel number monitored by ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x13C++0x03 line.long 0x00 "ADMAGINT3MASK,Magnitude Interrupt Mask 3" bitfld.long 0x00 11. " MAG_INT3_MASK[11] ,Comparison for the magnitude compare interrupt 3 mask 11" "Not masked,Masked" bitfld.long 0x00 10. " MAG_INT3_MASK[10] ,Comparison for the magnitude compare interrupt 3 mask 10" "Not masked,Masked" textline " " bitfld.long 0x00 9. " MAG_INT3_MASK[9] ,Comparison for the magnitude compare interrupt 3 mask 9" "Not masked,Masked" bitfld.long 0x00 8. " MAG_INT3_MASK[8] ,Comparison for the magnitude compare interrupt 3 mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MAG_INT3_MASK[7] ,Comparison for the magnitude compare interrupt 3 mask 7" "Not masked,Masked" bitfld.long 0x00 6. " MAG_INT3_MASK[6] ,Comparison for the magnitude compare interrupt 3 mask 6" "Not masked,Masked" textline " " bitfld.long 0x00 5. " MAG_INT3_MASK[5] ,Comparison for the magnitude compare interrupt 3 mask 5" "Not masked,Masked" bitfld.long 0x00 4. " MAG_INT3_MASK[4] ,Comparison for the magnitude compare interrupt 3 mask 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " MAG_INT3_MASK[3] ,Comparison for the magnitude compare interrupt 3 mask 3" "Not masked,Masked" bitfld.long 0x00 2. " MAG_INT3_MASK[2] ,Comparison for the magnitude compare interrupt 3 mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " MAG_INT3_MASK[1] ,Comparison for the magnitude compare interrupt 3 mask 1" "Not masked,Masked" bitfld.long 0x00 0. " MAG_INT3_MASK[0] ,Comparison for the magnitude compare interrupt 3 mask 0" "Not masked,Masked" else group.long 0x128++0x03 line.long 0x00 "ADMAGINTCR1,Magnitude Interrupt Control Register 1" bitfld.long 0x00 26.--30. " MAG_CHID1[4-0] ,Channel number monitored by ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 16.--25. 1. " MAG_THR1[9-0] ,10-bit compare value with MAG_CHID1" textline " " bitfld.long 0x00 8.--12. " COMP_CHID1[4-0] ,Channel number compared with MAG_CHID1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1. " CHN/THR_COMP1 ,Channel OR threshold comparison" "Threshold,COMP_CHID1 channel" textline " " bitfld.long 0x00 0. " CMP_GE/LT1 ,Greater than or equal to OR less than comparison operator" "Lower,Greater" group.long 0x12C++0x03 line.long 0x00 "ADMAGINT1MASK,Magnitude Interrupt Mask 1" bitfld.long 0x00 9. " MAG_INT1_MASK[9] ,Comparison for the magnitude compare interrupt 1 mask 9" "Not masked,Masked" bitfld.long 0x00 8. " MAG_INT1_MASK[8] ,Comparison for the magnitude compare interrupt 1 mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MAG_INT1_MASK[7] ,Comparison for the magnitude compare interrupt 1 mask 7" "Not masked,Masked" bitfld.long 0x00 6. " MAG_INT1_MASK[6] ,Comparison for the magnitude compare interrupt 1 mask 6" "Not masked,Masked" textline " " bitfld.long 0x00 5. " MAG_INT1_MASK[5] ,Comparison for the magnitude compare interrupt 1 mask 5" "Not masked,Masked" bitfld.long 0x00 4. " MAG_INT1_MASK[4] ,Comparison for the magnitude compare interrupt 1 mask 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " MAG_INT1_MASK[3] ,Comparison for the magnitude compare interrupt 1 mask 3" "Not masked,Masked" bitfld.long 0x00 2. " MAG_INT1_MASK[2] ,Comparison for the magnitude compare interrupt 1 mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " MAG_INT1_MASK[1] ,Comparison for the magnitude compare interrupt 1 mask 1" "Not masked,Masked" bitfld.long 0x00 0. " MAG_INT1_MASK[0] ,Comparison for the magnitude compare interrupt 1 mask 0" "Not masked,Masked" group.long 0x130++0x03 line.long 0x00 "ADMAGINTCR2,Magnitude Interrupt Control Register 2" bitfld.long 0x00 26.--30. " MAG_CHID2[4-0] ,Channel number monitored by ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 16.--25. 1. " MAG_THR2[9-0] ,10-bit compare value with MAG_CHID2" textline " " bitfld.long 0x00 8.--12. " COMP_CHID2[4-0] ,Channel number compared with MAG_CHID2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1. " CHN/THR_COMP2 ,Channel OR threshold comparison" "Threshold,COMP_CHID1 channel" textline " " bitfld.long 0x00 0. " CMP_GE/LT2 ,Greater than or equal to OR less than comparison operator" "Lower,Greater" group.long 0x134++0x03 line.long 0x00 "ADMAGINT2MASK,Magnitude Interrupt Mask 2" bitfld.long 0x00 9. " MAG_INT2_MASK[9] ,Comparison for the magnitude compare interrupt 2 mask 9" "Not masked,Masked" bitfld.long 0x00 8. " MAG_INT2_MASK[8] ,Comparison for the magnitude compare interrupt 2 mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MAG_INT2_MASK[7] ,Comparison for the magnitude compare interrupt 2 mask 7" "Not masked,Masked" bitfld.long 0x00 6. " MAG_INT2_MASK[6] ,Comparison for the magnitude compare interrupt 2 mask 6" "Not masked,Masked" textline " " bitfld.long 0x00 5. " MAG_INT2_MASK[5] ,Comparison for the magnitude compare interrupt 2 mask 5" "Not masked,Masked" bitfld.long 0x00 4. " MAG_INT2_MASK[4] ,Comparison for the magnitude compare interrupt 2 mask 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " MAG_INT2_MASK[3] ,Comparison for the magnitude compare interrupt 2 mask 3" "Not masked,Masked" bitfld.long 0x00 2. " MAG_INT2_MASK[2] ,Comparison for the magnitude compare interrupt 2 mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " MAG_INT2_MASK[1] ,Comparison for the magnitude compare interrupt 2 mask 1" "Not masked,Masked" bitfld.long 0x00 0. " MAG_INT2_MASK[0] ,Comparison for the magnitude compare interrupt 2 mask 0" "Not masked,Masked" group.long 0x138++0x03 line.long 0x00 "ADMAGINTCR3,Magnitude Interrupt Control Register 3" bitfld.long 0x00 26.--30. " MAG_CHID3[4-0] ,Channel number monitored by ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 16.--25. 1. " MAG_THR3[9-0] ,10-bit compare value with MAG_CHID3" textline " " bitfld.long 0x00 8.--12. " COMP_CHID3[4-0] ,Channel number compared with MAG_CHID3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1. " CHN/THR_COMP3 ,Channel OR threshold comparison" "Threshold,COMP_CHID3 channel" textline " " bitfld.long 0x00 0. " CMP_GE/LT3 ,Greater than or equal to OR less than comparison operator" "Lower,Greater" group.long 0x13C++0x03 line.long 0x00 "ADMAGINT3MASK,Magnitude Interrupt Mask 3" bitfld.long 0x00 9. " MAG_INT3_MASK[9] ,Comparison for the magnitude compare interrupt 3 mask 9" "Not masked,Masked" bitfld.long 0x00 8. " MAG_INT3_MASK[8] ,Comparison for the magnitude compare interrupt 3 mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MAG_INT3_MASK[7] ,Comparison for the magnitude compare interrupt 3 mask 7" "Not masked,Masked" bitfld.long 0x00 6. " MAG_INT3_MASK[6] ,Comparison for the magnitude compare interrupt 3 mask 6" "Not masked,Masked" textline " " bitfld.long 0x00 5. " MAG_INT3_MASK[5] ,Comparison for the magnitude compare interrupt 3 mask 5" "Not masked,Masked" bitfld.long 0x00 4. " MAG_INT3_MASK[4] ,Comparison for the magnitude compare interrupt 3 mask 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " MAG_INT3_MASK[3] ,Comparison for the magnitude compare interrupt 3 mask 3" "Not masked,Masked" bitfld.long 0x00 2. " MAG_INT3_MASK[2] ,Comparison for the magnitude compare interrupt 3 mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " MAG_INT3_MASK[1] ,Comparison for the magnitude compare interrupt 3 mask 1" "Not masked,Masked" bitfld.long 0x00 0. " MAG_INT3_MASK[0] ,Comparison for the magnitude compare interrupt 3 mask 0" "Not masked,Masked" endif else group.long 0x128++0x03 line.long 0x00 "ADMAGINTCR1,Magnitude Interrupt Control Register 1" bitfld.long 0x00 26.--30. " MAG_CHID1[4-0] ,Channel number monitored by ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 16.--25. 1. " MAG_THR1[9-0] ,10-bit compare value with MAG_CHID1" textline " " bitfld.long 0x00 8.--12. " COMP_CHID1[4-0] ,Channel number compared with MAG_CHID1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1. " CHN/THR_COMP1 ,Channel OR threshold comparison" "Threshold,COMP_CHID1 channel" textline " " bitfld.long 0x00 0. " CMP_GE/LT1 ,Greater than or equal to OR less than comparison operator" "Lower,Greater" group.long 0x12C++0x03 line.long 0x00 "ADMAGINT1MASK,Magnitude Interrupt Mask 1" bitfld.long 0x00 9. " MAG_INT1_MASK[9] ,Comparison for the magnitude compare interrupt 1 mask 9" "Not masked,Masked" bitfld.long 0x00 8. " MAG_INT1_MASK[8] ,Comparison for the magnitude compare interrupt 1 mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MAG_INT1_MASK[7] ,Comparison for the magnitude compare interrupt 1 mask 7" "Not masked,Masked" bitfld.long 0x00 6. " MAG_INT1_MASK[6] ,Comparison for the magnitude compare interrupt 1 mask 6" "Not masked,Masked" textline " " bitfld.long 0x00 5. " MAG_INT1_MASK[5] ,Comparison for the magnitude compare interrupt 1 mask 5" "Not masked,Masked" bitfld.long 0x00 4. " MAG_INT1_MASK[4] ,Comparison for the magnitude compare interrupt 1 mask 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " MAG_INT1_MASK[3] ,Comparison for the magnitude compare interrupt 1 mask 3" "Not masked,Masked" bitfld.long 0x00 2. " MAG_INT1_MASK[2] ,Comparison for the magnitude compare interrupt 1 mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " MAG_INT1_MASK[1] ,Comparison for the magnitude compare interrupt 1 mask 1" "Not masked,Masked" bitfld.long 0x00 0. " MAG_INT1_MASK[0] ,Comparison for the magnitude compare interrupt 1 mask 0" "Not masked,Masked" group.long 0x130++0x03 line.long 0x00 "ADMAGINTCR2,Magnitude Interrupt Control Register 2" bitfld.long 0x00 26.--30. " MAG_CHID2[4-0] ,Channel number monitored by ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 16.--25. 1. " MAG_THR2[9-0] ,10-bit compare value with MAG_CHID2" textline " " bitfld.long 0x00 8.--12. " COMP_CHID2[4-0] ,Channel number compared with MAG_CHID2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1. " CHN/THR_COMP2 ,Channel OR threshold comparison" "Threshold,COMP_CHID1 channel" textline " " bitfld.long 0x00 0. " CMP_GE/LT2 ,Greater than or equal to OR less than comparison operator" "Lower,Greater" group.long 0x134++0x03 line.long 0x00 "ADMAGINT2MASK,Magnitude Interrupt Mask 2" bitfld.long 0x00 9. " MAG_INT2_MASK[9] ,Comparison for the magnitude compare interrupt 2 mask 9" "Not masked,Masked" bitfld.long 0x00 8. " MAG_INT2_MASK[8] ,Comparison for the magnitude compare interrupt 2 mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MAG_INT2_MASK[7] ,Comparison for the magnitude compare interrupt 2 mask 7" "Not masked,Masked" bitfld.long 0x00 6. " MAG_INT2_MASK[6] ,Comparison for the magnitude compare interrupt 2 mask 6" "Not masked,Masked" textline " " bitfld.long 0x00 5. " MAG_INT2_MASK[5] ,Comparison for the magnitude compare interrupt 2 mask 5" "Not masked,Masked" bitfld.long 0x00 4. " MAG_INT2_MASK[4] ,Comparison for the magnitude compare interrupt 2 mask 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " MAG_INT2_MASK[3] ,Comparison for the magnitude compare interrupt 2 mask 3" "Not masked,Masked" bitfld.long 0x00 2. " MAG_INT2_MASK[2] ,Comparison for the magnitude compare interrupt 2 mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " MAG_INT2_MASK[1] ,Comparison for the magnitude compare interrupt 2 mask 1" "Not masked,Masked" bitfld.long 0x00 0. " MAG_INT2_MASK[0] ,Comparison for the magnitude compare interrupt 2 mask 0" "Not masked,Masked" group.long 0x138++0x03 line.long 0x00 "ADMAGINTCR3,Magnitude Interrupt Control Register 3" bitfld.long 0x00 26.--30. " MAG_CHID3[4-0] ,Channel number monitored by ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 16.--25. 1. " MAG_THR3[9-0] ,10-bit compare value with MAG_CHID3" textline " " bitfld.long 0x00 8.--12. " COMP_CHID3[4-0] ,Channel number compared with MAG_CHID3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1. " CHN/THR_COMP3 ,Channel OR threshold comparison" "Threshold,COMP_CHID3 channel" textline " " bitfld.long 0x00 0. " CMP_GE/LT3 ,Greater than or equal to OR less than comparison operator" "Lower,Greater" group.long 0x13C++0x03 line.long 0x00 "ADMAGINT3MASK,Magnitude Interrupt Mask 3" bitfld.long 0x00 9. " MAG_INT3_MASK[9] ,Comparison for the magnitude compare interrupt 3 mask 9" "Not masked,Masked" bitfld.long 0x00 8. " MAG_INT3_MASK[8] ,Comparison for the magnitude compare interrupt 3 mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MAG_INT3_MASK[7] ,Comparison for the magnitude compare interrupt 3 mask 7" "Not masked,Masked" bitfld.long 0x00 6. " MAG_INT3_MASK[6] ,Comparison for the magnitude compare interrupt 3 mask 6" "Not masked,Masked" textline " " bitfld.long 0x00 5. " MAG_INT3_MASK[5] ,Comparison for the magnitude compare interrupt 3 mask 5" "Not masked,Masked" bitfld.long 0x00 4. " MAG_INT3_MASK[4] ,Comparison for the magnitude compare interrupt 3 mask 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " MAG_INT3_MASK[3] ,Comparison for the magnitude compare interrupt 3 mask 3" "Not masked,Masked" bitfld.long 0x00 2. " MAG_INT3_MASK[2] ,Comparison for the magnitude compare interrupt 3 mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " MAG_INT3_MASK[1] ,Comparison for the magnitude compare interrupt 3 mask 1" "Not masked,Masked" bitfld.long 0x00 0. " MAG_INT3_MASK[0] ,Comparison for the magnitude compare interrupt 3 mask 0" "Not masked,Masked" endif sif (cpu()!="RM57L843-ZWT") group.long 0x140++0x1F line.long 0x00 "MAGINTCTRL4,Magnitude Interrupt Control" line.long 0x04 "MAGINT4MSK,Magnitude Interrupt Mask" line.long 0x08 "MAGINTCTRL5,Magnitude Interrupt Control" line.long 0x0C "MAGINT5MSK,Magnitude Interrupt Mask" line.long 0x10 "MAGINTCTRL6,Magnitude Interrupt Control" line.long 0x14 "MAGINT6MSK,Magnitude Interrupt Mask" line.long 0x18 "MAGTHRINTENASET,Magnitude Interrupt Enable Set" line.long 0x1C "MAGTHRINTENACLR,Magnitude Interrupt Enable Clear" endif group.long 0x160++0x03 line.long 0x00 "ADMAGINTFLG,Magnitude Compare Interrupt Flag" setclrfld.long 0x00 2. -0x08 2. -0x04 2. " MAG_INT3_SET/CLR ,Magnitude compare interrupt flag bit[3]" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 1. -0x08 1. -0x04 1. " MAG_INT2_SET/CLR ,Magnitude compare interrupt flag bit[2]" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 0. -0x08 0. -0x04 0. " MAG_INT1_SET/CLR ,Magnitude compare interrupt flag bit[1]" "No interrupt,Interrupt" hgroup.long 0x164++0x03 hide.long 0x00 "ADMAGINTOFF,Magnitude Compare Interrupt Offset" in tree.end width 17. tree "ADC RAM Control Registers" group.long 0x168++0x03 line.long 0x00 "ADEVFIFORESETCR,Event Group FIFO Reset" bitfld.long 0x00 0. " EV_FIFO_RESET ,Reset the ADC event group FIFO" "No reset,Reset" group.long 0x16C++0x03 line.long 0x00 "ADG1FIFORESETCR,Group 1 FIFO Reset" bitfld.long 0x00 0. " G1_FIFO_RESET ,Reset the ADC group 1 FIFO" "No reset,Reset" group.long 0x170++0x03 line.long 0x00 "ADG2FIFORESETCR,Group 2 FIFO Reset" bitfld.long 0x00 0. " G2_FIFO_RESET ,Reset the ADC group 2 FIFO" "No reset,Reset" rgroup.long 0x174++0x03 line.long 0x00 "ADEVRAMADDR,Event Group ADC RAM Pointer" hexmask.long.word 0x00 0.--8. 1. " EV_RAM_ADDR ,Event group ADC RAM pointer" rgroup.long 0x178++0x03 line.long 0x00 "ADG1RAMADDR,Group 1 ADC RAM Pointer" hexmask.long.word 0x00 0.--8. 1. " G1_RAM_ADDR ,Group 1 ADC RAM pointer" rgroup.long 0x17C++0x03 line.long 0x00 "ADG2RAMADDR,Group 2 ADC RAM Pointer" hexmask.long.word 0x00 0.--8. 1. " G2_RAM_ADDR ,Group 2 ADC RAM pointer" tree.end width 11. tree "ADC Parity Control Registers" group.long 0x180++0x03 line.long 0x00 "ADPARCR,Parity Control Register" bitfld.long 0x00 8. " TEST ,Parity bits map" "Not mapped,Mapped" bitfld.long 0x00 0.--3. " PARITY_ENA[3:0] ,Enable/disable parity checking" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" rgroup.long 0x184++0x03 line.long 0x00 "ADPARADDR,Parity Address" hexmask.long.word 0x00 2.--11. 0x04 " ERROR_ADDRESS ,ERROR ADDRESS" tree.end width 16. textline " " group.long 0x188++0x03 line.long 0x00 "ADPWRUPDLYCTRL,Power-Up Delay Control Register" hexmask.long.word 0x00 0.--9. 1. " PWRUP_DLY[9-0] ,Number of VCLK cycles to wait" sif (cpu()=="RM42L432"||cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE"||cpu()=="RM57L843-ZWT") width 20. tree "ADC Selection/count Registers" group.long 0x190++0x0B line.long 0x00 "ADEVCHNSELMODECTRL,ADC Event Group Channel Selection Mode Control Register" bitfld.long 0x00 0.--3. " EV_ENH_CHNSEL_MODE_EN ,Enable enhanced channel selection mode for event group" "No effect,No effect,No effect,No effect,No effect,Disabled,No effect,No effect,No effect,No effect,Enabled,No effect,No effect,No effect,No effect,No effect" line.long 0x04 "ADG1CHNSELMODECTRL,ADC Group1 Channel Selection Mode Control Register" bitfld.long 0x04 0.--3. " G1_ENH_CHNSEL_MODE_EN ,Enable enhanced channel selection mode for event group" "No effect,No effect,No effect,No effect,No effect,Disabled,No effect,No effect,No effect,No effect,Enabled,No effect,No effect,No effect,No effect,No effect" line.long 0x08 "ADG2CHNSELMODECTRL,ADC Group2 Channel Selection Mode Control Register" bitfld.long 0x08 0.--3. " G2_ENH_CHNSEL_MODE_EN ,Enable enhanced channel selection mode for event group" "No effect,No effect,No effect,No effect,No effect,Disabled,No effect,No effect,No effect,No effect,Enabled,No effect,No effect,No effect,No effect,No effect" group.long 0x19C++0x17 line.long 0x00 "ADEVCURRCOUNT,ADC Event Group Current Count Register" bitfld.long 0x00 0.--4. " EV_CURRENT_COUNT ,CURRENT_COUNT value for the event group conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "ADEVMAXCOUNT,ADC Event Group Maximum Count Register" bitfld.long 0x04 0.--4. " EV_MAX_COUNT ,MAX_COUNT value for the event group conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "ADG1CURRCOUNT,ADC Group1 Current Count Register" bitfld.long 0x08 0.--4. " G1_CURRENT_COUNT ,CURRENT_COUNT value for the group1 conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "ADG1MAXCOUNT,ADC Group1 Maximum Count Register" bitfld.long 0x0C 0.--4. " G1_MAX_COUNT ,MAX_COUNT value for the group1 conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "ADG2CURRCOUNT,ADC Group2 Current Count Register" bitfld.long 0x10 0.--4. " G2_CURRENT_COUNT ,CURRENT_COUNT value for the group2 conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x14 "ADG2MAXCOUNT,ADC Group2 Maximum Count Register" bitfld.long 0x14 0.--4. " G2_MAX_COUNT ,MAX_COUNT value for the group2 conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end endif width 0x0B tree.end else tree "MIBADC1" base ad:0xFFF7C000 width 12. group.long 0x00++0x03 line.long 0x00 "ADRSTCR,ADC Reset Control Register" bitfld.long 0x00 0. " RESET ,ADC reset" "No reset,Reset" group.long 0x04++0x03 line.long 0x00 "ADOPMODECR,ADC Operating Mode Control Register" bitfld.long 0x00 31. " 10/12BIT ,Resolution of the ADC core select" "10-bit,12-bit" bitfld.long 0x00 24. " COS ,ADCLK halt/continue when the emulation system enters suspend mode" "Halted,Continue" textline " " bitfld.long 0x00 17.--20. " CHNTESTEN ,Enable the input channels impedance measurement mode" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" bitfld.long 0x00 16. " RAMTESTEN ,Enable the ADC results RAM test mode" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " POWERDOWN ,ADC core power down" "Not powered down,Powered down" bitfld.long 0x00 4. " IDLEPWRDN ,ADC power down when idle" "Not powered down,Powered down" textline " " bitfld.long 0x00 0. " ADCEN ,ADC conversions enable" "Disabled,Enabled" group.long 0x08++0x03 line.long 0x00 "CLOCKCR,Clock Prescaler" bitfld.long 0x00 0.--4. " PS[4:0] ,ADC clock prescaler" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles" sif (cpuis("RM48L950*")||cpu()=="RM57L843-ZWT") if (((d.l(ad:0xFFF7C000+0x0C))&0x1020001)==0x1000000) group.long 0x0C++0x03 line.long 0x00 "ADCALCR,Calibration Conversion Register" bitfld.long 0x00 24. " SELF_TEST ,Self-Test enable" "Disabled,Enabled" bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started" textline " " bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full" bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " HILO ,Test and reference source selection" "(AD_REFHI*R1+AD_REFLO*R2)/(R1+R2),(AD_REFLO*R1+AD_REFHI*R2)/(R1+R2)" elif (((d.l(ad:0xFFF7C000+0x0C))&0x1020001)==0x01) group.long 0x0C++0x03 line.long 0x00 "ADCALCR,Calibration Conversion Register" bitfld.long 0x00 24. " SELF_TEST ,Self-Test enable" "Disabled,Enabled" bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started" textline " " bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full" bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " HILO ,Test and reference source selection" "(Ad_reflo via R1)||(R2 to vin),(Ad_refhi via R1)||(R2 to vin)" elif (((d.l(ad:0xFFF7C000+0x0C))&0x1020001)==0x1020000) group.long 0x0C++0x03 line.long 0x00 "ADCALCR,Calibration Conversion Register" bitfld.long 0x00 24. " SELF_TEST ,Self-Test enable" "Disabled,Enabled" bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started" textline " " bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full" bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " HILO ,Test and reference source selection" "AD_REFLO,AD_REFHI" elif (((d.l(ad:0xFFF7C000+0x0C))&0x1020001)==0x20001) group.long 0x0C++0x03 line.long 0x00 "ADCALCR,Calibration Conversion Register" bitfld.long 0x00 24. " SELF_TEST ,Self-Test enable" "Disabled,Enabled" bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started" textline " " bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full" bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " HILO ,Test and reference source selection" "(Ad_reflo via R1)||(R2 to vin),(Ad_refhi via R1)||(R2 to vin)" else group.long 0x0C++0x03 line.long 0x00 "ADCALCR,Calibration Conversion Register" bitfld.long 0x00 24. " SELF_TEST ,Self-Test enable" "Disabled,Enabled" bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started" textline " " bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full" bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled" endif else if (((d.l(ad:0xFFF7C000+0x0C))&0x1000201)==0x01) group.long 0x0C++0x03 line.long 0x00 "ADCALCR,Calibration Conversion Register" bitfld.long 0x00 24. " SELF_TEST ,Self-Test enable" "Disabled,Enabled" bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started" textline " " bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full" textline " " bitfld.long 0x00 8. " HILO ,Test and reference source selection" "(AD_REFHI*R1+AD_REFLO*R2)/(R1+R2),(AD_REFLO*R1+AD_REFHI*R2)/(R1+R2)" textline " " bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled" elif (((d.l(ad:0xFFF7C000+0x0C))&0x1000201)==0x1000000) group.long 0x0C++0x03 line.long 0x00 "ADCALCR,Calibration Conversion Register" bitfld.long 0x00 24. " SELF_TEST ,Self-Test enable" "Disabled,Enabled" bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started" textline " " bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full" textline " " bitfld.long 0x00 8. " HILO ,Test and reference source selection" "(Ad_reflo via R1)||(R2 to vin),(Ad_refhi via R1)||(R2 to vin)" textline " " bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled" elif (((d.l(ad:0xFFF7C000+0x0C))&0x1000201)==0x201) group.long 0x0C++0x03 line.long 0x00 "ADCALCR,Calibration Conversion Register" bitfld.long 0x00 24. " SELF_TEST ,Self-Test enable" "Disabled,Enabled" bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started" textline " " bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full" textline " " bitfld.long 0x00 8. " HILO ,Test and reference source selection" "AD_REFLO,AD_REFHI" textline " " bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled" elif (((d.l(ad:0xFFF7C000+0x0C))&0x1000201)==0x1000200) group.long 0x0C++0x03 line.long 0x00 "ADCALCR,Calibration Conversion Register" bitfld.long 0x00 24. " SELF_TEST ,Self-Test enable" "Disabled,Enabled" bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started" textline " " bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full" textline " " bitfld.long 0x00 8. " HILO ,Test and reference source selection" "(Ad_reflo via R1)||(R2 to vin),(Ad_refhi via R1)||(R2 to vin)" textline " " bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled" else group.long 0x0C++0x03 line.long 0x00 "ADCALCR,Calibration Conversion Register" bitfld.long 0x00 24. " SELF_TEST ,Self-Test enable" "Disabled,Enabled" bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started" textline " " bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full" textline " " textline " " bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled" endif endif group.long 0x10++0x03 line.long 0x00 "ADEVMODECR,EV MODE Control Register" bitfld.long 0x00 16. " NORESETONCHNSEL ,No event group results memory reset on new channel select" "Reset,No reset" bitfld.long 0x00 8.--9. " EV_DATA_FMT ,Event group (Read) data format" "12 bit,10 bit,8 bit,?..." textline " " bitfld.long 0x00 5. " EV_CHID ,Channel ID mode for the event group" "Forced to 0,ID of A/D channel" bitfld.long 0x00 4. " OVR_EV_RAM_IGN ,Overrun event group RAM ignore" "Not ignored,Ignored" textline " " bitfld.long 0x00 2. " EV8BIT ,Event group 8-bit result mode" "10-bit,8-bit" bitfld.long 0x00 1. " EV_MODE ,Event mode" "Single,Continuous" textline " " bitfld.long 0x00 0. " FRZ_EV ,Freeze conversion event group" "Completed,Frozen" group.long 0x14++0x03 line.long 0x00 "ADG1MODECR,G1 MODE Control Register" bitfld.long 0x00 16. " NORESETONCHNSEL ,No group1 results memory reset on new channel select" "Reset,No reset" bitfld.long 0x00 8.--9. " G1_DATA_FMT ,Group1 (Read) data format" "12 bit,10 bit,8 bit,?..." textline " " bitfld.long 0x00 5. " G1_CHID ,Channel ID mode for the group 1" "Forced to 0,ID of A/D channel" bitfld.long 0x00 4. " OVR_G1_RAM_IGN ,Overrun group 1 RAM ignore" "Not ignored,Ignored" textline " " bitfld.long 0x00 3. " G1_HW_TRIG ,Group 1 hardware triggered" "Software,Hardware" bitfld.long 0x00 2. " G1_8BIT ,Group1 8-bit result mode" "10-bit,8-bit" textline " " bitfld.long 0x00 1. " G1_MODE ,Group 1 mode" "Single,Continuous" bitfld.long 0x00 0. " FRZ_G1 ,Freeze conversion group 1" "Completed,Frozen" group.long 0x18++0x03 line.long 0x00 "ADG2MODECR,G2 MODE Control Register" bitfld.long 0x00 16. " NORESETONCHNSEL ,No group2 results memory reset on new channel select" "Reset,No reset" bitfld.long 0x00 8.--9. " G2_DATA_FMT ,Group2 (Read) data format" "12 bit,10 bit,8 bit,?..." textline " " bitfld.long 0x00 5. " G2_CHID ,Channel ID mode for the group 2" "Forced to 0,ID of A/D channel" bitfld.long 0x00 4. " OVR_G2_RAM_IGN ,Overrun group 2 RAM ignore" "Not ignored,Ignored" textline " " bitfld.long 0x00 3. " G2_HW_TRIG ,Group 2 hardware triggered" "Software,Hardware" bitfld.long 0x00 2. " G2_8BIT ,Group2 8-bit result mode" "10-bit,8-bit" textline " " bitfld.long 0x00 1. " G2_MODE ,Group 2 mode" "Single,Continuous" bitfld.long 0x00 0. " FRZ_G2 ,Freeze conversion group 2" "Completed,Frozen" group.long 0x1C++0x03 line.long 0x00 "ADEVSRC,Event Group Trigger Source Select" bitfld.long 0x00 4. " EV_EDG_BOTH ,Event group trigger on both edges" "EV_EDGE_SEL bit,Rising or falling" textline " " bitfld.long 0x00 3. " EV_EDG_SEL ,Event group trigger edge polarity select" "High/low,Low/high" sif (cpu()=="RM42L432") bitfld.long 0x00 0.--2. " EVSRC[2:0] ,Event group trigger source select" "ADEVT,N2HET1[8],N2HET1[10],RTI compare 0,N2HET1[12],N2HET1[14],N2HET1[17],N2HET1[19]" else bitfld.long 0x00 0.--2. " EVSRC[2:0] ,Event group trigger source select" "AD1EVT,N2HET1[8]/[5],N2HET1[10]/[27],RTI compare 0,N2HET1[12]/[17],N2HET1[14]/[19],GIOB[0]/N2HET1[11],GIOB[1]/N2HET2[13]" endif group.long 0x20++0x03 line.long 0x00 "ADG1SRC,Group 1 Trigger Source Select" bitfld.long 0x00 4. " G1_EDG_BOTH ,Group1 trigger on both edges" "G1_EDG_SEL bit,Rising or falling" textline " " bitfld.long 0x00 3. " G1_EDG_SEL ,ADC group 1 trigger edge select" "High/low,Low/high" sif (cpu()=="RM42L432") bitfld.long 0x00 0.--2. " G1SRC[2:0] ,Group 1 trigger source select" "ADEVT,N2HET1[8],N2HET1[10],RTI compare 0,N2HET1[12],N2HET1[14],N2HET1[17],N2HET2[19]" else bitfld.long 0x00 0.--2. " G1SRC[2:0] ,Group 1 trigger source select" "AD1EVT,N2HET1[8]/[5],N2HET1[10]/[27],RTI compare 0,N2HET1[12]/[17],N2HET1[14]/[19],GIOB[0]/N2HET1[11],GIOB[1]/N2HET2[13]" endif group.long 0x24++0x03 line.long 0x00 "ADG2SRC,Group 2 Trigger Source Select" bitfld.long 0x00 4. " G2_EDG_BOTH ,Group2 trigger on both edges" "G2_EDG_SEL bit,Rising or falling" textline " " bitfld.long 0x00 3. " G2_EDG_SEL ,ADC group 2 trigger edge select" "High/low,Low/high" sif (cpu()=="RM42L432") bitfld.long 0x00 0.--2. " G2SRC[2:0] ,Group 2 trigger source select" "ADEVT,N2HET1[8],N2HET1[10],RTI compare 0,N2HET1[12],N2HET1[14],N2HET1[17],N2HET2[19]" else bitfld.long 0x00 0.--2. " G2SRC[2:0] ,Group 2 trigger source select" "AD1EVT,N2HET1[8]/[5],N2HET1[10]/[27],RTI compare 0,N2HET1[12]/[17],N2HET1[14]/[19],GIOB[0]/N2HET1[11],GIOB[1]/N2HET2[13]" endif group.long 0x28++0x03 line.long 0x00 "ADEVINTENA,Event Group Interrupt Enable" bitfld.long 0x00 3. " EV_END_INT_EN ,Event group conversion end interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " EV_OVR_INT_EN ,Event group memory overrun interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " EV_THR_INT_EN ,Event group memory threshold interrupt enable" "Disabled,Enabled" group.long 0x2C++0x03 line.long 0x00 "ADG1INTENA,Group 1 Interrupt Enable" bitfld.long 0x00 3. " G1_END_INT_EN ,Event group conversion end interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " G1_OVR_INT_EN ,Group 1 memory overrun interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " G1_THR_INT_EN ,Group 1 memory threshold interrupt enable" "Disabled,Enabled" group.long 0x30++0x03 line.long 0x00 "ADG2INTENA,Group 2 Interrupt Enable" bitfld.long 0x00 3. " G2_END_INT_EN ,Event group conversion end interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " G2_OVR_INT_EN ,Group 2 memory overrun interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " G2_THR_INT_EN ,Group 2 memory threshold interrupt enable" "Disabled,Enabled" hgroup.long 0x34++0x0B hide.long 0x00 "ADEVINTFLG,Event Group Interrupt Flag" in hide.long 0x04 "ADG1INTFLG,Group 1 Interrupt Flag" in hide.long 0x08 "ADG2INTFLG,Group 2 Interrupt Flag" in group.long 0x40++0x03 line.long 0x00 "ADEVINTCR,Event Group Interrupt Threshold Counter" hexmask.long.byte 0x00 9.--15. 1. " SIGN_EXTENSION ,Sign extension" hexmask.long.word 0x00 0.--8. 1. " EVTHR[8:0] ,Event group interrupt threshold counter" group.long 0x44++0x03 line.long 0x00 "ADG1INTCR,Group 1 Interrupt Threshold Counter" hexmask.long.byte 0x00 9.--15. 1. " SIGN_EXTENSION ,Sign extension" hexmask.long.word 0x00 0.--8. 1. " G1THR[8:0] ,Group 1 interrupt threshold counter" group.long 0x48++0x03 line.long 0x00 "ADG2INTCR,Group 2 Interrupt Threshold Counter" hexmask.long.byte 0x00 9.--15. 1. " SIGN_EXTENSION ,Sign extension" hexmask.long.word 0x00 0.--8. 1. " G2THR[8:0] ,Group 2 interrupt threshold counter" group.long 0x4C++0x03 line.long 0x00 "ADEVDMACR,Event Group DMA Control Register" hexmask.long.word 0x00 16.--24. 1. " EVBLOCKS[8:0] ,Number of event group memory buffers to be transferred" bitfld.long 0x00 3. " DMA_EV_END ,Event group conversion end DMA transfer enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " EV_BLK_XFER ,Event group block DMA transfer enable" "Disabled,Enabled" bitfld.long 0x00 0. " EV_DMA_EN ,Event group DMA transfer enable" "Disabled,Enabled" group.long 0x50++0x03 line.long 0x00 "ADG1DMACR,Group 1 DMA Control Register" hexmask.long.word 0x00 16.--24. 1. " G1BLOCKS[8:0] ,Number of group 1 memory buffers to be transferred" bitfld.long 0x00 3. " DMA_G1_END ,Group1 conversion end DMA transfer enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " G1_BLK_XFER ,Group 1 block DMA transfer enable" "Disabled,Enabled" bitfld.long 0x00 0. " G1_DMA_EN ,Group 1 DMA transfer enable" "Disabled,Enabled" group.long 0x54++0x03 line.long 0x00 "ADG2DMACR,Group 2 DMA Control Register" hexmask.long.word 0x00 16.--24. 1. " G2BLOCKS[8:0] ,Number of group 2 memory buffers to be transferred" bitfld.long 0x00 3. " DMA_G2_END ,Group2 conversion end DMA transfer enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " G2_BLK_XFER ,Group 2 block DMA transfer enable" "Disabled,Enabled" bitfld.long 0x00 0. " G2_DMA_EN ,Group 2 DMA transfer enable" "Disabled,Enabled" group.long 0x58++0x03 line.long 0x00 "ADBNDCR,Buffer Boundary Control Register" hexmask.long.word 0x00 16.--24. 1. " BNDA[8:0] ,Buffer boundary A" hexmask.long.word 0x00 0.--8. 1. " BNDB[8:0] ,Buffer boundary B" group.long 0x5C++0x03 line.long 0x00 "ADBNDEND,Buffer End Boundary" bitfld.long 0x00 16. " BUF_INIT_ACTIVE ,Indicates the status of the ADC RAM intialization process" "Not initialized,Initialized" bitfld.long 0x00 0.--2. " BNDEND[2:0] ,Buffer end boundary" "16 words,32 words,64 words,128 words,192 words,256 words,512 words,1024 words" width 10. tree "ADC Sample Control Registers" group.long 0x60++0x03 line.long 0x00 "ADEVSAMP,Event Group Sampling Time Configuration" hexmask.long.word 0x00 0.--11. 1. " EVACQ[11:0] ,Event group acquisition time" group.long 0x64++0x03 line.long 0x00 "ADG1SAMP,Group1 Sampling Time Configuration" hexmask.long.word 0x00 0.--11. 1. " G1ACQ[11:0] ,Group 1 acquisition time" group.long 0x68++0x03 line.long 0x00 "ADG2SAMP,Group2 Sampling Time Configuration" hexmask.long.word 0x00 0.--11. 1. " G2ACQ[11:0] ,Group 2 acquisition time" tree.end width 8. tree "ADC Status Registers" group.long 0x6C++0x03 line.long 0x00 "ADEVSR,Event Group Status Register" bitfld.long 0x00 3. " EV_MEM_EMPTY ,Event group memory empty" "Not empty,Empty" bitfld.long 0x00 2. " EV_BUSY ,Event group Conversion-Busy flag" "Not active,Busy" bitfld.long 0x00 1. " EV_STOP ,Event group conversion stopped flag" "Not frozen,Frozen" textline " " eventfld.long 0x00 0. " EV_END ,Event Conversion-Ended flag R/W" "Not completed,Completed" group.long 0x70++0x03 line.long 0x00 "ADG1SR,Group 1 Status Register" bitfld.long 0x00 3. " G1_MEM_EMPTY ,Group 1 memory empty" "Not empty,Empty" bitfld.long 0x00 2. " G1_BUSY ,Group 1 Conversion-Busy flag" "Not active,Busy" bitfld.long 0x00 1. " G1_STOP ,Group 1 conversion stopped flag" "Not frozen,Frozen" textline " " eventfld.long 0x00 0. " G1_END ,Group 1 Conversion-Ended flag" "Not completed,Completed" group.long 0x74++0x03 line.long 0x00 "ADG2SR,Group 2 Status Register" bitfld.long 0x00 3. " G2_MEM_EMPTY ,Group 2 memory empty" "Not empty,Empty" bitfld.long 0x00 2. " G2_BUSY ,Group 2 Conversion-Busy flag" "Not active,Busy" bitfld.long 0x00 1. " G2_STOP ,Group 2 conversion stopped flag" "Not frozen,Frozen" textline " " eventfld.long 0x00 0. " G2_END ,Group 2 conversion-ended flag" "Not completed,Completed" tree.end width 9. tree "ADC Selection Control Registers" sif cpu()=="RM57L843-ZWT" group.long 0x78++0x03 line.long 0x00 "ADEVSEL,Event Group Select Register" bitfld.long 0x00 31. " EVCHNSEL[31] ,A/D event channel 31 selection bit" "Not converted,Converted" bitfld.long 0x00 30. " EVCHNSEL[30] ,A/D event channel 30 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 29. " EVCHNSEL[29] ,A/D event channel 29 selection bit" "Not converted,Converted" bitfld.long 0x00 28. " EVCHNSEL[28] ,A/D event channel 28 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 27. " EVCHNSEL[27] ,A/D event channel 27 selection bit" "Not converted,Converted" bitfld.long 0x00 26. " EVCHNSEL[26] ,A/D event channel 26 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 25. " EVCHNSEL[25] ,A/D event channel 25 selection bit" "Not converted,Converted" bitfld.long 0x00 24. " EVCHNSEL[24] ,A/D event channel 24 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 23. " EVCHNSEL[23] ,A/D event channel 23 selection bit" "Not converted,Converted" bitfld.long 0x00 22. " EVCHNSEL[22] ,A/D event channel 22 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 21. " EVCHNSEL[21] ,A/D event channel 21 selection bit" "Not converted,Converted" bitfld.long 0x00 20. " EVCHNSEL[20] ,A/D event channel 20 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 19. " EVCHNSEL[19] ,A/D event channel 19 selection bit" "Not converted,Converted" bitfld.long 0x00 18. " EVCHNSEL[18] ,A/D event channel 18 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 17. " EVCHNSEL[17] ,A/D event channel 17 selection bit" "Not converted,Converted" bitfld.long 0x00 16. " EVCHNSEL[16] ,A/D event channel 16 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 15. " EVCHNSEL[15] ,A/D event channel 15 selection bit" "Not converted,Converted" bitfld.long 0x00 14. " EVCHNSEL[14] ,A/D event channel 14 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 13. " EVCHNSEL[13] ,A/D event channel 13 selection bit" "Not converted,Converted" bitfld.long 0x00 12. " EVCHNSEL[12] ,A/D event channel 12 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 11. " EVCHNSEL[11] ,A/D event channel 11 selection bit" "Not converted,Converted" bitfld.long 0x00 10. " EVCHNSEL[10] ,A/D event channel 10 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 9. " EVCHNSEL[9] ,A/D event channel 9 selection bit" "Not converted,Converted" bitfld.long 0x00 8. " EVCHNSEL[8] ,A/D event channel 8 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 7. " EVCHNSEL[7] ,A/D event channel 7 selection bit" "Not converted,Converted" bitfld.long 0x00 6. " EVCHNSEL[6] ,A/D event channel 6 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 5. " EVCHNSEL[5] ,A/D event channel 5 selection bit" "Not converted,Converted" bitfld.long 0x00 4. " EVCHNSEL[4] ,A/D event channel 4 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 3. " EVCHNSEL[3] ,A/D event channel 3 selection bit" "Not converted,Converted" bitfld.long 0x00 2. " EVCHNSEL[2] ,A/D event channel 2 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 1. " EVCHNSEL[1] ,A/D event channel 1 selection bit" "Not converted,Converted" bitfld.long 0x00 0. " EVCHNSEL[0] ,A/D event channel 0 selection bit" "Not converted,Converted" group.long 0x7C++0x03 line.long 0x00 "ADG1SEL,Group 1 Select Register" bitfld.long 0x00 31. " G1CHNSEL[31] ,A/D channel 31 enable bit" "Not converted,Converted" bitfld.long 0x00 30. " G1CHNSEL[30] ,A/D channel 30 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 29. " G1CHNSEL[29] ,A/D channel 29 enable bit" "Not converted,Converted" bitfld.long 0x00 28. " G1CHNSEL[28] ,A/D channel 28 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 27. " G1CHNSEL[27] ,A/D channel 27 enable bit" "Not converted,Converted" bitfld.long 0x00 26. " G1CHNSEL[26] ,A/D channel 26 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 25. " G1CHNSEL[25] ,A/D channel 25 enable bit" "Not converted,Converted" bitfld.long 0x00 24. " G1CHNSEL[24] ,A/D channel 24 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 23. " G1CHNSEL[23] ,A/D channel 23 enable bit" "Not converted,Converted" bitfld.long 0x00 22. " G1CHNSEL[22] ,A/D channel 22 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 21. " G1CHNSEL[21] ,A/D channel 21 enable bit" "Not converted,Converted" bitfld.long 0x00 20. " G1CHNSEL[20] ,A/D channel 20 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 19. " G1CHNSEL[19] ,A/D channel 19 enable bit" "Not converted,Converted" bitfld.long 0x00 18. " G1CHNSEL[18] ,A/D channel 18 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 17. " G1CHNSEL[17] ,A/D channel 17 enable bit" "Not converted,Converted" bitfld.long 0x00 16. " G1CHNSEL[16] ,A/D channel 16 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 15. " G1CHNSEL[15] ,A/D channel 15 enable bit" "Not converted,Converted" bitfld.long 0x00 14. " G1CHNSEL[14] ,A/D channel 14 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 13. " G1CHNSEL[13] ,A/D channel 13 enable bit" "Not converted,Converted" bitfld.long 0x00 12. " G1CHNSEL[12] ,A/D channel 12 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 11. " G1CHNSEL[11] ,A/D channel 11 enable bit" "Not converted,Converted" bitfld.long 0x00 10. " G1CHNSEL[10] ,A/D channel 10 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 9. " G1CHNSEL[9] ,A/D channel 9 enable bit" "Not converted,Converted" bitfld.long 0x00 8. " G1CHNSEL[8] ,A/D channel 8 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 7. " G1CHNSEL[7] ,A/D channel 7 enable bit" "Not converted,Converted" bitfld.long 0x00 6. " G1CHNSEL[6] ,A/D channel 6 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 5. " G1CHNSEL[5] ,A/D channel 5 enable bit" "Not converted,Converted" bitfld.long 0x00 4. " G1CHNSEL[4] ,A/D channel 4 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 3. " G1CHNSEL[3] ,A/D channel 3 enable bit" "Not converted,Converted" bitfld.long 0x00 2. " G1CHNSEL[2] ,A/D channel 2 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 1. " G1CHNSEL[1] ,A/D channel 1 enable bit" "Not converted,Converted" bitfld.long 0x00 0. " G1CHNSEL[0] ,A/D channel 0 enable bit" "Not converted,Converted" group.long 0x80++0x03 line.long 0x00 "ADG2SEL,Group 2 Select Register" bitfld.long 0x00 31. " G2CHNSEL[31] ,A/D channel 31 enable bit" "Not converted,Converted" bitfld.long 0x00 30. " G2CHNSEL[30] ,A/D channel 30 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 29. " G2CHNSEL[29] ,A/D channel 29 enable bit" "Not converted,Converted" bitfld.long 0x00 28. " G2CHNSEL[28] ,A/D channel 28 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 27. " G2CHNSEL[27] ,A/D channel 27 enable bit" "Not converted,Converted" bitfld.long 0x00 26. " G2CHNSEL[26] ,A/D channel 26 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 25. " G2CHNSEL[25] ,A/D channel 25 enable bit" "Not converted,Converted" bitfld.long 0x00 24. " G2CHNSEL[24] ,A/D channel 24 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 23. " G2CHNSEL[23] ,A/D channel 23 enable bit" "Not converted,Converted" bitfld.long 0x00 22. " G2CHNSEL[22] ,A/D channel 22 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 21. " G2CHNSEL[21] ,A/D channel 21 enable bit" "Not converted,Converted" bitfld.long 0x00 20. " G2CHNSEL[20] ,A/D channel 20 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 19. " G2CHNSEL[19] ,A/D channel 19 enable bit" "Not converted,Converted" bitfld.long 0x00 18. " G2CHNSEL[18] ,A/D channel 18 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 17. " G2CHNSEL[17] ,A/D channel 17 enable bit" "Not converted,Converted" bitfld.long 0x00 16. " G2CHNSEL[16] ,A/D channel 16 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 15. " G2CHNSEL[15] ,A/D channel 15 enable bit" "Not converted,Converted" bitfld.long 0x00 14. " G2CHNSEL[14] ,A/D channel 14 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 13. " G2CHNSEL[13] ,A/D channel 13 enable bit" "Not converted,Converted" bitfld.long 0x00 12. " G2CHNSEL[12] ,A/D channel 12 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 11. " G2CHNSEL[11] ,A/D channel 11 enable bit" "Not converted,Converted" bitfld.long 0x00 10. " G2CHNSEL[10] ,A/D channel 10 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 9. " G2CHNSEL[9] ,A/D channel 9 enable bit" "Not converted,Converted" bitfld.long 0x00 8. " G2CHNSEL[8] ,A/D channel 8 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 7. " G2CHNSEL[7] ,A/D channel 7 enable bit" "Not converted,Converted" bitfld.long 0x00 6. " G2CHNSEL[6] ,A/D channel 6 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 5. " G2CHNSEL[5] ,A/D channel 5 enable bit" "Not converted,Converted" bitfld.long 0x00 4. " G2CHNSEL[4] ,A/D channel 4 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 3. " G2CHNSEL[3] ,A/D channel 3 enable bit" "Not converted,Converted" bitfld.long 0x00 2. " G2CHNSEL[2] ,A/D channel 2 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 1. " G2CHNSEL[1] ,A/D channel 1 enable bit" "Not converted,Converted" bitfld.long 0x00 0. " G2CHNSEL[0] ,A/D channel 0 enable bit" "Not converted,Converted" else group.long 0x78++0x03 line.long 0x00 "ADEVSEL,Event Group Select Register" bitfld.long 0x00 23. " EVCHNSEL[23] ,A/D event channel 23 selection bit" "Not converted,Converted" bitfld.long 0x00 22. " EVCHNSEL[22] ,A/D event channel 22 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 21. " EVCHNSEL[21] ,A/D event channel 21 selection bit" "Not converted,Converted" bitfld.long 0x00 20. " EVCHNSEL[20] ,A/D event channel 20 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 19. " EVCHNSEL[19] ,A/D event channel 19 selection bit" "Not converted,Converted" bitfld.long 0x00 18. " EVCHNSEL[18] ,A/D event channel 18 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 17. " EVCHNSEL[17] ,A/D event channel 17 selection bit" "Not converted,Converted" bitfld.long 0x00 16. " EVCHNSEL[16] ,A/D event channel 16 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 15. " EVCHNSEL[15] ,A/D event channel 15 selection bit" "Not converted,Converted" bitfld.long 0x00 14. " EVCHNSEL[14] ,A/D event channel 14 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 13. " EVCHNSEL[13] ,A/D event channel 13 selection bit" "Not converted,Converted" bitfld.long 0x00 12. " EVCHNSEL[12] ,A/D event channel 12 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 11. " EVCHNSEL[11] ,A/D event channel 11 selection bit" "Not converted,Converted" bitfld.long 0x00 10. " EVCHNSEL[10] ,A/D event channel 10 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 9. " EVCHNSEL[9] ,A/D event channel 9 selection bit" "Not converted,Converted" bitfld.long 0x00 8. " EVCHNSEL[8] ,A/D event channel 8 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 7. " EVCHNSEL[7] ,A/D event channel 7 selection bit" "Not converted,Converted" bitfld.long 0x00 6. " EVCHNSEL[6] ,A/D event channel 6 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 5. " EVCHNSEL[5] ,A/D event channel 5 selection bit" "Not converted,Converted" bitfld.long 0x00 4. " EVCHNSEL[4] ,A/D event channel 4 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 3. " EVCHNSEL[3] ,A/D event channel 3 selection bit" "Not converted,Converted" bitfld.long 0x00 2. " EVCHNSEL[2] ,A/D event channel 2 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 1. " EVCHNSEL[1] ,A/D event channel 1 selection bit" "Not converted,Converted" bitfld.long 0x00 0. " EVCHNSEL[0] ,A/D event channel 0 selection bit" "Not converted,Converted" group.long 0x7C++0x03 line.long 0x00 "ADG1SEL,Group 1 Select Register" bitfld.long 0x00 23. " G1CHNSEL[23] ,A/D channel 23 enable bit" "Not converted,Converted" bitfld.long 0x00 22. " G1CHNSEL[22] ,A/D channel 22 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 21. " G1CHNSEL[21] ,A/D channel 21 enable bit" "Not converted,Converted" bitfld.long 0x00 20. " G1CHNSEL[20] ,A/D channel 20 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 19. " G1CHNSEL[19] ,A/D channel 19 enable bit" "Not converted,Converted" bitfld.long 0x00 18. " G1CHNSEL[18] ,A/D channel 18 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 17. " G1CHNSEL[17] ,A/D channel 17 enable bit" "Not converted,Converted" bitfld.long 0x00 16. " G1CHNSEL[16] ,A/D channel 16 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 15. " G1CHNSEL[15] ,A/D channel 15 enable bit" "Not converted,Converted" bitfld.long 0x00 14. " G1CHNSEL[14] ,A/D channel 14 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 13. " G1CHNSEL[13] ,A/D channel 13 enable bit" "Not converted,Converted" bitfld.long 0x00 12. " G1CHNSEL[12] ,A/D channel 12 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 11. " G1CHNSEL[11] ,A/D channel 11 enable bit" "Not converted,Converted" bitfld.long 0x00 10. " G1CHNSEL[10] ,A/D channel 10 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 9. " G1CHNSEL[9] ,A/D channel 9 enable bit" "Not converted,Converted" bitfld.long 0x00 8. " G1CHNSEL[8] ,A/D channel 8 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 7. " G1CHNSEL[7] ,A/D channel 7 enable bit" "Not converted,Converted" bitfld.long 0x00 6. " G1CHNSEL[6] ,A/D channel 6 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 5. " G1CHNSEL[5] ,A/D channel 5 enable bit" "Not converted,Converted" bitfld.long 0x00 4. " G1CHNSEL[4] ,A/D channel 4 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 3. " G1CHNSEL[3] ,A/D channel 3 enable bit" "Not converted,Converted" bitfld.long 0x00 2. " G1CHNSEL[2] ,A/D channel 2 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 1. " G1CHNSEL[1] ,A/D channel 1 enable bit" "Not converted,Converted" bitfld.long 0x00 0. " G1CHNSEL[0] ,A/D channel 0 enable bit" "Not converted,Converted" group.long 0x80++0x03 line.long 0x00 "ADG2SEL,Group 2 Select Register" bitfld.long 0x00 23. " G2CHNSEL[23] ,A/D channel 23 enable bit" "Not converted,Converted" bitfld.long 0x00 22. " G2CHNSEL[22] ,A/D channel 22 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 21. " G2CHNSEL[21] ,A/D channel 21 enable bit" "Not converted,Converted" bitfld.long 0x00 20. " G2CHNSEL[20] ,A/D channel 20 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 19. " G2CHNSEL[19] ,A/D channel 19 enable bit" "Not converted,Converted" bitfld.long 0x00 18. " G2CHNSEL[18] ,A/D channel 18 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 17. " G2CHNSEL[17] ,A/D channel 17 enable bit" "Not converted,Converted" bitfld.long 0x00 16. " G2CHNSEL[16] ,A/D channel 16 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 15. " G2CHNSEL[15] ,A/D channel 15 enable bit" "Not converted,Converted" bitfld.long 0x00 14. " G2CHNSEL[14] ,A/D channel 14 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 13. " G2CHNSEL[13] ,A/D channel 13 enable bit" "Not converted,Converted" bitfld.long 0x00 12. " G2CHNSEL[12] ,A/D channel 12 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 11. " G2CHNSEL[11] ,A/D channel 11 enable bit" "Not converted,Converted" bitfld.long 0x00 10. " G2CHNSEL[10] ,A/D channel 10 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 9. " G2CHNSEL[9] ,A/D channel 9 enable bit" "Not converted,Converted" bitfld.long 0x00 8. " G2CHNSEL[8] ,A/D channel 8 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 7. " G2CHNSEL[7] ,A/D channel 7 enable bit" "Not converted,Converted" bitfld.long 0x00 6. " G2CHNSEL[6] ,A/D channel 6 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 5. " G2CHNSEL[5] ,A/D channel 5 enable bit" "Not converted,Converted" bitfld.long 0x00 4. " G2CHNSEL[4] ,A/D channel 4 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 3. " G2CHNSEL[3] ,A/D channel 3 enable bit" "Not converted,Converted" bitfld.long 0x00 2. " G2CHNSEL[2] ,A/D channel 2 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 1. " G2CHNSEL[1] ,A/D channel 1 enable bit" "Not converted,Converted" bitfld.long 0x00 0. " G2CHNSEL[0] ,A/D channel 0 enable bit" "Not converted,Converted" endif tree.end width 12. textline " " sif (cpuis("RM48L950*")||cpu()=="RM57L843-ZWT") if (((d.l(ad:0xFFF7C000+0x04))&0x80)==0x80) group.long 0x84++0x03 line.long 0x00 "ADCALR,Calibration Register" hexmask.long.word 0x00 0.--11. 1. " ADCALR[11:0] ,Calibration bits" else group.long 0x84++0x03 line.long 0x00 "ADCALR,Calibration Register" hexmask.long.word 0x00 0.--9. 1. " ADCALR[9:0] ,Calibration bits" endif else if (((d.l(ad:0xFFF7C000+0x04))&0x80000000)==0x80000000) group.long 0x84++0x03 line.long 0x00 "ADCALR,Calibration Register" hexmask.long.word 0x00 0.--11. 1. " ADCALR[11:0] ,Calibration bits" else group.long 0x84++0x03 line.long 0x00 "ADCALR,Calibration Register" hexmask.long.word 0x00 0.--9. 1. " ADCALR[9:0] ,Calibration bits" endif endif rgroup.long 0x88++0x03 line.long 0x00 "ADSMSTATE,State Machine Current State" bitfld.long 0x00 0.--3. " SMSTATE[3:0] ,ADC state machine current state" "Idle,Conv_ev,Conv_sw1,Conv_sw2,Conv_cal,Start_ev,Start_sw1,Start_sw2,Start_cal,Wait_ev,Wait_sw1,Wait_sw2,Wait_cal,?..." width 12. sif (cpu()=="RM57L843-ZWT") rgroup.long 0x8C++0x03 line.long 0x00 "ADLASTCONV,Last Conversion" bitfld.long 0x00 31. " LAST_CONV[31] ,Digital input channel 31" "Low,High" bitfld.long 0x00 30. " LAST_CONV[30] ,Digital input channel 30" "Low,High" bitfld.long 0x00 29. " LAST_CONV[29] ,Digital input channel 29" "Low,High" bitfld.long 0x00 28. " LAST_CONV[28] ,Digital input channel 28" "Low,High" textline " " bitfld.long 0x00 27. " LAST_CONV[27] ,Digital input channel 27" "Low,High" bitfld.long 0x00 26. " LAST_CONV[26] ,Digital input channel 26" "Low,High" bitfld.long 0x00 25. " LAST_CONV[25] ,Digital input channel 25" "Low,High" textline " " bitfld.long 0x00 24. " LAST_CONV[24] ,Digital input channel 24" "Low,High" textline " " bitfld.long 0x00 23. " LAST_CONV[23] ,Digital input channel 23" "Low,High" bitfld.long 0x00 22. " LAST_CONV[22] ,Digital input channel 22" "Low,High" bitfld.long 0x00 21. " LAST_CONV[21] ,Digital input channel 21" "Low,High" bitfld.long 0x00 20. " LAST_CONV[20] ,Digital input channel 20" "Low,High" textline " " bitfld.long 0x00 19. " LAST_CONV[19] ,Digital input channel 19" "Low,High" bitfld.long 0x00 18. " LAST_CONV[18] ,Digital input channel 18" "Low,High" bitfld.long 0x00 17. " LAST_CONV[17] ,Digital input channel 17" "Low,High" bitfld.long 0x00 16. " LAST_CONV[16] ,Digital input channel 16" "Low,High" textline " " bitfld.long 0x00 15. " LAST_CONV[15] ,Digital input channel 15" "Low,High" bitfld.long 0x00 14. " LAST_CONV[14] ,Digital input channel 14" "Low,High" bitfld.long 0x00 13. " LAST_CONV[13] ,Digital input channel 13" "Low,High" bitfld.long 0x00 12. " LAST_CONV[12] ,Digital input channel 12" "Low,High" textline " " bitfld.long 0x00 11. " LAST_CONV[11] ,Digital input channel 11" "Low,High" bitfld.long 0x00 10. " LAST_CONV[10] ,Digital input channel 10" "Low,High" bitfld.long 0x00 9. " LAST_CONV[9] ,Digital input channel 9" "Low,High" bitfld.long 0x00 8. " LAST_CONV[8] ,Digital input channel 8" "Low,High" textline " " bitfld.long 0x00 7. " LAST_CONV[7] ,Digital input channel 7" "Low,High" bitfld.long 0x00 6. " LAST_CONV[6] ,Digital input channel 6" "Low,High" bitfld.long 0x00 5. " LAST_CONV[5] ,Digital input channel 5" "Low,High" bitfld.long 0x00 4. " LAST_CONV[4] ,Digital input channel 4" "Low,High" textline " " bitfld.long 0x00 3. " LAST_CONV[3] ,Digital input channel 3" "Low,High" bitfld.long 0x00 2. " LAST_CONV[2] ,Digital input channel 2" "Low,High" bitfld.long 0x00 1. " LAST_CONV[1] ,Digital input channel 1" "Low,High" bitfld.long 0x00 0. " LAST_CONV[0] ,Digital input channel 0" "Low,High" else rgroup.long 0x8C++0x03 line.long 0x00 "ADLASTCONV,Last Conversion" bitfld.long 0x00 23. " LAST_CONV[23] ,Digital input channel 23" "Low,High" bitfld.long 0x00 22. " LAST_CONV[22] ,Digital input channel 22" "Low,High" bitfld.long 0x00 21. " LAST_CONV[21] ,Digital input channel 21" "Low,High" bitfld.long 0x00 20. " LAST_CONV[20] ,Digital input channel 20" "Low,High" textline " " bitfld.long 0x00 19. " LAST_CONV[19] ,Digital input channel 19" "Low,High" bitfld.long 0x00 18. " LAST_CONV[18] ,Digital input channel 18" "Low,High" bitfld.long 0x00 17. " LAST_CONV[17] ,Digital input channel 17" "Low,High" bitfld.long 0x00 16. " LAST_CONV[16] ,Digital input channel 16" "Low,High" textline " " bitfld.long 0x00 15. " LAST_CONV[15] ,Digital input channel 15" "Low,High" bitfld.long 0x00 14. " LAST_CONV[14] ,Digital input channel 14" "Low,High" bitfld.long 0x00 13. " LAST_CONV[13] ,Digital input channel 13" "Low,High" bitfld.long 0x00 12. " LAST_CONV[12] ,Digital input channel 12" "Low,High" textline " " bitfld.long 0x00 11. " LAST_CONV[11] ,Digital input channel 11" "Low,High" bitfld.long 0x00 10. " LAST_CONV[10] ,Digital input channel 10" "Low,High" bitfld.long 0x00 9. " LAST_CONV[9] ,Digital input channel 9" "Low,High" bitfld.long 0x00 8. " LAST_CONV[8] ,Digital input channel 8" "Low,High" textline " " bitfld.long 0x00 7. " LAST_CONV[7] ,Digital input channel 7" "Low,High" bitfld.long 0x00 6. " LAST_CONV[6] ,Digital input channel 6" "Low,High" bitfld.long 0x00 5. " LAST_CONV[5] ,Digital input channel 5" "Low,High" bitfld.long 0x00 4. " LAST_CONV[4] ,Digital input channel 4" "Low,High" textline " " bitfld.long 0x00 3. " LAST_CONV[3] ,Digital input channel 3" "Low,High" bitfld.long 0x00 2. " LAST_CONV[2] ,Digital input channel 2" "Low,High" bitfld.long 0x00 1. " LAST_CONV[1] ,Digital input channel 1" "Low,High" bitfld.long 0x00 0. " LAST_CONV[0] ,Digital input channel 0" "Low,High" endif width 15. tree "ADC Buffer Control Registers" hgroup.long 0x90++0x1F hide.long 0x00 "ADEVBUFFER0,Event Group Buffer 0" in hide.long 0x04 "ADEVBUFFER1,Event Group Buffer 1" in hide.long 0x08 "ADEVBUFFER2,Event Group Buffer 2" in hide.long 0x0C "ADEVBUFFER3,Event Group Buffer 3" in hide.long 0x10 "ADEVBUFFER4,Event Group Buffer 4" in hide.long 0x14 "ADEVBUFFER5,Event Group Buffer 5" in hide.long 0x18 "ADEVBUFFER6,Event Group Buffer 6" in hide.long 0x1C "ADEVBUFFER7,Event Group Buffer 7" in hgroup.long 0xB0++0x1F hide.long 0x00 "ADG1BUFFER0,Group1 Buffer 0" in hide.long 0x04 "ADG1BUFFER1,Group1 Buffer 1" in hide.long 0x08 "ADG1BUFFER2,Group1 Buffer 2" in hide.long 0x0C "ADG1BUFFER3,Group1 Buffer 3" in hide.long 0x10 "ADG1BUFFER4,Group1 Buffer 4" in hide.long 0x14 "ADG1BUFFER5,Group1 Buffer 5" in hide.long 0x18 "ADG1BUFFER6,Group1 Buffer 6" in hide.long 0x1C "ADG1BUFFER7,Group1 Buffer 7" in hgroup.long 0xD0++0x1F hide.long 0x00 "ADG2BUFFER0,Group2 Buffer 0" in hide.long 0x04 "ADG2BUFFER1,Group2 Buffer 1" in hide.long 0x08 "ADG2BUFFER2,Group2 Buffer 2" in hide.long 0x0C "ADG2BUFFER3,Group2 Buffer 3" in hide.long 0x10 "ADG2BUFFER4,Group2 Buffer 4" in hide.long 0x14 "ADG2BUFFER5,Group2 Buffer 5" in hide.long 0x18 "ADG2BUFFER6,Group2 Buffer 6" in hide.long 0x1C "ADG2BUFFER7,Group2 Buffer 7" in hgroup.long 0xF0++0x03 hide.long 0x00 "ADEVEMUBUFFER,Event Group EMU Buffer" in hgroup.long 0xF4++0x03 hide.long 0x00 "ADG1BUFFER,Group 1 EMU Buffer" in hgroup.long 0xF8++0x03 hide.long 0x00 "ADG2BUFFER,Group 2 EMU Buffer" in tree.end width 11. tree "ADC ADEVT Pin Control Registers" group.long 0xFC++0x03 line.long 0x00 "ADEVTDIR,Event Group Pin Direction Selection" bitfld.long 0x00 0. " EVT_DIR ,ADEVT pin direction selection" "Output disabled,Output enabled" sif (cpu()=="RM48L950"||cpu()=="RM48L952-PGE"||cpu()=="RM48L952-ZWT"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L540-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE"||cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE"||cpu()=="RM42L432") if (((d.l((ad:0xFFF7C000+0xFC)))&0x1000000)==0x1000000) group.long 0x100++0x03 line.long 0x00 "ADEVTOUT,Event Group Pin Data Output" bitfld.long 0x00 0. " EVT_OUT ,ADEVT pin data output" "Low,High" else hgroup.long 0x100++0x03 hide.long 0x00 "ADEVTOUT,Event Group Pin Data Output" endif else if (((d.l((ad:0xFFF7C000+0xFC)))&0x01)==0x01) group.long 0x100++0x03 line.long 0x00 "ADEVTOUT,Event Group Pin Data Output" bitfld.long 0x00 0. " EVT_OUT ,ADEVT pin data output" "Low,High" else hgroup.long 0x100++0x03 hide.long 0x00 "ADEVTOUT,Event Group Pin Data Output" endif endif group.long 0x104++0x03 line.long 0x00 "ADEVTIN,Event Group Pin Input Value" bitfld.long 0x00 0. " EVT_IN ,ADEVT pin input value" "Low,High" group.long 0x108++0x03 line.long 0x00 "ADEVTSET,Event Group Pin Set" bitfld.long 0x00 0. " ADEVT_SET ,ADEVT pin set" "Low/no effect,High/set" group.long 0x10C++0x03 line.long 0x00 "ADEVTCLR,Event Group Pin Clear" bitfld.long 0x00 0. " ADEVT_CLR ,ADEVT pin clear" "Low/no effect,High/clear" sif (cpuis("RM48L950*")) if ((((d.l((ad:0xFFF7C000+0xfc)))&0x01000000)==0x01000000)&&(((d.l((ad:0xFFF7C000+0x0100)))&0x01000000)==0x01000000)) group.long 0x110++0x03 line.long 0x00 "ADEVTPDR,Event Group Pin open-drain Enable" bitfld.long 0x00 0. " ADEVT_PDR ,ADEVT pin Open-Drain enable" "High,Tri-state" else hgroup.long 0x110++0x03 hide.long 0x00 "ADEVTPDR,Event Group Pin open-drain Enable" endif else if ((((d.l((ad:0xFFF7C000+0xfc)))&0x01)==0x01)&&(((d.l((ad:0xFFF7C000+0x0100)))&0x01)==0x01)) group.long 0x110++0x03 line.long 0x00 "ADEVTPDR,Event Group Pin open-drain Enable" bitfld.long 0x00 0. " ADEVT_PDR ,ADEVT pin Open-Drain enable" "High,Tri-state" else hgroup.long 0x110++0x03 hide.long 0x00 "ADEVTPDR,Event Group Pin open-drain Enable" endif endif sif (cpuis("RM48L950*")) if (((d.l((ad:0xFFF7C000+0xFC)))&0x1000000)==0x00) group.long 0x114++0x03 line.long 0x00 "ADEVTPDIS,Event Group Pin Pull Control Enable" bitfld.long 0x00 0. " ADEVT_PDIS ,ADEVT pin pull control enable" "Enabled,Disabled" else hgroup.long 0x114++0x03 hide.long 0x00 "ADEVTPDIS,Event Group Pin Pull Control Enable" endif else if (((d.l((ad:0xFFF7C000+0xFC)))&0x01)==0x00) group.long 0x114++0x03 line.long 0x00 "ADEVTPDIS,Event Group Pin Pull Control Enable" bitfld.long 0x00 0. " ADEVT_PDIS ,ADEVT pin pull control enable" "Enabled,Disabled" else hgroup.long 0x114++0x03 hide.long 0x00 "ADEVTPDIS,Event Group Pin Pull Control Enable" endif endif group.long 0x118++0x03 line.long 0x00 "ADEVTPSEL,Event Group Pull Select" bitfld.long 0x00 0. " ADEVT_PSEL ,ADEVT pull select" "Pull-down,Pull-up" tree.end width 15. tree "ADC Sampling Capacitor Discharge Mode Control Registers" group.long 0x11C++0x03 line.long 0x00 "ADEVSAMPDISEN,Event Group Sampling Capacitor Discharge Mode" hexmask.long.byte 0x00 8.--15. 1. " EV_SAMP_DIS_CYC[7:0] ,ADC sampling capacitor is dicharged cycles" bitfld.long 0x00 0. " EV_SAMP_DIS_EN ,Sampling capacitor discharge mode" "Disabled,Enabled" group.long 0x120++0x03 line.long 0x00 "ADG1SAMPDISEN,Group 1 Sampling Capacitor Discharge Mode" hexmask.long.byte 0x00 8.--15. 1. " G1_SAMP_DIS_CYC[7:0] ,ADC sampling capacitor is dicharged cycles" bitfld.long 0x00 0. " G1_SAMP_DIS_EN ,Sampling capacitor discharge mode" "Disabled,Enabled" group.long 0x124++0x03 line.long 0x00 "ADG2SAMPDISEN,Group 2 Sampling Capacitor Discharge Mode" hexmask.long.byte 0x00 8.--15. 1. " G2_SAMP_DIS_CYC[7:0] ,ADC sampling capacitor is dicharged cycles" bitfld.long 0x00 0. " G2_SAMP_DIS_EN ,Sampling capacitor discharge mode" "Disabled,Enabled" tree.end width 19. tree "ADC Interrupt Control Registers" sif (cpu()=="RM57L843-ZWT") if (((d.l(ad:0xFFF7C000+0x04))&0x80000000)==0x80000000) group.long 0x128++0x03 line.long 0x00 "ADMAGINTCR1,Magnitude Interrupt Control Register 1" hexmask.long.word 0x00 16.--27. 1. " MAG_THR1[11-0] ,12-bit compare value with MAG_CHID1" bitfld.long 0x00 15. " CHN_THR_COMP1 ,Channel OR threshold comparison" "Threshold,Channel" bitfld.long 0x00 14. " CMP_GE_LT1 ,'greater than or equal to' OR 'less than' comparison operator" "Lower,Greater" textline " " bitfld.long 0x00 8.--12. " COMP_CHID1[4-0] ,Channel number compared with MAG_CHID1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " MAG_CHID1[4-0] ,Channel number monitored by ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x12C++0x03 line.long 0x00 "ADMAGINT1MASK,Magnitude Interrupt Mask 1" bitfld.long 0x00 11. " MAG_INT1_MASK[11] ,Comparison for the magnitude compare interrupt 1 mask 11" "Not masked,Masked" bitfld.long 0x00 10. " MAG_INT1_MASK[10] ,Comparison for the magnitude compare interrupt 1 mask 10" "Not masked,Masked" textline " " bitfld.long 0x00 9. " MAG_INT1_MASK[9] ,Comparison for the magnitude compare interrupt 1 mask 9" "Not masked,Masked" bitfld.long 0x00 8. " MAG_INT1_MASK[8] ,Comparison for the magnitude compare interrupt 1 mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MAG_INT1_MASK[7] ,Comparison for the magnitude compare interrupt 1 mask 7" "Not masked,Masked" bitfld.long 0x00 6. " MAG_INT1_MASK[6] ,Comparison for the magnitude compare interrupt 1 mask 6" "Not masked,Masked" textline " " bitfld.long 0x00 5. " MAG_INT1_MASK[5] ,Comparison for the magnitude compare interrupt 1 mask 5" "Not masked,Masked" bitfld.long 0x00 4. " MAG_INT1_MASK[4] ,Comparison for the magnitude compare interrupt 1 mask 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " MAG_INT1_MASK[3] ,Comparison for the magnitude compare interrupt 1 mask 3" "Not masked,Masked" bitfld.long 0x00 2. " MAG_INT1_MASK[2] ,Comparison for the magnitude compare interrupt 1 mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " MAG_INT1_MASK[1] ,Comparison for the magnitude compare interrupt 1 mask 1" "Not masked,Masked" bitfld.long 0x00 0. " MAG_INT1_MASK[0] ,Comparison for the magnitude compare interrupt 1 mask 0" "Not masked,Masked" group.long 0x130++0x03 line.long 0x00 "ADMAGINTCR2,Magnitude Interrupt Control Register 2" hexmask.long.word 0x00 16.--27. 1. " MAG_THR2[11-0] ,12-bit compare value with MAG_CHID2" bitfld.long 0x00 15. " CHN_THR_COMP2 ,Channel OR threshold comparison" "Threshold,Channel" bitfld.long 0x00 14. " CMP_GE_LT2 ,'greater than or equal to' OR 'less than' comparison operator" "Lower,Greater" textline " " bitfld.long 0x00 8.--12. " COMP_CHID2[4-0] ,Channel number compared with MAG_CHID2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " MAG_CHID2[4-0] ,Channel number monitored by ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x134++0x03 line.long 0x00 "ADMAGINT2MASK,Magnitude Interrupt Mask 2" bitfld.long 0x00 11. " MAG_INT2_MASK[11] ,Comparison for the magnitude compare interrupt 2 mask 11" "Not masked,Masked" bitfld.long 0x00 10. " MAG_INT2_MASK[10] ,Comparison for the magnitude compare interrupt 2 mask 10" "Not masked,Masked" textline " " bitfld.long 0x00 9. " MAG_INT2_MASK[9] ,Comparison for the magnitude compare interrupt 2 mask 9" "Not masked,Masked" bitfld.long 0x00 8. " MAG_INT2_MASK[8] ,Comparison for the magnitude compare interrupt 2 mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MAG_INT2_MASK[7] ,Comparison for the magnitude compare interrupt 2 mask 7" "Not masked,Masked" bitfld.long 0x00 6. " MAG_INT2_MASK[6] ,Comparison for the magnitude compare interrupt 2 mask 6" "Not masked,Masked" textline " " bitfld.long 0x00 5. " MAG_INT2_MASK[5] ,Comparison for the magnitude compare interrupt 2 mask 5" "Not masked,Masked" bitfld.long 0x00 4. " MAG_INT2_MASK[4] ,Comparison for the magnitude compare interrupt 2 mask 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " MAG_INT2_MASK[3] ,Comparison for the magnitude compare interrupt 2 mask 3" "Not masked,Masked" bitfld.long 0x00 2. " MAG_INT2_MASK[2] ,Comparison for the magnitude compare interrupt 2 mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " MAG_INT2_MASK[1] ,Comparison for the magnitude compare interrupt 2 mask 1" "Not masked,Masked" bitfld.long 0x00 0. " MAG_INT2_MASK[0] ,Comparison for the magnitude compare interrupt 2 mask 0" "Not masked,Masked" group.long 0x138++0x03 line.long 0x00 "ADMAGINTCR3,Magnitude Interrupt Control Register 3" hexmask.long.word 0x00 16.--27. 1. " MAG_THR3[11-0] ,12-bit compare value with MAG_CHID3" bitfld.long 0x00 15. " CHN_THR_COMP3 ,Channel OR threshold comparison" "Threshold,Channel" bitfld.long 0x00 14. " CMP_GE_LT3 ,'greater than or equal to' OR 'less than' comparison operator" "Lower,Greater" textline " " bitfld.long 0x00 8.--12. " COMP_CHID3[4-0] ,Channel number compared with MAG_CHID3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " MAG_CHID3[4-0] ,Channel number monitored by ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x13C++0x03 line.long 0x00 "ADMAGINT3MASK,Magnitude Interrupt Mask 3" bitfld.long 0x00 11. " MAG_INT3_MASK[11] ,Comparison for the magnitude compare interrupt 3 mask 11" "Not masked,Masked" bitfld.long 0x00 10. " MAG_INT3_MASK[10] ,Comparison for the magnitude compare interrupt 3 mask 10" "Not masked,Masked" textline " " bitfld.long 0x00 9. " MAG_INT3_MASK[9] ,Comparison for the magnitude compare interrupt 3 mask 9" "Not masked,Masked" bitfld.long 0x00 8. " MAG_INT3_MASK[8] ,Comparison for the magnitude compare interrupt 3 mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MAG_INT3_MASK[7] ,Comparison for the magnitude compare interrupt 3 mask 7" "Not masked,Masked" bitfld.long 0x00 6. " MAG_INT3_MASK[6] ,Comparison for the magnitude compare interrupt 3 mask 6" "Not masked,Masked" textline " " bitfld.long 0x00 5. " MAG_INT3_MASK[5] ,Comparison for the magnitude compare interrupt 3 mask 5" "Not masked,Masked" bitfld.long 0x00 4. " MAG_INT3_MASK[4] ,Comparison for the magnitude compare interrupt 3 mask 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " MAG_INT3_MASK[3] ,Comparison for the magnitude compare interrupt 3 mask 3" "Not masked,Masked" bitfld.long 0x00 2. " MAG_INT3_MASK[2] ,Comparison for the magnitude compare interrupt 3 mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " MAG_INT3_MASK[1] ,Comparison for the magnitude compare interrupt 3 mask 1" "Not masked,Masked" bitfld.long 0x00 0. " MAG_INT3_MASK[0] ,Comparison for the magnitude compare interrupt 3 mask 0" "Not masked,Masked" else group.long 0x128++0x03 line.long 0x00 "ADMAGINTCR1,Magnitude Interrupt Control Register 1" bitfld.long 0x00 26.--30. " MAG_CHID1[4-0] ,Channel number monitored by ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 16.--25. 1. " MAG_THR1[9-0] ,10-bit compare value with MAG_CHID1" textline " " bitfld.long 0x00 8.--12. " COMP_CHID1[4-0] ,Channel number compared with MAG_CHID1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1. " CHN/THR_COMP1 ,Channel OR threshold comparison" "Threshold,COMP_CHID1 channel" textline " " bitfld.long 0x00 0. " CMP_GE/LT1 ,Greater than or equal to OR less than comparison operator" "Lower,Greater" group.long 0x12C++0x03 line.long 0x00 "ADMAGINT1MASK,Magnitude Interrupt Mask 1" bitfld.long 0x00 9. " MAG_INT1_MASK[9] ,Comparison for the magnitude compare interrupt 1 mask 9" "Not masked,Masked" bitfld.long 0x00 8. " MAG_INT1_MASK[8] ,Comparison for the magnitude compare interrupt 1 mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MAG_INT1_MASK[7] ,Comparison for the magnitude compare interrupt 1 mask 7" "Not masked,Masked" bitfld.long 0x00 6. " MAG_INT1_MASK[6] ,Comparison for the magnitude compare interrupt 1 mask 6" "Not masked,Masked" textline " " bitfld.long 0x00 5. " MAG_INT1_MASK[5] ,Comparison for the magnitude compare interrupt 1 mask 5" "Not masked,Masked" bitfld.long 0x00 4. " MAG_INT1_MASK[4] ,Comparison for the magnitude compare interrupt 1 mask 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " MAG_INT1_MASK[3] ,Comparison for the magnitude compare interrupt 1 mask 3" "Not masked,Masked" bitfld.long 0x00 2. " MAG_INT1_MASK[2] ,Comparison for the magnitude compare interrupt 1 mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " MAG_INT1_MASK[1] ,Comparison for the magnitude compare interrupt 1 mask 1" "Not masked,Masked" bitfld.long 0x00 0. " MAG_INT1_MASK[0] ,Comparison for the magnitude compare interrupt 1 mask 0" "Not masked,Masked" group.long 0x130++0x03 line.long 0x00 "ADMAGINTCR2,Magnitude Interrupt Control Register 2" bitfld.long 0x00 26.--30. " MAG_CHID2[4-0] ,Channel number monitored by ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 16.--25. 1. " MAG_THR2[9-0] ,10-bit compare value with MAG_CHID2" textline " " bitfld.long 0x00 8.--12. " COMP_CHID2[4-0] ,Channel number compared with MAG_CHID2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1. " CHN/THR_COMP2 ,Channel OR threshold comparison" "Threshold,COMP_CHID1 channel" textline " " bitfld.long 0x00 0. " CMP_GE/LT2 ,Greater than or equal to OR less than comparison operator" "Lower,Greater" group.long 0x134++0x03 line.long 0x00 "ADMAGINT2MASK,Magnitude Interrupt Mask 2" bitfld.long 0x00 9. " MAG_INT2_MASK[9] ,Comparison for the magnitude compare interrupt 2 mask 9" "Not masked,Masked" bitfld.long 0x00 8. " MAG_INT2_MASK[8] ,Comparison for the magnitude compare interrupt 2 mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MAG_INT2_MASK[7] ,Comparison for the magnitude compare interrupt 2 mask 7" "Not masked,Masked" bitfld.long 0x00 6. " MAG_INT2_MASK[6] ,Comparison for the magnitude compare interrupt 2 mask 6" "Not masked,Masked" textline " " bitfld.long 0x00 5. " MAG_INT2_MASK[5] ,Comparison for the magnitude compare interrupt 2 mask 5" "Not masked,Masked" bitfld.long 0x00 4. " MAG_INT2_MASK[4] ,Comparison for the magnitude compare interrupt 2 mask 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " MAG_INT2_MASK[3] ,Comparison for the magnitude compare interrupt 2 mask 3" "Not masked,Masked" bitfld.long 0x00 2. " MAG_INT2_MASK[2] ,Comparison for the magnitude compare interrupt 2 mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " MAG_INT2_MASK[1] ,Comparison for the magnitude compare interrupt 2 mask 1" "Not masked,Masked" bitfld.long 0x00 0. " MAG_INT2_MASK[0] ,Comparison for the magnitude compare interrupt 2 mask 0" "Not masked,Masked" group.long 0x138++0x03 line.long 0x00 "ADMAGINTCR3,Magnitude Interrupt Control Register 3" bitfld.long 0x00 26.--30. " MAG_CHID3[4-0] ,Channel number monitored by ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 16.--25. 1. " MAG_THR3[9-0] ,10-bit compare value with MAG_CHID3" textline " " bitfld.long 0x00 8.--12. " COMP_CHID3[4-0] ,Channel number compared with MAG_CHID3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1. " CHN/THR_COMP3 ,Channel OR threshold comparison" "Threshold,COMP_CHID3 channel" textline " " bitfld.long 0x00 0. " CMP_GE/LT3 ,Greater than or equal to OR less than comparison operator" "Lower,Greater" group.long 0x13C++0x03 line.long 0x00 "ADMAGINT3MASK,Magnitude Interrupt Mask 3" bitfld.long 0x00 9. " MAG_INT3_MASK[9] ,Comparison for the magnitude compare interrupt 3 mask 9" "Not masked,Masked" bitfld.long 0x00 8. " MAG_INT3_MASK[8] ,Comparison for the magnitude compare interrupt 3 mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MAG_INT3_MASK[7] ,Comparison for the magnitude compare interrupt 3 mask 7" "Not masked,Masked" bitfld.long 0x00 6. " MAG_INT3_MASK[6] ,Comparison for the magnitude compare interrupt 3 mask 6" "Not masked,Masked" textline " " bitfld.long 0x00 5. " MAG_INT3_MASK[5] ,Comparison for the magnitude compare interrupt 3 mask 5" "Not masked,Masked" bitfld.long 0x00 4. " MAG_INT3_MASK[4] ,Comparison for the magnitude compare interrupt 3 mask 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " MAG_INT3_MASK[3] ,Comparison for the magnitude compare interrupt 3 mask 3" "Not masked,Masked" bitfld.long 0x00 2. " MAG_INT3_MASK[2] ,Comparison for the magnitude compare interrupt 3 mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " MAG_INT3_MASK[1] ,Comparison for the magnitude compare interrupt 3 mask 1" "Not masked,Masked" bitfld.long 0x00 0. " MAG_INT3_MASK[0] ,Comparison for the magnitude compare interrupt 3 mask 0" "Not masked,Masked" endif else group.long 0x128++0x03 line.long 0x00 "ADMAGINTCR1,Magnitude Interrupt Control Register 1" bitfld.long 0x00 26.--30. " MAG_CHID1[4-0] ,Channel number monitored by ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 16.--25. 1. " MAG_THR1[9-0] ,10-bit compare value with MAG_CHID1" textline " " bitfld.long 0x00 8.--12. " COMP_CHID1[4-0] ,Channel number compared with MAG_CHID1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1. " CHN/THR_COMP1 ,Channel OR threshold comparison" "Threshold,COMP_CHID1 channel" textline " " bitfld.long 0x00 0. " CMP_GE/LT1 ,Greater than or equal to OR less than comparison operator" "Lower,Greater" group.long 0x12C++0x03 line.long 0x00 "ADMAGINT1MASK,Magnitude Interrupt Mask 1" bitfld.long 0x00 9. " MAG_INT1_MASK[9] ,Comparison for the magnitude compare interrupt 1 mask 9" "Not masked,Masked" bitfld.long 0x00 8. " MAG_INT1_MASK[8] ,Comparison for the magnitude compare interrupt 1 mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MAG_INT1_MASK[7] ,Comparison for the magnitude compare interrupt 1 mask 7" "Not masked,Masked" bitfld.long 0x00 6. " MAG_INT1_MASK[6] ,Comparison for the magnitude compare interrupt 1 mask 6" "Not masked,Masked" textline " " bitfld.long 0x00 5. " MAG_INT1_MASK[5] ,Comparison for the magnitude compare interrupt 1 mask 5" "Not masked,Masked" bitfld.long 0x00 4. " MAG_INT1_MASK[4] ,Comparison for the magnitude compare interrupt 1 mask 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " MAG_INT1_MASK[3] ,Comparison for the magnitude compare interrupt 1 mask 3" "Not masked,Masked" bitfld.long 0x00 2. " MAG_INT1_MASK[2] ,Comparison for the magnitude compare interrupt 1 mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " MAG_INT1_MASK[1] ,Comparison for the magnitude compare interrupt 1 mask 1" "Not masked,Masked" bitfld.long 0x00 0. " MAG_INT1_MASK[0] ,Comparison for the magnitude compare interrupt 1 mask 0" "Not masked,Masked" group.long 0x130++0x03 line.long 0x00 "ADMAGINTCR2,Magnitude Interrupt Control Register 2" bitfld.long 0x00 26.--30. " MAG_CHID2[4-0] ,Channel number monitored by ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 16.--25. 1. " MAG_THR2[9-0] ,10-bit compare value with MAG_CHID2" textline " " bitfld.long 0x00 8.--12. " COMP_CHID2[4-0] ,Channel number compared with MAG_CHID2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1. " CHN/THR_COMP2 ,Channel OR threshold comparison" "Threshold,COMP_CHID1 channel" textline " " bitfld.long 0x00 0. " CMP_GE/LT2 ,Greater than or equal to OR less than comparison operator" "Lower,Greater" group.long 0x134++0x03 line.long 0x00 "ADMAGINT2MASK,Magnitude Interrupt Mask 2" bitfld.long 0x00 9. " MAG_INT2_MASK[9] ,Comparison for the magnitude compare interrupt 2 mask 9" "Not masked,Masked" bitfld.long 0x00 8. " MAG_INT2_MASK[8] ,Comparison for the magnitude compare interrupt 2 mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MAG_INT2_MASK[7] ,Comparison for the magnitude compare interrupt 2 mask 7" "Not masked,Masked" bitfld.long 0x00 6. " MAG_INT2_MASK[6] ,Comparison for the magnitude compare interrupt 2 mask 6" "Not masked,Masked" textline " " bitfld.long 0x00 5. " MAG_INT2_MASK[5] ,Comparison for the magnitude compare interrupt 2 mask 5" "Not masked,Masked" bitfld.long 0x00 4. " MAG_INT2_MASK[4] ,Comparison for the magnitude compare interrupt 2 mask 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " MAG_INT2_MASK[3] ,Comparison for the magnitude compare interrupt 2 mask 3" "Not masked,Masked" bitfld.long 0x00 2. " MAG_INT2_MASK[2] ,Comparison for the magnitude compare interrupt 2 mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " MAG_INT2_MASK[1] ,Comparison for the magnitude compare interrupt 2 mask 1" "Not masked,Masked" bitfld.long 0x00 0. " MAG_INT2_MASK[0] ,Comparison for the magnitude compare interrupt 2 mask 0" "Not masked,Masked" group.long 0x138++0x03 line.long 0x00 "ADMAGINTCR3,Magnitude Interrupt Control Register 3" bitfld.long 0x00 26.--30. " MAG_CHID3[4-0] ,Channel number monitored by ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 16.--25. 1. " MAG_THR3[9-0] ,10-bit compare value with MAG_CHID3" textline " " bitfld.long 0x00 8.--12. " COMP_CHID3[4-0] ,Channel number compared with MAG_CHID3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1. " CHN/THR_COMP3 ,Channel OR threshold comparison" "Threshold,COMP_CHID3 channel" textline " " bitfld.long 0x00 0. " CMP_GE/LT3 ,Greater than or equal to OR less than comparison operator" "Lower,Greater" group.long 0x13C++0x03 line.long 0x00 "ADMAGINT3MASK,Magnitude Interrupt Mask 3" bitfld.long 0x00 9. " MAG_INT3_MASK[9] ,Comparison for the magnitude compare interrupt 3 mask 9" "Not masked,Masked" bitfld.long 0x00 8. " MAG_INT3_MASK[8] ,Comparison for the magnitude compare interrupt 3 mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MAG_INT3_MASK[7] ,Comparison for the magnitude compare interrupt 3 mask 7" "Not masked,Masked" bitfld.long 0x00 6. " MAG_INT3_MASK[6] ,Comparison for the magnitude compare interrupt 3 mask 6" "Not masked,Masked" textline " " bitfld.long 0x00 5. " MAG_INT3_MASK[5] ,Comparison for the magnitude compare interrupt 3 mask 5" "Not masked,Masked" bitfld.long 0x00 4. " MAG_INT3_MASK[4] ,Comparison for the magnitude compare interrupt 3 mask 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " MAG_INT3_MASK[3] ,Comparison for the magnitude compare interrupt 3 mask 3" "Not masked,Masked" bitfld.long 0x00 2. " MAG_INT3_MASK[2] ,Comparison for the magnitude compare interrupt 3 mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " MAG_INT3_MASK[1] ,Comparison for the magnitude compare interrupt 3 mask 1" "Not masked,Masked" bitfld.long 0x00 0. " MAG_INT3_MASK[0] ,Comparison for the magnitude compare interrupt 3 mask 0" "Not masked,Masked" endif sif (cpu()!="RM57L843-ZWT") group.long 0x140++0x1F line.long 0x00 "MAGINTCTRL4,Magnitude Interrupt Control" line.long 0x04 "MAGINT4MSK,Magnitude Interrupt Mask" line.long 0x08 "MAGINTCTRL5,Magnitude Interrupt Control" line.long 0x0C "MAGINT5MSK,Magnitude Interrupt Mask" line.long 0x10 "MAGINTCTRL6,Magnitude Interrupt Control" line.long 0x14 "MAGINT6MSK,Magnitude Interrupt Mask" line.long 0x18 "MAGTHRINTENASET,Magnitude Interrupt Enable Set" line.long 0x1C "MAGTHRINTENACLR,Magnitude Interrupt Enable Clear" endif group.long 0x160++0x03 line.long 0x00 "ADMAGINTFLG,Magnitude Compare Interrupt Flag" setclrfld.long 0x00 2. -0x08 2. -0x04 2. " MAG_INT3_SET/CLR ,Magnitude compare interrupt flag bit[3]" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 1. -0x08 1. -0x04 1. " MAG_INT2_SET/CLR ,Magnitude compare interrupt flag bit[2]" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 0. -0x08 0. -0x04 0. " MAG_INT1_SET/CLR ,Magnitude compare interrupt flag bit[1]" "No interrupt,Interrupt" hgroup.long 0x164++0x03 hide.long 0x00 "ADMAGINTOFF,Magnitude Compare Interrupt Offset" in tree.end width 17. tree "ADC RAM Control Registers" group.long 0x168++0x03 line.long 0x00 "ADEVFIFORESETCR,Event Group FIFO Reset" bitfld.long 0x00 0. " EV_FIFO_RESET ,Reset the ADC event group FIFO" "No reset,Reset" group.long 0x16C++0x03 line.long 0x00 "ADG1FIFORESETCR,Group 1 FIFO Reset" bitfld.long 0x00 0. " G1_FIFO_RESET ,Reset the ADC group 1 FIFO" "No reset,Reset" group.long 0x170++0x03 line.long 0x00 "ADG2FIFORESETCR,Group 2 FIFO Reset" bitfld.long 0x00 0. " G2_FIFO_RESET ,Reset the ADC group 2 FIFO" "No reset,Reset" rgroup.long 0x174++0x03 line.long 0x00 "ADEVRAMADDR,Event Group ADC RAM Pointer" hexmask.long.word 0x00 0.--8. 1. " EV_RAM_ADDR ,Event group ADC RAM pointer" rgroup.long 0x178++0x03 line.long 0x00 "ADG1RAMADDR,Group 1 ADC RAM Pointer" hexmask.long.word 0x00 0.--8. 1. " G1_RAM_ADDR ,Group 1 ADC RAM pointer" rgroup.long 0x17C++0x03 line.long 0x00 "ADG2RAMADDR,Group 2 ADC RAM Pointer" hexmask.long.word 0x00 0.--8. 1. " G2_RAM_ADDR ,Group 2 ADC RAM pointer" tree.end width 11. tree "ADC Parity Control Registers" group.long 0x180++0x03 line.long 0x00 "ADPARCR,Parity Control Register" bitfld.long 0x00 8. " TEST ,Parity bits map" "Not mapped,Mapped" bitfld.long 0x00 0.--3. " PARITY_ENA[3:0] ,Enable/disable parity checking" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" rgroup.long 0x184++0x03 line.long 0x00 "ADPARADDR,Parity Address" hexmask.long.word 0x00 2.--11. 0x04 " ERROR_ADDRESS ,ERROR ADDRESS" tree.end width 16. textline " " group.long 0x188++0x03 line.long 0x00 "ADPWRUPDLYCTRL,Power-Up Delay Control Register" hexmask.long.word 0x00 0.--9. 1. " PWRUP_DLY[9-0] ,Number of VCLK cycles to wait" sif (cpu()=="RM42L432"||cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE"||cpu()=="RM57L843-ZWT") width 20. tree "ADC Selection/count Registers" group.long 0x190++0x0B line.long 0x00 "ADEVCHNSELMODECTRL,ADC Event Group Channel Selection Mode Control Register" bitfld.long 0x00 0.--3. " EV_ENH_CHNSEL_MODE_EN ,Enable enhanced channel selection mode for event group" "No effect,No effect,No effect,No effect,No effect,Disabled,No effect,No effect,No effect,No effect,Enabled,No effect,No effect,No effect,No effect,No effect" line.long 0x04 "ADG1CHNSELMODECTRL,ADC Group1 Channel Selection Mode Control Register" bitfld.long 0x04 0.--3. " G1_ENH_CHNSEL_MODE_EN ,Enable enhanced channel selection mode for event group" "No effect,No effect,No effect,No effect,No effect,Disabled,No effect,No effect,No effect,No effect,Enabled,No effect,No effect,No effect,No effect,No effect" line.long 0x08 "ADG2CHNSELMODECTRL,ADC Group2 Channel Selection Mode Control Register" bitfld.long 0x08 0.--3. " G2_ENH_CHNSEL_MODE_EN ,Enable enhanced channel selection mode for event group" "No effect,No effect,No effect,No effect,No effect,Disabled,No effect,No effect,No effect,No effect,Enabled,No effect,No effect,No effect,No effect,No effect" group.long 0x19C++0x17 line.long 0x00 "ADEVCURRCOUNT,ADC Event Group Current Count Register" bitfld.long 0x00 0.--4. " EV_CURRENT_COUNT ,CURRENT_COUNT value for the event group conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "ADEVMAXCOUNT,ADC Event Group Maximum Count Register" bitfld.long 0x04 0.--4. " EV_MAX_COUNT ,MAX_COUNT value for the event group conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "ADG1CURRCOUNT,ADC Group1 Current Count Register" bitfld.long 0x08 0.--4. " G1_CURRENT_COUNT ,CURRENT_COUNT value for the group1 conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "ADG1MAXCOUNT,ADC Group1 Maximum Count Register" bitfld.long 0x0C 0.--4. " G1_MAX_COUNT ,MAX_COUNT value for the group1 conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "ADG2CURRCOUNT,ADC Group2 Current Count Register" bitfld.long 0x10 0.--4. " G2_CURRENT_COUNT ,CURRENT_COUNT value for the group2 conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x14 "ADG2MAXCOUNT,ADC Group2 Maximum Count Register" bitfld.long 0x14 0.--4. " G2_MAX_COUNT ,MAX_COUNT value for the group2 conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end endif width 0x0B tree.end tree "MIBADC2" base ad:0xFFF7C200 width 12. group.long 0x00++0x03 line.long 0x00 "ADRSTCR,ADC Reset Control Register" bitfld.long 0x00 0. " RESET ,ADC reset" "No reset,Reset" group.long 0x04++0x03 line.long 0x00 "ADOPMODECR,ADC Operating Mode Control Register" bitfld.long 0x00 31. " 10/12BIT ,Resolution of the ADC core select" "10-bit,12-bit" bitfld.long 0x00 24. " COS ,ADCLK halt/continue when the emulation system enters suspend mode" "Halted,Continue" textline " " bitfld.long 0x00 17.--20. " CHNTESTEN ,Enable the input channels impedance measurement mode" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" bitfld.long 0x00 16. " RAMTESTEN ,Enable the ADC results RAM test mode" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " POWERDOWN ,ADC core power down" "Not powered down,Powered down" bitfld.long 0x00 4. " IDLEPWRDN ,ADC power down when idle" "Not powered down,Powered down" textline " " bitfld.long 0x00 0. " ADCEN ,ADC conversions enable" "Disabled,Enabled" group.long 0x08++0x03 line.long 0x00 "CLOCKCR,Clock Prescaler" bitfld.long 0x00 0.--4. " PS[4:0] ,ADC clock prescaler" "1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,14 cycles,15 cycles,16 cycles,17 cycles,18 cycles,19 cycles,20 cycles,21 cycles,22 cycles,23 cycles,24 cycles,25 cycles,26 cycles,27 cycles,28 cycles,29 cycles,30 cycles,31 cycles,32 cycles" sif (cpuis("RM48L950*")||cpu()=="RM57L843-ZWT") if (((d.l(ad:0xFFF7C200+0x0C))&0x1020001)==0x1000000) group.long 0x0C++0x03 line.long 0x00 "ADCALCR,Calibration Conversion Register" bitfld.long 0x00 24. " SELF_TEST ,Self-Test enable" "Disabled,Enabled" bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started" textline " " bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full" bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " HILO ,Test and reference source selection" "(AD_REFHI*R1+AD_REFLO*R2)/(R1+R2),(AD_REFLO*R1+AD_REFHI*R2)/(R1+R2)" elif (((d.l(ad:0xFFF7C200+0x0C))&0x1020001)==0x01) group.long 0x0C++0x03 line.long 0x00 "ADCALCR,Calibration Conversion Register" bitfld.long 0x00 24. " SELF_TEST ,Self-Test enable" "Disabled,Enabled" bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started" textline " " bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full" bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " HILO ,Test and reference source selection" "(Ad_reflo via R1)||(R2 to vin),(Ad_refhi via R1)||(R2 to vin)" elif (((d.l(ad:0xFFF7C200+0x0C))&0x1020001)==0x1020000) group.long 0x0C++0x03 line.long 0x00 "ADCALCR,Calibration Conversion Register" bitfld.long 0x00 24. " SELF_TEST ,Self-Test enable" "Disabled,Enabled" bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started" textline " " bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full" bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " HILO ,Test and reference source selection" "AD_REFLO,AD_REFHI" elif (((d.l(ad:0xFFF7C200+0x0C))&0x1020001)==0x20001) group.long 0x0C++0x03 line.long 0x00 "ADCALCR,Calibration Conversion Register" bitfld.long 0x00 24. " SELF_TEST ,Self-Test enable" "Disabled,Enabled" bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started" textline " " bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full" bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " HILO ,Test and reference source selection" "(Ad_reflo via R1)||(R2 to vin),(Ad_refhi via R1)||(R2 to vin)" else group.long 0x0C++0x03 line.long 0x00 "ADCALCR,Calibration Conversion Register" bitfld.long 0x00 24. " SELF_TEST ,Self-Test enable" "Disabled,Enabled" bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started" textline " " bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full" bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled" endif else if (((d.l(ad:0xFFF7C200+0x0C))&0x1000201)==0x01) group.long 0x0C++0x03 line.long 0x00 "ADCALCR,Calibration Conversion Register" bitfld.long 0x00 24. " SELF_TEST ,Self-Test enable" "Disabled,Enabled" bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started" textline " " bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full" textline " " bitfld.long 0x00 8. " HILO ,Test and reference source selection" "(AD_REFHI*R1+AD_REFLO*R2)/(R1+R2),(AD_REFLO*R1+AD_REFHI*R2)/(R1+R2)" textline " " bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled" elif (((d.l(ad:0xFFF7C200+0x0C))&0x1000201)==0x1000000) group.long 0x0C++0x03 line.long 0x00 "ADCALCR,Calibration Conversion Register" bitfld.long 0x00 24. " SELF_TEST ,Self-Test enable" "Disabled,Enabled" bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started" textline " " bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full" textline " " bitfld.long 0x00 8. " HILO ,Test and reference source selection" "(Ad_reflo via R1)||(R2 to vin),(Ad_refhi via R1)||(R2 to vin)" textline " " bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled" elif (((d.l(ad:0xFFF7C200+0x0C))&0x1000201)==0x201) group.long 0x0C++0x03 line.long 0x00 "ADCALCR,Calibration Conversion Register" bitfld.long 0x00 24. " SELF_TEST ,Self-Test enable" "Disabled,Enabled" bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started" textline " " bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full" textline " " bitfld.long 0x00 8. " HILO ,Test and reference source selection" "AD_REFLO,AD_REFHI" textline " " bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled" elif (((d.l(ad:0xFFF7C200+0x0C))&0x1000201)==0x1000200) group.long 0x0C++0x03 line.long 0x00 "ADCALCR,Calibration Conversion Register" bitfld.long 0x00 24. " SELF_TEST ,Self-Test enable" "Disabled,Enabled" bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started" textline " " bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full" textline " " bitfld.long 0x00 8. " HILO ,Test and reference source selection" "(Ad_reflo via R1)||(R2 to vin),(Ad_refhi via R1)||(R2 to vin)" textline " " bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled" else group.long 0x0C++0x03 line.long 0x00 "ADCALCR,Calibration Conversion Register" bitfld.long 0x00 24. " SELF_TEST ,Self-Test enable" "Disabled,Enabled" bitfld.long 0x00 16. " CAL_ST ,Calibration conversion start" "No effect/completed,Started" textline " " bitfld.long 0x00 9. " BRIDGE_EN ,Bridge enable" "Midpoint,Full" textline " " textline " " bitfld.long 0x00 0. " CAL_EN ,Calibration enable" "Disabled,Enabled" endif endif group.long 0x10++0x03 line.long 0x00 "ADEVMODECR,EV MODE Control Register" bitfld.long 0x00 16. " NORESETONCHNSEL ,No event group results memory reset on new channel select" "Reset,No reset" bitfld.long 0x00 8.--9. " EV_DATA_FMT ,Event group (Read) data format" "12 bit,10 bit,8 bit,?..." textline " " bitfld.long 0x00 5. " EV_CHID ,Channel ID mode for the event group" "Forced to 0,ID of A/D channel" bitfld.long 0x00 4. " OVR_EV_RAM_IGN ,Overrun event group RAM ignore" "Not ignored,Ignored" textline " " bitfld.long 0x00 2. " EV8BIT ,Event group 8-bit result mode" "10-bit,8-bit" bitfld.long 0x00 1. " EV_MODE ,Event mode" "Single,Continuous" textline " " bitfld.long 0x00 0. " FRZ_EV ,Freeze conversion event group" "Completed,Frozen" group.long 0x14++0x03 line.long 0x00 "ADG1MODECR,G1 MODE Control Register" bitfld.long 0x00 16. " NORESETONCHNSEL ,No group1 results memory reset on new channel select" "Reset,No reset" bitfld.long 0x00 8.--9. " G1_DATA_FMT ,Group1 (Read) data format" "12 bit,10 bit,8 bit,?..." textline " " bitfld.long 0x00 5. " G1_CHID ,Channel ID mode for the group 1" "Forced to 0,ID of A/D channel" bitfld.long 0x00 4. " OVR_G1_RAM_IGN ,Overrun group 1 RAM ignore" "Not ignored,Ignored" textline " " bitfld.long 0x00 3. " G1_HW_TRIG ,Group 1 hardware triggered" "Software,Hardware" bitfld.long 0x00 2. " G1_8BIT ,Group1 8-bit result mode" "10-bit,8-bit" textline " " bitfld.long 0x00 1. " G1_MODE ,Group 1 mode" "Single,Continuous" bitfld.long 0x00 0. " FRZ_G1 ,Freeze conversion group 1" "Completed,Frozen" group.long 0x18++0x03 line.long 0x00 "ADG2MODECR,G2 MODE Control Register" bitfld.long 0x00 16. " NORESETONCHNSEL ,No group2 results memory reset on new channel select" "Reset,No reset" bitfld.long 0x00 8.--9. " G2_DATA_FMT ,Group2 (Read) data format" "12 bit,10 bit,8 bit,?..." textline " " bitfld.long 0x00 5. " G2_CHID ,Channel ID mode for the group 2" "Forced to 0,ID of A/D channel" bitfld.long 0x00 4. " OVR_G2_RAM_IGN ,Overrun group 2 RAM ignore" "Not ignored,Ignored" textline " " bitfld.long 0x00 3. " G2_HW_TRIG ,Group 2 hardware triggered" "Software,Hardware" bitfld.long 0x00 2. " G2_8BIT ,Group2 8-bit result mode" "10-bit,8-bit" textline " " bitfld.long 0x00 1. " G2_MODE ,Group 2 mode" "Single,Continuous" bitfld.long 0x00 0. " FRZ_G2 ,Freeze conversion group 2" "Completed,Frozen" group.long 0x1C++0x03 line.long 0x00 "ADEVSRC,Event Group Trigger Source Select" bitfld.long 0x00 4. " EV_EDG_BOTH ,Event group trigger on both edges" "EV_EDGE_SEL bit,Rising or falling" textline " " bitfld.long 0x00 3. " EV_EDG_SEL ,Event group trigger edge polarity select" "High/low,Low/high" sif (cpu()=="RM42L432") bitfld.long 0x00 0.--2. " EVSRC[2:0] ,Event group trigger source select" "ADEVT,N2HET1[8],N2HET1[10],RTI compare 0,N2HET1[12],N2HET1[14],N2HET1[17],N2HET1[19]" else bitfld.long 0x00 0.--2. " EVSRC[2:0] ,Event group trigger source select" "AD2EVT,N2HET1[8]/[5],N2HET1[10]/[27],RTI compare 0,N2HET1[12]/[17],N2HET1[14]/[19],GIOB[0]/N2HET1[11],GIOB[1]/N2HET2[13]" endif group.long 0x20++0x03 line.long 0x00 "ADG1SRC,Group 1 Trigger Source Select" bitfld.long 0x00 4. " G1_EDG_BOTH ,Group1 trigger on both edges" "G1_EDG_SEL bit,Rising or falling" textline " " bitfld.long 0x00 3. " G1_EDG_SEL ,ADC group 1 trigger edge select" "High/low,Low/high" sif (cpu()=="RM42L432") bitfld.long 0x00 0.--2. " G1SRC[2:0] ,Group 1 trigger source select" "ADEVT,N2HET1[8],N2HET1[10],RTI compare 0,N2HET1[12],N2HET1[14],N2HET1[17],N2HET2[19]" else bitfld.long 0x00 0.--2. " G1SRC[2:0] ,Group 1 trigger source select" "AD2EVT,N2HET1[8]/[5],N2HET1[10]/[27],RTI compare 0,N2HET1[12]/[17],N2HET1[14]/[19],GIOB[0]/N2HET1[11],GIOB[1]/N2HET2[13]" endif group.long 0x24++0x03 line.long 0x00 "ADG2SRC,Group 2 Trigger Source Select" bitfld.long 0x00 4. " G2_EDG_BOTH ,Group2 trigger on both edges" "G2_EDG_SEL bit,Rising or falling" textline " " bitfld.long 0x00 3. " G2_EDG_SEL ,ADC group 2 trigger edge select" "High/low,Low/high" sif (cpu()=="RM42L432") bitfld.long 0x00 0.--2. " G2SRC[2:0] ,Group 2 trigger source select" "ADEVT,N2HET1[8],N2HET1[10],RTI compare 0,N2HET1[12],N2HET1[14],N2HET1[17],N2HET2[19]" else bitfld.long 0x00 0.--2. " G2SRC[2:0] ,Group 2 trigger source select" "AD2EVT,N2HET1[8]/[5],N2HET1[10]/[27],RTI compare 0,N2HET1[12]/[17],N2HET1[14]/[19],GIOB[0]/N2HET1[11],GIOB[1]/N2HET2[13]" endif group.long 0x28++0x03 line.long 0x00 "ADEVINTENA,Event Group Interrupt Enable" bitfld.long 0x00 3. " EV_END_INT_EN ,Event group conversion end interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " EV_OVR_INT_EN ,Event group memory overrun interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " EV_THR_INT_EN ,Event group memory threshold interrupt enable" "Disabled,Enabled" group.long 0x2C++0x03 line.long 0x00 "ADG1INTENA,Group 1 Interrupt Enable" bitfld.long 0x00 3. " G1_END_INT_EN ,Event group conversion end interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " G1_OVR_INT_EN ,Group 1 memory overrun interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " G1_THR_INT_EN ,Group 1 memory threshold interrupt enable" "Disabled,Enabled" group.long 0x30++0x03 line.long 0x00 "ADG2INTENA,Group 2 Interrupt Enable" bitfld.long 0x00 3. " G2_END_INT_EN ,Event group conversion end interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " G2_OVR_INT_EN ,Group 2 memory overrun interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " G2_THR_INT_EN ,Group 2 memory threshold interrupt enable" "Disabled,Enabled" hgroup.long 0x34++0x0B hide.long 0x00 "ADEVINTFLG,Event Group Interrupt Flag" in hide.long 0x04 "ADG1INTFLG,Group 1 Interrupt Flag" in hide.long 0x08 "ADG2INTFLG,Group 2 Interrupt Flag" in group.long 0x40++0x03 line.long 0x00 "ADEVINTCR,Event Group Interrupt Threshold Counter" hexmask.long.byte 0x00 9.--15. 1. " SIGN_EXTENSION ,Sign extension" hexmask.long.word 0x00 0.--8. 1. " EVTHR[8:0] ,Event group interrupt threshold counter" group.long 0x44++0x03 line.long 0x00 "ADG1INTCR,Group 1 Interrupt Threshold Counter" hexmask.long.byte 0x00 9.--15. 1. " SIGN_EXTENSION ,Sign extension" hexmask.long.word 0x00 0.--8. 1. " G1THR[8:0] ,Group 1 interrupt threshold counter" group.long 0x48++0x03 line.long 0x00 "ADG2INTCR,Group 2 Interrupt Threshold Counter" hexmask.long.byte 0x00 9.--15. 1. " SIGN_EXTENSION ,Sign extension" hexmask.long.word 0x00 0.--8. 1. " G2THR[8:0] ,Group 2 interrupt threshold counter" group.long 0x4C++0x03 line.long 0x00 "ADEVDMACR,Event Group DMA Control Register" hexmask.long.word 0x00 16.--24. 1. " EVBLOCKS[8:0] ,Number of event group memory buffers to be transferred" bitfld.long 0x00 3. " DMA_EV_END ,Event group conversion end DMA transfer enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " EV_BLK_XFER ,Event group block DMA transfer enable" "Disabled,Enabled" bitfld.long 0x00 0. " EV_DMA_EN ,Event group DMA transfer enable" "Disabled,Enabled" group.long 0x50++0x03 line.long 0x00 "ADG1DMACR,Group 1 DMA Control Register" hexmask.long.word 0x00 16.--24. 1. " G1BLOCKS[8:0] ,Number of group 1 memory buffers to be transferred" bitfld.long 0x00 3. " DMA_G1_END ,Group1 conversion end DMA transfer enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " G1_BLK_XFER ,Group 1 block DMA transfer enable" "Disabled,Enabled" bitfld.long 0x00 0. " G1_DMA_EN ,Group 1 DMA transfer enable" "Disabled,Enabled" group.long 0x54++0x03 line.long 0x00 "ADG2DMACR,Group 2 DMA Control Register" hexmask.long.word 0x00 16.--24. 1. " G2BLOCKS[8:0] ,Number of group 2 memory buffers to be transferred" bitfld.long 0x00 3. " DMA_G2_END ,Group2 conversion end DMA transfer enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " G2_BLK_XFER ,Group 2 block DMA transfer enable" "Disabled,Enabled" bitfld.long 0x00 0. " G2_DMA_EN ,Group 2 DMA transfer enable" "Disabled,Enabled" group.long 0x58++0x03 line.long 0x00 "ADBNDCR,Buffer Boundary Control Register" hexmask.long.word 0x00 16.--24. 1. " BNDA[8:0] ,Buffer boundary A" hexmask.long.word 0x00 0.--8. 1. " BNDB[8:0] ,Buffer boundary B" group.long 0x5C++0x03 line.long 0x00 "ADBNDEND,Buffer End Boundary" bitfld.long 0x00 16. " BUF_INIT_ACTIVE ,Indicates the status of the ADC RAM intialization process" "Not initialized,Initialized" bitfld.long 0x00 0.--2. " BNDEND[2:0] ,Buffer end boundary" "16 words,32 words,64 words,128 words,192 words,256 words,512 words,1024 words" width 10. tree "ADC Sample Control Registers" group.long 0x60++0x03 line.long 0x00 "ADEVSAMP,Event Group Sampling Time Configuration" hexmask.long.word 0x00 0.--11. 1. " EVACQ[11:0] ,Event group acquisition time" group.long 0x64++0x03 line.long 0x00 "ADG1SAMP,Group1 Sampling Time Configuration" hexmask.long.word 0x00 0.--11. 1. " G1ACQ[11:0] ,Group 1 acquisition time" group.long 0x68++0x03 line.long 0x00 "ADG2SAMP,Group2 Sampling Time Configuration" hexmask.long.word 0x00 0.--11. 1. " G2ACQ[11:0] ,Group 2 acquisition time" tree.end width 8. tree "ADC Status Registers" group.long 0x6C++0x03 line.long 0x00 "ADEVSR,Event Group Status Register" bitfld.long 0x00 3. " EV_MEM_EMPTY ,Event group memory empty" "Not empty,Empty" bitfld.long 0x00 2. " EV_BUSY ,Event group Conversion-Busy flag" "Not active,Busy" bitfld.long 0x00 1. " EV_STOP ,Event group conversion stopped flag" "Not frozen,Frozen" textline " " eventfld.long 0x00 0. " EV_END ,Event Conversion-Ended flag R/W" "Not completed,Completed" group.long 0x70++0x03 line.long 0x00 "ADG1SR,Group 1 Status Register" bitfld.long 0x00 3. " G1_MEM_EMPTY ,Group 1 memory empty" "Not empty,Empty" bitfld.long 0x00 2. " G1_BUSY ,Group 1 Conversion-Busy flag" "Not active,Busy" bitfld.long 0x00 1. " G1_STOP ,Group 1 conversion stopped flag" "Not frozen,Frozen" textline " " eventfld.long 0x00 0. " G1_END ,Group 1 Conversion-Ended flag" "Not completed,Completed" group.long 0x74++0x03 line.long 0x00 "ADG2SR,Group 2 Status Register" bitfld.long 0x00 3. " G2_MEM_EMPTY ,Group 2 memory empty" "Not empty,Empty" bitfld.long 0x00 2. " G2_BUSY ,Group 2 Conversion-Busy flag" "Not active,Busy" bitfld.long 0x00 1. " G2_STOP ,Group 2 conversion stopped flag" "Not frozen,Frozen" textline " " eventfld.long 0x00 0. " G2_END ,Group 2 conversion-ended flag" "Not completed,Completed" tree.end width 9. tree "ADC Selection Control Registers" sif cpu()=="RM57L843-ZWT" group.long 0x78++0x03 line.long 0x00 "ADEVSEL,Event Group Select Register" bitfld.long 0x00 24. " EVCHNSEL[24] ,A/D event channel 24 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 23. " EVCHNSEL[23] ,A/D event channel 23 selection bit" "Not converted,Converted" bitfld.long 0x00 22. " EVCHNSEL[22] ,A/D event channel 22 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 21. " EVCHNSEL[21] ,A/D event channel 21 selection bit" "Not converted,Converted" bitfld.long 0x00 20. " EVCHNSEL[20] ,A/D event channel 20 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 19. " EVCHNSEL[19] ,A/D event channel 19 selection bit" "Not converted,Converted" bitfld.long 0x00 18. " EVCHNSEL[18] ,A/D event channel 18 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 17. " EVCHNSEL[17] ,A/D event channel 17 selection bit" "Not converted,Converted" bitfld.long 0x00 16. " EVCHNSEL[16] ,A/D event channel 16 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 15. " EVCHNSEL[15] ,A/D event channel 15 selection bit" "Not converted,Converted" bitfld.long 0x00 14. " EVCHNSEL[14] ,A/D event channel 14 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 13. " EVCHNSEL[13] ,A/D event channel 13 selection bit" "Not converted,Converted" bitfld.long 0x00 12. " EVCHNSEL[12] ,A/D event channel 12 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 11. " EVCHNSEL[11] ,A/D event channel 11 selection bit" "Not converted,Converted" bitfld.long 0x00 10. " EVCHNSEL[10] ,A/D event channel 10 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 9. " EVCHNSEL[9] ,A/D event channel 9 selection bit" "Not converted,Converted" bitfld.long 0x00 8. " EVCHNSEL[8] ,A/D event channel 8 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 7. " EVCHNSEL[7] ,A/D event channel 7 selection bit" "Not converted,Converted" bitfld.long 0x00 6. " EVCHNSEL[6] ,A/D event channel 6 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 5. " EVCHNSEL[5] ,A/D event channel 5 selection bit" "Not converted,Converted" bitfld.long 0x00 4. " EVCHNSEL[4] ,A/D event channel 4 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 3. " EVCHNSEL[3] ,A/D event channel 3 selection bit" "Not converted,Converted" bitfld.long 0x00 2. " EVCHNSEL[2] ,A/D event channel 2 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 1. " EVCHNSEL[1] ,A/D event channel 1 selection bit" "Not converted,Converted" bitfld.long 0x00 0. " EVCHNSEL[0] ,A/D event channel 0 selection bit" "Not converted,Converted" group.long 0x7C++0x03 line.long 0x00 "ADG1SEL,Group 1 Select Register" bitfld.long 0x00 24. " G1CHNSEL[24] ,A/D channel 24 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 23. " G1CHNSEL[23] ,A/D channel 23 enable bit" "Not converted,Converted" bitfld.long 0x00 22. " G1CHNSEL[22] ,A/D channel 22 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 21. " G1CHNSEL[21] ,A/D channel 21 enable bit" "Not converted,Converted" bitfld.long 0x00 20. " G1CHNSEL[20] ,A/D channel 20 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 19. " G1CHNSEL[19] ,A/D channel 19 enable bit" "Not converted,Converted" bitfld.long 0x00 18. " G1CHNSEL[18] ,A/D channel 18 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 17. " G1CHNSEL[17] ,A/D channel 17 enable bit" "Not converted,Converted" bitfld.long 0x00 16. " G1CHNSEL[16] ,A/D channel 16 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 15. " G1CHNSEL[15] ,A/D channel 15 enable bit" "Not converted,Converted" bitfld.long 0x00 14. " G1CHNSEL[14] ,A/D channel 14 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 13. " G1CHNSEL[13] ,A/D channel 13 enable bit" "Not converted,Converted" bitfld.long 0x00 12. " G1CHNSEL[12] ,A/D channel 12 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 11. " G1CHNSEL[11] ,A/D channel 11 enable bit" "Not converted,Converted" bitfld.long 0x00 10. " G1CHNSEL[10] ,A/D channel 10 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 9. " G1CHNSEL[9] ,A/D channel 9 enable bit" "Not converted,Converted" bitfld.long 0x00 8. " G1CHNSEL[8] ,A/D channel 8 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 7. " G1CHNSEL[7] ,A/D channel 7 enable bit" "Not converted,Converted" bitfld.long 0x00 6. " G1CHNSEL[6] ,A/D channel 6 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 5. " G1CHNSEL[5] ,A/D channel 5 enable bit" "Not converted,Converted" bitfld.long 0x00 4. " G1CHNSEL[4] ,A/D channel 4 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 3. " G1CHNSEL[3] ,A/D channel 3 enable bit" "Not converted,Converted" bitfld.long 0x00 2. " G1CHNSEL[2] ,A/D channel 2 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 1. " G1CHNSEL[1] ,A/D channel 1 enable bit" "Not converted,Converted" bitfld.long 0x00 0. " G1CHNSEL[0] ,A/D channel 0 enable bit" "Not converted,Converted" group.long 0x80++0x03 line.long 0x00 "ADG2SEL,Group 2 Select Register" bitfld.long 0x00 24. " G2CHNSEL[24] ,A/D channel 24 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 23. " G2CHNSEL[23] ,A/D channel 23 enable bit" "Not converted,Converted" bitfld.long 0x00 22. " G2CHNSEL[22] ,A/D channel 22 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 21. " G2CHNSEL[21] ,A/D channel 21 enable bit" "Not converted,Converted" bitfld.long 0x00 20. " G2CHNSEL[20] ,A/D channel 20 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 19. " G2CHNSEL[19] ,A/D channel 19 enable bit" "Not converted,Converted" bitfld.long 0x00 18. " G2CHNSEL[18] ,A/D channel 18 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 17. " G2CHNSEL[17] ,A/D channel 17 enable bit" "Not converted,Converted" bitfld.long 0x00 16. " G2CHNSEL[16] ,A/D channel 16 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 15. " G2CHNSEL[15] ,A/D channel 15 enable bit" "Not converted,Converted" bitfld.long 0x00 14. " G2CHNSEL[14] ,A/D channel 14 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 13. " G2CHNSEL[13] ,A/D channel 13 enable bit" "Not converted,Converted" bitfld.long 0x00 12. " G2CHNSEL[12] ,A/D channel 12 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 11. " G2CHNSEL[11] ,A/D channel 11 enable bit" "Not converted,Converted" bitfld.long 0x00 10. " G2CHNSEL[10] ,A/D channel 10 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 9. " G2CHNSEL[9] ,A/D channel 9 enable bit" "Not converted,Converted" bitfld.long 0x00 8. " G2CHNSEL[8] ,A/D channel 8 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 7. " G2CHNSEL[7] ,A/D channel 7 enable bit" "Not converted,Converted" bitfld.long 0x00 6. " G2CHNSEL[6] ,A/D channel 6 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 5. " G2CHNSEL[5] ,A/D channel 5 enable bit" "Not converted,Converted" bitfld.long 0x00 4. " G2CHNSEL[4] ,A/D channel 4 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 3. " G2CHNSEL[3] ,A/D channel 3 enable bit" "Not converted,Converted" bitfld.long 0x00 2. " G2CHNSEL[2] ,A/D channel 2 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 1. " G2CHNSEL[1] ,A/D channel 1 enable bit" "Not converted,Converted" bitfld.long 0x00 0. " G2CHNSEL[0] ,A/D channel 0 enable bit" "Not converted,Converted" else group.long 0x78++0x03 line.long 0x00 "ADEVSEL,Event Group Select Register" bitfld.long 0x00 15. " EVCHNSEL[15] ,A/D event channel 15 selection bit" "Not converted,Converted" bitfld.long 0x00 14. " EVCHNSEL[14] ,A/D event channel 14 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 13. " EVCHNSEL[13] ,A/D event channel 13 selection bit" "Not converted,Converted" bitfld.long 0x00 12. " EVCHNSEL[12] ,A/D event channel 12 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 11. " EVCHNSEL[11] ,A/D event channel 11 selection bit" "Not converted,Converted" bitfld.long 0x00 10. " EVCHNSEL[10] ,A/D event channel 10 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 9. " EVCHNSEL[9] ,A/D event channel 9 selection bit" "Not converted,Converted" bitfld.long 0x00 8. " EVCHNSEL[8] ,A/D event channel 8 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 7. " EVCHNSEL[7] ,A/D event channel 7 selection bit" "Not converted,Converted" bitfld.long 0x00 6. " EVCHNSEL[6] ,A/D event channel 6 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 5. " EVCHNSEL[5] ,A/D event channel 5 selection bit" "Not converted,Converted" bitfld.long 0x00 4. " EVCHNSEL[4] ,A/D event channel 4 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 3. " EVCHNSEL[3] ,A/D event channel 3 selection bit" "Not converted,Converted" bitfld.long 0x00 2. " EVCHNSEL[2] ,A/D event channel 2 selection bit" "Not converted,Converted" textline " " bitfld.long 0x00 1. " EVCHNSEL[1] ,A/D event channel 1 selection bit" "Not converted,Converted" bitfld.long 0x00 0. " EVCHNSEL[0] ,A/D event channel 0 selection bit" "Not converted,Converted" group.long 0x7C++0x03 line.long 0x00 "ADG1SEL,Group 1 Select Register" bitfld.long 0x00 15. " G1CHNSEL[15] ,A/D channel 15 enable bit" "Not converted,Converted" bitfld.long 0x00 14. " G1CHNSEL[14] ,A/D channel 14 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 13. " G1CHNSEL[13] ,A/D channel 13 enable bit" "Not converted,Converted" bitfld.long 0x00 12. " G1CHNSEL[12] ,A/D channel 12 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 11. " G1CHNSEL[11] ,A/D channel 11 enable bit" "Not converted,Converted" bitfld.long 0x00 10. " G1CHNSEL[10] ,A/D channel 10 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 9. " G1CHNSEL[9] ,A/D channel 9 enable bit" "Not converted,Converted" bitfld.long 0x00 8. " G1CHNSEL[8] ,A/D channel 8 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 7. " G1CHNSEL[7] ,A/D channel 7 enable bit" "Not converted,Converted" bitfld.long 0x00 6. " G1CHNSEL[6] ,A/D channel 6 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 5. " G1CHNSEL[5] ,A/D channel 5 enable bit" "Not converted,Converted" bitfld.long 0x00 4. " G1CHNSEL[4] ,A/D channel 4 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 3. " G1CHNSEL[3] ,A/D channel 3 enable bit" "Not converted,Converted" bitfld.long 0x00 2. " G1CHNSEL[2] ,A/D channel 2 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 1. " G1CHNSEL[1] ,A/D channel 1 enable bit" "Not converted,Converted" bitfld.long 0x00 0. " G1CHNSEL[0] ,A/D channel 0 enable bit" "Not converted,Converted" group.long 0x80++0x03 line.long 0x00 "ADG2SEL,Group 2 Select Register" bitfld.long 0x00 15. " G2CHNSEL[15] ,A/D channel 15 enable bit" "Not converted,Converted" bitfld.long 0x00 14. " G2CHNSEL[14] ,A/D channel 14 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 13. " G2CHNSEL[13] ,A/D channel 13 enable bit" "Not converted,Converted" bitfld.long 0x00 12. " G2CHNSEL[12] ,A/D channel 12 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 11. " G2CHNSEL[11] ,A/D channel 11 enable bit" "Not converted,Converted" bitfld.long 0x00 10. " G2CHNSEL[10] ,A/D channel 10 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 9. " G2CHNSEL[9] ,A/D channel 9 enable bit" "Not converted,Converted" bitfld.long 0x00 8. " G2CHNSEL[8] ,A/D channel 8 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 7. " G2CHNSEL[7] ,A/D channel 7 enable bit" "Not converted,Converted" bitfld.long 0x00 6. " G2CHNSEL[6] ,A/D channel 6 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 5. " G2CHNSEL[5] ,A/D channel 5 enable bit" "Not converted,Converted" bitfld.long 0x00 4. " G2CHNSEL[4] ,A/D channel 4 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 3. " G2CHNSEL[3] ,A/D channel 3 enable bit" "Not converted,Converted" bitfld.long 0x00 2. " G2CHNSEL[2] ,A/D channel 2 enable bit" "Not converted,Converted" textline " " bitfld.long 0x00 1. " G2CHNSEL[1] ,A/D channel 1 enable bit" "Not converted,Converted" bitfld.long 0x00 0. " G2CHNSEL[0] ,A/D channel 0 enable bit" "Not converted,Converted" endif tree.end width 12. textline " " sif (cpuis("RM48L950*")||cpu()=="RM57L843-ZWT") if (((d.l(ad:0xFFF7C200+0x04))&0x80)==0x80) group.long 0x84++0x03 line.long 0x00 "ADCALR,Calibration Register" hexmask.long.word 0x00 0.--11. 1. " ADCALR[11:0] ,Calibration bits" else group.long 0x84++0x03 line.long 0x00 "ADCALR,Calibration Register" hexmask.long.word 0x00 0.--9. 1. " ADCALR[9:0] ,Calibration bits" endif else if (((d.l(ad:0xFFF7C200+0x04))&0x80000000)==0x80000000) group.long 0x84++0x03 line.long 0x00 "ADCALR,Calibration Register" hexmask.long.word 0x00 0.--11. 1. " ADCALR[11:0] ,Calibration bits" else group.long 0x84++0x03 line.long 0x00 "ADCALR,Calibration Register" hexmask.long.word 0x00 0.--9. 1. " ADCALR[9:0] ,Calibration bits" endif endif rgroup.long 0x88++0x03 line.long 0x00 "ADSMSTATE,State Machine Current State" bitfld.long 0x00 0.--3. " SMSTATE[3:0] ,ADC state machine current state" "Idle,Conv_ev,Conv_sw1,Conv_sw2,Conv_cal,Start_ev,Start_sw1,Start_sw2,Start_cal,Wait_ev,Wait_sw1,Wait_sw2,Wait_cal,?..." width 12. sif (cpu()=="RM57L843-ZWT") rgroup.long 0x8C++0x03 line.long 0x00 "ADLASTCONV,Last Conversion" textline " " bitfld.long 0x00 24. " LAST_CONV[24] ,Digital input channel 24" "Low,High" textline " " bitfld.long 0x00 23. " LAST_CONV[23] ,Digital input channel 23" "Low,High" bitfld.long 0x00 22. " LAST_CONV[22] ,Digital input channel 22" "Low,High" bitfld.long 0x00 21. " LAST_CONV[21] ,Digital input channel 21" "Low,High" bitfld.long 0x00 20. " LAST_CONV[20] ,Digital input channel 20" "Low,High" textline " " bitfld.long 0x00 19. " LAST_CONV[19] ,Digital input channel 19" "Low,High" bitfld.long 0x00 18. " LAST_CONV[18] ,Digital input channel 18" "Low,High" bitfld.long 0x00 17. " LAST_CONV[17] ,Digital input channel 17" "Low,High" bitfld.long 0x00 16. " LAST_CONV[16] ,Digital input channel 16" "Low,High" textline " " bitfld.long 0x00 15. " LAST_CONV[15] ,Digital input channel 15" "Low,High" bitfld.long 0x00 14. " LAST_CONV[14] ,Digital input channel 14" "Low,High" bitfld.long 0x00 13. " LAST_CONV[13] ,Digital input channel 13" "Low,High" bitfld.long 0x00 12. " LAST_CONV[12] ,Digital input channel 12" "Low,High" textline " " bitfld.long 0x00 11. " LAST_CONV[11] ,Digital input channel 11" "Low,High" bitfld.long 0x00 10. " LAST_CONV[10] ,Digital input channel 10" "Low,High" bitfld.long 0x00 9. " LAST_CONV[9] ,Digital input channel 9" "Low,High" bitfld.long 0x00 8. " LAST_CONV[8] ,Digital input channel 8" "Low,High" textline " " bitfld.long 0x00 7. " LAST_CONV[7] ,Digital input channel 7" "Low,High" bitfld.long 0x00 6. " LAST_CONV[6] ,Digital input channel 6" "Low,High" bitfld.long 0x00 5. " LAST_CONV[5] ,Digital input channel 5" "Low,High" bitfld.long 0x00 4. " LAST_CONV[4] ,Digital input channel 4" "Low,High" textline " " bitfld.long 0x00 3. " LAST_CONV[3] ,Digital input channel 3" "Low,High" bitfld.long 0x00 2. " LAST_CONV[2] ,Digital input channel 2" "Low,High" bitfld.long 0x00 1. " LAST_CONV[1] ,Digital input channel 1" "Low,High" bitfld.long 0x00 0. " LAST_CONV[0] ,Digital input channel 0" "Low,High" else rgroup.long 0x8C++0x03 line.long 0x00 "ADLASTCONV,Last Conversion" bitfld.long 0x00 15. " LAST_CONV[15] ,Digital input channel 15" "Low,High" bitfld.long 0x00 14. " LAST_CONV[14] ,Digital input channel 14" "Low,High" bitfld.long 0x00 13. " LAST_CONV[13] ,Digital input channel 13" "Low,High" bitfld.long 0x00 12. " LAST_CONV[12] ,Digital input channel 12" "Low,High" textline " " bitfld.long 0x00 11. " LAST_CONV[11] ,Digital input channel 11" "Low,High" bitfld.long 0x00 10. " LAST_CONV[10] ,Digital input channel 10" "Low,High" bitfld.long 0x00 9. " LAST_CONV[9] ,Digital input channel 9" "Low,High" bitfld.long 0x00 8. " LAST_CONV[8] ,Digital input channel 8" "Low,High" textline " " bitfld.long 0x00 7. " LAST_CONV[7] ,Digital input channel 7" "Low,High" bitfld.long 0x00 6. " LAST_CONV[6] ,Digital input channel 6" "Low,High" bitfld.long 0x00 5. " LAST_CONV[5] ,Digital input channel 5" "Low,High" bitfld.long 0x00 4. " LAST_CONV[4] ,Digital input channel 4" "Low,High" textline " " bitfld.long 0x00 3. " LAST_CONV[3] ,Digital input channel 3" "Low,High" bitfld.long 0x00 2. " LAST_CONV[2] ,Digital input channel 2" "Low,High" bitfld.long 0x00 1. " LAST_CONV[1] ,Digital input channel 1" "Low,High" bitfld.long 0x00 0. " LAST_CONV[0] ,Digital input channel 0" "Low,High" endif width 15. tree "ADC Buffer Control Registers" hgroup.long 0x90++0x1F hide.long 0x00 "ADEVBUFFER0,Event Group Buffer 0" in hide.long 0x04 "ADEVBUFFER1,Event Group Buffer 1" in hide.long 0x08 "ADEVBUFFER2,Event Group Buffer 2" in hide.long 0x0C "ADEVBUFFER3,Event Group Buffer 3" in hide.long 0x10 "ADEVBUFFER4,Event Group Buffer 4" in hide.long 0x14 "ADEVBUFFER5,Event Group Buffer 5" in hide.long 0x18 "ADEVBUFFER6,Event Group Buffer 6" in hide.long 0x1C "ADEVBUFFER7,Event Group Buffer 7" in hgroup.long 0xB0++0x1F hide.long 0x00 "ADG1BUFFER0,Group1 Buffer 0" in hide.long 0x04 "ADG1BUFFER1,Group1 Buffer 1" in hide.long 0x08 "ADG1BUFFER2,Group1 Buffer 2" in hide.long 0x0C "ADG1BUFFER3,Group1 Buffer 3" in hide.long 0x10 "ADG1BUFFER4,Group1 Buffer 4" in hide.long 0x14 "ADG1BUFFER5,Group1 Buffer 5" in hide.long 0x18 "ADG1BUFFER6,Group1 Buffer 6" in hide.long 0x1C "ADG1BUFFER7,Group1 Buffer 7" in hgroup.long 0xD0++0x1F hide.long 0x00 "ADG2BUFFER0,Group2 Buffer 0" in hide.long 0x04 "ADG2BUFFER1,Group2 Buffer 1" in hide.long 0x08 "ADG2BUFFER2,Group2 Buffer 2" in hide.long 0x0C "ADG2BUFFER3,Group2 Buffer 3" in hide.long 0x10 "ADG2BUFFER4,Group2 Buffer 4" in hide.long 0x14 "ADG2BUFFER5,Group2 Buffer 5" in hide.long 0x18 "ADG2BUFFER6,Group2 Buffer 6" in hide.long 0x1C "ADG2BUFFER7,Group2 Buffer 7" in hgroup.long 0xF0++0x03 hide.long 0x00 "ADEVEMUBUFFER,Event Group EMU Buffer" in hgroup.long 0xF4++0x03 hide.long 0x00 "ADG1BUFFER,Group 1 EMU Buffer" in hgroup.long 0xF8++0x03 hide.long 0x00 "ADG2BUFFER,Group 2 EMU Buffer" in tree.end width 11. tree "ADC ADEVT Pin Control Registers" group.long 0xFC++0x03 line.long 0x00 "ADEVTDIR,Event Group Pin Direction Selection" bitfld.long 0x00 0. " EVT_DIR ,ADEVT pin direction selection" "Output disabled,Output enabled" sif (cpu()=="RM48L950"||cpu()=="RM48L952-PGE"||cpu()=="RM48L952-ZWT"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L540-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE"||cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE"||cpu()=="RM42L432") if (((d.l((ad:0xFFF7C200+0xFC)))&0x1000000)==0x1000000) group.long 0x100++0x03 line.long 0x00 "ADEVTOUT,Event Group Pin Data Output" bitfld.long 0x00 0. " EVT_OUT ,ADEVT pin data output" "Low,High" else hgroup.long 0x100++0x03 hide.long 0x00 "ADEVTOUT,Event Group Pin Data Output" endif else if (((d.l((ad:0xFFF7C200+0xFC)))&0x01)==0x01) group.long 0x100++0x03 line.long 0x00 "ADEVTOUT,Event Group Pin Data Output" bitfld.long 0x00 0. " EVT_OUT ,ADEVT pin data output" "Low,High" else hgroup.long 0x100++0x03 hide.long 0x00 "ADEVTOUT,Event Group Pin Data Output" endif endif group.long 0x104++0x03 line.long 0x00 "ADEVTIN,Event Group Pin Input Value" bitfld.long 0x00 0. " EVT_IN ,ADEVT pin input value" "Low,High" group.long 0x108++0x03 line.long 0x00 "ADEVTSET,Event Group Pin Set" bitfld.long 0x00 0. " ADEVT_SET ,ADEVT pin set" "Low/no effect,High/set" group.long 0x10C++0x03 line.long 0x00 "ADEVTCLR,Event Group Pin Clear" bitfld.long 0x00 0. " ADEVT_CLR ,ADEVT pin clear" "Low/no effect,High/clear" sif (cpuis("RM48L950*")) if ((((d.l((ad:0xFFF7C200+0xfc)))&0x01000000)==0x01000000)&&(((d.l((ad:0xFFF7C200+0x0100)))&0x01000000)==0x01000000)) group.long 0x110++0x03 line.long 0x00 "ADEVTPDR,Event Group Pin open-drain Enable" bitfld.long 0x00 0. " ADEVT_PDR ,ADEVT pin Open-Drain enable" "High,Tri-state" else hgroup.long 0x110++0x03 hide.long 0x00 "ADEVTPDR,Event Group Pin open-drain Enable" endif else if ((((d.l((ad:0xFFF7C200+0xfc)))&0x01)==0x01)&&(((d.l((ad:0xFFF7C200+0x0100)))&0x01)==0x01)) group.long 0x110++0x03 line.long 0x00 "ADEVTPDR,Event Group Pin open-drain Enable" bitfld.long 0x00 0. " ADEVT_PDR ,ADEVT pin Open-Drain enable" "High,Tri-state" else hgroup.long 0x110++0x03 hide.long 0x00 "ADEVTPDR,Event Group Pin open-drain Enable" endif endif sif (cpuis("RM48L950*")) if (((d.l((ad:0xFFF7C200+0xFC)))&0x1000000)==0x00) group.long 0x114++0x03 line.long 0x00 "ADEVTPDIS,Event Group Pin Pull Control Enable" bitfld.long 0x00 0. " ADEVT_PDIS ,ADEVT pin pull control enable" "Enabled,Disabled" else hgroup.long 0x114++0x03 hide.long 0x00 "ADEVTPDIS,Event Group Pin Pull Control Enable" endif else if (((d.l((ad:0xFFF7C200+0xFC)))&0x01)==0x00) group.long 0x114++0x03 line.long 0x00 "ADEVTPDIS,Event Group Pin Pull Control Enable" bitfld.long 0x00 0. " ADEVT_PDIS ,ADEVT pin pull control enable" "Enabled,Disabled" else hgroup.long 0x114++0x03 hide.long 0x00 "ADEVTPDIS,Event Group Pin Pull Control Enable" endif endif group.long 0x118++0x03 line.long 0x00 "ADEVTPSEL,Event Group Pull Select" bitfld.long 0x00 0. " ADEVT_PSEL ,ADEVT pull select" "Pull-down,Pull-up" tree.end width 15. tree "ADC Sampling Capacitor Discharge Mode Control Registers" group.long 0x11C++0x03 line.long 0x00 "ADEVSAMPDISEN,Event Group Sampling Capacitor Discharge Mode" hexmask.long.byte 0x00 8.--15. 1. " EV_SAMP_DIS_CYC[7:0] ,ADC sampling capacitor is dicharged cycles" bitfld.long 0x00 0. " EV_SAMP_DIS_EN ,Sampling capacitor discharge mode" "Disabled,Enabled" group.long 0x120++0x03 line.long 0x00 "ADG1SAMPDISEN,Group 1 Sampling Capacitor Discharge Mode" hexmask.long.byte 0x00 8.--15. 1. " G1_SAMP_DIS_CYC[7:0] ,ADC sampling capacitor is dicharged cycles" bitfld.long 0x00 0. " G1_SAMP_DIS_EN ,Sampling capacitor discharge mode" "Disabled,Enabled" group.long 0x124++0x03 line.long 0x00 "ADG2SAMPDISEN,Group 2 Sampling Capacitor Discharge Mode" hexmask.long.byte 0x00 8.--15. 1. " G2_SAMP_DIS_CYC[7:0] ,ADC sampling capacitor is dicharged cycles" bitfld.long 0x00 0. " G2_SAMP_DIS_EN ,Sampling capacitor discharge mode" "Disabled,Enabled" tree.end width 19. tree "ADC Interrupt Control Registers" sif (cpu()=="RM57L843-ZWT") if (((d.l(ad:0xFFF7C200+0x04))&0x80000000)==0x80000000) group.long 0x128++0x03 line.long 0x00 "ADMAGINTCR1,Magnitude Interrupt Control Register 1" hexmask.long.word 0x00 16.--27. 1. " MAG_THR1[11-0] ,12-bit compare value with MAG_CHID1" bitfld.long 0x00 15. " CHN_THR_COMP1 ,Channel OR threshold comparison" "Threshold,Channel" bitfld.long 0x00 14. " CMP_GE_LT1 ,'greater than or equal to' OR 'less than' comparison operator" "Lower,Greater" textline " " bitfld.long 0x00 8.--12. " COMP_CHID1[4-0] ,Channel number compared with MAG_CHID1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " MAG_CHID1[4-0] ,Channel number monitored by ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x12C++0x03 line.long 0x00 "ADMAGINT1MASK,Magnitude Interrupt Mask 1" bitfld.long 0x00 11. " MAG_INT1_MASK[11] ,Comparison for the magnitude compare interrupt 1 mask 11" "Not masked,Masked" bitfld.long 0x00 10. " MAG_INT1_MASK[10] ,Comparison for the magnitude compare interrupt 1 mask 10" "Not masked,Masked" textline " " bitfld.long 0x00 9. " MAG_INT1_MASK[9] ,Comparison for the magnitude compare interrupt 1 mask 9" "Not masked,Masked" bitfld.long 0x00 8. " MAG_INT1_MASK[8] ,Comparison for the magnitude compare interrupt 1 mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MAG_INT1_MASK[7] ,Comparison for the magnitude compare interrupt 1 mask 7" "Not masked,Masked" bitfld.long 0x00 6. " MAG_INT1_MASK[6] ,Comparison for the magnitude compare interrupt 1 mask 6" "Not masked,Masked" textline " " bitfld.long 0x00 5. " MAG_INT1_MASK[5] ,Comparison for the magnitude compare interrupt 1 mask 5" "Not masked,Masked" bitfld.long 0x00 4. " MAG_INT1_MASK[4] ,Comparison for the magnitude compare interrupt 1 mask 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " MAG_INT1_MASK[3] ,Comparison for the magnitude compare interrupt 1 mask 3" "Not masked,Masked" bitfld.long 0x00 2. " MAG_INT1_MASK[2] ,Comparison for the magnitude compare interrupt 1 mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " MAG_INT1_MASK[1] ,Comparison for the magnitude compare interrupt 1 mask 1" "Not masked,Masked" bitfld.long 0x00 0. " MAG_INT1_MASK[0] ,Comparison for the magnitude compare interrupt 1 mask 0" "Not masked,Masked" group.long 0x130++0x03 line.long 0x00 "ADMAGINTCR2,Magnitude Interrupt Control Register 2" hexmask.long.word 0x00 16.--27. 1. " MAG_THR2[11-0] ,12-bit compare value with MAG_CHID2" bitfld.long 0x00 15. " CHN_THR_COMP2 ,Channel OR threshold comparison" "Threshold,Channel" bitfld.long 0x00 14. " CMP_GE_LT2 ,'greater than or equal to' OR 'less than' comparison operator" "Lower,Greater" textline " " bitfld.long 0x00 8.--12. " COMP_CHID2[4-0] ,Channel number compared with MAG_CHID2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " MAG_CHID2[4-0] ,Channel number monitored by ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x134++0x03 line.long 0x00 "ADMAGINT2MASK,Magnitude Interrupt Mask 2" bitfld.long 0x00 11. " MAG_INT2_MASK[11] ,Comparison for the magnitude compare interrupt 2 mask 11" "Not masked,Masked" bitfld.long 0x00 10. " MAG_INT2_MASK[10] ,Comparison for the magnitude compare interrupt 2 mask 10" "Not masked,Masked" textline " " bitfld.long 0x00 9. " MAG_INT2_MASK[9] ,Comparison for the magnitude compare interrupt 2 mask 9" "Not masked,Masked" bitfld.long 0x00 8. " MAG_INT2_MASK[8] ,Comparison for the magnitude compare interrupt 2 mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MAG_INT2_MASK[7] ,Comparison for the magnitude compare interrupt 2 mask 7" "Not masked,Masked" bitfld.long 0x00 6. " MAG_INT2_MASK[6] ,Comparison for the magnitude compare interrupt 2 mask 6" "Not masked,Masked" textline " " bitfld.long 0x00 5. " MAG_INT2_MASK[5] ,Comparison for the magnitude compare interrupt 2 mask 5" "Not masked,Masked" bitfld.long 0x00 4. " MAG_INT2_MASK[4] ,Comparison for the magnitude compare interrupt 2 mask 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " MAG_INT2_MASK[3] ,Comparison for the magnitude compare interrupt 2 mask 3" "Not masked,Masked" bitfld.long 0x00 2. " MAG_INT2_MASK[2] ,Comparison for the magnitude compare interrupt 2 mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " MAG_INT2_MASK[1] ,Comparison for the magnitude compare interrupt 2 mask 1" "Not masked,Masked" bitfld.long 0x00 0. " MAG_INT2_MASK[0] ,Comparison for the magnitude compare interrupt 2 mask 0" "Not masked,Masked" group.long 0x138++0x03 line.long 0x00 "ADMAGINTCR3,Magnitude Interrupt Control Register 3" hexmask.long.word 0x00 16.--27. 1. " MAG_THR3[11-0] ,12-bit compare value with MAG_CHID3" bitfld.long 0x00 15. " CHN_THR_COMP3 ,Channel OR threshold comparison" "Threshold,Channel" bitfld.long 0x00 14. " CMP_GE_LT3 ,'greater than or equal to' OR 'less than' comparison operator" "Lower,Greater" textline " " bitfld.long 0x00 8.--12. " COMP_CHID3[4-0] ,Channel number compared with MAG_CHID3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " MAG_CHID3[4-0] ,Channel number monitored by ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x13C++0x03 line.long 0x00 "ADMAGINT3MASK,Magnitude Interrupt Mask 3" bitfld.long 0x00 11. " MAG_INT3_MASK[11] ,Comparison for the magnitude compare interrupt 3 mask 11" "Not masked,Masked" bitfld.long 0x00 10. " MAG_INT3_MASK[10] ,Comparison for the magnitude compare interrupt 3 mask 10" "Not masked,Masked" textline " " bitfld.long 0x00 9. " MAG_INT3_MASK[9] ,Comparison for the magnitude compare interrupt 3 mask 9" "Not masked,Masked" bitfld.long 0x00 8. " MAG_INT3_MASK[8] ,Comparison for the magnitude compare interrupt 3 mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MAG_INT3_MASK[7] ,Comparison for the magnitude compare interrupt 3 mask 7" "Not masked,Masked" bitfld.long 0x00 6. " MAG_INT3_MASK[6] ,Comparison for the magnitude compare interrupt 3 mask 6" "Not masked,Masked" textline " " bitfld.long 0x00 5. " MAG_INT3_MASK[5] ,Comparison for the magnitude compare interrupt 3 mask 5" "Not masked,Masked" bitfld.long 0x00 4. " MAG_INT3_MASK[4] ,Comparison for the magnitude compare interrupt 3 mask 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " MAG_INT3_MASK[3] ,Comparison for the magnitude compare interrupt 3 mask 3" "Not masked,Masked" bitfld.long 0x00 2. " MAG_INT3_MASK[2] ,Comparison for the magnitude compare interrupt 3 mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " MAG_INT3_MASK[1] ,Comparison for the magnitude compare interrupt 3 mask 1" "Not masked,Masked" bitfld.long 0x00 0. " MAG_INT3_MASK[0] ,Comparison for the magnitude compare interrupt 3 mask 0" "Not masked,Masked" else group.long 0x128++0x03 line.long 0x00 "ADMAGINTCR1,Magnitude Interrupt Control Register 1" bitfld.long 0x00 26.--30. " MAG_CHID1[4-0] ,Channel number monitored by ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 16.--25. 1. " MAG_THR1[9-0] ,10-bit compare value with MAG_CHID1" textline " " bitfld.long 0x00 8.--12. " COMP_CHID1[4-0] ,Channel number compared with MAG_CHID1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1. " CHN/THR_COMP1 ,Channel OR threshold comparison" "Threshold,COMP_CHID1 channel" textline " " bitfld.long 0x00 0. " CMP_GE/LT1 ,Greater than or equal to OR less than comparison operator" "Lower,Greater" group.long 0x12C++0x03 line.long 0x00 "ADMAGINT1MASK,Magnitude Interrupt Mask 1" bitfld.long 0x00 9. " MAG_INT1_MASK[9] ,Comparison for the magnitude compare interrupt 1 mask 9" "Not masked,Masked" bitfld.long 0x00 8. " MAG_INT1_MASK[8] ,Comparison for the magnitude compare interrupt 1 mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MAG_INT1_MASK[7] ,Comparison for the magnitude compare interrupt 1 mask 7" "Not masked,Masked" bitfld.long 0x00 6. " MAG_INT1_MASK[6] ,Comparison for the magnitude compare interrupt 1 mask 6" "Not masked,Masked" textline " " bitfld.long 0x00 5. " MAG_INT1_MASK[5] ,Comparison for the magnitude compare interrupt 1 mask 5" "Not masked,Masked" bitfld.long 0x00 4. " MAG_INT1_MASK[4] ,Comparison for the magnitude compare interrupt 1 mask 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " MAG_INT1_MASK[3] ,Comparison for the magnitude compare interrupt 1 mask 3" "Not masked,Masked" bitfld.long 0x00 2. " MAG_INT1_MASK[2] ,Comparison for the magnitude compare interrupt 1 mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " MAG_INT1_MASK[1] ,Comparison for the magnitude compare interrupt 1 mask 1" "Not masked,Masked" bitfld.long 0x00 0. " MAG_INT1_MASK[0] ,Comparison for the magnitude compare interrupt 1 mask 0" "Not masked,Masked" group.long 0x130++0x03 line.long 0x00 "ADMAGINTCR2,Magnitude Interrupt Control Register 2" bitfld.long 0x00 26.--30. " MAG_CHID2[4-0] ,Channel number monitored by ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 16.--25. 1. " MAG_THR2[9-0] ,10-bit compare value with MAG_CHID2" textline " " bitfld.long 0x00 8.--12. " COMP_CHID2[4-0] ,Channel number compared with MAG_CHID2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1. " CHN/THR_COMP2 ,Channel OR threshold comparison" "Threshold,COMP_CHID1 channel" textline " " bitfld.long 0x00 0. " CMP_GE/LT2 ,Greater than or equal to OR less than comparison operator" "Lower,Greater" group.long 0x134++0x03 line.long 0x00 "ADMAGINT2MASK,Magnitude Interrupt Mask 2" bitfld.long 0x00 9. " MAG_INT2_MASK[9] ,Comparison for the magnitude compare interrupt 2 mask 9" "Not masked,Masked" bitfld.long 0x00 8. " MAG_INT2_MASK[8] ,Comparison for the magnitude compare interrupt 2 mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MAG_INT2_MASK[7] ,Comparison for the magnitude compare interrupt 2 mask 7" "Not masked,Masked" bitfld.long 0x00 6. " MAG_INT2_MASK[6] ,Comparison for the magnitude compare interrupt 2 mask 6" "Not masked,Masked" textline " " bitfld.long 0x00 5. " MAG_INT2_MASK[5] ,Comparison for the magnitude compare interrupt 2 mask 5" "Not masked,Masked" bitfld.long 0x00 4. " MAG_INT2_MASK[4] ,Comparison for the magnitude compare interrupt 2 mask 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " MAG_INT2_MASK[3] ,Comparison for the magnitude compare interrupt 2 mask 3" "Not masked,Masked" bitfld.long 0x00 2. " MAG_INT2_MASK[2] ,Comparison for the magnitude compare interrupt 2 mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " MAG_INT2_MASK[1] ,Comparison for the magnitude compare interrupt 2 mask 1" "Not masked,Masked" bitfld.long 0x00 0. " MAG_INT2_MASK[0] ,Comparison for the magnitude compare interrupt 2 mask 0" "Not masked,Masked" group.long 0x138++0x03 line.long 0x00 "ADMAGINTCR3,Magnitude Interrupt Control Register 3" bitfld.long 0x00 26.--30. " MAG_CHID3[4-0] ,Channel number monitored by ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 16.--25. 1. " MAG_THR3[9-0] ,10-bit compare value with MAG_CHID3" textline " " bitfld.long 0x00 8.--12. " COMP_CHID3[4-0] ,Channel number compared with MAG_CHID3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1. " CHN/THR_COMP3 ,Channel OR threshold comparison" "Threshold,COMP_CHID3 channel" textline " " bitfld.long 0x00 0. " CMP_GE/LT3 ,Greater than or equal to OR less than comparison operator" "Lower,Greater" group.long 0x13C++0x03 line.long 0x00 "ADMAGINT3MASK,Magnitude Interrupt Mask 3" bitfld.long 0x00 9. " MAG_INT3_MASK[9] ,Comparison for the magnitude compare interrupt 3 mask 9" "Not masked,Masked" bitfld.long 0x00 8. " MAG_INT3_MASK[8] ,Comparison for the magnitude compare interrupt 3 mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MAG_INT3_MASK[7] ,Comparison for the magnitude compare interrupt 3 mask 7" "Not masked,Masked" bitfld.long 0x00 6. " MAG_INT3_MASK[6] ,Comparison for the magnitude compare interrupt 3 mask 6" "Not masked,Masked" textline " " bitfld.long 0x00 5. " MAG_INT3_MASK[5] ,Comparison for the magnitude compare interrupt 3 mask 5" "Not masked,Masked" bitfld.long 0x00 4. " MAG_INT3_MASK[4] ,Comparison for the magnitude compare interrupt 3 mask 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " MAG_INT3_MASK[3] ,Comparison for the magnitude compare interrupt 3 mask 3" "Not masked,Masked" bitfld.long 0x00 2. " MAG_INT3_MASK[2] ,Comparison for the magnitude compare interrupt 3 mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " MAG_INT3_MASK[1] ,Comparison for the magnitude compare interrupt 3 mask 1" "Not masked,Masked" bitfld.long 0x00 0. " MAG_INT3_MASK[0] ,Comparison for the magnitude compare interrupt 3 mask 0" "Not masked,Masked" endif else group.long 0x128++0x03 line.long 0x00 "ADMAGINTCR1,Magnitude Interrupt Control Register 1" bitfld.long 0x00 26.--30. " MAG_CHID1[4-0] ,Channel number monitored by ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 16.--25. 1. " MAG_THR1[9-0] ,10-bit compare value with MAG_CHID1" textline " " bitfld.long 0x00 8.--12. " COMP_CHID1[4-0] ,Channel number compared with MAG_CHID1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1. " CHN/THR_COMP1 ,Channel OR threshold comparison" "Threshold,COMP_CHID1 channel" textline " " bitfld.long 0x00 0. " CMP_GE/LT1 ,Greater than or equal to OR less than comparison operator" "Lower,Greater" group.long 0x12C++0x03 line.long 0x00 "ADMAGINT1MASK,Magnitude Interrupt Mask 1" bitfld.long 0x00 9. " MAG_INT1_MASK[9] ,Comparison for the magnitude compare interrupt 1 mask 9" "Not masked,Masked" bitfld.long 0x00 8. " MAG_INT1_MASK[8] ,Comparison for the magnitude compare interrupt 1 mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MAG_INT1_MASK[7] ,Comparison for the magnitude compare interrupt 1 mask 7" "Not masked,Masked" bitfld.long 0x00 6. " MAG_INT1_MASK[6] ,Comparison for the magnitude compare interrupt 1 mask 6" "Not masked,Masked" textline " " bitfld.long 0x00 5. " MAG_INT1_MASK[5] ,Comparison for the magnitude compare interrupt 1 mask 5" "Not masked,Masked" bitfld.long 0x00 4. " MAG_INT1_MASK[4] ,Comparison for the magnitude compare interrupt 1 mask 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " MAG_INT1_MASK[3] ,Comparison for the magnitude compare interrupt 1 mask 3" "Not masked,Masked" bitfld.long 0x00 2. " MAG_INT1_MASK[2] ,Comparison for the magnitude compare interrupt 1 mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " MAG_INT1_MASK[1] ,Comparison for the magnitude compare interrupt 1 mask 1" "Not masked,Masked" bitfld.long 0x00 0. " MAG_INT1_MASK[0] ,Comparison for the magnitude compare interrupt 1 mask 0" "Not masked,Masked" group.long 0x130++0x03 line.long 0x00 "ADMAGINTCR2,Magnitude Interrupt Control Register 2" bitfld.long 0x00 26.--30. " MAG_CHID2[4-0] ,Channel number monitored by ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 16.--25. 1. " MAG_THR2[9-0] ,10-bit compare value with MAG_CHID2" textline " " bitfld.long 0x00 8.--12. " COMP_CHID2[4-0] ,Channel number compared with MAG_CHID2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1. " CHN/THR_COMP2 ,Channel OR threshold comparison" "Threshold,COMP_CHID1 channel" textline " " bitfld.long 0x00 0. " CMP_GE/LT2 ,Greater than or equal to OR less than comparison operator" "Lower,Greater" group.long 0x134++0x03 line.long 0x00 "ADMAGINT2MASK,Magnitude Interrupt Mask 2" bitfld.long 0x00 9. " MAG_INT2_MASK[9] ,Comparison for the magnitude compare interrupt 2 mask 9" "Not masked,Masked" bitfld.long 0x00 8. " MAG_INT2_MASK[8] ,Comparison for the magnitude compare interrupt 2 mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MAG_INT2_MASK[7] ,Comparison for the magnitude compare interrupt 2 mask 7" "Not masked,Masked" bitfld.long 0x00 6. " MAG_INT2_MASK[6] ,Comparison for the magnitude compare interrupt 2 mask 6" "Not masked,Masked" textline " " bitfld.long 0x00 5. " MAG_INT2_MASK[5] ,Comparison for the magnitude compare interrupt 2 mask 5" "Not masked,Masked" bitfld.long 0x00 4. " MAG_INT2_MASK[4] ,Comparison for the magnitude compare interrupt 2 mask 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " MAG_INT2_MASK[3] ,Comparison for the magnitude compare interrupt 2 mask 3" "Not masked,Masked" bitfld.long 0x00 2. " MAG_INT2_MASK[2] ,Comparison for the magnitude compare interrupt 2 mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " MAG_INT2_MASK[1] ,Comparison for the magnitude compare interrupt 2 mask 1" "Not masked,Masked" bitfld.long 0x00 0. " MAG_INT2_MASK[0] ,Comparison for the magnitude compare interrupt 2 mask 0" "Not masked,Masked" group.long 0x138++0x03 line.long 0x00 "ADMAGINTCR3,Magnitude Interrupt Control Register 3" bitfld.long 0x00 26.--30. " MAG_CHID3[4-0] ,Channel number monitored by ADC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 16.--25. 1. " MAG_THR3[9-0] ,10-bit compare value with MAG_CHID3" textline " " bitfld.long 0x00 8.--12. " COMP_CHID3[4-0] ,Channel number compared with MAG_CHID3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 1. " CHN/THR_COMP3 ,Channel OR threshold comparison" "Threshold,COMP_CHID3 channel" textline " " bitfld.long 0x00 0. " CMP_GE/LT3 ,Greater than or equal to OR less than comparison operator" "Lower,Greater" group.long 0x13C++0x03 line.long 0x00 "ADMAGINT3MASK,Magnitude Interrupt Mask 3" bitfld.long 0x00 9. " MAG_INT3_MASK[9] ,Comparison for the magnitude compare interrupt 3 mask 9" "Not masked,Masked" bitfld.long 0x00 8. " MAG_INT3_MASK[8] ,Comparison for the magnitude compare interrupt 3 mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MAG_INT3_MASK[7] ,Comparison for the magnitude compare interrupt 3 mask 7" "Not masked,Masked" bitfld.long 0x00 6. " MAG_INT3_MASK[6] ,Comparison for the magnitude compare interrupt 3 mask 6" "Not masked,Masked" textline " " bitfld.long 0x00 5. " MAG_INT3_MASK[5] ,Comparison for the magnitude compare interrupt 3 mask 5" "Not masked,Masked" bitfld.long 0x00 4. " MAG_INT3_MASK[4] ,Comparison for the magnitude compare interrupt 3 mask 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " MAG_INT3_MASK[3] ,Comparison for the magnitude compare interrupt 3 mask 3" "Not masked,Masked" bitfld.long 0x00 2. " MAG_INT3_MASK[2] ,Comparison for the magnitude compare interrupt 3 mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " MAG_INT3_MASK[1] ,Comparison for the magnitude compare interrupt 3 mask 1" "Not masked,Masked" bitfld.long 0x00 0. " MAG_INT3_MASK[0] ,Comparison for the magnitude compare interrupt 3 mask 0" "Not masked,Masked" endif sif (cpu()!="RM57L843-ZWT") group.long 0x140++0x1F line.long 0x00 "MAGINTCTRL4,Magnitude Interrupt Control" line.long 0x04 "MAGINT4MSK,Magnitude Interrupt Mask" line.long 0x08 "MAGINTCTRL5,Magnitude Interrupt Control" line.long 0x0C "MAGINT5MSK,Magnitude Interrupt Mask" line.long 0x10 "MAGINTCTRL6,Magnitude Interrupt Control" line.long 0x14 "MAGINT6MSK,Magnitude Interrupt Mask" line.long 0x18 "MAGTHRINTENASET,Magnitude Interrupt Enable Set" line.long 0x1C "MAGTHRINTENACLR,Magnitude Interrupt Enable Clear" endif group.long 0x160++0x03 line.long 0x00 "ADMAGINTFLG,Magnitude Compare Interrupt Flag" setclrfld.long 0x00 2. -0x08 2. -0x04 2. " MAG_INT3_SET/CLR ,Magnitude compare interrupt flag bit[3]" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 1. -0x08 1. -0x04 1. " MAG_INT2_SET/CLR ,Magnitude compare interrupt flag bit[2]" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 0. -0x08 0. -0x04 0. " MAG_INT1_SET/CLR ,Magnitude compare interrupt flag bit[1]" "No interrupt,Interrupt" hgroup.long 0x164++0x03 hide.long 0x00 "ADMAGINTOFF,Magnitude Compare Interrupt Offset" in tree.end width 17. tree "ADC RAM Control Registers" group.long 0x168++0x03 line.long 0x00 "ADEVFIFORESETCR,Event Group FIFO Reset" bitfld.long 0x00 0. " EV_FIFO_RESET ,Reset the ADC event group FIFO" "No reset,Reset" group.long 0x16C++0x03 line.long 0x00 "ADG1FIFORESETCR,Group 1 FIFO Reset" bitfld.long 0x00 0. " G1_FIFO_RESET ,Reset the ADC group 1 FIFO" "No reset,Reset" group.long 0x170++0x03 line.long 0x00 "ADG2FIFORESETCR,Group 2 FIFO Reset" bitfld.long 0x00 0. " G2_FIFO_RESET ,Reset the ADC group 2 FIFO" "No reset,Reset" rgroup.long 0x174++0x03 line.long 0x00 "ADEVRAMADDR,Event Group ADC RAM Pointer" hexmask.long.word 0x00 0.--8. 1. " EV_RAM_ADDR ,Event group ADC RAM pointer" rgroup.long 0x178++0x03 line.long 0x00 "ADG1RAMADDR,Group 1 ADC RAM Pointer" hexmask.long.word 0x00 0.--8. 1. " G1_RAM_ADDR ,Group 1 ADC RAM pointer" rgroup.long 0x17C++0x03 line.long 0x00 "ADG2RAMADDR,Group 2 ADC RAM Pointer" hexmask.long.word 0x00 0.--8. 1. " G2_RAM_ADDR ,Group 2 ADC RAM pointer" tree.end width 11. tree "ADC Parity Control Registers" group.long 0x180++0x03 line.long 0x00 "ADPARCR,Parity Control Register" bitfld.long 0x00 8. " TEST ,Parity bits map" "Not mapped,Mapped" bitfld.long 0x00 0.--3. " PARITY_ENA[3:0] ,Enable/disable parity checking" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" rgroup.long 0x184++0x03 line.long 0x00 "ADPARADDR,Parity Address" hexmask.long.word 0x00 2.--11. 0x04 " ERROR_ADDRESS ,ERROR ADDRESS" tree.end width 16. textline " " group.long 0x188++0x03 line.long 0x00 "ADPWRUPDLYCTRL,Power-Up Delay Control Register" hexmask.long.word 0x00 0.--9. 1. " PWRUP_DLY[9-0] ,Number of VCLK cycles to wait" sif (cpu()=="RM42L432"||cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE"||cpu()=="RM57L843-ZWT") width 20. tree "ADC Selection/count Registers" group.long 0x190++0x0B line.long 0x00 "ADEVCHNSELMODECTRL,ADC Event Group Channel Selection Mode Control Register" bitfld.long 0x00 0.--3. " EV_ENH_CHNSEL_MODE_EN ,Enable enhanced channel selection mode for event group" "No effect,No effect,No effect,No effect,No effect,Disabled,No effect,No effect,No effect,No effect,Enabled,No effect,No effect,No effect,No effect,No effect" line.long 0x04 "ADG1CHNSELMODECTRL,ADC Group1 Channel Selection Mode Control Register" bitfld.long 0x04 0.--3. " G1_ENH_CHNSEL_MODE_EN ,Enable enhanced channel selection mode for event group" "No effect,No effect,No effect,No effect,No effect,Disabled,No effect,No effect,No effect,No effect,Enabled,No effect,No effect,No effect,No effect,No effect" line.long 0x08 "ADG2CHNSELMODECTRL,ADC Group2 Channel Selection Mode Control Register" bitfld.long 0x08 0.--3. " G2_ENH_CHNSEL_MODE_EN ,Enable enhanced channel selection mode for event group" "No effect,No effect,No effect,No effect,No effect,Disabled,No effect,No effect,No effect,No effect,Enabled,No effect,No effect,No effect,No effect,No effect" group.long 0x19C++0x17 line.long 0x00 "ADEVCURRCOUNT,ADC Event Group Current Count Register" bitfld.long 0x00 0.--4. " EV_CURRENT_COUNT ,CURRENT_COUNT value for the event group conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "ADEVMAXCOUNT,ADC Event Group Maximum Count Register" bitfld.long 0x04 0.--4. " EV_MAX_COUNT ,MAX_COUNT value for the event group conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "ADG1CURRCOUNT,ADC Group1 Current Count Register" bitfld.long 0x08 0.--4. " G1_CURRENT_COUNT ,CURRENT_COUNT value for the group1 conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "ADG1MAXCOUNT,ADC Group1 Maximum Count Register" bitfld.long 0x0C 0.--4. " G1_MAX_COUNT ,MAX_COUNT value for the group1 conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x10 "ADG2CURRCOUNT,ADC Group2 Current Count Register" bitfld.long 0x10 0.--4. " G2_CURRENT_COUNT ,CURRENT_COUNT value for the group2 conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x14 "ADG2MAXCOUNT,ADC Group2 Maximum Count Register" bitfld.long 0x14 0.--4. " G2_MAX_COUNT ,MAX_COUNT value for the group2 conversions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end endif width 0x0B tree.end endif tree.end tree "N2HET (Enhanced High-End Timer)" sif (cpu()=="RM42L432"||cpuis("RM46L*")) tree "HIGH-END TIMER (N2HET) MODULE Registers" base ad:0x0 ; width 11. ; group.long 0x00++0x2f ; line.long 0x00 "HETGCR,HETGCR Register" ; line.long 0x04 "HETPFR,HETPFR Register" ; line.long 0x08 "HETADDR,HETADDR Register" ; line.long 0x0C "HETOFF1,HETOFF1 Register" ; line.long 0x10 "HETOFF2,HETOFF2 Register" ; line.long 0x14 "HETINTENAS,HETINTENAS Register" ; line.long 0x18 "HETINTENAC,HETINTENAC Register" ; line.long 0x1C "HETEXC1,HETEXC1 Register" ; line.long 0x20 "HETEXC2,HETEXC2 Register" ; line.long 0x24 "HETPRY,HETPRY Register" ; line.long 0x28 "HETFLG,HETFLG Register" ; line.long 0x2C "HETAND,HETAND Register" ; group.long 0x34++0x33 ; line.long 0x00 "HETHRSH,HETHRSH Register" ; line.long 0x04 "HETXOR,HETXOR Register" ; line.long 0x08 "HETREQENS,HETREQENS Register" ; line.long 0x0C "HETREQENC,HETREQENC Register" ; line.long 0x10 "HETREQDS,HETREQDS Register" ; line.long 0x14 "HETDIR,HETDIR Register" ; line.long 0x18 "HETDIN,HETDIN Register" ; line.long 0x1C "HETDOUT,HETDOUT Register" ; line.long 0x20 "HETDSET,HETDSET Register" ; line.long 0x24 "HETDCLR,HETDCLR Register" ; line.long 0x28 "HETPDR,HETPDR Register" ; line.long 0x2C "HETPULDIS,HETPULDIS Register" ; line.long 0x30 "HETPSL,HETPSL Register" ; group.long 0x74++0x1F ; line.long 0x00 "HETPCR,HETPCR Register" ; line.long 0x04 "HETPAR,HETPAR Register" ; line.long 0x08 "HETPPR,HETPPR Register" ; line.long 0x0C "HETSFPRLD,HETSFPRLD Register" ; line.long 0x10 "HETSFENA,HETSFENA Register" ; line.long 0x14 "HETLBPSEL,HETLBPSEL Register" ; line.long 0x18 "HETLBPDIR,HETLBPDIR Register" ; line.long 0x1C "HETPINDIS,HETPINDIS Register" ; There is no bit descriptions nor base address to those registers width 29. group.long 0x122A000++0x03 line.long 0x00 "REQUEST_ENABLE_CLEAR,Request_Enable_Clear Register" bitfld.long 0x00 7. " REQ_DIS_7 ,Request Disable Bit 7" "No,Yes" bitfld.long 0x00 6. " REQ_DIS_6 ,Request Disable Bit 6" "No,Yes" textline " " bitfld.long 0x00 5. " REQ_DIS_5 ,Request Disable Bit 5" "No,Yes" bitfld.long 0x00 4. " REQ_DIS_4 ,Request Disable Bit 4" "No,Yes" textline " " bitfld.long 0x00 3. " REQ_DIS_3 ,Request Disable Bit 3" "No,Yes" bitfld.long 0x00 2. " REQ_DIS_2 ,Request Disable Bit 2" "No,Yes" textline " " bitfld.long 0x00 1. " REQ_DIS_1 ,Request Disable Bit 1" "No,Yes" bitfld.long 0x00 0. " REQ_DIS_0 ,Request Disable Bit 0" "No,Yes" group.long 0x123DE20++0x03 line.long 0x00 "LOOP_BACK_PAIR_SELECT,Loop_Back_Pair_Select Register" hexmask.long.word 0x00 16.--31. 1. " ARRAY ,Loop Back Pair Type Select Bits" hexmask.long.word 0x00 0.--15. 1. " ARRAY ,Loop Back Pair Select Bits" group.long 0x12407F0++0x03 line.long 0x00 "GLOBAL_CONFIGURATION,Global_Configuration Register" bitfld.long 0x00 24. " HET_PIN_ENA ,Enables the output buffers of the pin structures" "Disabled,Enabled" bitfld.long 0x00 21.--22. " MP ,Master Priority The NHET" "0,1,2,3" textline " " bitfld.long 0x00 18. " PPF ,Protect Program Fields The PPF bit together" "0,1" bitfld.long 0x00 17. " IS ,Ignore Suspend" "Not ignored,Ignored" textline " " bitfld.long 0x00 16. " CMS ,Clk_master/slave" "Slave,Master" bitfld.long 0x00 0. " TO ,Turn On/Off" "Off,On" group.long 0x1254A00++0x03 line.long 0x00 "PARITY_CONTROL,Parity_Control Register" bitfld.long 0x00 8. " TEST ,Test Bit" "Not mapped,Mapped" bitfld.long 0x00 3. " PARITY_ENA[3] ,Enable/disable parity checking bit 3" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " PARITY_ENA[2] ,Enable/disable parity checking bit 2" "Disabled,Enabled" bitfld.long 0x00 1. " PARITY_ENA[1] ,Enable/disable parity checking bit 1" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PARITY_ENA[0] ,Enable/disable parity checking bit 0" "Disabled,Enabled" group.long 0x125BFE0++0x03 line.long 0x00 "INTERRUPT_ENABLE_SET,Interrupt_Enable_Set Register" bitfld.long 0x00 31. " HETINTENAS31 ,Interrupt Enable Set bit 31 " "Disabled,Enabled" bitfld.long 0x00 30. " HETINTENAS30 ,Interrupt Enable Set bit 30 " "Disabled,Enabled" textline " " bitfld.long 0x00 29. " HETINTENAS29 ,Interrupt Enable Set bit 29 " "Disabled,Enabled" bitfld.long 0x00 28. " HETINTENAS28 ,Interrupt Enable Set bit 28 " "Disabled,Enabled" textline " " bitfld.long 0x00 27. " HETINTENAS27 ,Interrupt Enable Set bit 27 " "Disabled,Enabled" bitfld.long 0x00 26. " HETINTENAS26 ,Interrupt Enable Set bit 26 " "Disabled,Enabled" textline " " bitfld.long 0x00 25. " HETINTENAS25 ,Interrupt Enable Set bit 25 " "Disabled,Enabled" bitfld.long 0x00 24. " HETINTENAS24 ,Interrupt Enable Set bit 24 " "Disabled,Enabled" textline " " bitfld.long 0x00 23. " HETINTENAS23 ,Interrupt Enable Set bit 23 " "Disabled,Enabled" bitfld.long 0x00 22. " HETINTENAS22 ,Interrupt Enable Set bit 22 " "Disabled,Enabled" textline " " bitfld.long 0x00 21. " HETINTENAS21 ,Interrupt Enable Set bit 21 " "Disabled,Enabled" bitfld.long 0x00 20. " HETINTENAS20 ,Interrupt Enable Set bit 20 " "Disabled,Enabled" textline " " bitfld.long 0x00 19. " HETINTENAS19 ,Interrupt Enable Set bit 19 " "Disabled,Enabled" bitfld.long 0x00 18. " HETINTENAS18 ,Interrupt Enable Set bit 18 " "Disabled,Enabled" textline " " bitfld.long 0x00 17. " HETINTENAS17 ,Interrupt Enable Set bit 17 " "Disabled,Enabled" bitfld.long 0x00 16. " HETINTENAS16 ,Interrupt Enable Set bit 16 " "Disabled,Enabled" textline " " bitfld.long 0x00 15. " HETINTENAS15 ,Interrupt Enable Set bit 15 " "Disabled,Enabled" bitfld.long 0x00 14. " HETINTENAS14 ,Interrupt Enable Set bit 14 " "Disabled,Enabled" textline " " bitfld.long 0x00 13. " HETINTENAS13 ,Interrupt Enable Set bit 13 " "Disabled,Enabled" bitfld.long 0x00 12. " HETINTENAS12 ,Interrupt Enable Set bit 12 " "Disabled,Enabled" textline " " bitfld.long 0x00 11. " HETINTENAS11 ,Interrupt Enable Set bit 11 " "Disabled,Enabled" bitfld.long 0x00 10. " HETINTENAS10 ,Interrupt Enable Set bit 10 " "Disabled,Enabled" textline " " bitfld.long 0x00 9. " HETINTENAS9 ,Interrupt Enable Set bit 9 " "Disabled,Enabled" bitfld.long 0x00 8. " HETINTENAS8 ,Interrupt Enable Set bit 8 " "Disabled,Enabled" textline " " bitfld.long 0x00 7. " HETINTENAS7 ,Interrupt Enable Set bit 7 " "Disabled,Enabled" bitfld.long 0x00 6. " HETINTENAS6 ,Interrupt Enable Set bit 6 " "Disabled,Enabled" textline " " bitfld.long 0x00 5. " HETINTENAS5 ,Interrupt Enable Set bit 5 " "Disabled,Enabled" bitfld.long 0x00 4. " HETINTENAS4 ,Interrupt Enable Set bit 4 " "Disabled,Enabled" textline " " bitfld.long 0x00 3. " HETINTENAS3 ,Interrupt Enable Set bit 3 " "Disabled,Enabled" bitfld.long 0x00 2. " HETINTENAS2 ,Interrupt Enable Set bit 2 " "Disabled,Enabled" textline " " bitfld.long 0x00 1. " HETINTENAS1 ,Interrupt Enable Set bit 1 " "Disabled,Enabled" bitfld.long 0x00 0. " HETINTENAS0 ,Interrupt Enable Set bit 0 " "Disabled,Enabled" group.long 0x125FD80++0x03 line.long 0x00 "AND_SHARE_CONTROL,AND_Share_Control Register" bitfld.long 0x00 15. " ARRAY[15] ,AND Share Enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " ARRAY[14] ,AND Share Enable bit 14" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " ARRAY[13] ,AND Share Enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " ARRAY[12] ,AND Share Enable bit 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " ARRAY[11] ,AND Share Enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " ARRAY[10] ,AND Share Enable bit 10" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " ARRAY[9] ,AND Share Enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " ARRAY[8] ,AND Share Enable bit 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " ARRAY[7] ,AND Share Enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " ARRAY[6] ,AND Share Enable bit 6" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " ARRAY[5] ,AND Share Enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " ARRAY[4] ,AND Share Enable bit 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " ARRAY[3] ,AND Share Enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " ARRAY[2] ,AND Share Enable bit 2" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " ARRAY[1] ,AND Share Enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " ARRAY[0] ,AND Share Enable bit 0" "Disabled,Enabled" group.long 0x1264B40++0x03 line.long 0x00 "PARITY_PIN,Parity_Pin Register" bitfld.long 0x00 31. " HETPPR_31 ,NHET Parity Pin Select Bit 31" "Not selected,Selected" bitfld.long 0x00 30. " HETPPR_30 ,NHET Parity Pin Select Bit 30" "Not selected,Selected" textline " " bitfld.long 0x00 29. " HETPPR_29 ,NHET Parity Pin Select Bit 29" "Not selected,Selected" bitfld.long 0x00 28. " HETPPR_28 ,NHET Parity Pin Select Bit 28" "Not selected,Selected" textline " " bitfld.long 0x00 27. " HETPPR_27 ,NHET Parity Pin Select Bit 27" "Not selected,Selected" bitfld.long 0x00 26. " HETPPR_26 ,NHET Parity Pin Select Bit 26" "Not selected,Selected" textline " " bitfld.long 0x00 25. " HETPPR_25 ,NHET Parity Pin Select Bit 25" "Not selected,Selected" bitfld.long 0x00 24. " HETPPR_24 ,NHET Parity Pin Select Bit 24" "Not selected,Selected" textline " " bitfld.long 0x00 23. " HETPPR_23 ,NHET Parity Pin Select Bit 23" "Not selected,Selected" bitfld.long 0x00 22. " HETPPR_22 ,NHET Parity Pin Select Bit 22" "Not selected,Selected" textline " " bitfld.long 0x00 21. " HETPPR_21 ,NHET Parity Pin Select Bit 21" "Not selected,Selected" bitfld.long 0x00 20. " HETPPR_20 ,NHET Parity Pin Select Bit 20" "Not selected,Selected" textline " " bitfld.long 0x00 19. " HETPPR_19 ,NHET Parity Pin Select Bit 19" "Not selected,Selected" bitfld.long 0x00 18. " HETPPR_18 ,NHET Parity Pin Select Bit 18" "Not selected,Selected" textline " " bitfld.long 0x00 17. " HETPPR_17 ,NHET Parity Pin Select Bit 17" "Not selected,Selected" bitfld.long 0x00 16. " HETPPR_16 ,NHET Parity Pin Select Bit 16" "Not selected,Selected" textline " " bitfld.long 0x00 15. " HETPPR_15 ,NHET Parity Pin Select Bit 15" "Not selected,Selected" bitfld.long 0x00 14. " HETPPR_14 ,NHET Parity Pin Select Bit 14" "Not selected,Selected" textline " " bitfld.long 0x00 13. " HETPPR_13 ,NHET Parity Pin Select Bit 13" "Not selected,Selected" bitfld.long 0x00 12. " HETPPR_12 ,NHET Parity Pin Select Bit 12" "Not selected,Selected" textline " " bitfld.long 0x00 11. " HETPPR_11 ,NHET Parity Pin Select Bit 11" "Not selected,Selected" bitfld.long 0x00 10. " HETPPR_10 ,NHET Parity Pin Select Bit 10" "Not selected,Selected" textline " " bitfld.long 0x00 9. " HETPPR_9 ,NHET Parity Pin Select Bit 9" "Not selected,Selected" bitfld.long 0x00 8. " HETPPR_8 ,NHET Parity Pin Select Bit 8" "Not selected,Selected" textline " " bitfld.long 0x00 7. " HETPPR_7 ,NHET Parity Pin Select Bit 7" "Not selected,Selected" bitfld.long 0x00 6. " HETPPR_6 ,NHET Parity Pin Select Bit 6" "Not selected,Selected" textline " " bitfld.long 0x00 5. " HETPPR_5 ,NHET Parity Pin Select Bit 5" "Not selected,Selected" bitfld.long 0x00 4. " HETPPR_4 ,NHET Parity Pin Select Bit 4" "Not selected,Selected" textline " " bitfld.long 0x00 3. " HETPPR_3 ,NHET Parity Pin Select Bit 3" "Not selected,Selected" bitfld.long 0x00 2. " HETPPR_2 ,NHET Parity Pin Select Bit 2" "Not selected,Selected" textline " " bitfld.long 0x00 1. " HETPPR_1 ,NHET Parity Pin Select Bit 1" "Not selected,Selected" bitfld.long 0x00 0. " HETPPR_0 ,NHET Parity Pin Select Bit 0" "Not selected,Selected" group.long 0x1264C10++0x03 line.long 0x00 "NHET_PIN_DISABLE,NHET_Pin_Disable Register" bitfld.long 0x00 31. " HETPINDIS_31 ,N2HET Pin Disable Bit 31" "No,Yes" bitfld.long 0x00 30. " HETPINDIS_30 ,N2HET Pin Disable Bit 30" "No,Yes" textline " " bitfld.long 0x00 29. " HETPINDIS_29 ,N2HET Pin Disable Bit 29" "No,Yes" bitfld.long 0x00 28. " HETPINDIS_28 ,N2HET Pin Disable Bit 28" "No,Yes" textline " " bitfld.long 0x00 27. " HETPINDIS_27 ,N2HET Pin Disable Bit 27" "No,Yes" bitfld.long 0x00 26. " HETPINDIS_26 ,N2HET Pin Disable Bit 26" "No,Yes" textline " " bitfld.long 0x00 25. " HETPINDIS_25 ,N2HET Pin Disable Bit 25" "No,Yes" bitfld.long 0x00 24. " HETPINDIS_24 ,N2HET Pin Disable Bit 24" "No,Yes" textline " " bitfld.long 0x00 23. " HETPINDIS_23 ,N2HET Pin Disable Bit 23" "No,Yes" bitfld.long 0x00 22. " HETPINDIS_22 ,N2HET Pin Disable Bit 22" "No,Yes" textline " " bitfld.long 0x00 21. " HETPINDIS_21 ,N2HET Pin Disable Bit 21" "No,Yes" bitfld.long 0x00 20. " HETPINDIS_20 ,N2HET Pin Disable Bit 20" "No,Yes" textline " " bitfld.long 0x00 19. " HETPINDIS_19 ,N2HET Pin Disable Bit 19" "No,Yes" bitfld.long 0x00 18. " HETPINDIS_18 ,N2HET Pin Disable Bit 18" "No,Yes" textline " " bitfld.long 0x00 17. " HETPINDIS_17 ,N2HET Pin Disable Bit 17" "No,Yes" bitfld.long 0x00 16. " HETPINDIS_16 ,N2HET Pin Disable Bit 16" "No,Yes" textline " " bitfld.long 0x00 15. " HETPINDIS_15 ,N2HET Pin Disable Bit 15" "No,Yes" bitfld.long 0x00 14. " HETPINDIS_14 ,N2HET Pin Disable Bit 14" "No,Yes" textline " " bitfld.long 0x00 13. " HETPINDIS_13 ,N2HET Pin Disable Bit 13" "No,Yes" bitfld.long 0x00 12. " HETPINDIS_12 ,N2HET Pin Disable Bit 12" "No,Yes" textline " " bitfld.long 0x00 11. " HETPINDIS_11 ,N2HET Pin Disable Bit 11" "No,Yes" bitfld.long 0x00 10. " HETPINDIS_10 ,N2HET Pin Disable Bit 10" "No,Yes" textline " " bitfld.long 0x00 9. " HETPINDIS_9 ,N2HET Pin Disable Bit 9" "No,Yes" bitfld.long 0x00 8. " HETPINDIS_8 ,N2HET Pin Disable Bit 8" "No,Yes" textline " " bitfld.long 0x00 7. " HETPINDIS_7 ,N2HET Pin Disable Bit 7" "No,Yes" bitfld.long 0x00 6. " HETPINDIS_6 ,N2HET Pin Disable Bit 6" "No,Yes" textline " " bitfld.long 0x00 5. " HETPINDIS_5 ,N2HET Pin Disable Bit 5" "No,Yes" bitfld.long 0x00 4. " HETPINDIS_4 ,N2HET Pin Disable Bit 4" "No,Yes" textline " " bitfld.long 0x00 3. " HETPINDIS_3 ,N2HET Pin Disable Bit 3" "No,Yes" bitfld.long 0x00 2. " HETPINDIS_2 ,N2HET Pin Disable Bit 2" "No,Yes" textline " " bitfld.long 0x00 1. " HETPINDIS_1 ,N2HET Pin Disable Bit 1" "No,Yes" bitfld.long 0x00 0. " HETPINDIS_0 ,N2HET Pin Disable Bit 0" "No,Yes" hgroup.long 0x12696C0++0x03 hide.long 0x00 "Exception_Control,Exception_Control Register" in group.long 0x1285C40++0x03 line.long 0x00 "N2HET_DATA_INPUT,N2HET_Data_Input Register" bitfld.long 0x00 31. " HETDIN_31 ,Data input 31" "Low,High" bitfld.long 0x00 30. " HETDIN_30 ,Data input 30" "Low,High" textline " " bitfld.long 0x00 29. " HETDIN_29 ,Data input 29" "Low,High" bitfld.long 0x00 28. " HETDIN_28 ,Data input 28" "Low,High" textline " " bitfld.long 0x00 27. " HETDIN_27 ,Data input 27" "Low,High" bitfld.long 0x00 26. " HETDIN_26 ,Data input 26" "Low,High" textline " " bitfld.long 0x00 25. " HETDIN_25 ,Data input 25" "Low,High" bitfld.long 0x00 24. " HETDIN_24 ,Data input 24" "Low,High" textline " " bitfld.long 0x00 23. " HETDIN_23 ,Data input 23" "Low,High" bitfld.long 0x00 22. " HETDIN_22 ,Data input 22" "Low,High" textline " " bitfld.long 0x00 21. " HETDIN_21 ,Data input 21" "Low,High" bitfld.long 0x00 20. " HETDIN_20 ,Data input 20" "Low,High" textline " " bitfld.long 0x00 19. " HETDIN_19 ,Data input 19" "Low,High" bitfld.long 0x00 18. " HETDIN_18 ,Data input 18" "Low,High" textline " " bitfld.long 0x00 17. " HETDIN_17 ,Data input 17" "Low,High" bitfld.long 0x00 16. " HETDIN_16 ,Data input 16" "Low,High" textline " " bitfld.long 0x00 15. " HETDIN_15 ,Data input 15" "Low,High" bitfld.long 0x00 14. " HETDIN_14 ,Data input 14" "Low,High" textline " " bitfld.long 0x00 13. " HETDIN_13 ,Data input 13" "Low,High" bitfld.long 0x00 12. " HETDIN_12 ,Data input 12" "Low,High" textline " " bitfld.long 0x00 11. " HETDIN_11 ,Data input 11" "Low,High" bitfld.long 0x00 10. " HETDIN_10 ,Data input 10" "Low,High" textline " " bitfld.long 0x00 9. " HETDIN_9 ,Data input 9" "Low,High" bitfld.long 0x00 8. " HETDIN_8 ,Data input 8" "Low,High" textline " " bitfld.long 0x00 7. " HETDIN_7 ,Data input 7" "Low,High" bitfld.long 0x00 6. " HETDIN_6 ,Data input 6" "Low,High" textline " " bitfld.long 0x00 5. " HETDIN_5 ,Data input 5" "Low,High" bitfld.long 0x00 4. " HETDIN_4 ,Data input 4" "Low,High" textline " " bitfld.long 0x00 3. " HETDIN_3 ,Data input 3" "Low,High" bitfld.long 0x00 2. " HETDIN_2 ,Data input 2" "Low,High" textline " " bitfld.long 0x00 1. " HETDIN_1 ,Data input 1" "Low,High" bitfld.long 0x00 0. " HETDIN_0 ,Data input 0" "Low,High" group.long 0x128BC90++0x03 line.long 0x00 "REQUEST_ENABLE_SET,Request_Enable_Set Register" bitfld.long 0x00 7. " REQ_ENA_7 ,Request Enable Bit 7" "No effect,Enabled" bitfld.long 0x00 6. " REQ_ENA_6 ,Request Enable Bit 6" "No effect,Enabled" textline " " bitfld.long 0x00 5. " REQ_ENA_5 ,Request Enable Bit 5" "No effect,Enabled" bitfld.long 0x00 4. " REQ_ENA_4 ,Request Enable Bit 4" "No effect,Enabled" textline " " bitfld.long 0x00 3. " REQ_ENA_3 ,Request Enable Bit 3" "No effect,Enabled" bitfld.long 0x00 2. " REQ_ENA_2 ,Request Enable Bit 2" "No effect,Enabled" textline " " bitfld.long 0x00 1. " REQ_ENA_1 ,Request Enable Bit 1" "No effect,Enabled" bitfld.long 0x00 0. " REQ_ENA_0 ,Request Enable Bit 0" "No effect,Enabled" width 28. group.long 0x1291480++0x03 line.long 0x00 "SUPPRESSION_FILTER_PRELOAD,Suppression_Filter_Preload Register" bitfld.long 0x00 16.--17. " CCDIV ,Counter Clock Divider" "VCLK2,VCLK2 / 2,VCLK2 / 3,VCLK2 / 4" hexmask.long.word 0x00 0.--9. 1. " CPRLD ,Counter Preload Value" group.long 0x129C090++0x03 line.long 0x00 "N2HET_DATA_SET,N2HET_Data_Set Register" bitfld.long 0x00 31. " HETDSET_31 ,Allows bits of HETDOUT to be set " "No effect,Set" bitfld.long 0x00 30. " HETDSET_30 ,Allows bits of HETDOUT to be set " "No effect,Set" textline " " bitfld.long 0x00 29. " HETDSET_29 ,Allows bits of HETDOUT to be set " "No effect,Set" bitfld.long 0x00 28. " HETDSET_28 ,Allows bits of HETDOUT to be set " "No effect,Set" textline " " bitfld.long 0x00 27. " HETDSET_27 ,Allows bits of HETDOUT to be set " "No effect,Set" bitfld.long 0x00 26. " HETDSET_26 ,Allows bits of HETDOUT to be set " "No effect,Set" textline " " bitfld.long 0x00 25. " HETDSET_25 ,Allows bits of HETDOUT to be set " "No effect,Set" bitfld.long 0x00 24. " HETDSET_24 ,Allows bits of HETDOUT to be set " "No effect,Set" textline " " bitfld.long 0x00 23. " HETDSET_23 ,Allows bits of HETDOUT to be set " "No effect,Set" bitfld.long 0x00 22. " HETDSET_22 ,Allows bits of HETDOUT to be set " "No effect,Set" textline " " bitfld.long 0x00 21. " HETDSET_21 ,Allows bits of HETDOUT to be set " "No effect,Set" bitfld.long 0x00 20. " HETDSET_20 ,Allows bits of HETDOUT to be set " "No effect,Set" textline " " bitfld.long 0x00 19. " HETDSET_19 ,Allows bits of HETDOUT to be set " "No effect,Set" bitfld.long 0x00 18. " HETDSET_18 ,Allows bits of HETDOUT to be set " "No effect,Set" textline " " bitfld.long 0x00 17. " HETDSET_17 ,Allows bits of HETDOUT to be set " "No effect,Set" bitfld.long 0x00 16. " HETDSET_16 ,Allows bits of HETDOUT to be set " "No effect,Set" textline " " bitfld.long 0x00 15. " HETDSET_15 ,Allows bits of HETDOUT to be set " "No effect,Set" bitfld.long 0x00 14. " HETDSET_14 ,Allows bits of HETDOUT to be set " "No effect,Set" textline " " bitfld.long 0x00 13. " HETDSET_13 ,Allows bits of HETDOUT to be set " "No effect,Set" bitfld.long 0x00 12. " HETDSET_12 ,Allows bits of HETDOUT to be set " "No effect,Set" textline " " bitfld.long 0x00 11. " HETDSET_11 ,Allows bits of HETDOUT to be set " "No effect,Set" bitfld.long 0x00 10. " HETDSET_10 ,Allows bits of HETDOUT to be set " "No effect,Set" textline " " bitfld.long 0x00 9. " HETDSET_9 ,Allows bits of HETDOUT to be set " "No effect,Set" bitfld.long 0x00 8. " HETDSET_8 ,Allows bits of HETDOUT to be set " "No effect,Set" textline " " bitfld.long 0x00 7. " HETDSET_7 ,Allows bits of HETDOUT to be set " "No effect,Set" bitfld.long 0x00 6. " HETDSET_6 ,Allows bits of HETDOUT to be set " "No effect,Set" textline " " bitfld.long 0x00 5. " HETDSET_5 ,Allows bits of HETDOUT to be set " "No effect,Set" bitfld.long 0x00 4. " HETDSET_4 ,Allows bits of HETDOUT to be set " "No effect,Set" textline " " bitfld.long 0x00 3. " HETDSET_3 ,Allows bits of HETDOUT to be set " "No effect,Set" bitfld.long 0x00 2. " HETDSET_2 ,Allows bits of HETDOUT to be set " "No effect,Set" textline " " bitfld.long 0x00 1. " HETDSET_1 ,Allows bits of HETDOUT to be set " "No effect,Set" bitfld.long 0x00 0. " HETDSET_0 ,Allows bits of HETDOUT to be set " "No effect,Set" group.long 0x129C840++0x03 line.long 0x00 "INTERRUPT_PRIORITY,Interrupt_Priority Register" bitfld.long 0x00 31. " HETPRY31 ,HET Interrupt Priority Level bit 31" "Level 2,Level 1" bitfld.long 0x00 30. " HETPRY30 ,HET Interrupt Priority Level bit 30" "Level 2,Level 1" textline " " bitfld.long 0x00 29. " HETPRY29 ,HET Interrupt Priority Level bit 29" "Level 2,Level 1" bitfld.long 0x00 28. " HETPRY28 ,HET Interrupt Priority Level bit 28" "Level 2,Level 1" textline " " bitfld.long 0x00 27. " HETPRY27 ,HET Interrupt Priority Level bit 27" "Level 2,Level 1" bitfld.long 0x00 26. " HETPRY26 ,HET Interrupt Priority Level bit 26" "Level 2,Level 1" textline " " bitfld.long 0x00 25. " HETPRY25 ,HET Interrupt Priority Level bit 25" "Level 2,Level 1" bitfld.long 0x00 24. " HETPRY24 ,HET Interrupt Priority Level bit 24" "Level 2,Level 1" textline " " bitfld.long 0x00 23. " HETPRY23 ,HET Interrupt Priority Level bit 23" "Level 2,Level 1" bitfld.long 0x00 22. " HETPRY22 ,HET Interrupt Priority Level bit 22" "Level 2,Level 1" textline " " bitfld.long 0x00 21. " HETPRY21 ,HET Interrupt Priority Level bit 21" "Level 2,Level 1" bitfld.long 0x00 20. " HETPRY20 ,HET Interrupt Priority Level bit 20" "Level 2,Level 1" textline " " bitfld.long 0x00 19. " HETPRY19 ,HET Interrupt Priority Level bit 19" "Level 2,Level 1" bitfld.long 0x00 18. " HETPRY18 ,HET Interrupt Priority Level bit 18" "Level 2,Level 1" textline " " bitfld.long 0x00 17. " HETPRY17 ,HET Interrupt Priority Level bit 17" "Level 2,Level 1" bitfld.long 0x00 16. " HETPRY16 ,HET Interrupt Priority Level bit 16" "Level 2,Level 1" textline " " bitfld.long 0x00 15. " HETPRY15 ,HET Interrupt Priority Level bit 15" "Level 2,Level 1" bitfld.long 0x00 14. " HETPRY14 ,HET Interrupt Priority Level bit 14" "Level 2,Level 1" textline " " bitfld.long 0x00 13. " HETPRY13 ,HET Interrupt Priority Level bit 13" "Level 2,Level 1" bitfld.long 0x00 12. " HETPRY12 ,HET Interrupt Priority Level bit 12" "Level 2,Level 1" textline " " bitfld.long 0x00 11. " HETPRY11 ,HET Interrupt Priority Level bit 11" "Level 2,Level 1" bitfld.long 0x00 10. " HETPRY10 ,HET Interrupt Priority Level bit 10" "Level 2,Level 1" textline " " bitfld.long 0x00 9. " HETPRY9 ,HET Interrupt Priority Level bit 9" "Level 2,Level 1" bitfld.long 0x00 8. " HETPRY8 ,HET Interrupt Priority Level bit 8" "Level 2,Level 1" textline " " bitfld.long 0x00 7. " HETPRY7 ,HET Interrupt Priority Level bit 7" "Level 2,Level 1" bitfld.long 0x00 6. " HETPRY6 ,HET Interrupt Priority Level bit 6" "Level 2,Level 1" textline " " bitfld.long 0x00 5. " HETPRY5 ,HET Interrupt Priority Level bit 5" "Level 2,Level 1" bitfld.long 0x00 4. " HETPRY4 ,HET Interrupt Priority Level bit 4" "Level 2,Level 1" textline " " bitfld.long 0x00 3. " HETPRY3 ,HET Interrupt Priority Level bit 3" "Level 2,Level 1" bitfld.long 0x00 2. " HETPRY2 ,HET Interrupt Priority Level bit 2" "Level 2,Level 1" textline " " bitfld.long 0x00 1. " HETPRY1 ,HET Interrupt Priority Level bit 1" "Level 2,Level 1" bitfld.long 0x00 0. " HETPRY0 ,HET Interrupt Priority Level bit 0" "Level 2,Level 1" group.long 0x12A0E80++0x03 line.long 0x00 "PARITY_ADDRESS,Parity_Address Register" hexmask.long.word 0x00 2.--12. 0x04 " PAOFF ,Parity Error Address Offset" group.long 0x12A5BC0++0x03 line.long 0x00 "N2HET_DATA_OUTPUT,N2HET_Data_Output Register" bitfld.long 0x00 31. " HETDOUT_31 ,Data out write" "Low,High" bitfld.long 0x00 30. " HETDOUT_30 ,Data out write" "Low,High" textline " " bitfld.long 0x00 29. " HETDOUT_29 ,Data out write" "Low,High" bitfld.long 0x00 28. " HETDOUT_28 ,Data out write" "Low,High" textline " " bitfld.long 0x00 27. " HETDOUT_27 ,Data out write" "Low,High" bitfld.long 0x00 26. " HETDOUT_26 ,Data out write" "Low,High" textline " " bitfld.long 0x00 25. " HETDOUT_25 ,Data out write" "Low,High" bitfld.long 0x00 24. " HETDOUT_24 ,Data out write" "Low,High" textline " " bitfld.long 0x00 23. " HETDOUT_23 ,Data out write" "Low,High" bitfld.long 0x00 22. " HETDOUT_22 ,Data out write" "Low,High" textline " " bitfld.long 0x00 21. " HETDOUT_21 ,Data out write" "Low,High" bitfld.long 0x00 20. " HETDOUT_20 ,Data out write" "Low,High" textline " " bitfld.long 0x00 19. " HETDOUT_19 ,Data out write" "Low,High" bitfld.long 0x00 18. " HETDOUT_18 ,Data out write" "Low,High" textline " " bitfld.long 0x00 17. " HETDOUT_17 ,Data out write" "Low,High" bitfld.long 0x00 16. " HETDOUT_16 ,Data out write" "Low,High" textline " " bitfld.long 0x00 15. " HETDOUT_15 ,Data out write" "Low,High" bitfld.long 0x00 14. " HETDOUT_14 ,Data out write" "Low,High" textline " " bitfld.long 0x00 13. " HETDOUT_13 ,Data out write" "Low,High" bitfld.long 0x00 12. " HETDOUT_12 ,Data out write" "Low,High" textline " " bitfld.long 0x00 11. " HETDOUT_11 ,Data out write" "Low,High" bitfld.long 0x00 10. " HETDOUT_10 ,Data out write" "Low,High" textline " " bitfld.long 0x00 9. " HETDOUT_9 ,Data out write" "Low,High" bitfld.long 0x00 8. " HETDOUT_8 ,Data out write" "Low,High" textline " " bitfld.long 0x00 7. " HETDOUT_7 ,Data out write" "Low,High" bitfld.long 0x00 6. " HETDOUT_6 ,Data out write" "Low,High" textline " " bitfld.long 0x00 5. " HETDOUT_5 ,Data out write" "Low,High" bitfld.long 0x00 4. " HETDOUT_4 ,Data out write" "Low,High" textline " " bitfld.long 0x00 3. " HETDOUT_3 ,Data out write" "Low,High" bitfld.long 0x00 2. " HETDOUT_2 ,Data out write" "Low,High" textline " " bitfld.long 0x00 1. " HETDOUT_1 ,Data out write" "Low,High" bitfld.long 0x00 0. " HETDOUT_0 ,Data out write" "Low,High" group.long 0x12A6090++0x03 line.long 0x00 "N2HET_PULL_DISABLE,N2HET_Pull_Disable Register" bitfld.long 0x00 31. " HETPULDIS_31 ,Pull disable for N2HET pin 31" "No,Yes" bitfld.long 0x00 30. " HETPULDIS_30 ,Pull disable for N2HET pin 30" "No,Yes" textline " " bitfld.long 0x00 29. " HETPULDIS_29 ,Pull disable for N2HET pin 29" "No,Yes" bitfld.long 0x00 28. " HETPULDIS_28 ,Pull disable for N2HET pin 28" "No,Yes" textline " " bitfld.long 0x00 27. " HETPULDIS_27 ,Pull disable for N2HET pin 27" "No,Yes" bitfld.long 0x00 26. " HETPULDIS_26 ,Pull disable for N2HET pin 26" "No,Yes" textline " " bitfld.long 0x00 25. " HETPULDIS_25 ,Pull disable for N2HET pin 25" "No,Yes" bitfld.long 0x00 24. " HETPULDIS_24 ,Pull disable for N2HET pin 24" "No,Yes" textline " " bitfld.long 0x00 23. " HETPULDIS_23 ,Pull disable for N2HET pin 23" "No,Yes" bitfld.long 0x00 22. " HETPULDIS_22 ,Pull disable for N2HET pin 22" "No,Yes" textline " " bitfld.long 0x00 21. " HETPULDIS_21 ,Pull disable for N2HET pin 21" "No,Yes" bitfld.long 0x00 20. " HETPULDIS_20 ,Pull disable for N2HET pin 20" "No,Yes" textline " " bitfld.long 0x00 19. " HETPULDIS_19 ,Pull disable for N2HET pin 19" "No,Yes" bitfld.long 0x00 18. " HETPULDIS_18 ,Pull disable for N2HET pin 18" "No,Yes" textline " " bitfld.long 0x00 17. " HETPULDIS_17 ,Pull disable for N2HET pin 17" "No,Yes" bitfld.long 0x00 16. " HETPULDIS_16 ,Pull disable for N2HET pin 16" "No,Yes" textline " " bitfld.long 0x00 15. " HETPULDIS_15 ,Pull disable for N2HET pin 15" "No,Yes" bitfld.long 0x00 14. " HETPULDIS_14 ,Pull disable for N2HET pin 14" "No,Yes" textline " " bitfld.long 0x00 13. " HETPULDIS_13 ,Pull disable for N2HET pin 13" "No,Yes" bitfld.long 0x00 12. " HETPULDIS_12 ,Pull disable for N2HET pin 12" "No,Yes" textline " " bitfld.long 0x00 11. " HETPULDIS_11 ,Pull disable for N2HET pin 11" "No,Yes" bitfld.long 0x00 10. " HETPULDIS_10 ,Pull disable for N2HET pin 10" "No,Yes" textline " " bitfld.long 0x00 9. " HETPULDIS_9 ,Pull disable for N2HET pin 9" "No,Yes" bitfld.long 0x00 8. " HETPULDIS_8 ,Pull disable for N2HET pin 8" "No,Yes" textline " " bitfld.long 0x00 7. " HETPULDIS_7 ,Pull disable for N2HET pin 7" "No,Yes" bitfld.long 0x00 6. " HETPULDIS_6 ,Pull disable for N2HET pin 6" "No,Yes" textline " " bitfld.long 0x00 5. " HETPULDIS_5 ,Pull disable for N2HET pin 5" "No,Yes" bitfld.long 0x00 4. " HETPULDIS_4 ,Pull disable for N2HET pin 4" "No,Yes" textline " " bitfld.long 0x00 3. " HETPULDIS_3 ,Pull disable for N2HET pin 3" "No,Yes" bitfld.long 0x00 2. " HETPULDIS_2 ,Pull disable for N2HET pin 2" "No,Yes" textline " " bitfld.long 0x00 1. " HETPULDIS_1 ,Pull disable for N2HET pin 1" "No,Yes" bitfld.long 0x00 0. " HETPULDIS_0 ,Pull disable for N2HET pin 0" "No,Yes" group.long 0x12AD1C0++0x03 line.long 0x00 "REQUEST_DESTINATION_SELECT,Request_Destination_Select Register" bitfld.long 0x00 23. " TDBS_23 ,HTU DMA or Both Select Bit 7" "Specified by TDS bit 7,Assigned DMA & HTU" bitfld.long 0x00 22. " TDBS_22 ,HTU DMA or Both Select Bit 6" "Specified by TDS bit 6,Assigned DMA & HTU" textline " " bitfld.long 0x00 21. " TDBS_21 ,HTU DMA or Both Select Bit 5" "Specified by TDS bit 5,Assigned DMA & HTU" bitfld.long 0x00 20. " TDBS_20 ,HTU DMA or Both Select Bit 4" "Specified by TDS bit 4,Assigned DMA & HTU" textline " " bitfld.long 0x00 19. " TDBS_19 ,HTU DMA or Both Select Bit 3" "Specified by TDS bit 3,Assigned DMA & HTU" bitfld.long 0x00 18. " TDBS_18 ,HTU DMA or Both Select Bit 2" "Specified by TDS bit 2,Assigned DMA & HTU" textline " " bitfld.long 0x00 17. " TDBS_17 ,HTU DMA or Both Select Bit 1" "Specified by TDS bit 1,Assigned DMA & HTU" bitfld.long 0x00 16. " TDBS_16 ,HTU DMA or Both Select Bit 0" "Specified by TDS bit 0,Assigned DMA & HTU" textline " " bitfld.long 0x00 7. " TDS_7 ,HTU or DMA Select Bit 7" "HTU,DMA" bitfld.long 0x00 6. " TDS_6 ,HTU or DMA Select Bit 6" "HTU,DMA" textline " " bitfld.long 0x00 5. " TDS_5 ,HTU or DMA Select Bit 5" "HTU,DMA" bitfld.long 0x00 4. " TDS_4 ,HTU or DMA Select Bit 4" "HTU,DMA" textline " " bitfld.long 0x00 3. " TDS_3 ,HTU or DMA Select Bit 3" "HTU,DMA" bitfld.long 0x00 2. " TDS_2 ,HTU or DMA Select Bit 2" "HTU,DMA" textline " " bitfld.long 0x00 1. " TDS_1 ,HTU or DMA Select Bit 1" "HTU,DMA" bitfld.long 0x00 0. " TDS_0 ,HTU or DMA Select Bit 0" "HTU,DMA" group.long 0x12B1F70++0x03 line.long 0x00 "XOR_SHARE_CONTROL,XOR_Share_Control Register" bitfld.long 0x00 15. " ARRAY[15] ,XOR Share Enable bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " ARRAY[14] ,XOR Share Enable bit 14" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " ARRAY[13] ,XOR Share Enable bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " ARRAY[12] ,XOR Share Enable bit 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " ARRAY[11] ,XOR Share Enable bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " ARRAY[10] ,XOR Share Enable bit 10" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " ARRAY[9] ,XOR Share Enable bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " ARRAY[8] ,XOR Share Enable bit 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " ARRAY[7] ,XOR Share Enable bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " ARRAY[6] ,XOR Share Enable bit 6" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " ARRAY[5] ,XOR Share Enable bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " ARRAY[4] ,XOR Share Enable bit 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " ARRAY[3] ,XOR Share Enable bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " ARRAY[2] ,XOR Share Enable bit 2" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " ARRAY[1] ,XOR Share Enable bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " ARRAY[0] ,XOR Share Enable bit 0" "Disabled,Enabled" group.long 0x12B7510++0x03 line.long 0x00 "INTERRUPT_FLAG,Interrupt_Flag Register" bitfld.long 0x00 31. " HETFLAG_31 ,Interrupt Flag Register Bit 31" "Not occurred,Occurred" bitfld.long 0x00 30. " HETFLAG_30 ,Interrupt Flag Register Bit 30" "Not occurred,Occurred" textline " " bitfld.long 0x00 29. " HETFLAG_29 ,Interrupt Flag Register Bit 29" "Not occurred,Occurred" bitfld.long 0x00 28. " HETFLAG_28 ,Interrupt Flag Register Bit 28" "Not occurred,Occurred" textline " " bitfld.long 0x00 27. " HETFLAG_27 ,Interrupt Flag Register Bit 27" "Not occurred,Occurred" bitfld.long 0x00 26. " HETFLAG_26 ,Interrupt Flag Register Bit 26" "Not occurred,Occurred" textline " " bitfld.long 0x00 25. " HETFLAG_25 ,Interrupt Flag Register Bit 25" "Not occurred,Occurred" bitfld.long 0x00 24. " HETFLAG_24 ,Interrupt Flag Register Bit 24" "Not occurred,Occurred" textline " " bitfld.long 0x00 23. " HETFLAG_23 ,Interrupt Flag Register Bit 23" "Not occurred,Occurred" bitfld.long 0x00 22. " HETFLAG_22 ,Interrupt Flag Register Bit 22" "Not occurred,Occurred" textline " " bitfld.long 0x00 21. " HETFLAG_21 ,Interrupt Flag Register Bit 21" "Not occurred,Occurred" bitfld.long 0x00 20. " HETFLAG_20 ,Interrupt Flag Register Bit 20" "Not occurred,Occurred" textline " " bitfld.long 0x00 19. " HETFLAG_19 ,Interrupt Flag Register Bit 19" "Not occurred,Occurred" bitfld.long 0x00 18. " HETFLAG_18 ,Interrupt Flag Register Bit 18" "Not occurred,Occurred" textline " " bitfld.long 0x00 17. " HETFLAG_17 ,Interrupt Flag Register Bit 17" "Not occurred,Occurred" bitfld.long 0x00 16. " HETFLAG_16 ,Interrupt Flag Register Bit 16" "Not occurred,Occurred" textline " " bitfld.long 0x00 15. " HETFLAG_15 ,Interrupt Flag Register Bit 15" "Not occurred,Occurred" bitfld.long 0x00 14. " HETFLAG_14 ,Interrupt Flag Register Bit 14" "Not occurred,Occurred" textline " " bitfld.long 0x00 13. " HETFLAG_13 ,Interrupt Flag Register Bit 13" "Not occurred,Occurred" bitfld.long 0x00 12. " HETFLAG_12 ,Interrupt Flag Register Bit 12" "Not occurred,Occurred" textline " " bitfld.long 0x00 11. " HETFLAG_11 ,Interrupt Flag Register Bit 11" "Not occurred,Occurred" bitfld.long 0x00 10. " HETFLAG_10 ,Interrupt Flag Register Bit 10" "Not occurred,Occurred" textline " " bitfld.long 0x00 9. " HETFLAG_9 ,Interrupt Flag Register Bit 9" "Not occurred,Occurred" bitfld.long 0x00 8. " HETFLAG_8 ,Interrupt Flag Register Bit 8" "Not occurred,Occurred" textline " " bitfld.long 0x00 7. " HETFLAG_7 ,Interrupt Flag Register Bit 7" "Not occurred,Occurred" bitfld.long 0x00 6. " HETFLAG_6 ,Interrupt Flag Register Bit 6" "Not occurred,Occurred" textline " " bitfld.long 0x00 5. " HETFLAG_5 ,Interrupt Flag Register Bit 5" "Not occurred,Occurred" bitfld.long 0x00 4. " HETFLAG_4 ,Interrupt Flag Register Bit 4" "Not occurred,Occurred" textline " " bitfld.long 0x00 3. " HETFLAG_3 ,Interrupt Flag Register Bit 3" "Not occurred,Occurred" bitfld.long 0x00 2. " HETFLAG_2 ,Interrupt Flag Register Bit 2" "Not occurred,Occurred" textline " " bitfld.long 0x00 1. " HETFLAG_1 ,Interrupt Flag Register Bit 1" "Not occurred,Occurred" bitfld.long 0x00 0. " HETFLAG_0 ,Interrupt Flag Register Bit 0" "Not occurred,Occurred" group.long 0x12BCD80++0x03 line.long 0x00 "N2HET_OPEN_DRAIN,N2HET_Open_Drain Register" bitfld.long 0x00 31. " HETPDR_31 ,Open drain control for HET[31] pins 31" "Push/pull,Open drain" bitfld.long 0x00 30. " HETPDR_30 ,Open drain control for HET[30] pins 30" "Push/pull,Open drain" textline " " bitfld.long 0x00 29. " HETPDR_29 ,Open drain control for HET[29] pins 29" "Push/pull,Open drain" bitfld.long 0x00 28. " HETPDR_28 ,Open drain control for HET[28] pins 28" "Push/pull,Open drain" textline " " bitfld.long 0x00 27. " HETPDR_27 ,Open drain control for HET[27] pins 27" "Push/pull,Open drain" bitfld.long 0x00 26. " HETPDR_26 ,Open drain control for HET[26] pins 26" "Push/pull,Open drain" textline " " bitfld.long 0x00 25. " HETPDR_25 ,Open drain control for HET[25] pins 25" "Push/pull,Open drain" bitfld.long 0x00 24. " HETPDR_24 ,Open drain control for HET[24] pins 24" "Push/pull,Open drain" textline " " bitfld.long 0x00 23. " HETPDR_23 ,Open drain control for HET[23] pins 23" "Push/pull,Open drain" bitfld.long 0x00 22. " HETPDR_22 ,Open drain control for HET[22] pins 22" "Push/pull,Open drain" textline " " bitfld.long 0x00 21. " HETPDR_21 ,Open drain control for HET[21] pins 21" "Push/pull,Open drain" bitfld.long 0x00 20. " HETPDR_20 ,Open drain control for HET[20] pins 20" "Push/pull,Open drain" textline " " bitfld.long 0x00 19. " HETPDR_19 ,Open drain control for HET[19] pins 19" "Push/pull,Open drain" bitfld.long 0x00 18. " HETPDR_18 ,Open drain control for HET[18] pins 18" "Push/pull,Open drain" textline " " bitfld.long 0x00 17. " HETPDR_17 ,Open drain control for HET[17] pins 17" "Push/pull,Open drain" bitfld.long 0x00 16. " HETPDR_16 ,Open drain control for HET[16] pins 16" "Push/pull,Open drain" textline " " bitfld.long 0x00 15. " HETPDR_15 ,Open drain control for HET[15] pins 15" "Push/pull,Open drain" bitfld.long 0x00 14. " HETPDR_14 ,Open drain control for HET[14] pins 14" "Push/pull,Open drain" textline " " bitfld.long 0x00 13. " HETPDR_13 ,Open drain control for HET[13] pins 13" "Push/pull,Open drain" bitfld.long 0x00 12. " HETPDR_12 ,Open drain control for HET[12] pins 12" "Push/pull,Open drain" textline " " bitfld.long 0x00 11. " HETPDR_11 ,Open drain control for HET[11] pins 11" "Push/pull,Open drain" bitfld.long 0x00 10. " HETPDR_10 ,Open drain control for HET[10] pins 10" "Push/pull,Open drain" textline " " bitfld.long 0x00 9. " HETPDR_9 ,Open drain control for HET[9] pins 9" "Push/pull,Open drain" bitfld.long 0x00 8. " HETPDR_8 ,Open drain control for HET[8] pins 8" "Push/pull,Open drain" textline " " bitfld.long 0x00 7. " HETPDR_7 ,Open drain control for HET[7] pins 7" "Push/pull,Open drain" bitfld.long 0x00 6. " HETPDR_6 ,Open drain control for HET[6] pins 6" "Push/pull,Open drain" textline " " bitfld.long 0x00 5. " HETPDR_5 ,Open drain control for HET[5] pins 5" "Push/pull,Open drain" bitfld.long 0x00 4. " HETPDR_4 ,Open drain control for HET[4] pins 4" "Push/pull,Open drain" textline " " bitfld.long 0x00 3. " HETPDR_3 ,Open drain control for HET[3] pins 3" "Push/pull,Open drain" bitfld.long 0x00 2. " HETPDR_2 ,Open drain control for HET[2] pins 2" "Push/pull,Open drain" textline " " bitfld.long 0x00 1. " HETPDR_1 ,Open drain control for HET[1] pins 1" "Push/pull,Open drain" bitfld.long 0x00 0. " HETPDR_0 ,Open drain control for HET[0] pins 0" "Push/pull,Open drain" rgroup.long 0x12D54F0++0x03 line.long 0x00 "N2HET_CURRENT_ADDRESS,N2HET_Current_Address_(HETADDR)_Field_Descriptions Register" hexmask.long.word 0x00 0.--8. 1. " HETADDR ,N2HET Current Address" group.long 0x12DAB80++0x03 line.long 0x00 "NHET_INTERRUPT_ENABLE_CLEAR,NHET_Interrupt_Enable_Clear_(HETINTENAC)_Field_Descriptions Register" bitfld.long 0x00 31. " HETINTENAC31 ,Interrupt Enable Clear bit 31" "Disabled,Enabled" bitfld.long 0x00 30. " HETINTENAC30 ,Interrupt Enable Clear bit 30" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " HETINTENAC29 ,Interrupt Enable Clear bit 29" "Disabled,Enabled" bitfld.long 0x00 28. " HETINTENAC28 ,Interrupt Enable Clear bit 28" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " HETINTENAC27 ,Interrupt Enable Clear bit 27" "Disabled,Enabled" bitfld.long 0x00 26. " HETINTENAC26 ,Interrupt Enable Clear bit 26" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " HETINTENAC25 ,Interrupt Enable Clear bit 25" "Disabled,Enabled" bitfld.long 0x00 24. " HETINTENAC24 ,Interrupt Enable Clear bit 24" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " HETINTENAC23 ,Interrupt Enable Clear bit 23" "Disabled,Enabled" bitfld.long 0x00 22. " HETINTENAC22 ,Interrupt Enable Clear bit 22" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " HETINTENAC21 ,Interrupt Enable Clear bit 21" "Disabled,Enabled" bitfld.long 0x00 20. " HETINTENAC20 ,Interrupt Enable Clear bit 20" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " HETINTENAC19 ,Interrupt Enable Clear bit 19" "Disabled,Enabled" bitfld.long 0x00 18. " HETINTENAC18 ,Interrupt Enable Clear bit 18" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " HETINTENAC17 ,Interrupt Enable Clear bit 17" "Disabled,Enabled" bitfld.long 0x00 16. " HETINTENAC16 ,Interrupt Enable Clear bit 16" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " HETINTENAC15 ,Interrupt Enable Clear bit 15" "Disabled,Enabled" bitfld.long 0x00 14. " HETINTENAC14 ,Interrupt Enable Clear bit 14" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " HETINTENAC13 ,Interrupt Enable Clear bit 13" "Disabled,Enabled" bitfld.long 0x00 12. " HETINTENAC12 ,Interrupt Enable Clear bit 12" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " HETINTENAC11 ,Interrupt Enable Clear bit 11" "Disabled,Enabled" bitfld.long 0x00 10. " HETINTENAC10 ,Interrupt Enable Clear bit 10" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " HETINTENAC9 ,Interrupt Enable Clear bit 9" "Disabled,Enabled" bitfld.long 0x00 8. " HETINTENAC8 ,Interrupt Enable Clear bit 8" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " HETINTENAC7 ,Interrupt Enable Clear bit 7" "Disabled,Enabled" bitfld.long 0x00 6. " HETINTENAC6 ,Interrupt Enable Clear bit 6" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " HETINTENAC5 ,Interrupt Enable Clear bit 5" "Disabled,Enabled" bitfld.long 0x00 4. " HETINTENAC4 ,Interrupt Enable Clear bit 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " HETINTENAC3 ,Interrupt Enable Clear bit 3" "Disabled,Enabled" bitfld.long 0x00 2. " HETINTENAC2 ,Interrupt Enable Clear bit 2" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " HETINTENAC1 ,Interrupt Enable Clear bit 1" "Disabled,Enabled" bitfld.long 0x00 0. " HETINTENAC0 ,Interrupt Enable Clear bit 0" "Disabled,Enabled" group.long 0x12DFC30++0x03 line.long 0x00 "OFFSET_INDEX_PRIOR_LV_2,Offset_Index_Priority_Level_2 Register" bitfld.long 0x00 0.--5. " OFFSET2 ,HETOFF2[5:0] indexes the currently pending high-priority interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x12E3100++0x03 line.long 0x00 "N2HET_DIRECTION,N2HET_Direction Register" bitfld.long 0x00 31. " HETDIR_31 ,Data direction of NHET pins 31" "Input,Output" bitfld.long 0x00 30. " HETDIR_30 ,Data direction of NHET pins 30" "Input,Output" textline " " bitfld.long 0x00 29. " HETDIR_29 ,Data direction of NHET pins 29" "Input,Output" bitfld.long 0x00 28. " HETDIR_28 ,Data direction of NHET pins 28" "Input,Output" textline " " bitfld.long 0x00 27. " HETDIR_27 ,Data direction of NHET pins 27" "Input,Output" bitfld.long 0x00 26. " HETDIR_26 ,Data direction of NHET pins 26" "Input,Output" textline " " bitfld.long 0x00 25. " HETDIR_25 ,Data direction of NHET pins 25" "Input,Output" bitfld.long 0x00 24. " HETDIR_24 ,Data direction of NHET pins 24" "Input,Output" textline " " bitfld.long 0x00 23. " HETDIR_23 ,Data direction of NHET pins 23" "Input,Output" bitfld.long 0x00 22. " HETDIR_22 ,Data direction of NHET pins 22" "Input,Output" textline " " bitfld.long 0x00 21. " HETDIR_21 ,Data direction of NHET pins 21" "Input,Output" bitfld.long 0x00 20. " HETDIR_20 ,Data direction of NHET pins 20" "Input,Output" textline " " bitfld.long 0x00 19. " HETDIR_19 ,Data direction of NHET pins 19" "Input,Output" bitfld.long 0x00 18. " HETDIR_18 ,Data direction of NHET pins 18" "Input,Output" textline " " bitfld.long 0x00 17. " HETDIR_17 ,Data direction of NHET pins 17" "Input,Output" bitfld.long 0x00 16. " HETDIR_16 ,Data direction of NHET pins 16" "Input,Output" textline " " bitfld.long 0x00 15. " HETDIR_15 ,Data direction of NHET pins 15" "Input,Output" bitfld.long 0x00 14. " HETDIR_14 ,Data direction of NHET pins 14" "Input,Output" textline " " bitfld.long 0x00 13. " HETDIR_13 ,Data direction of NHET pins 13" "Input,Output" bitfld.long 0x00 12. " HETDIR_12 ,Data direction of NHET pins 12" "Input,Output" textline " " bitfld.long 0x00 11. " HETDIR_11 ,Data direction of NHET pins 11" "Input,Output" bitfld.long 0x00 10. " HETDIR_10 ,Data direction of NHET pins 10" "Input,Output" textline " " bitfld.long 0x00 9. " HETDIR_9 ,Data direction of NHET pins 9" "Input,Output" bitfld.long 0x00 8. " HETDIR_8 ,Data direction of NHET pins 8" "Input,Output" textline " " bitfld.long 0x00 7. " HETDIR_7 ,Data direction of NHET pins 7" "Input,Output" bitfld.long 0x00 6. " HETDIR_6 ,Data direction of NHET pins 6" "Input,Output" textline " " bitfld.long 0x00 5. " HETDIR_5 ,Data direction of NHET pins 5" "Input,Output" bitfld.long 0x00 4. " HETDIR_4 ,Data direction of NHET pins 4" "Input,Output" textline " " bitfld.long 0x00 3. " HETDIR_3 ,Data direction of NHET pins 3" "Input,Output" bitfld.long 0x00 2. " HETDIR_2 ,Data direction of NHET pins 2" "Input,Output" textline " " bitfld.long 0x00 1. " HETDIR_1 ,Data direction of NHET pins 1" "Input,Output" bitfld.long 0x00 0. " HETDIR_0 ,Data direction of NHET pins 0" "Input,Output" group.long 0x12E7010++0x03 line.long 0x00 "PRESCALE_FACTOR,Prescale_Factor Register" bitfld.long 0x00 8.--10. " LRPFC ,Loop Resolution Pre-scale Factor Code" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--5. " HRPFC ,High Resolution Pre-scale Factor Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x12F4530++0x03 line.long 0x00 "LOOP_BACK_PAIR_DIRECTION,Loop_Back_Pair_Direction Register" bitfld.long 0x00 16.--19. " IODFTENA ,Module IODFT Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" textline " " bitfld.long 0x00 15. " ARRAY[15] ,Loop Back Pair Direction Bit 15" "0,1" bitfld.long 0x00 14. " ARRAY[14] ,Loop Back Pair Direction Bit 14" "0,1" textline " " bitfld.long 0x00 13. " ARRAY[13] ,Loop Back Pair Direction Bit 13" "0,1" bitfld.long 0x00 12. " ARRAY[12] ,Loop Back Pair Direction Bit 12" "0,1" textline " " bitfld.long 0x00 11. " ARRAY[11] ,Loop Back Pair Direction Bit 11" "0,1" bitfld.long 0x00 10. " ARRAY[10] ,Loop Back Pair Direction Bit 10" "0,1" textline " " bitfld.long 0x00 9. " ARRAY[9] ,Loop Back Pair Direction Bit 9" "0,1" bitfld.long 0x00 8. " ARRAY[8] ,Loop Back Pair Direction Bit 8" "0,1" textline " " bitfld.long 0x00 7. " ARRAY[7] ,Loop Back Pair Direction Bit 7" "0,1" bitfld.long 0x00 6. " ARRAY[6] ,Loop Back Pair Direction Bit 6" "0,1" textline " " bitfld.long 0x00 5. " ARRAY[5] ,Loop Back Pair Direction Bit 5" "0,1" bitfld.long 0x00 4. " ARRAY[4] ,Loop Back Pair Direction Bit 4" "0,1" textline " " bitfld.long 0x00 3. " ARRAY[3] ,Loop Back Pair Direction Bit 3" "0,1" bitfld.long 0x00 2. " ARRAY[2] ,Loop Back Pair Direction Bit 2" "0,1" textline " " bitfld.long 0x00 1. " ARRAY[1] ,Loop Back Pair Direction Bit 1" "0,1" bitfld.long 0x00 0. " ARRAY[0] ,Loop Back Pair Direction Bit 0" "0,1" group.long 0x12FADA0++0x03 line.long 0x00 "N2HET_DATA_CLEAR,N2HET_Data_Clear Register" bitfld.long 0x00 31. " HETDCLR_31 ,Allows bits of HETDOUT to be cleared" "No effect,Cleared" bitfld.long 0x00 30. " HETDCLR_30 ,Allows bits of HETDOUT to be cleared" "No effect,Cleared" textline " " bitfld.long 0x00 29. " HETDCLR_29 ,Allows bits of HETDOUT to be cleared" "No effect,Cleared" bitfld.long 0x00 28. " HETDCLR_28 ,Allows bits of HETDOUT to be cleared" "No effect,Cleared" textline " " bitfld.long 0x00 27. " HETDCLR_27 ,Allows bits of HETDOUT to be cleared" "No effect,Cleared" bitfld.long 0x00 26. " HETDCLR_26 ,Allows bits of HETDOUT to be cleared" "No effect,Cleared" textline " " bitfld.long 0x00 25. " HETDCLR_25 ,Allows bits of HETDOUT to be cleared" "No effect,Cleared" bitfld.long 0x00 24. " HETDCLR_24 ,Allows bits of HETDOUT to be cleared" "No effect,Cleared" textline " " bitfld.long 0x00 23. " HETDCLR_23 ,Allows bits of HETDOUT to be cleared" "No effect,Cleared" bitfld.long 0x00 22. " HETDCLR_22 ,Allows bits of HETDOUT to be cleared" "No effect,Cleared" textline " " bitfld.long 0x00 21. " HETDCLR_21 ,Allows bits of HETDOUT to be cleared" "No effect,Cleared" bitfld.long 0x00 20. " HETDCLR_20 ,Allows bits of HETDOUT to be cleared" "No effect,Cleared" textline " " bitfld.long 0x00 19. " HETDCLR_19 ,Allows bits of HETDOUT to be cleared" "No effect,Cleared" bitfld.long 0x00 18. " HETDCLR_18 ,Allows bits of HETDOUT to be cleared" "No effect,Cleared" textline " " bitfld.long 0x00 17. " HETDCLR_17 ,Allows bits of HETDOUT to be cleared" "No effect,Cleared" bitfld.long 0x00 16. " HETDCLR_16 ,Allows bits of HETDOUT to be cleared" "No effect,Cleared" textline " " bitfld.long 0x00 15. " HETDCLR_15 ,Allows bits of HETDOUT to be cleared" "No effect,Cleared" bitfld.long 0x00 14. " HETDCLR_14 ,Allows bits of HETDOUT to be cleared" "No effect,Cleared" textline " " bitfld.long 0x00 13. " HETDCLR_13 ,Allows bits of HETDOUT to be cleared" "No effect,Cleared" bitfld.long 0x00 12. " HETDCLR_12 ,Allows bits of HETDOUT to be cleared" "No effect,Cleared" textline " " bitfld.long 0x00 11. " HETDCLR_11 ,Allows bits of HETDOUT to be cleared" "No effect,Cleared" bitfld.long 0x00 10. " HETDCLR_10 ,Allows bits of HETDOUT to be cleared" "No effect,Cleared" textline " " bitfld.long 0x00 9. " HETDCLR_9 ,Allows bits of HETDOUT to be cleared" "No effect,Cleared" bitfld.long 0x00 8. " HETDCLR_8 ,Allows bits of HETDOUT to be cleared" "No effect,Cleared" textline " " bitfld.long 0x00 7. " HETDCLR_7 ,Allows bits of HETDOUT to be cleared" "No effect,Cleared" bitfld.long 0x00 6. " HETDCLR_6 ,Allows bits of HETDOUT to be cleared" "No effect,Cleared" textline " " bitfld.long 0x00 5. " HETDCLR_5 ,Allows bits of HETDOUT to be cleared" "No effect,Cleared" bitfld.long 0x00 4. " HETDCLR_4 ,Allows bits of HETDOUT to be cleared" "No effect,Cleared" textline " " bitfld.long 0x00 3. " HETDCLR_3 ,Allows bits of HETDOUT to be cleared" "No effect,Cleared" bitfld.long 0x00 2. " HETDCLR_2 ,Allows bits of HETDOUT to be cleared" "No effect,Cleared" textline " " bitfld.long 0x00 1. " HETDCLR_1 ,Allows bits of HETDOUT to be cleared" "No effect,Cleared" bitfld.long 0x00 0. " HETDCLR_0 ,Allows bits of HETDOUT to be cleared" "No effect,Cleared" group.long 0x12FB990++0x03 line.long 0x00 "OFFSET_INDEX_PRIOR_LV_1,Offset_Index_Priority_Level_1 Register" bitfld.long 0x00 0.--5. " OFFSET1 ,HETOFF1[5:0] indexes the currently pending high-priority interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1305D10++0x03 line.long 0x00 "N2HET_PULL_SELECT,N2HET_Pull_Select Register" bitfld.long 0x00 31. " HETPSL_31 ,Pull select for NHET pins 31" "0,1" bitfld.long 0x00 30. " HETPSL_30 ,Pull select for NHET pins 30" "0,1" textline " " bitfld.long 0x00 29. " HETPSL_29 ,Pull select for NHET pins 29" "0,1" bitfld.long 0x00 28. " HETPSL_28 ,Pull select for NHET pins 28" "0,1" textline " " bitfld.long 0x00 27. " HETPSL_27 ,Pull select for NHET pins 27" "0,1" bitfld.long 0x00 26. " HETPSL_26 ,Pull select for NHET pins 26" "0,1" textline " " bitfld.long 0x00 25. " HETPSL_25 ,Pull select for NHET pins 25" "0,1" bitfld.long 0x00 24. " HETPSL_24 ,Pull select for NHET pins 24" "0,1" textline " " bitfld.long 0x00 23. " HETPSL_23 ,Pull select for NHET pins 23" "0,1" bitfld.long 0x00 22. " HETPSL_22 ,Pull select for NHET pins 22" "0,1" textline " " bitfld.long 0x00 21. " HETPSL_21 ,Pull select for NHET pins 21" "0,1" bitfld.long 0x00 20. " HETPSL_20 ,Pull select for NHET pins 20" "0,1" textline " " bitfld.long 0x00 19. " HETPSL_19 ,Pull select for NHET pins 19" "0,1" bitfld.long 0x00 18. " HETPSL_18 ,Pull select for NHET pins 18" "0,1" textline " " bitfld.long 0x00 17. " HETPSL_17 ,Pull select for NHET pins 17" "0,1" bitfld.long 0x00 16. " HETPSL_16 ,Pull select for NHET pins 16" "0,1" textline " " bitfld.long 0x00 15. " HETPSL_15 ,Pull select for NHET pins 15" "0,1" bitfld.long 0x00 14. " HETPSL_14 ,Pull select for NHET pins 14" "0,1" textline " " bitfld.long 0x00 13. " HETPSL_13 ,Pull select for NHET pins 13" "0,1" bitfld.long 0x00 12. " HETPSL_12 ,Pull select for NHET pins 12" "0,1" textline " " bitfld.long 0x00 11. " HETPSL_11 ,Pull select for NHET pins 11" "0,1" bitfld.long 0x00 10. " HETPSL_10 ,Pull select for NHET pins 10" "0,1" textline " " bitfld.long 0x00 9. " HETPSL_9 ,Pull select for NHET pins 9" "0,1" bitfld.long 0x00 8. " HETPSL_8 ,Pull select for NHET pins 8" "0,1" textline " " bitfld.long 0x00 7. " HETPSL_7 ,Pull select for NHET pins 7" "0,1" bitfld.long 0x00 6. " HETPSL_6 ,Pull select for NHET pins 6" "0,1" textline " " bitfld.long 0x00 5. " HETPSL_5 ,Pull select for NHET pins 5" "0,1" bitfld.long 0x00 4. " HETPSL_4 ,Pull select for NHET pins 4" "0,1" textline " " bitfld.long 0x00 3. " HETPSL_3 ,Pull select for NHET pins 3" "0,1" bitfld.long 0x00 2. " HETPSL_2 ,Pull select for NHET pins 2" "0,1" textline " " bitfld.long 0x00 1. " HETPSL_1 ,Pull select for NHET pins 1" "0,1" bitfld.long 0x00 0. " HETPSL_0 ,Pull select for NHET pins 0" "0,1" group.long 0x13120A0++0x03 line.long 0x00 "SUPPRESSION_FILTER_ENABLE,Suppression_Filter_Enable Register" bitfld.long 0x00 31. " HETSFENA_31 ,Suppression Filter Enable Bit 31 " "Disabled,Enabled" bitfld.long 0x00 30. " HETSFENA_30 ,Suppression Filter Enable Bit 30 " "Disabled,Enabled" textline " " bitfld.long 0x00 29. " HETSFENA_29 ,Suppression Filter Enable Bit 29 " "Disabled,Enabled" bitfld.long 0x00 28. " HETSFENA_28 ,Suppression Filter Enable Bit 28 " "Disabled,Enabled" textline " " bitfld.long 0x00 27. " HETSFENA_27 ,Suppression Filter Enable Bit 27 " "Disabled,Enabled" bitfld.long 0x00 26. " HETSFENA_26 ,Suppression Filter Enable Bit 26 " "Disabled,Enabled" textline " " bitfld.long 0x00 25. " HETSFENA_25 ,Suppression Filter Enable Bit 25 " "Disabled,Enabled" bitfld.long 0x00 24. " HETSFENA_24 ,Suppression Filter Enable Bit 24 " "Disabled,Enabled" textline " " bitfld.long 0x00 23. " HETSFENA_23 ,Suppression Filter Enable Bit 23 " "Disabled,Enabled" bitfld.long 0x00 22. " HETSFENA_22 ,Suppression Filter Enable Bit 22 " "Disabled,Enabled" textline " " bitfld.long 0x00 21. " HETSFENA_21 ,Suppression Filter Enable Bit 21 " "Disabled,Enabled" bitfld.long 0x00 20. " HETSFENA_20 ,Suppression Filter Enable Bit 20 " "Disabled,Enabled" textline " " bitfld.long 0x00 19. " HETSFENA_19 ,Suppression Filter Enable Bit 19 " "Disabled,Enabled" bitfld.long 0x00 18. " HETSFENA_18 ,Suppression Filter Enable Bit 18 " "Disabled,Enabled" textline " " bitfld.long 0x00 17. " HETSFENA_17 ,Suppression Filter Enable Bit 17 " "Disabled,Enabled" bitfld.long 0x00 16. " HETSFENA_16 ,Suppression Filter Enable Bit 16 " "Disabled,Enabled" textline " " bitfld.long 0x00 15. " HETSFENA_15 ,Suppression Filter Enable Bit 15 " "Disabled,Enabled" bitfld.long 0x00 14. " HETSFENA_14 ,Suppression Filter Enable Bit 14 " "Disabled,Enabled" textline " " bitfld.long 0x00 13. " HETSFENA_13 ,Suppression Filter Enable Bit 13 " "Disabled,Enabled" bitfld.long 0x00 12. " HETSFENA_12 ,Suppression Filter Enable Bit 12 " "Disabled,Enabled" textline " " bitfld.long 0x00 11. " HETSFENA_11 ,Suppression Filter Enable Bit 11 " "Disabled,Enabled" bitfld.long 0x00 10. " HETSFENA_10 ,Suppression Filter Enable Bit 10 " "Disabled,Enabled" textline " " bitfld.long 0x00 9. " HETSFENA_9 ,Suppression Filter Enable Bit 9 " "Disabled,Enabled" bitfld.long 0x00 8. " HETSFENA_8 ,Suppression Filter Enable Bit 8 " "Disabled,Enabled" textline " " bitfld.long 0x00 7. " HETSFENA_7 ,Suppression Filter Enable Bit 7 " "Disabled,Enabled" bitfld.long 0x00 6. " HETSFENA_6 ,Suppression Filter Enable Bit 6 " "Disabled,Enabled" textline " " bitfld.long 0x00 5. " HETSFENA_5 ,Suppression Filter Enable Bit 5 " "Disabled,Enabled" bitfld.long 0x00 4. " HETSFENA_4 ,Suppression Filter Enable Bit 4 " "Disabled,Enabled" textline " " bitfld.long 0x00 3. " HETSFENA_3 ,Suppression Filter Enable Bit 3 " "Disabled,Enabled" bitfld.long 0x00 2. " HETSFENA_2 ,Suppression Filter Enable Bit 2 " "Disabled,Enabled" textline " " bitfld.long 0x00 1. " HETSFENA_1 ,Suppression Filter Enable Bit 1 " "Disabled,Enabled" bitfld.long 0x00 0. " HETSFENA_0 ,Suppression Filter Enable Bit 0 " "Disabled,Enabled" group.long 0x1312C90++0x03 line.long 0x00 "HR_SHARE_CONTROL,HR_Share_Control Register" bitfld.long 0x00 15. " ARRAY[15] ,HR Share Bit 15 enable" "Disabled,Enabled" bitfld.long 0x00 14. " ARRAY[14] ,HR Share Bit 14 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " ARRAY[13] ,HR Share Bit 13 enable" "Disabled,Enabled" bitfld.long 0x00 12. " ARRAY[12] ,HR Share Bit 12 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " ARRAY[11] ,HR Share Bit 11 enable" "Disabled,Enabled" bitfld.long 0x00 10. " ARRAY[10] ,HR Share Bit 10 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " ARRAY[9] ,HR Share Bit 9 enable" "Disabled,Enabled" bitfld.long 0x00 8. " ARRAY[8] ,HR Share Bit 8 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " ARRAY[7] ,HR Share Bit 7 enable" "Disabled,Enabled" bitfld.long 0x00 6. " ARRAY[6] ,HR Share Bit 6 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " ARRAY[5] ,HR Share Bit 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " ARRAY[4] ,HR Share Bit 4 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " ARRAY[3] ,HR Share Bit 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " ARRAY[2] ,HR Share Bit 2 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " ARRAY[1] ,HR Share Bit 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " ARRAY[0] ,HR Share Bit 0 enable" "Disabled,Enabled" width 0xB tree.end endif tree "NHET1" base ad:0xFFF7B800 sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*") endian.be endif width 15. group.long 0x00++0x07 line.long 0x0 "GCR,Global Control Register" bitfld.long 0x00 24. " HET_PIN_ENA ,NHET Pin Enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " MP ,Master Priority" "Lower,Higher,Round robin,?..." bitfld.long 0x00 18. " PPF ,Protect Program Fields" "Low,High" newline bitfld.long 0x00 17. " IS ,Ignore Suspend" "Not ignored,Ignored" bitfld.long 0x00 16. " CMS ,Clk_master/Slave" "Slave,Master" bitfld.long 0x00 0. " TO ,Turn On/Off" "Off,On" line.long 0x04 "PFR,Prescaler Factor Register" bitfld.long 0x04 8.--10. " LRPFC ,Loop Resolution Pre-scale Factor Code" "1,2,4,8,16,32,64,128" bitfld.long 0x04 0.--5. " HRPFC ,HR Prescale Factor Code" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" rgroup.long 0x08++0x0B line.long 0x0 "ADDR,Current Address Register" hexmask.long.word 0x00 0.--8. 1. " HETADDR ,N2HET Current Address" line.long 0x04 "OFF1,Offset Level 1 Register" hexmask.long.byte 0x04 0.--5. 1. " Offset1 ,Indexes the Currently Pending High-Priority Interrupt" line.long 0x08 "OFF2,Offset Level 2 Register" hexmask.long.byte 0x08 0.--5. 1. " Offset2 ,Indexes the Currently Pending High-Priority Interrupt" newline group.long 0x14++0x03 line.long 0x00 "INTENA_SETCLR,Interrupt Enable Set/Clear Register" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " HETINTENAS_setclr[31] ,Interrupt Enable Set Pin 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Interrupt enable set/clear bit 30" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Interrupt enable set/clear bit 29" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Interrupt enable set/clear bit 28" "Disabled,Enabled" newline setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Interrupt enable set/clear bit 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Interrupt enable set/clear bit 26" "Disabled,Enabled" setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Interrupt enable set/clear bit 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Interrupt enable set/clear bit 24" "Disabled,Enabled" newline setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Interrupt enable set/clear bit 23" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Interrupt enable set/clear bit 22" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Interrupt enable set/clear bit 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Interrupt enable set/clear bit 20" "Disabled,Enabled" newline setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Interrupt enable set/clear bit 19" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Interrupt enable set/clear bit 18" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Interrupt enable set/clear bit 17" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Interrupt enable set/clear bit 16" "Disabled,Enabled" newline setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Interrupt enable set/clear bit 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Interrupt enable set/clear bit 14" "Disabled,Enabled" setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Interrupt enable set/clear bit 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Interrupt enable set/clear bit 12" "Disabled,Enabled" newline setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Interrupt enable set/clear bit 11" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Interrupt enable set/clear bit 10" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Interrupt enable set/clear bit 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Interrupt enable set/clear bit 8" "Disabled,Enabled" newline setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Interrupt enable set/clear bit 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Interrupt enable set/clear bit 6" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Interrupt enable set/clear bit 5" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Interrupt enable set/clear bit 4" "Disabled,Enabled" newline setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Interrupt enable set/clear bit 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Interrupt enable set/clear bit 2" "Disabled,Enabled" setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Interrupt enable set/clear bit 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Interrupt enable set/clear bit 0" "Disabled,Enabled" newline group.long 0x1C++0x0F line.long 0x00 "EXC1,Exception Control Register 1" bitfld.long 0x00 24. " APCNT_OVRFL_ENA ,APCNT Overflow Enable" "Disabled,Enabled" bitfld.long 0x00 16. " APCNT_UNDRFL_ENA ,APCNT Underflow Enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " PRGM_OVRFL_ENA ,Program Overflow Enable" "Disabled,Enabled" bitfld.long 0x00 2. " APCNT_OVRFL_ENA_PRY ,APCNT_Ovrfl_Ena Priority" "Level 2,Level 1" newline bitfld.long 0x00 1. " APCNT_UNDRFL_ENA_PRY ,APCNT_Undrfl_Ena Priority" "Level 2,Level 1" bitfld.long 0x00 0. " PRGM_OVRFL_ENA_PRY ,Prgm_Ovrfl_Ena Priority" "Level 2,Level 1" line.long 0x04 "EXC2,Exception Control Register 2" eventfld.long 0x04 8. " DEBUG_STATUS_FLG ,Debug_Status Flag" "No NHET,NHET" eventfld.long 0x04 2. " APCNT_OVRFL_FLG ,APCNT Overflow Flag" "Not occurred,Occurred" newline eventfld.long 0x04 1. " APCNT_UNDRFL_FLG ,APCNT Underflow Flag" "Not occurred,Occurred" eventfld.long 0x04 0. " PRGM_OVERFL_FLG ,Program Overflow Flag" "Not occurred,Occurred" newline line.long 0x08 "PRY,Interrupt Priority Register" bitfld.long 0x08 31. " HETPRY[31] ,HET Priority Level Bit[31]" "Level 2,Level 1" bitfld.long 0x08 30. " [30] ,HET Priority Level Bit[30]" "Level 2,Level 1" bitfld.long 0x08 29. " [29] ,HET Priority Level Bit[29]" "Level 2,Level 1" newline bitfld.long 0x08 28. " [28] ,HET Priority Level Bit[28]" "Level 2,Level 1" bitfld.long 0x08 27. " [27] ,HET Priority Level Bit[27]" "Level 2,Level 1" bitfld.long 0x08 26. " [26] ,HET Priority Level Bit[26]" "Level 2,Level 1" newline bitfld.long 0x08 25. " [25] ,HET Priority Level Bit[25]" "Level 2,Level 1" bitfld.long 0x08 24. " [24] ,HET Priority Level Bit[24]" "Level 2,Level 1" bitfld.long 0x08 23. " [23] ,HET Priority Level Bit[23]" "Level 2,Level 1" newline bitfld.long 0x08 22. " [22] ,HET Priority Level Bit[22]" "Level 2,Level 1" bitfld.long 0x08 21. " [21] ,HET Priority Level Bit[21]" "Level 2,Level 1" bitfld.long 0x08 20. " [20] ,HET Priority Level Bit[20]" "Level 2,Level 1" newline bitfld.long 0x08 19. " [19] ,HET Priority Level Bit[19]" "Level 2,Level 1" bitfld.long 0x08 18. " [18] ,HET Priority Level Bit[18]" "Level 2,Level 1" bitfld.long 0x08 17. " [17] ,HET Priority Level Bit[17]" "Level 2,Level 1" newline bitfld.long 0x08 16. " [16] ,HET Priority Level Bit[16]" "Level 2,Level 1" bitfld.long 0x08 15. " [15] ,HET Priority Level Bit[15]" "Level 2,Level 1" bitfld.long 0x08 14. " [14] ,HET Priority Level Bit[14]" "Level 2,Level 1" newline bitfld.long 0x08 13. " [13] ,HET Priority Level Bit[13]" "Level 2,Level 1" bitfld.long 0x08 12. " [12] ,HET Priority Level Bit[12]" "Level 2,Level 1" bitfld.long 0x08 11. " [11] ,HET Priority Level Bit[11]" "Level 2,Level 1" newline bitfld.long 0x08 10. " [10] ,HET Priority Level Bit[10]" "Level 2,Level 1" bitfld.long 0x08 9. " [9] ,HET Priority Level Bit[9]" "Level 2,Level 1" bitfld.long 0x08 8. " [8] ,HET Priority Level Bit[8]" "Level 2,Level 1" newline bitfld.long 0x08 7. " [7] ,HET Priority Level Bit[7]" "Level 2,Level 1" bitfld.long 0x08 6. " [6] ,HET Priority Level Bit[6]" "Level 2,Level 1" bitfld.long 0x08 5. " [5] ,HET Priority Level Bit[5]" "Level 2,Level 1" newline bitfld.long 0x08 4. " [4] ,HET Priority Level Bit[4]" "Level 2,Level 1" bitfld.long 0x08 3. " [3] ,HET Priority Level Bit[3]" "Level 2,Level 1" bitfld.long 0x08 2. " [2] ,HET Priority Level Bit[2]" "Level 2,Level 1" newline bitfld.long 0x08 1. " [1] ,HET Priority Level Bit[1]" "Level 2,Level 1" bitfld.long 0x08 0. " HETPRY[0] ,HET Priority Level Bit[0]" "Level 2,Level 1" line.long 0x0C "FLG,Interrupt Flag Register" eventfld.long 0x0C 31. " HETFLAG[31] ,Interrupt Flag Register Bit[31]" "No interrupt,Interrupt" eventfld.long 0x0C 30. " [30] ,Interrupt Flag Register Bit[30]" "No interrupt,Interrupt" newline eventfld.long 0x0C 29. " [29] ,Interrupt Flag Register Bit[29]" "No interrupt,Interrupt" eventfld.long 0x0C 28. " [28] ,Interrupt Flag Register Bit[28]" "No interrupt,Interrupt" newline eventfld.long 0x0C 27. " [27] ,Interrupt Flag Register Bit[27]" "No interrupt,Interrupt" eventfld.long 0x0C 26. " [26] ,Interrupt Flag Register Bit[26]" "No interrupt,Interrupt" newline eventfld.long 0x0C 25. " [25] ,Interrupt Flag Register Bit[25]" "No interrupt,Interrupt" eventfld.long 0x0C 24. " [24] ,Interrupt Flag Register Bit[24]" "No interrupt,Interrupt" newline eventfld.long 0x0C 23. " [23] ,Interrupt Flag Register Bit[23]" "No interrupt,Interrupt" eventfld.long 0x0C 22. " [22] ,Interrupt Flag Register Bit[22]" "No interrupt,Interrupt" newline eventfld.long 0x0C 21. " [21] ,Interrupt Flag Register Bit[21]" "No interrupt,Interrupt" eventfld.long 0x0C 20. " [20] ,Interrupt Flag Register Bit[20]" "No interrupt,Interrupt" newline eventfld.long 0x0C 19. " [19] ,Interrupt Flag Register Bit[19]" "No interrupt,Interrupt" eventfld.long 0x0C 18. " [18] ,Interrupt Flag Register Bit[18]" "No interrupt,Interrupt" newline eventfld.long 0x0C 17. " [17] ,Interrupt Flag Register Bit[17]" "No interrupt,Interrupt" eventfld.long 0x0C 16. " [16] ,Interrupt Flag Register Bit[16]" "No interrupt,Interrupt" newline eventfld.long 0x0C 15. " [15] ,Interrupt Flag Register Bit[15]" "No interrupt,Interrupt" eventfld.long 0x0C 14. " [14] ,Interrupt Flag Register Bit[14]" "No interrupt,Interrupt" newline eventfld.long 0x0C 13. " [13] ,Interrupt Flag Register Bit[13]" "No interrupt,Interrupt" eventfld.long 0x0C 12. " [12] ,Interrupt Flag Register Bit[12]" "No interrupt,Interrupt" newline eventfld.long 0x0C 11. " [11] ,Interrupt Flag Register Bit[11]" "No interrupt,Interrupt" eventfld.long 0x0C 10. " [10] ,Interrupt Flag Register Bit[10]" "No interrupt,Interrupt" newline eventfld.long 0x0C 9. " [9] ,Interrupt Flag Register Bit[9]" "No interrupt,Interrupt" eventfld.long 0x0C 8. " [8] ,Interrupt Flag Register Bit[8]" "No interrupt,Interrupt" newline eventfld.long 0x0C 7. " [7] ,Interrupt Flag Register Bit[7]" "No interrupt,Interrupt" eventfld.long 0x0C 6. " [6] ,Interrupt Flag Register Bit[6]" "No interrupt,Interrupt" newline eventfld.long 0x0C 5. " [5] ,Interrupt Flag Register Bit[5]" "No interrupt,Interrupt" eventfld.long 0x0C 4. " [4] ,Interrupt Flag Register Bit[4]" "No interrupt,Interrupt" newline eventfld.long 0x0C 3. " [3] ,Interrupt Flag Register Bit[3]" "No interrupt,Interrupt" eventfld.long 0x0C 2. " [2] ,Interrupt Flag Register Bit[2]" "No interrupt,Interrupt" newline eventfld.long 0x0C 1. " [1] ,Interrupt Flag Register Bit[1]" "No interrupt,Interrupt" eventfld.long 0x0C 0. " [0] ,Interrupt Flag Register Bit[0]" "No interrupt,Interrupt" sif (CPU()==("TMS570LS2124-PGE")||CPU()==("TMS570LS2124-ZWT")||CPU()==("TMS570LS2134-PGE")||CPU()==("TMS570LS2134-ZWT")||CPU()==("TMS570LS3134-PGE")||CPU()==("TMS570LS3134-ZWT")||CPU()==("TMS570LS3135-PGE")||CPU()==("TMS570LS3135-ZWT")||CPU()==("TMS570LS3136")||CPU()==("TMS570LS3137-PGE")||CPU()==("TMS570LS3137-ZWT")||CPU()==("TMS570LS30336")||CPU()==("TMS570LS2126")||CPU()==("TMS570LS2127")||CPU()==("TMS570LS2136")||CPU()==("TMS570LS2137")||CPU()==("TMS570LS2125-PGE")||CPU()==("TMS570LS2125-ZWT")||CPU()==("TMS570LS2135-PGE")||CPU()==("TMS570LS2135-ZWT")||CPU()==("RM48L950")||cpu()=="RM48L952-PGE"||cpu()=="RM48L952-ZWT"||CPU()=="RM48L950-PGE"||CPU()=="RM48L950-ZWT"||CPU()=="RM48L940-ZWT"||CPU()=="RM48L940-PGE"||CPU()=="RM48L930-ZWT"||CPU()=="RM48L930-PGE"||CPU()=="RM48L750-ZWT"||CPU()=="RM48L750-PGE"||CPU()=="RM48L740-ZWT"||CPU()=="RM48L740-PGE"||CPU()=="RM48L730-ZWT"||CPU()=="RM48L730-PGE"||CPU()=="RM48L550-PGE"||CPU()=="RM48L540-ZWT"||CPU()=="RM48L540-PGE"||CPU()=="RM48L530-ZWT"||CPU()=="RM48L530-PGE"||CPU()=="RM46L852-PGE"||CPU()=="RM46L852-ZWT"||CPU()=="RM46L850-PGE"||CPU()=="RM46L850-ZWT"||CPU()=="RM46L840-ZWT"||CPU()=="RM46L840-PGE"||CPU()=="RM46L830-ZWT"||CPU()=="RM46L830-PGE"||CPU()=="RM46L450-ZWT"||CPU()=="RM46L450-PGE"||CPU()=="RM46L440-ZWT"||CPU()=="RM46L440-PGE"||CPU()=="RM46L430-ZWT"||CPU()=="RM46L430-PGE"||CPU()=="RM42L432"||CPU()=="TMS570LC4357"||CPU()==("TMS570LS0332")||CPU()==("TMS570LS0432")||CPUIS("TMS570LS1114*")||CPUIS("TMS570LS1115*")||CPUIS("TMS570LS1224*")||CPUIS("TMS570LS1225*")||CPUIS("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")) group.long 0x2C++0x3 line.long 0x00 "HETAND,And Share Control Register" bitfld.long 0x00 15. " AND_SHARE[31/30] ,And share 31/30" "Not shared,Shared" bitfld.long 0x00 14. " [29/28] ,And share 29/28" "Not shared,Shared" newline bitfld.long 0x00 13. " [27/26] ,And share 27/26" "Not shared,Shared" bitfld.long 0x00 12. " [25/24] ,And share 25/24" "Not shared,Shared" newline bitfld.long 0x00 11. " [23/22] ,And share 23/22" "Not shared,Shared" bitfld.long 0x00 10. " [21/20] ,And share 21/20" "Not shared,Shared" newline bitfld.long 0x00 9. " [19/18] ,And share 19/18" "Not shared,Shared" bitfld.long 0x00 8. " [17/16] ,And share 17/16" "Not shared,Shared" newline bitfld.long 0x00 7. " [15/14] ,And share 15/14" "Not shared,Shared" bitfld.long 0x00 6. " [13/12] ,And share 13/12" "Not shared,Shared" newline bitfld.long 0x00 5. " [11/10] ,And share 11/10" "Not shared,Shared" bitfld.long 0x00 4. " [9/8] ,And share 9/8" "Not shared,Shared" newline bitfld.long 0x00 3. " [7/6] ,And share 7/6" "Not shared,Shared" bitfld.long 0x00 2. " [5/4] ,And share 5/4" "Not shared,Shared" newline bitfld.long 0x00 1. " [3/2] ,And share 3/2" "Not shared,Shared" bitfld.long 0x00 0. " [1/0] ,And share 1/0" "Not shared,Shared" endif group.long 0x34++0x07 line.long 0x0 "HRSH,HR Share Control Register" bitfld.long 0x00 15. " HR_SHARE[31/30] ,HR Share 31/30" "Not shared,Shared" bitfld.long 0x00 14. " [29/28] ,HR Share 29/28" "Not shared,Shared" newline bitfld.long 0x00 13. " [27/26] ,HR Share 27/26" "Not shared,Shared" bitfld.long 0x00 12. " [25/24] ,HR Share 25/24" "Not shared,Shared" newline bitfld.long 0x00 11. " [23/22] ,HR Share 23/22" "Not shared,Shared" bitfld.long 0x00 10. " [21/20] ,HR Share 21/20" "Not shared,Shared" newline bitfld.long 0x00 9. " [19/18] ,HR Share 19/18" "Not shared,Shared" bitfld.long 0x00 8. " [17/16] ,HR Share 17/16" "Not shared,Shared" newline bitfld.long 0x00 7. " [15/14] ,HR Share 15/14" "Not shared,Shared" bitfld.long 0x00 6. " [13/12] ,HR Share 13/12" "Not shared,Shared" newline bitfld.long 0x00 5. " [11/10] ,HR Share 11/10" "Not shared,Shared" bitfld.long 0x00 4. " [9/8] ,HR Share 9/8" "Not shared,Shared" newline bitfld.long 0x00 3. " [7/6] ,HR Share 7/6" "Not shared,Shared" bitfld.long 0x00 2. " [5/4] ,HR Share 5/4" "Not shared,Shared" newline bitfld.long 0x00 1. " [3/2] ,HR Share 3/2" "Not shared,Shared" bitfld.long 0x00 0. " [1/0] ,HR Share 1/0" "Not shared,Shared" line.long 0x04 "XOR,HR XOR Control Register" bitfld.long 0x04 15. " HR_XOR_SHARE[31/30] ,HR XOR-Share 31/30" "Not XOR-shared,XOR-shared" bitfld.long 0x04 14. " [29/28] ,HR XOR-Share 29/28" "Not XOR-shared,XOR-shared" newline bitfld.long 0x04 13. " [27/26] ,HR XOR-Share 27/26" "Not XOR-shared,XOR-shared" bitfld.long 0x04 12. " [25/24] ,HR XOR-Share 25/24" "Not XOR-shared,XOR-shared" newline bitfld.long 0x04 11. " [23/22] ,HR XOR-Share 23/22" "Not XOR-shared,XOR-shared" bitfld.long 0x04 10. " [21/20] ,HR XOR-Share 21/20" "Not XOR-shared,XOR-shared" newline bitfld.long 0x04 9. " [19/18] ,HR XOR-Share 19/18" "Not XOR-shared,XOR-shared" bitfld.long 0x04 8. " [17/16] ,HR XOR-Share 17/16" "Not XOR-shared,XOR-shared" newline bitfld.long 0x04 7. " [15/14] ,HR XOR-Share 15/14" "Not XOR-shared,XOR-shared" bitfld.long 0x04 6. " [13/12] ,HR XOR-Share 13/12" "Not XOR-shared,XOR-shared" newline bitfld.long 0x04 5. " [11/10] ,HR XOR-Share 11/10" "Not XOR-shared,XOR-shared" bitfld.long 0x04 4. " [9/8] ,HR XOR-Share 9/8" "Not XOR-shared,XOR-shared" newline bitfld.long 0x04 3. " [7/6] ,HR XOR-Share 7/6" "Not XOR-shared,XOR-shared" bitfld.long 0x04 2. " [5/4] ,HR XOR-Share 5/4" "Not XOR-shared,XOR-shared" newline bitfld.long 0x04 1. " [3/2] ,HR XOR-Share 3/2" "Not XOR-shared,XOR-shared" bitfld.long 0x04 0. " [1/0] ,HR XOR-Share 1/0" "Not XOR-shared,XOR-shared" group.long 0x3C++0x03 line.long 0x00 "REQEN_SETCLR,Request Enable Set/Clear Register" setclrfld.long 0x00 7. 0x00 7. 0x04 7. " REQENA_SET/CLR[7] ,Request enable set/clear bit [7]" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Request enable set/clear bit [6]" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Request enable set/clear bit [5]" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Request enable set/clear bit [4]" "Disabled,Enabled" newline setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Request enable set/clear bit [3]" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Request enable set/clear bit [2]" "Disabled,Enabled" setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Request enable set/clear bit [1]" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Request enable set/clear bit [0]" "Disabled,Enabled" sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS0232")) group.long 0x44++0x3 line.long 0x00 "REQDS,Request Destination Select Register" bitfld.long 0x00 23. " TDBS[7] ,HTU/DMA or Both Select Bit[7]" "HTU,Both" bitfld.long 0x00 22. " [6] ,HTU/DMA or Both Select Bit[6]" "HTU,Both" bitfld.long 0x00 21. " [5] ,HTU/DMA or Both Select Bit[5]" "HTU,Both" bitfld.long 0x00 20. " [4] ,HTU/DMA or Both Select Bit[4]" "HTU,Both" newline bitfld.long 0x00 19. " [3] ,HTU/DMA or Both Select Bit[3]" "HTU,Both" bitfld.long 0x00 18. " [2] ,HTU/DMA or Both Select Bit[2]" "HTU,Both" bitfld.long 0x00 17. " [1] ,HTU/DMA or Both Select Bit[1]" "HTU,Both" bitfld.long 0x00 16. " [0] ,HTU/DMA or Both Select Bit[0]" "HTU,Both" newline bitfld.long 0x00 7. " TDS[7] ,HTU or DMA Select Bit[7]" "HTU,DMA" bitfld.long 0x00 6. " TDS[6] ,HTU or DMA Select Bit[6]" "HTU,DMA" bitfld.long 0x00 5. " TDS[5] ,HTU or DMA Select Bit[5]" "HTU,DMA" bitfld.long 0x00 4. " TDS[4] ,HTU or DMA Select Bit[4]" "HTU,DMA" newline bitfld.long 0x00 3. " TDS[3] ,HTU or DMA Select Bit[3]" "HTU,DMA" bitfld.long 0x00 2. " TDS[2] ,HTU or DMA Select Bit[2]" "HTU,DMA" bitfld.long 0x00 1. " TDS[1] ,HTU or DMA Select Bit[1]" "HTU,DMA" bitfld.long 0x00 0. " TDS[0] ,HTU or DMA Select Bit[0]" "HTU,DMA" endif group.long 0x4C++0x3 line.long 0x00 "DIR,Direction Register" bitfld.long 0x00 31. " HET_DIR[31] ,Input/Output Direction Pin 31" "Input,Output" bitfld.long 0x00 30. " [30] ,Input/Output Direction Pin 30" "Input,Output" bitfld.long 0x00 29. " [29] ,Input/Output Direction Pin 29" "Input,Output" newline bitfld.long 0x00 28. " [28] ,Input/Output Direction Pin 28" "Input,Output" bitfld.long 0x00 27. " [27] ,Input/Output Direction Pin 27" "Input,Output" bitfld.long 0x00 26. " [26] ,Input/Output Direction Pin 26" "Input,Output" newline bitfld.long 0x00 25. " [25] ,Input/Output Direction Pin 25" "Input,Output" bitfld.long 0x00 24. " [24] ,Input/Output Direction Pin 24" "Input,Output" bitfld.long 0x00 23. " [23] ,Input/Output Direction Pin 23" "Input,Output" newline bitfld.long 0x00 22. " [22] ,Input/Output Direction Pin 22" "Input,Output" bitfld.long 0x00 21. " [21] ,Input/Output Direction Pin 21" "Input,Output" bitfld.long 0x00 20. " [20] ,Input/Output Direction Pin 20" "Input,Output" newline bitfld.long 0x00 19. " [19] ,Input/Output Direction Pin 19" "Input,Output" bitfld.long 0x00 18. " [18] ,Input/Output Direction Pin 18" "Input,Output" bitfld.long 0x00 17. " [17] ,Input/Output Direction Pin 17" "Input,Output" newline bitfld.long 0x00 16. " [16] ,Input/Output Direction Pin 16" "Input,Output" bitfld.long 0x00 15. " [15] ,Input/Output Direction Pin 15" "Input,Output" bitfld.long 0x00 14. " [14] ,Input/Output Direction Pin 14" "Input,Output" newline bitfld.long 0x00 13. " [13] ,Input/Output Direction Pin 13" "Input,Output" bitfld.long 0x00 12. " [12] ,Input/Output Direction Pin 12" "Input,Output" bitfld.long 0x00 11. " [11] ,Input/Output Direction Pin 11" "Input,Output" newline bitfld.long 0x00 10. " [10] ,Input/Output Direction Pin 10" "Input,Output" bitfld.long 0x00 9. " [9] ,Input/Output Direction Pin 9" "Input,Output" bitfld.long 0x00 8. " [8] ,Input/Output Direction Pin 8" "Input,Output" newline bitfld.long 0x00 7. " [7] ,Input/Output Direction Pin 7" "Input,Output" bitfld.long 0x00 6. " [6] ,Input/Output Direction Pin 6" "Input,Output" bitfld.long 0x00 5. " [5] ,Input/Output Direction Pin 5" "Input,Output" newline bitfld.long 0x00 4. " [4] ,Input/Output Direction Pin 4" "Input,Output" bitfld.long 0x00 3. " [3] ,Input/Output Direction Pin 3" "Input,Output" bitfld.long 0x00 2. " [2] ,Input/Output Direction Pin 2" "Input,Output" newline bitfld.long 0x00 1. " [1] ,Input/Output Direction Pin 1" "Input,Output" bitfld.long 0x00 0. " [0] ,Input/Output Direction Pin 0" "Input,Output" rgroup.long 0x50++0x3 line.long 0x00 "DIN,Input Data Register" bitfld.long 0x00 31. " HETDIN[31] ,NHET Data Input Register Pin 31" "Low,High" bitfld.long 0x00 30. " [30] ,NHET Data Input Register Pin 30" "Low,High" bitfld.long 0x00 29. " [29] ,NHET Data Input Register Pin 29" "Low,High" bitfld.long 0x00 28. " [28] ,NHET Data Input Register Pin 28" "Low,High" newline bitfld.long 0x00 27. " [27] ,NHET Data Input Register Pin 27" "Low,High" bitfld.long 0x00 26. " [26] ,NHET Data Input Register Pin 26" "Low,High" bitfld.long 0x00 25. " [25] ,NHET Data Input Register Pin 25" "Low,High" bitfld.long 0x00 24. " [24] ,NHET Data Input Register Pin 24" "Low,High" newline bitfld.long 0x00 23. " [23] ,NHET Data Input Register Pin 23" "Low,High" bitfld.long 0x00 22. " [22] ,NHET Data Input Register Pin 22" "Low,High" bitfld.long 0x00 21. " [21] ,NHET Data Input Register Pin 21" "Low,High" bitfld.long 0x00 20. " [20] ,NHET Data Input Register Pin 20" "Low,High" newline bitfld.long 0x00 19. " [19] ,NHET Data Input Register Pin 19" "Low,High" bitfld.long 0x00 18. " [18] ,NHET Data Input Register Pin 18" "Low,High" bitfld.long 0x00 17. " [17] ,NHET Data Input Register Pin 17" "Low,High" bitfld.long 0x00 16. " [16] ,NHET Data Input Register Pin 16" "Low,High" newline bitfld.long 0x00 15. " [15] ,NHET Data Input Register Pin 15" "Low,High" bitfld.long 0x00 14. " [14] ,NHET Data Input Register Pin 14" "Low,High" bitfld.long 0x00 13. " [13] ,NHET Data Input Register Pin 13" "Low,High" bitfld.long 0x00 12. " [12] ,NHET Data Input Register Pin 12" "Low,High" newline bitfld.long 0x00 11. " [11] ,NHET Data Input Register Pin 11" "Low,High" bitfld.long 0x00 10. " [10] ,NHET Data Input Register Pin 10" "Low,High" bitfld.long 0x00 9. " [9] ,NHET Data Input Register Pin 9" "Low,High" bitfld.long 0x00 8. " [8] ,NHET Data Input Register Pin 8" "Low,High" newline bitfld.long 0x00 7. " [7] ,NHET Data Input Register Pin 7" "Low,High" bitfld.long 0x00 6. " [6] ,NHET Data Input Register Pin 6" "Low,High" bitfld.long 0x00 5. " [5] ,NHET Data Input Register Pin 5" "Low,High" bitfld.long 0x00 4. " [4] ,NHET Data Input Register Pin 4" "Low,High" newline bitfld.long 0x00 3. " [3] ,NHET Data Input Register Pin 3" "Low,High" bitfld.long 0x00 2. " [2] ,NHET Data Input Register Pin 2" "Low,High" bitfld.long 0x00 1. " [1] ,NHET Data Input Register Pin 1" "Low,High" bitfld.long 0x00 0. " [0] ,NHET Data Input Register Pin 0" "Low,High" group.long 0x54++0x3 line.long 0x00 "DOUT_SET/CLR,Output Data Set/Clear Register" setclrfld.long 0x00 31. 0x04 31. 0x08 31. " HETDOUT[31] ,NHET Data Output Register Bit[31]" "Low,High" setclrfld.long 0x00 30. 0x04 30. 0x08 30. " [30] ,NHET Data Output Register Bit[30]" "Low,High" newline setclrfld.long 0x00 29. 0x04 29. 0x08 29. " [29] ,NHET Data Output Register Bit[29]" "Low,High" setclrfld.long 0x00 28. 0x04 28. 0x08 28. " [28] ,NHET Data Output Register Bit[28]" "Low,High" newline setclrfld.long 0x00 27. 0x04 27. 0x08 27. " [27] ,NHET Data Output Register Bit[27]" "Low,High" setclrfld.long 0x00 26. 0x04 26. 0x08 26. " [26] ,NHET Data Output Register Bit[26]" "Low,High" newline setclrfld.long 0x00 25. 0x04 25. 0x08 25. " [25] ,NHET Data Output Register Bit[25]" "Low,High" setclrfld.long 0x00 24. 0x04 24. 0x08 24. " [24] ,NHET Data Output Register Bit[24]" "Low,High" newline setclrfld.long 0x00 23. 0x04 23. 0x08 23. " [23] ,NHET Data Output Register Bit[23]" "Low,High" setclrfld.long 0x00 22. 0x04 22. 0x08 22. " [22] ,NHET Data Output Register Bit[22]" "Low,High" newline setclrfld.long 0x00 21. 0x04 21. 0x08 21. " [21] ,NHET Data Output Register Bit[21]" "Low,High" setclrfld.long 0x00 20. 0x04 20. 0x08 20. " [20] ,NHET Data Output Register Bit[20]" "Low,High" newline setclrfld.long 0x00 19. 0x04 19. 0x08 19. " [19] ,NHET Data Output Register Bit[19]" "Low,High" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " [18] ,NHET Data Output Register Bit[18]" "Low,High" newline setclrfld.long 0x00 17. 0x04 17. 0x08 17. " [17] ,NHET Data Output Register Bit[17]" "Low,High" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " [16] ,NHET Data Output Register Bit[16]" "Low,High" newline setclrfld.long 0x00 15. 0x04 15. 0x08 15. " [15] ,NHET Data Output Register Bit[15]" "Low,High" setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [14] ,NHET Data Output Register Bit[14]" "Low,High" newline setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [13] ,NHET Data Output Register Bit[13]" "Low,High" setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [12] ,NHET Data Output Register Bit[12]" "Low,High" newline setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [11] ,NHET Data Output Register Bit[11]" "Low,High" setclrfld.long 0x00 10. 0x04 10. 0x08 10. " [10] ,NHET Data Output Register Bit[10]" "Low,High" newline setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [9] ,NHET Data Output Register Bit[9]" "Low,High" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [8] ,NHET Data Output Register Bit[8]" "Low,High" newline setclrfld.long 0x00 7. 0x04 7. 0x08 7. " [7] ,NHET Data Output Register Bit[7]" "Low,High" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,NHET Data Output Register Bit[6]" "Low,High" newline setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,NHET Data Output Register Bit[5]" "Low,High" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,NHET Data Output Register Bit[4]" "Low,High" newline setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,NHET Data Output Register Bit[3]" "Low,High" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,NHET Data Output Register Bit[2]" "Low,High" newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,NHET Data Output Register Bit[1]" "Low,High" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,NHET Data Output Register Bit[0]" "Low,High" group.long 0x60++0x0B line.long 0x00 "PDR,Open Drain Register" bitfld.long 0x00 31. " HETPDR[31] ,NHET Open Drain Bit[31]" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,NHET Open Drain Bit[30]" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,NHET Open Drain Bit[29]" "Disabled,Enabled" newline bitfld.long 0x00 28. " [28] ,NHET Open Drain Bit[28]" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,NHET Open Drain Bit[27]" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,NHET Open Drain Bit[26]" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,NHET Open Drain Bit[25]" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,NHET Open Drain Bit[24]" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,NHET Open Drain Bit[23]" "Disabled,Enabled" newline bitfld.long 0x00 22. " [22] ,NHET Open Drain Bit[22]" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,NHET Open Drain Bit[21]" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,NHET Open Drain Bit[20]" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,NHET Open Drain Bit[19]" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,NHET Open Drain Bit[18]" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,NHET Open Drain Bit[17]" "Disabled,Enabled" newline bitfld.long 0x00 16. " [16] ,NHET Open Drain Bit[16]" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,NHET Open Drain Bit[15]" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,NHET Open Drain Bit[14]" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,NHET Open Drain Bit[13]" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,NHET Open Drain Bit[12]" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,NHET Open Drain Bit[11]" "Disabled,Enabled" newline bitfld.long 0x00 10. " [10] ,NHET Open Drain Bit[10]" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,NHET Open Drain Bit[9]" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,NHET Open Drain Bit[8]" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,NHET Open Drain Bit[7]" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,NHET Open Drain Bit[6]" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,NHET Open Drain Bit[5]" "Disabled,Enabled" newline bitfld.long 0x00 4. " [4] ,NHET Open Drain Bit[4]" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,NHET Open Drain Bit[3]" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,NHET Open Drain Bit[2]" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,NHET Open Drain Bit[1]" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,NHET Open Drain Bit[0]" "Disabled,Enabled" line.long 0x04 "PULDIS,Pull Disable Register" bitfld.long 0x04 31. " HETPULDIS[31] ,NHET Pull Disable Bit[31]" "No,Yes" bitfld.long 0x04 30. " [30] ,NHET Pull Disable Bit[30]" "No,Yes" bitfld.long 0x04 29. " [29] ,NHET Pull Disable Bit[29]" "No,Yes" newline bitfld.long 0x04 28. " [28] ,NHET Pull Disable Bit[28]" "No,Yes" bitfld.long 0x04 27. " [27] ,NHET Pull Disable Bit[27]" "No,Yes" bitfld.long 0x04 26. " [26] ,NHET Pull Disable Bit[26]" "No,Yes" newline bitfld.long 0x04 25. " [25] ,NHET Pull Disable Bit[25]" "No,Yes" bitfld.long 0x04 24. " [24] ,NHET Pull Disable Bit[24]" "No,Yes" bitfld.long 0x04 23. " [23] ,NHET Pull Disable Bit[23]" "No,Yes" newline bitfld.long 0x04 22. " [22] ,NHET Pull Disable Bit[22]" "No,Yes" bitfld.long 0x04 21. " [21] ,NHET Pull Disable Bit[21]" "No,Yes" bitfld.long 0x04 20. " [20] ,NHET Pull Disable Bit[20]" "No,Yes" newline bitfld.long 0x04 19. " [19] ,NHET Pull Disable Bit[19]" "No,Yes" bitfld.long 0x04 18. " [18] ,NHET Pull Disable Bit[18]" "No,Yes" bitfld.long 0x04 17. " [17] ,NHET Pull Disable Bit[17]" "No,Yes" newline bitfld.long 0x04 16. " [16] ,NHET Pull Disable Bit[16]" "No,Yes" bitfld.long 0x04 15. " [15] ,NHET Pull Disable Bit[15]" "No,Yes" bitfld.long 0x04 14. " [14] ,NHET Pull Disable Bit[14]" "No,Yes" newline bitfld.long 0x04 13. " [13] ,NHET Pull Disable Bit[13]" "No,Yes" bitfld.long 0x04 12. " [12] ,NHET Pull Disable Bit[12]" "No,Yes" bitfld.long 0x04 11. " [11] ,NHET Pull Disable Bit[11]" "No,Yes" newline bitfld.long 0x04 10. " [10] ,NHET Pull Disable Bit[10]" "No,Yes" bitfld.long 0x04 9. " [9] ,NHET Pull Disable Bit[9]" "No,Yes" bitfld.long 0x04 8. " [8] ,NHET Pull Disable Bit[8]" "No,Yes" newline bitfld.long 0x04 7. " [7] ,NHET Pull Disable Bit[7]" "No,Yes" bitfld.long 0x04 6. " [6] ,NHET Pull Disable Bit[6]" "No,Yes" bitfld.long 0x04 5. " [5] ,NHET Pull Disable Bit[5]" "No,Yes" newline bitfld.long 0x04 4. " [4] ,NHET Pull Disable Bit[4]" "No,Yes" bitfld.long 0x04 3. " [3] ,NHET Pull Disable Bit[3]" "No,Yes" bitfld.long 0x04 2. " [2] ,NHET Pull Disable Bit[2]" "No,Yes" newline bitfld.long 0x04 1. " [1] ,NHET Pull Disable Bit[1]" "No,Yes" bitfld.long 0x04 0. " [0] ,NHET Pull Disable Bit[0]" "No,Yes" line.long 0x08 "PSL,Pull Select Register" bitfld.long 0x08 31. " HETPSL[31] ,NHET Pull Select Bit[31]" "Pull down,Pull up" bitfld.long 0x08 30. " [30] ,NHET Pull Select Bit[30]" "Pull down,Pull up" bitfld.long 0x08 29. " [29] ,NHET Pull Select Bit[29]" "Pull down,Pull up" newline bitfld.long 0x08 28. " [28] ,NHET Pull Select Bit[28]" "Pull down,Pull up" bitfld.long 0x08 27. " [27] ,NHET Pull Select Bit[27]" "Pull down,Pull up" bitfld.long 0x08 26. " [26] ,NHET Pull Select Bit[26]" "Pull down,Pull up" newline bitfld.long 0x08 25. " [25] ,NHET Pull Select Bit[25]" "Pull down,Pull up" bitfld.long 0x08 24. " [24] ,NHET Pull Select Bit[24]" "Pull down,Pull up" bitfld.long 0x08 23. " [23] ,NHET Pull Select Bit[23]" "Pull down,Pull up" newline bitfld.long 0x08 22. " [22] ,NHET Pull Select Bit[22]" "Pull down,Pull up" bitfld.long 0x08 21. " [21] ,NHET Pull Select Bit[21]" "Pull down,Pull up" bitfld.long 0x08 20. " [20] ,NHET Pull Select Bit[20]" "Pull down,Pull up" newline bitfld.long 0x08 19. " [19] ,NHET Pull Select Bit[19]" "Pull down,Pull up" bitfld.long 0x08 18. " [18] ,NHET Pull Select Bit[18]" "Pull down,Pull up" bitfld.long 0x08 17. " [17] ,NHET Pull Select Bit[17]" "Pull down,Pull up" newline bitfld.long 0x08 16. " [16] ,NHET Pull Select Bit[16]" "Pull down,Pull up" bitfld.long 0x08 15. " [15] ,NHET Pull Select Bit[15]" "Pull down,Pull up" bitfld.long 0x08 14. " [14] ,NHET Pull Select Bit[14]" "Pull down,Pull up" newline bitfld.long 0x08 13. " [13] ,NHET Pull Select Bit[13]" "Pull down,Pull up" bitfld.long 0x08 12. " [12] ,NHET Pull Select Bit[12]" "Pull down,Pull up" bitfld.long 0x08 11. " [11] ,NHET Pull Select Bit[11]" "Pull down,Pull up" newline bitfld.long 0x08 10. " [10] ,NHET Pull Select Bit[10]" "Pull down,Pull up" bitfld.long 0x08 9. " [9] ,NHET Pull Select Bit[9]" "Pull down,Pull up" bitfld.long 0x08 8. " [8] ,NHET Pull Select Bit[8]" "Pull down,Pull up" newline bitfld.long 0x08 7. " [7] ,NHET Pull Select Bit[7]" "Pull down,Pull up" bitfld.long 0x08 6. " [6] ,NHET Pull Select Bit[6]" "Pull down,Pull up" bitfld.long 0x08 5. " [5] ,NHET Pull Select Bit[5]" "Pull down,Pull up" newline bitfld.long 0x08 4. " [4] ,NHET Pull Select Bit[4]" "Pull down,Pull up" bitfld.long 0x08 3. " [3] ,NHET Pull Select Bit[3]" "Pull down,Pull up" bitfld.long 0x08 2. " [2] ,NHET Pull Select Bit[2]" "Pull down,Pull up" newline bitfld.long 0x08 1. " [1] ,NHET Pull Select Bit[1]" "Pull down,Pull up" bitfld.long 0x08 0. " [0] ,NHET Pull Select Bit[0]" "Pull down,Pull up" group.long 0x74++0x3 line.long 0x0 "PCR,Parity Control Register" bitfld.long 0x00 8. " TEST ,TEST" "Not mapped,Mapped" bitfld.long 0x00 0.--3. " PARITY_ENA ,Enable / Disable Parity Checking" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" rgroup.long 0x78++0x3 line.long 0x0 "PAR,Parity Address Register" hexmask.long.word 0x00 2.--12. 0x4 " PAOFF ,Parity Error Address Offset" group.long 0x7C++0x0B line.long 0x0 "PPR,Parity Pin Register" bitfld.long 0x00 31. " HETPPR[31] ,NHET Parity Pin Select Bit[31]" "Low,High" bitfld.long 0x00 30. " [30] ,NHET Parity Pin Select Bit[30]" "Low,High" bitfld.long 0x00 29. " [29] ,NHET Parity Pin Select Bit[29]" "Low,High" bitfld.long 0x00 28. " [28] ,NHET Parity Pin Select Bit[28]" "Low,High" newline bitfld.long 0x00 27. " [27] ,NHET Parity Pin Select Bit[27]" "Low,High" bitfld.long 0x00 26. " [26] ,NHET Parity Pin Select Bit[26]" "Low,High" bitfld.long 0x00 25. " [25] ,NHET Parity Pin Select Bit[25]" "Low,High" bitfld.long 0x00 24. " [24] ,NHET Parity Pin Select Bit[24]" "Low,High" newline bitfld.long 0x00 23. " [23] ,NHET Parity Pin Select Bit[23]" "Low,High" bitfld.long 0x00 22. " [22] ,NHET Parity Pin Select Bit[22]" "Low,High" bitfld.long 0x00 21. " [21] ,NHET Parity Pin Select Bit[21]" "Low,High" bitfld.long 0x00 20. " [20] ,NHET Parity Pin Select Bit[20]" "Low,High" newline bitfld.long 0x00 19. " [19] ,NHET Parity Pin Select Bit[19]" "Low,High" bitfld.long 0x00 18. " [18] ,NHET Parity Pin Select Bit[18]" "Low,High" bitfld.long 0x00 17. " [17] ,NHET Parity Pin Select Bit[17]" "Low,High" bitfld.long 0x00 16. " [16] ,NHET Parity Pin Select Bit[16]" "Low,High" newline bitfld.long 0x00 15. " [15] ,NHET Parity Pin Select Bit[15]" "Low,High" bitfld.long 0x00 14. " [14] ,NHET Parity Pin Select Bit[14]" "Low,High" bitfld.long 0x00 13. " [13] ,NHET Parity Pin Select Bit[13]" "Low,High" bitfld.long 0x00 12. " [12] ,NHET Parity Pin Select Bit[12]" "Low,High" newline bitfld.long 0x00 11. " [11] ,NHET Parity Pin Select Bit[11]" "Low,High" bitfld.long 0x00 10. " [10] ,NHET Parity Pin Select Bit[10]" "Low,High" bitfld.long 0x00 9. " [9] ,NHET Parity Pin Select Bit[9]" "Low,High" bitfld.long 0x00 8. " [8] ,NHET Parity Pin Select Bit[8]" "Low,High" newline bitfld.long 0x00 7. " [7] ,NHET Parity Pin Select Bit[7]" "Low,High" bitfld.long 0x00 6. " [6] ,NHET Parity Pin Select Bit[6]" "Low,High" bitfld.long 0x00 5. " [5] ,NHET Parity Pin Select Bit[5]" "Low,High" bitfld.long 0x00 4. " [4] ,NHET Parity Pin Select Bit[4]" "Low,High" newline bitfld.long 0x00 3. " [3] ,NHET Parity Pin Select Bit[3]" "Low,High" bitfld.long 0x00 2. " [2] ,NHET Parity Pin Select Bit[2]" "Low,High" bitfld.long 0x00 1. " [1] ,NHET Parity Pin Select Bit[1]" "Low,High" bitfld.long 0x00 0. " [0] ,NHET Parity Pin Select Bit[0]" "Low,High" line.long 0x04 "SFPRLD,Suppresion Filter Preload Register" bitfld.long 0x04 16.--17. " CCDIV ,Counter Clock Divider" "VCLK2,VCLK2/2,VCLK2/3,VCLK2/4" hexmask.long.word 0x04 0.--9. 1. " CPRLD ,Counter Preload Value" line.long 0x08 "SFENA,Suppresion Filter Enable Register" bitfld.long 0x08 31. " HETSFENA[31] ,Suppression Filter Enable Bit[31]" "Disabled,Enabled" bitfld.long 0x08 30. " [30] ,Suppression Filter Enable Bit[30]" "Disabled,Enabled" bitfld.long 0x08 29. " [29] ,Suppression Filter Enable Bit[29]" "Disabled,Enabled" newline bitfld.long 0x08 28. " [28] ,Suppression Filter Enable Bit[28]" "Disabled,Enabled" bitfld.long 0x08 27. " [27] ,Suppression Filter Enable Bit[27]" "Disabled,Enabled" bitfld.long 0x08 26. " [26] ,Suppression Filter Enable Bit[26]" "Disabled,Enabled" newline bitfld.long 0x08 25. " [25] ,Suppression Filter Enable Bit[25]" "Disabled,Enabled" bitfld.long 0x08 24. " [24] ,Suppression Filter Enable Bit[24]" "Disabled,Enabled" bitfld.long 0x08 23. " [23] ,Suppression Filter Enable Bit[23]" "Disabled,Enabled" newline bitfld.long 0x08 22. " [22] ,Suppression Filter Enable Bit[22]" "Disabled,Enabled" bitfld.long 0x08 21. " [21] ,Suppression Filter Enable Bit[21]" "Disabled,Enabled" bitfld.long 0x08 20. " [20] ,Suppression Filter Enable Bit[20]" "Disabled,Enabled" newline bitfld.long 0x08 19. " [19] ,Suppression Filter Enable Bit[19]" "Disabled,Enabled" bitfld.long 0x08 18. " [18] ,Suppression Filter Enable Bit[18]" "Disabled,Enabled" bitfld.long 0x08 17. " [17] ,Suppression Filter Enable Bit[17]" "Disabled,Enabled" newline bitfld.long 0x08 16. " [16] ,Suppression Filter Enable Bit[16]" "Disabled,Enabled" bitfld.long 0x08 15. " [15] ,Suppression Filter Enable Bit[15]" "Disabled,Enabled" bitfld.long 0x08 14. " [14] ,Suppression Filter Enable Bit[14]" "Disabled,Enabled" newline bitfld.long 0x08 13. " [13] ,Suppression Filter Enable Bit[13]" "Disabled,Enabled" bitfld.long 0x08 12. " [12] ,Suppression Filter Enable Bit[12]" "Disabled,Enabled" bitfld.long 0x08 11. " [11] ,Suppression Filter Enable Bit[11]" "Disabled,Enabled" newline bitfld.long 0x08 10. " [10] ,Suppression Filter Enable Bit[10]" "Disabled,Enabled" bitfld.long 0x08 9. " [9] ,Suppression Filter Enable Bit[9]" "Disabled,Enabled" bitfld.long 0x08 8. " [8] ,Suppression Filter Enable Bit[8]" "Disabled,Enabled" newline bitfld.long 0x08 7. " [7] ,Suppression Filter Enable Bit[7]" "Disabled,Enabled" bitfld.long 0x08 6. " [6] ,Suppression Filter Enable Bit[6]" "Disabled,Enabled" bitfld.long 0x08 5. " [5] ,Suppression Filter Enable Bit[5]" "Disabled,Enabled" newline bitfld.long 0x08 4. " [4] ,Suppression Filter Enable Bit[4]" "Disabled,Enabled" bitfld.long 0x08 3. " [3] ,Suppression Filter Enable Bit[3]" "Disabled,Enabled" bitfld.long 0x08 2. " [2] ,Suppression Filter Enable Bit[2]" "Disabled,Enabled" newline bitfld.long 0x08 1. " [1] ,Suppression Filter Enable Bit[1]" "Disabled,Enabled" bitfld.long 0x08 0. " [0] ,Suppression Filter Enable Bit[0]" "Disabled,Enabled" sif (cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&cpu()!="TMS570LC4357"&&cpu()!="RM48L550-ZWT"&&cpu()!="RM42L432"&&!cpuis("TMS570LS0232")&&!cpuis("TMS570LS0714*")&&!cpuis("TMS570LS0914*")) if ((per.l(ad:0xFFF7B800+0x90)&0xF00)==0xA00) group.long 0x8C++0x3 line.long 0x0 "LBPSEL,Loop Back Pair Select Register" bitfld.long 0x00 31. " LBPTYPE[15] ,Loop Back Pair Type Select Bit[15]" "Digital,Analog" bitfld.long 0x00 30. " [14] ,Loop Back Pair Type Select Bit[14]" "Digital,Analog" newline bitfld.long 0x00 29. " [13] ,Loop Back Pair Type Select Bit[13]" "Digital,Analog" bitfld.long 0x00 28. " [12] ,Loop Back Pair Type Select Bit[12]" "Digital,Analog" newline bitfld.long 0x00 27. " [11] ,Loop Back Pair Type Select Bit[11]" "Digital,Analog" bitfld.long 0x00 26. " [10] ,Loop Back Pair Type Select Bit[10]" "Digital,Analog" newline bitfld.long 0x00 25. " [9] ,Loop Back Pair Type Select Bit[9]" "Digital,Analog" bitfld.long 0x00 24. " [8] ,Loop Back Pair Type Select Bit[8]" "Digital,Analog" newline bitfld.long 0x00 23. " [7] ,Loop Back Pair Type Select Bit[7]" "Digital,Analog" bitfld.long 0x00 22. " [6] ,Loop Back Pair Type Select Bit[6]" "Digital,Analog" newline bitfld.long 0x00 21. " [5] ,Loop Back Pair Type Select Bit[5]" "Digital,Analog" bitfld.long 0x00 20. " [4] ,Loop Back Pair Type Select Bit[4]" "Digital,Analog" newline bitfld.long 0x00 19. " [3] ,Loop Back Pair Type Select Bit[3]" "Digital,Analog" bitfld.long 0x00 18. " [2] ,Loop Back Pair Type Select Bit[2]" "Digital,Analog" newline bitfld.long 0x00 17. " [1] ,Loop Back Pair Type Select Bit[1]" "Digital,Analog" bitfld.long 0x00 16. " [0] ,Loop Back Pair Type Select Bit[0]" "Digital,Analog" newline bitfld.long 0x00 15. " LBPSEL[15] ,Loop Back Pair Select Bit[15]" "Not selected,Selected" bitfld.long 0x00 14. " [14] ,Loop Back Pair Select Bit[14]" "Not selected,Selected" newline bitfld.long 0x00 13. " [13] ,Loop Back Pair Select Bit[13]" "Not selected,Selected" bitfld.long 0x00 12. " [12] ,Loop Back Pair Select Bit[12]" "Not selected,Selected" newline bitfld.long 0x00 11. " [11] ,Loop Back Pair Select Bit[11]" "Not selected,Selected" bitfld.long 0x00 10. " [10] ,Loop Back Pair Select Bit[10]" "Not selected,Selected" newline bitfld.long 0x00 9. " [9] ,Loop Back Pair Select Bit[9]" "Not selected,Selected" bitfld.long 0x00 8. " [8] ,Loop Back Pair Select Bit[8]" "Not selected,Selected" newline bitfld.long 0x00 7. " [7] ,Loop Back Pair Select Bit[7]" "Not selected,Selected" bitfld.long 0x00 6. " [6] ,Loop Back Pair Select Bit[6]" "Not selected,Selected" newline bitfld.long 0x00 5. " [5] ,Loop Back Pair Select Bit[5]" "Not selected,Selected" bitfld.long 0x00 4. " [4] ,Loop Back Pair Select Bit[4]" "Not selected,Selected" newline bitfld.long 0x00 3. " [3] ,Loop Back Pair Select Bit[3]" "Not selected,Selected" bitfld.long 0x00 2. " [2] ,Loop Back Pair Select Bit[2]" "Not selected,Selected" newline bitfld.long 0x00 1. " [1] ,Loop Back Pair Select Bit[1]" "Not selected,Selected" bitfld.long 0x00 0. " [0] ,Loop Back Pair Select Bit[0]" "Not selected,Selected" else hgroup.long 0x8C++0x3 hide.long 0x0 "LBPSEL,Loop Back Pair Select Register" endif elif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*") if ((per.l.be(ad:0xFFF7B800+0x90)&0xF0000)==0xA0000) group.long 0x8C++0x3 line.long 0x0 "LBPSEL,Loop Back Pair Select Register" bitfld.long 0x00 31. " LBPTYPE[31/30] ,Loop Back Pair Type Select Bits 31/30" "Digital,Analog" bitfld.long 0x00 30. " [29/28] ,Loop Back Pair Type Select Bits 29/28" "Digital,Analog" newline bitfld.long 0x00 29. " [27/26] ,Loop Back Pair Type Select Bits 27/26" "Digital,Analog" bitfld.long 0x00 28. " [25/24] ,Loop Back Pair Type Select Bits 25/24" "Digital,Analog" newline bitfld.long 0x00 27. " [23/22] ,Loop Back Pair Type Select Bits 23/22" "Digital,Analog" bitfld.long 0x00 26. " [21/20] ,Loop Back Pair Type Select Bits 21/20" "Digital,Analog" newline bitfld.long 0x00 25. " [19/18] ,Loop Back Pair Type Select Bits 19/18" "Digital,Analog" bitfld.long 0x00 24. " [17/16] ,Loop Back Pair Type Select Bits 17/16" "Digital,Analog" newline bitfld.long 0x00 23. " [15/14] ,Loop Back Pair Type Select Bits 15/14" "Digital,Analog" bitfld.long 0x00 22. " [13/12] ,Loop Back Pair Type Select Bits 13/12" "Digital,Analog" newline bitfld.long 0x00 21. " [11/10] ,Loop Back Pair Type Select Bits 11/10" "Digital,Analog" bitfld.long 0x00 20. " [9/8] ,Loop Back Pair Type Select Bits 9/8" "Digital,Analog" newline bitfld.long 0x00 19. " [7/6] ,Loop Back Pair Type Select Bits 7/6" "Digital,Analog" bitfld.long 0x00 18. " [5/4] ,Loop Back Pair Type Select Bits 5/4" "Digital,Analog" newline bitfld.long 0x00 17. " [3/2] ,Loop Back Pair Type Select Bits 3/2" "Digital,Analog" bitfld.long 0x00 16. " [1/0] ,Loop Back Pair Type Select Bits 1/0" "Digital,Analog" newline bitfld.long 0x00 15. " LBPSEL31/30] ,Loop Back Pair Select Bits 31/30" "Not selected,Selected" bitfld.long 0x00 14. " [29/28] ,Loop Back Pair Select Bits 29/28" "Not selected,Selected" newline bitfld.long 0x00 13. " [27/26] ,Loop Back Pair Select Bits 27/26" "Not selected,Selected" bitfld.long 0x00 12. " [25/24] ,Loop Back Pair Select Bits 25/24" "Not selected,Selected" newline bitfld.long 0x00 11. " [23/22] ,Loop Back Pair Select Bits 23/22" "Not selected,Selected" bitfld.long 0x00 10. " [21/20] ,Loop Back Pair Select Bits 21/20" "Not selected,Selected" newline bitfld.long 0x00 9. " [19/18] ,Loop Back Pair Select Bits 19/18" "Not selected,Selected" bitfld.long 0x00 8. " [17/16] ,Loop Back Pair Select Bits 17/16" "Not selected,Selected" newline bitfld.long 0x00 7. " [15/14] ,Loop Back Pair Select Bits 15/14" "Not selected,Selected" bitfld.long 0x00 6. " [13/12] ,Loop Back Pair Select Bits 13/12" "Not selected,Selected" newline bitfld.long 0x00 5. " [11/10] ,Loop Back Pair Select Bits 11/10" "Not selected,Selected" bitfld.long 0x00 4. " [9/8] ,Loop Back Pair Select Bits 9/8" "Not selected,Selected" newline bitfld.long 0x00 3. " [7/6] ,Loop Back Pair Select Bits 7/6" "Not selected,Selected" bitfld.long 0x00 2. " [5/4] ,Loop Back Pair Select Bits 5/4" "Not selected,Selected" newline bitfld.long 0x00 1. " [3/2] ,Loop Back Pair Select Bits 3/2" "Not selected,Selected" bitfld.long 0x00 0. " [1/0] ,Loop Back Pair Select Bits 1/0" "Not selected,Selected" else hgroup.long 0x8C++0x3 hide.long 0x0 "LBPSEL,Loop Back Pair Select Register" endif else if ((per.l(ad:0xFFF7B800+0x90)&0xF0000)==0xA0000) group.long 0x8C++0x3 line.long 0x0 "LBPSEL,Loop Back Pair Select Register" bitfld.long 0x00 31. " LBPTYPE[15] ,Loop Back Pair Type Select Bit[15]" "Digital,Analog" bitfld.long 0x00 30. " [14] ,Loop Back Pair Type Select Bit[14]" "Digital,Analog" newline bitfld.long 0x00 29. " [13] ,Loop Back Pair Type Select Bit[13]" "Digital,Analog" bitfld.long 0x00 28. " [12] ,Loop Back Pair Type Select Bit[12]" "Digital,Analog" newline bitfld.long 0x00 27. " [11] ,Loop Back Pair Type Select Bit[11]" "Digital,Analog" bitfld.long 0x00 26. " [10] ,Loop Back Pair Type Select Bit[10]" "Digital,Analog" newline bitfld.long 0x00 25. " [9] ,Loop Back Pair Type Select Bit[9]" "Digital,Analog" bitfld.long 0x00 24. " [8] ,Loop Back Pair Type Select Bit[8]" "Digital,Analog" newline bitfld.long 0x00 23. " [7] ,Loop Back Pair Type Select Bit[7]" "Digital,Analog" bitfld.long 0x00 22. " [6] ,Loop Back Pair Type Select Bit[6]" "Digital,Analog" newline bitfld.long 0x00 21. " [5] ,Loop Back Pair Type Select Bit[5]" "Digital,Analog" bitfld.long 0x00 20. " [4] ,Loop Back Pair Type Select Bit[4]" "Digital,Analog" newline bitfld.long 0x00 19. " [3] ,Loop Back Pair Type Select Bit[3]" "Digital,Analog" bitfld.long 0x00 18. " [2] ,Loop Back Pair Type Select Bit[2]" "Digital,Analog" newline bitfld.long 0x00 17. " [1] ,Loop Back Pair Type Select Bit[1]" "Digital,Analog" bitfld.long 0x00 16. " [0] ,Loop Back Pair Type Select Bit[0]" "Digital,Analog" newline bitfld.long 0x00 15. " LBPSEL[15] ,Loop Back Pair Select Bit[15]" "Not selected,Selected" bitfld.long 0x00 14. " [14] ,Loop Back Pair Select Bit[14]" "Not selected,Selected" newline bitfld.long 0x00 13. " [13] ,Loop Back Pair Select Bit[13]" "Not selected,Selected" bitfld.long 0x00 12. " [12] ,Loop Back Pair Select Bit[12]" "Not selected,Selected" newline bitfld.long 0x00 11. " [11] ,Loop Back Pair Select Bit[11]" "Not selected,Selected" bitfld.long 0x00 10. " [10] ,Loop Back Pair Select Bit[10]" "Not selected,Selected" newline bitfld.long 0x00 9. " [9] ,Loop Back Pair Select Bit[9]" "Not selected,Selected" bitfld.long 0x00 8. " [8] ,Loop Back Pair Select Bit[8]" "Not selected,Selected" newline bitfld.long 0x00 7. " [7] ,Loop Back Pair Select Bit[7]" "Not selected,Selected" bitfld.long 0x00 6. " [6] ,Loop Back Pair Select Bit[6]" "Not selected,Selected" newline bitfld.long 0x00 5. " [5] ,Loop Back Pair Select Bit[5]" "Not selected,Selected" bitfld.long 0x00 4. " [4] ,Loop Back Pair Select Bit[4]" "Not selected,Selected" newline bitfld.long 0x00 3. " [3] ,Loop Back Pair Select Bit[3]" "Not selected,Selected" bitfld.long 0x00 2. " [2] ,Loop Back Pair Select Bit[2]" "Not selected,Selected" newline bitfld.long 0x00 1. " [1] ,Loop Back Pair Select Bit[1]" "Not selected,Selected" bitfld.long 0x00 0. " [0] ,Loop Back Pair Select Bit[0]" "Not selected,Selected" else hgroup.long 0x8C++0x3 hide.long 0x0 "LBPSEL,Loop Back Pair Select Register" endif endif group.long 0x90++0x07 line.long 0x00 "LBPDIR,Loop Back Pair Direction Register" bitfld.long 0x00 16.--19. " IODFTENA ,Module IODFT Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" bitfld.long 0x00 15. " LBPDIR[15] ,Loop Back Pair Direction Bit[15]" "Input,Output" bitfld.long 0x00 14. " [14] ,Loop Back Pair Direction Bit[14]" "Input,Output" newline bitfld.long 0x00 13. " [13] ,Loop Back Pair Direction Bit[13]" "Input,Output" bitfld.long 0x00 12. " [12] ,Loop Back Pair Direction Bit[12]" "Input,Output" bitfld.long 0x00 11. " [11] ,Loop Back Pair Direction Bit[11]" "Input,Output" newline bitfld.long 0x00 10. " [10] ,Loop Back Pair Direction Bit[10]" "Input,Output" bitfld.long 0x00 9. " [9] ,Loop Back Pair Direction Bit[9]" "Input,Output" bitfld.long 0x00 8. " [8] ,Loop Back Pair Direction Bit[8]" "Input,Output" newline bitfld.long 0x00 7. " [7] ,Loop Back Pair Direction Bit[7]" "Input,Output" bitfld.long 0x00 6. " [6] ,Loop Back Pair Direction Bit[6]" "Input,Output" bitfld.long 0x00 5. " [5] ,Loop Back Pair Direction Bit[5]" "Input,Output" newline bitfld.long 0x00 4. " [4] ,Loop Back Pair Direction Bit[4]" "Input,Output" bitfld.long 0x00 3. " [3] ,Loop Back Pair Direction Bit[3]" "Input,Output" bitfld.long 0x00 2. " [2] ,Loop Back Pair Direction Bit[2]" "Input,Output" newline bitfld.long 0x00 1. " [1] ,Loop Back Pair Direction Bit[1]" "Input,Output" bitfld.long 0x00 0. " [0] ,Loop Back Pair Direction Bit[0]" "Input,Output" line.long 0x04 "PINDIS,Pin Disable Register" bitfld.long 0x04 31. " HETPINDIS[31] ,NHET Pin Disable Bit[31]" "No,Yes" bitfld.long 0x04 30. " [30] ,NHET Pin Disable Bit[30]" "No,Yes" bitfld.long 0x04 29. " [29] ,NHET Pin Disable Bit[29]" "No,Yes" newline bitfld.long 0x04 28. " [28] ,NHET Pin Disable Bit[28]" "No,Yes" bitfld.long 0x04 27. " [27] ,NHET Pin Disable Bit[27]" "No,Yes" bitfld.long 0x04 26. " [26] ,NHET Pin Disable Bit[26]" "No,Yes" newline bitfld.long 0x04 25. " [25] ,NHET Pin Disable Bit[25]" "No,Yes" bitfld.long 0x04 24. " [24] ,NHET Pin Disable Bit[24]" "No,Yes" bitfld.long 0x04 23. " [23] ,NHET Pin Disable Bit[23]" "No,Yes" newline bitfld.long 0x04 22. " [22] ,NHET Pin Disable Bit[22]" "No,Yes" bitfld.long 0x04 21. " [21] ,NHET Pin Disable Bit[21]" "No,Yes" bitfld.long 0x04 20. " [20] ,NHET Pin Disable Bit[20]" "No,Yes" newline bitfld.long 0x04 19. " [19] ,NHET Pin Disable Bit[19]" "No,Yes" bitfld.long 0x04 18. " [18] ,NHET Pin Disable Bit[18]" "No,Yes" bitfld.long 0x04 17. " [17] ,NHET Pin Disable Bit[17]" "No,Yes" newline bitfld.long 0x04 16. " [16] ,NHET Pin Disable Bit[16]" "No,Yes" bitfld.long 0x04 15. " [15] ,NHET Pin Disable Bit[15]" "No,Yes" bitfld.long 0x04 14. " [14] ,NHET Pin Disable Bit[14]" "No,Yes" newline bitfld.long 0x04 13. " [13] ,NHET Pin Disable Bit[13]" "No,Yes" bitfld.long 0x04 12. " [12] ,NHET Pin Disable Bit[12]" "No,Yes" bitfld.long 0x04 11. " [11] ,NHET Pin Disable Bit[11]" "No,Yes" newline bitfld.long 0x04 10. " [10] ,NHET Pin Disable Bit[10]" "No,Yes" bitfld.long 0x04 9. " [9] ,NHET Pin Disable Bit[9]" "No,Yes" bitfld.long 0x04 8. " [8] ,NHET Pin Disable Bit[8]" "No,Yes" newline bitfld.long 0x04 7. " [7] ,NHET Pin Disable Bit[7]" "No,Yes" bitfld.long 0x04 6. " [6] ,NHET Pin Disable Bit[6]" "No,Yes" bitfld.long 0x04 5. " [5] ,NHET Pin Disable Bit[5]" "No,Yes" newline bitfld.long 0x04 4. " [4] ,NHET Pin Disable Bit[4]" "No,Yes" bitfld.long 0x04 3. " [3] ,NHET Pin Disable Bit[3]" "No,Yes" bitfld.long 0x04 2. " [2] ,NHET Pin Disable Bit[2]" "No,Yes" newline bitfld.long 0x04 1. " [1] ,NHET Pin Disable Bit[1]" "No,Yes" bitfld.long 0x04 0. " [0] ,NHET Pin Disable Bit[0]" "No,Yes" sif cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*") width 16. group.long 0x9C++0x13 "HWAG Registers" line.long 0x00 "HWAPINSEL,HWAG Pin Select Register" bitfld.long 0x00 0.--4. " PINSEL ,HWAG pin select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "HWAGCR0,HWAG Control Register 0" bitfld.long 0x04 0. " RESET ,HWAG module reset" "Reset,No reset" line.long 0x08 "HWAGCR1,HWAG Control Register 1" bitfld.long 0x08 0. " PPWN ,HWAG module power down" "Powered up,Powered down" line.long 0x0C "HWAGCR2,HWAG Control Register 2" bitfld.long 0x0C 24. " ARST ,Angle reset" "No reset,Reset" bitfld.long 0x0C 17. " TED ,Tooth edge" "Falling,Rising" bitfld.long 0x0C 16. " CRI ,Criteria enable" "Disabled,Enabled" newline bitfld.long 0x0C 8. " FIL ,Input filter enable" "Disabled,Enabled" bitfld.long 0x0C 0. " STRT ,Put the HWAG into run time start bit" "Stopped,Started" line.long 0x10 "HWAENA_SET/CLR,HWAG Interrupt Enable Set/Clear Register" setclrfld.long 0x10 7. 0x10 7. 0x14 7. " INTENA[7] ,Enable interrupt [7]" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x14 6. " [6] ,Enable interrupt [6]" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x14 5. " [5] ,Enable interrupt [5]" "Disabled,Enabled" newline setclrfld.long 0x10 4. 0x10 4. 0x14 4. " [4] ,Enable interrupt [4]" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x14 3. " [3] ,Enable interrupt [3]" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x14 2. " [2] ,Enable interrupt [2]" "Disabled,Enabled" newline setclrfld.long 0x10 1. 0x10 1. 0x14 1. " [1] ,Enable interrupt [1]" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x14 0. " [0] ,Enable interrupt [0]" "Disabled,Enabled" group.long 0xB0++0x03 line.long 0x00 "HWALVL_SET/CLR,HWAG Interrupt Priority Set Register" setclrfld.long 0x00 7. 0x00 7. 0x04 7. " LVLSET[7] ,Set interrupt [7] priority level" "Low,High" setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Set interrupt [6] priority level" "Low,High" setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Set interrupt [5] priority level" "Low,High" newline setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Set interrupt [4] priority level" "Low,High" setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Set interrupt [3] priority level" "Low,High" setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Set interrupt [2] priority level" "Low,High" newline setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Set interrupt [1] priority level" "Low,High" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Set interrupt [0] priority level" "Low,High" group.long 0xB8++0x27 line.long 0x00 "HWAFLG,HWAG Interrupt Flags Register" eventfld.long 0x00 7. " INTFLG[7] ,Interrupt 7 flag" "No effect,Pending" eventfld.long 0x00 6. " [6] ,Interrupt 6 flag" "No effect,Pending" eventfld.long 0x00 5. " [5] ,Interrupt 5 flag" "No effect,Pending" newline eventfld.long 0x00 4. " [4] ,Interrupt 4 flag" "No effect,Pending" eventfld.long 0x00 3. " [3] ,Interrupt 3 flag" "No effect,Pending" eventfld.long 0x00 2. " [2] ,Interrupt 2 flag" "No effect,Pending" newline eventfld.long 0x00 1. " [1] ,Interrupt 1 flag" "No effect,Pending" eventfld.long 0x00 0. " [0] ,Interrupt 0 flag" "No effect,Pending" line.long 0x04 "HWAOFF0,HWAG Interrupt Offset Register 0" hexmask.long.byte 0x04 0.--7. 0x01 " OFFSET1 ,High-priority interrupt offset" line.long 0x08 "HWAOFF1,HWAG Interrupt Offset Register 1" hexmask.long.byte 0x08 0.--7. 0x01 " OFFSET2 ,Low-priority interrupt offset" line.long 0x0C "HWAACNT,HWAG ACNT Register, HWAG Angle Value" hexmask.long.tbyte 0x0C 0.--23. 1. " ACNT ,Angle value" line.long 0x10 "HWAPCNT1,HWAG PCNT (n-1) Register, HWAG Previous Tooth Period" hexmask.long.tbyte 0x10 0.--23. 1. " PCNT(N-1) ,Period (n-1) value" line.long 0x14 "HWAPCNT,HWAG PCNT (n) Register, HWAG Current Tooth Period" hexmask.long.tbyte 0x14 0.--23. 1. " PCNT(N) ,Period (n) value" line.long 0x18 "HWASTWD,HWAG Step Register" bitfld.long 0x18 0.--3. " STWD ,Step width (ticks per period)" "4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536,131072" line.long 0x1C "HWATHNB,HWAG Teeth Number Register" hexmask.long.byte 0x1C 0.--7. 1. " THNB ,Teeth number" line.long 0x20 "HWATHVL,HHWAG Current Teeth Number Register" hexmask.long.byte 0x20 0.--7. 1. " THVL ,Teeth value" line.long 0x24 "HWAFIL,HWAG Filter Register" hexmask.long.word 0x24 0.--9. 1. " FIL1 ,Filter value 1" group.long 0xE8++0x07 line.long 0x00 "HWAFIL2,HWAG Filter Register 2, HWAG Tick Counter Compare Value During Singularity Tooth" hexmask.long.word 0x00 0.--11. 1. " FIL2 ,Filter value 2" line.long 0x04 "HWAANGI,HWAG Angle Increment Register" hexmask.long.word 0x04 0.--9. 1. " ANGI ,Angle increment value" elif (cpu()==("TMS570LS2126")||cpu()==("TMS570LS2127")||cpu()==("TMS570LS2136")||cpu()==("TMS570LS2137")||cpu()==("TMS570LS2125-PGE")||cpu()==("TMS570LS2125-ZWT")||cpu()==("TMS570LS2135-PGE")||cpu()==("TMS570LS2135-ZWT")||cpu()==("TMS570LS2124-PGE")||cpu()==("TMS570LS2124-ZWT")||cpu()==("TMS570LS2134-PGE")||cpu()==("TMS570LS2134-ZWT")||cpu()==("TMS570LS3134-PGE")||cpu()==("TMS570LS3134-ZWT")||cpu()==("TMS570LS3135-PGE")||cpu()==("TMS570LS3135-ZWT")||cpu()==("TMS570LS3136")||cpu()==("TMS570LS3137-PGE")||cpu()==("TMS570LS3137-ZWT")||cpu()==("TMS570LS30336")||cpuis("RM48L950*")) group.long 0xA0++0x43 line.long 0x00 "HWAGCR0,HWAG Control Register 0" line.long 0x04 "HWAGCR1,HWAG Control Register 1" line.long 0x08 "HWAGCR2,HWAG Control Register 2" line.long 0x0C "HWAENASET,HWAG Interrupt Enable Set Register" line.long 0x10 "HWAENACLR,HWAG Interrupt Enable Clear Register" line.long 0x14 "HWALVLSET,HWAG Interrupt Priority Set Register" line.long 0x18 "HWALVLCLR,HWAG Interrupt Priority Clear Register" line.long 0x1C "HWAFLG,HWAG Interrupt Flags Register" line.long 0x20 "HWAOFF0,HWAG Interrupt Offset Register 1, HWAG Low Priority Interrupt Offset" line.long 0x24 "HWAOFF1,HWAG Interrupt Offset Register 2, HWAG High Priority Interrupt Offset" line.long 0x28 "HWAACNT,HWAG ACNT Register, HWAG Angle Value" line.long 0x2C "HWAPCNT1,HWAG PCNT (n-1) Register, HWAG Previous Tooth Period" line.long 0x30 "HWAPCNT,HWAG PCNT (n) Register, HWAG Current Tooth Period" line.long 0x34 "HWASTWD,HWAG Step Register" line.long 0x38 "HWATHNB,HWAG Teeth Number Register" line.long 0x3C "HWATHVL,HHWAG Current Teeth Number Register" line.long 0x40 "HWAFIL,HWAG Filter Register, HWAG Tick Counter Compare Value" group.long 0xE8++0x07 line.long 0x00 "HWAFIL2,HWAG Filter Register 2, HWAG Tick Counter Compare Value During Singularity Tooth" line.long 0x04 "HWAANGI,HWAG Angle Increment Register" endif sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*") endian.le endif width 0x0B tree.end sif (cpu()!="RM42L432") tree "NHET2" base ad:0xFFF7B900 sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*") endian.be endif width 15. group.long 0x00++0x07 line.long 0x0 "GCR,Global Control Register" bitfld.long 0x00 24. " HET_PIN_ENA ,NHET Pin Enable" "Disabled,Enabled" bitfld.long 0x00 21.--22. " MP ,Master Priority" "Lower,Higher,Round robin,?..." bitfld.long 0x00 18. " PPF ,Protect Program Fields" "Low,High" newline bitfld.long 0x00 17. " IS ,Ignore Suspend" "Not ignored,Ignored" bitfld.long 0x00 16. " CMS ,Clk_master/Slave" "Slave,Master" bitfld.long 0x00 0. " TO ,Turn On/Off" "Off,On" line.long 0x04 "PFR,Prescaler Factor Register" bitfld.long 0x04 8.--10. " LRPFC ,Loop Resolution Pre-scale Factor Code" "1,2,4,8,16,32,64,128" bitfld.long 0x04 0.--5. " HRPFC ,HR Prescale Factor Code" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" rgroup.long 0x08++0x0B line.long 0x0 "ADDR,Current Address Register" hexmask.long.word 0x00 0.--8. 1. " HETADDR ,N2HET Current Address" line.long 0x04 "OFF1,Offset Level 1 Register" hexmask.long.byte 0x04 0.--5. 1. " Offset1 ,Indexes the Currently Pending High-Priority Interrupt" line.long 0x08 "OFF2,Offset Level 2 Register" hexmask.long.byte 0x08 0.--5. 1. " Offset2 ,Indexes the Currently Pending High-Priority Interrupt" newline group.long 0x14++0x03 line.long 0x00 "INTENA_SETCLR,Interrupt Enable Set/Clear Register" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " HETINTENAS_setclr[31] ,Interrupt Enable Set Pin 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x04 30. " [30] ,Interrupt enable set/clear bit 30" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x04 29. " [29] ,Interrupt enable set/clear bit 29" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x04 28. " [28] ,Interrupt enable set/clear bit 28" "Disabled,Enabled" newline setclrfld.long 0x00 27. 0x00 27. 0x04 27. " [27] ,Interrupt enable set/clear bit 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x04 26. " [26] ,Interrupt enable set/clear bit 26" "Disabled,Enabled" setclrfld.long 0x00 25. 0x00 25. 0x04 25. " [25] ,Interrupt enable set/clear bit 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x04 24. " [24] ,Interrupt enable set/clear bit 24" "Disabled,Enabled" newline setclrfld.long 0x00 23. 0x00 23. 0x04 23. " [23] ,Interrupt enable set/clear bit 23" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x04 22. " [22] ,Interrupt enable set/clear bit 22" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x04 21. " [21] ,Interrupt enable set/clear bit 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x04 20. " [20] ,Interrupt enable set/clear bit 20" "Disabled,Enabled" newline setclrfld.long 0x00 19. 0x00 19. 0x04 19. " [19] ,Interrupt enable set/clear bit 19" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x04 18. " [18] ,Interrupt enable set/clear bit 18" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x04 17. " [17] ,Interrupt enable set/clear bit 17" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x04 16. " [16] ,Interrupt enable set/clear bit 16" "Disabled,Enabled" newline setclrfld.long 0x00 15. 0x00 15. 0x04 15. " [15] ,Interrupt enable set/clear bit 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x04 14. " [14] ,Interrupt enable set/clear bit 14" "Disabled,Enabled" setclrfld.long 0x00 13. 0x00 13. 0x04 13. " [13] ,Interrupt enable set/clear bit 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x04 12. " [12] ,Interrupt enable set/clear bit 12" "Disabled,Enabled" newline setclrfld.long 0x00 11. 0x00 11. 0x04 11. " [11] ,Interrupt enable set/clear bit 11" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x04 10. " [10] ,Interrupt enable set/clear bit 10" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x04 9. " [9] ,Interrupt enable set/clear bit 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x04 8. " [8] ,Interrupt enable set/clear bit 8" "Disabled,Enabled" newline setclrfld.long 0x00 7. 0x00 7. 0x04 7. " [7] ,Interrupt enable set/clear bit 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Interrupt enable set/clear bit 6" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Interrupt enable set/clear bit 5" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Interrupt enable set/clear bit 4" "Disabled,Enabled" newline setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Interrupt enable set/clear bit 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Interrupt enable set/clear bit 2" "Disabled,Enabled" setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Interrupt enable set/clear bit 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Interrupt enable set/clear bit 0" "Disabled,Enabled" newline group.long 0x1C++0x0F line.long 0x00 "EXC1,Exception Control Register 1" bitfld.long 0x00 24. " APCNT_OVRFL_ENA ,APCNT Overflow Enable" "Disabled,Enabled" bitfld.long 0x00 16. " APCNT_UNDRFL_ENA ,APCNT Underflow Enable" "Disabled,Enabled" newline bitfld.long 0x00 8. " PRGM_OVRFL_ENA ,Program Overflow Enable" "Disabled,Enabled" bitfld.long 0x00 2. " APCNT_OVRFL_ENA_PRY ,APCNT_Ovrfl_Ena Priority" "Level 2,Level 1" newline bitfld.long 0x00 1. " APCNT_UNDRFL_ENA_PRY ,APCNT_Undrfl_Ena Priority" "Level 2,Level 1" bitfld.long 0x00 0. " PRGM_OVRFL_ENA_PRY ,Prgm_Ovrfl_Ena Priority" "Level 2,Level 1" line.long 0x04 "EXC2,Exception Control Register 2" eventfld.long 0x04 8. " DEBUG_STATUS_FLG ,Debug_Status Flag" "No NHET,NHET" eventfld.long 0x04 2. " APCNT_OVRFL_FLG ,APCNT Overflow Flag" "Not occurred,Occurred" newline eventfld.long 0x04 1. " APCNT_UNDRFL_FLG ,APCNT Underflow Flag" "Not occurred,Occurred" eventfld.long 0x04 0. " PRGM_OVERFL_FLG ,Program Overflow Flag" "Not occurred,Occurred" newline line.long 0x08 "PRY,Interrupt Priority Register" bitfld.long 0x08 31. " HETPRY[31] ,HET Priority Level Bit[31]" "Level 2,Level 1" bitfld.long 0x08 30. " [30] ,HET Priority Level Bit[30]" "Level 2,Level 1" bitfld.long 0x08 29. " [29] ,HET Priority Level Bit[29]" "Level 2,Level 1" newline bitfld.long 0x08 28. " [28] ,HET Priority Level Bit[28]" "Level 2,Level 1" bitfld.long 0x08 27. " [27] ,HET Priority Level Bit[27]" "Level 2,Level 1" bitfld.long 0x08 26. " [26] ,HET Priority Level Bit[26]" "Level 2,Level 1" newline bitfld.long 0x08 25. " [25] ,HET Priority Level Bit[25]" "Level 2,Level 1" bitfld.long 0x08 24. " [24] ,HET Priority Level Bit[24]" "Level 2,Level 1" bitfld.long 0x08 23. " [23] ,HET Priority Level Bit[23]" "Level 2,Level 1" newline bitfld.long 0x08 22. " [22] ,HET Priority Level Bit[22]" "Level 2,Level 1" bitfld.long 0x08 21. " [21] ,HET Priority Level Bit[21]" "Level 2,Level 1" bitfld.long 0x08 20. " [20] ,HET Priority Level Bit[20]" "Level 2,Level 1" newline bitfld.long 0x08 19. " [19] ,HET Priority Level Bit[19]" "Level 2,Level 1" bitfld.long 0x08 18. " [18] ,HET Priority Level Bit[18]" "Level 2,Level 1" bitfld.long 0x08 17. " [17] ,HET Priority Level Bit[17]" "Level 2,Level 1" newline bitfld.long 0x08 16. " [16] ,HET Priority Level Bit[16]" "Level 2,Level 1" bitfld.long 0x08 15. " [15] ,HET Priority Level Bit[15]" "Level 2,Level 1" bitfld.long 0x08 14. " [14] ,HET Priority Level Bit[14]" "Level 2,Level 1" newline bitfld.long 0x08 13. " [13] ,HET Priority Level Bit[13]" "Level 2,Level 1" bitfld.long 0x08 12. " [12] ,HET Priority Level Bit[12]" "Level 2,Level 1" bitfld.long 0x08 11. " [11] ,HET Priority Level Bit[11]" "Level 2,Level 1" newline bitfld.long 0x08 10. " [10] ,HET Priority Level Bit[10]" "Level 2,Level 1" bitfld.long 0x08 9. " [9] ,HET Priority Level Bit[9]" "Level 2,Level 1" bitfld.long 0x08 8. " [8] ,HET Priority Level Bit[8]" "Level 2,Level 1" newline bitfld.long 0x08 7. " [7] ,HET Priority Level Bit[7]" "Level 2,Level 1" bitfld.long 0x08 6. " [6] ,HET Priority Level Bit[6]" "Level 2,Level 1" bitfld.long 0x08 5. " [5] ,HET Priority Level Bit[5]" "Level 2,Level 1" newline bitfld.long 0x08 4. " [4] ,HET Priority Level Bit[4]" "Level 2,Level 1" bitfld.long 0x08 3. " [3] ,HET Priority Level Bit[3]" "Level 2,Level 1" bitfld.long 0x08 2. " [2] ,HET Priority Level Bit[2]" "Level 2,Level 1" newline bitfld.long 0x08 1. " [1] ,HET Priority Level Bit[1]" "Level 2,Level 1" bitfld.long 0x08 0. " HETPRY[0] ,HET Priority Level Bit[0]" "Level 2,Level 1" line.long 0x0C "FLG,Interrupt Flag Register" eventfld.long 0x0C 31. " HETFLAG[31] ,Interrupt Flag Register Bit[31]" "No interrupt,Interrupt" eventfld.long 0x0C 30. " [30] ,Interrupt Flag Register Bit[30]" "No interrupt,Interrupt" newline eventfld.long 0x0C 29. " [29] ,Interrupt Flag Register Bit[29]" "No interrupt,Interrupt" eventfld.long 0x0C 28. " [28] ,Interrupt Flag Register Bit[28]" "No interrupt,Interrupt" newline eventfld.long 0x0C 27. " [27] ,Interrupt Flag Register Bit[27]" "No interrupt,Interrupt" eventfld.long 0x0C 26. " [26] ,Interrupt Flag Register Bit[26]" "No interrupt,Interrupt" newline eventfld.long 0x0C 25. " [25] ,Interrupt Flag Register Bit[25]" "No interrupt,Interrupt" eventfld.long 0x0C 24. " [24] ,Interrupt Flag Register Bit[24]" "No interrupt,Interrupt" newline eventfld.long 0x0C 23. " [23] ,Interrupt Flag Register Bit[23]" "No interrupt,Interrupt" eventfld.long 0x0C 22. " [22] ,Interrupt Flag Register Bit[22]" "No interrupt,Interrupt" newline eventfld.long 0x0C 21. " [21] ,Interrupt Flag Register Bit[21]" "No interrupt,Interrupt" eventfld.long 0x0C 20. " [20] ,Interrupt Flag Register Bit[20]" "No interrupt,Interrupt" newline eventfld.long 0x0C 19. " [19] ,Interrupt Flag Register Bit[19]" "No interrupt,Interrupt" eventfld.long 0x0C 18. " [18] ,Interrupt Flag Register Bit[18]" "No interrupt,Interrupt" newline eventfld.long 0x0C 17. " [17] ,Interrupt Flag Register Bit[17]" "No interrupt,Interrupt" eventfld.long 0x0C 16. " [16] ,Interrupt Flag Register Bit[16]" "No interrupt,Interrupt" newline eventfld.long 0x0C 15. " [15] ,Interrupt Flag Register Bit[15]" "No interrupt,Interrupt" eventfld.long 0x0C 14. " [14] ,Interrupt Flag Register Bit[14]" "No interrupt,Interrupt" newline eventfld.long 0x0C 13. " [13] ,Interrupt Flag Register Bit[13]" "No interrupt,Interrupt" eventfld.long 0x0C 12. " [12] ,Interrupt Flag Register Bit[12]" "No interrupt,Interrupt" newline eventfld.long 0x0C 11. " [11] ,Interrupt Flag Register Bit[11]" "No interrupt,Interrupt" eventfld.long 0x0C 10. " [10] ,Interrupt Flag Register Bit[10]" "No interrupt,Interrupt" newline eventfld.long 0x0C 9. " [9] ,Interrupt Flag Register Bit[9]" "No interrupt,Interrupt" eventfld.long 0x0C 8. " [8] ,Interrupt Flag Register Bit[8]" "No interrupt,Interrupt" newline eventfld.long 0x0C 7. " [7] ,Interrupt Flag Register Bit[7]" "No interrupt,Interrupt" eventfld.long 0x0C 6. " [6] ,Interrupt Flag Register Bit[6]" "No interrupt,Interrupt" newline eventfld.long 0x0C 5. " [5] ,Interrupt Flag Register Bit[5]" "No interrupt,Interrupt" eventfld.long 0x0C 4. " [4] ,Interrupt Flag Register Bit[4]" "No interrupt,Interrupt" newline eventfld.long 0x0C 3. " [3] ,Interrupt Flag Register Bit[3]" "No interrupt,Interrupt" eventfld.long 0x0C 2. " [2] ,Interrupt Flag Register Bit[2]" "No interrupt,Interrupt" newline eventfld.long 0x0C 1. " [1] ,Interrupt Flag Register Bit[1]" "No interrupt,Interrupt" eventfld.long 0x0C 0. " [0] ,Interrupt Flag Register Bit[0]" "No interrupt,Interrupt" sif (CPU()==("TMS570LS2124-PGE")||CPU()==("TMS570LS2124-ZWT")||CPU()==("TMS570LS2134-PGE")||CPU()==("TMS570LS2134-ZWT")||CPU()==("TMS570LS3134-PGE")||CPU()==("TMS570LS3134-ZWT")||CPU()==("TMS570LS3135-PGE")||CPU()==("TMS570LS3135-ZWT")||CPU()==("TMS570LS3136")||CPU()==("TMS570LS3137-PGE")||CPU()==("TMS570LS3137-ZWT")||CPU()==("TMS570LS30336")||CPU()==("TMS570LS2126")||CPU()==("TMS570LS2127")||CPU()==("TMS570LS2136")||CPU()==("TMS570LS2137")||CPU()==("TMS570LS2125-PGE")||CPU()==("TMS570LS2125-ZWT")||CPU()==("TMS570LS2135-PGE")||CPU()==("TMS570LS2135-ZWT")||CPU()==("RM48L950")||cpu()=="RM48L952-PGE"||cpu()=="RM48L952-ZWT"||CPU()=="RM48L950-PGE"||CPU()=="RM48L950-ZWT"||CPU()=="RM48L940-ZWT"||CPU()=="RM48L940-PGE"||CPU()=="RM48L930-ZWT"||CPU()=="RM48L930-PGE"||CPU()=="RM48L750-ZWT"||CPU()=="RM48L750-PGE"||CPU()=="RM48L740-ZWT"||CPU()=="RM48L740-PGE"||CPU()=="RM48L730-ZWT"||CPU()=="RM48L730-PGE"||CPU()=="RM48L550-PGE"||CPU()=="RM48L540-ZWT"||CPU()=="RM48L540-PGE"||CPU()=="RM48L530-ZWT"||CPU()=="RM48L530-PGE"||CPU()=="RM46L852-PGE"||CPU()=="RM46L852-ZWT"||CPU()=="RM46L850-PGE"||CPU()=="RM46L850-ZWT"||CPU()=="RM46L840-ZWT"||CPU()=="RM46L840-PGE"||CPU()=="RM46L830-ZWT"||CPU()=="RM46L830-PGE"||CPU()=="RM46L450-ZWT"||CPU()=="RM46L450-PGE"||CPU()=="RM46L440-ZWT"||CPU()=="RM46L440-PGE"||CPU()=="RM46L430-ZWT"||CPU()=="RM46L430-PGE"||CPU()=="RM42L432"||CPU()=="TMS570LC4357"||CPU()==("TMS570LS0332")||CPU()==("TMS570LS0432")||CPUIS("TMS570LS1114*")||CPUIS("TMS570LS1115*")||CPUIS("TMS570LS1224*")||CPUIS("TMS570LS1225*")||CPUIS("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")) group.long 0x2C++0x3 line.long 0x00 "HETAND,And Share Control Register" bitfld.long 0x00 15. " AND_SHARE[31/30] ,And share 31/30" "Not shared,Shared" bitfld.long 0x00 14. " [29/28] ,And share 29/28" "Not shared,Shared" newline bitfld.long 0x00 13. " [27/26] ,And share 27/26" "Not shared,Shared" bitfld.long 0x00 12. " [25/24] ,And share 25/24" "Not shared,Shared" newline bitfld.long 0x00 11. " [23/22] ,And share 23/22" "Not shared,Shared" bitfld.long 0x00 10. " [21/20] ,And share 21/20" "Not shared,Shared" newline bitfld.long 0x00 9. " [19/18] ,And share 19/18" "Not shared,Shared" bitfld.long 0x00 8. " [17/16] ,And share 17/16" "Not shared,Shared" newline bitfld.long 0x00 7. " [15/14] ,And share 15/14" "Not shared,Shared" bitfld.long 0x00 6. " [13/12] ,And share 13/12" "Not shared,Shared" newline bitfld.long 0x00 5. " [11/10] ,And share 11/10" "Not shared,Shared" bitfld.long 0x00 4. " [9/8] ,And share 9/8" "Not shared,Shared" newline bitfld.long 0x00 3. " [7/6] ,And share 7/6" "Not shared,Shared" bitfld.long 0x00 2. " [5/4] ,And share 5/4" "Not shared,Shared" newline bitfld.long 0x00 1. " [3/2] ,And share 3/2" "Not shared,Shared" bitfld.long 0x00 0. " [1/0] ,And share 1/0" "Not shared,Shared" endif group.long 0x34++0x07 line.long 0x0 "HRSH,HR Share Control Register" bitfld.long 0x00 15. " HR_SHARE[31/30] ,HR Share 31/30" "Not shared,Shared" bitfld.long 0x00 14. " [29/28] ,HR Share 29/28" "Not shared,Shared" newline bitfld.long 0x00 13. " [27/26] ,HR Share 27/26" "Not shared,Shared" bitfld.long 0x00 12. " [25/24] ,HR Share 25/24" "Not shared,Shared" newline bitfld.long 0x00 11. " [23/22] ,HR Share 23/22" "Not shared,Shared" bitfld.long 0x00 10. " [21/20] ,HR Share 21/20" "Not shared,Shared" newline bitfld.long 0x00 9. " [19/18] ,HR Share 19/18" "Not shared,Shared" bitfld.long 0x00 8. " [17/16] ,HR Share 17/16" "Not shared,Shared" newline bitfld.long 0x00 7. " [15/14] ,HR Share 15/14" "Not shared,Shared" bitfld.long 0x00 6. " [13/12] ,HR Share 13/12" "Not shared,Shared" newline bitfld.long 0x00 5. " [11/10] ,HR Share 11/10" "Not shared,Shared" bitfld.long 0x00 4. " [9/8] ,HR Share 9/8" "Not shared,Shared" newline bitfld.long 0x00 3. " [7/6] ,HR Share 7/6" "Not shared,Shared" bitfld.long 0x00 2. " [5/4] ,HR Share 5/4" "Not shared,Shared" newline bitfld.long 0x00 1. " [3/2] ,HR Share 3/2" "Not shared,Shared" bitfld.long 0x00 0. " [1/0] ,HR Share 1/0" "Not shared,Shared" line.long 0x04 "XOR,HR XOR Control Register" bitfld.long 0x04 15. " HR_XOR_SHARE[31/30] ,HR XOR-Share 31/30" "Not XOR-shared,XOR-shared" bitfld.long 0x04 14. " [29/28] ,HR XOR-Share 29/28" "Not XOR-shared,XOR-shared" newline bitfld.long 0x04 13. " [27/26] ,HR XOR-Share 27/26" "Not XOR-shared,XOR-shared" bitfld.long 0x04 12. " [25/24] ,HR XOR-Share 25/24" "Not XOR-shared,XOR-shared" newline bitfld.long 0x04 11. " [23/22] ,HR XOR-Share 23/22" "Not XOR-shared,XOR-shared" bitfld.long 0x04 10. " [21/20] ,HR XOR-Share 21/20" "Not XOR-shared,XOR-shared" newline bitfld.long 0x04 9. " [19/18] ,HR XOR-Share 19/18" "Not XOR-shared,XOR-shared" bitfld.long 0x04 8. " [17/16] ,HR XOR-Share 17/16" "Not XOR-shared,XOR-shared" newline bitfld.long 0x04 7. " [15/14] ,HR XOR-Share 15/14" "Not XOR-shared,XOR-shared" bitfld.long 0x04 6. " [13/12] ,HR XOR-Share 13/12" "Not XOR-shared,XOR-shared" newline bitfld.long 0x04 5. " [11/10] ,HR XOR-Share 11/10" "Not XOR-shared,XOR-shared" bitfld.long 0x04 4. " [9/8] ,HR XOR-Share 9/8" "Not XOR-shared,XOR-shared" newline bitfld.long 0x04 3. " [7/6] ,HR XOR-Share 7/6" "Not XOR-shared,XOR-shared" bitfld.long 0x04 2. " [5/4] ,HR XOR-Share 5/4" "Not XOR-shared,XOR-shared" newline bitfld.long 0x04 1. " [3/2] ,HR XOR-Share 3/2" "Not XOR-shared,XOR-shared" bitfld.long 0x04 0. " [1/0] ,HR XOR-Share 1/0" "Not XOR-shared,XOR-shared" group.long 0x3C++0x03 line.long 0x00 "REQEN_SETCLR,Request Enable Set/Clear Register" setclrfld.long 0x00 7. 0x00 7. 0x04 7. " REQENA_SET/CLR[7] ,Request enable set/clear bit [7]" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Request enable set/clear bit [6]" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Request enable set/clear bit [5]" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Request enable set/clear bit [4]" "Disabled,Enabled" newline setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Request enable set/clear bit [3]" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Request enable set/clear bit [2]" "Disabled,Enabled" setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Request enable set/clear bit [1]" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Request enable set/clear bit [0]" "Disabled,Enabled" sif (cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")&&!cpuis("TMS570LS0232")) group.long 0x44++0x3 line.long 0x00 "REQDS,Request Destination Select Register" bitfld.long 0x00 23. " TDBS[7] ,HTU/DMA or Both Select Bit[7]" "HTU,Both" bitfld.long 0x00 22. " [6] ,HTU/DMA or Both Select Bit[6]" "HTU,Both" bitfld.long 0x00 21. " [5] ,HTU/DMA or Both Select Bit[5]" "HTU,Both" bitfld.long 0x00 20. " [4] ,HTU/DMA or Both Select Bit[4]" "HTU,Both" newline bitfld.long 0x00 19. " [3] ,HTU/DMA or Both Select Bit[3]" "HTU,Both" bitfld.long 0x00 18. " [2] ,HTU/DMA or Both Select Bit[2]" "HTU,Both" bitfld.long 0x00 17. " [1] ,HTU/DMA or Both Select Bit[1]" "HTU,Both" bitfld.long 0x00 16. " [0] ,HTU/DMA or Both Select Bit[0]" "HTU,Both" newline bitfld.long 0x00 7. " TDS[7] ,HTU or DMA Select Bit[7]" "HTU,DMA" bitfld.long 0x00 6. " TDS[6] ,HTU or DMA Select Bit[6]" "HTU,DMA" bitfld.long 0x00 5. " TDS[5] ,HTU or DMA Select Bit[5]" "HTU,DMA" bitfld.long 0x00 4. " TDS[4] ,HTU or DMA Select Bit[4]" "HTU,DMA" newline bitfld.long 0x00 3. " TDS[3] ,HTU or DMA Select Bit[3]" "HTU,DMA" bitfld.long 0x00 2. " TDS[2] ,HTU or DMA Select Bit[2]" "HTU,DMA" bitfld.long 0x00 1. " TDS[1] ,HTU or DMA Select Bit[1]" "HTU,DMA" bitfld.long 0x00 0. " TDS[0] ,HTU or DMA Select Bit[0]" "HTU,DMA" endif group.long 0x4C++0x3 line.long 0x00 "DIR,Direction Register" bitfld.long 0x00 31. " HET_DIR[31] ,Input/Output Direction Pin 31" "Input,Output" bitfld.long 0x00 30. " [30] ,Input/Output Direction Pin 30" "Input,Output" bitfld.long 0x00 29. " [29] ,Input/Output Direction Pin 29" "Input,Output" newline bitfld.long 0x00 28. " [28] ,Input/Output Direction Pin 28" "Input,Output" bitfld.long 0x00 27. " [27] ,Input/Output Direction Pin 27" "Input,Output" bitfld.long 0x00 26. " [26] ,Input/Output Direction Pin 26" "Input,Output" newline bitfld.long 0x00 25. " [25] ,Input/Output Direction Pin 25" "Input,Output" bitfld.long 0x00 24. " [24] ,Input/Output Direction Pin 24" "Input,Output" bitfld.long 0x00 23. " [23] ,Input/Output Direction Pin 23" "Input,Output" newline bitfld.long 0x00 22. " [22] ,Input/Output Direction Pin 22" "Input,Output" bitfld.long 0x00 21. " [21] ,Input/Output Direction Pin 21" "Input,Output" bitfld.long 0x00 20. " [20] ,Input/Output Direction Pin 20" "Input,Output" newline bitfld.long 0x00 19. " [19] ,Input/Output Direction Pin 19" "Input,Output" bitfld.long 0x00 18. " [18] ,Input/Output Direction Pin 18" "Input,Output" bitfld.long 0x00 17. " [17] ,Input/Output Direction Pin 17" "Input,Output" newline bitfld.long 0x00 16. " [16] ,Input/Output Direction Pin 16" "Input,Output" bitfld.long 0x00 15. " [15] ,Input/Output Direction Pin 15" "Input,Output" bitfld.long 0x00 14. " [14] ,Input/Output Direction Pin 14" "Input,Output" newline bitfld.long 0x00 13. " [13] ,Input/Output Direction Pin 13" "Input,Output" bitfld.long 0x00 12. " [12] ,Input/Output Direction Pin 12" "Input,Output" bitfld.long 0x00 11. " [11] ,Input/Output Direction Pin 11" "Input,Output" newline bitfld.long 0x00 10. " [10] ,Input/Output Direction Pin 10" "Input,Output" bitfld.long 0x00 9. " [9] ,Input/Output Direction Pin 9" "Input,Output" bitfld.long 0x00 8. " [8] ,Input/Output Direction Pin 8" "Input,Output" newline bitfld.long 0x00 7. " [7] ,Input/Output Direction Pin 7" "Input,Output" bitfld.long 0x00 6. " [6] ,Input/Output Direction Pin 6" "Input,Output" bitfld.long 0x00 5. " [5] ,Input/Output Direction Pin 5" "Input,Output" newline bitfld.long 0x00 4. " [4] ,Input/Output Direction Pin 4" "Input,Output" bitfld.long 0x00 3. " [3] ,Input/Output Direction Pin 3" "Input,Output" bitfld.long 0x00 2. " [2] ,Input/Output Direction Pin 2" "Input,Output" newline bitfld.long 0x00 1. " [1] ,Input/Output Direction Pin 1" "Input,Output" bitfld.long 0x00 0. " [0] ,Input/Output Direction Pin 0" "Input,Output" rgroup.long 0x50++0x3 line.long 0x00 "DIN,Input Data Register" bitfld.long 0x00 31. " HETDIN[31] ,NHET Data Input Register Pin 31" "Low,High" bitfld.long 0x00 30. " [30] ,NHET Data Input Register Pin 30" "Low,High" bitfld.long 0x00 29. " [29] ,NHET Data Input Register Pin 29" "Low,High" bitfld.long 0x00 28. " [28] ,NHET Data Input Register Pin 28" "Low,High" newline bitfld.long 0x00 27. " [27] ,NHET Data Input Register Pin 27" "Low,High" bitfld.long 0x00 26. " [26] ,NHET Data Input Register Pin 26" "Low,High" bitfld.long 0x00 25. " [25] ,NHET Data Input Register Pin 25" "Low,High" bitfld.long 0x00 24. " [24] ,NHET Data Input Register Pin 24" "Low,High" newline bitfld.long 0x00 23. " [23] ,NHET Data Input Register Pin 23" "Low,High" bitfld.long 0x00 22. " [22] ,NHET Data Input Register Pin 22" "Low,High" bitfld.long 0x00 21. " [21] ,NHET Data Input Register Pin 21" "Low,High" bitfld.long 0x00 20. " [20] ,NHET Data Input Register Pin 20" "Low,High" newline bitfld.long 0x00 19. " [19] ,NHET Data Input Register Pin 19" "Low,High" bitfld.long 0x00 18. " [18] ,NHET Data Input Register Pin 18" "Low,High" bitfld.long 0x00 17. " [17] ,NHET Data Input Register Pin 17" "Low,High" bitfld.long 0x00 16. " [16] ,NHET Data Input Register Pin 16" "Low,High" newline bitfld.long 0x00 15. " [15] ,NHET Data Input Register Pin 15" "Low,High" bitfld.long 0x00 14. " [14] ,NHET Data Input Register Pin 14" "Low,High" bitfld.long 0x00 13. " [13] ,NHET Data Input Register Pin 13" "Low,High" bitfld.long 0x00 12. " [12] ,NHET Data Input Register Pin 12" "Low,High" newline bitfld.long 0x00 11. " [11] ,NHET Data Input Register Pin 11" "Low,High" bitfld.long 0x00 10. " [10] ,NHET Data Input Register Pin 10" "Low,High" bitfld.long 0x00 9. " [9] ,NHET Data Input Register Pin 9" "Low,High" bitfld.long 0x00 8. " [8] ,NHET Data Input Register Pin 8" "Low,High" newline bitfld.long 0x00 7. " [7] ,NHET Data Input Register Pin 7" "Low,High" bitfld.long 0x00 6. " [6] ,NHET Data Input Register Pin 6" "Low,High" bitfld.long 0x00 5. " [5] ,NHET Data Input Register Pin 5" "Low,High" bitfld.long 0x00 4. " [4] ,NHET Data Input Register Pin 4" "Low,High" newline bitfld.long 0x00 3. " [3] ,NHET Data Input Register Pin 3" "Low,High" bitfld.long 0x00 2. " [2] ,NHET Data Input Register Pin 2" "Low,High" bitfld.long 0x00 1. " [1] ,NHET Data Input Register Pin 1" "Low,High" bitfld.long 0x00 0. " [0] ,NHET Data Input Register Pin 0" "Low,High" group.long 0x54++0x3 line.long 0x00 "DOUT_SET/CLR,Output Data Set/Clear Register" setclrfld.long 0x00 31. 0x04 31. 0x08 31. " HETDOUT[31] ,NHET Data Output Register Bit[31]" "Low,High" setclrfld.long 0x00 30. 0x04 30. 0x08 30. " [30] ,NHET Data Output Register Bit[30]" "Low,High" newline setclrfld.long 0x00 29. 0x04 29. 0x08 29. " [29] ,NHET Data Output Register Bit[29]" "Low,High" setclrfld.long 0x00 28. 0x04 28. 0x08 28. " [28] ,NHET Data Output Register Bit[28]" "Low,High" newline setclrfld.long 0x00 27. 0x04 27. 0x08 27. " [27] ,NHET Data Output Register Bit[27]" "Low,High" setclrfld.long 0x00 26. 0x04 26. 0x08 26. " [26] ,NHET Data Output Register Bit[26]" "Low,High" newline setclrfld.long 0x00 25. 0x04 25. 0x08 25. " [25] ,NHET Data Output Register Bit[25]" "Low,High" setclrfld.long 0x00 24. 0x04 24. 0x08 24. " [24] ,NHET Data Output Register Bit[24]" "Low,High" newline setclrfld.long 0x00 23. 0x04 23. 0x08 23. " [23] ,NHET Data Output Register Bit[23]" "Low,High" setclrfld.long 0x00 22. 0x04 22. 0x08 22. " [22] ,NHET Data Output Register Bit[22]" "Low,High" newline setclrfld.long 0x00 21. 0x04 21. 0x08 21. " [21] ,NHET Data Output Register Bit[21]" "Low,High" setclrfld.long 0x00 20. 0x04 20. 0x08 20. " [20] ,NHET Data Output Register Bit[20]" "Low,High" newline setclrfld.long 0x00 19. 0x04 19. 0x08 19. " [19] ,NHET Data Output Register Bit[19]" "Low,High" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " [18] ,NHET Data Output Register Bit[18]" "Low,High" newline setclrfld.long 0x00 17. 0x04 17. 0x08 17. " [17] ,NHET Data Output Register Bit[17]" "Low,High" setclrfld.long 0x00 16. 0x04 16. 0x08 16. " [16] ,NHET Data Output Register Bit[16]" "Low,High" newline setclrfld.long 0x00 15. 0x04 15. 0x08 15. " [15] ,NHET Data Output Register Bit[15]" "Low,High" setclrfld.long 0x00 14. 0x04 14. 0x08 14. " [14] ,NHET Data Output Register Bit[14]" "Low,High" newline setclrfld.long 0x00 13. 0x04 13. 0x08 13. " [13] ,NHET Data Output Register Bit[13]" "Low,High" setclrfld.long 0x00 12. 0x04 12. 0x08 12. " [12] ,NHET Data Output Register Bit[12]" "Low,High" newline setclrfld.long 0x00 11. 0x04 11. 0x08 11. " [11] ,NHET Data Output Register Bit[11]" "Low,High" setclrfld.long 0x00 10. 0x04 10. 0x08 10. " [10] ,NHET Data Output Register Bit[10]" "Low,High" newline setclrfld.long 0x00 9. 0x04 9. 0x08 9. " [9] ,NHET Data Output Register Bit[9]" "Low,High" setclrfld.long 0x00 8. 0x04 8. 0x08 8. " [8] ,NHET Data Output Register Bit[8]" "Low,High" newline setclrfld.long 0x00 7. 0x04 7. 0x08 7. " [7] ,NHET Data Output Register Bit[7]" "Low,High" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " [6] ,NHET Data Output Register Bit[6]" "Low,High" newline setclrfld.long 0x00 5. 0x04 5. 0x08 5. " [5] ,NHET Data Output Register Bit[5]" "Low,High" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " [4] ,NHET Data Output Register Bit[4]" "Low,High" newline setclrfld.long 0x00 3. 0x04 3. 0x08 3. " [3] ,NHET Data Output Register Bit[3]" "Low,High" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " [2] ,NHET Data Output Register Bit[2]" "Low,High" newline setclrfld.long 0x00 1. 0x04 1. 0x08 1. " [1] ,NHET Data Output Register Bit[1]" "Low,High" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " [0] ,NHET Data Output Register Bit[0]" "Low,High" group.long 0x60++0x0B line.long 0x00 "PDR,Open Drain Register" bitfld.long 0x00 31. " HETPDR[31] ,NHET Open Drain Bit[31]" "Disabled,Enabled" bitfld.long 0x00 30. " [30] ,NHET Open Drain Bit[30]" "Disabled,Enabled" bitfld.long 0x00 29. " [29] ,NHET Open Drain Bit[29]" "Disabled,Enabled" newline bitfld.long 0x00 28. " [28] ,NHET Open Drain Bit[28]" "Disabled,Enabled" bitfld.long 0x00 27. " [27] ,NHET Open Drain Bit[27]" "Disabled,Enabled" bitfld.long 0x00 26. " [26] ,NHET Open Drain Bit[26]" "Disabled,Enabled" newline bitfld.long 0x00 25. " [25] ,NHET Open Drain Bit[25]" "Disabled,Enabled" bitfld.long 0x00 24. " [24] ,NHET Open Drain Bit[24]" "Disabled,Enabled" bitfld.long 0x00 23. " [23] ,NHET Open Drain Bit[23]" "Disabled,Enabled" newline bitfld.long 0x00 22. " [22] ,NHET Open Drain Bit[22]" "Disabled,Enabled" bitfld.long 0x00 21. " [21] ,NHET Open Drain Bit[21]" "Disabled,Enabled" bitfld.long 0x00 20. " [20] ,NHET Open Drain Bit[20]" "Disabled,Enabled" newline bitfld.long 0x00 19. " [19] ,NHET Open Drain Bit[19]" "Disabled,Enabled" bitfld.long 0x00 18. " [18] ,NHET Open Drain Bit[18]" "Disabled,Enabled" bitfld.long 0x00 17. " [17] ,NHET Open Drain Bit[17]" "Disabled,Enabled" newline bitfld.long 0x00 16. " [16] ,NHET Open Drain Bit[16]" "Disabled,Enabled" bitfld.long 0x00 15. " [15] ,NHET Open Drain Bit[15]" "Disabled,Enabled" bitfld.long 0x00 14. " [14] ,NHET Open Drain Bit[14]" "Disabled,Enabled" newline bitfld.long 0x00 13. " [13] ,NHET Open Drain Bit[13]" "Disabled,Enabled" bitfld.long 0x00 12. " [12] ,NHET Open Drain Bit[12]" "Disabled,Enabled" bitfld.long 0x00 11. " [11] ,NHET Open Drain Bit[11]" "Disabled,Enabled" newline bitfld.long 0x00 10. " [10] ,NHET Open Drain Bit[10]" "Disabled,Enabled" bitfld.long 0x00 9. " [9] ,NHET Open Drain Bit[9]" "Disabled,Enabled" bitfld.long 0x00 8. " [8] ,NHET Open Drain Bit[8]" "Disabled,Enabled" newline bitfld.long 0x00 7. " [7] ,NHET Open Drain Bit[7]" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,NHET Open Drain Bit[6]" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,NHET Open Drain Bit[5]" "Disabled,Enabled" newline bitfld.long 0x00 4. " [4] ,NHET Open Drain Bit[4]" "Disabled,Enabled" bitfld.long 0x00 3. " [3] ,NHET Open Drain Bit[3]" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,NHET Open Drain Bit[2]" "Disabled,Enabled" newline bitfld.long 0x00 1. " [1] ,NHET Open Drain Bit[1]" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,NHET Open Drain Bit[0]" "Disabled,Enabled" line.long 0x04 "PULDIS,Pull Disable Register" bitfld.long 0x04 31. " HETPULDIS[31] ,NHET Pull Disable Bit[31]" "No,Yes" bitfld.long 0x04 30. " [30] ,NHET Pull Disable Bit[30]" "No,Yes" bitfld.long 0x04 29. " [29] ,NHET Pull Disable Bit[29]" "No,Yes" newline bitfld.long 0x04 28. " [28] ,NHET Pull Disable Bit[28]" "No,Yes" bitfld.long 0x04 27. " [27] ,NHET Pull Disable Bit[27]" "No,Yes" bitfld.long 0x04 26. " [26] ,NHET Pull Disable Bit[26]" "No,Yes" newline bitfld.long 0x04 25. " [25] ,NHET Pull Disable Bit[25]" "No,Yes" bitfld.long 0x04 24. " [24] ,NHET Pull Disable Bit[24]" "No,Yes" bitfld.long 0x04 23. " [23] ,NHET Pull Disable Bit[23]" "No,Yes" newline bitfld.long 0x04 22. " [22] ,NHET Pull Disable Bit[22]" "No,Yes" bitfld.long 0x04 21. " [21] ,NHET Pull Disable Bit[21]" "No,Yes" bitfld.long 0x04 20. " [20] ,NHET Pull Disable Bit[20]" "No,Yes" newline bitfld.long 0x04 19. " [19] ,NHET Pull Disable Bit[19]" "No,Yes" bitfld.long 0x04 18. " [18] ,NHET Pull Disable Bit[18]" "No,Yes" bitfld.long 0x04 17. " [17] ,NHET Pull Disable Bit[17]" "No,Yes" newline bitfld.long 0x04 16. " [16] ,NHET Pull Disable Bit[16]" "No,Yes" bitfld.long 0x04 15. " [15] ,NHET Pull Disable Bit[15]" "No,Yes" bitfld.long 0x04 14. " [14] ,NHET Pull Disable Bit[14]" "No,Yes" newline bitfld.long 0x04 13. " [13] ,NHET Pull Disable Bit[13]" "No,Yes" bitfld.long 0x04 12. " [12] ,NHET Pull Disable Bit[12]" "No,Yes" bitfld.long 0x04 11. " [11] ,NHET Pull Disable Bit[11]" "No,Yes" newline bitfld.long 0x04 10. " [10] ,NHET Pull Disable Bit[10]" "No,Yes" bitfld.long 0x04 9. " [9] ,NHET Pull Disable Bit[9]" "No,Yes" bitfld.long 0x04 8. " [8] ,NHET Pull Disable Bit[8]" "No,Yes" newline bitfld.long 0x04 7. " [7] ,NHET Pull Disable Bit[7]" "No,Yes" bitfld.long 0x04 6. " [6] ,NHET Pull Disable Bit[6]" "No,Yes" bitfld.long 0x04 5. " [5] ,NHET Pull Disable Bit[5]" "No,Yes" newline bitfld.long 0x04 4. " [4] ,NHET Pull Disable Bit[4]" "No,Yes" bitfld.long 0x04 3. " [3] ,NHET Pull Disable Bit[3]" "No,Yes" bitfld.long 0x04 2. " [2] ,NHET Pull Disable Bit[2]" "No,Yes" newline bitfld.long 0x04 1. " [1] ,NHET Pull Disable Bit[1]" "No,Yes" bitfld.long 0x04 0. " [0] ,NHET Pull Disable Bit[0]" "No,Yes" line.long 0x08 "PSL,Pull Select Register" bitfld.long 0x08 31. " HETPSL[31] ,NHET Pull Select Bit[31]" "Pull down,Pull up" bitfld.long 0x08 30. " [30] ,NHET Pull Select Bit[30]" "Pull down,Pull up" bitfld.long 0x08 29. " [29] ,NHET Pull Select Bit[29]" "Pull down,Pull up" newline bitfld.long 0x08 28. " [28] ,NHET Pull Select Bit[28]" "Pull down,Pull up" bitfld.long 0x08 27. " [27] ,NHET Pull Select Bit[27]" "Pull down,Pull up" bitfld.long 0x08 26. " [26] ,NHET Pull Select Bit[26]" "Pull down,Pull up" newline bitfld.long 0x08 25. " [25] ,NHET Pull Select Bit[25]" "Pull down,Pull up" bitfld.long 0x08 24. " [24] ,NHET Pull Select Bit[24]" "Pull down,Pull up" bitfld.long 0x08 23. " [23] ,NHET Pull Select Bit[23]" "Pull down,Pull up" newline bitfld.long 0x08 22. " [22] ,NHET Pull Select Bit[22]" "Pull down,Pull up" bitfld.long 0x08 21. " [21] ,NHET Pull Select Bit[21]" "Pull down,Pull up" bitfld.long 0x08 20. " [20] ,NHET Pull Select Bit[20]" "Pull down,Pull up" newline bitfld.long 0x08 19. " [19] ,NHET Pull Select Bit[19]" "Pull down,Pull up" bitfld.long 0x08 18. " [18] ,NHET Pull Select Bit[18]" "Pull down,Pull up" bitfld.long 0x08 17. " [17] ,NHET Pull Select Bit[17]" "Pull down,Pull up" newline bitfld.long 0x08 16. " [16] ,NHET Pull Select Bit[16]" "Pull down,Pull up" bitfld.long 0x08 15. " [15] ,NHET Pull Select Bit[15]" "Pull down,Pull up" bitfld.long 0x08 14. " [14] ,NHET Pull Select Bit[14]" "Pull down,Pull up" newline bitfld.long 0x08 13. " [13] ,NHET Pull Select Bit[13]" "Pull down,Pull up" bitfld.long 0x08 12. " [12] ,NHET Pull Select Bit[12]" "Pull down,Pull up" bitfld.long 0x08 11. " [11] ,NHET Pull Select Bit[11]" "Pull down,Pull up" newline bitfld.long 0x08 10. " [10] ,NHET Pull Select Bit[10]" "Pull down,Pull up" bitfld.long 0x08 9. " [9] ,NHET Pull Select Bit[9]" "Pull down,Pull up" bitfld.long 0x08 8. " [8] ,NHET Pull Select Bit[8]" "Pull down,Pull up" newline bitfld.long 0x08 7. " [7] ,NHET Pull Select Bit[7]" "Pull down,Pull up" bitfld.long 0x08 6. " [6] ,NHET Pull Select Bit[6]" "Pull down,Pull up" bitfld.long 0x08 5. " [5] ,NHET Pull Select Bit[5]" "Pull down,Pull up" newline bitfld.long 0x08 4. " [4] ,NHET Pull Select Bit[4]" "Pull down,Pull up" bitfld.long 0x08 3. " [3] ,NHET Pull Select Bit[3]" "Pull down,Pull up" bitfld.long 0x08 2. " [2] ,NHET Pull Select Bit[2]" "Pull down,Pull up" newline bitfld.long 0x08 1. " [1] ,NHET Pull Select Bit[1]" "Pull down,Pull up" bitfld.long 0x08 0. " [0] ,NHET Pull Select Bit[0]" "Pull down,Pull up" group.long 0x74++0x3 line.long 0x0 "PCR,Parity Control Register" bitfld.long 0x00 8. " TEST ,TEST" "Not mapped,Mapped" bitfld.long 0x00 0.--3. " PARITY_ENA ,Enable / Disable Parity Checking" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" rgroup.long 0x78++0x3 line.long 0x0 "PAR,Parity Address Register" hexmask.long.word 0x00 2.--12. 0x4 " PAOFF ,Parity Error Address Offset" group.long 0x7C++0x0B line.long 0x0 "PPR,Parity Pin Register" bitfld.long 0x00 31. " HETPPR[31] ,NHET Parity Pin Select Bit[31]" "Low,High" bitfld.long 0x00 30. " [30] ,NHET Parity Pin Select Bit[30]" "Low,High" bitfld.long 0x00 29. " [29] ,NHET Parity Pin Select Bit[29]" "Low,High" bitfld.long 0x00 28. " [28] ,NHET Parity Pin Select Bit[28]" "Low,High" newline bitfld.long 0x00 27. " [27] ,NHET Parity Pin Select Bit[27]" "Low,High" bitfld.long 0x00 26. " [26] ,NHET Parity Pin Select Bit[26]" "Low,High" bitfld.long 0x00 25. " [25] ,NHET Parity Pin Select Bit[25]" "Low,High" bitfld.long 0x00 24. " [24] ,NHET Parity Pin Select Bit[24]" "Low,High" newline bitfld.long 0x00 23. " [23] ,NHET Parity Pin Select Bit[23]" "Low,High" bitfld.long 0x00 22. " [22] ,NHET Parity Pin Select Bit[22]" "Low,High" bitfld.long 0x00 21. " [21] ,NHET Parity Pin Select Bit[21]" "Low,High" bitfld.long 0x00 20. " [20] ,NHET Parity Pin Select Bit[20]" "Low,High" newline bitfld.long 0x00 19. " [19] ,NHET Parity Pin Select Bit[19]" "Low,High" bitfld.long 0x00 18. " [18] ,NHET Parity Pin Select Bit[18]" "Low,High" bitfld.long 0x00 17. " [17] ,NHET Parity Pin Select Bit[17]" "Low,High" bitfld.long 0x00 16. " [16] ,NHET Parity Pin Select Bit[16]" "Low,High" newline bitfld.long 0x00 15. " [15] ,NHET Parity Pin Select Bit[15]" "Low,High" bitfld.long 0x00 14. " [14] ,NHET Parity Pin Select Bit[14]" "Low,High" bitfld.long 0x00 13. " [13] ,NHET Parity Pin Select Bit[13]" "Low,High" bitfld.long 0x00 12. " [12] ,NHET Parity Pin Select Bit[12]" "Low,High" newline bitfld.long 0x00 11. " [11] ,NHET Parity Pin Select Bit[11]" "Low,High" bitfld.long 0x00 10. " [10] ,NHET Parity Pin Select Bit[10]" "Low,High" bitfld.long 0x00 9. " [9] ,NHET Parity Pin Select Bit[9]" "Low,High" bitfld.long 0x00 8. " [8] ,NHET Parity Pin Select Bit[8]" "Low,High" newline bitfld.long 0x00 7. " [7] ,NHET Parity Pin Select Bit[7]" "Low,High" bitfld.long 0x00 6. " [6] ,NHET Parity Pin Select Bit[6]" "Low,High" bitfld.long 0x00 5. " [5] ,NHET Parity Pin Select Bit[5]" "Low,High" bitfld.long 0x00 4. " [4] ,NHET Parity Pin Select Bit[4]" "Low,High" newline bitfld.long 0x00 3. " [3] ,NHET Parity Pin Select Bit[3]" "Low,High" bitfld.long 0x00 2. " [2] ,NHET Parity Pin Select Bit[2]" "Low,High" bitfld.long 0x00 1. " [1] ,NHET Parity Pin Select Bit[1]" "Low,High" bitfld.long 0x00 0. " [0] ,NHET Parity Pin Select Bit[0]" "Low,High" line.long 0x04 "SFPRLD,Suppresion Filter Preload Register" bitfld.long 0x04 16.--17. " CCDIV ,Counter Clock Divider" "VCLK2,VCLK2/2,VCLK2/3,VCLK2/4" hexmask.long.word 0x04 0.--9. 1. " CPRLD ,Counter Preload Value" line.long 0x08 "SFENA,Suppresion Filter Enable Register" bitfld.long 0x08 31. " HETSFENA[31] ,Suppression Filter Enable Bit[31]" "Disabled,Enabled" bitfld.long 0x08 30. " [30] ,Suppression Filter Enable Bit[30]" "Disabled,Enabled" bitfld.long 0x08 29. " [29] ,Suppression Filter Enable Bit[29]" "Disabled,Enabled" newline bitfld.long 0x08 28. " [28] ,Suppression Filter Enable Bit[28]" "Disabled,Enabled" bitfld.long 0x08 27. " [27] ,Suppression Filter Enable Bit[27]" "Disabled,Enabled" bitfld.long 0x08 26. " [26] ,Suppression Filter Enable Bit[26]" "Disabled,Enabled" newline bitfld.long 0x08 25. " [25] ,Suppression Filter Enable Bit[25]" "Disabled,Enabled" bitfld.long 0x08 24. " [24] ,Suppression Filter Enable Bit[24]" "Disabled,Enabled" bitfld.long 0x08 23. " [23] ,Suppression Filter Enable Bit[23]" "Disabled,Enabled" newline bitfld.long 0x08 22. " [22] ,Suppression Filter Enable Bit[22]" "Disabled,Enabled" bitfld.long 0x08 21. " [21] ,Suppression Filter Enable Bit[21]" "Disabled,Enabled" bitfld.long 0x08 20. " [20] ,Suppression Filter Enable Bit[20]" "Disabled,Enabled" newline bitfld.long 0x08 19. " [19] ,Suppression Filter Enable Bit[19]" "Disabled,Enabled" bitfld.long 0x08 18. " [18] ,Suppression Filter Enable Bit[18]" "Disabled,Enabled" bitfld.long 0x08 17. " [17] ,Suppression Filter Enable Bit[17]" "Disabled,Enabled" newline bitfld.long 0x08 16. " [16] ,Suppression Filter Enable Bit[16]" "Disabled,Enabled" bitfld.long 0x08 15. " [15] ,Suppression Filter Enable Bit[15]" "Disabled,Enabled" bitfld.long 0x08 14. " [14] ,Suppression Filter Enable Bit[14]" "Disabled,Enabled" newline bitfld.long 0x08 13. " [13] ,Suppression Filter Enable Bit[13]" "Disabled,Enabled" bitfld.long 0x08 12. " [12] ,Suppression Filter Enable Bit[12]" "Disabled,Enabled" bitfld.long 0x08 11. " [11] ,Suppression Filter Enable Bit[11]" "Disabled,Enabled" newline bitfld.long 0x08 10. " [10] ,Suppression Filter Enable Bit[10]" "Disabled,Enabled" bitfld.long 0x08 9. " [9] ,Suppression Filter Enable Bit[9]" "Disabled,Enabled" bitfld.long 0x08 8. " [8] ,Suppression Filter Enable Bit[8]" "Disabled,Enabled" newline bitfld.long 0x08 7. " [7] ,Suppression Filter Enable Bit[7]" "Disabled,Enabled" bitfld.long 0x08 6. " [6] ,Suppression Filter Enable Bit[6]" "Disabled,Enabled" bitfld.long 0x08 5. " [5] ,Suppression Filter Enable Bit[5]" "Disabled,Enabled" newline bitfld.long 0x08 4. " [4] ,Suppression Filter Enable Bit[4]" "Disabled,Enabled" bitfld.long 0x08 3. " [3] ,Suppression Filter Enable Bit[3]" "Disabled,Enabled" bitfld.long 0x08 2. " [2] ,Suppression Filter Enable Bit[2]" "Disabled,Enabled" newline bitfld.long 0x08 1. " [1] ,Suppression Filter Enable Bit[1]" "Disabled,Enabled" bitfld.long 0x08 0. " [0] ,Suppression Filter Enable Bit[0]" "Disabled,Enabled" sif (cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&cpu()!="TMS570LC4357"&&cpu()!="RM48L550-ZWT"&&cpu()!="RM42L432"&&!cpuis("TMS570LS0232")&&!cpuis("TMS570LS0714*")&&!cpuis("TMS570LS0914*")) if ((per.l(ad:0xFFF7B900+0x90)&0xF00)==0xA00) group.long 0x8C++0x3 line.long 0x0 "LBPSEL,Loop Back Pair Select Register" bitfld.long 0x00 31. " LBPTYPE[15] ,Loop Back Pair Type Select Bit[15]" "Digital,Analog" bitfld.long 0x00 30. " [14] ,Loop Back Pair Type Select Bit[14]" "Digital,Analog" newline bitfld.long 0x00 29. " [13] ,Loop Back Pair Type Select Bit[13]" "Digital,Analog" bitfld.long 0x00 28. " [12] ,Loop Back Pair Type Select Bit[12]" "Digital,Analog" newline bitfld.long 0x00 27. " [11] ,Loop Back Pair Type Select Bit[11]" "Digital,Analog" bitfld.long 0x00 26. " [10] ,Loop Back Pair Type Select Bit[10]" "Digital,Analog" newline bitfld.long 0x00 25. " [9] ,Loop Back Pair Type Select Bit[9]" "Digital,Analog" bitfld.long 0x00 24. " [8] ,Loop Back Pair Type Select Bit[8]" "Digital,Analog" newline bitfld.long 0x00 23. " [7] ,Loop Back Pair Type Select Bit[7]" "Digital,Analog" bitfld.long 0x00 22. " [6] ,Loop Back Pair Type Select Bit[6]" "Digital,Analog" newline bitfld.long 0x00 21. " [5] ,Loop Back Pair Type Select Bit[5]" "Digital,Analog" bitfld.long 0x00 20. " [4] ,Loop Back Pair Type Select Bit[4]" "Digital,Analog" newline bitfld.long 0x00 19. " [3] ,Loop Back Pair Type Select Bit[3]" "Digital,Analog" bitfld.long 0x00 18. " [2] ,Loop Back Pair Type Select Bit[2]" "Digital,Analog" newline bitfld.long 0x00 17. " [1] ,Loop Back Pair Type Select Bit[1]" "Digital,Analog" bitfld.long 0x00 16. " [0] ,Loop Back Pair Type Select Bit[0]" "Digital,Analog" newline bitfld.long 0x00 15. " LBPSEL[15] ,Loop Back Pair Select Bit[15]" "Not selected,Selected" bitfld.long 0x00 14. " [14] ,Loop Back Pair Select Bit[14]" "Not selected,Selected" newline bitfld.long 0x00 13. " [13] ,Loop Back Pair Select Bit[13]" "Not selected,Selected" bitfld.long 0x00 12. " [12] ,Loop Back Pair Select Bit[12]" "Not selected,Selected" newline bitfld.long 0x00 11. " [11] ,Loop Back Pair Select Bit[11]" "Not selected,Selected" bitfld.long 0x00 10. " [10] ,Loop Back Pair Select Bit[10]" "Not selected,Selected" newline bitfld.long 0x00 9. " [9] ,Loop Back Pair Select Bit[9]" "Not selected,Selected" bitfld.long 0x00 8. " [8] ,Loop Back Pair Select Bit[8]" "Not selected,Selected" newline bitfld.long 0x00 7. " [7] ,Loop Back Pair Select Bit[7]" "Not selected,Selected" bitfld.long 0x00 6. " [6] ,Loop Back Pair Select Bit[6]" "Not selected,Selected" newline bitfld.long 0x00 5. " [5] ,Loop Back Pair Select Bit[5]" "Not selected,Selected" bitfld.long 0x00 4. " [4] ,Loop Back Pair Select Bit[4]" "Not selected,Selected" newline bitfld.long 0x00 3. " [3] ,Loop Back Pair Select Bit[3]" "Not selected,Selected" bitfld.long 0x00 2. " [2] ,Loop Back Pair Select Bit[2]" "Not selected,Selected" newline bitfld.long 0x00 1. " [1] ,Loop Back Pair Select Bit[1]" "Not selected,Selected" bitfld.long 0x00 0. " [0] ,Loop Back Pair Select Bit[0]" "Not selected,Selected" else hgroup.long 0x8C++0x3 hide.long 0x0 "LBPSEL,Loop Back Pair Select Register" endif elif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*") if ((per.l.be(ad:0xFFF7B900+0x90)&0xF0000)==0xA0000) group.long 0x8C++0x3 line.long 0x0 "LBPSEL,Loop Back Pair Select Register" bitfld.long 0x00 31. " LBPTYPE[31/30] ,Loop Back Pair Type Select Bits 31/30" "Digital,Analog" bitfld.long 0x00 30. " [29/28] ,Loop Back Pair Type Select Bits 29/28" "Digital,Analog" newline bitfld.long 0x00 29. " [27/26] ,Loop Back Pair Type Select Bits 27/26" "Digital,Analog" bitfld.long 0x00 28. " [25/24] ,Loop Back Pair Type Select Bits 25/24" "Digital,Analog" newline bitfld.long 0x00 27. " [23/22] ,Loop Back Pair Type Select Bits 23/22" "Digital,Analog" bitfld.long 0x00 26. " [21/20] ,Loop Back Pair Type Select Bits 21/20" "Digital,Analog" newline bitfld.long 0x00 25. " [19/18] ,Loop Back Pair Type Select Bits 19/18" "Digital,Analog" bitfld.long 0x00 24. " [17/16] ,Loop Back Pair Type Select Bits 17/16" "Digital,Analog" newline bitfld.long 0x00 23. " [15/14] ,Loop Back Pair Type Select Bits 15/14" "Digital,Analog" bitfld.long 0x00 22. " [13/12] ,Loop Back Pair Type Select Bits 13/12" "Digital,Analog" newline bitfld.long 0x00 21. " [11/10] ,Loop Back Pair Type Select Bits 11/10" "Digital,Analog" bitfld.long 0x00 20. " [9/8] ,Loop Back Pair Type Select Bits 9/8" "Digital,Analog" newline bitfld.long 0x00 19. " [7/6] ,Loop Back Pair Type Select Bits 7/6" "Digital,Analog" bitfld.long 0x00 18. " [5/4] ,Loop Back Pair Type Select Bits 5/4" "Digital,Analog" newline bitfld.long 0x00 17. " [3/2] ,Loop Back Pair Type Select Bits 3/2" "Digital,Analog" bitfld.long 0x00 16. " [1/0] ,Loop Back Pair Type Select Bits 1/0" "Digital,Analog" newline bitfld.long 0x00 15. " LBPSEL31/30] ,Loop Back Pair Select Bits 31/30" "Not selected,Selected" bitfld.long 0x00 14. " [29/28] ,Loop Back Pair Select Bits 29/28" "Not selected,Selected" newline bitfld.long 0x00 13. " [27/26] ,Loop Back Pair Select Bits 27/26" "Not selected,Selected" bitfld.long 0x00 12. " [25/24] ,Loop Back Pair Select Bits 25/24" "Not selected,Selected" newline bitfld.long 0x00 11. " [23/22] ,Loop Back Pair Select Bits 23/22" "Not selected,Selected" bitfld.long 0x00 10. " [21/20] ,Loop Back Pair Select Bits 21/20" "Not selected,Selected" newline bitfld.long 0x00 9. " [19/18] ,Loop Back Pair Select Bits 19/18" "Not selected,Selected" bitfld.long 0x00 8. " [17/16] ,Loop Back Pair Select Bits 17/16" "Not selected,Selected" newline bitfld.long 0x00 7. " [15/14] ,Loop Back Pair Select Bits 15/14" "Not selected,Selected" bitfld.long 0x00 6. " [13/12] ,Loop Back Pair Select Bits 13/12" "Not selected,Selected" newline bitfld.long 0x00 5. " [11/10] ,Loop Back Pair Select Bits 11/10" "Not selected,Selected" bitfld.long 0x00 4. " [9/8] ,Loop Back Pair Select Bits 9/8" "Not selected,Selected" newline bitfld.long 0x00 3. " [7/6] ,Loop Back Pair Select Bits 7/6" "Not selected,Selected" bitfld.long 0x00 2. " [5/4] ,Loop Back Pair Select Bits 5/4" "Not selected,Selected" newline bitfld.long 0x00 1. " [3/2] ,Loop Back Pair Select Bits 3/2" "Not selected,Selected" bitfld.long 0x00 0. " [1/0] ,Loop Back Pair Select Bits 1/0" "Not selected,Selected" else hgroup.long 0x8C++0x3 hide.long 0x0 "LBPSEL,Loop Back Pair Select Register" endif else if ((per.l(ad:0xFFF7B900+0x90)&0xF0000)==0xA0000) group.long 0x8C++0x3 line.long 0x0 "LBPSEL,Loop Back Pair Select Register" bitfld.long 0x00 31. " LBPTYPE[15] ,Loop Back Pair Type Select Bit[15]" "Digital,Analog" bitfld.long 0x00 30. " [14] ,Loop Back Pair Type Select Bit[14]" "Digital,Analog" newline bitfld.long 0x00 29. " [13] ,Loop Back Pair Type Select Bit[13]" "Digital,Analog" bitfld.long 0x00 28. " [12] ,Loop Back Pair Type Select Bit[12]" "Digital,Analog" newline bitfld.long 0x00 27. " [11] ,Loop Back Pair Type Select Bit[11]" "Digital,Analog" bitfld.long 0x00 26. " [10] ,Loop Back Pair Type Select Bit[10]" "Digital,Analog" newline bitfld.long 0x00 25. " [9] ,Loop Back Pair Type Select Bit[9]" "Digital,Analog" bitfld.long 0x00 24. " [8] ,Loop Back Pair Type Select Bit[8]" "Digital,Analog" newline bitfld.long 0x00 23. " [7] ,Loop Back Pair Type Select Bit[7]" "Digital,Analog" bitfld.long 0x00 22. " [6] ,Loop Back Pair Type Select Bit[6]" "Digital,Analog" newline bitfld.long 0x00 21. " [5] ,Loop Back Pair Type Select Bit[5]" "Digital,Analog" bitfld.long 0x00 20. " [4] ,Loop Back Pair Type Select Bit[4]" "Digital,Analog" newline bitfld.long 0x00 19. " [3] ,Loop Back Pair Type Select Bit[3]" "Digital,Analog" bitfld.long 0x00 18. " [2] ,Loop Back Pair Type Select Bit[2]" "Digital,Analog" newline bitfld.long 0x00 17. " [1] ,Loop Back Pair Type Select Bit[1]" "Digital,Analog" bitfld.long 0x00 16. " [0] ,Loop Back Pair Type Select Bit[0]" "Digital,Analog" newline bitfld.long 0x00 15. " LBPSEL[15] ,Loop Back Pair Select Bit[15]" "Not selected,Selected" bitfld.long 0x00 14. " [14] ,Loop Back Pair Select Bit[14]" "Not selected,Selected" newline bitfld.long 0x00 13. " [13] ,Loop Back Pair Select Bit[13]" "Not selected,Selected" bitfld.long 0x00 12. " [12] ,Loop Back Pair Select Bit[12]" "Not selected,Selected" newline bitfld.long 0x00 11. " [11] ,Loop Back Pair Select Bit[11]" "Not selected,Selected" bitfld.long 0x00 10. " [10] ,Loop Back Pair Select Bit[10]" "Not selected,Selected" newline bitfld.long 0x00 9. " [9] ,Loop Back Pair Select Bit[9]" "Not selected,Selected" bitfld.long 0x00 8. " [8] ,Loop Back Pair Select Bit[8]" "Not selected,Selected" newline bitfld.long 0x00 7. " [7] ,Loop Back Pair Select Bit[7]" "Not selected,Selected" bitfld.long 0x00 6. " [6] ,Loop Back Pair Select Bit[6]" "Not selected,Selected" newline bitfld.long 0x00 5. " [5] ,Loop Back Pair Select Bit[5]" "Not selected,Selected" bitfld.long 0x00 4. " [4] ,Loop Back Pair Select Bit[4]" "Not selected,Selected" newline bitfld.long 0x00 3. " [3] ,Loop Back Pair Select Bit[3]" "Not selected,Selected" bitfld.long 0x00 2. " [2] ,Loop Back Pair Select Bit[2]" "Not selected,Selected" newline bitfld.long 0x00 1. " [1] ,Loop Back Pair Select Bit[1]" "Not selected,Selected" bitfld.long 0x00 0. " [0] ,Loop Back Pair Select Bit[0]" "Not selected,Selected" else hgroup.long 0x8C++0x3 hide.long 0x0 "LBPSEL,Loop Back Pair Select Register" endif endif group.long 0x90++0x07 line.long 0x00 "LBPDIR,Loop Back Pair Direction Register" bitfld.long 0x00 16.--19. " IODFTENA ,Module IODFT Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" bitfld.long 0x00 15. " LBPDIR[15] ,Loop Back Pair Direction Bit[15]" "Input,Output" bitfld.long 0x00 14. " [14] ,Loop Back Pair Direction Bit[14]" "Input,Output" newline bitfld.long 0x00 13. " [13] ,Loop Back Pair Direction Bit[13]" "Input,Output" bitfld.long 0x00 12. " [12] ,Loop Back Pair Direction Bit[12]" "Input,Output" bitfld.long 0x00 11. " [11] ,Loop Back Pair Direction Bit[11]" "Input,Output" newline bitfld.long 0x00 10. " [10] ,Loop Back Pair Direction Bit[10]" "Input,Output" bitfld.long 0x00 9. " [9] ,Loop Back Pair Direction Bit[9]" "Input,Output" bitfld.long 0x00 8. " [8] ,Loop Back Pair Direction Bit[8]" "Input,Output" newline bitfld.long 0x00 7. " [7] ,Loop Back Pair Direction Bit[7]" "Input,Output" bitfld.long 0x00 6. " [6] ,Loop Back Pair Direction Bit[6]" "Input,Output" bitfld.long 0x00 5. " [5] ,Loop Back Pair Direction Bit[5]" "Input,Output" newline bitfld.long 0x00 4. " [4] ,Loop Back Pair Direction Bit[4]" "Input,Output" bitfld.long 0x00 3. " [3] ,Loop Back Pair Direction Bit[3]" "Input,Output" bitfld.long 0x00 2. " [2] ,Loop Back Pair Direction Bit[2]" "Input,Output" newline bitfld.long 0x00 1. " [1] ,Loop Back Pair Direction Bit[1]" "Input,Output" bitfld.long 0x00 0. " [0] ,Loop Back Pair Direction Bit[0]" "Input,Output" line.long 0x04 "PINDIS,Pin Disable Register" bitfld.long 0x04 31. " HETPINDIS[31] ,NHET Pin Disable Bit[31]" "No,Yes" bitfld.long 0x04 30. " [30] ,NHET Pin Disable Bit[30]" "No,Yes" bitfld.long 0x04 29. " [29] ,NHET Pin Disable Bit[29]" "No,Yes" newline bitfld.long 0x04 28. " [28] ,NHET Pin Disable Bit[28]" "No,Yes" bitfld.long 0x04 27. " [27] ,NHET Pin Disable Bit[27]" "No,Yes" bitfld.long 0x04 26. " [26] ,NHET Pin Disable Bit[26]" "No,Yes" newline bitfld.long 0x04 25. " [25] ,NHET Pin Disable Bit[25]" "No,Yes" bitfld.long 0x04 24. " [24] ,NHET Pin Disable Bit[24]" "No,Yes" bitfld.long 0x04 23. " [23] ,NHET Pin Disable Bit[23]" "No,Yes" newline bitfld.long 0x04 22. " [22] ,NHET Pin Disable Bit[22]" "No,Yes" bitfld.long 0x04 21. " [21] ,NHET Pin Disable Bit[21]" "No,Yes" bitfld.long 0x04 20. " [20] ,NHET Pin Disable Bit[20]" "No,Yes" newline bitfld.long 0x04 19. " [19] ,NHET Pin Disable Bit[19]" "No,Yes" bitfld.long 0x04 18. " [18] ,NHET Pin Disable Bit[18]" "No,Yes" bitfld.long 0x04 17. " [17] ,NHET Pin Disable Bit[17]" "No,Yes" newline bitfld.long 0x04 16. " [16] ,NHET Pin Disable Bit[16]" "No,Yes" bitfld.long 0x04 15. " [15] ,NHET Pin Disable Bit[15]" "No,Yes" bitfld.long 0x04 14. " [14] ,NHET Pin Disable Bit[14]" "No,Yes" newline bitfld.long 0x04 13. " [13] ,NHET Pin Disable Bit[13]" "No,Yes" bitfld.long 0x04 12. " [12] ,NHET Pin Disable Bit[12]" "No,Yes" bitfld.long 0x04 11. " [11] ,NHET Pin Disable Bit[11]" "No,Yes" newline bitfld.long 0x04 10. " [10] ,NHET Pin Disable Bit[10]" "No,Yes" bitfld.long 0x04 9. " [9] ,NHET Pin Disable Bit[9]" "No,Yes" bitfld.long 0x04 8. " [8] ,NHET Pin Disable Bit[8]" "No,Yes" newline bitfld.long 0x04 7. " [7] ,NHET Pin Disable Bit[7]" "No,Yes" bitfld.long 0x04 6. " [6] ,NHET Pin Disable Bit[6]" "No,Yes" bitfld.long 0x04 5. " [5] ,NHET Pin Disable Bit[5]" "No,Yes" newline bitfld.long 0x04 4. " [4] ,NHET Pin Disable Bit[4]" "No,Yes" bitfld.long 0x04 3. " [3] ,NHET Pin Disable Bit[3]" "No,Yes" bitfld.long 0x04 2. " [2] ,NHET Pin Disable Bit[2]" "No,Yes" newline bitfld.long 0x04 1. " [1] ,NHET Pin Disable Bit[1]" "No,Yes" bitfld.long 0x04 0. " [0] ,NHET Pin Disable Bit[0]" "No,Yes" sif cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*") width 16. group.long 0x9C++0x13 "HWAG Registers" line.long 0x00 "HWAPINSEL,HWAG Pin Select Register" bitfld.long 0x00 0.--4. " PINSEL ,HWAG pin select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "HWAGCR0,HWAG Control Register 0" bitfld.long 0x04 0. " RESET ,HWAG module reset" "Reset,No reset" line.long 0x08 "HWAGCR1,HWAG Control Register 1" bitfld.long 0x08 0. " PPWN ,HWAG module power down" "Powered up,Powered down" line.long 0x0C "HWAGCR2,HWAG Control Register 2" bitfld.long 0x0C 24. " ARST ,Angle reset" "No reset,Reset" bitfld.long 0x0C 17. " TED ,Tooth edge" "Falling,Rising" bitfld.long 0x0C 16. " CRI ,Criteria enable" "Disabled,Enabled" newline bitfld.long 0x0C 8. " FIL ,Input filter enable" "Disabled,Enabled" bitfld.long 0x0C 0. " STRT ,Put the HWAG into run time start bit" "Stopped,Started" line.long 0x10 "HWAENA_SET/CLR,HWAG Interrupt Enable Set/Clear Register" setclrfld.long 0x10 7. 0x10 7. 0x14 7. " INTENA[7] ,Enable interrupt [7]" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x14 6. " [6] ,Enable interrupt [6]" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x14 5. " [5] ,Enable interrupt [5]" "Disabled,Enabled" newline setclrfld.long 0x10 4. 0x10 4. 0x14 4. " [4] ,Enable interrupt [4]" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x14 3. " [3] ,Enable interrupt [3]" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x14 2. " [2] ,Enable interrupt [2]" "Disabled,Enabled" newline setclrfld.long 0x10 1. 0x10 1. 0x14 1. " [1] ,Enable interrupt [1]" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x14 0. " [0] ,Enable interrupt [0]" "Disabled,Enabled" group.long 0xB0++0x03 line.long 0x00 "HWALVL_SET/CLR,HWAG Interrupt Priority Set Register" setclrfld.long 0x00 7. 0x00 7. 0x04 7. " LVLSET[7] ,Set interrupt [7] priority level" "Low,High" setclrfld.long 0x00 6. 0x00 6. 0x04 6. " [6] ,Set interrupt [6] priority level" "Low,High" setclrfld.long 0x00 5. 0x00 5. 0x04 5. " [5] ,Set interrupt [5] priority level" "Low,High" newline setclrfld.long 0x00 4. 0x00 4. 0x04 4. " [4] ,Set interrupt [4] priority level" "Low,High" setclrfld.long 0x00 3. 0x00 3. 0x04 3. " [3] ,Set interrupt [3] priority level" "Low,High" setclrfld.long 0x00 2. 0x00 2. 0x04 2. " [2] ,Set interrupt [2] priority level" "Low,High" newline setclrfld.long 0x00 1. 0x00 1. 0x04 1. " [1] ,Set interrupt [1] priority level" "Low,High" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " [0] ,Set interrupt [0] priority level" "Low,High" group.long 0xB8++0x27 line.long 0x00 "HWAFLG,HWAG Interrupt Flags Register" eventfld.long 0x00 7. " INTFLG[7] ,Interrupt 7 flag" "No effect,Pending" eventfld.long 0x00 6. " [6] ,Interrupt 6 flag" "No effect,Pending" eventfld.long 0x00 5. " [5] ,Interrupt 5 flag" "No effect,Pending" newline eventfld.long 0x00 4. " [4] ,Interrupt 4 flag" "No effect,Pending" eventfld.long 0x00 3. " [3] ,Interrupt 3 flag" "No effect,Pending" eventfld.long 0x00 2. " [2] ,Interrupt 2 flag" "No effect,Pending" newline eventfld.long 0x00 1. " [1] ,Interrupt 1 flag" "No effect,Pending" eventfld.long 0x00 0. " [0] ,Interrupt 0 flag" "No effect,Pending" line.long 0x04 "HWAOFF0,HWAG Interrupt Offset Register 0" hexmask.long.byte 0x04 0.--7. 0x01 " OFFSET1 ,High-priority interrupt offset" line.long 0x08 "HWAOFF1,HWAG Interrupt Offset Register 1" hexmask.long.byte 0x08 0.--7. 0x01 " OFFSET2 ,Low-priority interrupt offset" line.long 0x0C "HWAACNT,HWAG ACNT Register, HWAG Angle Value" hexmask.long.tbyte 0x0C 0.--23. 1. " ACNT ,Angle value" line.long 0x10 "HWAPCNT1,HWAG PCNT (n-1) Register, HWAG Previous Tooth Period" hexmask.long.tbyte 0x10 0.--23. 1. " PCNT(N-1) ,Period (n-1) value" line.long 0x14 "HWAPCNT,HWAG PCNT (n) Register, HWAG Current Tooth Period" hexmask.long.tbyte 0x14 0.--23. 1. " PCNT(N) ,Period (n) value" line.long 0x18 "HWASTWD,HWAG Step Register" bitfld.long 0x18 0.--3. " STWD ,Step width (ticks per period)" "4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768,65536,131072" line.long 0x1C "HWATHNB,HWAG Teeth Number Register" hexmask.long.byte 0x1C 0.--7. 1. " THNB ,Teeth number" line.long 0x20 "HWATHVL,HHWAG Current Teeth Number Register" hexmask.long.byte 0x20 0.--7. 1. " THVL ,Teeth value" line.long 0x24 "HWAFIL,HWAG Filter Register" hexmask.long.word 0x24 0.--9. 1. " FIL1 ,Filter value 1" group.long 0xE8++0x07 line.long 0x00 "HWAFIL2,HWAG Filter Register 2, HWAG Tick Counter Compare Value During Singularity Tooth" hexmask.long.word 0x00 0.--11. 1. " FIL2 ,Filter value 2" line.long 0x04 "HWAANGI,HWAG Angle Increment Register" hexmask.long.word 0x04 0.--9. 1. " ANGI ,Angle increment value" elif (cpu()==("TMS570LS2126")||cpu()==("TMS570LS2127")||cpu()==("TMS570LS2136")||cpu()==("TMS570LS2137")||cpu()==("TMS570LS2125-PGE")||cpu()==("TMS570LS2125-ZWT")||cpu()==("TMS570LS2135-PGE")||cpu()==("TMS570LS2135-ZWT")||cpu()==("TMS570LS2124-PGE")||cpu()==("TMS570LS2124-ZWT")||cpu()==("TMS570LS2134-PGE")||cpu()==("TMS570LS2134-ZWT")||cpu()==("TMS570LS3134-PGE")||cpu()==("TMS570LS3134-ZWT")||cpu()==("TMS570LS3135-PGE")||cpu()==("TMS570LS3135-ZWT")||cpu()==("TMS570LS3136")||cpu()==("TMS570LS3137-PGE")||cpu()==("TMS570LS3137-ZWT")||cpu()==("TMS570LS30336")||cpuis("RM48L950*")) group.long 0xA0++0x43 line.long 0x00 "HWAGCR0,HWAG Control Register 0" line.long 0x04 "HWAGCR1,HWAG Control Register 1" line.long 0x08 "HWAGCR2,HWAG Control Register 2" line.long 0x0C "HWAENASET,HWAG Interrupt Enable Set Register" line.long 0x10 "HWAENACLR,HWAG Interrupt Enable Clear Register" line.long 0x14 "HWALVLSET,HWAG Interrupt Priority Set Register" line.long 0x18 "HWALVLCLR,HWAG Interrupt Priority Clear Register" line.long 0x1C "HWAFLG,HWAG Interrupt Flags Register" line.long 0x20 "HWAOFF0,HWAG Interrupt Offset Register 1, HWAG Low Priority Interrupt Offset" line.long 0x24 "HWAOFF1,HWAG Interrupt Offset Register 2, HWAG High Priority Interrupt Offset" line.long 0x28 "HWAACNT,HWAG ACNT Register, HWAG Angle Value" line.long 0x2C "HWAPCNT1,HWAG PCNT (n-1) Register, HWAG Previous Tooth Period" line.long 0x30 "HWAPCNT,HWAG PCNT (n) Register, HWAG Current Tooth Period" line.long 0x34 "HWASTWD,HWAG Step Register" line.long 0x38 "HWATHNB,HWAG Teeth Number Register" line.long 0x3C "HWATHVL,HHWAG Current Teeth Number Register" line.long 0x40 "HWAFIL,HWAG Filter Register, HWAG Tick Counter Compare Value" group.long 0xE8++0x07 line.long 0x00 "HWAFIL2,HWAG Filter Register 2, HWAG Tick Counter Compare Value During Singularity Tooth" line.long 0x04 "HWAANGI,HWAG Angle Increment Register" endif sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*") endian.le endif width 0x0B tree.end endif tree.end tree "HTU (High End Timer Transfer Unit)" tree "HTU1" base ad:0xFFF7A400 sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*") endian.be endif width 10. group.long 0x00++0x07 line.long 0x00 "GC,Global Control Register" bitfld.long 0x00 24. " VBUS_HOLD ,Hold the VBUS bus" "Not held,Held" bitfld.long 0x00 16. " HTUEN ,Transfer unit enable bit" "Disabled,Enabled" bitfld.long 0x00 8. " DEBM ,Debug mode" "Suspended,Continue" newline bitfld.long 0x00 0. " HTU_RES ,HTU software reset" "No reset,Reset" line.long 0x04 "CPENA,Control Packet Enable Register" bitfld.long 0x04 14.--15. " CPENA7 ,CP enable bits 7 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled" bitfld.long 0x04 12.--13. " CPENA6 ,CP enable bits 6 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled" newline bitfld.long 0x04 10.--11. " CPENA5 ,CP enable bits 5 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled" bitfld.long 0x04 8.--9. " CPENA4 ,CP enable bits 4 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled" newline bitfld.long 0x04 6.--7. " CPENA3 ,CP enable bits 3 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled" bitfld.long 0x04 4.--5. " CPENA2 ,CP enable bits 2 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled" newline bitfld.long 0x04 2.--3. " CPENA1 ,CP enable bits 1 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled" bitfld.long 0x04 0.--1. " CPENA0 ,CP enable bits 0 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled" group.long 0x8++0x03 line.long 0x00 "BUSY0,Control Packet (CP) Busy Register 0" eventfld.long 0x00 24. " BUSY0A ,Busy flag for CP A of double CP 0" "Low,High" eventfld.long 0x00 16. " BUSY0B ,Busy flag for CP B of double CP 0" "Low,High" eventfld.long 0x00 8. " BUSY1A ,Busy flag for CP A of double CP 1" "Low,High" eventfld.long 0x00 0. " BUSY1B ,Busy flag for CP B of double CP 1" "Low,High" group.long 0xC++0x03 line.long 0x00 "BUSY1,Control Packet (CP) Busy Register 1" eventfld.long 0x00 24. " BUSY2A ,Busy flag for CP A of double CP 2" "Low,High" eventfld.long 0x00 16. " BUSY2B ,Busy flag for CP B of double CP 2" "Low,High" eventfld.long 0x00 8. " BUSY3A ,Busy flag for CP A of double CP 3" "Low,High" eventfld.long 0x00 0. " BUSY3B ,Busy flag for CP B of double CP 3" "Low,High" group.long 0x10++0x03 line.long 0x00 "BUSY2,Control Packet (CP) Busy Register 2" eventfld.long 0x00 24. " BUSY4A ,Busy flag for CP A of double CP 4" "Low,High" eventfld.long 0x00 16. " BUSY4B ,Busy flag for CP B of double CP 4" "Low,High" eventfld.long 0x00 8. " BUSY5A ,Busy flag for CP A of double CP 5" "Low,High" eventfld.long 0x00 0. " BUSY5B ,Busy flag for CP B of double CP 5" "Low,High" group.long 0x14++0x03 line.long 0x00 "BUSY3,Control Packet (CP) Busy Register 3" eventfld.long 0x00 24. " BUSY6A ,Busy flag for CP A of double CP 6" "Low,High" eventfld.long 0x00 16. " BUSY6B ,Busy flag for CP B of double CP 6" "Low,High" eventfld.long 0x00 8. " BUSY7A ,Busy flag for CP A of double CP 7" "Low,High" eventfld.long 0x00 0. " BUSY7B ,Busy flag for CP B of double CP 7" "Low,High" sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP") group.long 0x18++0x3 line.long 0x00 "ACPE,Active Control Packet Register" eventfld.long 0x00 31. " ERRF ,Error flag" "No error,Error" rbitfld.long 0x00 24.--28. " ERRETC ,Error element transfer counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 16.--19. " ERRCPN ,Error control packet number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 15. " TIPF ,Transfer in progress flag" "Not active,Active" newline rbitfld.long 0x00 14. " BUS_BUSY ,VBUSP bus is busy" "Not busy,Busy" rbitfld.long 0x00 8.--12. " CETCOUNT ,Current element transfer counter" "No transfer,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 0.--3. " NACP ,Number of active control packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x18++0x3 line.long 0x00 "ACPE,Active Control Packet Register" eventfld.long 0x00 31. " ERRF ,Error flag" "No error,Error" bitfld.long 0x00 24.--28. " ERRETC ,Error element transfer counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 16.--19. 1. " ERRCPN ,Error control packet number" bitfld.long 0x00 15. " TIPF ,Transfer in progress flag" "Not active,Active" newline bitfld.long 0x00 14. " BUS_BUSY ,VBUSP bus is busy" "Not busy,Busy" bitfld.long 0x00 8.--12. " CETCOUNT ,Current element transfer counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 0.--3. 1. " NACP ,Number of active control packet" endif newline width 16. group.long 0x20++0x07 line.long 0x00 "RLBECTRL,Request Lost and Bus Error Control Register" bitfld.long 0x00 16. " BERINTENA ,Bus error interrupt enable bit" "Disabled,Enabled" bitfld.long 0x00 8. " CORL ,Continue on request lost error" "Lost,Continue" bitfld.long 0x00 0. " RLINTENA ,Request lost interrupt enable bit" "Disabled,Enabled" line.long 0x04 "BFINTS_SET/CLR,Buffer Full Interrupt Enable Set/Clr Register" setclrfld.long 0x04 15. 0x04 15. 0x08 15. " BFINTENA[15] ,CP B Buffer full interrupt enable bit 15" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x08 14. " [14] ,CP A Buffer full interrupt enable Bit 14" "Disabled,Enabled" setclrfld.long 0x04 13. 0x04 13. 0x08 13. " [13] ,CP B Bit 13" "Disabled,Enabled" newline setclrfld.long 0x04 12. 0x04 12. 0x08 12. " [12] ,CP A Buffer Full Interrupt Enable Bit 12" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x08 11. " [11] ,CP B buffer full interrupt enable bit 11" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x08 10. " [10] ,CP A buffer full interrupt enable bit 10" "Disabled,Enabled" newline setclrfld.long 0x04 9. 0x04 9. 0x08 9. " [9] ,CP B buffer full interrupt enable bit 9" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x08 8. " [8] ,CP A buffer full interrupt enable bit 8" "Disabled,Enabled" setclrfld.long 0x04 7. 0x04 7. 0x08 7. " [7] ,CP B buffer full interrupt enable bit 7" "Disabled,Enabled" newline setclrfld.long 0x04 6. 0x04 6. 0x08 6. " [6] ,CP A buffer full interrupt enable bit 6" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x08 5. " [5] ,CP B buffer full interrupt enable bit 5" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x08 4. " [4] ,CP A buffer full interrupt enable bit 4" "Disabled,Enabled" newline setclrfld.long 0x04 3. 0x04 3. 0x08 3. " [3] ,CP B buffer full interrupt enable bit 3" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x08 2. " [2] ,CP A buffer full interrupt enable bit 2" "Disabled,Enabled" setclrfld.long 0x04 1. 0x04 1. 0x08 1. " [1] ,CP B buffer full interrupt enable bit 1" "Disabled,Enabled" newline setclrfld.long 0x04 0. 0x04 0. 0x08 0. " [0] ,CP A buffer full interrupt enable bit 0" "Disabled,Enabled" group.long 0x2C++0x03 line.long 0x00 "INTMAP,Interrupt Mapping Register" bitfld.long 0x00 16. " MAPSEL ,Interrupt mapping select bit" "Low,High" bitfld.long 0x00 15. " CPINTMAP[15] ,CP B Interrupt mapping bit 15" "Line 0,Line 1" bitfld.long 0x00 14. " [14] ,CP A Interrupt mapping bit 14" "Line 0,Line 1" newline bitfld.long 0x00 13. " [13] ,CP B Interrupt mapping bit 13" "Line 0,Line 1" bitfld.long 0x00 12. " [12] ,CP A Interrupt mapping bit 12" "Line 0,Line 1" bitfld.long 0x00 11. " [11] ,CP B Interrupt mapping bit 11" "Line 0,Line 1" newline bitfld.long 0x00 10. " [10] ,CP A Interrupt mapping bit 10" "Line 0,Line 1" bitfld.long 0x00 9. " [9] ,CP B Interrupt mapping bit 9" "Line 0,Line 1" bitfld.long 0x00 8. " [8] ,CP A Interrupt mapping bit 8" "Line 0,Line 1" newline bitfld.long 0x00 7. " [7] ,CP B Interrupt mapping bit 7" "Line 0,Line 1" bitfld.long 0x00 6. " [6] ,CP A Interrupt mapping bit 6" "Line 0,Line 1" bitfld.long 0x00 5. " [5] ,CP B Interrupt mapping bit 5" "Line 0,Line 1" newline bitfld.long 0x00 4. " [4] ,CP A Interrupt mapping bit 4" "Line 0,Line 1" bitfld.long 0x00 3. " [3] ,CP B Interrupt mapping bit 3" "Line 0,Line 1" bitfld.long 0x00 2. " [2] ,CP A Interrupt mapping bit 2" "Line 0,Line 1" newline bitfld.long 0x00 1. " [1] ,CP B Interrupt mapping bit 1" "Line 0,Line 1" bitfld.long 0x00 0. " [0] ,CP A Interrupt mapping bit 0" "Line 0,Line 1" newline width 10. hgroup.long 0x34++0x3 hide.long 0x0 "INTOFF0,Interrupt Offset Register 0" in hgroup.long 0x38++0x3 hide.long 0x0 "INTOFF1,Interrupt Offset Register 1" in newline group.long 0x3C++0x23 line.long 0x00 "BIM,Buffer Initialization Mode Register" bitfld.long 0x00 7. " BIM[7] ,Buffer initialization mode bit 7" "Normal,Special" bitfld.long 0x00 6. " BIM[6] ,Buffer initialization mode bit 6" "Normal,Special" bitfld.long 0x00 5. " BIM[5] ,Buffer initialization mode bit 5" "Normal,Special" bitfld.long 0x00 4. " BIM[4] ,Buffer initialization mode bit 4" "Normal,Special" newline bitfld.long 0x00 3. " BIM[3] ,Buffer initialization mode bit 3" "Normal,Special" bitfld.long 0x00 2. " BIM[2] ,Buffer initialization mode bit 2" "Normal,Special" bitfld.long 0x00 1. " BIM[1] ,Buffer initialization mode bit 1" "Normal,Special" bitfld.long 0x00 0. " BIM[0] ,Buffer initialization mode bit 0" "Normal,Special" line.long 0x04 "RLOSTFL,Request Lost Flag Register" eventfld.long 0x04 15. " CPRLFL[15] ,CP B request lost flag 15" "Not requested,Requested" eventfld.long 0x04 14. " CPRLFL[14] ,CP A request lost flag 14" "Not requested,Requested" newline eventfld.long 0x04 13. " CPRLFL[13] ,CP B request lost flag 13" "Not requested,Requested" eventfld.long 0x04 12. " CPRLFL[12] ,CP A request lost flag 12" "Not requested,Requested" newline eventfld.long 0x04 11. " CPRLFL[11] ,CP B request lost flag 11" "Not requested,Requested" eventfld.long 0x04 10. " CPRLFL[10] ,CP A request lost flag 10" "Not requested,Requested" newline eventfld.long 0x04 9. " CPRLFL[9] ,CP B request lost flag 9" "Not requested,Requested" eventfld.long 0x04 8. " CPRLFL[8] ,CP A request lost flag 8" "Not requested,Requested" newline eventfld.long 0x04 7. " CPRLFL[7] ,CP B request lost flag 7" "Not requested,Requested" eventfld.long 0x04 6. " CPRLFL[6] ,CP A request lost flag 6" "Not requested,Requested" newline eventfld.long 0x04 5. " CPRLFL[5] ,CP B request lost flag 5" "Not requested,Requested" eventfld.long 0x04 4. " CPRLFL[4] ,CP A request lost flag 4" "Not requested,Requested" newline eventfld.long 0x04 3. " CPRLFL[3] ,CP B request lost flag 3" "Not requested,Requested" eventfld.long 0x04 2. " CPRLFL[2] ,CP A request lost flag 2" "Not requested,Requested" newline eventfld.long 0x04 1. " CPRLFL[1] ,CP B request lost flag 1" "Not requested,Requested" eventfld.long 0x04 0. " CPRLFL[0] ,CP A request lost flag 0" "Not requested,Requested" line.long 0x08 "BFINTFL,Buffer Full Interrupt Flag Register" eventfld.long 0x08 15. " BFINTFL[15] ,CP B buffer full interrupt flag 15" "No interrupt,Interrupt" eventfld.long 0x08 14. " BFINTFL[14] ,CP A buffer full interrupt flag 14" "No interrupt,Interrupt" newline eventfld.long 0x08 13. " BFINTFL[13] ,CP B buffer full interrupt flag 13" "No interrupt,Interrupt" eventfld.long 0x08 12. " BFINTFL[12] ,CP A buffer full interrupt flag 12" "No interrupt,Interrupt" newline eventfld.long 0x08 11. " BFINTFL[11] ,CP B buffer full interrupt flag 11" "No interrupt,Interrupt" eventfld.long 0x08 10. " BFINTFL[10] ,CP A buffer full interrupt flag 10" "No interrupt,Interrupt" newline eventfld.long 0x08 9. " BFINTFL[9] ,CP B buffer full interrupt flag 9" "No interrupt,Interrupt" eventfld.long 0x08 8. " BFINTFL[8] ,CP A buffer full interrupt flag 8" "No interrupt,Interrupt" newline eventfld.long 0x08 7. " BFINTFL[7] ,CP B buffer full interrupt flag 7" "No interrupt,Interrupt" eventfld.long 0x08 6. " BFINTFL[6] ,CP A buffer full interrupt flag 6" "No interrupt,Interrupt" newline eventfld.long 0x08 5. " BFINTFL[5] ,CP B buffer full interrupt flag 5" "No interrupt,Interrupt" eventfld.long 0x08 4. " BFINTFL[4] ,CP A buffer full interrupt flag 4" "No interrupt,Interrupt" newline eventfld.long 0x08 3. " BFINTFL[3] ,CP B buffer full interrupt flag 3" "No interrupt,Interrupt" eventfld.long 0x08 2. " BFINTFL[2] ,CP A buffer full interrupt flag 2" "No interrupt,Interrupt" newline eventfld.long 0x08 1. " BFINTFL[1] ,CP B buffer full interrupt flag 1" "No interrupt,Interrupt" eventfld.long 0x08 0. " BFINTFL[0] ,CP A buffer full interrupt flag 0" "No interrupt,Interrupt" line.long 0x0C "BERINTFL,BER Interrupt Flag Register" eventfld.long 0x0C 15. " BERINTFL[15] ,CP B bus error interrupt flag 15" "No interrupt,Interrupt" eventfld.long 0x0C 14. " BERINTFL[14] ,CP A bus error interrupt flag 14" "No interrupt,Interrupt" newline eventfld.long 0x0C 13. " BERINTFL[13] ,CP B bus error interrupt flag 13" "No interrupt,Interrupt" eventfld.long 0x0C 12. " BERINTFL[12] ,CP A bus error interrupt flag 12" "No interrupt,Interrupt" newline eventfld.long 0x0C 11. " BERINTFL[11] ,CP B bus error interrupt flag 11" "No interrupt,Interrupt" eventfld.long 0x0C 10. " BERINTFL[10] ,CP A bus error interrupt flag 10" "No interrupt,Interrupt" newline eventfld.long 0x0C 9. " BERINTFL[9] ,CP B bus error interrupt flag 9" "No interrupt,Interrupt" eventfld.long 0x0C 8. " BERINTFL[8] ,CP A bus error interrupt flag 8" "No interrupt,Interrupt" newline eventfld.long 0x0C 7. " BERINTFL[7] ,CP B bus error interrupt flag 7" "No interrupt,Interrupt" eventfld.long 0x0C 6. " BERINTFL[6] ,CP A bus error interrupt flag 6" "No interrupt,Interrupt" newline eventfld.long 0x0C 5. " BERINTFL[5] ,CP B bus error interrupt flag 5" "No interrupt,Interrupt" eventfld.long 0x0C 4. " BERINTFL[4] ,CP A bus error interrupt flag 4" "No interrupt,Interrupt" newline eventfld.long 0x0C 3. " BERINTFL[3] ,CP B bus error interrupt flag 3" "No interrupt,Interrupt" eventfld.long 0x0C 2. " BERINTFL[2] ,CP A bus error interrupt flag 2" "No interrupt,Interrupt" newline eventfld.long 0x0C 1. " BERINTFL[1] ,CP B bus error interrupt flag 1" "No interrupt,Interrupt" eventfld.long 0x0C 0. " BERINTFL[0] ,CP A bus error interrupt flag 0" "No interrupt,Interrupt" line.long 0x10 "MP1S,Memory Protection 1 Start Address" line.long 0x14 "MP1E,Memory Protection 1 End Address" line.long 0x18 "DCTRL,Debug Control Register" sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")) rbitfld.long 0x18 24.--27. " CPNUM ,CP number" "CP A of DCP0,CP B of DCP0,CP A of DCP1,,,,,,,,,,,,CP A of DCP7,CP B of DCP7" elif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP") bitfld.long 0x18 24.--27. " CPNUM ,CP number" "CP A of DCP 0,CP B of DCP 0,CP A of DCP 1,CP B of DCP 1,CP A of DCP 2,CP B of DCP 2,CP A of DCP 3,CP B of DCP 3,CP A of DCP 4,CP B of DCP 4,CP A of DCP 5,CP B of DCP 5,CP A of DCP 6,CP B of DCP 6,CP A of DCP 7,CP B of DCP 7" else bitfld.long 0x18 24.--27. " CPNUM ,CP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline eventfld.long 0x18 16. " HTUDBGS ,HTU debug status" "Not detected,Detected" bitfld.long 0x18 0. " DBREN ,Debug request enable" "Disabled,Enabled" line.long 0x1C "WPR,Watch Point Register" line.long 0x20 "WMR,Watch Mask Register" rgroup.long 0x60++0x03 line.long 0x00 "ID,Module Identification Register" hexmask.long.byte 0x00 16.--23. 1. " CLASS ,Module class" hexmask.long.byte 0x00 8.--15. 1. " TYPE ,Subtype within a class" hexmask.long.byte 0x00 0.--7. 1. " REV ,Module revision number" group.long 0x64++0x07 line.long 0x0 "PCR,Parity Control Register" bitfld.long 0x00 16. " COPE , Continue on parity error" "Stopped,Continued" bitfld.long 0x00 8. " TEST ,Test" "Not mapped,Mapped" bitfld.long 0x00 0.--3. " PARITY_ENA ,Enable/disable parity checking" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" line.long 0x04 "PAR,Parity Address Register" eventfld.long 0x04 16. " PEFT ,Parity Error fault flag" "Not detected,Detected" hexmask.long.word 0x04 0.--8. 1. " PAOFF ,Parity error address offset" group.long 0x70++0x0B line.long 0x00 "MPCS,Memory Protection Control and Status Register" sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP") rbitfld.long 0x00 24.--27. " CPNUM0 ,CP number" "CP A of DCP 0,CP B of DCP 0,CP A of DCP 1,CP B of DCP 1,CP A of DCP 2,CP B of DCP 2,CP A of DCP 3,CP B of DCP 3,CP A of DCP 4,CP B of DCP 4,CP A of DCP 5,CP B of DCP 5,CP A of DCP 6,CP B of DCP 6,CP A of DCP 7,CP B of DCP 7" else bitfld.long 0x00 24.--27. " CPNUM0 ,CP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline eventfld.long 0x00 17. " MPEFT1 ,Memory protection error fault flag" "Not detected,Detected" eventfld.long 0x00 16. " MPEFT0 ,Memory protection error fault flag" "Not detected,Detected" newline sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")) rbitfld.long 0x00 8.--11. " CPNUM1 ,CP number" "CP A of DCP0,CP B of DCP0,CP A of DCP1,,,,,,,,,,,,CP A of DCP7,CP B of DCP7" elif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP") rbitfld.long 0x00 8.--11. " CPNUM1 ,CP number" "CP A of DCP 0,CP B of DCP 0,CP A of DCP 1,CP B of DCP 1,CP A of DCP 2,CP B of DCP 2,CP A of DCP 3,CP B of DCP 3,CP A of DCP 4,CP B of DCP 4,CP A of DCP 5,CP B of DCP 5,CP A of DCP 6,CP B of DCP 6,CP A of DCP 7,CP B of DCP 7" else bitfld.long 0x00 8.--11. " CPNUM1 ,CP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.long 0x00 5. " INTENA01 ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " ACCR01 ,Access rights HTU" "Allowed,Forbidden" newline bitfld.long 0x00 3. " REG01ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x00 2. " INTENA0 ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " ACCR ,Access rights HTU" "Allowed,Forbidden" newline bitfld.long 0x00 0. " REG0ENA ,Region enable" "Disabled,Enabled" line.long 0x04 "MP0S,Memory Protection Start Address Register" line.long 0x08 "MP0E,Memory Protection End Address Register" sif (cpuis("TMS570LS10106-PGE")||cpuis("TMS570LS10106-ZWT")||cpuis("TMS570LS10116-PGE")||cpuis("TMS570LS10116-ZWT")||cpuis("TMS570LS10206-PGE")||cpuis("TMS570LS10206-ZWT")||cpuis("TMS570LS10216-PGE")||cpuis("TMS570LS10216-ZWT")||cpuis("TMS570LS20206-PGE")||cpuis("TMS570LS20206-ZWT")||cpuis("TMS570LS20216-PGE")||cpuis("TMS570LS20216-ZWT")||cpuis("RM48L952-PGE")||cpuis("RM48L952-ZWT")||cpuis("RM48L950-PGE")||cpuis("RM48L950-ZWT")||cpuis("RM48L940-ZWT")||cpuis("RM48L940-PGE")||cpuis("RM48L930-ZWT")||cpuis("RM48L930-PGE")||cpuis("RM48L750-ZWT")||cpuis("RM48L750-PGE")||cpuis("RM48L740-ZWT")||cpuis("RM48L740-PGE")||cpuis("RM48L730-ZWT")||cpuis("RM48L730-PGE")||cpuis("RM48L550-PGE")||cpuis("RM48L540-ZWT")||cpuis("RM48L540-PGE")||cpuis("RM48L530-ZWT")||cpuis("RM48L530-PGE")||cpuis("RM46L852-PGE")||cpuis("RM46L852-ZWT")||cpuis("RM46L850-PGE")||cpuis("RM46L850-ZWT")||cpuis("RM46L840-ZWT")||cpuis("RM46L840-PGE")||cpuis("RM46L830-ZWT")||cpuis("RM46L830-PGE")||cpuis("RM46L450-ZWT")||cpuis("RM46L450-PGE")||cpuis("RM46L440-ZWT")||cpuis("RM46L440-PGE")||cpuis("RM46L430-ZWT")||cpuis("RM46L430-PGE")||cpuis("RM42L432")||cpuis("RM48L550-ZWT")||cpuis("TMS570LC4357")||cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP")) tree "Double Control Packet Configuration Memory" base ad:0xFF4E0000 sif !cpuis("TMS570LS0714*")&&!cpuis("TMS570LS0914*")&&!cpuis("RM46L852*")&&!cpuis("TMS570LS3137-EP") group.long 0x00++0xF line.long 0x00 "IFADDRA,Initial main memory address Control Packet A" line.long 0x04 "IFADDRB,Initial main memory address Control Packet B" line.long 0x08 "IHADDRCT,Initial NHET address and control" bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET" bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit" newline bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (increment value)" "16 bytes,8 bytes" bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant" newline bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch" bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch" newline hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address" line.long 0x0C "ITCOUNT,Initial transfer count" bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count" group.long 0x100++0xB line.long 0x00 "CFADDRA,Current main memory address Control Packet A" line.long 0x04 "CFADDRB,Current main memory address Control Packet B" line.long 0x08 "CFCOUNT,Current frame count" hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A" hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B" else width 15. group.long 0x0++0x0F "DCP0" line.long 0x00 "DCP0IFADDRA,DCP0 Initial main memory address Control Packet A" line.long 0x04 "DCP0IFADDRB,DCP0 Initial main memory address Control Packet B" line.long 0x08 "DCP0IHADDRCT,DCP0 Initial NHET address and control" bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET" bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit" newline bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes" bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant" newline bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch" bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch" newline hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address" line.long 0x0C "DCP0ITCOUNT,DCP0 Initial transfer count" bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count" group.long (0x0+0x100)++0xB line.long 0x00 "DCP0CFADDRA,DCP0 Current main memory address control packet A" line.long 0x04 "DCP0CFADDRB,DCP0 Current main memory address control packet B" line.long 0x08 "DCP0CFCOUNT,DCP0 Current frame count" hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A" hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B" group.long 0x10++0x0F "DCP1" line.long 0x00 "DCP1IFADDRA,DCP1 Initial main memory address Control Packet A" line.long 0x04 "DCP1IFADDRB,DCP1 Initial main memory address Control Packet B" line.long 0x08 "DCP1IHADDRCT,DCP1 Initial NHET address and control" bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET" bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit" newline bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes" bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant" newline bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch" bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch" newline hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address" line.long 0x0C "DCP1ITCOUNT,DCP1 Initial transfer count" bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count" group.long (0x10+0x100)++0xB line.long 0x00 "DCP1CFADDRA,DCP1 Current main memory address control packet A" line.long 0x04 "DCP1CFADDRB,DCP1 Current main memory address control packet B" line.long 0x08 "DCP1CFCOUNT,DCP1 Current frame count" hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A" hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B" group.long 0x20++0x0F "DCP2" line.long 0x00 "DCP2IFADDRA,DCP2 Initial main memory address Control Packet A" line.long 0x04 "DCP2IFADDRB,DCP2 Initial main memory address Control Packet B" line.long 0x08 "DCP2IHADDRCT,DCP2 Initial NHET address and control" bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET" bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit" newline bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes" bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant" newline bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch" bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch" newline hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address" line.long 0x0C "DCP2ITCOUNT,DCP2 Initial transfer count" bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count" group.long (0x20+0x100)++0xB line.long 0x00 "DCP2CFADDRA,DCP2 Current main memory address control packet A" line.long 0x04 "DCP2CFADDRB,DCP2 Current main memory address control packet B" line.long 0x08 "DCP2CFCOUNT,DCP2 Current frame count" hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A" hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B" group.long 0x30++0x0F "DCP3" line.long 0x00 "DCP3IFADDRA,DCP3 Initial main memory address Control Packet A" line.long 0x04 "DCP3IFADDRB,DCP3 Initial main memory address Control Packet B" line.long 0x08 "DCP3IHADDRCT,DCP3 Initial NHET address and control" bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET" bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit" newline bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes" bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant" newline bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch" bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch" newline hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address" line.long 0x0C "DCP3ITCOUNT,DCP3 Initial transfer count" bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count" group.long (0x30+0x100)++0xB line.long 0x00 "DCP3CFADDRA,DCP3 Current main memory address control packet A" line.long 0x04 "DCP3CFADDRB,DCP3 Current main memory address control packet B" line.long 0x08 "DCP3CFCOUNT,DCP3 Current frame count" hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A" hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B" group.long 0x40++0x0F "DCP4" line.long 0x00 "DCP4IFADDRA,DCP4 Initial main memory address Control Packet A" line.long 0x04 "DCP4IFADDRB,DCP4 Initial main memory address Control Packet B" line.long 0x08 "DCP4IHADDRCT,DCP4 Initial NHET address and control" bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET" bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit" newline bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes" bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant" newline bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch" bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch" newline hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address" line.long 0x0C "DCP4ITCOUNT,DCP4 Initial transfer count" bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count" group.long (0x40+0x100)++0xB line.long 0x00 "DCP4CFADDRA,DCP4 Current main memory address control packet A" line.long 0x04 "DCP4CFADDRB,DCP4 Current main memory address control packet B" line.long 0x08 "DCP4CFCOUNT,DCP4 Current frame count" hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A" hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B" group.long 0x50++0x0F "DCP5" line.long 0x00 "DCP5IFADDRA,DCP5 Initial main memory address Control Packet A" line.long 0x04 "DCP5IFADDRB,DCP5 Initial main memory address Control Packet B" line.long 0x08 "DCP5IHADDRCT,DCP5 Initial NHET address and control" bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET" bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit" newline bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes" bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant" newline bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch" bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch" newline hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address" line.long 0x0C "DCP5ITCOUNT,DCP5 Initial transfer count" bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count" group.long (0x50+0x100)++0xB line.long 0x00 "DCP5CFADDRA,DCP5 Current main memory address control packet A" line.long 0x04 "DCP5CFADDRB,DCP5 Current main memory address control packet B" line.long 0x08 "DCP5CFCOUNT,DCP5 Current frame count" hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A" hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B" group.long 0x60++0x0F "DCP6" line.long 0x00 "DCP6IFADDRA,DCP6 Initial main memory address Control Packet A" line.long 0x04 "DCP6IFADDRB,DCP6 Initial main memory address Control Packet B" line.long 0x08 "DCP6IHADDRCT,DCP6 Initial NHET address and control" bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET" bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit" newline bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes" bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant" newline bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch" bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch" newline hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address" line.long 0x0C "DCP6ITCOUNT,DCP6 Initial transfer count" bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count" group.long (0x60+0x100)++0xB line.long 0x00 "DCP6CFADDRA,DCP6 Current main memory address control packet A" line.long 0x04 "DCP6CFADDRB,DCP6 Current main memory address control packet B" line.long 0x08 "DCP6CFCOUNT,DCP6 Current frame count" hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A" hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B" group.long 0x70++0x0F "DCP7" line.long 0x00 "DCP7IFADDRA,DCP7 Initial main memory address Control Packet A" line.long 0x04 "DCP7IFADDRB,DCP7 Initial main memory address Control Packet B" line.long 0x08 "DCP7IHADDRCT,DCP7 Initial NHET address and control" bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET" bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit" newline bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes" bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant" newline bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch" bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch" newline hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address" line.long 0x0C "DCP7ITCOUNT,DCP7 Initial transfer count" bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count" group.long (0x70+0x100)++0xB line.long 0x00 "DCP7CFADDRA,DCP7 Current main memory address control packet A" line.long 0x04 "DCP7CFADDRB,DCP7 Current main memory address control packet B" line.long 0x08 "DCP7CFCOUNT,DCP7 Current frame count" hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A" hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B" endif tree.end endif sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*") endian.le endif width 0x0B tree.end sif (cpu()!="RM42L432") tree "HTU2" base ad:0xFFF7A500 sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*") endian.be endif width 10. group.long 0x00++0x07 line.long 0x00 "GC,Global Control Register" bitfld.long 0x00 24. " VBUS_HOLD ,Hold the VBUS bus" "Not held,Held" bitfld.long 0x00 16. " HTUEN ,Transfer unit enable bit" "Disabled,Enabled" bitfld.long 0x00 8. " DEBM ,Debug mode" "Suspended,Continue" newline bitfld.long 0x00 0. " HTU_RES ,HTU software reset" "No reset,Reset" line.long 0x04 "CPENA,Control Packet Enable Register" bitfld.long 0x04 14.--15. " CPENA7 ,CP enable bits 7 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled" bitfld.long 0x04 12.--13. " CPENA6 ,CP enable bits 6 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled" newline bitfld.long 0x04 10.--11. " CPENA5 ,CP enable bits 5 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled" bitfld.long 0x04 8.--9. " CPENA4 ,CP enable bits 4 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled" newline bitfld.long 0x04 6.--7. " CPENA3 ,CP enable bits 3 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled" bitfld.long 0x04 4.--5. " CPENA2 ,CP enable bits 2 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled" newline bitfld.long 0x04 2.--3. " CPENA1 ,CP enable bits 1 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled" bitfld.long 0x04 0.--1. " CPENA0 ,CP enable bits 0 (CP B/CP A)" "Disabled,Disabled/Enabled,Enabled/Disabled,Disabled" group.long 0x8++0x03 line.long 0x00 "BUSY0,Control Packet (CP) Busy Register 0" eventfld.long 0x00 24. " BUSY0A ,Busy flag for CP A of double CP 0" "Low,High" eventfld.long 0x00 16. " BUSY0B ,Busy flag for CP B of double CP 0" "Low,High" eventfld.long 0x00 8. " BUSY1A ,Busy flag for CP A of double CP 1" "Low,High" eventfld.long 0x00 0. " BUSY1B ,Busy flag for CP B of double CP 1" "Low,High" group.long 0xC++0x03 line.long 0x00 "BUSY1,Control Packet (CP) Busy Register 1" eventfld.long 0x00 24. " BUSY2A ,Busy flag for CP A of double CP 2" "Low,High" eventfld.long 0x00 16. " BUSY2B ,Busy flag for CP B of double CP 2" "Low,High" eventfld.long 0x00 8. " BUSY3A ,Busy flag for CP A of double CP 3" "Low,High" eventfld.long 0x00 0. " BUSY3B ,Busy flag for CP B of double CP 3" "Low,High" group.long 0x10++0x03 line.long 0x00 "BUSY2,Control Packet (CP) Busy Register 2" eventfld.long 0x00 24. " BUSY4A ,Busy flag for CP A of double CP 4" "Low,High" eventfld.long 0x00 16. " BUSY4B ,Busy flag for CP B of double CP 4" "Low,High" eventfld.long 0x00 8. " BUSY5A ,Busy flag for CP A of double CP 5" "Low,High" eventfld.long 0x00 0. " BUSY5B ,Busy flag for CP B of double CP 5" "Low,High" group.long 0x14++0x03 line.long 0x00 "BUSY3,Control Packet (CP) Busy Register 3" eventfld.long 0x00 24. " BUSY6A ,Busy flag for CP A of double CP 6" "Low,High" eventfld.long 0x00 16. " BUSY6B ,Busy flag for CP B of double CP 6" "Low,High" eventfld.long 0x00 8. " BUSY7A ,Busy flag for CP A of double CP 7" "Low,High" eventfld.long 0x00 0. " BUSY7B ,Busy flag for CP B of double CP 7" "Low,High" sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP") group.long 0x18++0x3 line.long 0x00 "ACPE,Active Control Packet Register" eventfld.long 0x00 31. " ERRF ,Error flag" "No error,Error" rbitfld.long 0x00 24.--28. " ERRETC ,Error element transfer counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 16.--19. " ERRCPN ,Error control packet number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 15. " TIPF ,Transfer in progress flag" "Not active,Active" newline rbitfld.long 0x00 14. " BUS_BUSY ,VBUSP bus is busy" "Not busy,Busy" rbitfld.long 0x00 8.--12. " CETCOUNT ,Current element transfer counter" "No transfer,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 0.--3. " NACP ,Number of active control packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x18++0x3 line.long 0x00 "ACPE,Active Control Packet Register" eventfld.long 0x00 31. " ERRF ,Error flag" "No error,Error" bitfld.long 0x00 24.--28. " ERRETC ,Error element transfer counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 16.--19. 1. " ERRCPN ,Error control packet number" bitfld.long 0x00 15. " TIPF ,Transfer in progress flag" "Not active,Active" newline bitfld.long 0x00 14. " BUS_BUSY ,VBUSP bus is busy" "Not busy,Busy" bitfld.long 0x00 8.--12. " CETCOUNT ,Current element transfer counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x00 0.--3. 1. " NACP ,Number of active control packet" endif newline width 16. group.long 0x20++0x07 line.long 0x00 "RLBECTRL,Request Lost and Bus Error Control Register" bitfld.long 0x00 16. " BERINTENA ,Bus error interrupt enable bit" "Disabled,Enabled" bitfld.long 0x00 8. " CORL ,Continue on request lost error" "Lost,Continue" bitfld.long 0x00 0. " RLINTENA ,Request lost interrupt enable bit" "Disabled,Enabled" line.long 0x04 "BFINTS_SET/CLR,Buffer Full Interrupt Enable Set/Clr Register" setclrfld.long 0x04 15. 0x04 15. 0x08 15. " BFINTENA[15] ,CP B Buffer full interrupt enable bit 15" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x08 14. " [14] ,CP A Buffer full interrupt enable Bit 14" "Disabled,Enabled" setclrfld.long 0x04 13. 0x04 13. 0x08 13. " [13] ,CP B Bit 13" "Disabled,Enabled" newline setclrfld.long 0x04 12. 0x04 12. 0x08 12. " [12] ,CP A Buffer Full Interrupt Enable Bit 12" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x08 11. " [11] ,CP B buffer full interrupt enable bit 11" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x08 10. " [10] ,CP A buffer full interrupt enable bit 10" "Disabled,Enabled" newline setclrfld.long 0x04 9. 0x04 9. 0x08 9. " [9] ,CP B buffer full interrupt enable bit 9" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x08 8. " [8] ,CP A buffer full interrupt enable bit 8" "Disabled,Enabled" setclrfld.long 0x04 7. 0x04 7. 0x08 7. " [7] ,CP B buffer full interrupt enable bit 7" "Disabled,Enabled" newline setclrfld.long 0x04 6. 0x04 6. 0x08 6. " [6] ,CP A buffer full interrupt enable bit 6" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x08 5. " [5] ,CP B buffer full interrupt enable bit 5" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x08 4. " [4] ,CP A buffer full interrupt enable bit 4" "Disabled,Enabled" newline setclrfld.long 0x04 3. 0x04 3. 0x08 3. " [3] ,CP B buffer full interrupt enable bit 3" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x08 2. " [2] ,CP A buffer full interrupt enable bit 2" "Disabled,Enabled" setclrfld.long 0x04 1. 0x04 1. 0x08 1. " [1] ,CP B buffer full interrupt enable bit 1" "Disabled,Enabled" newline setclrfld.long 0x04 0. 0x04 0. 0x08 0. " [0] ,CP A buffer full interrupt enable bit 0" "Disabled,Enabled" group.long 0x2C++0x03 line.long 0x00 "INTMAP,Interrupt Mapping Register" bitfld.long 0x00 16. " MAPSEL ,Interrupt mapping select bit" "Low,High" bitfld.long 0x00 15. " CPINTMAP[15] ,CP B Interrupt mapping bit 15" "Line 0,Line 1" bitfld.long 0x00 14. " [14] ,CP A Interrupt mapping bit 14" "Line 0,Line 1" newline bitfld.long 0x00 13. " [13] ,CP B Interrupt mapping bit 13" "Line 0,Line 1" bitfld.long 0x00 12. " [12] ,CP A Interrupt mapping bit 12" "Line 0,Line 1" bitfld.long 0x00 11. " [11] ,CP B Interrupt mapping bit 11" "Line 0,Line 1" newline bitfld.long 0x00 10. " [10] ,CP A Interrupt mapping bit 10" "Line 0,Line 1" bitfld.long 0x00 9. " [9] ,CP B Interrupt mapping bit 9" "Line 0,Line 1" bitfld.long 0x00 8. " [8] ,CP A Interrupt mapping bit 8" "Line 0,Line 1" newline bitfld.long 0x00 7. " [7] ,CP B Interrupt mapping bit 7" "Line 0,Line 1" bitfld.long 0x00 6. " [6] ,CP A Interrupt mapping bit 6" "Line 0,Line 1" bitfld.long 0x00 5. " [5] ,CP B Interrupt mapping bit 5" "Line 0,Line 1" newline bitfld.long 0x00 4. " [4] ,CP A Interrupt mapping bit 4" "Line 0,Line 1" bitfld.long 0x00 3. " [3] ,CP B Interrupt mapping bit 3" "Line 0,Line 1" bitfld.long 0x00 2. " [2] ,CP A Interrupt mapping bit 2" "Line 0,Line 1" newline bitfld.long 0x00 1. " [1] ,CP B Interrupt mapping bit 1" "Line 0,Line 1" bitfld.long 0x00 0. " [0] ,CP A Interrupt mapping bit 0" "Line 0,Line 1" newline width 10. hgroup.long 0x34++0x3 hide.long 0x0 "INTOFF0,Interrupt Offset Register 0" in hgroup.long 0x38++0x3 hide.long 0x0 "INTOFF1,Interrupt Offset Register 1" in newline group.long 0x3C++0x23 line.long 0x00 "BIM,Buffer Initialization Mode Register" bitfld.long 0x00 7. " BIM[7] ,Buffer initialization mode bit 7" "Normal,Special" bitfld.long 0x00 6. " BIM[6] ,Buffer initialization mode bit 6" "Normal,Special" bitfld.long 0x00 5. " BIM[5] ,Buffer initialization mode bit 5" "Normal,Special" bitfld.long 0x00 4. " BIM[4] ,Buffer initialization mode bit 4" "Normal,Special" newline bitfld.long 0x00 3. " BIM[3] ,Buffer initialization mode bit 3" "Normal,Special" bitfld.long 0x00 2. " BIM[2] ,Buffer initialization mode bit 2" "Normal,Special" bitfld.long 0x00 1. " BIM[1] ,Buffer initialization mode bit 1" "Normal,Special" bitfld.long 0x00 0. " BIM[0] ,Buffer initialization mode bit 0" "Normal,Special" line.long 0x04 "RLOSTFL,Request Lost Flag Register" eventfld.long 0x04 15. " CPRLFL[15] ,CP B request lost flag 15" "Not requested,Requested" eventfld.long 0x04 14. " CPRLFL[14] ,CP A request lost flag 14" "Not requested,Requested" newline eventfld.long 0x04 13. " CPRLFL[13] ,CP B request lost flag 13" "Not requested,Requested" eventfld.long 0x04 12. " CPRLFL[12] ,CP A request lost flag 12" "Not requested,Requested" newline eventfld.long 0x04 11. " CPRLFL[11] ,CP B request lost flag 11" "Not requested,Requested" eventfld.long 0x04 10. " CPRLFL[10] ,CP A request lost flag 10" "Not requested,Requested" newline eventfld.long 0x04 9. " CPRLFL[9] ,CP B request lost flag 9" "Not requested,Requested" eventfld.long 0x04 8. " CPRLFL[8] ,CP A request lost flag 8" "Not requested,Requested" newline eventfld.long 0x04 7. " CPRLFL[7] ,CP B request lost flag 7" "Not requested,Requested" eventfld.long 0x04 6. " CPRLFL[6] ,CP A request lost flag 6" "Not requested,Requested" newline eventfld.long 0x04 5. " CPRLFL[5] ,CP B request lost flag 5" "Not requested,Requested" eventfld.long 0x04 4. " CPRLFL[4] ,CP A request lost flag 4" "Not requested,Requested" newline eventfld.long 0x04 3. " CPRLFL[3] ,CP B request lost flag 3" "Not requested,Requested" eventfld.long 0x04 2. " CPRLFL[2] ,CP A request lost flag 2" "Not requested,Requested" newline eventfld.long 0x04 1. " CPRLFL[1] ,CP B request lost flag 1" "Not requested,Requested" eventfld.long 0x04 0. " CPRLFL[0] ,CP A request lost flag 0" "Not requested,Requested" line.long 0x08 "BFINTFL,Buffer Full Interrupt Flag Register" eventfld.long 0x08 15. " BFINTFL[15] ,CP B buffer full interrupt flag 15" "No interrupt,Interrupt" eventfld.long 0x08 14. " BFINTFL[14] ,CP A buffer full interrupt flag 14" "No interrupt,Interrupt" newline eventfld.long 0x08 13. " BFINTFL[13] ,CP B buffer full interrupt flag 13" "No interrupt,Interrupt" eventfld.long 0x08 12. " BFINTFL[12] ,CP A buffer full interrupt flag 12" "No interrupt,Interrupt" newline eventfld.long 0x08 11. " BFINTFL[11] ,CP B buffer full interrupt flag 11" "No interrupt,Interrupt" eventfld.long 0x08 10. " BFINTFL[10] ,CP A buffer full interrupt flag 10" "No interrupt,Interrupt" newline eventfld.long 0x08 9. " BFINTFL[9] ,CP B buffer full interrupt flag 9" "No interrupt,Interrupt" eventfld.long 0x08 8. " BFINTFL[8] ,CP A buffer full interrupt flag 8" "No interrupt,Interrupt" newline eventfld.long 0x08 7. " BFINTFL[7] ,CP B buffer full interrupt flag 7" "No interrupt,Interrupt" eventfld.long 0x08 6. " BFINTFL[6] ,CP A buffer full interrupt flag 6" "No interrupt,Interrupt" newline eventfld.long 0x08 5. " BFINTFL[5] ,CP B buffer full interrupt flag 5" "No interrupt,Interrupt" eventfld.long 0x08 4. " BFINTFL[4] ,CP A buffer full interrupt flag 4" "No interrupt,Interrupt" newline eventfld.long 0x08 3. " BFINTFL[3] ,CP B buffer full interrupt flag 3" "No interrupt,Interrupt" eventfld.long 0x08 2. " BFINTFL[2] ,CP A buffer full interrupt flag 2" "No interrupt,Interrupt" newline eventfld.long 0x08 1. " BFINTFL[1] ,CP B buffer full interrupt flag 1" "No interrupt,Interrupt" eventfld.long 0x08 0. " BFINTFL[0] ,CP A buffer full interrupt flag 0" "No interrupt,Interrupt" line.long 0x0C "BERINTFL,BER Interrupt Flag Register" eventfld.long 0x0C 15. " BERINTFL[15] ,CP B bus error interrupt flag 15" "No interrupt,Interrupt" eventfld.long 0x0C 14. " BERINTFL[14] ,CP A bus error interrupt flag 14" "No interrupt,Interrupt" newline eventfld.long 0x0C 13. " BERINTFL[13] ,CP B bus error interrupt flag 13" "No interrupt,Interrupt" eventfld.long 0x0C 12. " BERINTFL[12] ,CP A bus error interrupt flag 12" "No interrupt,Interrupt" newline eventfld.long 0x0C 11. " BERINTFL[11] ,CP B bus error interrupt flag 11" "No interrupt,Interrupt" eventfld.long 0x0C 10. " BERINTFL[10] ,CP A bus error interrupt flag 10" "No interrupt,Interrupt" newline eventfld.long 0x0C 9. " BERINTFL[9] ,CP B bus error interrupt flag 9" "No interrupt,Interrupt" eventfld.long 0x0C 8. " BERINTFL[8] ,CP A bus error interrupt flag 8" "No interrupt,Interrupt" newline eventfld.long 0x0C 7. " BERINTFL[7] ,CP B bus error interrupt flag 7" "No interrupt,Interrupt" eventfld.long 0x0C 6. " BERINTFL[6] ,CP A bus error interrupt flag 6" "No interrupt,Interrupt" newline eventfld.long 0x0C 5. " BERINTFL[5] ,CP B bus error interrupt flag 5" "No interrupt,Interrupt" eventfld.long 0x0C 4. " BERINTFL[4] ,CP A bus error interrupt flag 4" "No interrupt,Interrupt" newline eventfld.long 0x0C 3. " BERINTFL[3] ,CP B bus error interrupt flag 3" "No interrupt,Interrupt" eventfld.long 0x0C 2. " BERINTFL[2] ,CP A bus error interrupt flag 2" "No interrupt,Interrupt" newline eventfld.long 0x0C 1. " BERINTFL[1] ,CP B bus error interrupt flag 1" "No interrupt,Interrupt" eventfld.long 0x0C 0. " BERINTFL[0] ,CP A bus error interrupt flag 0" "No interrupt,Interrupt" line.long 0x10 "MP1S,Memory Protection 1 Start Address" line.long 0x14 "MP1E,Memory Protection 1 End Address" line.long 0x18 "DCTRL,Debug Control Register" sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")) rbitfld.long 0x18 24.--27. " CPNUM ,CP number" "CP A of DCP0,CP B of DCP0,CP A of DCP1,,,,,,,,,,,,CP A of DCP7,CP B of DCP7" elif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP") bitfld.long 0x18 24.--27. " CPNUM ,CP number" "CP A of DCP 0,CP B of DCP 0,CP A of DCP 1,CP B of DCP 1,CP A of DCP 2,CP B of DCP 2,CP A of DCP 3,CP B of DCP 3,CP A of DCP 4,CP B of DCP 4,CP A of DCP 5,CP B of DCP 5,CP A of DCP 6,CP B of DCP 6,CP A of DCP 7,CP B of DCP 7" else bitfld.long 0x18 24.--27. " CPNUM ,CP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline eventfld.long 0x18 16. " HTUDBGS ,HTU debug status" "Not detected,Detected" bitfld.long 0x18 0. " DBREN ,Debug request enable" "Disabled,Enabled" line.long 0x1C "WPR,Watch Point Register" line.long 0x20 "WMR,Watch Mask Register" rgroup.long 0x60++0x03 line.long 0x00 "ID,Module Identification Register" hexmask.long.byte 0x00 16.--23. 1. " CLASS ,Module class" hexmask.long.byte 0x00 8.--15. 1. " TYPE ,Subtype within a class" hexmask.long.byte 0x00 0.--7. 1. " REV ,Module revision number" group.long 0x64++0x07 line.long 0x0 "PCR,Parity Control Register" bitfld.long 0x00 16. " COPE , Continue on parity error" "Stopped,Continued" bitfld.long 0x00 8. " TEST ,Test" "Not mapped,Mapped" bitfld.long 0x00 0.--3. " PARITY_ENA ,Enable/disable parity checking" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" line.long 0x04 "PAR,Parity Address Register" eventfld.long 0x04 16. " PEFT ,Parity Error fault flag" "Not detected,Detected" hexmask.long.word 0x04 0.--8. 1. " PAOFF ,Parity error address offset" group.long 0x70++0x0B line.long 0x00 "MPCS,Memory Protection Control and Status Register" sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP") rbitfld.long 0x00 24.--27. " CPNUM0 ,CP number" "CP A of DCP 0,CP B of DCP 0,CP A of DCP 1,CP B of DCP 1,CP A of DCP 2,CP B of DCP 2,CP A of DCP 3,CP B of DCP 3,CP A of DCP 4,CP B of DCP 4,CP A of DCP 5,CP B of DCP 5,CP A of DCP 6,CP B of DCP 6,CP A of DCP 7,CP B of DCP 7" else bitfld.long 0x00 24.--27. " CPNUM0 ,CP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline eventfld.long 0x00 17. " MPEFT1 ,Memory protection error fault flag" "Not detected,Detected" eventfld.long 0x00 16. " MPEFT0 ,Memory protection error fault flag" "Not detected,Detected" newline sif (cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")) rbitfld.long 0x00 8.--11. " CPNUM1 ,CP number" "CP A of DCP0,CP B of DCP0,CP A of DCP1,,,,,,,,,,,,CP A of DCP7,CP B of DCP7" elif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP") rbitfld.long 0x00 8.--11. " CPNUM1 ,CP number" "CP A of DCP 0,CP B of DCP 0,CP A of DCP 1,CP B of DCP 1,CP A of DCP 2,CP B of DCP 2,CP A of DCP 3,CP B of DCP 3,CP A of DCP 4,CP B of DCP 4,CP A of DCP 5,CP B of DCP 5,CP A of DCP 6,CP B of DCP 6,CP A of DCP 7,CP B of DCP 7" else bitfld.long 0x00 8.--11. " CPNUM1 ,CP number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif newline bitfld.long 0x00 5. " INTENA01 ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 4. " ACCR01 ,Access rights HTU" "Allowed,Forbidden" newline bitfld.long 0x00 3. " REG01ENA ,Region enable" "Disabled,Enabled" bitfld.long 0x00 2. " INTENA0 ,Interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " ACCR ,Access rights HTU" "Allowed,Forbidden" newline bitfld.long 0x00 0. " REG0ENA ,Region enable" "Disabled,Enabled" line.long 0x04 "MP0S,Memory Protection Start Address Register" line.long 0x08 "MP0E,Memory Protection End Address Register" sif (cpuis("TMS570LS10106-PGE")||cpuis("TMS570LS10106-ZWT")||cpuis("TMS570LS10116-PGE")||cpuis("TMS570LS10116-ZWT")||cpuis("TMS570LS10206-PGE")||cpuis("TMS570LS10206-ZWT")||cpuis("TMS570LS10216-PGE")||cpuis("TMS570LS10216-ZWT")||cpuis("TMS570LS20206-PGE")||cpuis("TMS570LS20206-ZWT")||cpuis("TMS570LS20216-PGE")||cpuis("TMS570LS20216-ZWT")||cpuis("RM48L952-PGE")||cpuis("RM48L952-ZWT")||cpuis("RM48L950-PGE")||cpuis("RM48L950-ZWT")||cpuis("RM48L940-ZWT")||cpuis("RM48L940-PGE")||cpuis("RM48L930-ZWT")||cpuis("RM48L930-PGE")||cpuis("RM48L750-ZWT")||cpuis("RM48L750-PGE")||cpuis("RM48L740-ZWT")||cpuis("RM48L740-PGE")||cpuis("RM48L730-ZWT")||cpuis("RM48L730-PGE")||cpuis("RM48L550-PGE")||cpuis("RM48L540-ZWT")||cpuis("RM48L540-PGE")||cpuis("RM48L530-ZWT")||cpuis("RM48L530-PGE")||cpuis("RM46L852-PGE")||cpuis("RM46L852-ZWT")||cpuis("RM46L850-PGE")||cpuis("RM46L850-ZWT")||cpuis("RM46L840-ZWT")||cpuis("RM46L840-PGE")||cpuis("RM46L830-ZWT")||cpuis("RM46L830-PGE")||cpuis("RM46L450-ZWT")||cpuis("RM46L450-PGE")||cpuis("RM46L440-ZWT")||cpuis("RM46L440-PGE")||cpuis("RM46L430-ZWT")||cpuis("RM46L430-PGE")||cpuis("RM42L432")||cpuis("RM48L550-ZWT")||cpuis("TMS570LC4357")||cpuis("TMS570LS0332")||cpuis("TMS570LS0432")||cpuis("TMS570LS1114*")||cpuis("TMS570LS1115*")||cpuis("TMS570LS1224*")||cpuis("TMS570LS1225*")||cpuis("TMS570LS1227*")||cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*")||cpuis("TMS570LS3137-EP")) tree "Double Control Packet Configuration Memory" base ad:0xFF4C0000 sif !cpuis("TMS570LS0714*")&&!cpuis("TMS570LS0914*")&&!cpuis("RM46L852*")&&!cpuis("TMS570LS3137-EP") group.long 0x00++0xF line.long 0x00 "IFADDRA,Initial main memory address Control Packet A" line.long 0x04 "IFADDRB,Initial main memory address Control Packet B" line.long 0x08 "IHADDRCT,Initial NHET address and control" bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET" bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit" newline bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (increment value)" "16 bytes,8 bytes" bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant" newline bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch" bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch" newline hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address" line.long 0x0C "ITCOUNT,Initial transfer count" bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count" group.long 0x100++0xB line.long 0x00 "CFADDRA,Current main memory address Control Packet A" line.long 0x04 "CFADDRB,Current main memory address Control Packet B" line.long 0x08 "CFCOUNT,Current frame count" hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A" hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B" else width 15. group.long 0x0++0x0F "DCP0" line.long 0x00 "DCP0IFADDRA,DCP0 Initial main memory address Control Packet A" line.long 0x04 "DCP0IFADDRB,DCP0 Initial main memory address Control Packet B" line.long 0x08 "DCP0IHADDRCT,DCP0 Initial NHET address and control" bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET" bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit" newline bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes" bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant" newline bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch" bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch" newline hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address" line.long 0x0C "DCP0ITCOUNT,DCP0 Initial transfer count" bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count" group.long (0x0+0x100)++0xB line.long 0x00 "DCP0CFADDRA,DCP0 Current main memory address control packet A" line.long 0x04 "DCP0CFADDRB,DCP0 Current main memory address control packet B" line.long 0x08 "DCP0CFCOUNT,DCP0 Current frame count" hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A" hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B" group.long 0x10++0x0F "DCP1" line.long 0x00 "DCP1IFADDRA,DCP1 Initial main memory address Control Packet A" line.long 0x04 "DCP1IFADDRB,DCP1 Initial main memory address Control Packet B" line.long 0x08 "DCP1IHADDRCT,DCP1 Initial NHET address and control" bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET" bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit" newline bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes" bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant" newline bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch" bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch" newline hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address" line.long 0x0C "DCP1ITCOUNT,DCP1 Initial transfer count" bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count" group.long (0x10+0x100)++0xB line.long 0x00 "DCP1CFADDRA,DCP1 Current main memory address control packet A" line.long 0x04 "DCP1CFADDRB,DCP1 Current main memory address control packet B" line.long 0x08 "DCP1CFCOUNT,DCP1 Current frame count" hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A" hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B" group.long 0x20++0x0F "DCP2" line.long 0x00 "DCP2IFADDRA,DCP2 Initial main memory address Control Packet A" line.long 0x04 "DCP2IFADDRB,DCP2 Initial main memory address Control Packet B" line.long 0x08 "DCP2IHADDRCT,DCP2 Initial NHET address and control" bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET" bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit" newline bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes" bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant" newline bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch" bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch" newline hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address" line.long 0x0C "DCP2ITCOUNT,DCP2 Initial transfer count" bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count" group.long (0x20+0x100)++0xB line.long 0x00 "DCP2CFADDRA,DCP2 Current main memory address control packet A" line.long 0x04 "DCP2CFADDRB,DCP2 Current main memory address control packet B" line.long 0x08 "DCP2CFCOUNT,DCP2 Current frame count" hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A" hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B" group.long 0x30++0x0F "DCP3" line.long 0x00 "DCP3IFADDRA,DCP3 Initial main memory address Control Packet A" line.long 0x04 "DCP3IFADDRB,DCP3 Initial main memory address Control Packet B" line.long 0x08 "DCP3IHADDRCT,DCP3 Initial NHET address and control" bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET" bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit" newline bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes" bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant" newline bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch" bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch" newline hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address" line.long 0x0C "DCP3ITCOUNT,DCP3 Initial transfer count" bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count" group.long (0x30+0x100)++0xB line.long 0x00 "DCP3CFADDRA,DCP3 Current main memory address control packet A" line.long 0x04 "DCP3CFADDRB,DCP3 Current main memory address control packet B" line.long 0x08 "DCP3CFCOUNT,DCP3 Current frame count" hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A" hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B" group.long 0x40++0x0F "DCP4" line.long 0x00 "DCP4IFADDRA,DCP4 Initial main memory address Control Packet A" line.long 0x04 "DCP4IFADDRB,DCP4 Initial main memory address Control Packet B" line.long 0x08 "DCP4IHADDRCT,DCP4 Initial NHET address and control" bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET" bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit" newline bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes" bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant" newline bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch" bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch" newline hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address" line.long 0x0C "DCP4ITCOUNT,DCP4 Initial transfer count" bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count" group.long (0x40+0x100)++0xB line.long 0x00 "DCP4CFADDRA,DCP4 Current main memory address control packet A" line.long 0x04 "DCP4CFADDRB,DCP4 Current main memory address control packet B" line.long 0x08 "DCP4CFCOUNT,DCP4 Current frame count" hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A" hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B" group.long 0x50++0x0F "DCP5" line.long 0x00 "DCP5IFADDRA,DCP5 Initial main memory address Control Packet A" line.long 0x04 "DCP5IFADDRB,DCP5 Initial main memory address Control Packet B" line.long 0x08 "DCP5IHADDRCT,DCP5 Initial NHET address and control" bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET" bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit" newline bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes" bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant" newline bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch" bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch" newline hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address" line.long 0x0C "DCP5ITCOUNT,DCP5 Initial transfer count" bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count" group.long (0x50+0x100)++0xB line.long 0x00 "DCP5CFADDRA,DCP5 Current main memory address control packet A" line.long 0x04 "DCP5CFADDRB,DCP5 Current main memory address control packet B" line.long 0x08 "DCP5CFCOUNT,DCP5 Current frame count" hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A" hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B" group.long 0x60++0x0F "DCP6" line.long 0x00 "DCP6IFADDRA,DCP6 Initial main memory address Control Packet A" line.long 0x04 "DCP6IFADDRB,DCP6 Initial main memory address Control Packet B" line.long 0x08 "DCP6IHADDRCT,DCP6 Initial NHET address and control" bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET" bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit" newline bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes" bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant" newline bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch" bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch" newline hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address" line.long 0x0C "DCP6ITCOUNT,DCP6 Initial transfer count" bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count" group.long (0x60+0x100)++0xB line.long 0x00 "DCP6CFADDRA,DCP6 Current main memory address control packet A" line.long 0x04 "DCP6CFADDRB,DCP6 Current main memory address control packet B" line.long 0x08 "DCP6CFCOUNT,DCP6 Current frame count" hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A" hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B" group.long 0x70++0x0F "DCP7" line.long 0x00 "DCP7IFADDRA,DCP7 Initial main memory address Control Packet A" line.long 0x04 "DCP7IFADDRB,DCP7 Initial main memory address Control Packet B" line.long 0x08 "DCP7IHADDRCT,DCP7 Initial NHET address and control" bitfld.long 0x08 23. " DIR ,Direction of transfer (read->write)" "NHET->Main,Main->NHET" bitfld.long 0x08 22. " SIZE ,Size of transferred data" "32-bit,64-bit" newline bitfld.long 0x08 21. " ADDMH ,Addressing mode NHET address (Increment value)" "16 bytes,8 bytes" bitfld.long 0x08 20. " ADDMF ,Addressing mode main memory address" "Post-increment,Constant" newline bitfld.long 0x08 18.--19. " TMBA ,Transfer mode for buffer A" "One Shot,Circular,Auto Switch,Auto Switch" bitfld.long 0x08 16.--17. " TMBB ,Transfer mode for buffer B" "One Shot,Circular,Auto Switch,Auto Switch" newline hexmask.long.word 0x08 2.--12. 0x4 " IHADDR ,Initial NHET address" line.long 0x0C "DCP7ITCOUNT,DCP7 Initial transfer count" bitfld.long 0x0C 16.--20. " IETCOUNT ,Initial element transfer count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.byte 0x0C 0.--7. 1. " IFTCOUNT ,Initial frame transfer count" group.long (0x70+0x100)++0xB line.long 0x00 "DCP7CFADDRA,DCP7 Current main memory address control packet A" line.long 0x04 "DCP7CFADDRB,DCP7 Current main memory address control packet B" line.long 0x08 "DCP7CFCOUNT,DCP7 Current frame count" hexmask.long.byte 0x08 16.--23. 1. " CFTCTA ,Current frame transfer count for CP A" hexmask.long.byte 0x08 0.--7. 1. " CFTCTB ,Current frame transfer count for CP B" endif tree.end endif sif cpuis("TMS570LS0232")||cpuis("TMS570LS0714*")||cpuis("TMS570LS0914*") endian.le endif width 0x0B tree.end endif tree.end tree "GIO (General-Purpose Input/Output)" sif (cpu()=="RM42L432") tree "GIO" base ad:0xFFF7BC00 width 8. textline " " sif (cpu()=="RM42L432"||cpu()=="TMS570LC4357"||cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")||cpuis("TMS570LS0232")||cpuis("TMS570LS3137-EP")) group.long 0x00++0x03 line.long 0x00 "GCR0,Global Control Register" bitfld.long 0x00 0. " GIOGCR0 ,GIO Global Control" "Reset,Normal" else group.long 0x00++0x07 line.long 0x00 "GCR0,Global Control Register" bitfld.long 0x00 0. " GIOGCR0 ,GIO Global Control" "Reset,Normal" line.long 0x04 "PWDN,Power Down" endif tree "GIO Interrupt Registers" group.long 0x08++0x07 line.long 0x00 "INTDET,Interrupt Detect" sif (cpu()!="RM42L432"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")) sif (cpu()!="TMS570LC4357") bitfld.long 0x00 31. " INTDET_3_7 ,GIOD7 Interrupt Detection Select" "Falling/rising,Both" bitfld.long 0x00 30. " INTDET_3_6 ,GIOD6 Interrupt Detection Select" "Falling/rising,Both" textline " " bitfld.long 0x00 29. " INTDET_3_5 ,GIOD5 Interrupt Detection Select" "Falling/rising,Both" bitfld.long 0x00 28. " INTDET_3_4 ,GIOD4 Interrupt Detection Select" "Falling/rising,Both" textline " " bitfld.long 0x00 27. " INTDET_3_3 ,GIOD3 Interrupt Detection Select" "Falling/rising,Both" bitfld.long 0x00 26. " INTDET_3_2 ,GIOC2 Interrupt Detection Select" "Falling/rising,Both" textline " " bitfld.long 0x00 25. " INTDET_3_1 ,GIOC1 Interrupt Detection Select" "Falling/rising,Both" bitfld.long 0x00 24. " INTDET_3_0 ,GIOC0 Interrupt Detection Select" "Falling/rising,Both" textline " " bitfld.long 0x00 23. " INTDET_2_7 ,GIOC7 Interrupt Detection Select" "Falling/rising,Both" bitfld.long 0x00 22. " INTDET_2_6 ,GIOC6 Interrupt Detection Select" "Falling/rising,Both" textline " " bitfld.long 0x00 21. " INTDET_2_5 ,GIOC5 Interrupt Detection Select" "Falling/rising,Both" bitfld.long 0x00 20. " INTDET_2_4 ,GIOC4 Interrupt Detection Select" "Falling/rising,Both" textline " " bitfld.long 0x00 19. " INTDET_2_3 ,GIOC3 Interrupt Detection Select" "Falling/rising,Both" bitfld.long 0x00 18. " INTDET_2_2 ,GIOC2 Interrupt Detection Select" "Falling/rising,Both" textline " " bitfld.long 0x00 17. " INTDET_2_1 ,GIOC1 Interrupt Detection Select" "Falling/rising,Both" bitfld.long 0x00 16. " INTDET_2_0 ,GIOC0 Interrupt Detection Select" "Falling/rising,Both" textline " " endif bitfld.long 0x00 15. " INTDET_1_7 ,GIOB7 Interrupt Detection Select" "Falling/rising,Both" bitfld.long 0x00 14. " INTDET_1_6 ,GIOB6 Interrupt Detection Select" "Falling/rising,Both" textline " " bitfld.long 0x00 13. " INTDET_1_5 ,GIOB5 Interrupt Detection Select" "Falling/rising,Both" bitfld.long 0x00 12. " INTDET_1_4 ,GIOB4 Interrupt Detection Select" "Falling/rising,Both" textline " " bitfld.long 0x00 11. " INTDET_1_3 ,GIOB3 Interrupt Detection Select" "Falling/rising,Both" bitfld.long 0x00 10. " INTDET_1_2 ,GIOB2 Interrupt Detection Select" "Falling/rising,Both" textline " " bitfld.long 0x00 9. " INTDET_1_1 ,GIOB1 Interrupt Detection Select" "Falling/rising,Both" bitfld.long 0x00 8. " INTDET_1_0 ,GIOB0 Interrupt Detection Select" "Falling/rising,Both" textline " " endif bitfld.long 0x00 7. " INTDET_0_7 ,GIOA7 Interrupt Detection Select" "Falling/rising,Both" bitfld.long 0x00 6. " INTDET_0_6 ,GIOA6 Interrupt Detection Select" "Falling/rising,Both" textline " " bitfld.long 0x00 5. " INTDET_0_5 ,GIOA5 Interrupt Detection Select" "Falling/rising,Both" bitfld.long 0x00 4. " INTDET_0_4 ,GIOA4 Interrupt Detection Select" "Falling/rising,Both" textline " " bitfld.long 0x00 3. " INTDET_0_3 ,GIOA3 Interrupt Detection Select" "Falling/rising,Both" bitfld.long 0x00 2. " INTDET_0_2 ,GIOA2 Interrupt Detection Select" "Falling/rising,Both" textline " " bitfld.long 0x00 1. " INTDET_0_1 ,GIOA1 Interrupt Detection Select" "Falling/rising,Both" bitfld.long 0x00 0. " INTDET_0_0 ,GIOA0 Interrupt Detection Select" "Falling/rising,Both" line.long 0x04 "POL,Interrupt Polarity" sif (cpu()!="RM42L432"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")) sif (cpu()!="TMS570LC4357") bitfld.long 0x04 31. " GIOPOL_3_7 ,GIOD7 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" bitfld.long 0x04 30. " GIOPOL_3_6 ,GIOD6 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" textline " " bitfld.long 0x04 29. " GIOPOL_3_5 ,GIOD5 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" bitfld.long 0x04 28. " GIOPOL_3_4 ,GIOD4 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" textline " " bitfld.long 0x04 27. " GIOPOL_3_3 ,GIOD3 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" bitfld.long 0x04 26. " GIOPOL_3_2 ,GIOD2 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" textline " " bitfld.long 0x04 25. " GIOPOL_3_1 ,GIOD1 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" bitfld.long 0x04 24. " GIOPOL_3_0 ,GIOD0 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" textline " " bitfld.long 0x04 23. " GIOPOL_2_7 ,GIOC7 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" bitfld.long 0x04 22. " GIOPOL_2_6 ,GIOC6 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" textline " " bitfld.long 0x04 21. " GIOPOL_2_5 ,GIOC5 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" bitfld.long 0x04 20. " GIOPOL_2_4 ,GIOC4 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" textline " " bitfld.long 0x04 19. " GIOPOL_2_3 ,GIOC3 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" bitfld.long 0x04 18. " GIOPOL_2_2 ,GIOC2 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" textline " " bitfld.long 0x04 17. " GIOPOL_2_1 ,GIOC1 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" bitfld.long 0x04 16. " GIOPOL_2_0 ,GIOC0 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" textline " " endif bitfld.long 0x04 15. " GIOPOL_1_7 ,GIOB7 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" bitfld.long 0x04 14. " GIOPOL_1_6 ,GIOB6 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" textline " " bitfld.long 0x04 13. " GIOPOL_1_5 ,GIOB5 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" bitfld.long 0x04 12. " GIOPOL_1_4 ,GIOB4 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" textline " " bitfld.long 0x04 11. " GIOPOL_1_3 ,GIOB3 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" bitfld.long 0x04 10. " GIOPOL_1_2 ,GIOB2 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" textline " " bitfld.long 0x04 9. " GIOPOL_1_1 ,GIOB1 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" bitfld.long 0x04 8. " GIOPOL_1_0 ,GIOB0 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" textline " " endif bitfld.long 0x04 7. " GIOPOL_0_7 ,GIOA7 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" bitfld.long 0x04 6. " GIOPOL_0_6 ,GIOA6 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" textline " " bitfld.long 0x04 5. " GIOPOL_0_5 ,GIOA5 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" bitfld.long 0x04 4. " GIOPOL_0_4 ,GIOA4 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" textline " " bitfld.long 0x04 3. " GIOPOL_0_3 ,GIOA3 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" bitfld.long 0x04 2. " GIOPOL_0_2 ,GIOA2 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" textline " " bitfld.long 0x04 1. " GIOPOL_0_1 ,GIOA1 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" bitfld.long 0x04 0. " GIOPOL_0_0 ,GIOA0 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" tree.end tree "GIO Interrupt Enable Registers" width 13. group.long 0x10++0x03 line.long 0x00 "ENA_set/clr,Interrupt Enable Set/Clr" sif (cpu()!="RM42L432"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")) sif (cpu()!="TMS570LC4357") setclrfld.long 0x00 31. 0x00 31. 0x04 31. " GIOENA_3_7 ,GIOD7 Interrupt Enable" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x04 30. " GIOENA_3_6 ,GIOD6 Interrupt Enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 29. 0x00 29. 0x04 29. " GIOENA_3_5 ,GIOD5 Interrupt Enable" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x04 28. " GIOENA_3_4 ,GIOD4 Interrupt Enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. 0x00 27. 0x04 27. " GIOENA_3_3 ,GIOD3 Interrupt Enable" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x04 26. " GIOENA_3_2 ,GIOD2 Interrupt Enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x04 25. " GIOENA_3_1 ,GIOD1 Interrupt Enable" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x04 24. " GIOENA_3_0 ,GIOD0 Interrupt Enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. 0x00 23. 0x04 23. " GIOENA_2_7 ,GIOC7 Interrupt Enable" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x04 22. " GIOENA_2_6 ,GIOC6 Interrupt Enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. 0x00 21. 0x04 21. " GIOENA_2_5 ,GIOC5 Interrupt Enable" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x04 20. " GIOENA_2_4 ,GIOC4 Interrupt Enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x04 19. " GIOENA_2_3 ,GIOC3 Interrupt Enable" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x04 18. " GIOENA_2_2 ,GIOC2 Interrupt Enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. 0x00 17. 0x04 17. " GIOENA_2_1 ,GIOC1 Interrupt Enable" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x04 16. " GIOENA_2_0 ,GIOC0 Interrupt Enable" "Disabled,Enabled" textline " " endif setclrfld.long 0x00 15. 0x00 15. 0x04 15. " GIOENA_1_7 ,GIOB7 Interrupt Enable" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x04 14. " GIOENA_1_6 ,GIOB6 Interrupt Enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x04 13. " GIOENA_1_5 ,GIOB5 Interrupt Enable" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x04 12. " GIOENA_1_4 ,GIOB4 Interrupt Enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 11. 0x00 11. 0x04 11. " GIOENA_1_3 ,GIOB3 Interrupt Enable" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x04 10. " GIOENA_1_2 ,GIOB2 Interrupt Enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. 0x00 9. 0x04 9. " GIOENA_1_1 ,GIOB1 Interrupt Enable" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x04 8. " GIOENA_1_0 ,GIOB0 Interrupt Enable" "Disabled,Enabled" textline " " endif setclrfld.long 0x00 7. 0x00 7. 0x04 7. " GIOENA_0_7 ,GIOA7 Interrupt Enable" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x04 6. " GIOENA_0_6 ,GIOA6 Interrupt Enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x00 5. 0x04 5. " GIOENA_0_5 ,GIOA5 Interrupt Enable" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x04 4. " GIOENA_0_4 ,GIOA4 Interrupt Enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. 0x00 3. 0x04 3. " GIOENA_0_3 ,GIOA3 Interrupt Enable" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x04 2. " GIOENA_0_2 ,GIOA2 Interrupt Enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x04 1. " GIOENA_0_1 ,GIOA1 Interrupt Enable" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " GIOENA_0_0 ,GIOA0 Interrupt Enable" "Disabled,Enabled" tree.end tree "GIO Interrupt Priority Registers" group.long 0x18++0x03 line.long 0x00 "LVL_set/clr,Interrupt Priority Set/Clr" sif (cpu()!="RM42L432"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")) sif (cpu()!="TMS570LC4357") setclrfld.long 0x00 31. 0x00 31. 0x00 31. " GIOLVL_3_7 ,GIOD7 High Priority Interrupt" "Low-level,High-level" setclrfld.long 0x00 30. 0x00 30. 0x00 30. " GIOLVL_3_6 ,GIOD6 High Priority Interrupt" "Low-level,High-level" textline " " setclrfld.long 0x00 29. 0x00 29. 0x00 29. " GIOLVL_3_5 ,GIOD5 High Priority Interrupt" "Low-level,High-level" setclrfld.long 0x00 28. 0x00 28. 0x00 28. " GIOLVL_3_4 ,GIOD4 High Priority Interrupt" "Low-level,High-level" textline " " setclrfld.long 0x00 27. 0x00 27. 0x00 27. " GIOLVL_3_3 ,GIOD3 High Priority Interrupt" "Low-level,High-level" setclrfld.long 0x00 26. 0x00 26. 0x00 26. " GIOLVL_3_2 ,GIOD2 High Priority Interrupt" "Low-level,High-level" textline " " setclrfld.long 0x00 25. 0x00 25. 0x00 25. " GIOLVL_3_1 ,GIOD1 High Priority Interrupt" "Low-level,High-level" setclrfld.long 0x00 24. 0x00 24. 0x00 24. " GIOLVL_3_0 ,GIOD0 High Priority Interrupt" "Low-level,High-level" textline " " setclrfld.long 0x00 23. 0x00 23. 0x00 23. " GIOLVL_2_7 ,GIOC7 High Priority Interrupt" "Low-level,High-level" setclrfld.long 0x00 22. 0x00 22. 0x00 22. " GIOLVL_2_6 ,GIOC6 High Priority Interrupt" "Low-level,High-level" textline " " setclrfld.long 0x00 21. 0x00 21. 0x00 21. " GIOLVL_2_5 ,GIOC5 High Priority Interrupt" "Low-level,High-level" setclrfld.long 0x00 20. 0x00 20. 0x00 20. " GIOLVL_2_4 ,GIOC4 High Priority Interrupt" "Low-level,High-level" textline " " setclrfld.long 0x00 19. 0x00 19. 0x00 19. " GIOLVL_2_3 ,GIOC3 High Priority Interrupt" "Low-level,High-level" setclrfld.long 0x00 18. 0x00 18. 0x00 18. " GIOLVL_2_2 ,GIOC2 High Priority Interrupt" "Low-level,High-level" textline " " setclrfld.long 0x00 17. 0x00 17. 0x00 17. " GIOLVL_2_1 ,GIOC1 High Priority Interrupt" "Low-level,High-level" setclrfld.long 0x00 16. 0x00 16. 0x00 16. " GIOLVL_2_0 ,GIOC0 High Priority Interrupt" "Low-level,High-level" textline " " endif setclrfld.long 0x00 15. 0x00 15. 0x00 15. " GIOLVL_1_7 ,GIOB7 High Priority Interrupt" "Low-level,High-level" setclrfld.long 0x00 14. 0x00 14. 0x00 14. " GIOLVL_1_6 ,GIOB6 High Priority Interrupt" "Low-level,High-level" textline " " setclrfld.long 0x00 13. 0x00 13. 0x00 13. " GIOLVL_1_5 ,GIOB5 High Priority Interrupt" "Low-level,High-level" setclrfld.long 0x00 12. 0x00 12. 0x00 12. " GIOLVL_1_4 ,GIOB4 High Priority Interrupt" "Low-level,High-level" textline " " setclrfld.long 0x00 11. 0x00 11. 0x00 11. " GIOLVL_1_3 ,GIOB3 High Priority Interrupt" "Low-level,High-level" setclrfld.long 0x00 10. 0x00 10. 0x00 10. " GIOLVL_1_2 ,GIOB2 High Priority Interrupt" "Low-level,High-level" textline " " setclrfld.long 0x00 9. 0x00 9. 0x00 9. " GIOLVL_1_1 ,GIOB1 High Priority Interrupt" "Low-level,High-level" setclrfld.long 0x00 8. 0x00 8. 0x00 8. " GIOLVL_1_0 ,GIOB0 High Priority Interrupt" "Low-level,High-level" textline " " endif setclrfld.long 0x00 7. 0x00 7. 0x00 7. " GIOLVL_0_7 ,GIOA7 High Priority Interrupt" "Low-level,High-level" setclrfld.long 0x00 6. 0x00 6. 0x00 6. " GIOLVL_0_6 ,GIOA6 High Priority Interrupt" "Low-level,High-level" textline " " setclrfld.long 0x00 5. 0x00 5. 0x00 5. " GIOLVL_0_5 ,GIOA5 High Priority Interrupt" "Low-level,High-level" setclrfld.long 0x00 4. 0x00 4. 0x00 4. " GIOLVL_0_4 ,GIOA4 High Priority Interrupt" "Low-level,High-level" textline " " setclrfld.long 0x00 3. 0x00 3. 0x00 3. " GIOLVL_0_3 ,GIOA3 High Priority Interrupt" "Low-level,High-level" setclrfld.long 0x00 2. 0x00 2. 0x00 2. " GIOLVL_0_2 ,GIOA2 High Priority Interrupt" "Low-level,High-level" textline " " setclrfld.long 0x00 1. 0x00 1. 0x00 1. " GIOLVL_0_1 ,GIOA1 High Priority Interrupt" "Low-level,High-level" setclrfld.long 0x00 0. 0x00 0. 0x00 0. " GIOLVL_0_0 ,GIOA0 High Priority Interrupt" "Low-level,High-level" tree.end textline " " width 8. group.long 0x20++0x03 line.long 0x00 "FLG,Interrupt Flag" sif (cpu()!="RM42L432"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")) sif (cpu()!="TMS570LC4357") eventfld.long 0x00 31. " GIOFLG_3_7 ,GIOD7 Flag" "Not occurred,Occurred" eventfld.long 0x00 30. " GIOFLG_3_6 ,GIOD6 Flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 29. " GIOFLG_3_5 ,GIOD5 Flag" "Not occurred,Occurred" eventfld.long 0x00 28. " GIOFLG_3_4 ,GIOD4 Flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 27. " GIOFLG_3_3 ,GIOD3 Flag" "Not occurred,Occurred" eventfld.long 0x00 26. " GIOFLG_3_2 ,GIOD2 Flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 25. " GIOFLG_3_1 ,GIOD1 Flag" "Not occurred,Occurred" eventfld.long 0x00 24. " GIOFLG_3_0 ,GIOD0 Flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 23. " GIOFLG_2_7 ,GIOC7 Flag" "Not occurred,Occurred" eventfld.long 0x00 22. " GIOFLG_2_6 ,GIOC6 Flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 21. " GIOFLG_2_5 ,GIOC5 Flag" "Not occurred,Occurred" eventfld.long 0x00 20. " GIOFLG_2_4 ,GIOC4 Flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 19. " GIOFLG_2_3 ,GIOC3 Flag" "Not occurred,Occurred" eventfld.long 0x00 18. " GIOFLG_2_2 ,GIOC2 Flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 17. " GIOFLG_2_1 ,GIOC1 Flag" "Not occurred,Occurred" eventfld.long 0x00 16. " GIOFLG_2_0 ,GIOC0 Flag" "Not occurred,Occurred" textline " " endif eventfld.long 0x00 15. " GIOFLG_1_7 ,GIOB7 Flag" "Not occurred,Occurred" eventfld.long 0x00 14. " GIOFLG_1_6 ,GIOB6 Flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 13. " GIOFLG_1_5 ,GIOB5 Flag" "Not occurred,Occurred" eventfld.long 0x00 12. " GIOFLG_1_4 ,GIOB4 Flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 11. " GIOFLG_1_3 ,GIOB3 Flag" "Not occurred,Occurred" eventfld.long 0x00 10. " GIOFLG_1_2 ,GIOB2 Flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 9. " GIOFLG_1_1 ,GIOB1 Flag" "Not occurred,Occurred" eventfld.long 0x00 8. " GIOFLG_1_0 ,GIOB0 Flag" "Not occurred,Occurred" textline " " endif eventfld.long 0x00 7. " GIOFLG_0_7 ,GIOA7 Flag" "Not occurred,Occurred" eventfld.long 0x00 6. " GIOFLG_0_6 ,GIOA6 Flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 5. " GIOFLG_0_5 ,GIOA5 Flag" "Not occurred,Occurred" eventfld.long 0x00 4. " GIOFLG_0_4 ,GIOA4 Flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 3. " GIOFLG_0_3 ,GIOA3 Flag" "Not occurred,Occurred" eventfld.long 0x00 2. " GIOFLG_0_2 ,GIOA2 Flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 1. " GIOFLG_0_1 ,GIOA1 Flag" "Not occurred,Occurred" eventfld.long 0x00 0. " GIOFLG_0_0 ,GIOA0 Flag" "Not occurred,Occurred" sif !cpuis("TMS570LS3137-EP") hgroup.long 0x24++0x03 hide.long 0x00 "OFFA,Offset A" in else hgroup.long 0x24++0x07 hide.long 0x00 "OFF1,Offset Register 1" in hide.long 0x04 "OFF2,Offset B register" in endif sif !cpuis("TMS570LS3137-EP") sif (cpu()!="TMS570LC4357"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")) rgroup.long 0x2C++0x03 line.long 0x00 "EMUA,Emulation A" bitfld.long 0x00 0.--5. " GIOEMUA ,GIO Offset A" "No interrupt,Interrupt 0,Interrupt 1,Interrupt 2,Interrupt 3,Interrupt 4,Interrupt 5,Interrupt 6,Interrupt 7,Interrupt 8,Interrupt 9,Interrupt 10,Interrupt 11,Interrupt 12,Interrupt 13,Interrupt 14,Interrupt 15,Interrupt 16,Interrupt 17,Interrupt 18,Interrupt 19,Interrupt 20,Interrupt 21,Interrupt 22,Interrupt 23,Interrupt 24,Interrupt 25,Interrupt 26,Interrupt 27,Interrupt 28,Interrupt 29,Interrupt 30,Interrupt 31,?..." elif (cpu()==("TMS570LS0332")||cpu()==("TMS570LS0432")) rgroup.long 0x2C++0x03 line.long 0x00 "EMUA,Emulation A" bitfld.long 0x00 0.--5. " GIOEMUA ,GIO Offset A" "No interrupt,Interrupt 0,Interrupt 1,Interrupt 2,Interrupt 3,Interrupt 4,Interrupt 5,Interrupt 6,Interrupt 7,?..." else rgroup.long 0x2C++0x03 line.long 0x00 "EMUA,Emulation A" bitfld.long 0x00 0.--5. " GIOEMUA ,GIO Offset A" "No interrupt,Interrupt 0,Interrupt 1,Interrupt 2,Interrupt 3,Interrupt 4,Interrupt 5,Interrupt 6,Interrupt 7,Interrupt 8,Interrupt 9,Interrupt 10,Interrupt 11,Interrupt 12,Interrupt 13,Interrupt 14,Interrupt 15,Interrupt 16,?..." endif sif (cpu()!="RM42L432"&&cpu()!=("TMS570LS0332")&&cpu()!=("TMS570LS0432")) hgroup.long 0x28++0x03 hide.long 0x00 "OFFB,Offset B" in sif (cpu()!="TMS570LC4357") rgroup.long 0x30++0x03 line.long 0x00 "EMUB,Emulation B" bitfld.long 0x00 0.--5. " GIOEMUB ,GIO Offset B" "No interrupt,Interrupt 0,Interrupt 1,Interrupt 2,Interrupt 3,Interrupt 4,Interrupt 5,Interrupt 6,Interrupt 7,Interrupt 8,Interrupt 9,Interrupt 10,Interrupt 11,Interrupt 12,Interrupt 13,Interrupt 14,Interrupt 15,Interrupt 16,Interrupt 17,Interrupt 18,Interrupt 19,Interrupt 20,Interrupt 21,Interrupt 22,Interrupt 23,Interrupt 24,Interrupt 25,Interrupt 26,Interrupt 27,Interrupt 28,Interrupt 29,Interrupt 30,Interrupt 31,?..." else rgroup.long 0x30++0x03 line.long 0x00 "EMUB,Emulation B" bitfld.long 0x00 0.--5. " GIOEMUB ,GIO Offset B" "No interrupt,Interrupt 0,Interrupt 1,Interrupt 2,Interrupt 3,Interrupt 4,Interrupt 5,Interrupt 6,Interrupt 7,Interrupt 8,Interrupt 9,Interrupt 10,Interrupt 11,Interrupt 12,Interrupt 13,Interrupt 14,Interrupt 15,Interrupt 16,?..." endif endif else rgroup.long 0x2C++0x07 line.long 0x00 "EMU1,Emulation A Register" bitfld.long 0x00 0.--5. " GIOEMUA ,GIO Offset A" "No interrupt,Interrupt 0,Interrupt 1,Interrupt 2,Interrupt 3,Interrupt 4,Interrupt 5,Interrupt 6,Interrupt 7,Interrupt 8,Interrupt 9,Interrupt 10,Interrupt 11,Interrupt 12,Interrupt 13,Interrupt 14,Interrupt 15,Interrupt 16,Interrupt 17,Interrupt 18,Interrupt 19,Interrupt 20,Interrupt 21,Interrupt 22,Interrupt 23,Interrupt 24,Interrupt 25,Interrupt 26,Interrupt 27,Interrupt 28,Interrupt 29,Interrupt 30,Interrupt 31,?..." line.long 0x04 "EMU2,Emulation B Register" bitfld.long 0x04 0.--5. " GIOEMUA ,GIO Offset A" "No interrupt,Interrupt 0,Interrupt 1,Interrupt 2,Interrupt 3,Interrupt 4,Interrupt 5,Interrupt 6,Interrupt 7,Interrupt 8,Interrupt 9,Interrupt 10,Interrupt 11,Interrupt 12,Interrupt 13,Interrupt 14,Interrupt 15,Interrupt 16,Interrupt 17,Interrupt 18,Interrupt 19,Interrupt 20,Interrupt 21,Interrupt 22,Interrupt 23,Interrupt 24,Interrupt 25,Interrupt 26,Interrupt 27,Interrupt 28,Interrupt 29,Interrupt 30,Interrupt 31,?..." endif width 0xB tree.end tree "GIOA" base ad:0xFFF7BC00 width 9. rgroup.long 0x34++0x07 line.long 0x0 "DIR,Data Direction GIOA" bitfld.long 0x00 7. " GIODIR7 ,GIO Data Direction 7" "Input,Output" bitfld.long 0x00 6. " GIODIR6 ,GIO Data Direction 6" "Input,Output" textline " " bitfld.long 0x00 5. " GIODIR5 ,GIO Data Direction 5" "Input,Output" bitfld.long 0x00 4. " GIODIR4 ,GIO Data Direction 4" "Input,Output" textline " " bitfld.long 0x00 3. " GIODIR3 ,GIO Data Direction 3" "Input,Output" bitfld.long 0x00 2. " GIODIR2 ,GIO Data Direction 2" "Input,Output" textline " " bitfld.long 0x00 1. " GIODIR1 ,GIO Data Direction 1" "Input,Output" bitfld.long 0x00 0. " GIODIR0 ,GIO Data Direction 0" "Input,Output" line.long 0x04 "DIN,Data Input GIOA" bitfld.long 0x04 7. " GIODIN7 ,GIO Data Input 7" "Low,High" bitfld.long 0x04 6. " GIODIN6 ,GIO Data Input 6" "Low,High" bitfld.long 0x04 5. " GIODIN5 ,GIO Data Input 5" "Low,High" bitfld.long 0x04 4. " GIODIN4 ,GIO Data Input 4" "Low,High" textline " " bitfld.long 0x04 3. " GIODIN3 ,GIO Data Input 3" "Low,High" bitfld.long 0x04 2. " GIODIN2 ,GIO Data Input 2" "Low,High" bitfld.long 0x04 1. " GIODIN1 ,GIO Data Input 1" "Low,High" bitfld.long 0x04 0. " GIODIN0 ,GIO Data Input 0" "Low,High" group.long 0x3C++0x03 line.long 0x00 "DOUT,Data Output GIOA" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " GIODOUT7_set/clr ,GIO Data Output 7" "Low,High" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " GIODOUT6_set/clr ,GIO Data Output 6" "Low,High" textline " " setclrfld.long 0x00 5. 0x04 5. 0x08 5. " GIODOUT5_set/clr ,GIO Data Output 5" "Low,High" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " GIODOUT4_set/clr ,GIO Data Output 4" "Low,High" textline " " setclrfld.long 0x00 3. 0x04 3. 0x08 3. " GIODOUT3_set/clr ,GIO Data Output 3" "Low,High" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " GIODOUT2_set/clr ,GIO Data Output 2" "Low,High" textline " " setclrfld.long 0x00 1. 0x04 1. 0x08 1. " GIODOUT1_set/clr ,GIO Data Output 1" "Low,High" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " GIODOUT0_set/clr ,GIO Data Output 0" "Low,High" group.long 0x48++0x0B line.long 0x00 "PDR,Open Drain GIOA" bitfld.long 0x00 7. " GIOPDR7 ,GIO Open Drain 7" "Disabled,Enabled" bitfld.long 0x00 6. " GIOPDR6 ,GIO Open Drain 6" "Disabled,Enabled" bitfld.long 0x00 5. " GIOPDR5 ,GIO Open Drain 5" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " GIOPDR4 ,GIO Open Drain 4" "Disabled,Enabled" bitfld.long 0x00 3. " GIOPDR3 ,GIO Open Drain 3" "Disabled,Enabled" bitfld.long 0x00 2. " GIOPDR2 ,GIO Open Drain 2" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " GIOPDR1 ,GIO Open Drain 1" "Disabled,Enabled" bitfld.long 0x00 0. " GIOPDR0 ,GIO Open Drain 0" "Disabled,Enabled" line.long 0x04 "PULLDIS,Pull Disable GIOA" bitfld.long 0x04 7. " GIOPULDIS7 ,GIO Pull Disable 7" "No,Yes" bitfld.long 0x04 6. " GIOPULDIS6 ,GIO Pull Disable 6" "No,Yes" bitfld.long 0x04 5. " GIOPULDIS5 ,GIO Pull Disable 5" "No,Yes" textline " " bitfld.long 0x04 4. " GIOPULDIS4 ,GIO Pull Disable 4" "No,Yes" bitfld.long 0x04 3. " GIOPULDIS3 ,GIO Pull Disable 3" "No,Yes" bitfld.long 0x04 2. " GIOPULDIS2 ,GIO Pull Disable 2" "No,Yes" textline " " bitfld.long 0x04 1. " GIOPULDIS1 ,GIO Pull Disable 1" "No,Yes" bitfld.long 0x04 0. " GIOPULDIS0 ,GIO Pull Disable 0" "No,Yes" line.long 0x08 "PSL,Pull Select GIOA" bitfld.long 0x08 7. " GIOPSL7 ,GIO Pull Select 7" "Pull down,Pull up" bitfld.long 0x08 6. " GIOPSL6 ,GIO Pull Select 6" "Pull down,Pull up" bitfld.long 0x08 5. " GIOPSL5 ,GIO Pull Select 5" "Pull down,Pull up" textline " " bitfld.long 0x08 4. " GIOPSL4 ,GIO Pull Select 4" "Pull down,Pull up" bitfld.long 0x08 3. " GIOPSL3 ,GIO Pull Select 3" "Pull down,Pull up" bitfld.long 0x08 2. " GIOPSL2 ,GIO Pull Select 2" "Pull down,Pull up" textline " " bitfld.long 0x08 1. " GIOPSL1 ,GIO Pull Select 1" "Pull down,Pull up" bitfld.long 0x08 0. " GIOPSL0 ,GIO Pull Select 0" "Pull down,Pull up" width 0xB tree.end else tree "GIO" base ad:0xFFF7BC00 width 6. sif (cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")||cpu()=="RM48L530-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L540-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L550-PGE"||cpu()=="RM48L550-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L952-PGE"||cpu()=="RM48L952-ZWT"||cpu()=="RM42L432"||cpu()=="RM46L430-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM48L550-ZWT") group.long 0x0++0x3 line.long 0x00 "GCR0,Global Control Register" bitfld.long 0x00 0. " GIOGCR0 ,GIO Global Control" "Reset,Normal" else group.long 0x0++0x7 line.long 0x00 "GCR0,Global Control Register" bitfld.long 0x00 0. " GIOGCR0 ,GIO Global Control" "Reset,Normal" line.long 0x04 "PWDN,Power Down" endif width 8. tree "GIO Interrupt Registers" group.long 0x8++0x3 line.long 0x0 "INTDET,Interrupt Detect" sif (cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!=("RM48L950")&&cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!="RM48L550-ZWT") bitfld.long 0x00 15. " INTDET_1_7 ,GIOB7 Interrupt Detection Select" "Falling/rising,Both" bitfld.long 0x00 14. " INTDET_1_6 ,GIOB6 Interrupt Detection Select" "Falling/rising,Both" textline " " bitfld.long 0x00 13. " INTDET_1_5 ,GIOB5 Interrupt Detection Select" "Falling/rising,Both" bitfld.long 0x00 12. " INTDET_1_4 ,GIOB4 Interrupt Detection Select" "Falling/rising,Both" textline " " bitfld.long 0x00 11. " INTDET_1_3 ,GIOB3 Interrupt Detection Select" "Falling/rising,Both" bitfld.long 0x00 10. " INTDET_1_2 ,GIOB2 Interrupt Detection Select" "Falling/rising,Both" textline " " bitfld.long 0x00 9. " INTDET_1_1 ,GIOB1 Interrupt Detection Select" "Falling/rising,Both" bitfld.long 0x00 8. " INTDET_1_0 ,GIOB0 Interrupt Detection Select" "Falling/rising,Both" textline " " endif bitfld.long 0x00 7. " INTDET_0_7 ,GIOA7 Interrupt Detection Select" "Falling/rising,Both" bitfld.long 0x00 6. " INTDET_0_6 ,GIOA6 Interrupt Detection Select" "Falling/rising,Both" textline " " bitfld.long 0x00 5. " INTDET_0_5 ,GIOA5 Interrupt Detection Select" "Falling/rising,Both" bitfld.long 0x00 4. " INTDET_0_4 ,GIOA4 Interrupt Detection Select" "Falling/rising,Both" textline " " bitfld.long 0x00 3. " INTDET_0_3 ,GIOA3 Interrupt Detection Select" "Falling/rising,Both" bitfld.long 0x00 2. " INTDET_0_2 ,GIOA2 Interrupt Detection Select" "Falling/rising,Both" textline " " bitfld.long 0x00 1. " INTDET_0_1 ,GIOA1 Interrupt Detection Select" "Falling/rising,Both" bitfld.long 0x00 0. " INTDET_0_0 ,GIOA0 Interrupt Detection Select" "Falling/rising,Both" width 8. group.long 0xC++0x3 line.long 0x0 "POL,Interrupt Polarity" sif (cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!=("RM48L950")&&cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!="RM48L550-ZWT") bitfld.long 0x00 15. " GIOPOL_1_7 ,GIOB7 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" bitfld.long 0x00 14. " GIOPOL_1_6 ,GIOB6 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" textline " " bitfld.long 0x00 13. " GIOPOL_1_5 ,GIOB5 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" bitfld.long 0x00 12. " GIOPOL_1_4 ,GIOB4 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" textline " " bitfld.long 0x00 11. " GIOPOL_1_3 ,GIOB3 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" bitfld.long 0x00 10. " GIOPOL_1_2 ,GIOB2 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" textline " " bitfld.long 0x00 9. " GIOPOL_1_1 ,GIOB1 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" bitfld.long 0x00 8. " GIOPOL_1_0 ,GIOB0 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" textline " " endif bitfld.long 0x00 7. " GIOPOL_0_7 ,GIOA7 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" bitfld.long 0x00 6. " GIOPOL_0_6 ,GIOA6 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" textline " " bitfld.long 0x00 5. " GIOPOL_0_5 ,GIOA5 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" bitfld.long 0x00 4. " GIOPOL_0_4 ,GIOA4 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" textline " " bitfld.long 0x00 3. " GIOPOL_0_3 ,GIOA3 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" bitfld.long 0x00 2. " GIOPOL_0_2 ,GIOA2 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" textline " " bitfld.long 0x00 1. " GIOPOL_0_1 ,GIOA1 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" bitfld.long 0x00 0. " GIOPOL_0_0 ,GIOA0 Interrupt Polarity Select (User-priviledge/Low power mode)" "Falling/Low,Rising/High" width 8. tree "GIO Interrupt Enable Registers" group.long 0x10++0x3 line.long 0x0 "ENASET,Interrupt Enable Set" sif (cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!=("RM48L950")&&cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!="RM48L550-ZWT") bitfld.long 0x00 15. " GIOENASET_1_7 ,GIOB7 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 14. " GIOENASET_1_6 ,GIOB6 Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " GIOENASET_1_5 ,GIOB5 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 12. " GIOENASET_1_4 ,GIOB4 Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " GIOENASET_1_3 ,GIOB3 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10. " GIOENASET_1_2 ,GIOB2 Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " GIOENASET_1_1 ,GIOB1 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 8. " GIOENASET_1_0 ,GIOB0 Interrupt Enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 7. " GIOENASET_0_7 ,GIOA7 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. " GIOENASET_0_6 ,GIOA6 Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " GIOENASET_0_5 ,GIOA5 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " GIOENASET_0_4 ,GIOA4 Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " GIOENASET_0_3 ,GIOA3 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. " GIOENASET_0_2 ,GIOA2 Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " GIOENASET_0_1 ,GIOA1 Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. " GIOENASET_0_0 ,GIOA0 Interrupt Enable" "Disabled,Enabled" width 8. group.long 0x14++0x3 line.long 0x0 "ENACLR,Interrupt Enable Clear" sif (cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!=("RM48L950")&&cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!="RM48L550-ZWT") bitfld.long 0x00 15. " GIOENACLR_1_7 ,GIOB7 Interrupt Disable" "No,Yes" bitfld.long 0x00 14. " GIOENACLR_1_6 ,GIOB6 Interrupt Disable" "No,Yes" textline " " bitfld.long 0x00 13. " GIOENACLR_1_5 ,GIOB5 Interrupt Disable" "No,Yes" bitfld.long 0x00 12. " GIOENACLR_1_4 ,GIOB4 Interrupt Disable" "No,Yes" textline " " bitfld.long 0x00 11. " GIOENACLR_1_3 ,GIOB3 Interrupt Disable" "No,Yes" bitfld.long 0x00 10. " GIOENACLR_1_2 ,GIOB2 Interrupt Disable" "No,Yes" textline " " bitfld.long 0x00 9. " GIOENACLR_1_1 ,GIOB1 Interrupt Disable" "No,Yes" bitfld.long 0x00 8. " GIOENACLR_1_0 ,GIOB0 Interrupt Disable" "No,Yes" textline " " endif bitfld.long 0x00 7. " GIOENACLR_0_7 ,GIOA7 Interrupt Disable" "No,Yes" bitfld.long 0x00 6. " GIOENACLR_0_6 ,GIOA6 Interrupt Disable" "No,Yes" textline " " bitfld.long 0x00 5. " GIOENACLR_0_5 ,GIOA5 Interrupt Disable" "No,Yes" bitfld.long 0x00 4. " GIOENACLR_0_4 ,GIOA4 Interrupt Disable" "No,Yes" textline " " bitfld.long 0x00 3. " GIOENACLR_0_3 ,GIOA3 Interrupt Disable" "No,Yes" bitfld.long 0x00 2. " GIOENACLR_0_2 ,GIOA2 Interrupt Disable" "No,Yes" textline " " bitfld.long 0x00 1. " GIOENACLR_0_1 ,GIOA1 Interrupt Disable" "No,Yes" bitfld.long 0x00 0. " GIOENACLR_0_0 ,GIOA0 Interrupt Disable" "No,Yes" tree.end width 8. tree "GIO Interrupt Priority Registers" group.long 0x18++0x3 line.long 0x0 "LVLSET,Interrupt Priority Set" sif (cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!=("RM48L950")&&cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!="RM48L550-ZWT") bitfld.long 0x00 15. " GIOLVLSET_1_7 ,GIOB7 High Priority Interrupt" "No effect,High priority" bitfld.long 0x00 14. " GIOLVLSET_1_6 ,GIOB6 High Priority Interrupt" "No effect,High priority" textline " " bitfld.long 0x00 13. " GIOLVLSET_1_5 ,GIOB5 High Priority Interrupt" "No effect,High priority" bitfld.long 0x00 12. " GIOLVLSET_1_4 ,GIOB4 High Priority Interrupt" "No effect,High priority" textline " " bitfld.long 0x00 11. " GIOLVLSET_1_3 ,GIOB3 High Priority Interrupt" "No effect,High priority" bitfld.long 0x00 10. " GIOLVLSET_1_2 ,GIOB2 High Priority Interrupt" "No effect,High priority" textline " " bitfld.long 0x00 9. " GIOLVLSET_1_1 ,GIOB1 High Priority Interrupt" "No effect,High priority" bitfld.long 0x00 8. " GIOLVLSET_1_0 ,GIOB0 High Priority Interrupt" "No effect,High priority" textline " " endif bitfld.long 0x00 7. " GIOLVLSET_0_7 ,GIOA7 High Priority Interrupt" "No effect,High priority" bitfld.long 0x00 6. " GIOLVLSET_0_6 ,GIOA6 High Priority Interrupt" "No effect,High priority" textline " " bitfld.long 0x00 5. " GIOLVLSET_0_5 ,GIOA5 High Priority Interrupt" "No effect,High priority" bitfld.long 0x00 4. " GIOLVLSET_0_4 ,GIOA4 High Priority Interrupt" "No effect,High priority" textline " " bitfld.long 0x00 3. " GIOLVLSET_0_3 ,GIOA3 High Priority Interrupt" "No effect,High priority" bitfld.long 0x00 2. " GIOLVLSET_0_2 ,GIOA2 High Priority Interrupt" "No effect,High priority" textline " " bitfld.long 0x00 1. " GIOLVLSET_0_1 ,GIOA1 High Priority Interrupt" "No effect,High priority" bitfld.long 0x00 0. " GIOLVLSET_0_0 ,GIOA0 High Priority Interrupt" "No effect,High priority" group.long 0x1C++0x3 line.long 0x0 "LVLCLR,Interrupt Priority Clear" sif (cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!=("RM48L950")&&cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!="RM48L550-ZWT") bitfld.long 0x00 15. " GIOLVLCLR_1_7 ,GIOB7 Low Priority Interrupt" "No effect,Low priority" bitfld.long 0x00 14. " GIOLVLCLR_1_6 ,GIOB6 Low Priority Interrupt" "No effect,Low priority" textline " " bitfld.long 0x00 13. " GIOLVLCLR_1_5 ,GIOB5 Low Priority Interrupt" "No effect,Low priority" bitfld.long 0x00 12. " GIOLVLCLR_1_4 ,GIOB4 Low Priority Interrupt" "No effect,Low priority" textline " " bitfld.long 0x00 11. " GIOLVLCLR_1_3 ,GIOB3 Low Priority Interrupt" "No effect,Low priority" bitfld.long 0x00 10. " GIOLVLCLR_1_2 ,GIOB2 Low Priority Interrupt" "No effect,Low priority" textline " " bitfld.long 0x00 9. " GIOLVLCLR_1_1 ,GIOB1 Low Priority Interrupt" "No effect,Low priority" bitfld.long 0x00 8. " GIOLVLCLR_1_0 ,GIOB0 Low Priority Interrupt" "No effect,Low priority" textline " " endif bitfld.long 0x00 7. " GIOLVLCLR_0_7 ,GIOA7 Low Priority Interrupt" "No effect,Low priority" bitfld.long 0x00 6. " GIOLVLCLR_0_6 ,GIOA6 Low Priority Interrupt" "No effect,Low priority" textline " " bitfld.long 0x00 5. " GIOLVLCLR_0_5 ,GIOA5 Low Priority Interrupt" "No effect,Low priority" bitfld.long 0x00 4. " GIOLVLCLR_0_4 ,GIOA4 Low Priority Interrupt" "No effect,Low priority" textline " " bitfld.long 0x00 3. " GIOLVLCLR_0_3 ,GIOA3 Low Priority Interrupt" "No effect,Low priority" bitfld.long 0x00 2. " GIOLVLCLR_0_2 ,GIOA2 Low Priority Interrupt" "No effect,Low priority" textline " " bitfld.long 0x00 1. " GIOLVLCLR_0_1 ,GIOA1 Low Priority Interrupt" "No effect,Low priority" bitfld.long 0x00 0. " GIOLVLCLR_0_0 ,GIOA0 Low Priority Interrupt" "No effect,Low priority" tree.end width 8. group.long 0x20++0x3 line.long 0x0 "FLG,Interrupt Flag" sif (cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!=("RM48L950")&&cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!="RM48L550-ZWT") eventfld.long 0x00 15. " GIOFLG_1_7 ,GIOB7 Flag" "Not occurred,Occurred" eventfld.long 0x00 14. " GIOFLG_1_6 ,GIOB6 Flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 13. " GIOFLG_1_5 ,GIOB5 Flag" "Not occurred,Occurred" eventfld.long 0x00 12. " GIOFLG_1_4 ,GIOB4 Flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 11. " GIOFLG_1_3 ,GIOB3 Flag" "Not occurred,Occurred" eventfld.long 0x00 10. " GIOFLG_1_2 ,GIOB2 Flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 9. " GIOFLG_1_1 ,GIOB1 Flag" "Not occurred,Occurred" eventfld.long 0x00 8. " GIOFLG_1_0 ,GIOB0 Flag" "Not occurred,Occurred" textline " " endif eventfld.long 0x00 7. " GIOFLG_0_7 ,GIOA7 Flag" "Not occurred,Occurred" eventfld.long 0x00 6. " GIOFLG_0_6 ,GIOA6 Flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 5. " GIOFLG_0_5 ,GIOA5 Flag" "Not occurred,Occurred" eventfld.long 0x00 4. " GIOFLG_0_4 ,GIOA4 Flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 3. " GIOFLG_0_3 ,GIOA3 Flag" "Not occurred,Occurred" eventfld.long 0x00 2. " GIOFLG_0_2 ,GIOA2 Flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 1. " GIOFLG_0_1 ,GIOA1 Flag" "Not occurred,Occurred" eventfld.long 0x00 0. " GIOFLG_0_0 ,GIOA0 Flag" "Not occurred,Occurred" width 6. tree "GIO Interrupt Offset Registers" hgroup.long 0x24++0x3 hide.long 0x0 "OFFA,Offset A" in rgroup.long 0x2C++0x3 line.long 0x0 "EMUA,Emulation A" sif (cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!=("RM48L950")&&cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!="RM48L550-ZWT") bitfld.long 0x00 0.--5. " GIOEMUA ,GIO Offset A" "No interrupt,Interrupt 0,Interrupt 1,Interrupt 2,Interrupt 3,Interrupt 4,Interrupt 5,Interrupt 6,Interrupt 7,?..." else bitfld.long 0x00 0.--5. " GIOEMUA ,GIO Offset A" "No interrupt,Interrupt 0,Interrupt 1,Interrupt 2,Interrupt 3,Interrupt 4,Interrupt 5,Interrupt 6,Interrupt 7,Interrupt 8,Interrupt 9,Interrupt 10,Interrupt 11,Interrupt 12,Interrupt 13,Interrupt 14,Interrupt 15,Interrupt 16,Interrupt 17,Interrupt 18,Interrupt 19,Interrupt 20,Interrupt 21,Interrupt 22,Interrupt 23,Interrupt 24,Interrupt 25,Interrupt 26,Interrupt 27,Interrupt 28,Interrupt 29,Interrupt 30,Interrupt 31,?..." endif hgroup.long 0x28++0x3 hide.long 0x0 "OFFB,Offset B" in rgroup.long 0x30++0x3 line.long 0x0 "EMUB,Emulation B" sif (cpu()!="TMS570PSFC61"&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-PGE")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!=("TMS570LS30336")&&cpu()!=("RM48L950")&&cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!="RM48L550-ZWT") bitfld.long 0x00 0.--5. " GIOEMUB ,GIO Offset B" "No interrupt,Interrupt 0,Interrupt 1,Interrupt 2,Interrupt 3,Interrupt 4,Interrupt 5,Interrupt 6,Interrupt 7,?..." else bitfld.long 0x00 0.--5. " GIOEMUB ,GIO Offset B" "No interrupt,Interrupt 0,Interrupt 1,Interrupt 2,Interrupt 3,Interrupt 4,Interrupt 5,Interrupt 6,Interrupt 7,Interrupt 8,Interrupt 9,Interrupt 10,Interrupt 11,Interrupt 12,Interrupt 13,Interrupt 14,Interrupt 15,Interrupt 16,Interrupt 17,Interrupt 18,Interrupt 19,Interrupt 20,Interrupt 21,Interrupt 22,Interrupt 23,Interrupt 24,Interrupt 25,Interrupt 26,Interrupt 27,Interrupt 28,Interrupt 29,Interrupt 30,Interrupt 31,?..." endif tree.end tree.end width 0xb tree.end tree "GIOA" base ad:0xFFF7BC00 width 9. rgroup.long 0x34++0x3 line.long 0x0 "DIR,Data Direction GIOA" sif (cpu()==("TMS570LS2124-PGE")||cpu()==("TMS570LS2124-ZWT")||cpu()==("TMS570LS2134-PGE")||cpu()==("TMS570LS2134-ZWT")||cpu()==("TMS570LS3134-PGE")||cpu()==("TMS570LS3134-ZWT")||cpu()==("TMS570LS3135-PGE")||cpu()==("TMS570LS3135-ZWT")||cpu()==("TMS570LS3136")||cpu()==("TMS570LS3137-PGE")||cpu()==("TMS570LS3137-ZWT")||cpu()==("TMS570LS30336")||cpu()==("TMS570LS2126")||cpu()==("TMS570LS2127")||cpu()==("TMS570LS2136")||cpu()==("TMS570LS2137")||cpu()==("TMS570LS2125-PGE")||cpu()==("TMS570LS2125-ZWT")||cpu()==("TMS570LS2135-PGE")||cpu()==("TMS570LS2135-ZWT")||cpu()==("RM48L950")||cpu()=="RM48L952-PGE"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L540-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE"||cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE") bitfld.long 0x00 7. " GIODIR7 ,GIO Data Direction 7" "Input,Output" bitfld.long 0x00 6. " GIODIR6 ,GIO Data Direction 6" "Input,Output" textline " " bitfld.long 0x00 5. " GIODIR5 ,GIO Data Direction 5" "Input,Output" bitfld.long 0x00 4. " GIODIR4 ,GIO Data Direction 4" "Input,Output" textline " " bitfld.long 0x00 3. " GIODIR3 ,GIO Data Direction 3" "Input,Output" bitfld.long 0x00 2. " GIODIR2 ,GIO Data Direction 2" "Input,Output" textline " " bitfld.long 0x00 1. " GIODIR1 ,GIO Data Direction 1" "Input,Output" bitfld.long 0x00 0. " GIODIR0 ,GIO Data Direction 0" "Input,Output" else bitfld.long 0x00 7. " GIODIR7 ,GIO Data Direction 7" "Output disabled,Output enabled" bitfld.long 0x00 6. " GIODIR6 ,GIO Data Direction 6" "Output disabled,Output enabled" textline " " bitfld.long 0x00 5. " GIODIR5 ,GIO Data Direction 5" "Output disabled,Output enabled" bitfld.long 0x00 4. " GIODIR4 ,GIO Data Direction 4" "Output disabled,Output enabled" textline " " bitfld.long 0x00 3. " GIODIR3 ,GIO Data Direction 3" "Output disabled,Output enabled" bitfld.long 0x00 2. " GIODIR2 ,GIO Data Direction 2" "Output disabled,Output enabled" textline " " bitfld.long 0x00 1. " GIODIR1 ,GIO Data Direction 1" "Output disabled,Output enabled" bitfld.long 0x00 0. " GIODIR0 ,GIO Data Direction 0" "Output disabled,Output enabled" endif width 9. rgroup.long 0x38++0x3 line.long 0x0 "DIN,Data Input GIOA" bitfld.long 0x00 7. " GIODIN7 ,GIO Data Input 7" "Low,High" bitfld.long 0x00 6. " GIODIN6 ,GIO Data Input 6" "Low,High" textline " " bitfld.long 0x00 5. " GIODIN5 ,GIO Data Input 5" "Low,High" bitfld.long 0x00 4. " GIODIN4 ,GIO Data Input 4" "Low,High" textline " " bitfld.long 0x00 3. " GIODIN3 ,GIO Data Input 3" "Low,High" bitfld.long 0x00 2. " GIODIN2 ,GIO Data Input 2" "Low,High" textline " " bitfld.long 0x00 1. " GIODIN1 ,GIO Data Input 1" "Low,High" bitfld.long 0x00 0. " GIODIN0 ,GIO Data Input 0" "Low,High" width 9. group.long 0x3C++0x3 line.long 0x0 "DOUT,Data Output GIOA" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " GIODOUT7_set/clr ,GIO Data Output 7" "Low,High" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " GIODOUT6_set/clr ,GIO Data Output 6" "Low,High" textline " " setclrfld.long 0x00 5. 0x04 5. 0x08 5. " GIODOUT5_set/clr ,GIO Data Output 5" "Low,High" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " GIODOUT4_set/clr ,GIO Data Output 4" "Low,High" textline " " setclrfld.long 0x00 3. 0x04 3. 0x08 3. " GIODOUT3_set/clr ,GIO Data Output 3" "Low,High" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " GIODOUT2_set/clr ,GIO Data Output 2" "Low,High" textline " " setclrfld.long 0x00 1. 0x04 1. 0x08 1. " GIODOUT1_set/clr ,GIO Data Output 1" "Low,High" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " GIODOUT0_set/clr ,GIO Data Output 0" "Low,High" width 9. group.long 0x48++0x3 line.long 0x0 "PDR,Open Drain GIOA" bitfld.long 0x00 7. " GIOPDR7 ,GIO Open Drain 7" "Disabled,Enabled" bitfld.long 0x00 6. " GIOPDR6 ,GIO Open Drain 6" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " GIOPDR5 ,GIO Open Drain 5" "Disabled,Enabled" bitfld.long 0x00 4. " GIOPDR4 ,GIO Open Drain 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " GIOPDR3 ,GIO Open Drain 3" "Disabled,Enabled" bitfld.long 0x00 2. " GIOPDR2 ,GIO Open Drain 2" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " GIOPDR1 ,GIO Open Drain 1" "Disabled,Enabled" bitfld.long 0x00 0. " GIOPDR0 ,GIO Open Drain 0" "Disabled,Enabled" width 9. group.long 0x4C++0x3 line.long 0x0 "PULLDIS,Pull Disable GIOA" bitfld.long 0x0 7. " GIOPULDIS7 ,GIO Pull Disable 7" "No,Yes" bitfld.long 0x0 6. " GIOPULDIS6 ,GIO Pull Disable 6" "No,Yes" textline " " bitfld.long 0x0 5. " GIOPULDIS5 ,GIO Pull Disable 5" "No,Yes" bitfld.long 0x0 4. " GIOPULDIS4 ,GIO Pull Disable 4" "No,Yes" textline " " bitfld.long 0x0 3. " GIOPULDIS3 ,GIO Pull Disable 3" "No,Yes" bitfld.long 0x0 2. " GIOPULDIS2 ,GIO Pull Disable 2" "No,Yes" textline " " bitfld.long 0x0 1. " GIOPULDIS1 ,GIO Pull Disable 1" "No,Yes" bitfld.long 0x0 0. " GIOPULDIS0 ,GIO Pull Disable 0" "No,Yes" width 9. group.long 0x50++0x3 line.long 0x0 "PSL,Pull Select GIOA" bitfld.long 0x0 7. " GIOPSL7 ,GIO Pull Select 7" "Pull down,Pull up" bitfld.long 0x0 6. " GIOPSL6 ,GIO Pull Select 6" "Pull down,Pull up" textline " " bitfld.long 0x0 5. " GIOPSL5 ,GIO Pull Select 5" "Pull down,Pull up" bitfld.long 0x0 4. " GIOPSL4 ,GIO Pull Select 4" "Pull down,Pull up" textline " " bitfld.long 0x0 3. " GIOPSL3 ,GIO Pull Select 3" "Pull down,Pull up" bitfld.long 0x0 2. " GIOPSL2 ,GIO Pull Select 2" "Pull down,Pull up" textline " " bitfld.long 0x0 1. " GIOPSL1 ,GIO Pull Select 1" "Pull down,Pull up" bitfld.long 0x0 0. " GIOPSL0 ,GIO Pull Select 0" "Pull down,Pull up" sif (cpu()!="TMS570PSFC61"&&cpu()!="RM48L952-PGE"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!="RM48L550-ZWT") width 9. group.long 0x134++0x3 line.long 0x0 "SRS,Slew Rate Select GIOA" bitfld.long 0x00 7. " GIOSRS7 ,GIO Slew Rate Select 7" "Normal,Slow" bitfld.long 0x00 6. " GIOSRS6 ,GIO Slew Rate Select 6" "Normal,Slow" textline " " bitfld.long 0x00 5. " GIOSRS5 ,GIO Slew Rate Select 5" "Normal,Slow" bitfld.long 0x00 4. " GIOSRS4 ,GIO Slew Rate Select 4" "Normal,Slow" textline " " bitfld.long 0x00 3. " GIOSRS3 ,GIO Slew Rate Select 3" "Normal,Slow" bitfld.long 0x00 2. " GIOSRS2 ,GIO Slew Rate Select 2" "Normal,Slow" textline " " bitfld.long 0x00 1. " GIOSRS1 ,GIO Slew Rate Select 1" "Normal,Slow" bitfld.long 0x00 0. " GIOSRS0 ,GIO Slew Rate Select 0" "Normal,Slow" endif width 0xb tree.end tree "GIOB" base ad:0xFFF7BC00 width 9. rgroup.long 0x54++0x3 line.long 0x0 "DIR,Data Direction GIOB" sif (cpu()=="TMS570PSFC61") bitfld.long 0x00 7. " GIODIR7 ,GIO Data Direction 7" "Output disabled,Output enabled" bitfld.long 0x00 6. " GIODIR6 ,GIO Data Direction 6" "Output disabled,Output enabled" textline " " bitfld.long 0x00 5. " GIODIR5 ,GIO Data Direction 5" "Output disabled,Output enabled" bitfld.long 0x00 4. " GIODIR4 ,GIO Data Direction 4" "Output disabled,Output enabled" textline " " bitfld.long 0x00 3. " GIODIR3 ,GIO Data Direction 3" "Output disabled,Output enabled" bitfld.long 0x00 2. " GIODIR2 ,GIO Data Direction 2" "Output disabled,Output enabled" textline " " bitfld.long 0x00 1. " GIODIR1 ,GIO Data Direction 1" "Output disabled,Output enabled" bitfld.long 0x00 0. " GIODIR0 ,GIO Data Direction 0" "Output disabled,Output enabled" elif (cpu()==("TMS570LS2124-PGE")||cpu()==("TMS570LS2124-ZWT")||cpu()==("TMS570LS2134-PGE")||cpu()==("TMS570LS2134-ZWT")||cpu()==("TMS570LS3134-PGE")||cpu()==("TMS570LS3134-ZWT")||cpu()==("TMS570LS3135-PGE")||cpu()==("TMS570LS3135-ZWT")||cpu()==("TMS570LS3136")||cpu()==("TMS570LS3137-PGE")||cpu()==("TMS570LS3137-ZWT")||cpu()==("TMS570LS30336")||cpu()==("TMS570LS2126")||cpu()==("TMS570LS2127")||cpu()==("TMS570LS2136")||cpu()==("TMS570LS2137")||cpu()==("TMS570LS2125-PGE")||cpu()==("TMS570LS2125-ZWT")||cpu()==("TMS570LS2135-PGE")||cpu()==("TMS570LS2135-ZWT")||cpu()==("RM48L950")||cpu()=="RM48L952-PGE"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L540-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE"||cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE"||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")||cpu()=="RM48L550-ZWT") bitfld.long 0x00 7. " GIODIR7 ,GIO Data Direction 7" "Input,Output" bitfld.long 0x00 6. " GIODIR6 ,GIO Data Direction 6" "Input,Output" textline " " bitfld.long 0x00 5. " GIODIR5 ,GIO Data Direction 5" "Input,Output" bitfld.long 0x00 4. " GIODIR4 ,GIO Data Direction 4" "Input,Output" textline " " bitfld.long 0x00 3. " GIODIR3 ,GIO Data Direction 3" "Input,Output" bitfld.long 0x00 2. " GIODIR2 ,GIO Data Direction 2" "Input,Output" textline " " bitfld.long 0x00 1. " GIODIR1 ,GIO Data Direction 1" "Input,Output" bitfld.long 0x00 0. " GIODIR0 ,GIO Data Direction 0" "Input,Output" else bitfld.long 0x00 1. " GIODIR1 ,GIO Data Direction 1" "Output disabled,Output enabled" bitfld.long 0x00 0. " GIODIR0 ,GIO Data Direction 0" "Output disabled,Output enabled" endif width 9. sif (cpu()=="TMS570PSFC61"||cpu()==("TMS570LS2126")||cpu()==("TMS570LS2127")||cpu()==("TMS570LS2136")||cpu()==("TMS570LS2137")||cpu()==("TMS570LS2125-PGE")||cpu()==("TMS570LS2125-ZWT")||cpu()==("TMS570LS2135-PGE")||cpu()==("TMS570LS2135-ZWT")||cpu()==("TMS570LS2124-PGE")||cpu()==("TMS570LS2124-ZWT")||cpu()==("TMS570LS2134-PGE")||cpu()==("TMS570LS2134-ZWT")||cpu()==("TMS570LS3134-PGE")||cpu()==("TMS570LS3134-ZWT")||cpu()==("TMS570LS3135-PGE")||cpu()==("TMS570LS3135-ZWT")||cpu()==("TMS570LS3136")||cpu()==("TMS570LS3137-PGE")||cpu()==("TMS570LS3137-ZWT")||cpu()==("TMS570LS30336")||cpu()==("RM48L950")||cpu()=="RM48L952-PGE"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L540-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE"||cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE"||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")||cpu()=="RM48L550-ZWT") rgroup.long 0x58++0x3 line.long 0x0 "DIN,Data Input GIOB" bitfld.long 0x00 7. " GIODIN7 ,GIO Data Input 7" "Low,High" bitfld.long 0x00 6. " GIODIN6 ,GIO Data Input 6" "Low,High" textline " " bitfld.long 0x00 5. " GIODIN5 ,GIO Data Input 5" "Low,High" bitfld.long 0x00 4. " GIODIN4 ,GIO Data Input 4" "Low,High" textline " " bitfld.long 0x00 3. " GIODIN3 ,GIO Data Input 3" "Low,High" bitfld.long 0x00 2. " GIODIN2 ,GIO Data Input 2" "Low,High" textline " " bitfld.long 0x00 1. " GIODIN1 ,GIO Data Input 1" "Low,High" bitfld.long 0x00 0. " GIODIN0 ,GIO Data Input 0" "Low,High" else group.long 0x58++0x3 line.long 0x0 "DIN,Data Input GIOB" bitfld.long 0x00 1. " GIODIN1 ,GIO Data Input 1" "Low,High" bitfld.long 0x00 0. " GIODIN0 ,GIO Data Input 0" "Low,High" endif width 9. group.long 0x5C++0x3 line.long 0x0 "DOUT,Data Output GIOB" sif (cpu()=="TMS570PSFC61"||cpu()==("TMS570LS2126")||cpu()==("TMS570LS2127")||cpu()==("TMS570LS2136")||cpu()==("TMS570LS2137")||cpu()==("TMS570LS2125-PGE")||cpu()==("TMS570LS2125-ZWT")||cpu()==("TMS570LS2135-PGE")||cpu()==("TMS570LS2135-ZWT")||cpu()==("TMS570LS2124-PGE")||cpu()==("TMS570LS2124-ZWT")||cpu()==("TMS570LS2134-PGE")||cpu()==("TMS570LS2134-ZWT")||cpu()==("TMS570LS3134-PGE")||cpu()==("TMS570LS3134-ZWT")||cpu()==("TMS570LS3135-PGE")||cpu()==("TMS570LS3135-ZWT")||cpu()==("TMS570LS3136")||cpu()==("TMS570LS3137-PGE")||cpu()==("TMS570LS3137-ZWT")||cpu()==("TMS570LS30336")||cpu()==("RM48L950")||cpu()=="RM48L952-PGE"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L540-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE"||cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE"||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")||cpu()=="RM48L550-ZWT") setclrfld.long 0x00 7. 0x04 7. 0x08 7. " GIODOUT7_set/clr ,GIO Data Output 7" "Low,High" setclrfld.long 0x00 6. 0x04 6. 0x08 6. " GIODOUT6_set/clr ,GIO Data Output 6" "Low,High" textline " " setclrfld.long 0x00 5. 0x04 5. 0x08 5. " GIODOUT5_set/clr ,GIO Data Output 5" "Low,High" setclrfld.long 0x00 4. 0x04 4. 0x08 4. " GIODOUT4_set/clr ,GIO Data Output 4" "Low,High" textline " " setclrfld.long 0x00 3. 0x04 3. 0x08 3. " GIODOUT3_set/clr ,GIO Data Output 3" "Low,High" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " GIODOUT2_set/clr ,GIO Data Output 2" "Low,High" textline " " endif setclrfld.long 0x00 1. 0x04 1. 0x08 1. " GIODOUT1_set/clr ,GIO Data Output 1" "Low,High" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " GIODOUT0_set/clr ,GIO Data Output 0" "Low,High" width 9. group.long 0x68++0x3 line.long 0x0 "PDR,Open Drain GIOB" sif (cpu()=="TMS570PSFC61"||cpu()==("TMS570LS2126")||cpu()==("TMS570LS2127")||cpu()==("TMS570LS2136")||cpu()==("TMS570LS2137")||cpu()==("TMS570LS2125-PGE")||cpu()==("TMS570LS2125-ZWT")||cpu()==("TMS570LS2135-PGE")||cpu()==("TMS570LS2135-ZWT")||cpu()==("TMS570LS2124-PGE")||cpu()==("TMS570LS2124-ZWT")||cpu()==("TMS570LS2134-PGE")||cpu()==("TMS570LS2134-ZWT")||cpu()==("TMS570LS3134-PGE")||cpu()==("TMS570LS3134-ZWT")||cpu()==("TMS570LS3135-PGE")||cpu()==("TMS570LS3135-ZWT")||cpu()==("TMS570LS3136")||cpu()==("TMS570LS3137-PGE")||cpu()==("TMS570LS3137-ZWT")||cpu()==("TMS570LS30336")||cpu()==("RM48L950")||cpu()=="RM48L952-PGE"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L540-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE"||cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE"||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")||cpu()=="RM48L550-ZWT") bitfld.long 0x00 7. " GIOPDR7 ,GIO Open Drain 7" "Disabled,Enabled" bitfld.long 0x00 6. " GIOPDR6 ,GIO Open Drain 6" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " GIOPDR5 ,GIO Open Drain 5" "Disabled,Enabled" bitfld.long 0x00 4. " GIOPDR4 ,GIO Open Drain 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " GIOPDR3 ,GIO Open Drain 3" "Disabled,Enabled" bitfld.long 0x00 2. " GIOPDR2 ,GIO Open Drain 2" "Disabled,Enabled" textline " " endif bitfld.long 0x00 1. " GIOPDR1 ,GIO Open Drain 1" "Disabled,Enabled" bitfld.long 0x00 0. " GIOPDR0 ,GIO Open Drain 0" "Disabled,Enabled" group.long 0x6C++0x3 line.long 0x0 "PULLDIS,Pull Disable GIOB" sif (cpu()=="TMS570PSFC61"||cpu()==("TMS570LS2126")||cpu()==("TMS570LS2127")||cpu()==("TMS570LS2136")||cpu()==("TMS570LS2137")||cpu()==("TMS570LS2125-PGE")||cpu()==("TMS570LS2125-ZWT")||cpu()==("TMS570LS2135-PGE")||cpu()==("TMS570LS2135-ZWT")||cpu()==("TMS570LS2124-PGE")||cpu()==("TMS570LS2124-ZWT")||cpu()==("TMS570LS2134-PGE")||cpu()==("TMS570LS2134-ZWT")||cpu()==("TMS570LS3134-PGE")||cpu()==("TMS570LS3134-ZWT")||cpu()==("TMS570LS3135-PGE")||cpu()==("TMS570LS3135-ZWT")||cpu()==("TMS570LS3136")||cpu()==("TMS570LS3137-PGE")||cpu()==("TMS570LS3137-ZWT")||cpu()==("TMS570LS30336")||cpu()==("RM48L950")||cpu()=="RM48L952-PGE"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L540-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE"||cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE"||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")||cpu()=="RM48L550-ZWT") bitfld.long 0x0 7. " GIOPULDIS6 ,GIO Pull Disable 6" "No,Yes" bitfld.long 0x0 6. " GIOPULDIS6 ,GIO Pull Disable 6" "No,Yes" textline " " bitfld.long 0x0 5. " GIOPULDIS5 ,GIO Pull Disable 5" "No,Yes" bitfld.long 0x0 4. " GIOPULDIS4 ,GIO Pull Disable 4" "No,Yes" textline " " bitfld.long 0x0 3. " GIOPULDIS3 ,GIO Pull Disable 3" "No,Yes" bitfld.long 0x0 2. " GIOPULDIS2 ,GIO Pull Disable 2" "No,Yes" textline " " endif bitfld.long 0x0 1. " GIOPULDIS1 ,GIO Pull Disable 1" "No,Yes" bitfld.long 0x0 0. " GIOPULDIS0 ,GIO Pull Disable 0" "No,Yes" group.long 0x70++0x3 line.long 0x0 "PSL,Pull Select GIOB" sif (cpu()=="TMS570PSFC61"||cpu()==("TMS570LS2126")||cpu()==("TMS570LS2127")||cpu()==("TMS570LS2136")||cpu()==("TMS570LS2137")||cpu()==("TMS570LS2125-PGE")||cpu()==("TMS570LS2125-ZWT")||cpu()==("TMS570LS2135-PGE")||cpu()==("TMS570LS2135-ZWT")||cpu()==("TMS570LS2124-PGE")||cpu()==("TMS570LS2124-ZWT")||cpu()==("TMS570LS2134-PGE")||cpu()==("TMS570LS2134-ZWT")||cpu()==("TMS570LS3134-PGE")||cpu()==("TMS570LS3134-ZWT")||cpu()==("TMS570LS3135-PGE")||cpu()==("TMS570LS3135-ZWT")||cpu()==("TMS570LS3136")||cpu()==("TMS570LS3137-PGE")||cpu()==("TMS570LS3137-ZWT")||cpu()==("TMS570LS30336")||cpu()==("RM48L950")||cpu()=="RM48L952-PGE"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L540-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE"||cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE"||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10206-PGE")||cpu()=="RM48L550-ZWT") bitfld.long 0x0 7. " GIOPSL7 ,GIO Pull Select 7" "Pull down,Pull up" bitfld.long 0x0 6. " GIOPSL6 ,GIO Pull Select 6" "Pull down,Pull up" textline " " bitfld.long 0x0 5. " GIOPSL5 ,GIO Pull Select 5" "Pull down,Pull up" bitfld.long 0x0 4. " GIOPSL4 ,GIO Pull Select 4" "Pull down,Pull up" textline " " bitfld.long 0x0 3. " GIOPSL3 ,GIO Pull Select 3" "Pull down,Pull up" bitfld.long 0x0 2. " GIOPSL2 ,GIO Pull Select 2" "Pull down,Pull up" textline " " endif bitfld.long 0x0 1. " GIOPSL1 ,GIO Pull Select 1" "Pull down,Pull up" bitfld.long 0x0 0. " GIOPSL0 ,GIO Pull Select 0" "Pull down,Pull up" sif (cpu()!="TMS570PSFC61"&&cpu()!="RM48L952-PGE"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()=="RM48L550-ZWT") group.long 0x138++0x3 line.long 0x0 "SRS,Slew Rate Select GIOB" bitfld.long 0x00 1. " GIOSRS1 ,GIO Slew Rate Select 1" "Normal,Slow" bitfld.long 0x00 0. " GIOSRS0 ,GIO Slew Rate Select 0" "Normal,Slow" endif width 0xb tree.end endif tree.end tree "DCAN (Controller Area Network)" tree "DCAN1" base ad:0xFFF7DC00 width 12. group.long 0x00++0x3 line.long 0x0 "CTL,Control register" bitfld.long 0x00 25. " WUBA ,Automatic wake up on bus activity" "Not detected,Detected" bitfld.long 0x00 24. " PDR ,Request for local low power down mode" "Not requested,Requested" bitfld.long 0x00 20. " DE3 ,Enable DMA request line for IF3" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " DE2 ,Enable DMA request line for IF2" "Disabled,Enabled" bitfld.long 0x00 18. " DE1 ,Enable DMA request line for IF1" "Disabled,Enabled" bitfld.long 0x00 17. " IE1 ,Interrupt DCAN1INT line 1 Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " INITDBG ,Internal Init state while debug access" "Not initialized,Initialized" bitfld.long 0x00 15. " SWR ,SW Reset Enable" "Normal,Reset" bitfld.long 0x00 10.--13. " PMD ,Parity on/off" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" textline " " bitfld.long 0x00 9. " ABO ,Auto-Bus-On Enable" "Disabled,Enabled" bitfld.long 0x00 8. " IDS ,Interruption Debug Support Enable" "Disabled,Enabled" bitfld.long 0x00 7. " TEST ,Test Mode Enable" "Normal,Enabled" textline " " bitfld.long 0x00 6. " CCE ,Configuration Change Enable" "No WR access,WR Access" bitfld.long 0x00 5. " DAR ,Disable Automatic Retransmission" "Enabled,Disabled" bitfld.long 0x00 3. " EIE ,Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SIE ,Status Change Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 1. " IE0 ,Interrupt DCAN0INT line 0 Enable" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization mode" "Disabled,Enabled" hgroup.long 0x04++0x3 hide.long 0x0 "ES,Error and Status Register" in rgroup.long 0x08++0x3 line.long 0x0 "ERRC,Error Counter Register" bitfld.long 0x00 15. " RP ,Receive Error Passive" "Below,Reached" hexmask.long.byte 0x00 8.--14. 1. " REC ,Receive Error Counter" hexmask.long.byte 0x00 0.--7. 1. " TEC ,Transmit Error Counter" group.long 0x0C++0x3 line.long 0x0 "BTR,Bit Timing_BRP Extension Register" bitfld.long 0x00 16.--19. " BRPE ,Baud Rate Prescaler Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--14. " TSEG2 ,Time segment after the sample point" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--11. " TSEG1 ,Time segment before the sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 6.--7. " SJW ,Synchronization Jump Width" "0,1,2,3" bitfld.long 0x00 0.--5. " BRP ,Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x10++0x3 line.long 0x0 "INT,Interrupt Register" hexmask.long.byte 0x00 16.--23. 1. " INT1ID ,Interrupt 1 Identifier" hexmask.long.word 0x00 0.--15. 1. " INT0ID ,Interrupt Identifier" group.long 0x14++0x3 line.long 0x0 "TEST,Test Register" bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Disabled,Enabled" bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Disabled,Enabled" bitfld.long 0x00 7. " RX ,Receive Pin" "Bus is dominant,Bus is recessive" textline " " bitfld.long 0x00 5.--6. " TX ,Control of CAN_TX pin" "Normal operation,Monitored,Dominant value,Recessive value" bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled" bitfld.long 0x00 3. " SILENT ,Silent Mode" "Disabled,Enabled" rgroup.long 0x1C++0x3 line.long 0x0 "PARERR,Parity Error Code Register" bitfld.long 0x00 8.--10. " WORD_NUMBER ,Word number where parity error has been detected" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Message object number where parity error has been detected" group.long 0x80++0x3 line.long 0x0 "ABOTR,Auto Bus On Time" group.long 0x84++0x3 line.long 0x0 "TRREQX,Transmission Request X" bitfld.long 0x00 14.--15. " TXRQSTREG8 ,Transmission Request 8 Register" "0,1,2,3" bitfld.long 0x00 12.--13. " TXRQSTREG7 ,Transmission Request 7 Register" "0,1,2,3" bitfld.long 0x00 10.--11. " TXRQSTREG6 ,Transmission Request 6 Register" "0,1,2,3" textline " " bitfld.long 0x00 8.--9. " TXRQSTREG5 ,Transmission Request 5 Register" "0,1,2,3" bitfld.long 0x00 6.--7. " TXRQSTREG4 ,Transmission Request 4 Register" "0,1,2,3" bitfld.long 0x00 4.--5. " TXRQSTREG3 ,Transmission Request 3 Register" "0,1,2,3" textline " " bitfld.long 0x00 2.--3. " TXRQSTREG2 ,Transmission Request 2 Register" "0,1,2,3" bitfld.long 0x00 0.--1. " TXRQSTREG1 ,Transmission Request 1 Register" "0,1,2,3" rgroup.long 0x88++0x3 line.long 0x0 "TRREQ12,Transmission Request 1 2 Register" bitfld.long 0x00 31. " TXRQST[32] ,Transmission Request Bits[32]" "Not requested,Requested" bitfld.long 0x00 30. " TXRQST[31] ,Transmission Request Bits[31]" "Not requested,Requested" textline " " bitfld.long 0x00 29. " TXRQST[30] ,Transmission Request Bits[30]" "Not requested,Requested" bitfld.long 0x00 28. " TXRQST[29] ,Transmission Request Bits[29]" "Not requested,Requested" textline " " bitfld.long 0x00 27. " TXRQST[28] ,Transmission Request Bits[28]" "Not requested,Requested" bitfld.long 0x00 26. " TXRQST[27] ,Transmission Request Bits[27]" "Not requested,Requested" textline " " bitfld.long 0x00 25. " TXRQST[26] ,Transmission Request Bits[26]" "Not requested,Requested" bitfld.long 0x00 24. " TXRQST[25] ,Transmission Request Bits[25]" "Not requested,Requested" textline " " bitfld.long 0x00 23. " TXRQST[24] ,Transmission Request Bits[24]" "Not requested,Requested" bitfld.long 0x00 22. " TXRQST[23] ,Transmission Request Bits[23]" "Not requested,Requested" textline " " bitfld.long 0x00 21. " TXRQST[22] ,Transmission Request Bits[22]" "Not requested,Requested" bitfld.long 0x00 20. " TXRQST[21] ,Transmission Request Bits[21]" "Not requested,Requested" textline " " bitfld.long 0x00 19. " TXRQST[20] ,Transmission Request Bits[20]" "Not requested,Requested" bitfld.long 0x00 18. " TXRQST[19] ,Transmission Request Bits[19]" "Not requested,Requested" textline " " bitfld.long 0x00 17. " TXRQST[18] ,Transmission Request Bits[18]" "Not requested,Requested" bitfld.long 0x00 16. " TXRQST[17] ,Transmission Request Bits[17]" "Not requested,Requested" textline " " bitfld.long 0x00 15. " TXRQST[16] ,Transmission Request Bits[16]" "Not requested,Requested" bitfld.long 0x00 14. " TXRQST[15] ,Transmission Request Bits[15]" "Not requested,Requested" textline " " bitfld.long 0x00 13. " TXRQST[14] ,Transmission Request Bits[14]" "Not requested,Requested" bitfld.long 0x00 12. " TXRQST[13] ,Transmission Request Bits[13]" "Not requested,Requested" textline " " bitfld.long 0x00 11. " TXRQST[12] ,Transmission Request Bits[12]" "Not requested,Requested" bitfld.long 0x00 10. " TXRQST[11] ,Transmission Request Bits[11]" "Not requested,Requested" textline " " bitfld.long 0x00 9. " TXRQST[10] ,Transmission Request Bits[10]" "Not requested,Requested" bitfld.long 0x00 8. " TXRQST[9] ,Transmission Request Bits[9]" "Not requested,Requested" textline " " bitfld.long 0x00 7. " TXRQST[8] ,Transmission Request Bits[8]" "Not requested,Requested" bitfld.long 0x00 6. " TXRQST[7] ,Transmission Request Bits[7]" "Not requested,Requested" textline " " bitfld.long 0x00 5. " TXRQST[6] ,Transmission Request Bits[6]" "Not requested,Requested" bitfld.long 0x00 4. " TXRQST[5] ,Transmission Request Bits[5]" "Not requested,Requested" textline " " bitfld.long 0x00 3. " TXRQST[4] ,Transmission Request Bits[4]" "Not requested,Requested" bitfld.long 0x00 2. " TXRQST[3] ,Transmission Request Bits[3]" "Not requested,Requested" textline " " bitfld.long 0x00 1. " TXRQST[2] ,Transmission Request Bits[2]" "Not requested,Requested" bitfld.long 0x00 0. " TXRQST[1] ,Transmission Request Bits[1]" "Not requested,Requested" rgroup.long 0x8C++0x3 line.long 0x0 "TRREQ34,Transmission Request 3-4" bitfld.long 0x00 31. " TXRQST[64] ,Transmission Request Bits[64]" "Not requested,Requested" bitfld.long 0x00 30. " TXRQST[63] ,Transmission Request Bits[63]" "Not requested,Requested" textline " " bitfld.long 0x00 29. " TXRQST[62] ,Transmission Request Bits[62]" "Not requested,Requested" bitfld.long 0x00 28. " TXRQST[61] ,Transmission Request Bits[61]" "Not requested,Requested" textline " " bitfld.long 0x00 27. " TXRQST[60] ,Transmission Request Bits[60]" "Not requested,Requested" bitfld.long 0x00 26. " TXRQST[59] ,Transmission Request Bits[59]" "Not requested,Requested" textline " " bitfld.long 0x00 25. " TXRQST[58] ,Transmission Request Bits[58]" "Not requested,Requested" bitfld.long 0x00 24. " TXRQST[57] ,Transmission Request Bits[57]" "Not requested,Requested" textline " " bitfld.long 0x00 23. " TXRQST[56] ,Transmission Request Bits[56]" "Not requested,Requested" bitfld.long 0x00 22. " TXRQST[55] ,Transmission Request Bits[55]" "Not requested,Requested" textline " " bitfld.long 0x00 21. " TXRQST[54] ,Transmission Request Bits[54]" "Not requested,Requested" bitfld.long 0x00 20. " TXRQST[53] ,Transmission Request Bits[53]" "Not requested,Requested" textline " " bitfld.long 0x00 19. " TXRQST[52] ,Transmission Request Bits[52]" "Not requested,Requested" bitfld.long 0x00 18. " TXRQST[51] ,Transmission Request Bits[51]" "Not requested,Requested" textline " " bitfld.long 0x00 17. " TXRQST[50] ,Transmission Request Bits[50]" "Not requested,Requested" bitfld.long 0x00 16. " TXRQST[49] ,Transmission Request Bits[49]" "Not requested,Requested" textline " " bitfld.long 0x00 15. " TXRQST[48] ,Transmission Request Bits[48]" "Not requested,Requested" bitfld.long 0x00 14. " TXRQST[47] ,Transmission Request Bits[47]" "Not requested,Requested" textline " " bitfld.long 0x00 13. " TXRQST[46] ,Transmission Request Bits[46]" "Not requested,Requested" bitfld.long 0x00 12. " TXRQST[45] ,Transmission Request Bits[45]" "Not requested,Requested" textline " " bitfld.long 0x00 11. " TXRQST[44] ,Transmission Request Bits[44]" "Not requested,Requested" bitfld.long 0x00 10. " TXRQST[43] ,Transmission Request Bits[43]" "Not requested,Requested" textline " " bitfld.long 0x00 9. " TXRQST[42] ,Transmission Request Bits[42]" "Not requested,Requested" bitfld.long 0x00 8. " TXRQST[41] ,Transmission Request Bits[41]" "Not requested,Requested" textline " " bitfld.long 0x00 7. " TXRQST[40] ,Transmission Request Bits[40]" "Not requested,Requested" bitfld.long 0x00 6. " TXRQST[39] ,Transmission Request Bits[39]" "Not requested,Requested" textline " " bitfld.long 0x00 5. " TXRQST[38] ,Transmission Request Bits[38]" "Not requested,Requested" bitfld.long 0x00 4. " TXRQST[37] ,Transmission Request Bits[37]" "Not requested,Requested" textline " " bitfld.long 0x00 3. " TXRQST[36] ,Transmission Request Bits[36]" "Not requested,Requested" bitfld.long 0x00 2. " TXRQST[35] ,Transmission Request Bits[35]" "Not requested,Requested" textline " " bitfld.long 0x00 1. " TXRQST[34] ,Transmission Request Bits[34]" "Not requested,Requested" bitfld.long 0x00 0. " TXRQST[33] ,Transmission Request Bits[33]" "Not requested,Requested" rgroup.long 0x90++0x3 line.long 0x0 "TRREQ56,Transmission Request 5-6" bitfld.long 0x00 31. " TXRQST[96] ,Transmission Request Bits[96]" "Not requested,Requested" bitfld.long 0x00 30. " TXRQST[95] ,Transmission Request Bits[95]" "Not requested,Requested" textline " " bitfld.long 0x00 29. " TXRQST[94] ,Transmission Request Bits[94]" "Not requested,Requested" bitfld.long 0x00 28. " TXRQST[93] ,Transmission Request Bits[93]" "Not requested,Requested" textline " " bitfld.long 0x00 27. " TXRQST[92] ,Transmission Request Bits[92]" "Not requested,Requested" bitfld.long 0x00 26. " TXRQST[91] ,Transmission Request Bits[91]" "Not requested,Requested" textline " " bitfld.long 0x00 25. " TXRQST[90] ,Transmission Request Bits[90]" "Not requested,Requested" bitfld.long 0x00 24. " TXRQST[89] ,Transmission Request Bits[89]" "Not requested,Requested" textline " " bitfld.long 0x00 23. " TXRQST[88] ,Transmission Request Bits[88]" "Not requested,Requested" bitfld.long 0x00 22. " TXRQST[87] ,Transmission Request Bits[87]" "Not requested,Requested" textline " " bitfld.long 0x00 21. " TXRQST[86] ,Transmission Request Bits[86]" "Not requested,Requested" bitfld.long 0x00 20. " TXRQST[85] ,Transmission Request Bits[85]" "Not requested,Requested" textline " " bitfld.long 0x00 19. " TXRQST[84] ,Transmission Request Bits[84]" "Not requested,Requested" bitfld.long 0x00 18. " TXRQST[83] ,Transmission Request Bits[83]" "Not requested,Requested" textline " " bitfld.long 0x00 17. " TXRQST[82] ,Transmission Request Bits[82]" "Not requested,Requested" bitfld.long 0x00 16. " TXRQST[81] ,Transmission Request Bits[81]" "Not requested,Requested" textline " " bitfld.long 0x00 15. " TXRQST[80] ,Transmission Request Bits[80]" "Not requested,Requested" bitfld.long 0x00 14. " TXRQST[79] ,Transmission Request Bits[79]" "Not requested,Requested" textline " " bitfld.long 0x00 13. " TXRQST[78] ,Transmission Request Bits[78]" "Not requested,Requested" bitfld.long 0x00 12. " TXRQST[77] ,Transmission Request Bits[77]" "Not requested,Requested" textline " " bitfld.long 0x00 11. " TXRQST[76] ,Transmission Request Bits[76]" "Not requested,Requested" bitfld.long 0x00 10. " TXRQST[75] ,Transmission Request Bits[75]" "Not requested,Requested" textline " " bitfld.long 0x00 9. " TXRQST[74] ,Transmission Request Bits[74]" "Not requested,Requested" bitfld.long 0x00 8. " TXRQST[73] ,Transmission Request Bits[73]" "Not requested,Requested" textline " " bitfld.long 0x00 7. " TXRQST[72] ,Transmission Request Bits[72]" "Not requested,Requested" bitfld.long 0x00 6. " TXRQST[71] ,Transmission Request Bits[71]" "Not requested,Requested" textline " " bitfld.long 0x00 5. " TXRQST[70] ,Transmission Request Bits[70]" "Not requested,Requested" bitfld.long 0x00 4. " TXRQST[69] ,Transmission Request Bits[69]" "Not requested,Requested" textline " " bitfld.long 0x00 3. " TXRQST[68] ,Transmission Request Bits[68]" "Not requested,Requested" bitfld.long 0x00 2. " TXRQST[67] ,Transmission Request Bits[67]" "Not requested,Requested" textline " " bitfld.long 0x00 1. " TXRQST[66] ,Transmission Request Bits[66]" "Not requested,Requested" bitfld.long 0x00 0. " TXRQST[65] ,Transmission Request Bits[65]" "Not requested,Requested" rgroup.long 0x94++0x3 line.long 0x0 "TRREQ78,Transmission Request 7-8" bitfld.long 0x00 31. " TXRQST[128] ,Transmission Request Bits[128]" "Not requested,Requested" bitfld.long 0x00 30. " TXRQST[127] ,Transmission Request Bits[127]" "Not requested,Requested" textline " " bitfld.long 0x00 29. " TXRQST[126] ,Transmission Request Bits[126]" "Not requested,Requested" bitfld.long 0x00 28. " TXRQST[125] ,Transmission Request Bits[125]" "Not requested,Requested" textline " " bitfld.long 0x00 27. " TXRQST[124] ,Transmission Request Bits[124]" "Not requested,Requested" bitfld.long 0x00 26. " TXRQST[123] ,Transmission Request Bits[123]" "Not requested,Requested" textline " " bitfld.long 0x00 25. " TXRQST[122] ,Transmission Request Bits[122]" "Not requested,Requested" bitfld.long 0x00 24. " TXRQST[121] ,Transmission Request Bits[121]" "Not requested,Requested" textline " " bitfld.long 0x00 23. " TXRQST[120] ,Transmission Request Bits[120]" "Not requested,Requested" bitfld.long 0x00 22. " TXRQST[119] ,Transmission Request Bits[119]" "Not requested,Requested" textline " " bitfld.long 0x00 21. " TXRQST[118] ,Transmission Request Bits[118]" "Not requested,Requested" bitfld.long 0x00 20. " TXRQST[117] ,Transmission Request Bits[117]" "Not requested,Requested" textline " " bitfld.long 0x00 19. " TXRQST[116] ,Transmission Request Bits[116]" "Not requested,Requested" bitfld.long 0x00 18. " TXRQST[115] ,Transmission Request Bits[115]" "Not requested,Requested" textline " " bitfld.long 0x00 17. " TXRQST[114] ,Transmission Request Bits[114]" "Not requested,Requested" bitfld.long 0x00 16. " TXRQST[113] ,Transmission Request Bits[113]" "Not requested,Requested" textline " " bitfld.long 0x00 15. " TXRQST[112] ,Transmission Request Bits[112]" "Not requested,Requested" bitfld.long 0x00 14. " TXRQST[111] ,Transmission Request Bits[111]" "Not requested,Requested" textline " " bitfld.long 0x00 13. " TXRQST[110] ,Transmission Request Bits[110]" "Not requested,Requested" bitfld.long 0x00 12. " TXRQST[109] ,Transmission Request Bits[109]" "Not requested,Requested" textline " " bitfld.long 0x00 11. " TXRQST[108] ,Transmission Request Bits[108]" "Not requested,Requested" bitfld.long 0x00 10. " TXRQST[107] ,Transmission Request Bits[107]" "Not requested,Requested" textline " " bitfld.long 0x00 9. " TXRQST[106] ,Transmission Request Bits[106]" "Not requested,Requested" bitfld.long 0x00 8. " TXRQST[105] ,Transmission Request Bits[105]" "Not requested,Requested" textline " " bitfld.long 0x00 7. " TXRQST[104] ,Transmission Request Bits[104]" "Not requested,Requested" bitfld.long 0x00 6. " TXRQST[103] ,Transmission Request Bits[103]" "Not requested,Requested" textline " " bitfld.long 0x00 5. " TXRQST[102] ,Transmission Request Bits[102]" "Not requested,Requested" bitfld.long 0x00 4. " TXRQST[101] ,Transmission Request Bits[101]" "Not requested,Requested" textline " " bitfld.long 0x00 3. " TXRQST[100] ,Transmission Request Bits[100]" "Not requested,Requested" bitfld.long 0x00 2. " TXRQST[99] ,Transmission Request Bits[99]" "Not requested,Requested" textline " " bitfld.long 0x00 1. " TXRQST[98] ,Transmission Request Bits[98]" "Not requested,Requested" bitfld.long 0x00 0. " TXRQST[97] ,Transmission Request Bits[97]" "Not requested,Requested" rgroup.long 0x98++0x3 line.long 0x0 "NEWDATX,New Data X" bitfld.long 0x00 14.--15. " NEWDATREG8 ,New Data 8 Register" "0,1,2,3" bitfld.long 0x00 12.--13. " NEWDATREG7 ,New Data 7 Register" "0,1,2,3" bitfld.long 0x00 10.--11. " NEWDATREG6 ,New Data 6 Register" "0,1,2,3" textline " " bitfld.long 0x00 8.--9. " NEWDATREG5 ,New Data 5 Register" "0,1,2,3" bitfld.long 0x00 6.--7. " NEWDATREG4 ,New Data 4 Register" "0,1,2,3" bitfld.long 0x00 4.--5. " NEWDATREG3 ,New Data 3 Register" "0,1,2,3" textline " " bitfld.long 0x00 2.--3. " NEWDATREG2 ,New Data 2 Register" "0,1,2,3" bitfld.long 0x00 0.--1. " NEWDATREG1 ,New Data 1 Register" "0,1,2,3" rgroup.long 0x9C++0x3 line.long 0x0 "NEWDAT12,New Data 1-2" bitfld.long 0x00 31. " NEWDAT[32] ,New Data Bit[32]" "Not requested,Requested" bitfld.long 0x00 30. " NEWDAT[31] ,New Data Bit[31]" "Not requested,Requested" textline " " bitfld.long 0x00 29. " NEWDAT[30] ,New Data Bit[30]" "Not requested,Requested" bitfld.long 0x00 28. " NEWDAT[29] ,New Data Bit[29]" "Not requested,Requested" textline " " bitfld.long 0x00 27. " NEWDAT[28] ,New Data Bit[28]" "Not requested,Requested" bitfld.long 0x00 26. " NEWDAT[27] ,New Data Bit[27]" "Not requested,Requested" textline " " bitfld.long 0x00 25. " NEWDAT[26] ,New Data Bit[26]" "Not requested,Requested" bitfld.long 0x00 24. " NEWDAT[25] ,New Data Bit[25]" "Not requested,Requested" textline " " bitfld.long 0x00 23. " NEWDAT[24] ,New Data Bit[24]" "Not requested,Requested" bitfld.long 0x00 22. " NEWDAT[23] ,New Data Bit[23]" "Not requested,Requested" textline " " bitfld.long 0x00 21. " NEWDAT[22] ,New Data Bit[22]" "Not requested,Requested" bitfld.long 0x00 20. " NEWDAT[21] ,New Data Bit[21]" "Not requested,Requested" textline " " bitfld.long 0x00 19. " NEWDAT[20] ,New Data Bit[20]" "Not requested,Requested" bitfld.long 0x00 18. " NEWDAT[19] ,New Data Bit[19]" "Not requested,Requested" textline " " bitfld.long 0x00 17. " NEWDAT[18] ,New Data Bit[18]" "Not requested,Requested" bitfld.long 0x00 16. " NEWDAT[17] ,New Data Bit[17]" "Not requested,Requested" textline " " bitfld.long 0x00 15. " NEWDAT[16] ,New Data Bit[16]" "Not requested,Requested" bitfld.long 0x00 14. " NEWDAT[15] ,New Data Bit[15]" "Not requested,Requested" textline " " bitfld.long 0x00 13. " NEWDAT[14] ,New Data Bit[14]" "Not requested,Requested" bitfld.long 0x00 12. " NEWDAT[13] ,New Data Bit[13]" "Not requested,Requested" textline " " bitfld.long 0x00 11. " NEWDAT[12] ,New Data Bit[12]" "Not requested,Requested" bitfld.long 0x00 10. " NEWDAT[11] ,New Data Bit[11]" "Not requested,Requested" textline " " bitfld.long 0x00 9. " NEWDAT[10] ,New Data Bit[10]" "Not requested,Requested" bitfld.long 0x00 8. " NEWDAT[9] ,New Data Bit[9]" "Not requested,Requested" textline " " bitfld.long 0x00 7. " NEWDAT[8] ,New Data Bit[8]" "Not requested,Requested" bitfld.long 0x00 6. " NEWDAT[7] ,New Data Bit[7]" "Not requested,Requested" textline " " bitfld.long 0x00 5. " NEWDAT[6] ,New Data Bit[6]" "Not requested,Requested" bitfld.long 0x00 4. " NEWDAT[5] ,New Data Bit[5]" "Not requested,Requested" textline " " bitfld.long 0x00 3. " NEWDAT[4] ,New Data Bit[4]" "Not requested,Requested" bitfld.long 0x00 2. " NEWDAT[3] ,New Data Bit[3]" "Not requested,Requested" textline " " bitfld.long 0x00 1. " NEWDAT[2] ,New Data Bit[2]" "Not requested,Requested" bitfld.long 0x00 0. " NEWDAT[1] ,New Data Bit[1]" "Not requested,Requested" rgroup.long 0xA0++0x3 line.long 0x0 "NEWDAT34,New Data 3-4" bitfld.long 0x00 31. " NEWDAT[64] ,New Data Bit[64]" "Not requested,Requested" bitfld.long 0x00 30. " NEWDAT[63] ,New Data Bit[63]" "Not requested,Requested" textline " " bitfld.long 0x00 29. " NEWDAT[62] ,New Data Bit[62]" "Not requested,Requested" bitfld.long 0x00 28. " NEWDAT[61] ,New Data Bit[61]" "Not requested,Requested" textline " " bitfld.long 0x00 27. " NEWDAT[60] ,New Data Bit[60]" "Not requested,Requested" bitfld.long 0x00 26. " NEWDAT[59] ,New Data Bit[59]" "Not requested,Requested" textline " " bitfld.long 0x00 25. " NEWDAT[58] ,New Data Bit[58]" "Not requested,Requested" bitfld.long 0x00 24. " NEWDAT[57] ,New Data Bit[57]" "Not requested,Requested" textline " " bitfld.long 0x00 23. " NEWDAT[56] ,New Data Bit[56]" "Not requested,Requested" bitfld.long 0x00 22. " NEWDAT[55] ,New Data Bit[55]" "Not requested,Requested" textline " " bitfld.long 0x00 21. " NEWDAT[54] ,New Data Bit[54]" "Not requested,Requested" bitfld.long 0x00 20. " NEWDAT[53] ,New Data Bit[53]" "Not requested,Requested" textline " " bitfld.long 0x00 19. " NEWDAT[52] ,New Data Bit[52]" "Not requested,Requested" bitfld.long 0x00 18. " NEWDAT[51] ,New Data Bit[51]" "Not requested,Requested" textline " " bitfld.long 0x00 17. " NEWDAT[50] ,New Data Bit[50]" "Not requested,Requested" bitfld.long 0x00 16. " NEWDAT[49] ,New Data Bit[49]" "Not requested,Requested" textline " " bitfld.long 0x00 15. " NEWDAT[48] ,New Data Bit[48]" "Not requested,Requested" bitfld.long 0x00 14. " NEWDAT[47] ,New Data Bit[47]" "Not requested,Requested" textline " " bitfld.long 0x00 13. " NEWDAT[46] ,New Data Bit[46]" "Not requested,Requested" bitfld.long 0x00 12. " NEWDAT[45] ,New Data Bit[45]" "Not requested,Requested" textline " " bitfld.long 0x00 11. " NEWDAT[44] ,New Data Bit[44]" "Not requested,Requested" bitfld.long 0x00 10. " NEWDAT[43] ,New Data Bit[43]" "Not requested,Requested" textline " " bitfld.long 0x00 9. " NEWDAT[42] ,New Data Bit[42]" "Not requested,Requested" bitfld.long 0x00 8. " NEWDAT[41] ,New Data Bit[41]" "Not requested,Requested" textline " " bitfld.long 0x00 7. " NEWDAT[40] ,New Data Bit[40]" "Not requested,Requested" bitfld.long 0x00 6. " NEWDAT[39] ,New Data Bit[39]" "Not requested,Requested" textline " " bitfld.long 0x00 5. " NEWDAT[38] ,New Data Bit[38]" "Not requested,Requested" bitfld.long 0x00 4. " NEWDAT[37] ,New Data Bit[37]" "Not requested,Requested" textline " " bitfld.long 0x00 3. " NEWDAT[36] ,New Data Bit[36]" "Not requested,Requested" bitfld.long 0x00 2. " NEWDAT[35] ,New Data Bit[35]" "Not requested,Requested" textline " " bitfld.long 0x00 1. " NEWDAT[34] ,New Data Bit[34]" "Not requested,Requested" bitfld.long 0x00 0. " NEWDAT[33] ,New Data Bit[33]" "Not requested,Requested" rgroup.long 0xA4++0x3 line.long 0x0 "NEWDAT56,New Data 5-6" bitfld.long 0x00 31. " NEWDAT[96] ,New Data Bit[96]" "Not requested,Requested" bitfld.long 0x00 30. " NEWDAT[95] ,New Data Bit[95]" "Not requested,Requested" textline " " bitfld.long 0x00 29. " NEWDAT[94] ,New Data Bit[94]" "Not requested,Requested" bitfld.long 0x00 28. " NEWDAT[93] ,New Data Bit[93]" "Not requested,Requested" textline " " bitfld.long 0x00 27. " NEWDAT[92] ,New Data Bit[92]" "Not requested,Requested" bitfld.long 0x00 26. " NEWDAT[91] ,New Data Bit[91]" "Not requested,Requested" textline " " bitfld.long 0x00 25. " NEWDAT[90] ,New Data Bit[90]" "Not requested,Requested" bitfld.long 0x00 24. " NEWDAT[89] ,New Data Bit[89]" "Not requested,Requested" textline " " bitfld.long 0x00 23. " NEWDAT[88] ,New Data Bit[88]" "Not requested,Requested" bitfld.long 0x00 22. " NEWDAT[87] ,New Data Bit[87]" "Not requested,Requested" textline " " bitfld.long 0x00 21. " NEWDAT[86] ,New Data Bit[86]" "Not requested,Requested" bitfld.long 0x00 20. " NEWDAT[85] ,New Data Bit[85]" "Not requested,Requested" textline " " bitfld.long 0x00 19. " NEWDAT[84] ,New Data Bit[84]" "Not requested,Requested" bitfld.long 0x00 18. " NEWDAT[83] ,New Data Bit[83]" "Not requested,Requested" textline " " bitfld.long 0x00 17. " NEWDAT[82] ,New Data Bit[82]" "Not requested,Requested" bitfld.long 0x00 16. " NEWDAT[81] ,New Data Bit[81]" "Not requested,Requested" textline " " bitfld.long 0x00 15. " NEWDAT[80] ,New Data Bit[80]" "Not requested,Requested" bitfld.long 0x00 14. " NEWDAT[79] ,New Data Bit[79]" "Not requested,Requested" textline " " bitfld.long 0x00 13. " NEWDAT[78] ,New Data Bit[78]" "Not requested,Requested" bitfld.long 0x00 12. " NEWDAT[77] ,New Data Bit[77]" "Not requested,Requested" textline " " bitfld.long 0x00 11. " NEWDAT[76] ,New Data Bit[76]" "Not requested,Requested" bitfld.long 0x00 10. " NEWDAT[75] ,New Data Bit[75]" "Not requested,Requested" textline " " bitfld.long 0x00 9. " NEWDAT[74] ,New Data Bit[74]" "Not requested,Requested" bitfld.long 0x00 8. " NEWDAT[73] ,New Data Bit[73]" "Not requested,Requested" textline " " bitfld.long 0x00 7. " NEWDAT[72] ,New Data Bit[72]" "Not requested,Requested" bitfld.long 0x00 6. " NEWDAT[71] ,New Data Bit[71]" "Not requested,Requested" textline " " bitfld.long 0x00 5. " NEWDAT[70] ,New Data Bit[70]" "Not requested,Requested" bitfld.long 0x00 4. " NEWDAT[69] ,New Data Bit[69]" "Not requested,Requested" textline " " bitfld.long 0x00 3. " NEWDAT[68] ,New Data Bit[68]" "Not requested,Requested" bitfld.long 0x00 2. " NEWDAT[67] ,New Data Bit[67]" "Not requested,Requested" textline " " bitfld.long 0x00 1. " NEWDAT[66] ,New Data Bit[66]" "Not requested,Requested" bitfld.long 0x00 0. " NEWDAT[65] ,New Data Bit[65]" "Not requested,Requested" rgroup.long 0xA8++0x3 line.long 0x0 "NEWDAT78,New Data 7-8" bitfld.long 0x00 31. " NEWDAT[128] ,New Data Bit[128]" "Not requested,Requested" bitfld.long 0x00 30. " NEWDAT[127] ,New Data Bit[127]" "Not requested,Requested" textline " " bitfld.long 0x00 29. " NEWDAT[126] ,New Data Bit[126]" "Not requested,Requested" bitfld.long 0x00 28. " NEWDAT[125] ,New Data Bit[125]" "Not requested,Requested" textline " " bitfld.long 0x00 27. " NEWDAT[124] ,New Data Bit[124]" "Not requested,Requested" bitfld.long 0x00 26. " NEWDAT[123] ,New Data Bit[123]" "Not requested,Requested" textline " " bitfld.long 0x00 25. " NEWDAT[122] ,New Data Bit[122]" "Not requested,Requested" bitfld.long 0x00 24. " NEWDAT[121] ,New Data Bit[121]" "Not requested,Requested" textline " " bitfld.long 0x00 23. " NEWDAT[120] ,New Data Bit[120]" "Not requested,Requested" bitfld.long 0x00 22. " NEWDAT[119] ,New Data Bit[119]" "Not requested,Requested" textline " " bitfld.long 0x00 21. " NEWDAT[118] ,New Data Bit[118]" "Not requested,Requested" bitfld.long 0x00 20. " NEWDAT[117] ,New Data Bit[117]" "Not requested,Requested" textline " " bitfld.long 0x00 19. " NEWDAT[116] ,New Data Bit[116]" "Not requested,Requested" bitfld.long 0x00 18. " NEWDAT[115] ,New Data Bit[115]" "Not requested,Requested" textline " " bitfld.long 0x00 17. " NEWDAT[114] ,New Data Bit[114]" "Not requested,Requested" bitfld.long 0x00 16. " NEWDAT[113] ,New Data Bit[113]" "Not requested,Requested" textline " " bitfld.long 0x00 15. " NEWDAT[112] ,New Data Bit[112]" "Not requested,Requested" bitfld.long 0x00 14. " NEWDAT[111] ,New Data Bit[111]" "Not requested,Requested" textline " " bitfld.long 0x00 13. " NEWDAT[110] ,New Data Bit[110]" "Not requested,Requested" bitfld.long 0x00 12. " NEWDAT[109] ,New Data Bit[109]" "Not requested,Requested" textline " " bitfld.long 0x00 11. " NEWDAT[108] ,New Data Bit[108]" "Not requested,Requested" bitfld.long 0x00 10. " NEWDAT[107] ,New Data Bit[107]" "Not requested,Requested" textline " " bitfld.long 0x00 9. " NEWDAT[106] ,New Data Bit[106]" "Not requested,Requested" bitfld.long 0x00 8. " NEWDAT[105] ,New Data Bit[105]" "Not requested,Requested" textline " " bitfld.long 0x00 7. " NEWDAT[104] ,New Data Bit[104]" "Not requested,Requested" bitfld.long 0x00 6. " NEWDAT[103] ,New Data Bit[103]" "Not requested,Requested" textline " " bitfld.long 0x00 5. " NEWDAT[102] ,New Data Bit[102]" "Not requested,Requested" bitfld.long 0x00 4. " NEWDAT[101] ,New Data Bit[101]" "Not requested,Requested" textline " " bitfld.long 0x00 3. " NEWDAT[100] ,New Data Bit[100]" "Not requested,Requested" bitfld.long 0x00 2. " NEWDAT[99] ,New Data Bit[99]" "Not requested,Requested" textline " " bitfld.long 0x00 1. " NEWDAT[98] ,New Data Bit[98]" "Not requested,Requested" bitfld.long 0x00 0. " NEWDAT[97] ,New Data Bit[97]" "Not requested,Requested" rgroup.long 0xAC++0x3 line.long 0x0 "INTPENX,Interrupt Pending X" bitfld.long 0x00 14.--15. " INTPNDREG8 ,Interrupt Pending 8" "0,1,2,3" bitfld.long 0x00 12.--13. " INTPNDREG7 ,Interrupt Pending 7" "0,1,2,3" bitfld.long 0x00 10.--11. " INTPNDREG6 ,Interrupt Pending 6" "0,1,2,3" textline " " bitfld.long 0x00 8.--9. " INTPNDREG5 ,Interrupt Pending 5 Register" "0,1,2,3" bitfld.long 0x00 6.--7. " INTPNDREG4 ,Interrupt Pending4" "0,1,2,3" bitfld.long 0x00 4.--5. " INTPNDREG3 ,Interrupt Pending3" "0,1,2,3" textline " " bitfld.long 0x00 2.--3. " INTPNDREG2 ,Interrupt Pending2 Register" "0,1,2,3" bitfld.long 0x00 0.--1. " INTPNDREG1 ,Interrupt Pending1" "0,1,2,3" rgroup.long 0xB0++0x3 line.long 0x0 "INTPEN12,Interrupt Pending 1-2" bitfld.long 0x00 31. " INTPND[32] ,Interrupt Pending Bit[32]" "No interrupt,Interrupt" bitfld.long 0x00 30. " INTPND[31] ,Interrupt Pending Bit[31]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 29. " INTPND[30] ,Interrupt Pending Bit[30]" "No interrupt,Interrupt" bitfld.long 0x00 28. " INTPND[29] ,Interrupt Pending Bit[29]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " INTPND[28] ,Interrupt Pending Bit[28]" "No interrupt,Interrupt" bitfld.long 0x00 26. " INTPND[27] ,Interrupt Pending Bit[27]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 25. " INTPND[26] ,Interrupt Pending Bit[26]" "No interrupt,Interrupt" bitfld.long 0x00 24. " INTPND[25] ,Interrupt Pending Bit[25]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " INTPND[24] ,Interrupt Pending Bit[24]" "No interrupt,Interrupt" bitfld.long 0x00 22. " INTPND[23] ,Interrupt Pending Bit[23]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 21. " INTPND[22] ,Interrupt Pending Bit[22]" "No interrupt,Interrupt" bitfld.long 0x00 20. " INTPND[21] ,Interrupt Pending Bit[21]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " INTPND[20] ,Interrupt Pending Bit[20]" "No interrupt,Interrupt" bitfld.long 0x00 18. " INTPND[19] ,Interrupt Pending Bit[19]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 17. " INTPND[18] ,Interrupt Pending Bit[18]" "No interrupt,Interrupt" bitfld.long 0x00 16. " INTPND[17] ,Interrupt Pending Bit[17]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 15. " INTPND[16] ,Interrupt Pending Bit[16]" "No interrupt,Interrupt" bitfld.long 0x00 14. " INTPND[15] ,Interrupt Pending Bit[15]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 13. " INTPND[14] ,Interrupt Pending Bit[14]" "No interrupt,Interrupt" bitfld.long 0x00 12. " INTPND[13] ,Interrupt Pending Bit[13]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " INTPND[12] ,Interrupt Pending Bit[12]" "No interrupt,Interrupt" bitfld.long 0x00 10. " INTPND[11] ,Interrupt Pending Bit[11]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 9. " INTPND[10] ,Interrupt Pending Bit[10]" "No interrupt,Interrupt" bitfld.long 0x00 8. " INTPND[9] ,Interrupt Pending Bit[9]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 7. " INTPND[8] ,Interrupt Pending Bit[8]" "No interrupt,Interrupt" bitfld.long 0x00 6. " INTPND[7] ,Interrupt Pending Bit[7]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 5. " INTPND[6] ,Interrupt Pending Bit[6]" "No interrupt,Interrupt" bitfld.long 0x00 4. " INTPND[5] ,Interrupt Pending Bit[5]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " INTPND[4] ,Interrupt Pending Bit[4]" "No interrupt,Interrupt" bitfld.long 0x00 2. " INTPND[3] ,Interrupt Pending Bit[3]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " INTPND[2] ,Interrupt Pending Bit[2]" "No interrupt,Interrupt" bitfld.long 0x00 0. " INTPND[1] ,Interrupt Pending Bit[1]" "No interrupt,Interrupt" rgroup.long 0xB4++0x3 line.long 0x0 "INTPEN34,Interrupt Pending 3-4" bitfld.long 0x00 31. " INTPND[64] ,Interrupt Pending Bit[64]" "No interrupt,Interrupt" bitfld.long 0x00 30. " INTPND[63] ,Interrupt Pending Bit[63]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 29. " INTPND[62] ,Interrupt Pending Bit[62]" "No interrupt,Interrupt" bitfld.long 0x00 28. " INTPND[61] ,Interrupt Pending Bit[61]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " INTPND[60] ,Interrupt Pending Bit[60]" "No interrupt,Interrupt" bitfld.long 0x00 26. " INTPND[59] ,Interrupt Pending Bit[59]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 25. " INTPND[58] ,Interrupt Pending Bit[58]" "No interrupt,Interrupt" bitfld.long 0x00 24. " INTPND[57] ,Interrupt Pending Bit[57]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " INTPND[56] ,Interrupt Pending Bit[56]" "No interrupt,Interrupt" bitfld.long 0x00 22. " INTPND[55] ,Interrupt Pending Bit[55]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 21. " INTPND[54] ,Interrupt Pending Bit[54]" "No interrupt,Interrupt" bitfld.long 0x00 20. " INTPND[53] ,Interrupt Pending Bit[53]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " INTPND[52] ,Interrupt Pending Bit[52]" "No interrupt,Interrupt" bitfld.long 0x00 18. " INTPND[51] ,Interrupt Pending Bit[51]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 17. " INTPND[50] ,Interrupt Pending Bit[50]" "No interrupt,Interrupt" bitfld.long 0x00 16. " INTPND[49] ,Interrupt Pending Bit[49]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 15. " INTPND[48] ,Interrupt Pending Bit[48]" "No interrupt,Interrupt" bitfld.long 0x00 14. " INTPND[47] ,Interrupt Pending Bit[47]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 13. " INTPND[46] ,Interrupt Pending Bit[46]" "No interrupt,Interrupt" bitfld.long 0x00 12. " INTPND[45] ,Interrupt Pending Bit[45]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " INTPND[44] ,Interrupt Pending Bit[44]" "No interrupt,Interrupt" bitfld.long 0x00 10. " INTPND[43] ,Interrupt Pending Bit[43]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 9. " INTPND[42] ,Interrupt Pending Bit[42]" "No interrupt,Interrupt" bitfld.long 0x00 8. " INTPND[41] ,Interrupt Pending Bit[41]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 7. " INTPND[40] ,Interrupt Pending Bit[40]" "No interrupt,Interrupt" bitfld.long 0x00 6. " INTPND[39] ,Interrupt Pending Bit[39]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 5. " INTPND[38] ,Interrupt Pending Bit[38]" "No interrupt,Interrupt" bitfld.long 0x00 4. " INTPND[37] ,Interrupt Pending Bit[37]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " INTPND[36] ,Interrupt Pending Bit[36]" "No interrupt,Interrupt" bitfld.long 0x00 2. " INTPND[35] ,Interrupt Pending Bit[35]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " INTPND[34] ,Interrupt Pending Bit[34]" "No interrupt,Interrupt" bitfld.long 0x00 0. " INTPND[33] ,Interrupt Pending Bit[33]" "No interrupt,Interrupt" rgroup.long 0xB8++0x3 line.long 0x0 "INTPEN56,Interrupt Pending 5-6" bitfld.long 0x00 31. " INTPND[96] ,Interrupt Pending Bit[96]" "No interrupt,Interrupt" bitfld.long 0x00 30. " INTPND[95] ,Interrupt Pending Bit[95]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 29. " INTPND[94] ,Interrupt Pending Bit[94]" "No interrupt,Interrupt" bitfld.long 0x00 28. " INTPND[93] ,Interrupt Pending Bit[93]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " INTPND[92] ,Interrupt Pending Bit[92]" "No interrupt,Interrupt" bitfld.long 0x00 26. " INTPND[91] ,Interrupt Pending Bit[91]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 25. " INTPND[90] ,Interrupt Pending Bit[90]" "No interrupt,Interrupt" bitfld.long 0x00 24. " INTPND[89] ,Interrupt Pending Bit[89]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " INTPND[88] ,Interrupt Pending Bit[88]" "No interrupt,Interrupt" bitfld.long 0x00 22. " INTPND[87] ,Interrupt Pending Bit[87]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 21. " INTPND[86] ,Interrupt Pending Bit[86]" "No interrupt,Interrupt" bitfld.long 0x00 20. " INTPND[85] ,Interrupt Pending Bit[85]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " INTPND[84] ,Interrupt Pending Bit[84]" "No interrupt,Interrupt" bitfld.long 0x00 18. " INTPND[83] ,Interrupt Pending Bit[83]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 17. " INTPND[82] ,Interrupt Pending Bit[82]" "No interrupt,Interrupt" bitfld.long 0x00 16. " INTPND[81] ,Interrupt Pending Bit[81]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 15. " INTPND[80] ,Interrupt Pending Bit[80]" "No interrupt,Interrupt" bitfld.long 0x00 14. " INTPND[79] ,Interrupt Pending Bit[79]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 13. " INTPND[78] ,Interrupt Pending Bit[78]" "No interrupt,Interrupt" bitfld.long 0x00 12. " INTPND[77] ,Interrupt Pending Bit[77]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " INTPND[76] ,Interrupt Pending Bit[76]" "No interrupt,Interrupt" bitfld.long 0x00 10. " INTPND[75] ,Interrupt Pending Bit[75]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 9. " INTPND[74] ,Interrupt Pending Bit[74]" "No interrupt,Interrupt" bitfld.long 0x00 8. " INTPND[73] ,Interrupt Pending Bit[73]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 7. " INTPND[72] ,Interrupt Pending Bit[72]" "No interrupt,Interrupt" bitfld.long 0x00 6. " INTPND[71] ,Interrupt Pending Bit[71]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 5. " INTPND[70] ,Interrupt Pending Bit[70]" "No interrupt,Interrupt" bitfld.long 0x00 4. " INTPND[69] ,Interrupt Pending Bit[69]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " INTPND[68] ,Interrupt Pending Bit[68]" "No interrupt,Interrupt" bitfld.long 0x00 2. " INTPND[67] ,Interrupt Pending Bit[67]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " INTPND[66] ,Interrupt Pending Bit[66]" "No interrupt,Interrupt" bitfld.long 0x00 0. " INTPND[65] ,Interrupt Pending Bit[65]" "No interrupt,Interrupt" rgroup.long 0xBC++0x3 line.long 0x0 "INTPEN78,Interrupt Pending 7-8" bitfld.long 0x00 31. " INTPND[128] ,Interrupt Pending Bit[128]" "No interrupt,Interrupt" bitfld.long 0x00 30. " INTPND[127] ,Interrupt Pending Bit[127]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 29. " INTPND[126] ,Interrupt Pending Bit[126]" "No interrupt,Interrupt" bitfld.long 0x00 28. " INTPND[125] ,Interrupt Pending Bit[125]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " INTPND[124] ,Interrupt Pending Bit[124]" "No interrupt,Interrupt" bitfld.long 0x00 26. " INTPND[123] ,Interrupt Pending Bit[123]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 25. " INTPND[122] ,Interrupt Pending Bit[122]" "No interrupt,Interrupt" bitfld.long 0x00 24. " INTPND[121] ,Interrupt Pending Bit[121]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " INTPND[120] ,Interrupt Pending Bit[120]" "No interrupt,Interrupt" bitfld.long 0x00 22. " INTPND[119] ,Interrupt Pending Bit[119]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 21. " INTPND[118] ,Interrupt Pending Bit[118]" "No interrupt,Interrupt" bitfld.long 0x00 20. " INTPND[117] ,Interrupt Pending Bit[117]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " INTPND[116] ,Interrupt Pending Bit[116]" "No interrupt,Interrupt" bitfld.long 0x00 18. " INTPND[115] ,Interrupt Pending Bit[115]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 17. " INTPND[114] ,Interrupt Pending Bit[114]" "No interrupt,Interrupt" bitfld.long 0x00 16. " INTPND[113] ,Interrupt Pending Bit[113]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 15. " INTPND[112] ,Interrupt Pending Bit[112]" "No interrupt,Interrupt" bitfld.long 0x00 14. " INTPND[111] ,Interrupt Pending Bit[111]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 13. " INTPND[110] ,Interrupt Pending Bit[110]" "No interrupt,Interrupt" bitfld.long 0x00 12. " INTPND[109] ,Interrupt Pending Bit[109]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " INTPND[108] ,Interrupt Pending Bit[108]" "No interrupt,Interrupt" bitfld.long 0x00 10. " INTPND[107] ,Interrupt Pending Bit[107]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 9. " INTPND[106] ,Interrupt Pending Bit[106]" "No interrupt,Interrupt" bitfld.long 0x00 8. " INTPND[105] ,Interrupt Pending Bit[105]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 7. " INTPND[104] ,Interrupt Pending Bit[104]" "No interrupt,Interrupt" bitfld.long 0x00 6. " INTPND[103] ,Interrupt Pending Bit[103]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 5. " INTPND[102] ,Interrupt Pending Bit[102]" "No interrupt,Interrupt" bitfld.long 0x00 4. " INTPND[101] ,Interrupt Pending Bit[101]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " INTPND[100] ,Interrupt Pending Bit[100]" "No interrupt,Interrupt" bitfld.long 0x00 2. " INTPND[99] ,Interrupt Pending Bit[99]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " INTPND[98] ,Interrupt Pending Bit[98]" "No interrupt,Interrupt" bitfld.long 0x00 0. " INTPND[97] ,Interrupt Pending Bit[97]" "No interrupt,Interrupt" rgroup.long 0xC0++0x3 line.long 0x0 "MSGVALX,Message Valid X" bitfld.long 0x00 14.--15. " MSGVALREG8 ,Message Valid 8 Register" "0,1,2,3" bitfld.long 0x00 12.--13. " MSGVALREG7 ,Message Valid 7 Register" "0,1,2,3" bitfld.long 0x00 10.--11. " MSGVALREG6 ,Message Valid 6 Register" "0,1,2,3" textline " " bitfld.long 0x00 8.--9. " MSGVALREG5 ,Message Valid 5 Register" "0,1,2,3" bitfld.long 0x00 6.--7. " MSGVALREG4 ,Message Valid 4 Register" "0,1,2,3" bitfld.long 0x00 4.--5. " MSGVALREG3 ,Message Valid 3 Register" "0,1,2,3" textline " " bitfld.long 0x00 2.--3. " MSGVALREG2 ,Message Valid 2 Register" "0,1,2,3" bitfld.long 0x00 0.--1. " MSGVALREG1 ,Message Valid 1 Register" "0,1,2,3" rgroup.long 0xC4++0x3 line.long 0x0 "MSGVAL12,Message Valid 2-1" bitfld.long 0x00 31. " MSGVAL[32] ,Message Valid Bit[32]" "Ignored,Configured" bitfld.long 0x00 30. " MSGVAL[31] ,Message Valid Bit[31]" "Ignored,Configured" textline " " bitfld.long 0x00 29. " MSGVAL[30] ,Message Valid Bit[30]" "Ignored,Configured" bitfld.long 0x00 28. " MSGVAL[29] ,Message Valid Bit[29]" "Ignored,Configured" textline " " bitfld.long 0x00 27. " MSGVAL[28] ,Message Valid Bit[28]" "Ignored,Configured" bitfld.long 0x00 26. " MSGVAL[27] ,Message Valid Bit[27]" "Ignored,Configured" textline " " bitfld.long 0x00 25. " MSGVAL[26] ,Message Valid Bit[26]" "Ignored,Configured" bitfld.long 0x00 24. " MSGVAL[25] ,Message Valid Bit[25]" "Ignored,Configured" textline " " bitfld.long 0x00 23. " MSGVAL[24] ,Message Valid Bit[24]" "Ignored,Configured" bitfld.long 0x00 22. " MSGVAL[23] ,Message Valid Bit[23]" "Ignored,Configured" textline " " bitfld.long 0x00 21. " MSGVAL[22] ,Message Valid Bit[22]" "Ignored,Configured" bitfld.long 0x00 20. " MSGVAL[21] ,Message Valid Bit[21]" "Ignored,Configured" textline " " bitfld.long 0x00 19. " MSGVAL[20] ,Message Valid Bit[20]" "Ignored,Configured" bitfld.long 0x00 18. " MSGVAL[19] ,Message Valid Bit[19]" "Ignored,Configured" textline " " bitfld.long 0x00 17. " MSGVAL[18] ,Message Valid Bit[18]" "Ignored,Configured" bitfld.long 0x00 16. " MSGVAL[17] ,Message Valid Bit[17]" "Ignored,Configured" textline " " bitfld.long 0x00 15. " MSGVAL[16] ,Message Valid Bit[16]" "Ignored,Configured" bitfld.long 0x00 14. " MSGVAL[15] ,Message Valid Bit[15]" "Ignored,Configured" textline " " bitfld.long 0x00 13. " MSGVAL[14] ,Message Valid Bit[14]" "Ignored,Configured" bitfld.long 0x00 12. " MSGVAL[13] ,Message Valid Bit[13]" "Ignored,Configured" textline " " bitfld.long 0x00 11. " MSGVAL[12] ,Message Valid Bit[12]" "Ignored,Configured" bitfld.long 0x00 10. " MSGVAL[11] ,Message Valid Bit[11]" "Ignored,Configured" textline " " bitfld.long 0x00 9. " MSGVAL[10] ,Message Valid Bit[10]" "Ignored,Configured" bitfld.long 0x00 8. " MSGVAL[9] ,Message Valid Bit[9]" "Ignored,Configured" textline " " bitfld.long 0x00 7. " MSGVAL[8] ,Message Valid Bit[8]" "Ignored,Configured" bitfld.long 0x00 6. " MSGVAL[7] ,Message Valid Bit[7]" "Ignored,Configured" textline " " bitfld.long 0x00 5. " MSGVAL[6] ,Message Valid Bit[6]" "Ignored,Configured" bitfld.long 0x00 4. " MSGVAL[5] ,Message Valid Bit[5]" "Ignored,Configured" textline " " bitfld.long 0x00 3. " MSGVAL[4] ,Message Valid Bit[4]" "Ignored,Configured" bitfld.long 0x00 2. " MSGVAL[3] ,Message Valid Bit[3]" "Ignored,Configured" textline " " bitfld.long 0x00 1. " MSGVAL[2] ,Message Valid Bit[2]" "Ignored,Configured" bitfld.long 0x00 0. " MSGVAL[1] ,Message Valid Bit[1]" "Ignored,Configured" rgroup.long 0xC8++0x3 line.long 0x0 "MSGVAL34,Message Valid 4-3" bitfld.long 0x00 31. " MSGVAL[64] ,Message Valid Bit[64]" "Ignored,Configured" bitfld.long 0x00 30. " MSGVAL[63] ,Message Valid Bit[63]" "Ignored,Configured" textline " " bitfld.long 0x00 29. " MSGVAL[62] ,Message Valid Bit[62]" "Ignored,Configured" bitfld.long 0x00 28. " MSGVAL[61] ,Message Valid Bit[61]" "Ignored,Configured" textline " " bitfld.long 0x00 27. " MSGVAL[60] ,Message Valid Bit[60]" "Ignored,Configured" bitfld.long 0x00 26. " MSGVAL[59] ,Message Valid Bit[59]" "Ignored,Configured" textline " " bitfld.long 0x00 25. " MSGVAL[58] ,Message Valid Bit[58]" "Ignored,Configured" bitfld.long 0x00 24. " MSGVAL[57] ,Message Valid Bit[57]" "Ignored,Configured" textline " " bitfld.long 0x00 23. " MSGVAL[56] ,Message Valid Bit[56]" "Ignored,Configured" bitfld.long 0x00 22. " MSGVAL[55] ,Message Valid Bit[55]" "Ignored,Configured" textline " " bitfld.long 0x00 21. " MSGVAL[54] ,Message Valid Bit[54]" "Ignored,Configured" bitfld.long 0x00 20. " MSGVAL[53] ,Message Valid Bit[53]" "Ignored,Configured" textline " " bitfld.long 0x00 19. " MSGVAL[52] ,Message Valid Bit[52]" "Ignored,Configured" bitfld.long 0x00 18. " MSGVAL[51] ,Message Valid Bit[51]" "Ignored,Configured" textline " " bitfld.long 0x00 17. " MSGVAL[50] ,Message Valid Bit[50]" "Ignored,Configured" bitfld.long 0x00 16. " MSGVAL[49] ,Message Valid Bit[49]" "Ignored,Configured" textline " " bitfld.long 0x00 15. " MSGVAL[48] ,Message Valid Bit[48]" "Ignored,Configured" bitfld.long 0x00 14. " MSGVAL[47] ,Message Valid Bit[47]" "Ignored,Configured" textline " " bitfld.long 0x00 13. " MSGVAL[46] ,Message Valid Bit[46]" "Ignored,Configured" bitfld.long 0x00 12. " MSGVAL[45] ,Message Valid Bit[45]" "Ignored,Configured" textline " " bitfld.long 0x00 11. " MSGVAL[44] ,Message Valid Bit[44]" "Ignored,Configured" bitfld.long 0x00 10. " MSGVAL[43] ,Message Valid Bit[43]" "Ignored,Configured" textline " " bitfld.long 0x00 9. " MSGVAL[42] ,Message Valid Bit[42]" "Ignored,Configured" bitfld.long 0x00 8. " MSGVAL[41] ,Message Valid Bit[41]" "Ignored,Configured" textline " " bitfld.long 0x00 7. " MSGVAL[40] ,Message Valid Bit[40]" "Ignored,Configured" bitfld.long 0x00 6. " MSGVAL[39] ,Message Valid Bit[39]" "Ignored,Configured" textline " " bitfld.long 0x00 5. " MSGVAL[38] ,Message Valid Bit[38]" "Ignored,Configured" bitfld.long 0x00 4. " MSGVAL[37] ,Message Valid Bit[37]" "Ignored,Configured" textline " " bitfld.long 0x00 3. " MSGVAL[36] ,Message Valid Bit[36]" "Ignored,Configured" bitfld.long 0x00 2. " MSGVAL[35] ,Message Valid Bit[35]" "Ignored,Configured" textline " " bitfld.long 0x00 1. " MSGVAL[34] ,Message Valid Bit[34]" "Ignored,Configured" bitfld.long 0x00 0. " MSGVAL[33] ,Message Valid Bit[33]" "Ignored,Configured" rgroup.long 0xCC++0x3 line.long 0x0 "MSGVAL56,Message Valid 6-5" bitfld.long 0x00 31. " MSGVAL[96] ,Message Valid Bit[96]" "Ignored,Configured" bitfld.long 0x00 30. " MSGVAL[95] ,Message Valid Bit[95]" "Ignored,Configured" textline " " bitfld.long 0x00 29. " MSGVAL[94] ,Message Valid Bit[94]" "Ignored,Configured" bitfld.long 0x00 28. " MSGVAL[93] ,Message Valid Bit[93]" "Ignored,Configured" textline " " bitfld.long 0x00 27. " MSGVAL[92] ,Message Valid Bit[92]" "Ignored,Configured" bitfld.long 0x00 26. " MSGVAL[91] ,Message Valid Bit[91]" "Ignored,Configured" textline " " bitfld.long 0x00 25. " MSGVAL[90] ,Message Valid Bit[90]" "Ignored,Configured" bitfld.long 0x00 24. " MSGVAL[89] ,Message Valid Bit[89]" "Ignored,Configured" textline " " bitfld.long 0x00 23. " MSGVAL[88] ,Message Valid Bit[88]" "Ignored,Configured" bitfld.long 0x00 22. " MSGVAL[87] ,Message Valid Bit[87]" "Ignored,Configured" textline " " bitfld.long 0x00 21. " MSGVAL[86] ,Message Valid Bit[86]" "Ignored,Configured" bitfld.long 0x00 20. " MSGVAL[85] ,Message Valid Bit[85]" "Ignored,Configured" textline " " bitfld.long 0x00 19. " MSGVAL[84] ,Message Valid Bit[84]" "Ignored,Configured" bitfld.long 0x00 18. " MSGVAL[83] ,Message Valid Bit[83]" "Ignored,Configured" textline " " bitfld.long 0x00 17. " MSGVAL[82] ,Message Valid Bit[82]" "Ignored,Configured" bitfld.long 0x00 16. " MSGVAL[81] ,Message Valid Bit[81]" "Ignored,Configured" textline " " bitfld.long 0x00 15. " MSGVAL[80] ,Message Valid Bit[80]" "Ignored,Configured" bitfld.long 0x00 14. " MSGVAL[79] ,Message Valid Bit[79]" "Ignored,Configured" textline " " bitfld.long 0x00 13. " MSGVAL[78] ,Message Valid Bit[78]" "Ignored,Configured" bitfld.long 0x00 12. " MSGVAL[77] ,Message Valid Bit[77]" "Ignored,Configured" textline " " bitfld.long 0x00 11. " MSGVAL[76] ,Message Valid Bit[76]" "Ignored,Configured" bitfld.long 0x00 10. " MSGVAL[75] ,Message Valid Bit[75]" "Ignored,Configured" textline " " bitfld.long 0x00 9. " MSGVAL[74] ,Message Valid Bit[74]" "Ignored,Configured" bitfld.long 0x00 8. " MSGVAL[73] ,Message Valid Bit[73]" "Ignored,Configured" textline " " bitfld.long 0x00 7. " MSGVAL[72] ,Message Valid Bit[72]" "Ignored,Configured" bitfld.long 0x00 6. " MSGVAL[71] ,Message Valid Bit[71]" "Ignored,Configured" textline " " bitfld.long 0x00 5. " MSGVAL[70] ,Message Valid Bit[70]" "Ignored,Configured" bitfld.long 0x00 4. " MSGVAL[69] ,Message Valid Bit[69]" "Ignored,Configured" textline " " bitfld.long 0x00 3. " MSGVAL[68] ,Message Valid Bit[68]" "Ignored,Configured" bitfld.long 0x00 2. " MSGVAL[67] ,Message Valid Bit[67]" "Ignored,Configured" textline " " bitfld.long 0x00 1. " MSGVAL[66] ,Message Valid Bit[66]" "Ignored,Configured" bitfld.long 0x00 0. " MSGVAL[65] ,Message Valid Bit[65]" "Ignored,Configured" rgroup.long 0xD0++0x3 line.long 0x0 "MSGVAL78,Message Valid 8-7" bitfld.long 0x00 31. " MSGVAL[128] ,Message Valid Bit[128]" "Ignored,Configured" bitfld.long 0x00 30. " MSGVAL[127] ,Message Valid Bit[127]" "Ignored,Configured" textline " " bitfld.long 0x00 29. " MSGVAL[126] ,Message Valid Bit[126]" "Ignored,Configured" bitfld.long 0x00 28. " MSGVAL[125] ,Message Valid Bit[125]" "Ignored,Configured" textline " " bitfld.long 0x00 27. " MSGVAL[124] ,Message Valid Bit[124]" "Ignored,Configured" bitfld.long 0x00 26. " MSGVAL[123] ,Message Valid Bit[123]" "Ignored,Configured" textline " " bitfld.long 0x00 25. " MSGVAL[122] ,Message Valid Bit[122]" "Ignored,Configured" bitfld.long 0x00 24. " MSGVAL[121] ,Message Valid Bit[121]" "Ignored,Configured" textline " " bitfld.long 0x00 23. " MSGVAL[120] ,Message Valid Bit[120]" "Ignored,Configured" bitfld.long 0x00 22. " MSGVAL[119] ,Message Valid Bit[119]" "Ignored,Configured" textline " " bitfld.long 0x00 21. " MSGVAL[118] ,Message Valid Bit[118]" "Ignored,Configured" bitfld.long 0x00 20. " MSGVAL[117] ,Message Valid Bit[117]" "Ignored,Configured" textline " " bitfld.long 0x00 19. " MSGVAL[116] ,Message Valid Bit[116]" "Ignored,Configured" bitfld.long 0x00 18. " MSGVAL[115] ,Message Valid Bit[115]" "Ignored,Configured" textline " " bitfld.long 0x00 17. " MSGVAL[114] ,Message Valid Bit[114]" "Ignored,Configured" bitfld.long 0x00 16. " MSGVAL[113] ,Message Valid Bit[113]" "Ignored,Configured" textline " " bitfld.long 0x00 15. " MSGVAL[112] ,Message Valid Bit[112]" "Ignored,Configured" bitfld.long 0x00 14. " MSGVAL[111] ,Message Valid Bit[111]" "Ignored,Configured" textline " " bitfld.long 0x00 13. " MSGVAL[110] ,Message Valid Bit[110]" "Ignored,Configured" bitfld.long 0x00 12. " MSGVAL[109] ,Message Valid Bit[109]" "Ignored,Configured" textline " " bitfld.long 0x00 11. " MSGVAL[108] ,Message Valid Bit[108]" "Ignored,Configured" bitfld.long 0x00 10. " MSGVAL[107] ,Message Valid Bit[107]" "Ignored,Configured" textline " " bitfld.long 0x00 9. " MSGVAL[106] ,Message Valid Bit[106]" "Ignored,Configured" bitfld.long 0x00 8. " MSGVAL[105] ,Message Valid Bit[105]" "Ignored,Configured" textline " " bitfld.long 0x00 7. " MSGVAL[104] ,Message Valid Bit[104]" "Ignored,Configured" bitfld.long 0x00 6. " MSGVAL[103] ,Message Valid Bit[103]" "Ignored,Configured" textline " " bitfld.long 0x00 5. " MSGVAL[102] ,Message Valid Bit[102]" "Ignored,Configured" bitfld.long 0x00 4. " MSGVAL[101] ,Message Valid Bit[101]" "Ignored,Configured" textline " " bitfld.long 0x00 3. " MSGVAL[100] ,Message Valid Bit[100]" "Ignored,Configured" bitfld.long 0x00 2. " MSGVAL[99] ,Message Valid Bit[99]" "Ignored,Configured" textline " " bitfld.long 0x00 1. " MSGVAL[98] ,Message Valid Bit[98]" "Ignored,Configured" bitfld.long 0x00 0. " MSGVAL[97] ,Message Valid Bit[97]" "Ignored,Configured" group.long 0xD8++0x3 line.long 0x0 "INTPNDMX12,IntPndMux 1-2" bitfld.long 0x00 31. " INTPNDMUX[32] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[32]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 30. " INTPNDMUX[31] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[31]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 29. " INTPNDMUX[30] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[30]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 28. " INTPNDMUX[29] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[29]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 27. " INTPNDMUX[28] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[28]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 26. " INTPNDMUX[27] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[27]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 25. " INTPNDMUX[26] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[26]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 24. " INTPNDMUX[25] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[25]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 23. " INTPNDMUX[24] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[24]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 22. " INTPNDMUX[23] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[23]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 21. " INTPNDMUX[22] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[22]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 20. " INTPNDMUX[21] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[21]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 19. " INTPNDMUX[20] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[20]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 18. " INTPNDMUX[19] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[19]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 17. " INTPNDMUX[18] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[18]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 16. " INTPNDMUX[17] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[17]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 15. " INTPNDMUX[16] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[16]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 14. " INTPNDMUX[15] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[15]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 13. " INTPNDMUX[14] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[14]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 12. " INTPNDMUX[13] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[13]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 11. " INTPNDMUX[12] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[12]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 10. " INTPNDMUX[11] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[11]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 9. " INTPNDMUX[10] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[10]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 8. " INTPNDMUX[9] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[9]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 7. " INTPNDMUX[8] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[8]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 6. " INTPNDMUX[7] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[7]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 5. " INTPNDMUX[6] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[6]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 4. " INTPNDMUX[5] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[5]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 3. " INTPNDMUX[4] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[4]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 2. " INTPNDMUX[3] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[3]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 1. " INTPNDMUX[2] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[2]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 0. " INTPNDMUX[1] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[1]" "DCAN0INT,DCAN1INT" group.long 0xDC++0x3 line.long 0x0 "INTPNDMX34,IntPndMux 3-4" bitfld.long 0x00 31. " INTPNDMUX[64] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[64]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 30. " INTPNDMUX[63] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[63]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 29. " INTPNDMUX[62] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[62]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 28. " INTPNDMUX[61] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[61]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 27. " INTPNDMUX[60] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[60]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 26. " INTPNDMUX[59] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[59]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 25. " INTPNDMUX[58] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[58]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 24. " INTPNDMUX[57] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[57]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 23. " INTPNDMUX[56] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[56]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 22. " INTPNDMUX[55] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[55]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 21. " INTPNDMUX[54] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[54]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 20. " INTPNDMUX[53] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[53]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 19. " INTPNDMUX[52] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[52]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 18. " INTPNDMUX[51] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[51]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 17. " INTPNDMUX[50] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[50]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 16. " INTPNDMUX[49] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[49]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 15. " INTPNDMUX[48] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[48]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 14. " INTPNDMUX[47] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[47]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 13. " INTPNDMUX[46] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[46]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 12. " INTPNDMUX[45] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[45]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 11. " INTPNDMUX[44] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[44]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 10. " INTPNDMUX[43] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[43]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 9. " INTPNDMUX[42] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[42]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 8. " INTPNDMUX[41] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[41]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 7. " INTPNDMUX[40] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[40]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 6. " INTPNDMUX[39] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[39]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 5. " INTPNDMUX[38] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[38]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 4. " INTPNDMUX[37] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[37]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 3. " INTPNDMUX[36] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[36]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 2. " INTPNDMUX[35] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[35]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 1. " INTPNDMUX[34] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[34]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 0. " INTPNDMUX[33] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[33]" "DCAN0INT,DCAN1INT" group.long 0xE0++0x3 line.long 0x0 "INTPNDMX56,IntPndMux 5-6" bitfld.long 0x00 31. " INTPNDMUX[96] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[96]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 30. " INTPNDMUX[95] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[95]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 29. " INTPNDMUX[94] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[94]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 28. " INTPNDMUX[93] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[93]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 27. " INTPNDMUX[92] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[92]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 26. " INTPNDMUX[91] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[91]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 25. " INTPNDMUX[90] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[90]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 24. " INTPNDMUX[89] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[89]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 23. " INTPNDMUX[88] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[88]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 22. " INTPNDMUX[87] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[87]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 21. " INTPNDMUX[86] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[86]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 20. " INTPNDMUX[85] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[85]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 19. " INTPNDMUX[84] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[84]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 18. " INTPNDMUX[83] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[83]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 17. " INTPNDMUX[82] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[82]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 16. " INTPNDMUX[81] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[81]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 15. " INTPNDMUX[80] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[80]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 14. " INTPNDMUX[79] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[79]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 13. " INTPNDMUX[78] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[78]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 12. " INTPNDMUX[77] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[77]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 11. " INTPNDMUX[76] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[76]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 10. " INTPNDMUX[75] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[75]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 9. " INTPNDMUX[74] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[74]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 8. " INTPNDMUX[73] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[73]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 7. " INTPNDMUX[72] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[72]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 6. " INTPNDMUX[71] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[71]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 5. " INTPNDMUX[70] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[70]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 4. " INTPNDMUX[69] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[69]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 3. " INTPNDMUX[68] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[68]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 2. " INTPNDMUX[67] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[67]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 1. " INTPNDMUX[66] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[66]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 0. " INTPNDMUX[65] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[65]" "DCAN0INT,DCAN1INT" group.long 0xE4++0x3 line.long 0x0 "INTPNDMX78,IntPndMux 7-8" bitfld.long 0x00 31. " INTPNDMUX[128] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[128]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 30. " INTPNDMUX[127] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[127]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 29. " INTPNDMUX[126] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[126]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 28. " INTPNDMUX[125] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[125]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 27. " INTPNDMUX[124] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[124]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 26. " INTPNDMUX[123] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[123]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 25. " INTPNDMUX[122] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[122]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 24. " INTPNDMUX[121] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[121]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 23. " INTPNDMUX[120] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[120]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 22. " INTPNDMUX[119] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[119]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 21. " INTPNDMUX[118] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[118]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 20. " INTPNDMUX[117] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[117]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 19. " INTPNDMUX[116] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[116]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 18. " INTPNDMUX[115] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[115]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 17. " INTPNDMUX[114] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[114]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 16. " INTPNDMUX[113] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[113]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 15. " INTPNDMUX[112] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[112]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 14. " INTPNDMUX[111] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[111]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 13. " INTPNDMUX[110] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[110]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 12. " INTPNDMUX[109] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[109]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 11. " INTPNDMUX[108] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[108]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 10. " INTPNDMUX[107] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[107]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 9. " INTPNDMUX[106] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[106]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 8. " INTPNDMUX[105] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[105]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 7. " INTPNDMUX[104] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[104]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 6. " INTPNDMUX[103] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[103]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 5. " INTPNDMUX[102] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[102]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 4. " INTPNDMUX[101] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[101]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 3. " INTPNDMUX[100] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[100]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 2. " INTPNDMUX[99] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[99]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 1. " INTPNDMUX[98] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[98]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 0. " INTPNDMUX[97] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[97]" "DCAN0INT,DCAN1INT" width 9. tree "IF1 / IF2" group.long 0x100++0x3 line.long 0x0 "IF1COM,IF1 Command Mask / Command Request Register" bitfld.long 0x00 23. " WR/RD ,Write / Read" "Read,Write" bitfld.long 0x00 22. " MASK ,Access Mask Bits" "Not accessed,Accessed" textline " " bitfld.long 0x00 21. " ARB ,Access Arbitration Bits" "Not accessed,Accessed" bitfld.long 0x00 20. " CONTROL ,Access Control Bits" "Unchanged,Control bits" textline " " bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Low,High" bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Not requested,Requested" textline " " bitfld.long 0x00 17. " DATA_A ,Access Data Bytes 0-3" "Unchanged,Data bytes 0-3" bitfld.long 0x00 16. " DATA_B ,Access Data Bytes 4-7" "Unchanged,Data bytes 4-7" textline " " bitfld.long 0x00 15. " BUSY ,Busy Flag" "Reset,Set" bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA Feature for Subsequent Internal IF1 Update" "No active,Active" textline " " hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Message Number" group.long 0x120++0x3 line.long 0x0 "IF2COM,IF2 Command Mask / Command Request Register" bitfld.long 0x00 23. " WR/RD ,Write / Read" "Read,Write" bitfld.long 0x00 22. " MASK ,Access Mask Bits" "Not accessed,Accessed" textline " " bitfld.long 0x00 21. " ARB ,Access Arbitration Bits" "Not accessed,Accessed" bitfld.long 0x00 20. " CONTROL ,Access Control Bits" "Unchanged,Control bits" textline " " bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Low,High" bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Not requested,Requested" textline " " bitfld.long 0x00 17. " DATA_A ,Access Data Bytes 0-3" "Unchanged,Data bytes 0-3" bitfld.long 0x00 16. " DATA_B ,Access Data Bytes 4-7" "Unchanged,Data bytes 4-7" textline " " bitfld.long 0x00 15. " BUSY ,Busy Flag" "Reset,Set" bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA Feature for Subsequent Internal IF1 Update" "No active,Active" textline " " hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Message Number" group.long 0x104++0x3 line.long 0x0 "IF1MSK,If1 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Not masked,Masked" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Not masked,Masked" textline " " bitfld.long 0x00 28. " MSK[28] ,Identifier Mask 28" "Not masked,Masked" bitfld.long 0x00 27. " MSK[27] ,Identifier Mask 27" "Not masked,Masked" bitfld.long 0x00 26. " MSK[26] ,Identifier Mask 26" "Not masked,Masked" textline " " bitfld.long 0x00 25. " MSK[25] ,Identifier Mask 25" "Not masked,Masked" bitfld.long 0x00 24. " MSK[24] ,Identifier Mask 24" "Not masked,Masked" bitfld.long 0x00 23. " MSK[23] ,Identifier Mask 23" "Not masked,Masked" textline " " bitfld.long 0x00 22. " MSK[22] ,Identifier Mask 22" "Not masked,Masked" bitfld.long 0x00 21. " MSK[21] ,Identifier Mask 21" "Not masked,Masked" bitfld.long 0x00 20. " MSK[20] ,Identifier Mask 20" "Not masked,Masked" textline " " bitfld.long 0x00 19. " MSK[19] ,Identifier Mask 19" "Not masked,Masked" bitfld.long 0x00 18. " MSK[18] ,Identifier Mask 18" "Not masked,Masked" bitfld.long 0x00 17. " MSK[17] ,Identifier Mask 17" "Not masked,Masked" textline " " bitfld.long 0x00 16. " MSK[16] ,Identifier Mask 16" "Not masked,Masked" bitfld.long 0x00 15. " MSK[15] ,Identifier Mask 15" "Not masked,Masked" bitfld.long 0x00 14. " MSK[14] ,Identifier Mask 14" "Not masked,Masked" textline " " bitfld.long 0x00 13. " MSK[13] ,Identifier Mask 13" "Not masked,Masked" bitfld.long 0x00 12. " MSK[12] ,Identifier Mask 12" "Not masked,Masked" bitfld.long 0x00 11. " MSK[11] ,Identifier Mask 11" "Not masked,Masked" textline " " bitfld.long 0x00 10. " MSK[10] ,Identifier Mask 10" "Not masked,Masked" bitfld.long 0x00 9. " MSK[9] ,Identifier Mask 9" "Not masked,Masked" bitfld.long 0x00 8. " MSK[8] ,Identifier Mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MSK[7] ,Identifier Mask 7" "Not masked,Masked" bitfld.long 0x00 6. " MSK[6] ,Identifier Mask 6" "Not masked,Masked" bitfld.long 0x00 5. " MSK[5] ,Identifier Mask 5" "Not masked,Masked" textline " " bitfld.long 0x00 4. " MSK[4] ,Identifier Mask 4" "Not masked,Masked" bitfld.long 0x00 3. " MSK[3] ,Identifier Mask 3" "Not masked,Masked" bitfld.long 0x00 2. " MSK[2] ,Identifier Mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " MSK[1] ,Identifier Mask 1" "Not masked,Masked" bitfld.long 0x00 0. " MSK[0] ,Identifier Mask 0" "Not masked,Masked" group.long 0x124++0x3 line.long 0x0 "IF2MSK,If2 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Not masked,Masked" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Not masked,Masked" textline " " bitfld.long 0x00 28. " MSK[28] ,Identifier Mask 28" "Not masked,Masked" bitfld.long 0x00 27. " MSK[27] ,Identifier Mask 27" "Not masked,Masked" bitfld.long 0x00 26. " MSK[26] ,Identifier Mask 26" "Not masked,Masked" textline " " bitfld.long 0x00 25. " MSK[25] ,Identifier Mask 25" "Not masked,Masked" bitfld.long 0x00 24. " MSK[24] ,Identifier Mask 24" "Not masked,Masked" bitfld.long 0x00 23. " MSK[23] ,Identifier Mask 23" "Not masked,Masked" textline " " bitfld.long 0x00 22. " MSK[22] ,Identifier Mask 22" "Not masked,Masked" bitfld.long 0x00 21. " MSK[21] ,Identifier Mask 21" "Not masked,Masked" bitfld.long 0x00 20. " MSK[20] ,Identifier Mask 20" "Not masked,Masked" textline " " bitfld.long 0x00 19. " MSK[19] ,Identifier Mask 19" "Not masked,Masked" bitfld.long 0x00 18. " MSK[18] ,Identifier Mask 18" "Not masked,Masked" bitfld.long 0x00 17. " MSK[17] ,Identifier Mask 17" "Not masked,Masked" textline " " bitfld.long 0x00 16. " MSK[16] ,Identifier Mask 16" "Not masked,Masked" bitfld.long 0x00 15. " MSK[15] ,Identifier Mask 15" "Not masked,Masked" bitfld.long 0x00 14. " MSK[14] ,Identifier Mask 14" "Not masked,Masked" textline " " bitfld.long 0x00 13. " MSK[13] ,Identifier Mask 13" "Not masked,Masked" bitfld.long 0x00 12. " MSK[12] ,Identifier Mask 12" "Not masked,Masked" bitfld.long 0x00 11. " MSK[11] ,Identifier Mask 11" "Not masked,Masked" textline " " bitfld.long 0x00 10. " MSK[10] ,Identifier Mask 10" "Not masked,Masked" bitfld.long 0x00 9. " MSK[9] ,Identifier Mask 9" "Not masked,Masked" bitfld.long 0x00 8. " MSK[8] ,Identifier Mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MSK[7] ,Identifier Mask 7" "Not masked,Masked" bitfld.long 0x00 6. " MSK[6] ,Identifier Mask 6" "Not masked,Masked" bitfld.long 0x00 5. " MSK[5] ,Identifier Mask 5" "Not masked,Masked" textline " " bitfld.long 0x00 4. " MSK[4] ,Identifier Mask 4" "Not masked,Masked" bitfld.long 0x00 3. " MSK[3] ,Identifier Mask 3" "Not masked,Masked" bitfld.long 0x00 2. " MSK[2] ,Identifier Mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " MSK[1] ,Identifier Mask 1" "Not masked,Masked" bitfld.long 0x00 0. " MSK[0] ,Identifier Mask 0" "Not masked,Masked" group.long 0x108++0x3 line.long 0x0 "IF1ARB,If1 Arbitation Register" bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Ignored,Used" bitfld.long 0x00 30. " XTD ,Extended Identifier" "11-bit-standard,29-bit-extended" bitfld.long 0x00 29. " DIR ,Message direction" "Receive,Transmit" textline " " bitfld.long 0x00 28. " ID[28] ,Message Identifier 28" "29-bit ID,11-bit ID" bitfld.long 0x00 27. " ID[27] ,Message Identifier 27" "29-bit ID,11-bit ID" bitfld.long 0x00 26. " ID[26] ,Message Identifier 26" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 25. " ID[25] ,Message Identifier 25" "29-bit ID,11-bit ID" bitfld.long 0x00 24. " ID[24] ,Message Identifier 24" "29-bit ID,11-bit ID" bitfld.long 0x00 23. " ID[23] ,Message Identifier 23" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 22. " ID[22] ,Message Identifier 22" "29-bit ID,11-bit ID" bitfld.long 0x00 21. " ID[21] ,Message Identifier 21" "29-bit ID,11-bit ID" bitfld.long 0x00 20. " ID[20] ,Message Identifier 20" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 19. " ID[19] ,Message Identifier 19" "29-bit ID,11-bit ID" bitfld.long 0x00 18. " ID[18] ,Message Identifier 18" "29-bit ID,11-bit ID" bitfld.long 0x00 17. " ID[17] ,Message Identifier 17" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 16. " ID[16] ,Message Identifier 16" "29-bit ID,11-bit ID" bitfld.long 0x00 15. " ID[15] ,Message Identifier 15" "29-bit ID,11-bit ID" bitfld.long 0x00 14. " ID[14] ,Message Identifier 14" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 13. " ID[13] ,Message Identifier 13" "29-bit ID,11-bit ID" bitfld.long 0x00 12. " ID[12] ,Message Identifier 12" "29-bit ID,11-bit ID" bitfld.long 0x00 11. " ID[11] ,Message Identifier 11" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 10. " ID[10] ,Message Identifier 10" "29-bit ID,11-bit ID" bitfld.long 0x00 9. " ID[9] ,Message Identifier 9" "29-bit ID,11-bit ID" bitfld.long 0x00 8. " ID[8] ,Message Identifier 8" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 7. " ID[7] ,Message Identifier 7" "29-bit ID,11-bit ID" bitfld.long 0x00 6. " ID[6] ,Message Identifier 6" "29-bit ID,11-bit ID" bitfld.long 0x00 5. " ID[5] ,Message Identifier 5" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 4. " ID[4] ,Message Identifier 4" "29-bit ID,11-bit ID" bitfld.long 0x00 3. " ID[3] ,Message Identifier 3" "29-bit ID,11-bit ID" bitfld.long 0x00 2. " ID[2] ,Message Identifier 2" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 1. " ID[1] ,Message Identifier 1" "29-bit ID,11-bit ID" bitfld.long 0x00 0. " ID[0] ,Message Identifier 0" "29-bit ID,11-bit ID" group.long 0x128++0x3 line.long 0x0 "IF2ARB,If2 Arbitation Register" bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Ignored,Used" bitfld.long 0x00 30. " XTD ,Extended Identifier" "11-bit-standard,29-bit-extended" bitfld.long 0x00 29. " DIR ,Message direction" "Receive,Transmit" textline " " bitfld.long 0x00 28. " ID[28] ,Message Identifier 28" "29-bit ID,11-bit ID" bitfld.long 0x00 27. " ID[27] ,Message Identifier 27" "29-bit ID,11-bit ID" bitfld.long 0x00 26. " ID[26] ,Message Identifier 26" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 25. " ID[25] ,Message Identifier 25" "29-bit ID,11-bit ID" bitfld.long 0x00 24. " ID[24] ,Message Identifier 24" "29-bit ID,11-bit ID" bitfld.long 0x00 23. " ID[23] ,Message Identifier 23" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 22. " ID[22] ,Message Identifier 22" "29-bit ID,11-bit ID" bitfld.long 0x00 21. " ID[21] ,Message Identifier 21" "29-bit ID,11-bit ID" bitfld.long 0x00 20. " ID[20] ,Message Identifier 20" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 19. " ID[19] ,Message Identifier 19" "29-bit ID,11-bit ID" bitfld.long 0x00 18. " ID[18] ,Message Identifier 18" "29-bit ID,11-bit ID" bitfld.long 0x00 17. " ID[17] ,Message Identifier 17" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 16. " ID[16] ,Message Identifier 16" "29-bit ID,11-bit ID" bitfld.long 0x00 15. " ID[15] ,Message Identifier 15" "29-bit ID,11-bit ID" bitfld.long 0x00 14. " ID[14] ,Message Identifier 14" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 13. " ID[13] ,Message Identifier 13" "29-bit ID,11-bit ID" bitfld.long 0x00 12. " ID[12] ,Message Identifier 12" "29-bit ID,11-bit ID" bitfld.long 0x00 11. " ID[11] ,Message Identifier 11" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 10. " ID[10] ,Message Identifier 10" "29-bit ID,11-bit ID" bitfld.long 0x00 9. " ID[9] ,Message Identifier 9" "29-bit ID,11-bit ID" bitfld.long 0x00 8. " ID[8] ,Message Identifier 8" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 7. " ID[7] ,Message Identifier 7" "29-bit ID,11-bit ID" bitfld.long 0x00 6. " ID[6] ,Message Identifier 6" "29-bit ID,11-bit ID" bitfld.long 0x00 5. " ID[5] ,Message Identifier 5" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 4. " ID[4] ,Message Identifier 4" "29-bit ID,11-bit ID" bitfld.long 0x00 3. " ID[3] ,Message Identifier 3" "29-bit ID,11-bit ID" bitfld.long 0x00 2. " ID[2] ,Message Identifier 2" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 1. " ID[1] ,Message Identifier 1" "29-bit ID,11-bit ID" bitfld.long 0x00 0. " ID[0] ,Message Identifier 0" "29-bit ID,11-bit ID" hgroup.long 0x10C++0x3 hide.long 0x0 "IF1MCTL,If1 Message Control Register" in hgroup.long 0x12C++0x3 hide.long 0x0 "IF2MCTL,If2 Message Control Register" in group.long 0x110++0x3 line.long 0x0 "IF1DATA,If1 Data A Register" hexmask.long.byte 0x00 24.--31. 1. " DATA_3 ,Data 3" hexmask.long.byte 0x00 16.--23. 1. " DATA_2 ,Data 2" textline " " hexmask.long.byte 0x00 8.--15. 1. " DATA_1 ,Data 1" hexmask.long.byte 0x00 0.--7. 1. " DATA_0 ,Data 0" group.long 0x114++0x3 line.long 0x0 "IF1DATB,If1 Data B Register" hexmask.long.byte 0x00 24.--31. 1. " DATA_7 ,Data 7" hexmask.long.byte 0x00 16.--23. 1. " DATA_6 ,Data 6" textline " " hexmask.long.byte 0x00 8.--15. 1. " DATA_5 ,Data 5" hexmask.long.byte 0x00 0.--7. 1. " DATA_4 ,Data 4" group.long 0x130++0x3 line.long 0x0 "IF2DATA,If2 Data A Register" hexmask.long.byte 0x00 24.--31. 1. " DATA_3 ,Data 3" hexmask.long.byte 0x00 16.--23. 1. " DATA_2 ,Data 2" textline " " hexmask.long.byte 0x00 8.--15. 1. " DATA_1 ,Data 1" hexmask.long.byte 0x00 0.--7. 1. " DATA_0 ,Data 0" group.long 0x134++0x3 line.long 0x0 "IF2DATB,If2 Data B Register" hexmask.long.byte 0x00 24.--31. 1. " DATA_7 ,Data 7" hexmask.long.byte 0x00 16.--23. 1. " DATA_6 ,Data 6" textline " " hexmask.long.byte 0x00 8.--15. 1. " DATA_5 ,Data 5" hexmask.long.byte 0x00 0.--7. 1. " DATA_4 ,Data 4" tree.end tree "IF 3" group.long 0x140++0x3 line.long 0x0 "IF3OBS,If3 Observation Register" bitfld.long 0x00 15. " IF3_UPD ,IF3 Update Data" "No,Yes" bitfld.long 0x00 12. " IF3_SDB ,IF3 Status of Data B read access" "No access,Access" bitfld.long 0x00 11. " IF3_SDA ,IF3 Status of Data A read access" "No access,Access" textline " " bitfld.long 0x00 10. " IF3_SC ,IF3 Status of Control bits read access" "No access,Access" bitfld.long 0x00 9. " IF3_SA ,IF3 Status of Arbitration data read access" "No access,Access" bitfld.long 0x00 8. " IF3_SM ,IF3 Status of Mask data read access" "No access,Access" textline " " bitfld.long 0x00 4. " DATA_B ,Data B read observation" "No,Yes" bitfld.long 0x00 3. " DATA_A ,Data A read observation" "No,Yes" bitfld.long 0x00 2. " CTRL ,Ctrl read observation" "No,Yes" textline " " bitfld.long 0x00 1. " ARB ,Arbitration data read observation" "No,Yes" bitfld.long 0x00 0. " MASK ,Mask data read observation" "No,Yes" group.long 0x144++0x3 line.long 0x0 "IF3MSK,If3 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Not masked,Masked" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Not masked,Masked" textline " " bitfld.long 0x00 28. " MSK[28] ,Identifier Mask 28" "Not masked,Masked" bitfld.long 0x00 27. " MSK[27] ,Identifier Mask 27" "Not masked,Masked" bitfld.long 0x00 26. " MSK[26] ,Identifier Mask 26" "Not masked,Masked" textline " " bitfld.long 0x00 25. " MSK[25] ,Identifier Mask 25" "Not masked,Masked" bitfld.long 0x00 24. " MSK[24] ,Identifier Mask 24" "Not masked,Masked" bitfld.long 0x00 23. " MSK[23] ,Identifier Mask 23" "Not masked,Masked" textline " " bitfld.long 0x00 22. " MSK[22] ,Identifier Mask 22" "Not masked,Masked" bitfld.long 0x00 21. " MSK[21] ,Identifier Mask 21" "Not masked,Masked" bitfld.long 0x00 20. " MSK[20] ,Identifier Mask 20" "Not masked,Masked" textline " " bitfld.long 0x00 19. " MSK[19] ,Identifier Mask 19" "Not masked,Masked" bitfld.long 0x00 18. " MSK[18] ,Identifier Mask 18" "Not masked,Masked" bitfld.long 0x00 17. " MSK[17] ,Identifier Mask 17" "Not masked,Masked" textline " " bitfld.long 0x00 16. " MSK[16] ,Identifier Mask 16" "Not masked,Masked" bitfld.long 0x00 15. " MSK[15] ,Identifier Mask 15" "Not masked,Masked" bitfld.long 0x00 14. " MSK[14] ,Identifier Mask 14" "Not masked,Masked" textline " " bitfld.long 0x00 13. " MSK[13] ,Identifier Mask 13" "Not masked,Masked" bitfld.long 0x00 12. " MSK[12] ,Identifier Mask 12" "Not masked,Masked" bitfld.long 0x00 11. " MSK[11] ,Identifier Mask 11" "Not masked,Masked" textline " " bitfld.long 0x00 10. " MSK[10] ,Identifier Mask 10" "Not masked,Masked" bitfld.long 0x00 9. " MSK[9] ,Identifier Mask 9" "Not masked,Masked" bitfld.long 0x00 8. " MSK[8] ,Identifier Mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MSK[7] ,Identifier Mask 7" "Not masked,Masked" bitfld.long 0x00 6. " MSK[6] ,Identifier Mask 6" "Not masked,Masked" bitfld.long 0x00 5. " MSK[5] ,Identifier Mask 5" "Not masked,Masked" textline " " bitfld.long 0x00 4. " MSK[4] ,Identifier Mask 4" "Not masked,Masked" bitfld.long 0x00 3. " MSK[3] ,Identifier Mask 3" "Not masked,Masked" bitfld.long 0x00 2. " MSK[2] ,Identifier Mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " MSK[1] ,Identifier Mask 1" "Not masked,Masked" bitfld.long 0x00 0. " MSK[0] ,Identifier Mask 0" "Not masked,Masked" group.long 0x148++0x3 line.long 0x0 "IF3ARB,If3 Arbitation Register" bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Ignored,Used" bitfld.long 0x00 30. " XTD ,Extended Identifier" "11-bit-standard,29-bit-extended" bitfld.long 0x00 29. " DIR ,Message direction" "Receive,Transmit" textline " " bitfld.long 0x00 28. " ID[28] ,Message Identifier 28" "29-bit ID,11-bit ID" bitfld.long 0x00 27. " ID[27] ,Message Identifier 27" "29-bit ID,11-bit ID" bitfld.long 0x00 26. " ID[26] ,Message Identifier 26" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 25. " ID[25] ,Message Identifier 25" "29-bit ID,11-bit ID" bitfld.long 0x00 24. " ID[24] ,Message Identifier 24" "29-bit ID,11-bit ID" bitfld.long 0x00 23. " ID[23] ,Message Identifier 23" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 22. " ID[22] ,Message Identifier 22" "29-bit ID,11-bit ID" bitfld.long 0x00 21. " ID[21] ,Message Identifier 21" "29-bit ID,11-bit ID" bitfld.long 0x00 20. " ID[20] ,Message Identifier 20" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 19. " ID[19] ,Message Identifier 19" "29-bit ID,11-bit ID" bitfld.long 0x00 18. " ID[18] ,Message Identifier 18" "29-bit ID,11-bit ID" bitfld.long 0x00 17. " ID[17] ,Message Identifier 17" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 16. " ID[16] ,Message Identifier 16" "29-bit ID,11-bit ID" bitfld.long 0x00 15. " ID[15] ,Message Identifier 15" "29-bit ID,11-bit ID" bitfld.long 0x00 14. " ID[14] ,Message Identifier 14" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 13. " ID[13] ,Message Identifier 13" "29-bit ID,11-bit ID" bitfld.long 0x00 12. " ID[12] ,Message Identifier 12" "29-bit ID,11-bit ID" bitfld.long 0x00 11. " ID[11] ,Message Identifier 11" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 10. " ID[10] ,Message Identifier 10" "29-bit ID,11-bit ID" bitfld.long 0x00 9. " ID[9] ,Message Identifier 9" "29-bit ID,11-bit ID" bitfld.long 0x00 8. " ID[8] ,Message Identifier 8" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 7. " ID[7] ,Message Identifier 7" "29-bit ID,11-bit ID" bitfld.long 0x00 6. " ID[6] ,Message Identifier 6" "29-bit ID,11-bit ID" bitfld.long 0x00 5. " ID[5] ,Message Identifier 5" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 4. " ID[4] ,Message Identifier 4" "29-bit ID,11-bit ID" bitfld.long 0x00 3. " ID[3] ,Message Identifier 3" "29-bit ID,11-bit ID" bitfld.long 0x00 2. " ID[2] ,Message Identifier 2" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 1. " ID[1] ,Message Identifier 1" "29-bit ID,11-bit ID" bitfld.long 0x00 0. " ID[0] ,Message Identifier 0" "29-bit ID,11-bit ID" group.long 0x14C++0x3 line.long 0x0 "IF3MCTL,If3 Message Control Register" bitfld.long 0x00 15. " NEWDAT ,New Data" "Not written,Wrote" bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not losted,Losted" bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "Not pended,Pended" textline " " bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Not used,Used" bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Disabled,Enabled" bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested" bitfld.long 0x00 7. " EOB ,Data Frame 0-8 bits" "0,1" textline " " bitfld.long 0x00 0.--3. " DLC[3:0] ,Data length code" "0-8 data bits,0-8 data bits,0-8 data bits,0-8 data bits,0-8 data bits,0-8 data bits,0-8 data bits,0-8 data bits,0-8 data bits,8 data bytes,8 data bytes,8 data bytes,8 data bytes,8 data bytes,8 data bytes,8 data bytes" group.long 0x150++0x3 line.long 0x0 "IF3DATA,If3 Data A Register" hexmask.long.byte 0x00 24.--31. 1. " DATA_3 ,Data 3" hexmask.long.byte 0x00 16.--23. 1. " DATA_2 ,Data 2" textline " " hexmask.long.byte 0x00 8.--15. 1. " DATA_1 ,Data 1" hexmask.long.byte 0x00 0.--7. 1. " DATA_0 ,Data 0" group.long 0x154++0x3 line.long 0x0 "IF3DATB,If3 Data B Register" hexmask.long.byte 0x00 24.--31. 1. " DATA_7 ,Data 7" hexmask.long.byte 0x00 16.--23. 1. " DATA_6 ,Data 6" textline " " hexmask.long.byte 0x00 8.--15. 1. " DATA_5 ,Data 5" hexmask.long.byte 0x00 0.--7. 1. " DATA_4 ,Data 4" group.long 0x160++0x3 line.long 0x0 "IF3UPD12,Update enable 1-2 Register" bitfld.long 0x00 31. " IF3UPDATEEN[32] ,IF3 Update Enabled Bit[32]" "Disabled,Enabled" bitfld.long 0x00 30. " IF3UPDATEEN[31] ,IF3 Update Enabled Bit[31]" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " IF3UPDATEEN[30] ,IF3 Update Enabled Bit[30]" "Disabled,Enabled" bitfld.long 0x00 28. " IF3UPDATEEN[29] ,IF3 Update Enabled Bit[29]" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " IF3UPDATEEN[28] ,IF3 Update Enabled Bit[28]" "Disabled,Enabled" bitfld.long 0x00 26. " IF3UPDATEEN[27] ,IF3 Update Enabled Bit[27]" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " IF3UPDATEEN[26] ,IF3 Update Enabled Bit[26]" "Disabled,Enabled" bitfld.long 0x00 24. " IF3UPDATEEN[25] ,IF3 Update Enabled Bit[25]" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " IF3UPDATEEN[24] ,IF3 Update Enabled Bit[24]" "Disabled,Enabled" bitfld.long 0x00 22. " IF3UPDATEEN[23] ,IF3 Update Enabled Bit[23]" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " IF3UPDATEEN[22] ,IF3 Update Enabled Bit[22]" "Disabled,Enabled" bitfld.long 0x00 20. " IF3UPDATEEN[21] ,IF3 Update Enabled Bit[21]" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " IF3UPDATEEN[20] ,IF3 Update Enabled Bit[20]" "Disabled,Enabled" bitfld.long 0x00 18. " IF3UPDATEEN[19] ,IF3 Update Enabled Bit[19]" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " IF3UPDATEEN[18] ,IF3 Update Enabled Bit[18]" "Disabled,Enabled" bitfld.long 0x00 16. " IF3UPDATEEN[17] ,IF3 Update Enabled Bit[17]" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " IF3UPDATEEN[16] ,IF3 Update Enabled Bit[16]" "Disabled,Enabled" bitfld.long 0x00 14. " IF3UPDATEEN[15] ,IF3 Update Enabled Bit[15]" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " IF3UPDATEEN[14] ,IF3 Update Enabled Bit[14]" "Disabled,Enabled" bitfld.long 0x00 12. " IF3UPDATEEN[13] ,IF3 Update Enabled Bit[13]" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " IF3UPDATEEN[12] ,IF3 Update Enabled Bit[12]" "Disabled,Enabled" bitfld.long 0x00 10. " IF3UPDATEEN[11] ,IF3 Update Enabled Bit[11]" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " IF3UPDATEEN[10] ,IF3 Update Enabled Bit[10]" "Disabled,Enabled" bitfld.long 0x00 8. " IF3UPDATEEN[9] ,IF3 Update Enabled Bit[9]" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " IF3UPDATEEN[8] ,IF3 Update Enabled Bit[8]" "Disabled,Enabled" bitfld.long 0x00 6. " IF3UPDATEEN[7] ,IF3 Update Enabled Bit[7]" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " IF3UPDATEEN[6] ,IF3 Update Enabled Bit[6]" "Disabled,Enabled" bitfld.long 0x00 4. " IF3UPDATEEN[5] ,IF3 Update Enabled Bit[5]" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " IF3UPDATEEN[4] ,IF3 Update Enabled Bit[4]" "Disabled,Enabled" bitfld.long 0x00 2. " IF3UPDATEEN[3] ,IF3 Update Enabled Bit[3]" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " IF3UPDATEEN[2] ,IF3 Update Enabled Bit[2]" "Disabled,Enabled" bitfld.long 0x00 0. " IF3UPDATEEN[1] ,IF3 Update Enabled Bit[1]" "Disabled,Enabled" group.long 0x164++0x3 line.long 0x0 "IF3UPD34,Update enable 3-4 Register" bitfld.long 0x00 31. " IF3UPDATEEN[64] ,IF3 Update Enabled Bit[64]" "Disabled,Enabled" bitfld.long 0x00 30. " IF3UPDATEEN[63] ,IF3 Update Enabled Bit[63]" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " IF3UPDATEEN[62] ,IF3 Update Enabled Bit[62]" "Disabled,Enabled" bitfld.long 0x00 28. " IF3UPDATEEN[61] ,IF3 Update Enabled Bit[61]" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " IF3UPDATEEN[60] ,IF3 Update Enabled Bit[60]" "Disabled,Enabled" bitfld.long 0x00 26. " IF3UPDATEEN[59] ,IF3 Update Enabled Bit[59]" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " IF3UPDATEEN[58] ,IF3 Update Enabled Bit[58]" "Disabled,Enabled" bitfld.long 0x00 24. " IF3UPDATEEN[57] ,IF3 Update Enabled Bit[57]" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " IF3UPDATEEN[56] ,IF3 Update Enabled Bit[56]" "Disabled,Enabled" bitfld.long 0x00 22. " IF3UPDATEEN[55] ,IF3 Update Enabled Bit[55]" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " IF3UPDATEEN[54] ,IF3 Update Enabled Bit[54]" "Disabled,Enabled" bitfld.long 0x00 20. " IF3UPDATEEN[53] ,IF3 Update Enabled Bit[53]" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " IF3UPDATEEN[52] ,IF3 Update Enabled Bit[52]" "Disabled,Enabled" bitfld.long 0x00 18. " IF3UPDATEEN[51] ,IF3 Update Enabled Bit[51]" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " IF3UPDATEEN[50] ,IF3 Update Enabled Bit[50]" "Disabled,Enabled" bitfld.long 0x00 16. " IF3UPDATEEN[49] ,IF3 Update Enabled Bit[49]" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " IF3UPDATEEN[48] ,IF3 Update Enabled Bit[48]" "Disabled,Enabled" bitfld.long 0x00 14. " IF3UPDATEEN[47] ,IF3 Update Enabled Bit[47]" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " IF3UPDATEEN[46] ,IF3 Update Enabled Bit[46]" "Disabled,Enabled" bitfld.long 0x00 12. " IF3UPDATEEN[45] ,IF3 Update Enabled Bit[45]" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " IF3UPDATEEN[44] ,IF3 Update Enabled Bit[44]" "Disabled,Enabled" bitfld.long 0x00 10. " IF3UPDATEEN[43] ,IF3 Update Enabled Bit[43]" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " IF3UPDATEEN[42] ,IF3 Update Enabled Bit[42]" "Disabled,Enabled" bitfld.long 0x00 8. " IF3UPDATEEN[41] ,IF3 Update Enabled Bit[41]" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " IF3UPDATEEN[40] ,IF3 Update Enabled Bit[40]" "Disabled,Enabled" bitfld.long 0x00 6. " IF3UPDATEEN[39] ,IF3 Update Enabled Bit[39]" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " IF3UPDATEEN[38] ,IF3 Update Enabled Bit[38]" "Disabled,Enabled" bitfld.long 0x00 4. " IF3UPDATEEN[37] ,IF3 Update Enabled Bit[37]" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " IF3UPDATEEN[36] ,IF3 Update Enabled Bit[36]" "Disabled,Enabled" bitfld.long 0x00 2. " IF3UPDATEEN[35] ,IF3 Update Enabled Bit[35]" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " IF3UPDATEEN[34] ,IF3 Update Enabled Bit[34]" "Disabled,Enabled" bitfld.long 0x00 0. " IF3UPDATEEN[33] ,IF3 Update Enabled Bit[33]" "Disabled,Enabled" group.long 0x168++0x3 line.long 0x0 "IF3UPD56,Update enable 5-6 Register" bitfld.long 0x00 31. " IF3UPDATEEN[96] ,IF3 Update Enabled Bit[96]" "Disabled,Enabled" bitfld.long 0x00 30. " IF3UPDATEEN[95] ,IF3 Update Enabled Bit[95]" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " IF3UPDATEEN[94] ,IF3 Update Enabled Bit[94]" "Disabled,Enabled" bitfld.long 0x00 28. " IF3UPDATEEN[93] ,IF3 Update Enabled Bit[93]" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " IF3UPDATEEN[92] ,IF3 Update Enabled Bit[92]" "Disabled,Enabled" bitfld.long 0x00 26. " IF3UPDATEEN[91] ,IF3 Update Enabled Bit[91]" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " IF3UPDATEEN[90] ,IF3 Update Enabled Bit[90]" "Disabled,Enabled" bitfld.long 0x00 24. " IF3UPDATEEN[89] ,IF3 Update Enabled Bit[89]" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " IF3UPDATEEN[88] ,IF3 Update Enabled Bit[88]" "Disabled,Enabled" bitfld.long 0x00 22. " IF3UPDATEEN[87] ,IF3 Update Enabled Bit[87]" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " IF3UPDATEEN[86] ,IF3 Update Enabled Bit[86]" "Disabled,Enabled" bitfld.long 0x00 20. " IF3UPDATEEN[85] ,IF3 Update Enabled Bit[85]" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " IF3UPDATEEN[84] ,IF3 Update Enabled Bit[84]" "Disabled,Enabled" bitfld.long 0x00 18. " IF3UPDATEEN[83] ,IF3 Update Enabled Bit[83]" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " IF3UPDATEEN[82] ,IF3 Update Enabled Bit[82]" "Disabled,Enabled" bitfld.long 0x00 16. " IF3UPDATEEN[81] ,IF3 Update Enabled Bit[81]" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " IF3UPDATEEN[80] ,IF3 Update Enabled Bit[80]" "Disabled,Enabled" bitfld.long 0x00 14. " IF3UPDATEEN[79] ,IF3 Update Enabled Bit[79]" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " IF3UPDATEEN[78] ,IF3 Update Enabled Bit[78]" "Disabled,Enabled" bitfld.long 0x00 12. " IF3UPDATEEN[77] ,IF3 Update Enabled Bit[77]" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " IF3UPDATEEN[76] ,IF3 Update Enabled Bit[76]" "Disabled,Enabled" bitfld.long 0x00 10. " IF3UPDATEEN[75] ,IF3 Update Enabled Bit[75]" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " IF3UPDATEEN[74] ,IF3 Update Enabled Bit[74]" "Disabled,Enabled" bitfld.long 0x00 8. " IF3UPDATEEN[73] ,IF3 Update Enabled Bit[73]" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " IF3UPDATEEN[72] ,IF3 Update Enabled Bit[72]" "Disabled,Enabled" bitfld.long 0x00 6. " IF3UPDATEEN[71] ,IF3 Update Enabled Bit[71]" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " IF3UPDATEEN[70] ,IF3 Update Enabled Bit[70]" "Disabled,Enabled" bitfld.long 0x00 4. " IF3UPDATEEN[69] ,IF3 Update Enabled Bit[69]" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " IF3UPDATEEN[68] ,IF3 Update Enabled Bit[68]" "Disabled,Enabled" bitfld.long 0x00 2. " IF3UPDATEEN[67] ,IF3 Update Enabled Bit[67]" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " IF3UPDATEEN[66] ,IF3 Update Enabled Bit[66]" "Disabled,Enabled" bitfld.long 0x00 0. " IF3UPDATEEN[65] ,IF3 Update Enabled Bit[65]" "Disabled,Enabled" group.long 0x16C++0x3 line.long 0x0 "IF3UPD78,Update enable 7-8 Register" bitfld.long 0x00 31. " IF3UPDATEEN[128] ,IF3 Update Enabled Bit[128]" "Disabled,Enabled" bitfld.long 0x00 30. " IF3UPDATEEN[127] ,IF3 Update Enabled Bit[127]" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " IF3UPDATEEN[126] ,IF3 Update Enabled Bit[126]" "Disabled,Enabled" bitfld.long 0x00 28. " IF3UPDATEEN[125] ,IF3 Update Enabled Bit[125]" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " IF3UPDATEEN[124] ,IF3 Update Enabled Bit[124]" "Disabled,Enabled" bitfld.long 0x00 26. " IF3UPDATEEN[123] ,IF3 Update Enabled Bit[123]" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " IF3UPDATEEN[122] ,IF3 Update Enabled Bit[122]" "Disabled,Enabled" bitfld.long 0x00 24. " IF3UPDATEEN[121] ,IF3 Update Enabled Bit[121]" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " IF3UPDATEEN[120] ,IF3 Update Enabled Bit[120]" "Disabled,Enabled" bitfld.long 0x00 22. " IF3UPDATEEN[119] ,IF3 Update Enabled Bit[119]" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " IF3UPDATEEN[118] ,IF3 Update Enabled Bit[118]" "Disabled,Enabled" bitfld.long 0x00 20. " IF3UPDATEEN[117] ,IF3 Update Enabled Bit[117]" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " IF3UPDATEEN[116] ,IF3 Update Enabled Bit[116]" "Disabled,Enabled" bitfld.long 0x00 18. " IF3UPDATEEN[115] ,IF3 Update Enabled Bit[115]" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " IF3UPDATEEN[114] ,IF3 Update Enabled Bit[114]" "Disabled,Enabled" bitfld.long 0x00 16. " IF3UPDATEEN[113] ,IF3 Update Enabled Bit[113]" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " IF3UPDATEEN[112] ,IF3 Update Enabled Bit[112]" "Disabled,Enabled" bitfld.long 0x00 14. " IF3UPDATEEN[111] ,IF3 Update Enabled Bit[111]" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " IF3UPDATEEN[110] ,IF3 Update Enabled Bit[110]" "Disabled,Enabled" bitfld.long 0x00 12. " IF3UPDATEEN[109] ,IF3 Update Enabled Bit[109]" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " IF3UPDATEEN[108] ,IF3 Update Enabled Bit[108]" "Disabled,Enabled" bitfld.long 0x00 10. " IF3UPDATEEN[107] ,IF3 Update Enabled Bit[107]" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " IF3UPDATEEN[106] ,IF3 Update Enabled Bit[106]" "Disabled,Enabled" bitfld.long 0x00 8. " IF3UPDATEEN[105] ,IF3 Update Enabled Bit[105]" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " IF3UPDATEEN[104] ,IF3 Update Enabled Bit[104]" "Disabled,Enabled" bitfld.long 0x00 6. " IF3UPDATEEN[103] ,IF3 Update Enabled Bit[103]" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " IF3UPDATEEN[102] ,IF3 Update Enabled Bit[102]" "Disabled,Enabled" bitfld.long 0x00 4. " IF3UPDATEEN[101] ,IF3 Update Enabled Bit[101]" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " IF3UPDATEEN[100] ,IF3 Update Enabled Bit[100]" "Disabled,Enabled" bitfld.long 0x00 2. " IF3UPDATEEN[99] ,IF3 Update Enabled Bit[99]" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " IF3UPDATEEN[98] ,IF3 Update Enabled Bit[98]" "Disabled,Enabled" bitfld.long 0x00 0. " IF3UPDATEEN[97] ,IF3 Update Enabled Bit[97]" "Disabled,Enabled" tree.end width 6. group.long 0x1E0++0x3 line.long 0x0 "TIOC,TX IO Control Register" bitfld.long 0x00 18. " PU ,CAN_TX Pullup/Pulldown select" "Pulldown,Pullup" bitfld.long 0x00 17. " PD ,CAN_TX pull disable" "Active,Disabled" bitfld.long 0x00 16. " OD ,CAN_TX open drain enable" "Push/pull,Open drain" textline " " bitfld.long 0x00 3. " FUNC ,CAN_TX function" "GIO,Functional" bitfld.long 0x00 2. " DIR ,CAN_TX data direction" "Input,Output" bitfld.long 0x00 1. " OUT ,CAN_TX data out write" "Low,High" textline " " bitfld.long 0x00 0. " IN ,CAN_TX data in" "Low,High" group.long 0x1E4++0x3 line.long 0x0 "RIOC,RX IO Control Register" bitfld.long 0x00 18. " PU ,CAN_TX Pullup/Pulldown select" "Pulldown,Pullup" bitfld.long 0x00 17. " PD ,CAN_TX pull disable" "Active,Disabled" bitfld.long 0x00 16. " OD ,CAN_TX open drain enable" "Push/pull,Open drain" textline " " bitfld.long 0x00 3. " FUNC ,CAN_TX function" "GIO,Functional" bitfld.long 0x00 2. " DIR ,CAN_TX data direction" "Input,Output" bitfld.long 0x00 1. " OUT ,CAN_TX data out write" "Low,High" textline " " bitfld.long 0x00 0. " IN ,CAN_TX data in" "Low,High" width 11. tree.end tree "DCAN2" base ad:0xFFF7DE00 width 12. group.long 0x00++0x3 line.long 0x0 "CTL,Control register" bitfld.long 0x00 25. " WUBA ,Automatic wake up on bus activity" "Not detected,Detected" bitfld.long 0x00 24. " PDR ,Request for local low power down mode" "Not requested,Requested" bitfld.long 0x00 20. " DE3 ,Enable DMA request line for IF3" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " DE2 ,Enable DMA request line for IF2" "Disabled,Enabled" bitfld.long 0x00 18. " DE1 ,Enable DMA request line for IF1" "Disabled,Enabled" bitfld.long 0x00 17. " IE1 ,Interrupt DCAN1INT line 1 Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " INITDBG ,Internal Init state while debug access" "Not initialized,Initialized" bitfld.long 0x00 15. " SWR ,SW Reset Enable" "Normal,Reset" bitfld.long 0x00 10.--13. " PMD ,Parity on/off" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" textline " " bitfld.long 0x00 9. " ABO ,Auto-Bus-On Enable" "Disabled,Enabled" bitfld.long 0x00 8. " IDS ,Interruption Debug Support Enable" "Disabled,Enabled" bitfld.long 0x00 7. " TEST ,Test Mode Enable" "Normal,Enabled" textline " " bitfld.long 0x00 6. " CCE ,Configuration Change Enable" "No WR access,WR Access" bitfld.long 0x00 5. " DAR ,Disable Automatic Retransmission" "Enabled,Disabled" bitfld.long 0x00 3. " EIE ,Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SIE ,Status Change Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 1. " IE0 ,Interrupt DCAN0INT line 0 Enable" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization mode" "Disabled,Enabled" hgroup.long 0x04++0x3 hide.long 0x0 "ES,Error and Status Register" in rgroup.long 0x08++0x3 line.long 0x0 "ERRC,Error Counter Register" bitfld.long 0x00 15. " RP ,Receive Error Passive" "Below,Reached" hexmask.long.byte 0x00 8.--14. 1. " REC ,Receive Error Counter" hexmask.long.byte 0x00 0.--7. 1. " TEC ,Transmit Error Counter" group.long 0x0C++0x3 line.long 0x0 "BTR,Bit Timing_BRP Extension Register" bitfld.long 0x00 16.--19. " BRPE ,Baud Rate Prescaler Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--14. " TSEG2 ,Time segment after the sample point" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--11. " TSEG1 ,Time segment before the sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 6.--7. " SJW ,Synchronization Jump Width" "0,1,2,3" bitfld.long 0x00 0.--5. " BRP ,Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x10++0x3 line.long 0x0 "INT,Interrupt Register" hexmask.long.byte 0x00 16.--23. 1. " INT1ID ,Interrupt 1 Identifier" hexmask.long.word 0x00 0.--15. 1. " INT0ID ,Interrupt Identifier" group.long 0x14++0x3 line.long 0x0 "TEST,Test Register" bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Disabled,Enabled" bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Disabled,Enabled" bitfld.long 0x00 7. " RX ,Receive Pin" "Bus is dominant,Bus is recessive" textline " " bitfld.long 0x00 5.--6. " TX ,Control of CAN_TX pin" "Normal operation,Monitored,Dominant value,Recessive value" bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled" bitfld.long 0x00 3. " SILENT ,Silent Mode" "Disabled,Enabled" rgroup.long 0x1C++0x3 line.long 0x0 "PARERR,Parity Error Code Register" bitfld.long 0x00 8.--10. " WORD_NUMBER ,Word number where parity error has been detected" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Message object number where parity error has been detected" group.long 0x80++0x3 line.long 0x0 "ABOTR,Auto Bus On Time" group.long 0x84++0x3 line.long 0x0 "TRREQX,Transmission Request X" bitfld.long 0x00 14.--15. " TXRQSTREG8 ,Transmission Request 8 Register" "0,1,2,3" bitfld.long 0x00 12.--13. " TXRQSTREG7 ,Transmission Request 7 Register" "0,1,2,3" bitfld.long 0x00 10.--11. " TXRQSTREG6 ,Transmission Request 6 Register" "0,1,2,3" textline " " bitfld.long 0x00 8.--9. " TXRQSTREG5 ,Transmission Request 5 Register" "0,1,2,3" bitfld.long 0x00 6.--7. " TXRQSTREG4 ,Transmission Request 4 Register" "0,1,2,3" bitfld.long 0x00 4.--5. " TXRQSTREG3 ,Transmission Request 3 Register" "0,1,2,3" textline " " bitfld.long 0x00 2.--3. " TXRQSTREG2 ,Transmission Request 2 Register" "0,1,2,3" bitfld.long 0x00 0.--1. " TXRQSTREG1 ,Transmission Request 1 Register" "0,1,2,3" rgroup.long 0x88++0x3 line.long 0x0 "TRREQ12,Transmission Request 1 2 Register" bitfld.long 0x00 31. " TXRQST[32] ,Transmission Request Bits[32]" "Not requested,Requested" bitfld.long 0x00 30. " TXRQST[31] ,Transmission Request Bits[31]" "Not requested,Requested" textline " " bitfld.long 0x00 29. " TXRQST[30] ,Transmission Request Bits[30]" "Not requested,Requested" bitfld.long 0x00 28. " TXRQST[29] ,Transmission Request Bits[29]" "Not requested,Requested" textline " " bitfld.long 0x00 27. " TXRQST[28] ,Transmission Request Bits[28]" "Not requested,Requested" bitfld.long 0x00 26. " TXRQST[27] ,Transmission Request Bits[27]" "Not requested,Requested" textline " " bitfld.long 0x00 25. " TXRQST[26] ,Transmission Request Bits[26]" "Not requested,Requested" bitfld.long 0x00 24. " TXRQST[25] ,Transmission Request Bits[25]" "Not requested,Requested" textline " " bitfld.long 0x00 23. " TXRQST[24] ,Transmission Request Bits[24]" "Not requested,Requested" bitfld.long 0x00 22. " TXRQST[23] ,Transmission Request Bits[23]" "Not requested,Requested" textline " " bitfld.long 0x00 21. " TXRQST[22] ,Transmission Request Bits[22]" "Not requested,Requested" bitfld.long 0x00 20. " TXRQST[21] ,Transmission Request Bits[21]" "Not requested,Requested" textline " " bitfld.long 0x00 19. " TXRQST[20] ,Transmission Request Bits[20]" "Not requested,Requested" bitfld.long 0x00 18. " TXRQST[19] ,Transmission Request Bits[19]" "Not requested,Requested" textline " " bitfld.long 0x00 17. " TXRQST[18] ,Transmission Request Bits[18]" "Not requested,Requested" bitfld.long 0x00 16. " TXRQST[17] ,Transmission Request Bits[17]" "Not requested,Requested" textline " " bitfld.long 0x00 15. " TXRQST[16] ,Transmission Request Bits[16]" "Not requested,Requested" bitfld.long 0x00 14. " TXRQST[15] ,Transmission Request Bits[15]" "Not requested,Requested" textline " " bitfld.long 0x00 13. " TXRQST[14] ,Transmission Request Bits[14]" "Not requested,Requested" bitfld.long 0x00 12. " TXRQST[13] ,Transmission Request Bits[13]" "Not requested,Requested" textline " " bitfld.long 0x00 11. " TXRQST[12] ,Transmission Request Bits[12]" "Not requested,Requested" bitfld.long 0x00 10. " TXRQST[11] ,Transmission Request Bits[11]" "Not requested,Requested" textline " " bitfld.long 0x00 9. " TXRQST[10] ,Transmission Request Bits[10]" "Not requested,Requested" bitfld.long 0x00 8. " TXRQST[9] ,Transmission Request Bits[9]" "Not requested,Requested" textline " " bitfld.long 0x00 7. " TXRQST[8] ,Transmission Request Bits[8]" "Not requested,Requested" bitfld.long 0x00 6. " TXRQST[7] ,Transmission Request Bits[7]" "Not requested,Requested" textline " " bitfld.long 0x00 5. " TXRQST[6] ,Transmission Request Bits[6]" "Not requested,Requested" bitfld.long 0x00 4. " TXRQST[5] ,Transmission Request Bits[5]" "Not requested,Requested" textline " " bitfld.long 0x00 3. " TXRQST[4] ,Transmission Request Bits[4]" "Not requested,Requested" bitfld.long 0x00 2. " TXRQST[3] ,Transmission Request Bits[3]" "Not requested,Requested" textline " " bitfld.long 0x00 1. " TXRQST[2] ,Transmission Request Bits[2]" "Not requested,Requested" bitfld.long 0x00 0. " TXRQST[1] ,Transmission Request Bits[1]" "Not requested,Requested" rgroup.long 0x8C++0x3 line.long 0x0 "TRREQ34,Transmission Request 3-4" bitfld.long 0x00 31. " TXRQST[64] ,Transmission Request Bits[64]" "Not requested,Requested" bitfld.long 0x00 30. " TXRQST[63] ,Transmission Request Bits[63]" "Not requested,Requested" textline " " bitfld.long 0x00 29. " TXRQST[62] ,Transmission Request Bits[62]" "Not requested,Requested" bitfld.long 0x00 28. " TXRQST[61] ,Transmission Request Bits[61]" "Not requested,Requested" textline " " bitfld.long 0x00 27. " TXRQST[60] ,Transmission Request Bits[60]" "Not requested,Requested" bitfld.long 0x00 26. " TXRQST[59] ,Transmission Request Bits[59]" "Not requested,Requested" textline " " bitfld.long 0x00 25. " TXRQST[58] ,Transmission Request Bits[58]" "Not requested,Requested" bitfld.long 0x00 24. " TXRQST[57] ,Transmission Request Bits[57]" "Not requested,Requested" textline " " bitfld.long 0x00 23. " TXRQST[56] ,Transmission Request Bits[56]" "Not requested,Requested" bitfld.long 0x00 22. " TXRQST[55] ,Transmission Request Bits[55]" "Not requested,Requested" textline " " bitfld.long 0x00 21. " TXRQST[54] ,Transmission Request Bits[54]" "Not requested,Requested" bitfld.long 0x00 20. " TXRQST[53] ,Transmission Request Bits[53]" "Not requested,Requested" textline " " bitfld.long 0x00 19. " TXRQST[52] ,Transmission Request Bits[52]" "Not requested,Requested" bitfld.long 0x00 18. " TXRQST[51] ,Transmission Request Bits[51]" "Not requested,Requested" textline " " bitfld.long 0x00 17. " TXRQST[50] ,Transmission Request Bits[50]" "Not requested,Requested" bitfld.long 0x00 16. " TXRQST[49] ,Transmission Request Bits[49]" "Not requested,Requested" textline " " bitfld.long 0x00 15. " TXRQST[48] ,Transmission Request Bits[48]" "Not requested,Requested" bitfld.long 0x00 14. " TXRQST[47] ,Transmission Request Bits[47]" "Not requested,Requested" textline " " bitfld.long 0x00 13. " TXRQST[46] ,Transmission Request Bits[46]" "Not requested,Requested" bitfld.long 0x00 12. " TXRQST[45] ,Transmission Request Bits[45]" "Not requested,Requested" textline " " bitfld.long 0x00 11. " TXRQST[44] ,Transmission Request Bits[44]" "Not requested,Requested" bitfld.long 0x00 10. " TXRQST[43] ,Transmission Request Bits[43]" "Not requested,Requested" textline " " bitfld.long 0x00 9. " TXRQST[42] ,Transmission Request Bits[42]" "Not requested,Requested" bitfld.long 0x00 8. " TXRQST[41] ,Transmission Request Bits[41]" "Not requested,Requested" textline " " bitfld.long 0x00 7. " TXRQST[40] ,Transmission Request Bits[40]" "Not requested,Requested" bitfld.long 0x00 6. " TXRQST[39] ,Transmission Request Bits[39]" "Not requested,Requested" textline " " bitfld.long 0x00 5. " TXRQST[38] ,Transmission Request Bits[38]" "Not requested,Requested" bitfld.long 0x00 4. " TXRQST[37] ,Transmission Request Bits[37]" "Not requested,Requested" textline " " bitfld.long 0x00 3. " TXRQST[36] ,Transmission Request Bits[36]" "Not requested,Requested" bitfld.long 0x00 2. " TXRQST[35] ,Transmission Request Bits[35]" "Not requested,Requested" textline " " bitfld.long 0x00 1. " TXRQST[34] ,Transmission Request Bits[34]" "Not requested,Requested" bitfld.long 0x00 0. " TXRQST[33] ,Transmission Request Bits[33]" "Not requested,Requested" rgroup.long 0x90++0x3 line.long 0x0 "TRREQ56,Transmission Request 5-6" bitfld.long 0x00 31. " TXRQST[96] ,Transmission Request Bits[96]" "Not requested,Requested" bitfld.long 0x00 30. " TXRQST[95] ,Transmission Request Bits[95]" "Not requested,Requested" textline " " bitfld.long 0x00 29. " TXRQST[94] ,Transmission Request Bits[94]" "Not requested,Requested" bitfld.long 0x00 28. " TXRQST[93] ,Transmission Request Bits[93]" "Not requested,Requested" textline " " bitfld.long 0x00 27. " TXRQST[92] ,Transmission Request Bits[92]" "Not requested,Requested" bitfld.long 0x00 26. " TXRQST[91] ,Transmission Request Bits[91]" "Not requested,Requested" textline " " bitfld.long 0x00 25. " TXRQST[90] ,Transmission Request Bits[90]" "Not requested,Requested" bitfld.long 0x00 24. " TXRQST[89] ,Transmission Request Bits[89]" "Not requested,Requested" textline " " bitfld.long 0x00 23. " TXRQST[88] ,Transmission Request Bits[88]" "Not requested,Requested" bitfld.long 0x00 22. " TXRQST[87] ,Transmission Request Bits[87]" "Not requested,Requested" textline " " bitfld.long 0x00 21. " TXRQST[86] ,Transmission Request Bits[86]" "Not requested,Requested" bitfld.long 0x00 20. " TXRQST[85] ,Transmission Request Bits[85]" "Not requested,Requested" textline " " bitfld.long 0x00 19. " TXRQST[84] ,Transmission Request Bits[84]" "Not requested,Requested" bitfld.long 0x00 18. " TXRQST[83] ,Transmission Request Bits[83]" "Not requested,Requested" textline " " bitfld.long 0x00 17. " TXRQST[82] ,Transmission Request Bits[82]" "Not requested,Requested" bitfld.long 0x00 16. " TXRQST[81] ,Transmission Request Bits[81]" "Not requested,Requested" textline " " bitfld.long 0x00 15. " TXRQST[80] ,Transmission Request Bits[80]" "Not requested,Requested" bitfld.long 0x00 14. " TXRQST[79] ,Transmission Request Bits[79]" "Not requested,Requested" textline " " bitfld.long 0x00 13. " TXRQST[78] ,Transmission Request Bits[78]" "Not requested,Requested" bitfld.long 0x00 12. " TXRQST[77] ,Transmission Request Bits[77]" "Not requested,Requested" textline " " bitfld.long 0x00 11. " TXRQST[76] ,Transmission Request Bits[76]" "Not requested,Requested" bitfld.long 0x00 10. " TXRQST[75] ,Transmission Request Bits[75]" "Not requested,Requested" textline " " bitfld.long 0x00 9. " TXRQST[74] ,Transmission Request Bits[74]" "Not requested,Requested" bitfld.long 0x00 8. " TXRQST[73] ,Transmission Request Bits[73]" "Not requested,Requested" textline " " bitfld.long 0x00 7. " TXRQST[72] ,Transmission Request Bits[72]" "Not requested,Requested" bitfld.long 0x00 6. " TXRQST[71] ,Transmission Request Bits[71]" "Not requested,Requested" textline " " bitfld.long 0x00 5. " TXRQST[70] ,Transmission Request Bits[70]" "Not requested,Requested" bitfld.long 0x00 4. " TXRQST[69] ,Transmission Request Bits[69]" "Not requested,Requested" textline " " bitfld.long 0x00 3. " TXRQST[68] ,Transmission Request Bits[68]" "Not requested,Requested" bitfld.long 0x00 2. " TXRQST[67] ,Transmission Request Bits[67]" "Not requested,Requested" textline " " bitfld.long 0x00 1. " TXRQST[66] ,Transmission Request Bits[66]" "Not requested,Requested" bitfld.long 0x00 0. " TXRQST[65] ,Transmission Request Bits[65]" "Not requested,Requested" rgroup.long 0x94++0x3 line.long 0x0 "TRREQ78,Transmission Request 7-8" bitfld.long 0x00 31. " TXRQST[128] ,Transmission Request Bits[128]" "Not requested,Requested" bitfld.long 0x00 30. " TXRQST[127] ,Transmission Request Bits[127]" "Not requested,Requested" textline " " bitfld.long 0x00 29. " TXRQST[126] ,Transmission Request Bits[126]" "Not requested,Requested" bitfld.long 0x00 28. " TXRQST[125] ,Transmission Request Bits[125]" "Not requested,Requested" textline " " bitfld.long 0x00 27. " TXRQST[124] ,Transmission Request Bits[124]" "Not requested,Requested" bitfld.long 0x00 26. " TXRQST[123] ,Transmission Request Bits[123]" "Not requested,Requested" textline " " bitfld.long 0x00 25. " TXRQST[122] ,Transmission Request Bits[122]" "Not requested,Requested" bitfld.long 0x00 24. " TXRQST[121] ,Transmission Request Bits[121]" "Not requested,Requested" textline " " bitfld.long 0x00 23. " TXRQST[120] ,Transmission Request Bits[120]" "Not requested,Requested" bitfld.long 0x00 22. " TXRQST[119] ,Transmission Request Bits[119]" "Not requested,Requested" textline " " bitfld.long 0x00 21. " TXRQST[118] ,Transmission Request Bits[118]" "Not requested,Requested" bitfld.long 0x00 20. " TXRQST[117] ,Transmission Request Bits[117]" "Not requested,Requested" textline " " bitfld.long 0x00 19. " TXRQST[116] ,Transmission Request Bits[116]" "Not requested,Requested" bitfld.long 0x00 18. " TXRQST[115] ,Transmission Request Bits[115]" "Not requested,Requested" textline " " bitfld.long 0x00 17. " TXRQST[114] ,Transmission Request Bits[114]" "Not requested,Requested" bitfld.long 0x00 16. " TXRQST[113] ,Transmission Request Bits[113]" "Not requested,Requested" textline " " bitfld.long 0x00 15. " TXRQST[112] ,Transmission Request Bits[112]" "Not requested,Requested" bitfld.long 0x00 14. " TXRQST[111] ,Transmission Request Bits[111]" "Not requested,Requested" textline " " bitfld.long 0x00 13. " TXRQST[110] ,Transmission Request Bits[110]" "Not requested,Requested" bitfld.long 0x00 12. " TXRQST[109] ,Transmission Request Bits[109]" "Not requested,Requested" textline " " bitfld.long 0x00 11. " TXRQST[108] ,Transmission Request Bits[108]" "Not requested,Requested" bitfld.long 0x00 10. " TXRQST[107] ,Transmission Request Bits[107]" "Not requested,Requested" textline " " bitfld.long 0x00 9. " TXRQST[106] ,Transmission Request Bits[106]" "Not requested,Requested" bitfld.long 0x00 8. " TXRQST[105] ,Transmission Request Bits[105]" "Not requested,Requested" textline " " bitfld.long 0x00 7. " TXRQST[104] ,Transmission Request Bits[104]" "Not requested,Requested" bitfld.long 0x00 6. " TXRQST[103] ,Transmission Request Bits[103]" "Not requested,Requested" textline " " bitfld.long 0x00 5. " TXRQST[102] ,Transmission Request Bits[102]" "Not requested,Requested" bitfld.long 0x00 4. " TXRQST[101] ,Transmission Request Bits[101]" "Not requested,Requested" textline " " bitfld.long 0x00 3. " TXRQST[100] ,Transmission Request Bits[100]" "Not requested,Requested" bitfld.long 0x00 2. " TXRQST[99] ,Transmission Request Bits[99]" "Not requested,Requested" textline " " bitfld.long 0x00 1. " TXRQST[98] ,Transmission Request Bits[98]" "Not requested,Requested" bitfld.long 0x00 0. " TXRQST[97] ,Transmission Request Bits[97]" "Not requested,Requested" rgroup.long 0x98++0x3 line.long 0x0 "NEWDATX,New Data X" bitfld.long 0x00 14.--15. " NEWDATREG8 ,New Data 8 Register" "0,1,2,3" bitfld.long 0x00 12.--13. " NEWDATREG7 ,New Data 7 Register" "0,1,2,3" bitfld.long 0x00 10.--11. " NEWDATREG6 ,New Data 6 Register" "0,1,2,3" textline " " bitfld.long 0x00 8.--9. " NEWDATREG5 ,New Data 5 Register" "0,1,2,3" bitfld.long 0x00 6.--7. " NEWDATREG4 ,New Data 4 Register" "0,1,2,3" bitfld.long 0x00 4.--5. " NEWDATREG3 ,New Data 3 Register" "0,1,2,3" textline " " bitfld.long 0x00 2.--3. " NEWDATREG2 ,New Data 2 Register" "0,1,2,3" bitfld.long 0x00 0.--1. " NEWDATREG1 ,New Data 1 Register" "0,1,2,3" rgroup.long 0x9C++0x3 line.long 0x0 "NEWDAT12,New Data 1-2" bitfld.long 0x00 31. " NEWDAT[32] ,New Data Bit[32]" "Not requested,Requested" bitfld.long 0x00 30. " NEWDAT[31] ,New Data Bit[31]" "Not requested,Requested" textline " " bitfld.long 0x00 29. " NEWDAT[30] ,New Data Bit[30]" "Not requested,Requested" bitfld.long 0x00 28. " NEWDAT[29] ,New Data Bit[29]" "Not requested,Requested" textline " " bitfld.long 0x00 27. " NEWDAT[28] ,New Data Bit[28]" "Not requested,Requested" bitfld.long 0x00 26. " NEWDAT[27] ,New Data Bit[27]" "Not requested,Requested" textline " " bitfld.long 0x00 25. " NEWDAT[26] ,New Data Bit[26]" "Not requested,Requested" bitfld.long 0x00 24. " NEWDAT[25] ,New Data Bit[25]" "Not requested,Requested" textline " " bitfld.long 0x00 23. " NEWDAT[24] ,New Data Bit[24]" "Not requested,Requested" bitfld.long 0x00 22. " NEWDAT[23] ,New Data Bit[23]" "Not requested,Requested" textline " " bitfld.long 0x00 21. " NEWDAT[22] ,New Data Bit[22]" "Not requested,Requested" bitfld.long 0x00 20. " NEWDAT[21] ,New Data Bit[21]" "Not requested,Requested" textline " " bitfld.long 0x00 19. " NEWDAT[20] ,New Data Bit[20]" "Not requested,Requested" bitfld.long 0x00 18. " NEWDAT[19] ,New Data Bit[19]" "Not requested,Requested" textline " " bitfld.long 0x00 17. " NEWDAT[18] ,New Data Bit[18]" "Not requested,Requested" bitfld.long 0x00 16. " NEWDAT[17] ,New Data Bit[17]" "Not requested,Requested" textline " " bitfld.long 0x00 15. " NEWDAT[16] ,New Data Bit[16]" "Not requested,Requested" bitfld.long 0x00 14. " NEWDAT[15] ,New Data Bit[15]" "Not requested,Requested" textline " " bitfld.long 0x00 13. " NEWDAT[14] ,New Data Bit[14]" "Not requested,Requested" bitfld.long 0x00 12. " NEWDAT[13] ,New Data Bit[13]" "Not requested,Requested" textline " " bitfld.long 0x00 11. " NEWDAT[12] ,New Data Bit[12]" "Not requested,Requested" bitfld.long 0x00 10. " NEWDAT[11] ,New Data Bit[11]" "Not requested,Requested" textline " " bitfld.long 0x00 9. " NEWDAT[10] ,New Data Bit[10]" "Not requested,Requested" bitfld.long 0x00 8. " NEWDAT[9] ,New Data Bit[9]" "Not requested,Requested" textline " " bitfld.long 0x00 7. " NEWDAT[8] ,New Data Bit[8]" "Not requested,Requested" bitfld.long 0x00 6. " NEWDAT[7] ,New Data Bit[7]" "Not requested,Requested" textline " " bitfld.long 0x00 5. " NEWDAT[6] ,New Data Bit[6]" "Not requested,Requested" bitfld.long 0x00 4. " NEWDAT[5] ,New Data Bit[5]" "Not requested,Requested" textline " " bitfld.long 0x00 3. " NEWDAT[4] ,New Data Bit[4]" "Not requested,Requested" bitfld.long 0x00 2. " NEWDAT[3] ,New Data Bit[3]" "Not requested,Requested" textline " " bitfld.long 0x00 1. " NEWDAT[2] ,New Data Bit[2]" "Not requested,Requested" bitfld.long 0x00 0. " NEWDAT[1] ,New Data Bit[1]" "Not requested,Requested" rgroup.long 0xA0++0x3 line.long 0x0 "NEWDAT34,New Data 3-4" bitfld.long 0x00 31. " NEWDAT[64] ,New Data Bit[64]" "Not requested,Requested" bitfld.long 0x00 30. " NEWDAT[63] ,New Data Bit[63]" "Not requested,Requested" textline " " bitfld.long 0x00 29. " NEWDAT[62] ,New Data Bit[62]" "Not requested,Requested" bitfld.long 0x00 28. " NEWDAT[61] ,New Data Bit[61]" "Not requested,Requested" textline " " bitfld.long 0x00 27. " NEWDAT[60] ,New Data Bit[60]" "Not requested,Requested" bitfld.long 0x00 26. " NEWDAT[59] ,New Data Bit[59]" "Not requested,Requested" textline " " bitfld.long 0x00 25. " NEWDAT[58] ,New Data Bit[58]" "Not requested,Requested" bitfld.long 0x00 24. " NEWDAT[57] ,New Data Bit[57]" "Not requested,Requested" textline " " bitfld.long 0x00 23. " NEWDAT[56] ,New Data Bit[56]" "Not requested,Requested" bitfld.long 0x00 22. " NEWDAT[55] ,New Data Bit[55]" "Not requested,Requested" textline " " bitfld.long 0x00 21. " NEWDAT[54] ,New Data Bit[54]" "Not requested,Requested" bitfld.long 0x00 20. " NEWDAT[53] ,New Data Bit[53]" "Not requested,Requested" textline " " bitfld.long 0x00 19. " NEWDAT[52] ,New Data Bit[52]" "Not requested,Requested" bitfld.long 0x00 18. " NEWDAT[51] ,New Data Bit[51]" "Not requested,Requested" textline " " bitfld.long 0x00 17. " NEWDAT[50] ,New Data Bit[50]" "Not requested,Requested" bitfld.long 0x00 16. " NEWDAT[49] ,New Data Bit[49]" "Not requested,Requested" textline " " bitfld.long 0x00 15. " NEWDAT[48] ,New Data Bit[48]" "Not requested,Requested" bitfld.long 0x00 14. " NEWDAT[47] ,New Data Bit[47]" "Not requested,Requested" textline " " bitfld.long 0x00 13. " NEWDAT[46] ,New Data Bit[46]" "Not requested,Requested" bitfld.long 0x00 12. " NEWDAT[45] ,New Data Bit[45]" "Not requested,Requested" textline " " bitfld.long 0x00 11. " NEWDAT[44] ,New Data Bit[44]" "Not requested,Requested" bitfld.long 0x00 10. " NEWDAT[43] ,New Data Bit[43]" "Not requested,Requested" textline " " bitfld.long 0x00 9. " NEWDAT[42] ,New Data Bit[42]" "Not requested,Requested" bitfld.long 0x00 8. " NEWDAT[41] ,New Data Bit[41]" "Not requested,Requested" textline " " bitfld.long 0x00 7. " NEWDAT[40] ,New Data Bit[40]" "Not requested,Requested" bitfld.long 0x00 6. " NEWDAT[39] ,New Data Bit[39]" "Not requested,Requested" textline " " bitfld.long 0x00 5. " NEWDAT[38] ,New Data Bit[38]" "Not requested,Requested" bitfld.long 0x00 4. " NEWDAT[37] ,New Data Bit[37]" "Not requested,Requested" textline " " bitfld.long 0x00 3. " NEWDAT[36] ,New Data Bit[36]" "Not requested,Requested" bitfld.long 0x00 2. " NEWDAT[35] ,New Data Bit[35]" "Not requested,Requested" textline " " bitfld.long 0x00 1. " NEWDAT[34] ,New Data Bit[34]" "Not requested,Requested" bitfld.long 0x00 0. " NEWDAT[33] ,New Data Bit[33]" "Not requested,Requested" rgroup.long 0xA4++0x3 line.long 0x0 "NEWDAT56,New Data 5-6" bitfld.long 0x00 31. " NEWDAT[96] ,New Data Bit[96]" "Not requested,Requested" bitfld.long 0x00 30. " NEWDAT[95] ,New Data Bit[95]" "Not requested,Requested" textline " " bitfld.long 0x00 29. " NEWDAT[94] ,New Data Bit[94]" "Not requested,Requested" bitfld.long 0x00 28. " NEWDAT[93] ,New Data Bit[93]" "Not requested,Requested" textline " " bitfld.long 0x00 27. " NEWDAT[92] ,New Data Bit[92]" "Not requested,Requested" bitfld.long 0x00 26. " NEWDAT[91] ,New Data Bit[91]" "Not requested,Requested" textline " " bitfld.long 0x00 25. " NEWDAT[90] ,New Data Bit[90]" "Not requested,Requested" bitfld.long 0x00 24. " NEWDAT[89] ,New Data Bit[89]" "Not requested,Requested" textline " " bitfld.long 0x00 23. " NEWDAT[88] ,New Data Bit[88]" "Not requested,Requested" bitfld.long 0x00 22. " NEWDAT[87] ,New Data Bit[87]" "Not requested,Requested" textline " " bitfld.long 0x00 21. " NEWDAT[86] ,New Data Bit[86]" "Not requested,Requested" bitfld.long 0x00 20. " NEWDAT[85] ,New Data Bit[85]" "Not requested,Requested" textline " " bitfld.long 0x00 19. " NEWDAT[84] ,New Data Bit[84]" "Not requested,Requested" bitfld.long 0x00 18. " NEWDAT[83] ,New Data Bit[83]" "Not requested,Requested" textline " " bitfld.long 0x00 17. " NEWDAT[82] ,New Data Bit[82]" "Not requested,Requested" bitfld.long 0x00 16. " NEWDAT[81] ,New Data Bit[81]" "Not requested,Requested" textline " " bitfld.long 0x00 15. " NEWDAT[80] ,New Data Bit[80]" "Not requested,Requested" bitfld.long 0x00 14. " NEWDAT[79] ,New Data Bit[79]" "Not requested,Requested" textline " " bitfld.long 0x00 13. " NEWDAT[78] ,New Data Bit[78]" "Not requested,Requested" bitfld.long 0x00 12. " NEWDAT[77] ,New Data Bit[77]" "Not requested,Requested" textline " " bitfld.long 0x00 11. " NEWDAT[76] ,New Data Bit[76]" "Not requested,Requested" bitfld.long 0x00 10. " NEWDAT[75] ,New Data Bit[75]" "Not requested,Requested" textline " " bitfld.long 0x00 9. " NEWDAT[74] ,New Data Bit[74]" "Not requested,Requested" bitfld.long 0x00 8. " NEWDAT[73] ,New Data Bit[73]" "Not requested,Requested" textline " " bitfld.long 0x00 7. " NEWDAT[72] ,New Data Bit[72]" "Not requested,Requested" bitfld.long 0x00 6. " NEWDAT[71] ,New Data Bit[71]" "Not requested,Requested" textline " " bitfld.long 0x00 5. " NEWDAT[70] ,New Data Bit[70]" "Not requested,Requested" bitfld.long 0x00 4. " NEWDAT[69] ,New Data Bit[69]" "Not requested,Requested" textline " " bitfld.long 0x00 3. " NEWDAT[68] ,New Data Bit[68]" "Not requested,Requested" bitfld.long 0x00 2. " NEWDAT[67] ,New Data Bit[67]" "Not requested,Requested" textline " " bitfld.long 0x00 1. " NEWDAT[66] ,New Data Bit[66]" "Not requested,Requested" bitfld.long 0x00 0. " NEWDAT[65] ,New Data Bit[65]" "Not requested,Requested" rgroup.long 0xA8++0x3 line.long 0x0 "NEWDAT78,New Data 7-8" bitfld.long 0x00 31. " NEWDAT[128] ,New Data Bit[128]" "Not requested,Requested" bitfld.long 0x00 30. " NEWDAT[127] ,New Data Bit[127]" "Not requested,Requested" textline " " bitfld.long 0x00 29. " NEWDAT[126] ,New Data Bit[126]" "Not requested,Requested" bitfld.long 0x00 28. " NEWDAT[125] ,New Data Bit[125]" "Not requested,Requested" textline " " bitfld.long 0x00 27. " NEWDAT[124] ,New Data Bit[124]" "Not requested,Requested" bitfld.long 0x00 26. " NEWDAT[123] ,New Data Bit[123]" "Not requested,Requested" textline " " bitfld.long 0x00 25. " NEWDAT[122] ,New Data Bit[122]" "Not requested,Requested" bitfld.long 0x00 24. " NEWDAT[121] ,New Data Bit[121]" "Not requested,Requested" textline " " bitfld.long 0x00 23. " NEWDAT[120] ,New Data Bit[120]" "Not requested,Requested" bitfld.long 0x00 22. " NEWDAT[119] ,New Data Bit[119]" "Not requested,Requested" textline " " bitfld.long 0x00 21. " NEWDAT[118] ,New Data Bit[118]" "Not requested,Requested" bitfld.long 0x00 20. " NEWDAT[117] ,New Data Bit[117]" "Not requested,Requested" textline " " bitfld.long 0x00 19. " NEWDAT[116] ,New Data Bit[116]" "Not requested,Requested" bitfld.long 0x00 18. " NEWDAT[115] ,New Data Bit[115]" "Not requested,Requested" textline " " bitfld.long 0x00 17. " NEWDAT[114] ,New Data Bit[114]" "Not requested,Requested" bitfld.long 0x00 16. " NEWDAT[113] ,New Data Bit[113]" "Not requested,Requested" textline " " bitfld.long 0x00 15. " NEWDAT[112] ,New Data Bit[112]" "Not requested,Requested" bitfld.long 0x00 14. " NEWDAT[111] ,New Data Bit[111]" "Not requested,Requested" textline " " bitfld.long 0x00 13. " NEWDAT[110] ,New Data Bit[110]" "Not requested,Requested" bitfld.long 0x00 12. " NEWDAT[109] ,New Data Bit[109]" "Not requested,Requested" textline " " bitfld.long 0x00 11. " NEWDAT[108] ,New Data Bit[108]" "Not requested,Requested" bitfld.long 0x00 10. " NEWDAT[107] ,New Data Bit[107]" "Not requested,Requested" textline " " bitfld.long 0x00 9. " NEWDAT[106] ,New Data Bit[106]" "Not requested,Requested" bitfld.long 0x00 8. " NEWDAT[105] ,New Data Bit[105]" "Not requested,Requested" textline " " bitfld.long 0x00 7. " NEWDAT[104] ,New Data Bit[104]" "Not requested,Requested" bitfld.long 0x00 6. " NEWDAT[103] ,New Data Bit[103]" "Not requested,Requested" textline " " bitfld.long 0x00 5. " NEWDAT[102] ,New Data Bit[102]" "Not requested,Requested" bitfld.long 0x00 4. " NEWDAT[101] ,New Data Bit[101]" "Not requested,Requested" textline " " bitfld.long 0x00 3. " NEWDAT[100] ,New Data Bit[100]" "Not requested,Requested" bitfld.long 0x00 2. " NEWDAT[99] ,New Data Bit[99]" "Not requested,Requested" textline " " bitfld.long 0x00 1. " NEWDAT[98] ,New Data Bit[98]" "Not requested,Requested" bitfld.long 0x00 0. " NEWDAT[97] ,New Data Bit[97]" "Not requested,Requested" rgroup.long 0xAC++0x3 line.long 0x0 "INTPENX,Interrupt Pending X" bitfld.long 0x00 14.--15. " INTPNDREG8 ,Interrupt Pending 8" "0,1,2,3" bitfld.long 0x00 12.--13. " INTPNDREG7 ,Interrupt Pending 7" "0,1,2,3" bitfld.long 0x00 10.--11. " INTPNDREG6 ,Interrupt Pending 6" "0,1,2,3" textline " " bitfld.long 0x00 8.--9. " INTPNDREG5 ,Interrupt Pending 5 Register" "0,1,2,3" bitfld.long 0x00 6.--7. " INTPNDREG4 ,Interrupt Pending4" "0,1,2,3" bitfld.long 0x00 4.--5. " INTPNDREG3 ,Interrupt Pending3" "0,1,2,3" textline " " bitfld.long 0x00 2.--3. " INTPNDREG2 ,Interrupt Pending2 Register" "0,1,2,3" bitfld.long 0x00 0.--1. " INTPNDREG1 ,Interrupt Pending1" "0,1,2,3" rgroup.long 0xB0++0x3 line.long 0x0 "INTPEN12,Interrupt Pending 1-2" bitfld.long 0x00 31. " INTPND[32] ,Interrupt Pending Bit[32]" "No interrupt,Interrupt" bitfld.long 0x00 30. " INTPND[31] ,Interrupt Pending Bit[31]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 29. " INTPND[30] ,Interrupt Pending Bit[30]" "No interrupt,Interrupt" bitfld.long 0x00 28. " INTPND[29] ,Interrupt Pending Bit[29]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " INTPND[28] ,Interrupt Pending Bit[28]" "No interrupt,Interrupt" bitfld.long 0x00 26. " INTPND[27] ,Interrupt Pending Bit[27]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 25. " INTPND[26] ,Interrupt Pending Bit[26]" "No interrupt,Interrupt" bitfld.long 0x00 24. " INTPND[25] ,Interrupt Pending Bit[25]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " INTPND[24] ,Interrupt Pending Bit[24]" "No interrupt,Interrupt" bitfld.long 0x00 22. " INTPND[23] ,Interrupt Pending Bit[23]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 21. " INTPND[22] ,Interrupt Pending Bit[22]" "No interrupt,Interrupt" bitfld.long 0x00 20. " INTPND[21] ,Interrupt Pending Bit[21]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " INTPND[20] ,Interrupt Pending Bit[20]" "No interrupt,Interrupt" bitfld.long 0x00 18. " INTPND[19] ,Interrupt Pending Bit[19]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 17. " INTPND[18] ,Interrupt Pending Bit[18]" "No interrupt,Interrupt" bitfld.long 0x00 16. " INTPND[17] ,Interrupt Pending Bit[17]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 15. " INTPND[16] ,Interrupt Pending Bit[16]" "No interrupt,Interrupt" bitfld.long 0x00 14. " INTPND[15] ,Interrupt Pending Bit[15]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 13. " INTPND[14] ,Interrupt Pending Bit[14]" "No interrupt,Interrupt" bitfld.long 0x00 12. " INTPND[13] ,Interrupt Pending Bit[13]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " INTPND[12] ,Interrupt Pending Bit[12]" "No interrupt,Interrupt" bitfld.long 0x00 10. " INTPND[11] ,Interrupt Pending Bit[11]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 9. " INTPND[10] ,Interrupt Pending Bit[10]" "No interrupt,Interrupt" bitfld.long 0x00 8. " INTPND[9] ,Interrupt Pending Bit[9]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 7. " INTPND[8] ,Interrupt Pending Bit[8]" "No interrupt,Interrupt" bitfld.long 0x00 6. " INTPND[7] ,Interrupt Pending Bit[7]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 5. " INTPND[6] ,Interrupt Pending Bit[6]" "No interrupt,Interrupt" bitfld.long 0x00 4. " INTPND[5] ,Interrupt Pending Bit[5]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " INTPND[4] ,Interrupt Pending Bit[4]" "No interrupt,Interrupt" bitfld.long 0x00 2. " INTPND[3] ,Interrupt Pending Bit[3]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " INTPND[2] ,Interrupt Pending Bit[2]" "No interrupt,Interrupt" bitfld.long 0x00 0. " INTPND[1] ,Interrupt Pending Bit[1]" "No interrupt,Interrupt" rgroup.long 0xB4++0x3 line.long 0x0 "INTPEN34,Interrupt Pending 3-4" bitfld.long 0x00 31. " INTPND[64] ,Interrupt Pending Bit[64]" "No interrupt,Interrupt" bitfld.long 0x00 30. " INTPND[63] ,Interrupt Pending Bit[63]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 29. " INTPND[62] ,Interrupt Pending Bit[62]" "No interrupt,Interrupt" bitfld.long 0x00 28. " INTPND[61] ,Interrupt Pending Bit[61]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " INTPND[60] ,Interrupt Pending Bit[60]" "No interrupt,Interrupt" bitfld.long 0x00 26. " INTPND[59] ,Interrupt Pending Bit[59]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 25. " INTPND[58] ,Interrupt Pending Bit[58]" "No interrupt,Interrupt" bitfld.long 0x00 24. " INTPND[57] ,Interrupt Pending Bit[57]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " INTPND[56] ,Interrupt Pending Bit[56]" "No interrupt,Interrupt" bitfld.long 0x00 22. " INTPND[55] ,Interrupt Pending Bit[55]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 21. " INTPND[54] ,Interrupt Pending Bit[54]" "No interrupt,Interrupt" bitfld.long 0x00 20. " INTPND[53] ,Interrupt Pending Bit[53]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " INTPND[52] ,Interrupt Pending Bit[52]" "No interrupt,Interrupt" bitfld.long 0x00 18. " INTPND[51] ,Interrupt Pending Bit[51]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 17. " INTPND[50] ,Interrupt Pending Bit[50]" "No interrupt,Interrupt" bitfld.long 0x00 16. " INTPND[49] ,Interrupt Pending Bit[49]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 15. " INTPND[48] ,Interrupt Pending Bit[48]" "No interrupt,Interrupt" bitfld.long 0x00 14. " INTPND[47] ,Interrupt Pending Bit[47]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 13. " INTPND[46] ,Interrupt Pending Bit[46]" "No interrupt,Interrupt" bitfld.long 0x00 12. " INTPND[45] ,Interrupt Pending Bit[45]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " INTPND[44] ,Interrupt Pending Bit[44]" "No interrupt,Interrupt" bitfld.long 0x00 10. " INTPND[43] ,Interrupt Pending Bit[43]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 9. " INTPND[42] ,Interrupt Pending Bit[42]" "No interrupt,Interrupt" bitfld.long 0x00 8. " INTPND[41] ,Interrupt Pending Bit[41]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 7. " INTPND[40] ,Interrupt Pending Bit[40]" "No interrupt,Interrupt" bitfld.long 0x00 6. " INTPND[39] ,Interrupt Pending Bit[39]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 5. " INTPND[38] ,Interrupt Pending Bit[38]" "No interrupt,Interrupt" bitfld.long 0x00 4. " INTPND[37] ,Interrupt Pending Bit[37]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " INTPND[36] ,Interrupt Pending Bit[36]" "No interrupt,Interrupt" bitfld.long 0x00 2. " INTPND[35] ,Interrupt Pending Bit[35]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " INTPND[34] ,Interrupt Pending Bit[34]" "No interrupt,Interrupt" bitfld.long 0x00 0. " INTPND[33] ,Interrupt Pending Bit[33]" "No interrupt,Interrupt" rgroup.long 0xB8++0x3 line.long 0x0 "INTPEN56,Interrupt Pending 5-6" bitfld.long 0x00 31. " INTPND[96] ,Interrupt Pending Bit[96]" "No interrupt,Interrupt" bitfld.long 0x00 30. " INTPND[95] ,Interrupt Pending Bit[95]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 29. " INTPND[94] ,Interrupt Pending Bit[94]" "No interrupt,Interrupt" bitfld.long 0x00 28. " INTPND[93] ,Interrupt Pending Bit[93]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " INTPND[92] ,Interrupt Pending Bit[92]" "No interrupt,Interrupt" bitfld.long 0x00 26. " INTPND[91] ,Interrupt Pending Bit[91]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 25. " INTPND[90] ,Interrupt Pending Bit[90]" "No interrupt,Interrupt" bitfld.long 0x00 24. " INTPND[89] ,Interrupt Pending Bit[89]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " INTPND[88] ,Interrupt Pending Bit[88]" "No interrupt,Interrupt" bitfld.long 0x00 22. " INTPND[87] ,Interrupt Pending Bit[87]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 21. " INTPND[86] ,Interrupt Pending Bit[86]" "No interrupt,Interrupt" bitfld.long 0x00 20. " INTPND[85] ,Interrupt Pending Bit[85]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " INTPND[84] ,Interrupt Pending Bit[84]" "No interrupt,Interrupt" bitfld.long 0x00 18. " INTPND[83] ,Interrupt Pending Bit[83]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 17. " INTPND[82] ,Interrupt Pending Bit[82]" "No interrupt,Interrupt" bitfld.long 0x00 16. " INTPND[81] ,Interrupt Pending Bit[81]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 15. " INTPND[80] ,Interrupt Pending Bit[80]" "No interrupt,Interrupt" bitfld.long 0x00 14. " INTPND[79] ,Interrupt Pending Bit[79]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 13. " INTPND[78] ,Interrupt Pending Bit[78]" "No interrupt,Interrupt" bitfld.long 0x00 12. " INTPND[77] ,Interrupt Pending Bit[77]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " INTPND[76] ,Interrupt Pending Bit[76]" "No interrupt,Interrupt" bitfld.long 0x00 10. " INTPND[75] ,Interrupt Pending Bit[75]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 9. " INTPND[74] ,Interrupt Pending Bit[74]" "No interrupt,Interrupt" bitfld.long 0x00 8. " INTPND[73] ,Interrupt Pending Bit[73]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 7. " INTPND[72] ,Interrupt Pending Bit[72]" "No interrupt,Interrupt" bitfld.long 0x00 6. " INTPND[71] ,Interrupt Pending Bit[71]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 5. " INTPND[70] ,Interrupt Pending Bit[70]" "No interrupt,Interrupt" bitfld.long 0x00 4. " INTPND[69] ,Interrupt Pending Bit[69]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " INTPND[68] ,Interrupt Pending Bit[68]" "No interrupt,Interrupt" bitfld.long 0x00 2. " INTPND[67] ,Interrupt Pending Bit[67]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " INTPND[66] ,Interrupt Pending Bit[66]" "No interrupt,Interrupt" bitfld.long 0x00 0. " INTPND[65] ,Interrupt Pending Bit[65]" "No interrupt,Interrupt" rgroup.long 0xBC++0x3 line.long 0x0 "INTPEN78,Interrupt Pending 7-8" bitfld.long 0x00 31. " INTPND[128] ,Interrupt Pending Bit[128]" "No interrupt,Interrupt" bitfld.long 0x00 30. " INTPND[127] ,Interrupt Pending Bit[127]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 29. " INTPND[126] ,Interrupt Pending Bit[126]" "No interrupt,Interrupt" bitfld.long 0x00 28. " INTPND[125] ,Interrupt Pending Bit[125]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " INTPND[124] ,Interrupt Pending Bit[124]" "No interrupt,Interrupt" bitfld.long 0x00 26. " INTPND[123] ,Interrupt Pending Bit[123]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 25. " INTPND[122] ,Interrupt Pending Bit[122]" "No interrupt,Interrupt" bitfld.long 0x00 24. " INTPND[121] ,Interrupt Pending Bit[121]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " INTPND[120] ,Interrupt Pending Bit[120]" "No interrupt,Interrupt" bitfld.long 0x00 22. " INTPND[119] ,Interrupt Pending Bit[119]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 21. " INTPND[118] ,Interrupt Pending Bit[118]" "No interrupt,Interrupt" bitfld.long 0x00 20. " INTPND[117] ,Interrupt Pending Bit[117]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " INTPND[116] ,Interrupt Pending Bit[116]" "No interrupt,Interrupt" bitfld.long 0x00 18. " INTPND[115] ,Interrupt Pending Bit[115]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 17. " INTPND[114] ,Interrupt Pending Bit[114]" "No interrupt,Interrupt" bitfld.long 0x00 16. " INTPND[113] ,Interrupt Pending Bit[113]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 15. " INTPND[112] ,Interrupt Pending Bit[112]" "No interrupt,Interrupt" bitfld.long 0x00 14. " INTPND[111] ,Interrupt Pending Bit[111]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 13. " INTPND[110] ,Interrupt Pending Bit[110]" "No interrupt,Interrupt" bitfld.long 0x00 12. " INTPND[109] ,Interrupt Pending Bit[109]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " INTPND[108] ,Interrupt Pending Bit[108]" "No interrupt,Interrupt" bitfld.long 0x00 10. " INTPND[107] ,Interrupt Pending Bit[107]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 9. " INTPND[106] ,Interrupt Pending Bit[106]" "No interrupt,Interrupt" bitfld.long 0x00 8. " INTPND[105] ,Interrupt Pending Bit[105]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 7. " INTPND[104] ,Interrupt Pending Bit[104]" "No interrupt,Interrupt" bitfld.long 0x00 6. " INTPND[103] ,Interrupt Pending Bit[103]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 5. " INTPND[102] ,Interrupt Pending Bit[102]" "No interrupt,Interrupt" bitfld.long 0x00 4. " INTPND[101] ,Interrupt Pending Bit[101]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " INTPND[100] ,Interrupt Pending Bit[100]" "No interrupt,Interrupt" bitfld.long 0x00 2. " INTPND[99] ,Interrupt Pending Bit[99]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " INTPND[98] ,Interrupt Pending Bit[98]" "No interrupt,Interrupt" bitfld.long 0x00 0. " INTPND[97] ,Interrupt Pending Bit[97]" "No interrupt,Interrupt" rgroup.long 0xC0++0x3 line.long 0x0 "MSGVALX,Message Valid X" bitfld.long 0x00 14.--15. " MSGVALREG8 ,Message Valid 8 Register" "0,1,2,3" bitfld.long 0x00 12.--13. " MSGVALREG7 ,Message Valid 7 Register" "0,1,2,3" bitfld.long 0x00 10.--11. " MSGVALREG6 ,Message Valid 6 Register" "0,1,2,3" textline " " bitfld.long 0x00 8.--9. " MSGVALREG5 ,Message Valid 5 Register" "0,1,2,3" bitfld.long 0x00 6.--7. " MSGVALREG4 ,Message Valid 4 Register" "0,1,2,3" bitfld.long 0x00 4.--5. " MSGVALREG3 ,Message Valid 3 Register" "0,1,2,3" textline " " bitfld.long 0x00 2.--3. " MSGVALREG2 ,Message Valid 2 Register" "0,1,2,3" bitfld.long 0x00 0.--1. " MSGVALREG1 ,Message Valid 1 Register" "0,1,2,3" rgroup.long 0xC4++0x3 line.long 0x0 "MSGVAL12,Message Valid 2-1" bitfld.long 0x00 31. " MSGVAL[32] ,Message Valid Bit[32]" "Ignored,Configured" bitfld.long 0x00 30. " MSGVAL[31] ,Message Valid Bit[31]" "Ignored,Configured" textline " " bitfld.long 0x00 29. " MSGVAL[30] ,Message Valid Bit[30]" "Ignored,Configured" bitfld.long 0x00 28. " MSGVAL[29] ,Message Valid Bit[29]" "Ignored,Configured" textline " " bitfld.long 0x00 27. " MSGVAL[28] ,Message Valid Bit[28]" "Ignored,Configured" bitfld.long 0x00 26. " MSGVAL[27] ,Message Valid Bit[27]" "Ignored,Configured" textline " " bitfld.long 0x00 25. " MSGVAL[26] ,Message Valid Bit[26]" "Ignored,Configured" bitfld.long 0x00 24. " MSGVAL[25] ,Message Valid Bit[25]" "Ignored,Configured" textline " " bitfld.long 0x00 23. " MSGVAL[24] ,Message Valid Bit[24]" "Ignored,Configured" bitfld.long 0x00 22. " MSGVAL[23] ,Message Valid Bit[23]" "Ignored,Configured" textline " " bitfld.long 0x00 21. " MSGVAL[22] ,Message Valid Bit[22]" "Ignored,Configured" bitfld.long 0x00 20. " MSGVAL[21] ,Message Valid Bit[21]" "Ignored,Configured" textline " " bitfld.long 0x00 19. " MSGVAL[20] ,Message Valid Bit[20]" "Ignored,Configured" bitfld.long 0x00 18. " MSGVAL[19] ,Message Valid Bit[19]" "Ignored,Configured" textline " " bitfld.long 0x00 17. " MSGVAL[18] ,Message Valid Bit[18]" "Ignored,Configured" bitfld.long 0x00 16. " MSGVAL[17] ,Message Valid Bit[17]" "Ignored,Configured" textline " " bitfld.long 0x00 15. " MSGVAL[16] ,Message Valid Bit[16]" "Ignored,Configured" bitfld.long 0x00 14. " MSGVAL[15] ,Message Valid Bit[15]" "Ignored,Configured" textline " " bitfld.long 0x00 13. " MSGVAL[14] ,Message Valid Bit[14]" "Ignored,Configured" bitfld.long 0x00 12. " MSGVAL[13] ,Message Valid Bit[13]" "Ignored,Configured" textline " " bitfld.long 0x00 11. " MSGVAL[12] ,Message Valid Bit[12]" "Ignored,Configured" bitfld.long 0x00 10. " MSGVAL[11] ,Message Valid Bit[11]" "Ignored,Configured" textline " " bitfld.long 0x00 9. " MSGVAL[10] ,Message Valid Bit[10]" "Ignored,Configured" bitfld.long 0x00 8. " MSGVAL[9] ,Message Valid Bit[9]" "Ignored,Configured" textline " " bitfld.long 0x00 7. " MSGVAL[8] ,Message Valid Bit[8]" "Ignored,Configured" bitfld.long 0x00 6. " MSGVAL[7] ,Message Valid Bit[7]" "Ignored,Configured" textline " " bitfld.long 0x00 5. " MSGVAL[6] ,Message Valid Bit[6]" "Ignored,Configured" bitfld.long 0x00 4. " MSGVAL[5] ,Message Valid Bit[5]" "Ignored,Configured" textline " " bitfld.long 0x00 3. " MSGVAL[4] ,Message Valid Bit[4]" "Ignored,Configured" bitfld.long 0x00 2. " MSGVAL[3] ,Message Valid Bit[3]" "Ignored,Configured" textline " " bitfld.long 0x00 1. " MSGVAL[2] ,Message Valid Bit[2]" "Ignored,Configured" bitfld.long 0x00 0. " MSGVAL[1] ,Message Valid Bit[1]" "Ignored,Configured" rgroup.long 0xC8++0x3 line.long 0x0 "MSGVAL34,Message Valid 4-3" bitfld.long 0x00 31. " MSGVAL[64] ,Message Valid Bit[64]" "Ignored,Configured" bitfld.long 0x00 30. " MSGVAL[63] ,Message Valid Bit[63]" "Ignored,Configured" textline " " bitfld.long 0x00 29. " MSGVAL[62] ,Message Valid Bit[62]" "Ignored,Configured" bitfld.long 0x00 28. " MSGVAL[61] ,Message Valid Bit[61]" "Ignored,Configured" textline " " bitfld.long 0x00 27. " MSGVAL[60] ,Message Valid Bit[60]" "Ignored,Configured" bitfld.long 0x00 26. " MSGVAL[59] ,Message Valid Bit[59]" "Ignored,Configured" textline " " bitfld.long 0x00 25. " MSGVAL[58] ,Message Valid Bit[58]" "Ignored,Configured" bitfld.long 0x00 24. " MSGVAL[57] ,Message Valid Bit[57]" "Ignored,Configured" textline " " bitfld.long 0x00 23. " MSGVAL[56] ,Message Valid Bit[56]" "Ignored,Configured" bitfld.long 0x00 22. " MSGVAL[55] ,Message Valid Bit[55]" "Ignored,Configured" textline " " bitfld.long 0x00 21. " MSGVAL[54] ,Message Valid Bit[54]" "Ignored,Configured" bitfld.long 0x00 20. " MSGVAL[53] ,Message Valid Bit[53]" "Ignored,Configured" textline " " bitfld.long 0x00 19. " MSGVAL[52] ,Message Valid Bit[52]" "Ignored,Configured" bitfld.long 0x00 18. " MSGVAL[51] ,Message Valid Bit[51]" "Ignored,Configured" textline " " bitfld.long 0x00 17. " MSGVAL[50] ,Message Valid Bit[50]" "Ignored,Configured" bitfld.long 0x00 16. " MSGVAL[49] ,Message Valid Bit[49]" "Ignored,Configured" textline " " bitfld.long 0x00 15. " MSGVAL[48] ,Message Valid Bit[48]" "Ignored,Configured" bitfld.long 0x00 14. " MSGVAL[47] ,Message Valid Bit[47]" "Ignored,Configured" textline " " bitfld.long 0x00 13. " MSGVAL[46] ,Message Valid Bit[46]" "Ignored,Configured" bitfld.long 0x00 12. " MSGVAL[45] ,Message Valid Bit[45]" "Ignored,Configured" textline " " bitfld.long 0x00 11. " MSGVAL[44] ,Message Valid Bit[44]" "Ignored,Configured" bitfld.long 0x00 10. " MSGVAL[43] ,Message Valid Bit[43]" "Ignored,Configured" textline " " bitfld.long 0x00 9. " MSGVAL[42] ,Message Valid Bit[42]" "Ignored,Configured" bitfld.long 0x00 8. " MSGVAL[41] ,Message Valid Bit[41]" "Ignored,Configured" textline " " bitfld.long 0x00 7. " MSGVAL[40] ,Message Valid Bit[40]" "Ignored,Configured" bitfld.long 0x00 6. " MSGVAL[39] ,Message Valid Bit[39]" "Ignored,Configured" textline " " bitfld.long 0x00 5. " MSGVAL[38] ,Message Valid Bit[38]" "Ignored,Configured" bitfld.long 0x00 4. " MSGVAL[37] ,Message Valid Bit[37]" "Ignored,Configured" textline " " bitfld.long 0x00 3. " MSGVAL[36] ,Message Valid Bit[36]" "Ignored,Configured" bitfld.long 0x00 2. " MSGVAL[35] ,Message Valid Bit[35]" "Ignored,Configured" textline " " bitfld.long 0x00 1. " MSGVAL[34] ,Message Valid Bit[34]" "Ignored,Configured" bitfld.long 0x00 0. " MSGVAL[33] ,Message Valid Bit[33]" "Ignored,Configured" rgroup.long 0xCC++0x3 line.long 0x0 "MSGVAL56,Message Valid 6-5" bitfld.long 0x00 31. " MSGVAL[96] ,Message Valid Bit[96]" "Ignored,Configured" bitfld.long 0x00 30. " MSGVAL[95] ,Message Valid Bit[95]" "Ignored,Configured" textline " " bitfld.long 0x00 29. " MSGVAL[94] ,Message Valid Bit[94]" "Ignored,Configured" bitfld.long 0x00 28. " MSGVAL[93] ,Message Valid Bit[93]" "Ignored,Configured" textline " " bitfld.long 0x00 27. " MSGVAL[92] ,Message Valid Bit[92]" "Ignored,Configured" bitfld.long 0x00 26. " MSGVAL[91] ,Message Valid Bit[91]" "Ignored,Configured" textline " " bitfld.long 0x00 25. " MSGVAL[90] ,Message Valid Bit[90]" "Ignored,Configured" bitfld.long 0x00 24. " MSGVAL[89] ,Message Valid Bit[89]" "Ignored,Configured" textline " " bitfld.long 0x00 23. " MSGVAL[88] ,Message Valid Bit[88]" "Ignored,Configured" bitfld.long 0x00 22. " MSGVAL[87] ,Message Valid Bit[87]" "Ignored,Configured" textline " " bitfld.long 0x00 21. " MSGVAL[86] ,Message Valid Bit[86]" "Ignored,Configured" bitfld.long 0x00 20. " MSGVAL[85] ,Message Valid Bit[85]" "Ignored,Configured" textline " " bitfld.long 0x00 19. " MSGVAL[84] ,Message Valid Bit[84]" "Ignored,Configured" bitfld.long 0x00 18. " MSGVAL[83] ,Message Valid Bit[83]" "Ignored,Configured" textline " " bitfld.long 0x00 17. " MSGVAL[82] ,Message Valid Bit[82]" "Ignored,Configured" bitfld.long 0x00 16. " MSGVAL[81] ,Message Valid Bit[81]" "Ignored,Configured" textline " " bitfld.long 0x00 15. " MSGVAL[80] ,Message Valid Bit[80]" "Ignored,Configured" bitfld.long 0x00 14. " MSGVAL[79] ,Message Valid Bit[79]" "Ignored,Configured" textline " " bitfld.long 0x00 13. " MSGVAL[78] ,Message Valid Bit[78]" "Ignored,Configured" bitfld.long 0x00 12. " MSGVAL[77] ,Message Valid Bit[77]" "Ignored,Configured" textline " " bitfld.long 0x00 11. " MSGVAL[76] ,Message Valid Bit[76]" "Ignored,Configured" bitfld.long 0x00 10. " MSGVAL[75] ,Message Valid Bit[75]" "Ignored,Configured" textline " " bitfld.long 0x00 9. " MSGVAL[74] ,Message Valid Bit[74]" "Ignored,Configured" bitfld.long 0x00 8. " MSGVAL[73] ,Message Valid Bit[73]" "Ignored,Configured" textline " " bitfld.long 0x00 7. " MSGVAL[72] ,Message Valid Bit[72]" "Ignored,Configured" bitfld.long 0x00 6. " MSGVAL[71] ,Message Valid Bit[71]" "Ignored,Configured" textline " " bitfld.long 0x00 5. " MSGVAL[70] ,Message Valid Bit[70]" "Ignored,Configured" bitfld.long 0x00 4. " MSGVAL[69] ,Message Valid Bit[69]" "Ignored,Configured" textline " " bitfld.long 0x00 3. " MSGVAL[68] ,Message Valid Bit[68]" "Ignored,Configured" bitfld.long 0x00 2. " MSGVAL[67] ,Message Valid Bit[67]" "Ignored,Configured" textline " " bitfld.long 0x00 1. " MSGVAL[66] ,Message Valid Bit[66]" "Ignored,Configured" bitfld.long 0x00 0. " MSGVAL[65] ,Message Valid Bit[65]" "Ignored,Configured" rgroup.long 0xD0++0x3 line.long 0x0 "MSGVAL78,Message Valid 8-7" bitfld.long 0x00 31. " MSGVAL[128] ,Message Valid Bit[128]" "Ignored,Configured" bitfld.long 0x00 30. " MSGVAL[127] ,Message Valid Bit[127]" "Ignored,Configured" textline " " bitfld.long 0x00 29. " MSGVAL[126] ,Message Valid Bit[126]" "Ignored,Configured" bitfld.long 0x00 28. " MSGVAL[125] ,Message Valid Bit[125]" "Ignored,Configured" textline " " bitfld.long 0x00 27. " MSGVAL[124] ,Message Valid Bit[124]" "Ignored,Configured" bitfld.long 0x00 26. " MSGVAL[123] ,Message Valid Bit[123]" "Ignored,Configured" textline " " bitfld.long 0x00 25. " MSGVAL[122] ,Message Valid Bit[122]" "Ignored,Configured" bitfld.long 0x00 24. " MSGVAL[121] ,Message Valid Bit[121]" "Ignored,Configured" textline " " bitfld.long 0x00 23. " MSGVAL[120] ,Message Valid Bit[120]" "Ignored,Configured" bitfld.long 0x00 22. " MSGVAL[119] ,Message Valid Bit[119]" "Ignored,Configured" textline " " bitfld.long 0x00 21. " MSGVAL[118] ,Message Valid Bit[118]" "Ignored,Configured" bitfld.long 0x00 20. " MSGVAL[117] ,Message Valid Bit[117]" "Ignored,Configured" textline " " bitfld.long 0x00 19. " MSGVAL[116] ,Message Valid Bit[116]" "Ignored,Configured" bitfld.long 0x00 18. " MSGVAL[115] ,Message Valid Bit[115]" "Ignored,Configured" textline " " bitfld.long 0x00 17. " MSGVAL[114] ,Message Valid Bit[114]" "Ignored,Configured" bitfld.long 0x00 16. " MSGVAL[113] ,Message Valid Bit[113]" "Ignored,Configured" textline " " bitfld.long 0x00 15. " MSGVAL[112] ,Message Valid Bit[112]" "Ignored,Configured" bitfld.long 0x00 14. " MSGVAL[111] ,Message Valid Bit[111]" "Ignored,Configured" textline " " bitfld.long 0x00 13. " MSGVAL[110] ,Message Valid Bit[110]" "Ignored,Configured" bitfld.long 0x00 12. " MSGVAL[109] ,Message Valid Bit[109]" "Ignored,Configured" textline " " bitfld.long 0x00 11. " MSGVAL[108] ,Message Valid Bit[108]" "Ignored,Configured" bitfld.long 0x00 10. " MSGVAL[107] ,Message Valid Bit[107]" "Ignored,Configured" textline " " bitfld.long 0x00 9. " MSGVAL[106] ,Message Valid Bit[106]" "Ignored,Configured" bitfld.long 0x00 8. " MSGVAL[105] ,Message Valid Bit[105]" "Ignored,Configured" textline " " bitfld.long 0x00 7. " MSGVAL[104] ,Message Valid Bit[104]" "Ignored,Configured" bitfld.long 0x00 6. " MSGVAL[103] ,Message Valid Bit[103]" "Ignored,Configured" textline " " bitfld.long 0x00 5. " MSGVAL[102] ,Message Valid Bit[102]" "Ignored,Configured" bitfld.long 0x00 4. " MSGVAL[101] ,Message Valid Bit[101]" "Ignored,Configured" textline " " bitfld.long 0x00 3. " MSGVAL[100] ,Message Valid Bit[100]" "Ignored,Configured" bitfld.long 0x00 2. " MSGVAL[99] ,Message Valid Bit[99]" "Ignored,Configured" textline " " bitfld.long 0x00 1. " MSGVAL[98] ,Message Valid Bit[98]" "Ignored,Configured" bitfld.long 0x00 0. " MSGVAL[97] ,Message Valid Bit[97]" "Ignored,Configured" group.long 0xD8++0x3 line.long 0x0 "INTPNDMX12,IntPndMux 1-2" bitfld.long 0x00 31. " INTPNDMUX[32] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[32]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 30. " INTPNDMUX[31] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[31]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 29. " INTPNDMUX[30] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[30]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 28. " INTPNDMUX[29] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[29]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 27. " INTPNDMUX[28] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[28]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 26. " INTPNDMUX[27] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[27]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 25. " INTPNDMUX[26] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[26]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 24. " INTPNDMUX[25] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[25]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 23. " INTPNDMUX[24] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[24]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 22. " INTPNDMUX[23] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[23]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 21. " INTPNDMUX[22] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[22]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 20. " INTPNDMUX[21] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[21]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 19. " INTPNDMUX[20] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[20]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 18. " INTPNDMUX[19] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[19]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 17. " INTPNDMUX[18] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[18]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 16. " INTPNDMUX[17] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[17]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 15. " INTPNDMUX[16] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[16]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 14. " INTPNDMUX[15] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[15]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 13. " INTPNDMUX[14] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[14]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 12. " INTPNDMUX[13] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[13]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 11. " INTPNDMUX[12] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[12]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 10. " INTPNDMUX[11] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[11]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 9. " INTPNDMUX[10] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[10]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 8. " INTPNDMUX[9] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[9]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 7. " INTPNDMUX[8] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[8]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 6. " INTPNDMUX[7] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[7]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 5. " INTPNDMUX[6] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[6]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 4. " INTPNDMUX[5] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[5]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 3. " INTPNDMUX[4] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[4]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 2. " INTPNDMUX[3] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[3]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 1. " INTPNDMUX[2] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[2]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 0. " INTPNDMUX[1] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[1]" "DCAN0INT,DCAN1INT" group.long 0xDC++0x3 line.long 0x0 "INTPNDMX34,IntPndMux 3-4" bitfld.long 0x00 31. " INTPNDMUX[64] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[64]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 30. " INTPNDMUX[63] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[63]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 29. " INTPNDMUX[62] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[62]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 28. " INTPNDMUX[61] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[61]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 27. " INTPNDMUX[60] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[60]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 26. " INTPNDMUX[59] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[59]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 25. " INTPNDMUX[58] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[58]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 24. " INTPNDMUX[57] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[57]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 23. " INTPNDMUX[56] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[56]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 22. " INTPNDMUX[55] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[55]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 21. " INTPNDMUX[54] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[54]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 20. " INTPNDMUX[53] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[53]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 19. " INTPNDMUX[52] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[52]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 18. " INTPNDMUX[51] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[51]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 17. " INTPNDMUX[50] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[50]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 16. " INTPNDMUX[49] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[49]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 15. " INTPNDMUX[48] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[48]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 14. " INTPNDMUX[47] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[47]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 13. " INTPNDMUX[46] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[46]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 12. " INTPNDMUX[45] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[45]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 11. " INTPNDMUX[44] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[44]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 10. " INTPNDMUX[43] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[43]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 9. " INTPNDMUX[42] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[42]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 8. " INTPNDMUX[41] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[41]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 7. " INTPNDMUX[40] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[40]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 6. " INTPNDMUX[39] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[39]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 5. " INTPNDMUX[38] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[38]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 4. " INTPNDMUX[37] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[37]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 3. " INTPNDMUX[36] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[36]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 2. " INTPNDMUX[35] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[35]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 1. " INTPNDMUX[34] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[34]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 0. " INTPNDMUX[33] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[33]" "DCAN0INT,DCAN1INT" group.long 0xE0++0x3 line.long 0x0 "INTPNDMX56,IntPndMux 5-6" bitfld.long 0x00 31. " INTPNDMUX[96] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[96]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 30. " INTPNDMUX[95] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[95]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 29. " INTPNDMUX[94] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[94]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 28. " INTPNDMUX[93] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[93]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 27. " INTPNDMUX[92] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[92]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 26. " INTPNDMUX[91] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[91]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 25. " INTPNDMUX[90] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[90]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 24. " INTPNDMUX[89] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[89]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 23. " INTPNDMUX[88] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[88]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 22. " INTPNDMUX[87] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[87]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 21. " INTPNDMUX[86] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[86]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 20. " INTPNDMUX[85] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[85]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 19. " INTPNDMUX[84] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[84]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 18. " INTPNDMUX[83] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[83]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 17. " INTPNDMUX[82] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[82]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 16. " INTPNDMUX[81] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[81]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 15. " INTPNDMUX[80] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[80]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 14. " INTPNDMUX[79] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[79]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 13. " INTPNDMUX[78] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[78]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 12. " INTPNDMUX[77] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[77]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 11. " INTPNDMUX[76] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[76]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 10. " INTPNDMUX[75] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[75]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 9. " INTPNDMUX[74] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[74]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 8. " INTPNDMUX[73] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[73]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 7. " INTPNDMUX[72] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[72]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 6. " INTPNDMUX[71] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[71]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 5. " INTPNDMUX[70] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[70]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 4. " INTPNDMUX[69] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[69]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 3. " INTPNDMUX[68] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[68]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 2. " INTPNDMUX[67] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[67]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 1. " INTPNDMUX[66] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[66]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 0. " INTPNDMUX[65] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[65]" "DCAN0INT,DCAN1INT" group.long 0xE4++0x3 line.long 0x0 "INTPNDMX78,IntPndMux 7-8" bitfld.long 0x00 31. " INTPNDMUX[128] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[128]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 30. " INTPNDMUX[127] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[127]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 29. " INTPNDMUX[126] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[126]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 28. " INTPNDMUX[125] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[125]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 27. " INTPNDMUX[124] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[124]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 26. " INTPNDMUX[123] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[123]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 25. " INTPNDMUX[122] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[122]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 24. " INTPNDMUX[121] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[121]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 23. " INTPNDMUX[120] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[120]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 22. " INTPNDMUX[119] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[119]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 21. " INTPNDMUX[118] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[118]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 20. " INTPNDMUX[117] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[117]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 19. " INTPNDMUX[116] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[116]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 18. " INTPNDMUX[115] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[115]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 17. " INTPNDMUX[114] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[114]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 16. " INTPNDMUX[113] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[113]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 15. " INTPNDMUX[112] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[112]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 14. " INTPNDMUX[111] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[111]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 13. " INTPNDMUX[110] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[110]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 12. " INTPNDMUX[109] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[109]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 11. " INTPNDMUX[108] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[108]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 10. " INTPNDMUX[107] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[107]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 9. " INTPNDMUX[106] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[106]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 8. " INTPNDMUX[105] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[105]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 7. " INTPNDMUX[104] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[104]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 6. " INTPNDMUX[103] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[103]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 5. " INTPNDMUX[102] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[102]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 4. " INTPNDMUX[101] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[101]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 3. " INTPNDMUX[100] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[100]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 2. " INTPNDMUX[99] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[99]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 1. " INTPNDMUX[98] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[98]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 0. " INTPNDMUX[97] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[97]" "DCAN0INT,DCAN1INT" width 9. tree "IF1 / IF2" group.long 0x100++0x3 line.long 0x0 "IF1COM,IF1 Command Mask / Command Request Register" bitfld.long 0x00 23. " WR/RD ,Write / Read" "Read,Write" bitfld.long 0x00 22. " MASK ,Access Mask Bits" "Not accessed,Accessed" textline " " bitfld.long 0x00 21. " ARB ,Access Arbitration Bits" "Not accessed,Accessed" bitfld.long 0x00 20. " CONTROL ,Access Control Bits" "Unchanged,Control bits" textline " " bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Low,High" bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Not requested,Requested" textline " " bitfld.long 0x00 17. " DATA_A ,Access Data Bytes 0-3" "Unchanged,Data bytes 0-3" bitfld.long 0x00 16. " DATA_B ,Access Data Bytes 4-7" "Unchanged,Data bytes 4-7" textline " " bitfld.long 0x00 15. " BUSY ,Busy Flag" "Reset,Set" bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA Feature for Subsequent Internal IF1 Update" "No active,Active" textline " " hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Message Number" group.long 0x120++0x3 line.long 0x0 "IF2COM,IF2 Command Mask / Command Request Register" bitfld.long 0x00 23. " WR/RD ,Write / Read" "Read,Write" bitfld.long 0x00 22. " MASK ,Access Mask Bits" "Not accessed,Accessed" textline " " bitfld.long 0x00 21. " ARB ,Access Arbitration Bits" "Not accessed,Accessed" bitfld.long 0x00 20. " CONTROL ,Access Control Bits" "Unchanged,Control bits" textline " " bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Low,High" bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Not requested,Requested" textline " " bitfld.long 0x00 17. " DATA_A ,Access Data Bytes 0-3" "Unchanged,Data bytes 0-3" bitfld.long 0x00 16. " DATA_B ,Access Data Bytes 4-7" "Unchanged,Data bytes 4-7" textline " " bitfld.long 0x00 15. " BUSY ,Busy Flag" "Reset,Set" bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA Feature for Subsequent Internal IF1 Update" "No active,Active" textline " " hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Message Number" group.long 0x104++0x3 line.long 0x0 "IF1MSK,If1 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Not masked,Masked" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Not masked,Masked" textline " " bitfld.long 0x00 28. " MSK[28] ,Identifier Mask 28" "Not masked,Masked" bitfld.long 0x00 27. " MSK[27] ,Identifier Mask 27" "Not masked,Masked" bitfld.long 0x00 26. " MSK[26] ,Identifier Mask 26" "Not masked,Masked" textline " " bitfld.long 0x00 25. " MSK[25] ,Identifier Mask 25" "Not masked,Masked" bitfld.long 0x00 24. " MSK[24] ,Identifier Mask 24" "Not masked,Masked" bitfld.long 0x00 23. " MSK[23] ,Identifier Mask 23" "Not masked,Masked" textline " " bitfld.long 0x00 22. " MSK[22] ,Identifier Mask 22" "Not masked,Masked" bitfld.long 0x00 21. " MSK[21] ,Identifier Mask 21" "Not masked,Masked" bitfld.long 0x00 20. " MSK[20] ,Identifier Mask 20" "Not masked,Masked" textline " " bitfld.long 0x00 19. " MSK[19] ,Identifier Mask 19" "Not masked,Masked" bitfld.long 0x00 18. " MSK[18] ,Identifier Mask 18" "Not masked,Masked" bitfld.long 0x00 17. " MSK[17] ,Identifier Mask 17" "Not masked,Masked" textline " " bitfld.long 0x00 16. " MSK[16] ,Identifier Mask 16" "Not masked,Masked" bitfld.long 0x00 15. " MSK[15] ,Identifier Mask 15" "Not masked,Masked" bitfld.long 0x00 14. " MSK[14] ,Identifier Mask 14" "Not masked,Masked" textline " " bitfld.long 0x00 13. " MSK[13] ,Identifier Mask 13" "Not masked,Masked" bitfld.long 0x00 12. " MSK[12] ,Identifier Mask 12" "Not masked,Masked" bitfld.long 0x00 11. " MSK[11] ,Identifier Mask 11" "Not masked,Masked" textline " " bitfld.long 0x00 10. " MSK[10] ,Identifier Mask 10" "Not masked,Masked" bitfld.long 0x00 9. " MSK[9] ,Identifier Mask 9" "Not masked,Masked" bitfld.long 0x00 8. " MSK[8] ,Identifier Mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MSK[7] ,Identifier Mask 7" "Not masked,Masked" bitfld.long 0x00 6. " MSK[6] ,Identifier Mask 6" "Not masked,Masked" bitfld.long 0x00 5. " MSK[5] ,Identifier Mask 5" "Not masked,Masked" textline " " bitfld.long 0x00 4. " MSK[4] ,Identifier Mask 4" "Not masked,Masked" bitfld.long 0x00 3. " MSK[3] ,Identifier Mask 3" "Not masked,Masked" bitfld.long 0x00 2. " MSK[2] ,Identifier Mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " MSK[1] ,Identifier Mask 1" "Not masked,Masked" bitfld.long 0x00 0. " MSK[0] ,Identifier Mask 0" "Not masked,Masked" group.long 0x124++0x3 line.long 0x0 "IF2MSK,If2 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Not masked,Masked" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Not masked,Masked" textline " " bitfld.long 0x00 28. " MSK[28] ,Identifier Mask 28" "Not masked,Masked" bitfld.long 0x00 27. " MSK[27] ,Identifier Mask 27" "Not masked,Masked" bitfld.long 0x00 26. " MSK[26] ,Identifier Mask 26" "Not masked,Masked" textline " " bitfld.long 0x00 25. " MSK[25] ,Identifier Mask 25" "Not masked,Masked" bitfld.long 0x00 24. " MSK[24] ,Identifier Mask 24" "Not masked,Masked" bitfld.long 0x00 23. " MSK[23] ,Identifier Mask 23" "Not masked,Masked" textline " " bitfld.long 0x00 22. " MSK[22] ,Identifier Mask 22" "Not masked,Masked" bitfld.long 0x00 21. " MSK[21] ,Identifier Mask 21" "Not masked,Masked" bitfld.long 0x00 20. " MSK[20] ,Identifier Mask 20" "Not masked,Masked" textline " " bitfld.long 0x00 19. " MSK[19] ,Identifier Mask 19" "Not masked,Masked" bitfld.long 0x00 18. " MSK[18] ,Identifier Mask 18" "Not masked,Masked" bitfld.long 0x00 17. " MSK[17] ,Identifier Mask 17" "Not masked,Masked" textline " " bitfld.long 0x00 16. " MSK[16] ,Identifier Mask 16" "Not masked,Masked" bitfld.long 0x00 15. " MSK[15] ,Identifier Mask 15" "Not masked,Masked" bitfld.long 0x00 14. " MSK[14] ,Identifier Mask 14" "Not masked,Masked" textline " " bitfld.long 0x00 13. " MSK[13] ,Identifier Mask 13" "Not masked,Masked" bitfld.long 0x00 12. " MSK[12] ,Identifier Mask 12" "Not masked,Masked" bitfld.long 0x00 11. " MSK[11] ,Identifier Mask 11" "Not masked,Masked" textline " " bitfld.long 0x00 10. " MSK[10] ,Identifier Mask 10" "Not masked,Masked" bitfld.long 0x00 9. " MSK[9] ,Identifier Mask 9" "Not masked,Masked" bitfld.long 0x00 8. " MSK[8] ,Identifier Mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MSK[7] ,Identifier Mask 7" "Not masked,Masked" bitfld.long 0x00 6. " MSK[6] ,Identifier Mask 6" "Not masked,Masked" bitfld.long 0x00 5. " MSK[5] ,Identifier Mask 5" "Not masked,Masked" textline " " bitfld.long 0x00 4. " MSK[4] ,Identifier Mask 4" "Not masked,Masked" bitfld.long 0x00 3. " MSK[3] ,Identifier Mask 3" "Not masked,Masked" bitfld.long 0x00 2. " MSK[2] ,Identifier Mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " MSK[1] ,Identifier Mask 1" "Not masked,Masked" bitfld.long 0x00 0. " MSK[0] ,Identifier Mask 0" "Not masked,Masked" group.long 0x108++0x3 line.long 0x0 "IF1ARB,If1 Arbitation Register" bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Ignored,Used" bitfld.long 0x00 30. " XTD ,Extended Identifier" "11-bit-standard,29-bit-extended" bitfld.long 0x00 29. " DIR ,Message direction" "Receive,Transmit" textline " " bitfld.long 0x00 28. " ID[28] ,Message Identifier 28" "29-bit ID,11-bit ID" bitfld.long 0x00 27. " ID[27] ,Message Identifier 27" "29-bit ID,11-bit ID" bitfld.long 0x00 26. " ID[26] ,Message Identifier 26" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 25. " ID[25] ,Message Identifier 25" "29-bit ID,11-bit ID" bitfld.long 0x00 24. " ID[24] ,Message Identifier 24" "29-bit ID,11-bit ID" bitfld.long 0x00 23. " ID[23] ,Message Identifier 23" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 22. " ID[22] ,Message Identifier 22" "29-bit ID,11-bit ID" bitfld.long 0x00 21. " ID[21] ,Message Identifier 21" "29-bit ID,11-bit ID" bitfld.long 0x00 20. " ID[20] ,Message Identifier 20" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 19. " ID[19] ,Message Identifier 19" "29-bit ID,11-bit ID" bitfld.long 0x00 18. " ID[18] ,Message Identifier 18" "29-bit ID,11-bit ID" bitfld.long 0x00 17. " ID[17] ,Message Identifier 17" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 16. " ID[16] ,Message Identifier 16" "29-bit ID,11-bit ID" bitfld.long 0x00 15. " ID[15] ,Message Identifier 15" "29-bit ID,11-bit ID" bitfld.long 0x00 14. " ID[14] ,Message Identifier 14" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 13. " ID[13] ,Message Identifier 13" "29-bit ID,11-bit ID" bitfld.long 0x00 12. " ID[12] ,Message Identifier 12" "29-bit ID,11-bit ID" bitfld.long 0x00 11. " ID[11] ,Message Identifier 11" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 10. " ID[10] ,Message Identifier 10" "29-bit ID,11-bit ID" bitfld.long 0x00 9. " ID[9] ,Message Identifier 9" "29-bit ID,11-bit ID" bitfld.long 0x00 8. " ID[8] ,Message Identifier 8" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 7. " ID[7] ,Message Identifier 7" "29-bit ID,11-bit ID" bitfld.long 0x00 6. " ID[6] ,Message Identifier 6" "29-bit ID,11-bit ID" bitfld.long 0x00 5. " ID[5] ,Message Identifier 5" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 4. " ID[4] ,Message Identifier 4" "29-bit ID,11-bit ID" bitfld.long 0x00 3. " ID[3] ,Message Identifier 3" "29-bit ID,11-bit ID" bitfld.long 0x00 2. " ID[2] ,Message Identifier 2" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 1. " ID[1] ,Message Identifier 1" "29-bit ID,11-bit ID" bitfld.long 0x00 0. " ID[0] ,Message Identifier 0" "29-bit ID,11-bit ID" group.long 0x128++0x3 line.long 0x0 "IF2ARB,If2 Arbitation Register" bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Ignored,Used" bitfld.long 0x00 30. " XTD ,Extended Identifier" "11-bit-standard,29-bit-extended" bitfld.long 0x00 29. " DIR ,Message direction" "Receive,Transmit" textline " " bitfld.long 0x00 28. " ID[28] ,Message Identifier 28" "29-bit ID,11-bit ID" bitfld.long 0x00 27. " ID[27] ,Message Identifier 27" "29-bit ID,11-bit ID" bitfld.long 0x00 26. " ID[26] ,Message Identifier 26" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 25. " ID[25] ,Message Identifier 25" "29-bit ID,11-bit ID" bitfld.long 0x00 24. " ID[24] ,Message Identifier 24" "29-bit ID,11-bit ID" bitfld.long 0x00 23. " ID[23] ,Message Identifier 23" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 22. " ID[22] ,Message Identifier 22" "29-bit ID,11-bit ID" bitfld.long 0x00 21. " ID[21] ,Message Identifier 21" "29-bit ID,11-bit ID" bitfld.long 0x00 20. " ID[20] ,Message Identifier 20" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 19. " ID[19] ,Message Identifier 19" "29-bit ID,11-bit ID" bitfld.long 0x00 18. " ID[18] ,Message Identifier 18" "29-bit ID,11-bit ID" bitfld.long 0x00 17. " ID[17] ,Message Identifier 17" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 16. " ID[16] ,Message Identifier 16" "29-bit ID,11-bit ID" bitfld.long 0x00 15. " ID[15] ,Message Identifier 15" "29-bit ID,11-bit ID" bitfld.long 0x00 14. " ID[14] ,Message Identifier 14" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 13. " ID[13] ,Message Identifier 13" "29-bit ID,11-bit ID" bitfld.long 0x00 12. " ID[12] ,Message Identifier 12" "29-bit ID,11-bit ID" bitfld.long 0x00 11. " ID[11] ,Message Identifier 11" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 10. " ID[10] ,Message Identifier 10" "29-bit ID,11-bit ID" bitfld.long 0x00 9. " ID[9] ,Message Identifier 9" "29-bit ID,11-bit ID" bitfld.long 0x00 8. " ID[8] ,Message Identifier 8" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 7. " ID[7] ,Message Identifier 7" "29-bit ID,11-bit ID" bitfld.long 0x00 6. " ID[6] ,Message Identifier 6" "29-bit ID,11-bit ID" bitfld.long 0x00 5. " ID[5] ,Message Identifier 5" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 4. " ID[4] ,Message Identifier 4" "29-bit ID,11-bit ID" bitfld.long 0x00 3. " ID[3] ,Message Identifier 3" "29-bit ID,11-bit ID" bitfld.long 0x00 2. " ID[2] ,Message Identifier 2" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 1. " ID[1] ,Message Identifier 1" "29-bit ID,11-bit ID" bitfld.long 0x00 0. " ID[0] ,Message Identifier 0" "29-bit ID,11-bit ID" hgroup.long 0x10C++0x3 hide.long 0x0 "IF1MCTL,If1 Message Control Register" in hgroup.long 0x12C++0x3 hide.long 0x0 "IF2MCTL,If2 Message Control Register" in group.long 0x110++0x3 line.long 0x0 "IF1DATA,If1 Data A Register" hexmask.long.byte 0x00 24.--31. 1. " DATA_3 ,Data 3" hexmask.long.byte 0x00 16.--23. 1. " DATA_2 ,Data 2" textline " " hexmask.long.byte 0x00 8.--15. 1. " DATA_1 ,Data 1" hexmask.long.byte 0x00 0.--7. 1. " DATA_0 ,Data 0" group.long 0x114++0x3 line.long 0x0 "IF1DATB,If1 Data B Register" hexmask.long.byte 0x00 24.--31. 1. " DATA_7 ,Data 7" hexmask.long.byte 0x00 16.--23. 1. " DATA_6 ,Data 6" textline " " hexmask.long.byte 0x00 8.--15. 1. " DATA_5 ,Data 5" hexmask.long.byte 0x00 0.--7. 1. " DATA_4 ,Data 4" group.long 0x130++0x3 line.long 0x0 "IF2DATA,If2 Data A Register" hexmask.long.byte 0x00 24.--31. 1. " DATA_3 ,Data 3" hexmask.long.byte 0x00 16.--23. 1. " DATA_2 ,Data 2" textline " " hexmask.long.byte 0x00 8.--15. 1. " DATA_1 ,Data 1" hexmask.long.byte 0x00 0.--7. 1. " DATA_0 ,Data 0" group.long 0x134++0x3 line.long 0x0 "IF2DATB,If2 Data B Register" hexmask.long.byte 0x00 24.--31. 1. " DATA_7 ,Data 7" hexmask.long.byte 0x00 16.--23. 1. " DATA_6 ,Data 6" textline " " hexmask.long.byte 0x00 8.--15. 1. " DATA_5 ,Data 5" hexmask.long.byte 0x00 0.--7. 1. " DATA_4 ,Data 4" tree.end tree "IF 3" group.long 0x140++0x3 line.long 0x0 "IF3OBS,If3 Observation Register" bitfld.long 0x00 15. " IF3_UPD ,IF3 Update Data" "No,Yes" bitfld.long 0x00 12. " IF3_SDB ,IF3 Status of Data B read access" "No access,Access" bitfld.long 0x00 11. " IF3_SDA ,IF3 Status of Data A read access" "No access,Access" textline " " bitfld.long 0x00 10. " IF3_SC ,IF3 Status of Control bits read access" "No access,Access" bitfld.long 0x00 9. " IF3_SA ,IF3 Status of Arbitration data read access" "No access,Access" bitfld.long 0x00 8. " IF3_SM ,IF3 Status of Mask data read access" "No access,Access" textline " " bitfld.long 0x00 4. " DATA_B ,Data B read observation" "No,Yes" bitfld.long 0x00 3. " DATA_A ,Data A read observation" "No,Yes" bitfld.long 0x00 2. " CTRL ,Ctrl read observation" "No,Yes" textline " " bitfld.long 0x00 1. " ARB ,Arbitration data read observation" "No,Yes" bitfld.long 0x00 0. " MASK ,Mask data read observation" "No,Yes" group.long 0x144++0x3 line.long 0x0 "IF3MSK,If3 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Not masked,Masked" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Not masked,Masked" textline " " bitfld.long 0x00 28. " MSK[28] ,Identifier Mask 28" "Not masked,Masked" bitfld.long 0x00 27. " MSK[27] ,Identifier Mask 27" "Not masked,Masked" bitfld.long 0x00 26. " MSK[26] ,Identifier Mask 26" "Not masked,Masked" textline " " bitfld.long 0x00 25. " MSK[25] ,Identifier Mask 25" "Not masked,Masked" bitfld.long 0x00 24. " MSK[24] ,Identifier Mask 24" "Not masked,Masked" bitfld.long 0x00 23. " MSK[23] ,Identifier Mask 23" "Not masked,Masked" textline " " bitfld.long 0x00 22. " MSK[22] ,Identifier Mask 22" "Not masked,Masked" bitfld.long 0x00 21. " MSK[21] ,Identifier Mask 21" "Not masked,Masked" bitfld.long 0x00 20. " MSK[20] ,Identifier Mask 20" "Not masked,Masked" textline " " bitfld.long 0x00 19. " MSK[19] ,Identifier Mask 19" "Not masked,Masked" bitfld.long 0x00 18. " MSK[18] ,Identifier Mask 18" "Not masked,Masked" bitfld.long 0x00 17. " MSK[17] ,Identifier Mask 17" "Not masked,Masked" textline " " bitfld.long 0x00 16. " MSK[16] ,Identifier Mask 16" "Not masked,Masked" bitfld.long 0x00 15. " MSK[15] ,Identifier Mask 15" "Not masked,Masked" bitfld.long 0x00 14. " MSK[14] ,Identifier Mask 14" "Not masked,Masked" textline " " bitfld.long 0x00 13. " MSK[13] ,Identifier Mask 13" "Not masked,Masked" bitfld.long 0x00 12. " MSK[12] ,Identifier Mask 12" "Not masked,Masked" bitfld.long 0x00 11. " MSK[11] ,Identifier Mask 11" "Not masked,Masked" textline " " bitfld.long 0x00 10. " MSK[10] ,Identifier Mask 10" "Not masked,Masked" bitfld.long 0x00 9. " MSK[9] ,Identifier Mask 9" "Not masked,Masked" bitfld.long 0x00 8. " MSK[8] ,Identifier Mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MSK[7] ,Identifier Mask 7" "Not masked,Masked" bitfld.long 0x00 6. " MSK[6] ,Identifier Mask 6" "Not masked,Masked" bitfld.long 0x00 5. " MSK[5] ,Identifier Mask 5" "Not masked,Masked" textline " " bitfld.long 0x00 4. " MSK[4] ,Identifier Mask 4" "Not masked,Masked" bitfld.long 0x00 3. " MSK[3] ,Identifier Mask 3" "Not masked,Masked" bitfld.long 0x00 2. " MSK[2] ,Identifier Mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " MSK[1] ,Identifier Mask 1" "Not masked,Masked" bitfld.long 0x00 0. " MSK[0] ,Identifier Mask 0" "Not masked,Masked" group.long 0x148++0x3 line.long 0x0 "IF3ARB,If3 Arbitation Register" bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Ignored,Used" bitfld.long 0x00 30. " XTD ,Extended Identifier" "11-bit-standard,29-bit-extended" bitfld.long 0x00 29. " DIR ,Message direction" "Receive,Transmit" textline " " bitfld.long 0x00 28. " ID[28] ,Message Identifier 28" "29-bit ID,11-bit ID" bitfld.long 0x00 27. " ID[27] ,Message Identifier 27" "29-bit ID,11-bit ID" bitfld.long 0x00 26. " ID[26] ,Message Identifier 26" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 25. " ID[25] ,Message Identifier 25" "29-bit ID,11-bit ID" bitfld.long 0x00 24. " ID[24] ,Message Identifier 24" "29-bit ID,11-bit ID" bitfld.long 0x00 23. " ID[23] ,Message Identifier 23" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 22. " ID[22] ,Message Identifier 22" "29-bit ID,11-bit ID" bitfld.long 0x00 21. " ID[21] ,Message Identifier 21" "29-bit ID,11-bit ID" bitfld.long 0x00 20. " ID[20] ,Message Identifier 20" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 19. " ID[19] ,Message Identifier 19" "29-bit ID,11-bit ID" bitfld.long 0x00 18. " ID[18] ,Message Identifier 18" "29-bit ID,11-bit ID" bitfld.long 0x00 17. " ID[17] ,Message Identifier 17" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 16. " ID[16] ,Message Identifier 16" "29-bit ID,11-bit ID" bitfld.long 0x00 15. " ID[15] ,Message Identifier 15" "29-bit ID,11-bit ID" bitfld.long 0x00 14. " ID[14] ,Message Identifier 14" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 13. " ID[13] ,Message Identifier 13" "29-bit ID,11-bit ID" bitfld.long 0x00 12. " ID[12] ,Message Identifier 12" "29-bit ID,11-bit ID" bitfld.long 0x00 11. " ID[11] ,Message Identifier 11" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 10. " ID[10] ,Message Identifier 10" "29-bit ID,11-bit ID" bitfld.long 0x00 9. " ID[9] ,Message Identifier 9" "29-bit ID,11-bit ID" bitfld.long 0x00 8. " ID[8] ,Message Identifier 8" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 7. " ID[7] ,Message Identifier 7" "29-bit ID,11-bit ID" bitfld.long 0x00 6. " ID[6] ,Message Identifier 6" "29-bit ID,11-bit ID" bitfld.long 0x00 5. " ID[5] ,Message Identifier 5" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 4. " ID[4] ,Message Identifier 4" "29-bit ID,11-bit ID" bitfld.long 0x00 3. " ID[3] ,Message Identifier 3" "29-bit ID,11-bit ID" bitfld.long 0x00 2. " ID[2] ,Message Identifier 2" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 1. " ID[1] ,Message Identifier 1" "29-bit ID,11-bit ID" bitfld.long 0x00 0. " ID[0] ,Message Identifier 0" "29-bit ID,11-bit ID" group.long 0x14C++0x3 line.long 0x0 "IF3MCTL,If3 Message Control Register" bitfld.long 0x00 15. " NEWDAT ,New Data" "Not written,Wrote" bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not losted,Losted" bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "Not pended,Pended" textline " " bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Not used,Used" bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Disabled,Enabled" bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested" bitfld.long 0x00 7. " EOB ,Data Frame 0-8 bits" "0,1" textline " " bitfld.long 0x00 0.--3. " DLC[3:0] ,Data length code" "0-8 data bits,0-8 data bits,0-8 data bits,0-8 data bits,0-8 data bits,0-8 data bits,0-8 data bits,0-8 data bits,0-8 data bits,8 data bytes,8 data bytes,8 data bytes,8 data bytes,8 data bytes,8 data bytes,8 data bytes" group.long 0x150++0x3 line.long 0x0 "IF3DATA,If3 Data A Register" hexmask.long.byte 0x00 24.--31. 1. " DATA_3 ,Data 3" hexmask.long.byte 0x00 16.--23. 1. " DATA_2 ,Data 2" textline " " hexmask.long.byte 0x00 8.--15. 1. " DATA_1 ,Data 1" hexmask.long.byte 0x00 0.--7. 1. " DATA_0 ,Data 0" group.long 0x154++0x3 line.long 0x0 "IF3DATB,If3 Data B Register" hexmask.long.byte 0x00 24.--31. 1. " DATA_7 ,Data 7" hexmask.long.byte 0x00 16.--23. 1. " DATA_6 ,Data 6" textline " " hexmask.long.byte 0x00 8.--15. 1. " DATA_5 ,Data 5" hexmask.long.byte 0x00 0.--7. 1. " DATA_4 ,Data 4" group.long 0x160++0x3 line.long 0x0 "IF3UPD12,Update enable 1-2 Register" bitfld.long 0x00 31. " IF3UPDATEEN[32] ,IF3 Update Enabled Bit[32]" "Disabled,Enabled" bitfld.long 0x00 30. " IF3UPDATEEN[31] ,IF3 Update Enabled Bit[31]" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " IF3UPDATEEN[30] ,IF3 Update Enabled Bit[30]" "Disabled,Enabled" bitfld.long 0x00 28. " IF3UPDATEEN[29] ,IF3 Update Enabled Bit[29]" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " IF3UPDATEEN[28] ,IF3 Update Enabled Bit[28]" "Disabled,Enabled" bitfld.long 0x00 26. " IF3UPDATEEN[27] ,IF3 Update Enabled Bit[27]" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " IF3UPDATEEN[26] ,IF3 Update Enabled Bit[26]" "Disabled,Enabled" bitfld.long 0x00 24. " IF3UPDATEEN[25] ,IF3 Update Enabled Bit[25]" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " IF3UPDATEEN[24] ,IF3 Update Enabled Bit[24]" "Disabled,Enabled" bitfld.long 0x00 22. " IF3UPDATEEN[23] ,IF3 Update Enabled Bit[23]" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " IF3UPDATEEN[22] ,IF3 Update Enabled Bit[22]" "Disabled,Enabled" bitfld.long 0x00 20. " IF3UPDATEEN[21] ,IF3 Update Enabled Bit[21]" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " IF3UPDATEEN[20] ,IF3 Update Enabled Bit[20]" "Disabled,Enabled" bitfld.long 0x00 18. " IF3UPDATEEN[19] ,IF3 Update Enabled Bit[19]" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " IF3UPDATEEN[18] ,IF3 Update Enabled Bit[18]" "Disabled,Enabled" bitfld.long 0x00 16. " IF3UPDATEEN[17] ,IF3 Update Enabled Bit[17]" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " IF3UPDATEEN[16] ,IF3 Update Enabled Bit[16]" "Disabled,Enabled" bitfld.long 0x00 14. " IF3UPDATEEN[15] ,IF3 Update Enabled Bit[15]" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " IF3UPDATEEN[14] ,IF3 Update Enabled Bit[14]" "Disabled,Enabled" bitfld.long 0x00 12. " IF3UPDATEEN[13] ,IF3 Update Enabled Bit[13]" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " IF3UPDATEEN[12] ,IF3 Update Enabled Bit[12]" "Disabled,Enabled" bitfld.long 0x00 10. " IF3UPDATEEN[11] ,IF3 Update Enabled Bit[11]" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " IF3UPDATEEN[10] ,IF3 Update Enabled Bit[10]" "Disabled,Enabled" bitfld.long 0x00 8. " IF3UPDATEEN[9] ,IF3 Update Enabled Bit[9]" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " IF3UPDATEEN[8] ,IF3 Update Enabled Bit[8]" "Disabled,Enabled" bitfld.long 0x00 6. " IF3UPDATEEN[7] ,IF3 Update Enabled Bit[7]" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " IF3UPDATEEN[6] ,IF3 Update Enabled Bit[6]" "Disabled,Enabled" bitfld.long 0x00 4. " IF3UPDATEEN[5] ,IF3 Update Enabled Bit[5]" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " IF3UPDATEEN[4] ,IF3 Update Enabled Bit[4]" "Disabled,Enabled" bitfld.long 0x00 2. " IF3UPDATEEN[3] ,IF3 Update Enabled Bit[3]" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " IF3UPDATEEN[2] ,IF3 Update Enabled Bit[2]" "Disabled,Enabled" bitfld.long 0x00 0. " IF3UPDATEEN[1] ,IF3 Update Enabled Bit[1]" "Disabled,Enabled" group.long 0x164++0x3 line.long 0x0 "IF3UPD34,Update enable 3-4 Register" bitfld.long 0x00 31. " IF3UPDATEEN[64] ,IF3 Update Enabled Bit[64]" "Disabled,Enabled" bitfld.long 0x00 30. " IF3UPDATEEN[63] ,IF3 Update Enabled Bit[63]" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " IF3UPDATEEN[62] ,IF3 Update Enabled Bit[62]" "Disabled,Enabled" bitfld.long 0x00 28. " IF3UPDATEEN[61] ,IF3 Update Enabled Bit[61]" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " IF3UPDATEEN[60] ,IF3 Update Enabled Bit[60]" "Disabled,Enabled" bitfld.long 0x00 26. " IF3UPDATEEN[59] ,IF3 Update Enabled Bit[59]" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " IF3UPDATEEN[58] ,IF3 Update Enabled Bit[58]" "Disabled,Enabled" bitfld.long 0x00 24. " IF3UPDATEEN[57] ,IF3 Update Enabled Bit[57]" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " IF3UPDATEEN[56] ,IF3 Update Enabled Bit[56]" "Disabled,Enabled" bitfld.long 0x00 22. " IF3UPDATEEN[55] ,IF3 Update Enabled Bit[55]" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " IF3UPDATEEN[54] ,IF3 Update Enabled Bit[54]" "Disabled,Enabled" bitfld.long 0x00 20. " IF3UPDATEEN[53] ,IF3 Update Enabled Bit[53]" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " IF3UPDATEEN[52] ,IF3 Update Enabled Bit[52]" "Disabled,Enabled" bitfld.long 0x00 18. " IF3UPDATEEN[51] ,IF3 Update Enabled Bit[51]" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " IF3UPDATEEN[50] ,IF3 Update Enabled Bit[50]" "Disabled,Enabled" bitfld.long 0x00 16. " IF3UPDATEEN[49] ,IF3 Update Enabled Bit[49]" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " IF3UPDATEEN[48] ,IF3 Update Enabled Bit[48]" "Disabled,Enabled" bitfld.long 0x00 14. " IF3UPDATEEN[47] ,IF3 Update Enabled Bit[47]" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " IF3UPDATEEN[46] ,IF3 Update Enabled Bit[46]" "Disabled,Enabled" bitfld.long 0x00 12. " IF3UPDATEEN[45] ,IF3 Update Enabled Bit[45]" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " IF3UPDATEEN[44] ,IF3 Update Enabled Bit[44]" "Disabled,Enabled" bitfld.long 0x00 10. " IF3UPDATEEN[43] ,IF3 Update Enabled Bit[43]" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " IF3UPDATEEN[42] ,IF3 Update Enabled Bit[42]" "Disabled,Enabled" bitfld.long 0x00 8. " IF3UPDATEEN[41] ,IF3 Update Enabled Bit[41]" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " IF3UPDATEEN[40] ,IF3 Update Enabled Bit[40]" "Disabled,Enabled" bitfld.long 0x00 6. " IF3UPDATEEN[39] ,IF3 Update Enabled Bit[39]" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " IF3UPDATEEN[38] ,IF3 Update Enabled Bit[38]" "Disabled,Enabled" bitfld.long 0x00 4. " IF3UPDATEEN[37] ,IF3 Update Enabled Bit[37]" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " IF3UPDATEEN[36] ,IF3 Update Enabled Bit[36]" "Disabled,Enabled" bitfld.long 0x00 2. " IF3UPDATEEN[35] ,IF3 Update Enabled Bit[35]" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " IF3UPDATEEN[34] ,IF3 Update Enabled Bit[34]" "Disabled,Enabled" bitfld.long 0x00 0. " IF3UPDATEEN[33] ,IF3 Update Enabled Bit[33]" "Disabled,Enabled" group.long 0x168++0x3 line.long 0x0 "IF3UPD56,Update enable 5-6 Register" bitfld.long 0x00 31. " IF3UPDATEEN[96] ,IF3 Update Enabled Bit[96]" "Disabled,Enabled" bitfld.long 0x00 30. " IF3UPDATEEN[95] ,IF3 Update Enabled Bit[95]" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " IF3UPDATEEN[94] ,IF3 Update Enabled Bit[94]" "Disabled,Enabled" bitfld.long 0x00 28. " IF3UPDATEEN[93] ,IF3 Update Enabled Bit[93]" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " IF3UPDATEEN[92] ,IF3 Update Enabled Bit[92]" "Disabled,Enabled" bitfld.long 0x00 26. " IF3UPDATEEN[91] ,IF3 Update Enabled Bit[91]" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " IF3UPDATEEN[90] ,IF3 Update Enabled Bit[90]" "Disabled,Enabled" bitfld.long 0x00 24. " IF3UPDATEEN[89] ,IF3 Update Enabled Bit[89]" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " IF3UPDATEEN[88] ,IF3 Update Enabled Bit[88]" "Disabled,Enabled" bitfld.long 0x00 22. " IF3UPDATEEN[87] ,IF3 Update Enabled Bit[87]" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " IF3UPDATEEN[86] ,IF3 Update Enabled Bit[86]" "Disabled,Enabled" bitfld.long 0x00 20. " IF3UPDATEEN[85] ,IF3 Update Enabled Bit[85]" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " IF3UPDATEEN[84] ,IF3 Update Enabled Bit[84]" "Disabled,Enabled" bitfld.long 0x00 18. " IF3UPDATEEN[83] ,IF3 Update Enabled Bit[83]" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " IF3UPDATEEN[82] ,IF3 Update Enabled Bit[82]" "Disabled,Enabled" bitfld.long 0x00 16. " IF3UPDATEEN[81] ,IF3 Update Enabled Bit[81]" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " IF3UPDATEEN[80] ,IF3 Update Enabled Bit[80]" "Disabled,Enabled" bitfld.long 0x00 14. " IF3UPDATEEN[79] ,IF3 Update Enabled Bit[79]" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " IF3UPDATEEN[78] ,IF3 Update Enabled Bit[78]" "Disabled,Enabled" bitfld.long 0x00 12. " IF3UPDATEEN[77] ,IF3 Update Enabled Bit[77]" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " IF3UPDATEEN[76] ,IF3 Update Enabled Bit[76]" "Disabled,Enabled" bitfld.long 0x00 10. " IF3UPDATEEN[75] ,IF3 Update Enabled Bit[75]" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " IF3UPDATEEN[74] ,IF3 Update Enabled Bit[74]" "Disabled,Enabled" bitfld.long 0x00 8. " IF3UPDATEEN[73] ,IF3 Update Enabled Bit[73]" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " IF3UPDATEEN[72] ,IF3 Update Enabled Bit[72]" "Disabled,Enabled" bitfld.long 0x00 6. " IF3UPDATEEN[71] ,IF3 Update Enabled Bit[71]" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " IF3UPDATEEN[70] ,IF3 Update Enabled Bit[70]" "Disabled,Enabled" bitfld.long 0x00 4. " IF3UPDATEEN[69] ,IF3 Update Enabled Bit[69]" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " IF3UPDATEEN[68] ,IF3 Update Enabled Bit[68]" "Disabled,Enabled" bitfld.long 0x00 2. " IF3UPDATEEN[67] ,IF3 Update Enabled Bit[67]" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " IF3UPDATEEN[66] ,IF3 Update Enabled Bit[66]" "Disabled,Enabled" bitfld.long 0x00 0. " IF3UPDATEEN[65] ,IF3 Update Enabled Bit[65]" "Disabled,Enabled" group.long 0x16C++0x3 line.long 0x0 "IF3UPD78,Update enable 7-8 Register" bitfld.long 0x00 31. " IF3UPDATEEN[128] ,IF3 Update Enabled Bit[128]" "Disabled,Enabled" bitfld.long 0x00 30. " IF3UPDATEEN[127] ,IF3 Update Enabled Bit[127]" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " IF3UPDATEEN[126] ,IF3 Update Enabled Bit[126]" "Disabled,Enabled" bitfld.long 0x00 28. " IF3UPDATEEN[125] ,IF3 Update Enabled Bit[125]" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " IF3UPDATEEN[124] ,IF3 Update Enabled Bit[124]" "Disabled,Enabled" bitfld.long 0x00 26. " IF3UPDATEEN[123] ,IF3 Update Enabled Bit[123]" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " IF3UPDATEEN[122] ,IF3 Update Enabled Bit[122]" "Disabled,Enabled" bitfld.long 0x00 24. " IF3UPDATEEN[121] ,IF3 Update Enabled Bit[121]" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " IF3UPDATEEN[120] ,IF3 Update Enabled Bit[120]" "Disabled,Enabled" bitfld.long 0x00 22. " IF3UPDATEEN[119] ,IF3 Update Enabled Bit[119]" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " IF3UPDATEEN[118] ,IF3 Update Enabled Bit[118]" "Disabled,Enabled" bitfld.long 0x00 20. " IF3UPDATEEN[117] ,IF3 Update Enabled Bit[117]" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " IF3UPDATEEN[116] ,IF3 Update Enabled Bit[116]" "Disabled,Enabled" bitfld.long 0x00 18. " IF3UPDATEEN[115] ,IF3 Update Enabled Bit[115]" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " IF3UPDATEEN[114] ,IF3 Update Enabled Bit[114]" "Disabled,Enabled" bitfld.long 0x00 16. " IF3UPDATEEN[113] ,IF3 Update Enabled Bit[113]" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " IF3UPDATEEN[112] ,IF3 Update Enabled Bit[112]" "Disabled,Enabled" bitfld.long 0x00 14. " IF3UPDATEEN[111] ,IF3 Update Enabled Bit[111]" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " IF3UPDATEEN[110] ,IF3 Update Enabled Bit[110]" "Disabled,Enabled" bitfld.long 0x00 12. " IF3UPDATEEN[109] ,IF3 Update Enabled Bit[109]" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " IF3UPDATEEN[108] ,IF3 Update Enabled Bit[108]" "Disabled,Enabled" bitfld.long 0x00 10. " IF3UPDATEEN[107] ,IF3 Update Enabled Bit[107]" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " IF3UPDATEEN[106] ,IF3 Update Enabled Bit[106]" "Disabled,Enabled" bitfld.long 0x00 8. " IF3UPDATEEN[105] ,IF3 Update Enabled Bit[105]" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " IF3UPDATEEN[104] ,IF3 Update Enabled Bit[104]" "Disabled,Enabled" bitfld.long 0x00 6. " IF3UPDATEEN[103] ,IF3 Update Enabled Bit[103]" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " IF3UPDATEEN[102] ,IF3 Update Enabled Bit[102]" "Disabled,Enabled" bitfld.long 0x00 4. " IF3UPDATEEN[101] ,IF3 Update Enabled Bit[101]" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " IF3UPDATEEN[100] ,IF3 Update Enabled Bit[100]" "Disabled,Enabled" bitfld.long 0x00 2. " IF3UPDATEEN[99] ,IF3 Update Enabled Bit[99]" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " IF3UPDATEEN[98] ,IF3 Update Enabled Bit[98]" "Disabled,Enabled" bitfld.long 0x00 0. " IF3UPDATEEN[97] ,IF3 Update Enabled Bit[97]" "Disabled,Enabled" tree.end width 6. group.long 0x1E0++0x3 line.long 0x0 "TIOC,TX IO Control Register" bitfld.long 0x00 18. " PU ,CAN_TX Pullup/Pulldown select" "Pulldown,Pullup" bitfld.long 0x00 17. " PD ,CAN_TX pull disable" "Active,Disabled" bitfld.long 0x00 16. " OD ,CAN_TX open drain enable" "Push/pull,Open drain" textline " " bitfld.long 0x00 3. " FUNC ,CAN_TX function" "GIO,Functional" bitfld.long 0x00 2. " DIR ,CAN_TX data direction" "Input,Output" bitfld.long 0x00 1. " OUT ,CAN_TX data out write" "Low,High" textline " " bitfld.long 0x00 0. " IN ,CAN_TX data in" "Low,High" group.long 0x1E4++0x3 line.long 0x0 "RIOC,RX IO Control Register" bitfld.long 0x00 18. " PU ,CAN_TX Pullup/Pulldown select" "Pulldown,Pullup" bitfld.long 0x00 17. " PD ,CAN_TX pull disable" "Active,Disabled" bitfld.long 0x00 16. " OD ,CAN_TX open drain enable" "Push/pull,Open drain" textline " " bitfld.long 0x00 3. " FUNC ,CAN_TX function" "GIO,Functional" bitfld.long 0x00 2. " DIR ,CAN_TX data direction" "Input,Output" bitfld.long 0x00 1. " OUT ,CAN_TX data out write" "Low,High" textline " " bitfld.long 0x00 0. " IN ,CAN_TX data in" "Low,High" width 11. tree.end sif (cpu()!="RM42L432") tree "DCAN3" base ad:0xFFF7E000 width 12. group.long 0x00++0x3 line.long 0x0 "CTL,Control register" bitfld.long 0x00 25. " WUBA ,Automatic wake up on bus activity" "Not detected,Detected" bitfld.long 0x00 24. " PDR ,Request for local low power down mode" "Not requested,Requested" bitfld.long 0x00 20. " DE3 ,Enable DMA request line for IF3" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " DE2 ,Enable DMA request line for IF2" "Disabled,Enabled" bitfld.long 0x00 18. " DE1 ,Enable DMA request line for IF1" "Disabled,Enabled" bitfld.long 0x00 17. " IE1 ,Interrupt DCAN1INT line 1 Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " INITDBG ,Internal Init state while debug access" "Not initialized,Initialized" bitfld.long 0x00 15. " SWR ,SW Reset Enable" "Normal,Reset" bitfld.long 0x00 10.--13. " PMD ,Parity on/off" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" textline " " bitfld.long 0x00 9. " ABO ,Auto-Bus-On Enable" "Disabled,Enabled" bitfld.long 0x00 8. " IDS ,Interruption Debug Support Enable" "Disabled,Enabled" bitfld.long 0x00 7. " TEST ,Test Mode Enable" "Normal,Enabled" textline " " bitfld.long 0x00 6. " CCE ,Configuration Change Enable" "No WR access,WR Access" bitfld.long 0x00 5. " DAR ,Disable Automatic Retransmission" "Enabled,Disabled" bitfld.long 0x00 3. " EIE ,Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " SIE ,Status Change Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 1. " IE0 ,Interrupt DCAN0INT line 0 Enable" "Disabled,Enabled" bitfld.long 0x00 0. " INIT ,Initialization mode" "Disabled,Enabled" hgroup.long 0x04++0x3 hide.long 0x0 "ES,Error and Status Register" in rgroup.long 0x08++0x3 line.long 0x0 "ERRC,Error Counter Register" bitfld.long 0x00 15. " RP ,Receive Error Passive" "Below,Reached" hexmask.long.byte 0x00 8.--14. 1. " REC ,Receive Error Counter" hexmask.long.byte 0x00 0.--7. 1. " TEC ,Transmit Error Counter" group.long 0x0C++0x3 line.long 0x0 "BTR,Bit Timing_BRP Extension Register" bitfld.long 0x00 16.--19. " BRPE ,Baud Rate Prescaler Extension" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--14. " TSEG2 ,Time segment after the sample point" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--11. " TSEG1 ,Time segment before the sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 6.--7. " SJW ,Synchronization Jump Width" "0,1,2,3" bitfld.long 0x00 0.--5. " BRP ,Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x10++0x3 line.long 0x0 "INT,Interrupt Register" hexmask.long.byte 0x00 16.--23. 1. " INT1ID ,Interrupt 1 Identifier" hexmask.long.word 0x00 0.--15. 1. " INT0ID ,Interrupt Identifier" group.long 0x14++0x3 line.long 0x0 "TEST,Test Register" bitfld.long 0x00 9. " RDA ,RAM Direct Access Enable" "Disabled,Enabled" bitfld.long 0x00 8. " EXL ,External Loop Back Mode" "Disabled,Enabled" bitfld.long 0x00 7. " RX ,Receive Pin" "Bus is dominant,Bus is recessive" textline " " bitfld.long 0x00 5.--6. " TX ,Control of CAN_TX pin" "Normal operation,Monitored,Dominant value,Recessive value" bitfld.long 0x00 4. " LBACK ,Loop Back Mode" "Disabled,Enabled" bitfld.long 0x00 3. " SILENT ,Silent Mode" "Disabled,Enabled" rgroup.long 0x1C++0x3 line.long 0x0 "PARERR,Parity Error Code Register" bitfld.long 0x00 8.--10. " WORD_NUMBER ,Word number where parity error has been detected" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Message object number where parity error has been detected" group.long 0x80++0x3 line.long 0x0 "ABOTR,Auto Bus On Time" group.long 0x84++0x3 line.long 0x0 "TRREQX,Transmission Request X" bitfld.long 0x00 14.--15. " TXRQSTREG8 ,Transmission Request 8 Register" "0,1,2,3" bitfld.long 0x00 12.--13. " TXRQSTREG7 ,Transmission Request 7 Register" "0,1,2,3" bitfld.long 0x00 10.--11. " TXRQSTREG6 ,Transmission Request 6 Register" "0,1,2,3" textline " " bitfld.long 0x00 8.--9. " TXRQSTREG5 ,Transmission Request 5 Register" "0,1,2,3" bitfld.long 0x00 6.--7. " TXRQSTREG4 ,Transmission Request 4 Register" "0,1,2,3" bitfld.long 0x00 4.--5. " TXRQSTREG3 ,Transmission Request 3 Register" "0,1,2,3" textline " " bitfld.long 0x00 2.--3. " TXRQSTREG2 ,Transmission Request 2 Register" "0,1,2,3" bitfld.long 0x00 0.--1. " TXRQSTREG1 ,Transmission Request 1 Register" "0,1,2,3" rgroup.long 0x88++0x3 line.long 0x0 "TRREQ12,Transmission Request 1 2 Register" bitfld.long 0x00 31. " TXRQST[32] ,Transmission Request Bits[32]" "Not requested,Requested" bitfld.long 0x00 30. " TXRQST[31] ,Transmission Request Bits[31]" "Not requested,Requested" textline " " bitfld.long 0x00 29. " TXRQST[30] ,Transmission Request Bits[30]" "Not requested,Requested" bitfld.long 0x00 28. " TXRQST[29] ,Transmission Request Bits[29]" "Not requested,Requested" textline " " bitfld.long 0x00 27. " TXRQST[28] ,Transmission Request Bits[28]" "Not requested,Requested" bitfld.long 0x00 26. " TXRQST[27] ,Transmission Request Bits[27]" "Not requested,Requested" textline " " bitfld.long 0x00 25. " TXRQST[26] ,Transmission Request Bits[26]" "Not requested,Requested" bitfld.long 0x00 24. " TXRQST[25] ,Transmission Request Bits[25]" "Not requested,Requested" textline " " bitfld.long 0x00 23. " TXRQST[24] ,Transmission Request Bits[24]" "Not requested,Requested" bitfld.long 0x00 22. " TXRQST[23] ,Transmission Request Bits[23]" "Not requested,Requested" textline " " bitfld.long 0x00 21. " TXRQST[22] ,Transmission Request Bits[22]" "Not requested,Requested" bitfld.long 0x00 20. " TXRQST[21] ,Transmission Request Bits[21]" "Not requested,Requested" textline " " bitfld.long 0x00 19. " TXRQST[20] ,Transmission Request Bits[20]" "Not requested,Requested" bitfld.long 0x00 18. " TXRQST[19] ,Transmission Request Bits[19]" "Not requested,Requested" textline " " bitfld.long 0x00 17. " TXRQST[18] ,Transmission Request Bits[18]" "Not requested,Requested" bitfld.long 0x00 16. " TXRQST[17] ,Transmission Request Bits[17]" "Not requested,Requested" textline " " bitfld.long 0x00 15. " TXRQST[16] ,Transmission Request Bits[16]" "Not requested,Requested" bitfld.long 0x00 14. " TXRQST[15] ,Transmission Request Bits[15]" "Not requested,Requested" textline " " bitfld.long 0x00 13. " TXRQST[14] ,Transmission Request Bits[14]" "Not requested,Requested" bitfld.long 0x00 12. " TXRQST[13] ,Transmission Request Bits[13]" "Not requested,Requested" textline " " bitfld.long 0x00 11. " TXRQST[12] ,Transmission Request Bits[12]" "Not requested,Requested" bitfld.long 0x00 10. " TXRQST[11] ,Transmission Request Bits[11]" "Not requested,Requested" textline " " bitfld.long 0x00 9. " TXRQST[10] ,Transmission Request Bits[10]" "Not requested,Requested" bitfld.long 0x00 8. " TXRQST[9] ,Transmission Request Bits[9]" "Not requested,Requested" textline " " bitfld.long 0x00 7. " TXRQST[8] ,Transmission Request Bits[8]" "Not requested,Requested" bitfld.long 0x00 6. " TXRQST[7] ,Transmission Request Bits[7]" "Not requested,Requested" textline " " bitfld.long 0x00 5. " TXRQST[6] ,Transmission Request Bits[6]" "Not requested,Requested" bitfld.long 0x00 4. " TXRQST[5] ,Transmission Request Bits[5]" "Not requested,Requested" textline " " bitfld.long 0x00 3. " TXRQST[4] ,Transmission Request Bits[4]" "Not requested,Requested" bitfld.long 0x00 2. " TXRQST[3] ,Transmission Request Bits[3]" "Not requested,Requested" textline " " bitfld.long 0x00 1. " TXRQST[2] ,Transmission Request Bits[2]" "Not requested,Requested" bitfld.long 0x00 0. " TXRQST[1] ,Transmission Request Bits[1]" "Not requested,Requested" rgroup.long 0x8C++0x3 line.long 0x0 "TRREQ34,Transmission Request 3-4" bitfld.long 0x00 31. " TXRQST[64] ,Transmission Request Bits[64]" "Not requested,Requested" bitfld.long 0x00 30. " TXRQST[63] ,Transmission Request Bits[63]" "Not requested,Requested" textline " " bitfld.long 0x00 29. " TXRQST[62] ,Transmission Request Bits[62]" "Not requested,Requested" bitfld.long 0x00 28. " TXRQST[61] ,Transmission Request Bits[61]" "Not requested,Requested" textline " " bitfld.long 0x00 27. " TXRQST[60] ,Transmission Request Bits[60]" "Not requested,Requested" bitfld.long 0x00 26. " TXRQST[59] ,Transmission Request Bits[59]" "Not requested,Requested" textline " " bitfld.long 0x00 25. " TXRQST[58] ,Transmission Request Bits[58]" "Not requested,Requested" bitfld.long 0x00 24. " TXRQST[57] ,Transmission Request Bits[57]" "Not requested,Requested" textline " " bitfld.long 0x00 23. " TXRQST[56] ,Transmission Request Bits[56]" "Not requested,Requested" bitfld.long 0x00 22. " TXRQST[55] ,Transmission Request Bits[55]" "Not requested,Requested" textline " " bitfld.long 0x00 21. " TXRQST[54] ,Transmission Request Bits[54]" "Not requested,Requested" bitfld.long 0x00 20. " TXRQST[53] ,Transmission Request Bits[53]" "Not requested,Requested" textline " " bitfld.long 0x00 19. " TXRQST[52] ,Transmission Request Bits[52]" "Not requested,Requested" bitfld.long 0x00 18. " TXRQST[51] ,Transmission Request Bits[51]" "Not requested,Requested" textline " " bitfld.long 0x00 17. " TXRQST[50] ,Transmission Request Bits[50]" "Not requested,Requested" bitfld.long 0x00 16. " TXRQST[49] ,Transmission Request Bits[49]" "Not requested,Requested" textline " " bitfld.long 0x00 15. " TXRQST[48] ,Transmission Request Bits[48]" "Not requested,Requested" bitfld.long 0x00 14. " TXRQST[47] ,Transmission Request Bits[47]" "Not requested,Requested" textline " " bitfld.long 0x00 13. " TXRQST[46] ,Transmission Request Bits[46]" "Not requested,Requested" bitfld.long 0x00 12. " TXRQST[45] ,Transmission Request Bits[45]" "Not requested,Requested" textline " " bitfld.long 0x00 11. " TXRQST[44] ,Transmission Request Bits[44]" "Not requested,Requested" bitfld.long 0x00 10. " TXRQST[43] ,Transmission Request Bits[43]" "Not requested,Requested" textline " " bitfld.long 0x00 9. " TXRQST[42] ,Transmission Request Bits[42]" "Not requested,Requested" bitfld.long 0x00 8. " TXRQST[41] ,Transmission Request Bits[41]" "Not requested,Requested" textline " " bitfld.long 0x00 7. " TXRQST[40] ,Transmission Request Bits[40]" "Not requested,Requested" bitfld.long 0x00 6. " TXRQST[39] ,Transmission Request Bits[39]" "Not requested,Requested" textline " " bitfld.long 0x00 5. " TXRQST[38] ,Transmission Request Bits[38]" "Not requested,Requested" bitfld.long 0x00 4. " TXRQST[37] ,Transmission Request Bits[37]" "Not requested,Requested" textline " " bitfld.long 0x00 3. " TXRQST[36] ,Transmission Request Bits[36]" "Not requested,Requested" bitfld.long 0x00 2. " TXRQST[35] ,Transmission Request Bits[35]" "Not requested,Requested" textline " " bitfld.long 0x00 1. " TXRQST[34] ,Transmission Request Bits[34]" "Not requested,Requested" bitfld.long 0x00 0. " TXRQST[33] ,Transmission Request Bits[33]" "Not requested,Requested" rgroup.long 0x90++0x3 line.long 0x0 "TRREQ56,Transmission Request 5-6" bitfld.long 0x00 31. " TXRQST[96] ,Transmission Request Bits[96]" "Not requested,Requested" bitfld.long 0x00 30. " TXRQST[95] ,Transmission Request Bits[95]" "Not requested,Requested" textline " " bitfld.long 0x00 29. " TXRQST[94] ,Transmission Request Bits[94]" "Not requested,Requested" bitfld.long 0x00 28. " TXRQST[93] ,Transmission Request Bits[93]" "Not requested,Requested" textline " " bitfld.long 0x00 27. " TXRQST[92] ,Transmission Request Bits[92]" "Not requested,Requested" bitfld.long 0x00 26. " TXRQST[91] ,Transmission Request Bits[91]" "Not requested,Requested" textline " " bitfld.long 0x00 25. " TXRQST[90] ,Transmission Request Bits[90]" "Not requested,Requested" bitfld.long 0x00 24. " TXRQST[89] ,Transmission Request Bits[89]" "Not requested,Requested" textline " " bitfld.long 0x00 23. " TXRQST[88] ,Transmission Request Bits[88]" "Not requested,Requested" bitfld.long 0x00 22. " TXRQST[87] ,Transmission Request Bits[87]" "Not requested,Requested" textline " " bitfld.long 0x00 21. " TXRQST[86] ,Transmission Request Bits[86]" "Not requested,Requested" bitfld.long 0x00 20. " TXRQST[85] ,Transmission Request Bits[85]" "Not requested,Requested" textline " " bitfld.long 0x00 19. " TXRQST[84] ,Transmission Request Bits[84]" "Not requested,Requested" bitfld.long 0x00 18. " TXRQST[83] ,Transmission Request Bits[83]" "Not requested,Requested" textline " " bitfld.long 0x00 17. " TXRQST[82] ,Transmission Request Bits[82]" "Not requested,Requested" bitfld.long 0x00 16. " TXRQST[81] ,Transmission Request Bits[81]" "Not requested,Requested" textline " " bitfld.long 0x00 15. " TXRQST[80] ,Transmission Request Bits[80]" "Not requested,Requested" bitfld.long 0x00 14. " TXRQST[79] ,Transmission Request Bits[79]" "Not requested,Requested" textline " " bitfld.long 0x00 13. " TXRQST[78] ,Transmission Request Bits[78]" "Not requested,Requested" bitfld.long 0x00 12. " TXRQST[77] ,Transmission Request Bits[77]" "Not requested,Requested" textline " " bitfld.long 0x00 11. " TXRQST[76] ,Transmission Request Bits[76]" "Not requested,Requested" bitfld.long 0x00 10. " TXRQST[75] ,Transmission Request Bits[75]" "Not requested,Requested" textline " " bitfld.long 0x00 9. " TXRQST[74] ,Transmission Request Bits[74]" "Not requested,Requested" bitfld.long 0x00 8. " TXRQST[73] ,Transmission Request Bits[73]" "Not requested,Requested" textline " " bitfld.long 0x00 7. " TXRQST[72] ,Transmission Request Bits[72]" "Not requested,Requested" bitfld.long 0x00 6. " TXRQST[71] ,Transmission Request Bits[71]" "Not requested,Requested" textline " " bitfld.long 0x00 5. " TXRQST[70] ,Transmission Request Bits[70]" "Not requested,Requested" bitfld.long 0x00 4. " TXRQST[69] ,Transmission Request Bits[69]" "Not requested,Requested" textline " " bitfld.long 0x00 3. " TXRQST[68] ,Transmission Request Bits[68]" "Not requested,Requested" bitfld.long 0x00 2. " TXRQST[67] ,Transmission Request Bits[67]" "Not requested,Requested" textline " " bitfld.long 0x00 1. " TXRQST[66] ,Transmission Request Bits[66]" "Not requested,Requested" bitfld.long 0x00 0. " TXRQST[65] ,Transmission Request Bits[65]" "Not requested,Requested" rgroup.long 0x94++0x3 line.long 0x0 "TRREQ78,Transmission Request 7-8" bitfld.long 0x00 31. " TXRQST[128] ,Transmission Request Bits[128]" "Not requested,Requested" bitfld.long 0x00 30. " TXRQST[127] ,Transmission Request Bits[127]" "Not requested,Requested" textline " " bitfld.long 0x00 29. " TXRQST[126] ,Transmission Request Bits[126]" "Not requested,Requested" bitfld.long 0x00 28. " TXRQST[125] ,Transmission Request Bits[125]" "Not requested,Requested" textline " " bitfld.long 0x00 27. " TXRQST[124] ,Transmission Request Bits[124]" "Not requested,Requested" bitfld.long 0x00 26. " TXRQST[123] ,Transmission Request Bits[123]" "Not requested,Requested" textline " " bitfld.long 0x00 25. " TXRQST[122] ,Transmission Request Bits[122]" "Not requested,Requested" bitfld.long 0x00 24. " TXRQST[121] ,Transmission Request Bits[121]" "Not requested,Requested" textline " " bitfld.long 0x00 23. " TXRQST[120] ,Transmission Request Bits[120]" "Not requested,Requested" bitfld.long 0x00 22. " TXRQST[119] ,Transmission Request Bits[119]" "Not requested,Requested" textline " " bitfld.long 0x00 21. " TXRQST[118] ,Transmission Request Bits[118]" "Not requested,Requested" bitfld.long 0x00 20. " TXRQST[117] ,Transmission Request Bits[117]" "Not requested,Requested" textline " " bitfld.long 0x00 19. " TXRQST[116] ,Transmission Request Bits[116]" "Not requested,Requested" bitfld.long 0x00 18. " TXRQST[115] ,Transmission Request Bits[115]" "Not requested,Requested" textline " " bitfld.long 0x00 17. " TXRQST[114] ,Transmission Request Bits[114]" "Not requested,Requested" bitfld.long 0x00 16. " TXRQST[113] ,Transmission Request Bits[113]" "Not requested,Requested" textline " " bitfld.long 0x00 15. " TXRQST[112] ,Transmission Request Bits[112]" "Not requested,Requested" bitfld.long 0x00 14. " TXRQST[111] ,Transmission Request Bits[111]" "Not requested,Requested" textline " " bitfld.long 0x00 13. " TXRQST[110] ,Transmission Request Bits[110]" "Not requested,Requested" bitfld.long 0x00 12. " TXRQST[109] ,Transmission Request Bits[109]" "Not requested,Requested" textline " " bitfld.long 0x00 11. " TXRQST[108] ,Transmission Request Bits[108]" "Not requested,Requested" bitfld.long 0x00 10. " TXRQST[107] ,Transmission Request Bits[107]" "Not requested,Requested" textline " " bitfld.long 0x00 9. " TXRQST[106] ,Transmission Request Bits[106]" "Not requested,Requested" bitfld.long 0x00 8. " TXRQST[105] ,Transmission Request Bits[105]" "Not requested,Requested" textline " " bitfld.long 0x00 7. " TXRQST[104] ,Transmission Request Bits[104]" "Not requested,Requested" bitfld.long 0x00 6. " TXRQST[103] ,Transmission Request Bits[103]" "Not requested,Requested" textline " " bitfld.long 0x00 5. " TXRQST[102] ,Transmission Request Bits[102]" "Not requested,Requested" bitfld.long 0x00 4. " TXRQST[101] ,Transmission Request Bits[101]" "Not requested,Requested" textline " " bitfld.long 0x00 3. " TXRQST[100] ,Transmission Request Bits[100]" "Not requested,Requested" bitfld.long 0x00 2. " TXRQST[99] ,Transmission Request Bits[99]" "Not requested,Requested" textline " " bitfld.long 0x00 1. " TXRQST[98] ,Transmission Request Bits[98]" "Not requested,Requested" bitfld.long 0x00 0. " TXRQST[97] ,Transmission Request Bits[97]" "Not requested,Requested" rgroup.long 0x98++0x3 line.long 0x0 "NEWDATX,New Data X" bitfld.long 0x00 14.--15. " NEWDATREG8 ,New Data 8 Register" "0,1,2,3" bitfld.long 0x00 12.--13. " NEWDATREG7 ,New Data 7 Register" "0,1,2,3" bitfld.long 0x00 10.--11. " NEWDATREG6 ,New Data 6 Register" "0,1,2,3" textline " " bitfld.long 0x00 8.--9. " NEWDATREG5 ,New Data 5 Register" "0,1,2,3" bitfld.long 0x00 6.--7. " NEWDATREG4 ,New Data 4 Register" "0,1,2,3" bitfld.long 0x00 4.--5. " NEWDATREG3 ,New Data 3 Register" "0,1,2,3" textline " " bitfld.long 0x00 2.--3. " NEWDATREG2 ,New Data 2 Register" "0,1,2,3" bitfld.long 0x00 0.--1. " NEWDATREG1 ,New Data 1 Register" "0,1,2,3" rgroup.long 0x9C++0x3 line.long 0x0 "NEWDAT12,New Data 1-2" bitfld.long 0x00 31. " NEWDAT[32] ,New Data Bit[32]" "Not requested,Requested" bitfld.long 0x00 30. " NEWDAT[31] ,New Data Bit[31]" "Not requested,Requested" textline " " bitfld.long 0x00 29. " NEWDAT[30] ,New Data Bit[30]" "Not requested,Requested" bitfld.long 0x00 28. " NEWDAT[29] ,New Data Bit[29]" "Not requested,Requested" textline " " bitfld.long 0x00 27. " NEWDAT[28] ,New Data Bit[28]" "Not requested,Requested" bitfld.long 0x00 26. " NEWDAT[27] ,New Data Bit[27]" "Not requested,Requested" textline " " bitfld.long 0x00 25. " NEWDAT[26] ,New Data Bit[26]" "Not requested,Requested" bitfld.long 0x00 24. " NEWDAT[25] ,New Data Bit[25]" "Not requested,Requested" textline " " bitfld.long 0x00 23. " NEWDAT[24] ,New Data Bit[24]" "Not requested,Requested" bitfld.long 0x00 22. " NEWDAT[23] ,New Data Bit[23]" "Not requested,Requested" textline " " bitfld.long 0x00 21. " NEWDAT[22] ,New Data Bit[22]" "Not requested,Requested" bitfld.long 0x00 20. " NEWDAT[21] ,New Data Bit[21]" "Not requested,Requested" textline " " bitfld.long 0x00 19. " NEWDAT[20] ,New Data Bit[20]" "Not requested,Requested" bitfld.long 0x00 18. " NEWDAT[19] ,New Data Bit[19]" "Not requested,Requested" textline " " bitfld.long 0x00 17. " NEWDAT[18] ,New Data Bit[18]" "Not requested,Requested" bitfld.long 0x00 16. " NEWDAT[17] ,New Data Bit[17]" "Not requested,Requested" textline " " bitfld.long 0x00 15. " NEWDAT[16] ,New Data Bit[16]" "Not requested,Requested" bitfld.long 0x00 14. " NEWDAT[15] ,New Data Bit[15]" "Not requested,Requested" textline " " bitfld.long 0x00 13. " NEWDAT[14] ,New Data Bit[14]" "Not requested,Requested" bitfld.long 0x00 12. " NEWDAT[13] ,New Data Bit[13]" "Not requested,Requested" textline " " bitfld.long 0x00 11. " NEWDAT[12] ,New Data Bit[12]" "Not requested,Requested" bitfld.long 0x00 10. " NEWDAT[11] ,New Data Bit[11]" "Not requested,Requested" textline " " bitfld.long 0x00 9. " NEWDAT[10] ,New Data Bit[10]" "Not requested,Requested" bitfld.long 0x00 8. " NEWDAT[9] ,New Data Bit[9]" "Not requested,Requested" textline " " bitfld.long 0x00 7. " NEWDAT[8] ,New Data Bit[8]" "Not requested,Requested" bitfld.long 0x00 6. " NEWDAT[7] ,New Data Bit[7]" "Not requested,Requested" textline " " bitfld.long 0x00 5. " NEWDAT[6] ,New Data Bit[6]" "Not requested,Requested" bitfld.long 0x00 4. " NEWDAT[5] ,New Data Bit[5]" "Not requested,Requested" textline " " bitfld.long 0x00 3. " NEWDAT[4] ,New Data Bit[4]" "Not requested,Requested" bitfld.long 0x00 2. " NEWDAT[3] ,New Data Bit[3]" "Not requested,Requested" textline " " bitfld.long 0x00 1. " NEWDAT[2] ,New Data Bit[2]" "Not requested,Requested" bitfld.long 0x00 0. " NEWDAT[1] ,New Data Bit[1]" "Not requested,Requested" rgroup.long 0xA0++0x3 line.long 0x0 "NEWDAT34,New Data 3-4" bitfld.long 0x00 31. " NEWDAT[64] ,New Data Bit[64]" "Not requested,Requested" bitfld.long 0x00 30. " NEWDAT[63] ,New Data Bit[63]" "Not requested,Requested" textline " " bitfld.long 0x00 29. " NEWDAT[62] ,New Data Bit[62]" "Not requested,Requested" bitfld.long 0x00 28. " NEWDAT[61] ,New Data Bit[61]" "Not requested,Requested" textline " " bitfld.long 0x00 27. " NEWDAT[60] ,New Data Bit[60]" "Not requested,Requested" bitfld.long 0x00 26. " NEWDAT[59] ,New Data Bit[59]" "Not requested,Requested" textline " " bitfld.long 0x00 25. " NEWDAT[58] ,New Data Bit[58]" "Not requested,Requested" bitfld.long 0x00 24. " NEWDAT[57] ,New Data Bit[57]" "Not requested,Requested" textline " " bitfld.long 0x00 23. " NEWDAT[56] ,New Data Bit[56]" "Not requested,Requested" bitfld.long 0x00 22. " NEWDAT[55] ,New Data Bit[55]" "Not requested,Requested" textline " " bitfld.long 0x00 21. " NEWDAT[54] ,New Data Bit[54]" "Not requested,Requested" bitfld.long 0x00 20. " NEWDAT[53] ,New Data Bit[53]" "Not requested,Requested" textline " " bitfld.long 0x00 19. " NEWDAT[52] ,New Data Bit[52]" "Not requested,Requested" bitfld.long 0x00 18. " NEWDAT[51] ,New Data Bit[51]" "Not requested,Requested" textline " " bitfld.long 0x00 17. " NEWDAT[50] ,New Data Bit[50]" "Not requested,Requested" bitfld.long 0x00 16. " NEWDAT[49] ,New Data Bit[49]" "Not requested,Requested" textline " " bitfld.long 0x00 15. " NEWDAT[48] ,New Data Bit[48]" "Not requested,Requested" bitfld.long 0x00 14. " NEWDAT[47] ,New Data Bit[47]" "Not requested,Requested" textline " " bitfld.long 0x00 13. " NEWDAT[46] ,New Data Bit[46]" "Not requested,Requested" bitfld.long 0x00 12. " NEWDAT[45] ,New Data Bit[45]" "Not requested,Requested" textline " " bitfld.long 0x00 11. " NEWDAT[44] ,New Data Bit[44]" "Not requested,Requested" bitfld.long 0x00 10. " NEWDAT[43] ,New Data Bit[43]" "Not requested,Requested" textline " " bitfld.long 0x00 9. " NEWDAT[42] ,New Data Bit[42]" "Not requested,Requested" bitfld.long 0x00 8. " NEWDAT[41] ,New Data Bit[41]" "Not requested,Requested" textline " " bitfld.long 0x00 7. " NEWDAT[40] ,New Data Bit[40]" "Not requested,Requested" bitfld.long 0x00 6. " NEWDAT[39] ,New Data Bit[39]" "Not requested,Requested" textline " " bitfld.long 0x00 5. " NEWDAT[38] ,New Data Bit[38]" "Not requested,Requested" bitfld.long 0x00 4. " NEWDAT[37] ,New Data Bit[37]" "Not requested,Requested" textline " " bitfld.long 0x00 3. " NEWDAT[36] ,New Data Bit[36]" "Not requested,Requested" bitfld.long 0x00 2. " NEWDAT[35] ,New Data Bit[35]" "Not requested,Requested" textline " " bitfld.long 0x00 1. " NEWDAT[34] ,New Data Bit[34]" "Not requested,Requested" bitfld.long 0x00 0. " NEWDAT[33] ,New Data Bit[33]" "Not requested,Requested" rgroup.long 0xA4++0x3 line.long 0x0 "NEWDAT56,New Data 5-6" bitfld.long 0x00 31. " NEWDAT[96] ,New Data Bit[96]" "Not requested,Requested" bitfld.long 0x00 30. " NEWDAT[95] ,New Data Bit[95]" "Not requested,Requested" textline " " bitfld.long 0x00 29. " NEWDAT[94] ,New Data Bit[94]" "Not requested,Requested" bitfld.long 0x00 28. " NEWDAT[93] ,New Data Bit[93]" "Not requested,Requested" textline " " bitfld.long 0x00 27. " NEWDAT[92] ,New Data Bit[92]" "Not requested,Requested" bitfld.long 0x00 26. " NEWDAT[91] ,New Data Bit[91]" "Not requested,Requested" textline " " bitfld.long 0x00 25. " NEWDAT[90] ,New Data Bit[90]" "Not requested,Requested" bitfld.long 0x00 24. " NEWDAT[89] ,New Data Bit[89]" "Not requested,Requested" textline " " bitfld.long 0x00 23. " NEWDAT[88] ,New Data Bit[88]" "Not requested,Requested" bitfld.long 0x00 22. " NEWDAT[87] ,New Data Bit[87]" "Not requested,Requested" textline " " bitfld.long 0x00 21. " NEWDAT[86] ,New Data Bit[86]" "Not requested,Requested" bitfld.long 0x00 20. " NEWDAT[85] ,New Data Bit[85]" "Not requested,Requested" textline " " bitfld.long 0x00 19. " NEWDAT[84] ,New Data Bit[84]" "Not requested,Requested" bitfld.long 0x00 18. " NEWDAT[83] ,New Data Bit[83]" "Not requested,Requested" textline " " bitfld.long 0x00 17. " NEWDAT[82] ,New Data Bit[82]" "Not requested,Requested" bitfld.long 0x00 16. " NEWDAT[81] ,New Data Bit[81]" "Not requested,Requested" textline " " bitfld.long 0x00 15. " NEWDAT[80] ,New Data Bit[80]" "Not requested,Requested" bitfld.long 0x00 14. " NEWDAT[79] ,New Data Bit[79]" "Not requested,Requested" textline " " bitfld.long 0x00 13. " NEWDAT[78] ,New Data Bit[78]" "Not requested,Requested" bitfld.long 0x00 12. " NEWDAT[77] ,New Data Bit[77]" "Not requested,Requested" textline " " bitfld.long 0x00 11. " NEWDAT[76] ,New Data Bit[76]" "Not requested,Requested" bitfld.long 0x00 10. " NEWDAT[75] ,New Data Bit[75]" "Not requested,Requested" textline " " bitfld.long 0x00 9. " NEWDAT[74] ,New Data Bit[74]" "Not requested,Requested" bitfld.long 0x00 8. " NEWDAT[73] ,New Data Bit[73]" "Not requested,Requested" textline " " bitfld.long 0x00 7. " NEWDAT[72] ,New Data Bit[72]" "Not requested,Requested" bitfld.long 0x00 6. " NEWDAT[71] ,New Data Bit[71]" "Not requested,Requested" textline " " bitfld.long 0x00 5. " NEWDAT[70] ,New Data Bit[70]" "Not requested,Requested" bitfld.long 0x00 4. " NEWDAT[69] ,New Data Bit[69]" "Not requested,Requested" textline " " bitfld.long 0x00 3. " NEWDAT[68] ,New Data Bit[68]" "Not requested,Requested" bitfld.long 0x00 2. " NEWDAT[67] ,New Data Bit[67]" "Not requested,Requested" textline " " bitfld.long 0x00 1. " NEWDAT[66] ,New Data Bit[66]" "Not requested,Requested" bitfld.long 0x00 0. " NEWDAT[65] ,New Data Bit[65]" "Not requested,Requested" rgroup.long 0xA8++0x3 line.long 0x0 "NEWDAT78,New Data 7-8" bitfld.long 0x00 31. " NEWDAT[128] ,New Data Bit[128]" "Not requested,Requested" bitfld.long 0x00 30. " NEWDAT[127] ,New Data Bit[127]" "Not requested,Requested" textline " " bitfld.long 0x00 29. " NEWDAT[126] ,New Data Bit[126]" "Not requested,Requested" bitfld.long 0x00 28. " NEWDAT[125] ,New Data Bit[125]" "Not requested,Requested" textline " " bitfld.long 0x00 27. " NEWDAT[124] ,New Data Bit[124]" "Not requested,Requested" bitfld.long 0x00 26. " NEWDAT[123] ,New Data Bit[123]" "Not requested,Requested" textline " " bitfld.long 0x00 25. " NEWDAT[122] ,New Data Bit[122]" "Not requested,Requested" bitfld.long 0x00 24. " NEWDAT[121] ,New Data Bit[121]" "Not requested,Requested" textline " " bitfld.long 0x00 23. " NEWDAT[120] ,New Data Bit[120]" "Not requested,Requested" bitfld.long 0x00 22. " NEWDAT[119] ,New Data Bit[119]" "Not requested,Requested" textline " " bitfld.long 0x00 21. " NEWDAT[118] ,New Data Bit[118]" "Not requested,Requested" bitfld.long 0x00 20. " NEWDAT[117] ,New Data Bit[117]" "Not requested,Requested" textline " " bitfld.long 0x00 19. " NEWDAT[116] ,New Data Bit[116]" "Not requested,Requested" bitfld.long 0x00 18. " NEWDAT[115] ,New Data Bit[115]" "Not requested,Requested" textline " " bitfld.long 0x00 17. " NEWDAT[114] ,New Data Bit[114]" "Not requested,Requested" bitfld.long 0x00 16. " NEWDAT[113] ,New Data Bit[113]" "Not requested,Requested" textline " " bitfld.long 0x00 15. " NEWDAT[112] ,New Data Bit[112]" "Not requested,Requested" bitfld.long 0x00 14. " NEWDAT[111] ,New Data Bit[111]" "Not requested,Requested" textline " " bitfld.long 0x00 13. " NEWDAT[110] ,New Data Bit[110]" "Not requested,Requested" bitfld.long 0x00 12. " NEWDAT[109] ,New Data Bit[109]" "Not requested,Requested" textline " " bitfld.long 0x00 11. " NEWDAT[108] ,New Data Bit[108]" "Not requested,Requested" bitfld.long 0x00 10. " NEWDAT[107] ,New Data Bit[107]" "Not requested,Requested" textline " " bitfld.long 0x00 9. " NEWDAT[106] ,New Data Bit[106]" "Not requested,Requested" bitfld.long 0x00 8. " NEWDAT[105] ,New Data Bit[105]" "Not requested,Requested" textline " " bitfld.long 0x00 7. " NEWDAT[104] ,New Data Bit[104]" "Not requested,Requested" bitfld.long 0x00 6. " NEWDAT[103] ,New Data Bit[103]" "Not requested,Requested" textline " " bitfld.long 0x00 5. " NEWDAT[102] ,New Data Bit[102]" "Not requested,Requested" bitfld.long 0x00 4. " NEWDAT[101] ,New Data Bit[101]" "Not requested,Requested" textline " " bitfld.long 0x00 3. " NEWDAT[100] ,New Data Bit[100]" "Not requested,Requested" bitfld.long 0x00 2. " NEWDAT[99] ,New Data Bit[99]" "Not requested,Requested" textline " " bitfld.long 0x00 1. " NEWDAT[98] ,New Data Bit[98]" "Not requested,Requested" bitfld.long 0x00 0. " NEWDAT[97] ,New Data Bit[97]" "Not requested,Requested" rgroup.long 0xAC++0x3 line.long 0x0 "INTPENX,Interrupt Pending X" bitfld.long 0x00 14.--15. " INTPNDREG8 ,Interrupt Pending 8" "0,1,2,3" bitfld.long 0x00 12.--13. " INTPNDREG7 ,Interrupt Pending 7" "0,1,2,3" bitfld.long 0x00 10.--11. " INTPNDREG6 ,Interrupt Pending 6" "0,1,2,3" textline " " bitfld.long 0x00 8.--9. " INTPNDREG5 ,Interrupt Pending 5 Register" "0,1,2,3" bitfld.long 0x00 6.--7. " INTPNDREG4 ,Interrupt Pending4" "0,1,2,3" bitfld.long 0x00 4.--5. " INTPNDREG3 ,Interrupt Pending3" "0,1,2,3" textline " " bitfld.long 0x00 2.--3. " INTPNDREG2 ,Interrupt Pending2 Register" "0,1,2,3" bitfld.long 0x00 0.--1. " INTPNDREG1 ,Interrupt Pending1" "0,1,2,3" rgroup.long 0xB0++0x3 line.long 0x0 "INTPEN12,Interrupt Pending 1-2" bitfld.long 0x00 31. " INTPND[32] ,Interrupt Pending Bit[32]" "No interrupt,Interrupt" bitfld.long 0x00 30. " INTPND[31] ,Interrupt Pending Bit[31]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 29. " INTPND[30] ,Interrupt Pending Bit[30]" "No interrupt,Interrupt" bitfld.long 0x00 28. " INTPND[29] ,Interrupt Pending Bit[29]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " INTPND[28] ,Interrupt Pending Bit[28]" "No interrupt,Interrupt" bitfld.long 0x00 26. " INTPND[27] ,Interrupt Pending Bit[27]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 25. " INTPND[26] ,Interrupt Pending Bit[26]" "No interrupt,Interrupt" bitfld.long 0x00 24. " INTPND[25] ,Interrupt Pending Bit[25]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " INTPND[24] ,Interrupt Pending Bit[24]" "No interrupt,Interrupt" bitfld.long 0x00 22. " INTPND[23] ,Interrupt Pending Bit[23]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 21. " INTPND[22] ,Interrupt Pending Bit[22]" "No interrupt,Interrupt" bitfld.long 0x00 20. " INTPND[21] ,Interrupt Pending Bit[21]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " INTPND[20] ,Interrupt Pending Bit[20]" "No interrupt,Interrupt" bitfld.long 0x00 18. " INTPND[19] ,Interrupt Pending Bit[19]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 17. " INTPND[18] ,Interrupt Pending Bit[18]" "No interrupt,Interrupt" bitfld.long 0x00 16. " INTPND[17] ,Interrupt Pending Bit[17]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 15. " INTPND[16] ,Interrupt Pending Bit[16]" "No interrupt,Interrupt" bitfld.long 0x00 14. " INTPND[15] ,Interrupt Pending Bit[15]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 13. " INTPND[14] ,Interrupt Pending Bit[14]" "No interrupt,Interrupt" bitfld.long 0x00 12. " INTPND[13] ,Interrupt Pending Bit[13]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " INTPND[12] ,Interrupt Pending Bit[12]" "No interrupt,Interrupt" bitfld.long 0x00 10. " INTPND[11] ,Interrupt Pending Bit[11]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 9. " INTPND[10] ,Interrupt Pending Bit[10]" "No interrupt,Interrupt" bitfld.long 0x00 8. " INTPND[9] ,Interrupt Pending Bit[9]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 7. " INTPND[8] ,Interrupt Pending Bit[8]" "No interrupt,Interrupt" bitfld.long 0x00 6. " INTPND[7] ,Interrupt Pending Bit[7]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 5. " INTPND[6] ,Interrupt Pending Bit[6]" "No interrupt,Interrupt" bitfld.long 0x00 4. " INTPND[5] ,Interrupt Pending Bit[5]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " INTPND[4] ,Interrupt Pending Bit[4]" "No interrupt,Interrupt" bitfld.long 0x00 2. " INTPND[3] ,Interrupt Pending Bit[3]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " INTPND[2] ,Interrupt Pending Bit[2]" "No interrupt,Interrupt" bitfld.long 0x00 0. " INTPND[1] ,Interrupt Pending Bit[1]" "No interrupt,Interrupt" rgroup.long 0xB4++0x3 line.long 0x0 "INTPEN34,Interrupt Pending 3-4" bitfld.long 0x00 31. " INTPND[64] ,Interrupt Pending Bit[64]" "No interrupt,Interrupt" bitfld.long 0x00 30. " INTPND[63] ,Interrupt Pending Bit[63]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 29. " INTPND[62] ,Interrupt Pending Bit[62]" "No interrupt,Interrupt" bitfld.long 0x00 28. " INTPND[61] ,Interrupt Pending Bit[61]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " INTPND[60] ,Interrupt Pending Bit[60]" "No interrupt,Interrupt" bitfld.long 0x00 26. " INTPND[59] ,Interrupt Pending Bit[59]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 25. " INTPND[58] ,Interrupt Pending Bit[58]" "No interrupt,Interrupt" bitfld.long 0x00 24. " INTPND[57] ,Interrupt Pending Bit[57]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " INTPND[56] ,Interrupt Pending Bit[56]" "No interrupt,Interrupt" bitfld.long 0x00 22. " INTPND[55] ,Interrupt Pending Bit[55]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 21. " INTPND[54] ,Interrupt Pending Bit[54]" "No interrupt,Interrupt" bitfld.long 0x00 20. " INTPND[53] ,Interrupt Pending Bit[53]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " INTPND[52] ,Interrupt Pending Bit[52]" "No interrupt,Interrupt" bitfld.long 0x00 18. " INTPND[51] ,Interrupt Pending Bit[51]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 17. " INTPND[50] ,Interrupt Pending Bit[50]" "No interrupt,Interrupt" bitfld.long 0x00 16. " INTPND[49] ,Interrupt Pending Bit[49]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 15. " INTPND[48] ,Interrupt Pending Bit[48]" "No interrupt,Interrupt" bitfld.long 0x00 14. " INTPND[47] ,Interrupt Pending Bit[47]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 13. " INTPND[46] ,Interrupt Pending Bit[46]" "No interrupt,Interrupt" bitfld.long 0x00 12. " INTPND[45] ,Interrupt Pending Bit[45]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " INTPND[44] ,Interrupt Pending Bit[44]" "No interrupt,Interrupt" bitfld.long 0x00 10. " INTPND[43] ,Interrupt Pending Bit[43]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 9. " INTPND[42] ,Interrupt Pending Bit[42]" "No interrupt,Interrupt" bitfld.long 0x00 8. " INTPND[41] ,Interrupt Pending Bit[41]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 7. " INTPND[40] ,Interrupt Pending Bit[40]" "No interrupt,Interrupt" bitfld.long 0x00 6. " INTPND[39] ,Interrupt Pending Bit[39]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 5. " INTPND[38] ,Interrupt Pending Bit[38]" "No interrupt,Interrupt" bitfld.long 0x00 4. " INTPND[37] ,Interrupt Pending Bit[37]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " INTPND[36] ,Interrupt Pending Bit[36]" "No interrupt,Interrupt" bitfld.long 0x00 2. " INTPND[35] ,Interrupt Pending Bit[35]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " INTPND[34] ,Interrupt Pending Bit[34]" "No interrupt,Interrupt" bitfld.long 0x00 0. " INTPND[33] ,Interrupt Pending Bit[33]" "No interrupt,Interrupt" rgroup.long 0xB8++0x3 line.long 0x0 "INTPEN56,Interrupt Pending 5-6" bitfld.long 0x00 31. " INTPND[96] ,Interrupt Pending Bit[96]" "No interrupt,Interrupt" bitfld.long 0x00 30. " INTPND[95] ,Interrupt Pending Bit[95]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 29. " INTPND[94] ,Interrupt Pending Bit[94]" "No interrupt,Interrupt" bitfld.long 0x00 28. " INTPND[93] ,Interrupt Pending Bit[93]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " INTPND[92] ,Interrupt Pending Bit[92]" "No interrupt,Interrupt" bitfld.long 0x00 26. " INTPND[91] ,Interrupt Pending Bit[91]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 25. " INTPND[90] ,Interrupt Pending Bit[90]" "No interrupt,Interrupt" bitfld.long 0x00 24. " INTPND[89] ,Interrupt Pending Bit[89]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " INTPND[88] ,Interrupt Pending Bit[88]" "No interrupt,Interrupt" bitfld.long 0x00 22. " INTPND[87] ,Interrupt Pending Bit[87]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 21. " INTPND[86] ,Interrupt Pending Bit[86]" "No interrupt,Interrupt" bitfld.long 0x00 20. " INTPND[85] ,Interrupt Pending Bit[85]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " INTPND[84] ,Interrupt Pending Bit[84]" "No interrupt,Interrupt" bitfld.long 0x00 18. " INTPND[83] ,Interrupt Pending Bit[83]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 17. " INTPND[82] ,Interrupt Pending Bit[82]" "No interrupt,Interrupt" bitfld.long 0x00 16. " INTPND[81] ,Interrupt Pending Bit[81]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 15. " INTPND[80] ,Interrupt Pending Bit[80]" "No interrupt,Interrupt" bitfld.long 0x00 14. " INTPND[79] ,Interrupt Pending Bit[79]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 13. " INTPND[78] ,Interrupt Pending Bit[78]" "No interrupt,Interrupt" bitfld.long 0x00 12. " INTPND[77] ,Interrupt Pending Bit[77]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " INTPND[76] ,Interrupt Pending Bit[76]" "No interrupt,Interrupt" bitfld.long 0x00 10. " INTPND[75] ,Interrupt Pending Bit[75]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 9. " INTPND[74] ,Interrupt Pending Bit[74]" "No interrupt,Interrupt" bitfld.long 0x00 8. " INTPND[73] ,Interrupt Pending Bit[73]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 7. " INTPND[72] ,Interrupt Pending Bit[72]" "No interrupt,Interrupt" bitfld.long 0x00 6. " INTPND[71] ,Interrupt Pending Bit[71]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 5. " INTPND[70] ,Interrupt Pending Bit[70]" "No interrupt,Interrupt" bitfld.long 0x00 4. " INTPND[69] ,Interrupt Pending Bit[69]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " INTPND[68] ,Interrupt Pending Bit[68]" "No interrupt,Interrupt" bitfld.long 0x00 2. " INTPND[67] ,Interrupt Pending Bit[67]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " INTPND[66] ,Interrupt Pending Bit[66]" "No interrupt,Interrupt" bitfld.long 0x00 0. " INTPND[65] ,Interrupt Pending Bit[65]" "No interrupt,Interrupt" rgroup.long 0xBC++0x3 line.long 0x0 "INTPEN78,Interrupt Pending 7-8" bitfld.long 0x00 31. " INTPND[128] ,Interrupt Pending Bit[128]" "No interrupt,Interrupt" bitfld.long 0x00 30. " INTPND[127] ,Interrupt Pending Bit[127]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 29. " INTPND[126] ,Interrupt Pending Bit[126]" "No interrupt,Interrupt" bitfld.long 0x00 28. " INTPND[125] ,Interrupt Pending Bit[125]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " INTPND[124] ,Interrupt Pending Bit[124]" "No interrupt,Interrupt" bitfld.long 0x00 26. " INTPND[123] ,Interrupt Pending Bit[123]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 25. " INTPND[122] ,Interrupt Pending Bit[122]" "No interrupt,Interrupt" bitfld.long 0x00 24. " INTPND[121] ,Interrupt Pending Bit[121]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " INTPND[120] ,Interrupt Pending Bit[120]" "No interrupt,Interrupt" bitfld.long 0x00 22. " INTPND[119] ,Interrupt Pending Bit[119]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 21. " INTPND[118] ,Interrupt Pending Bit[118]" "No interrupt,Interrupt" bitfld.long 0x00 20. " INTPND[117] ,Interrupt Pending Bit[117]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " INTPND[116] ,Interrupt Pending Bit[116]" "No interrupt,Interrupt" bitfld.long 0x00 18. " INTPND[115] ,Interrupt Pending Bit[115]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 17. " INTPND[114] ,Interrupt Pending Bit[114]" "No interrupt,Interrupt" bitfld.long 0x00 16. " INTPND[113] ,Interrupt Pending Bit[113]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 15. " INTPND[112] ,Interrupt Pending Bit[112]" "No interrupt,Interrupt" bitfld.long 0x00 14. " INTPND[111] ,Interrupt Pending Bit[111]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 13. " INTPND[110] ,Interrupt Pending Bit[110]" "No interrupt,Interrupt" bitfld.long 0x00 12. " INTPND[109] ,Interrupt Pending Bit[109]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " INTPND[108] ,Interrupt Pending Bit[108]" "No interrupt,Interrupt" bitfld.long 0x00 10. " INTPND[107] ,Interrupt Pending Bit[107]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 9. " INTPND[106] ,Interrupt Pending Bit[106]" "No interrupt,Interrupt" bitfld.long 0x00 8. " INTPND[105] ,Interrupt Pending Bit[105]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 7. " INTPND[104] ,Interrupt Pending Bit[104]" "No interrupt,Interrupt" bitfld.long 0x00 6. " INTPND[103] ,Interrupt Pending Bit[103]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 5. " INTPND[102] ,Interrupt Pending Bit[102]" "No interrupt,Interrupt" bitfld.long 0x00 4. " INTPND[101] ,Interrupt Pending Bit[101]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " INTPND[100] ,Interrupt Pending Bit[100]" "No interrupt,Interrupt" bitfld.long 0x00 2. " INTPND[99] ,Interrupt Pending Bit[99]" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " INTPND[98] ,Interrupt Pending Bit[98]" "No interrupt,Interrupt" bitfld.long 0x00 0. " INTPND[97] ,Interrupt Pending Bit[97]" "No interrupt,Interrupt" rgroup.long 0xC0++0x3 line.long 0x0 "MSGVALX,Message Valid X" bitfld.long 0x00 14.--15. " MSGVALREG8 ,Message Valid 8 Register" "0,1,2,3" bitfld.long 0x00 12.--13. " MSGVALREG7 ,Message Valid 7 Register" "0,1,2,3" bitfld.long 0x00 10.--11. " MSGVALREG6 ,Message Valid 6 Register" "0,1,2,3" textline " " bitfld.long 0x00 8.--9. " MSGVALREG5 ,Message Valid 5 Register" "0,1,2,3" bitfld.long 0x00 6.--7. " MSGVALREG4 ,Message Valid 4 Register" "0,1,2,3" bitfld.long 0x00 4.--5. " MSGVALREG3 ,Message Valid 3 Register" "0,1,2,3" textline " " bitfld.long 0x00 2.--3. " MSGVALREG2 ,Message Valid 2 Register" "0,1,2,3" bitfld.long 0x00 0.--1. " MSGVALREG1 ,Message Valid 1 Register" "0,1,2,3" rgroup.long 0xC4++0x3 line.long 0x0 "MSGVAL12,Message Valid 2-1" bitfld.long 0x00 31. " MSGVAL[32] ,Message Valid Bit[32]" "Ignored,Configured" bitfld.long 0x00 30. " MSGVAL[31] ,Message Valid Bit[31]" "Ignored,Configured" textline " " bitfld.long 0x00 29. " MSGVAL[30] ,Message Valid Bit[30]" "Ignored,Configured" bitfld.long 0x00 28. " MSGVAL[29] ,Message Valid Bit[29]" "Ignored,Configured" textline " " bitfld.long 0x00 27. " MSGVAL[28] ,Message Valid Bit[28]" "Ignored,Configured" bitfld.long 0x00 26. " MSGVAL[27] ,Message Valid Bit[27]" "Ignored,Configured" textline " " bitfld.long 0x00 25. " MSGVAL[26] ,Message Valid Bit[26]" "Ignored,Configured" bitfld.long 0x00 24. " MSGVAL[25] ,Message Valid Bit[25]" "Ignored,Configured" textline " " bitfld.long 0x00 23. " MSGVAL[24] ,Message Valid Bit[24]" "Ignored,Configured" bitfld.long 0x00 22. " MSGVAL[23] ,Message Valid Bit[23]" "Ignored,Configured" textline " " bitfld.long 0x00 21. " MSGVAL[22] ,Message Valid Bit[22]" "Ignored,Configured" bitfld.long 0x00 20. " MSGVAL[21] ,Message Valid Bit[21]" "Ignored,Configured" textline " " bitfld.long 0x00 19. " MSGVAL[20] ,Message Valid Bit[20]" "Ignored,Configured" bitfld.long 0x00 18. " MSGVAL[19] ,Message Valid Bit[19]" "Ignored,Configured" textline " " bitfld.long 0x00 17. " MSGVAL[18] ,Message Valid Bit[18]" "Ignored,Configured" bitfld.long 0x00 16. " MSGVAL[17] ,Message Valid Bit[17]" "Ignored,Configured" textline " " bitfld.long 0x00 15. " MSGVAL[16] ,Message Valid Bit[16]" "Ignored,Configured" bitfld.long 0x00 14. " MSGVAL[15] ,Message Valid Bit[15]" "Ignored,Configured" textline " " bitfld.long 0x00 13. " MSGVAL[14] ,Message Valid Bit[14]" "Ignored,Configured" bitfld.long 0x00 12. " MSGVAL[13] ,Message Valid Bit[13]" "Ignored,Configured" textline " " bitfld.long 0x00 11. " MSGVAL[12] ,Message Valid Bit[12]" "Ignored,Configured" bitfld.long 0x00 10. " MSGVAL[11] ,Message Valid Bit[11]" "Ignored,Configured" textline " " bitfld.long 0x00 9. " MSGVAL[10] ,Message Valid Bit[10]" "Ignored,Configured" bitfld.long 0x00 8. " MSGVAL[9] ,Message Valid Bit[9]" "Ignored,Configured" textline " " bitfld.long 0x00 7. " MSGVAL[8] ,Message Valid Bit[8]" "Ignored,Configured" bitfld.long 0x00 6. " MSGVAL[7] ,Message Valid Bit[7]" "Ignored,Configured" textline " " bitfld.long 0x00 5. " MSGVAL[6] ,Message Valid Bit[6]" "Ignored,Configured" bitfld.long 0x00 4. " MSGVAL[5] ,Message Valid Bit[5]" "Ignored,Configured" textline " " bitfld.long 0x00 3. " MSGVAL[4] ,Message Valid Bit[4]" "Ignored,Configured" bitfld.long 0x00 2. " MSGVAL[3] ,Message Valid Bit[3]" "Ignored,Configured" textline " " bitfld.long 0x00 1. " MSGVAL[2] ,Message Valid Bit[2]" "Ignored,Configured" bitfld.long 0x00 0. " MSGVAL[1] ,Message Valid Bit[1]" "Ignored,Configured" rgroup.long 0xC8++0x3 line.long 0x0 "MSGVAL34,Message Valid 4-3" bitfld.long 0x00 31. " MSGVAL[64] ,Message Valid Bit[64]" "Ignored,Configured" bitfld.long 0x00 30. " MSGVAL[63] ,Message Valid Bit[63]" "Ignored,Configured" textline " " bitfld.long 0x00 29. " MSGVAL[62] ,Message Valid Bit[62]" "Ignored,Configured" bitfld.long 0x00 28. " MSGVAL[61] ,Message Valid Bit[61]" "Ignored,Configured" textline " " bitfld.long 0x00 27. " MSGVAL[60] ,Message Valid Bit[60]" "Ignored,Configured" bitfld.long 0x00 26. " MSGVAL[59] ,Message Valid Bit[59]" "Ignored,Configured" textline " " bitfld.long 0x00 25. " MSGVAL[58] ,Message Valid Bit[58]" "Ignored,Configured" bitfld.long 0x00 24. " MSGVAL[57] ,Message Valid Bit[57]" "Ignored,Configured" textline " " bitfld.long 0x00 23. " MSGVAL[56] ,Message Valid Bit[56]" "Ignored,Configured" bitfld.long 0x00 22. " MSGVAL[55] ,Message Valid Bit[55]" "Ignored,Configured" textline " " bitfld.long 0x00 21. " MSGVAL[54] ,Message Valid Bit[54]" "Ignored,Configured" bitfld.long 0x00 20. " MSGVAL[53] ,Message Valid Bit[53]" "Ignored,Configured" textline " " bitfld.long 0x00 19. " MSGVAL[52] ,Message Valid Bit[52]" "Ignored,Configured" bitfld.long 0x00 18. " MSGVAL[51] ,Message Valid Bit[51]" "Ignored,Configured" textline " " bitfld.long 0x00 17. " MSGVAL[50] ,Message Valid Bit[50]" "Ignored,Configured" bitfld.long 0x00 16. " MSGVAL[49] ,Message Valid Bit[49]" "Ignored,Configured" textline " " bitfld.long 0x00 15. " MSGVAL[48] ,Message Valid Bit[48]" "Ignored,Configured" bitfld.long 0x00 14. " MSGVAL[47] ,Message Valid Bit[47]" "Ignored,Configured" textline " " bitfld.long 0x00 13. " MSGVAL[46] ,Message Valid Bit[46]" "Ignored,Configured" bitfld.long 0x00 12. " MSGVAL[45] ,Message Valid Bit[45]" "Ignored,Configured" textline " " bitfld.long 0x00 11. " MSGVAL[44] ,Message Valid Bit[44]" "Ignored,Configured" bitfld.long 0x00 10. " MSGVAL[43] ,Message Valid Bit[43]" "Ignored,Configured" textline " " bitfld.long 0x00 9. " MSGVAL[42] ,Message Valid Bit[42]" "Ignored,Configured" bitfld.long 0x00 8. " MSGVAL[41] ,Message Valid Bit[41]" "Ignored,Configured" textline " " bitfld.long 0x00 7. " MSGVAL[40] ,Message Valid Bit[40]" "Ignored,Configured" bitfld.long 0x00 6. " MSGVAL[39] ,Message Valid Bit[39]" "Ignored,Configured" textline " " bitfld.long 0x00 5. " MSGVAL[38] ,Message Valid Bit[38]" "Ignored,Configured" bitfld.long 0x00 4. " MSGVAL[37] ,Message Valid Bit[37]" "Ignored,Configured" textline " " bitfld.long 0x00 3. " MSGVAL[36] ,Message Valid Bit[36]" "Ignored,Configured" bitfld.long 0x00 2. " MSGVAL[35] ,Message Valid Bit[35]" "Ignored,Configured" textline " " bitfld.long 0x00 1. " MSGVAL[34] ,Message Valid Bit[34]" "Ignored,Configured" bitfld.long 0x00 0. " MSGVAL[33] ,Message Valid Bit[33]" "Ignored,Configured" rgroup.long 0xCC++0x3 line.long 0x0 "MSGVAL56,Message Valid 6-5" bitfld.long 0x00 31. " MSGVAL[96] ,Message Valid Bit[96]" "Ignored,Configured" bitfld.long 0x00 30. " MSGVAL[95] ,Message Valid Bit[95]" "Ignored,Configured" textline " " bitfld.long 0x00 29. " MSGVAL[94] ,Message Valid Bit[94]" "Ignored,Configured" bitfld.long 0x00 28. " MSGVAL[93] ,Message Valid Bit[93]" "Ignored,Configured" textline " " bitfld.long 0x00 27. " MSGVAL[92] ,Message Valid Bit[92]" "Ignored,Configured" bitfld.long 0x00 26. " MSGVAL[91] ,Message Valid Bit[91]" "Ignored,Configured" textline " " bitfld.long 0x00 25. " MSGVAL[90] ,Message Valid Bit[90]" "Ignored,Configured" bitfld.long 0x00 24. " MSGVAL[89] ,Message Valid Bit[89]" "Ignored,Configured" textline " " bitfld.long 0x00 23. " MSGVAL[88] ,Message Valid Bit[88]" "Ignored,Configured" bitfld.long 0x00 22. " MSGVAL[87] ,Message Valid Bit[87]" "Ignored,Configured" textline " " bitfld.long 0x00 21. " MSGVAL[86] ,Message Valid Bit[86]" "Ignored,Configured" bitfld.long 0x00 20. " MSGVAL[85] ,Message Valid Bit[85]" "Ignored,Configured" textline " " bitfld.long 0x00 19. " MSGVAL[84] ,Message Valid Bit[84]" "Ignored,Configured" bitfld.long 0x00 18. " MSGVAL[83] ,Message Valid Bit[83]" "Ignored,Configured" textline " " bitfld.long 0x00 17. " MSGVAL[82] ,Message Valid Bit[82]" "Ignored,Configured" bitfld.long 0x00 16. " MSGVAL[81] ,Message Valid Bit[81]" "Ignored,Configured" textline " " bitfld.long 0x00 15. " MSGVAL[80] ,Message Valid Bit[80]" "Ignored,Configured" bitfld.long 0x00 14. " MSGVAL[79] ,Message Valid Bit[79]" "Ignored,Configured" textline " " bitfld.long 0x00 13. " MSGVAL[78] ,Message Valid Bit[78]" "Ignored,Configured" bitfld.long 0x00 12. " MSGVAL[77] ,Message Valid Bit[77]" "Ignored,Configured" textline " " bitfld.long 0x00 11. " MSGVAL[76] ,Message Valid Bit[76]" "Ignored,Configured" bitfld.long 0x00 10. " MSGVAL[75] ,Message Valid Bit[75]" "Ignored,Configured" textline " " bitfld.long 0x00 9. " MSGVAL[74] ,Message Valid Bit[74]" "Ignored,Configured" bitfld.long 0x00 8. " MSGVAL[73] ,Message Valid Bit[73]" "Ignored,Configured" textline " " bitfld.long 0x00 7. " MSGVAL[72] ,Message Valid Bit[72]" "Ignored,Configured" bitfld.long 0x00 6. " MSGVAL[71] ,Message Valid Bit[71]" "Ignored,Configured" textline " " bitfld.long 0x00 5. " MSGVAL[70] ,Message Valid Bit[70]" "Ignored,Configured" bitfld.long 0x00 4. " MSGVAL[69] ,Message Valid Bit[69]" "Ignored,Configured" textline " " bitfld.long 0x00 3. " MSGVAL[68] ,Message Valid Bit[68]" "Ignored,Configured" bitfld.long 0x00 2. " MSGVAL[67] ,Message Valid Bit[67]" "Ignored,Configured" textline " " bitfld.long 0x00 1. " MSGVAL[66] ,Message Valid Bit[66]" "Ignored,Configured" bitfld.long 0x00 0. " MSGVAL[65] ,Message Valid Bit[65]" "Ignored,Configured" rgroup.long 0xD0++0x3 line.long 0x0 "MSGVAL78,Message Valid 8-7" bitfld.long 0x00 31. " MSGVAL[128] ,Message Valid Bit[128]" "Ignored,Configured" bitfld.long 0x00 30. " MSGVAL[127] ,Message Valid Bit[127]" "Ignored,Configured" textline " " bitfld.long 0x00 29. " MSGVAL[126] ,Message Valid Bit[126]" "Ignored,Configured" bitfld.long 0x00 28. " MSGVAL[125] ,Message Valid Bit[125]" "Ignored,Configured" textline " " bitfld.long 0x00 27. " MSGVAL[124] ,Message Valid Bit[124]" "Ignored,Configured" bitfld.long 0x00 26. " MSGVAL[123] ,Message Valid Bit[123]" "Ignored,Configured" textline " " bitfld.long 0x00 25. " MSGVAL[122] ,Message Valid Bit[122]" "Ignored,Configured" bitfld.long 0x00 24. " MSGVAL[121] ,Message Valid Bit[121]" "Ignored,Configured" textline " " bitfld.long 0x00 23. " MSGVAL[120] ,Message Valid Bit[120]" "Ignored,Configured" bitfld.long 0x00 22. " MSGVAL[119] ,Message Valid Bit[119]" "Ignored,Configured" textline " " bitfld.long 0x00 21. " MSGVAL[118] ,Message Valid Bit[118]" "Ignored,Configured" bitfld.long 0x00 20. " MSGVAL[117] ,Message Valid Bit[117]" "Ignored,Configured" textline " " bitfld.long 0x00 19. " MSGVAL[116] ,Message Valid Bit[116]" "Ignored,Configured" bitfld.long 0x00 18. " MSGVAL[115] ,Message Valid Bit[115]" "Ignored,Configured" textline " " bitfld.long 0x00 17. " MSGVAL[114] ,Message Valid Bit[114]" "Ignored,Configured" bitfld.long 0x00 16. " MSGVAL[113] ,Message Valid Bit[113]" "Ignored,Configured" textline " " bitfld.long 0x00 15. " MSGVAL[112] ,Message Valid Bit[112]" "Ignored,Configured" bitfld.long 0x00 14. " MSGVAL[111] ,Message Valid Bit[111]" "Ignored,Configured" textline " " bitfld.long 0x00 13. " MSGVAL[110] ,Message Valid Bit[110]" "Ignored,Configured" bitfld.long 0x00 12. " MSGVAL[109] ,Message Valid Bit[109]" "Ignored,Configured" textline " " bitfld.long 0x00 11. " MSGVAL[108] ,Message Valid Bit[108]" "Ignored,Configured" bitfld.long 0x00 10. " MSGVAL[107] ,Message Valid Bit[107]" "Ignored,Configured" textline " " bitfld.long 0x00 9. " MSGVAL[106] ,Message Valid Bit[106]" "Ignored,Configured" bitfld.long 0x00 8. " MSGVAL[105] ,Message Valid Bit[105]" "Ignored,Configured" textline " " bitfld.long 0x00 7. " MSGVAL[104] ,Message Valid Bit[104]" "Ignored,Configured" bitfld.long 0x00 6. " MSGVAL[103] ,Message Valid Bit[103]" "Ignored,Configured" textline " " bitfld.long 0x00 5. " MSGVAL[102] ,Message Valid Bit[102]" "Ignored,Configured" bitfld.long 0x00 4. " MSGVAL[101] ,Message Valid Bit[101]" "Ignored,Configured" textline " " bitfld.long 0x00 3. " MSGVAL[100] ,Message Valid Bit[100]" "Ignored,Configured" bitfld.long 0x00 2. " MSGVAL[99] ,Message Valid Bit[99]" "Ignored,Configured" textline " " bitfld.long 0x00 1. " MSGVAL[98] ,Message Valid Bit[98]" "Ignored,Configured" bitfld.long 0x00 0. " MSGVAL[97] ,Message Valid Bit[97]" "Ignored,Configured" group.long 0xD8++0x3 line.long 0x0 "INTPNDMX12,IntPndMux 1-2" bitfld.long 0x00 31. " INTPNDMUX[32] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[32]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 30. " INTPNDMUX[31] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[31]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 29. " INTPNDMUX[30] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[30]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 28. " INTPNDMUX[29] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[29]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 27. " INTPNDMUX[28] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[28]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 26. " INTPNDMUX[27] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[27]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 25. " INTPNDMUX[26] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[26]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 24. " INTPNDMUX[25] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[25]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 23. " INTPNDMUX[24] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[24]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 22. " INTPNDMUX[23] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[23]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 21. " INTPNDMUX[22] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[22]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 20. " INTPNDMUX[21] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[21]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 19. " INTPNDMUX[20] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[20]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 18. " INTPNDMUX[19] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[19]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 17. " INTPNDMUX[18] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[18]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 16. " INTPNDMUX[17] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[17]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 15. " INTPNDMUX[16] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[16]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 14. " INTPNDMUX[15] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[15]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 13. " INTPNDMUX[14] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[14]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 12. " INTPNDMUX[13] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[13]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 11. " INTPNDMUX[12] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[12]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 10. " INTPNDMUX[11] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[11]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 9. " INTPNDMUX[10] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[10]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 8. " INTPNDMUX[9] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[9]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 7. " INTPNDMUX[8] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[8]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 6. " INTPNDMUX[7] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[7]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 5. " INTPNDMUX[6] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[6]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 4. " INTPNDMUX[5] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[5]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 3. " INTPNDMUX[4] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[4]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 2. " INTPNDMUX[3] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[3]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 1. " INTPNDMUX[2] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[2]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 0. " INTPNDMUX[1] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[1]" "DCAN0INT,DCAN1INT" group.long 0xDC++0x3 line.long 0x0 "INTPNDMX34,IntPndMux 3-4" bitfld.long 0x00 31. " INTPNDMUX[64] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[64]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 30. " INTPNDMUX[63] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[63]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 29. " INTPNDMUX[62] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[62]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 28. " INTPNDMUX[61] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[61]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 27. " INTPNDMUX[60] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[60]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 26. " INTPNDMUX[59] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[59]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 25. " INTPNDMUX[58] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[58]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 24. " INTPNDMUX[57] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[57]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 23. " INTPNDMUX[56] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[56]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 22. " INTPNDMUX[55] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[55]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 21. " INTPNDMUX[54] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[54]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 20. " INTPNDMUX[53] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[53]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 19. " INTPNDMUX[52] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[52]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 18. " INTPNDMUX[51] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[51]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 17. " INTPNDMUX[50] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[50]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 16. " INTPNDMUX[49] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[49]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 15. " INTPNDMUX[48] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[48]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 14. " INTPNDMUX[47] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[47]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 13. " INTPNDMUX[46] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[46]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 12. " INTPNDMUX[45] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[45]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 11. " INTPNDMUX[44] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[44]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 10. " INTPNDMUX[43] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[43]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 9. " INTPNDMUX[42] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[42]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 8. " INTPNDMUX[41] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[41]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 7. " INTPNDMUX[40] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[40]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 6. " INTPNDMUX[39] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[39]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 5. " INTPNDMUX[38] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[38]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 4. " INTPNDMUX[37] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[37]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 3. " INTPNDMUX[36] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[36]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 2. " INTPNDMUX[35] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[35]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 1. " INTPNDMUX[34] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[34]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 0. " INTPNDMUX[33] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[33]" "DCAN0INT,DCAN1INT" group.long 0xE0++0x3 line.long 0x0 "INTPNDMX56,IntPndMux 5-6" bitfld.long 0x00 31. " INTPNDMUX[96] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[96]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 30. " INTPNDMUX[95] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[95]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 29. " INTPNDMUX[94] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[94]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 28. " INTPNDMUX[93] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[93]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 27. " INTPNDMUX[92] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[92]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 26. " INTPNDMUX[91] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[91]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 25. " INTPNDMUX[90] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[90]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 24. " INTPNDMUX[89] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[89]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 23. " INTPNDMUX[88] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[88]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 22. " INTPNDMUX[87] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[87]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 21. " INTPNDMUX[86] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[86]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 20. " INTPNDMUX[85] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[85]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 19. " INTPNDMUX[84] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[84]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 18. " INTPNDMUX[83] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[83]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 17. " INTPNDMUX[82] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[82]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 16. " INTPNDMUX[81] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[81]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 15. " INTPNDMUX[80] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[80]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 14. " INTPNDMUX[79] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[79]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 13. " INTPNDMUX[78] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[78]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 12. " INTPNDMUX[77] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[77]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 11. " INTPNDMUX[76] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[76]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 10. " INTPNDMUX[75] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[75]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 9. " INTPNDMUX[74] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[74]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 8. " INTPNDMUX[73] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[73]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 7. " INTPNDMUX[72] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[72]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 6. " INTPNDMUX[71] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[71]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 5. " INTPNDMUX[70] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[70]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 4. " INTPNDMUX[69] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[69]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 3. " INTPNDMUX[68] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[68]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 2. " INTPNDMUX[67] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[67]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 1. " INTPNDMUX[66] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[66]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 0. " INTPNDMUX[65] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[65]" "DCAN0INT,DCAN1INT" group.long 0xE4++0x3 line.long 0x0 "INTPNDMX78,IntPndMux 7-8" bitfld.long 0x00 31. " INTPNDMUX[128] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[128]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 30. " INTPNDMUX[127] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[127]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 29. " INTPNDMUX[126] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[126]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 28. " INTPNDMUX[125] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[125]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 27. " INTPNDMUX[124] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[124]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 26. " INTPNDMUX[123] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[123]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 25. " INTPNDMUX[122] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[122]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 24. " INTPNDMUX[121] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[121]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 23. " INTPNDMUX[120] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[120]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 22. " INTPNDMUX[119] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[119]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 21. " INTPNDMUX[118] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[118]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 20. " INTPNDMUX[117] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[117]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 19. " INTPNDMUX[116] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[116]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 18. " INTPNDMUX[115] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[115]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 17. " INTPNDMUX[114] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[114]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 16. " INTPNDMUX[113] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[113]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 15. " INTPNDMUX[112] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[112]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 14. " INTPNDMUX[111] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[111]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 13. " INTPNDMUX[110] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[110]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 12. " INTPNDMUX[109] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[109]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 11. " INTPNDMUX[108] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[108]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 10. " INTPNDMUX[107] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[107]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 9. " INTPNDMUX[106] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[106]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 8. " INTPNDMUX[105] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[105]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 7. " INTPNDMUX[104] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[104]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 6. " INTPNDMUX[103] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[103]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 5. " INTPNDMUX[102] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[102]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 4. " INTPNDMUX[101] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[101]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 3. " INTPNDMUX[100] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[100]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 2. " INTPNDMUX[99] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[99]" "DCAN0INT,DCAN1INT" textline " " bitfld.long 0x00 1. " INTPNDMUX[98] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[98]" "DCAN0INT,DCAN1INT" bitfld.long 0x00 0. " INTPNDMUX[97] ,Multiplexes IntPnd Value to One of Two Interrupt Lines Bit[97]" "DCAN0INT,DCAN1INT" width 9. tree "IF1 / IF2" group.long 0x100++0x3 line.long 0x0 "IF1COM,IF1 Command Mask / Command Request Register" bitfld.long 0x00 23. " WR/RD ,Write / Read" "Read,Write" bitfld.long 0x00 22. " MASK ,Access Mask Bits" "Not accessed,Accessed" textline " " bitfld.long 0x00 21. " ARB ,Access Arbitration Bits" "Not accessed,Accessed" bitfld.long 0x00 20. " CONTROL ,Access Control Bits" "Unchanged,Control bits" textline " " bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Low,High" bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Not requested,Requested" textline " " bitfld.long 0x00 17. " DATA_A ,Access Data Bytes 0-3" "Unchanged,Data bytes 0-3" bitfld.long 0x00 16. " DATA_B ,Access Data Bytes 4-7" "Unchanged,Data bytes 4-7" textline " " bitfld.long 0x00 15. " BUSY ,Busy Flag" "Reset,Set" bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA Feature for Subsequent Internal IF1 Update" "No active,Active" textline " " hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Message Number" group.long 0x120++0x3 line.long 0x0 "IF2COM,IF2 Command Mask / Command Request Register" bitfld.long 0x00 23. " WR/RD ,Write / Read" "Read,Write" bitfld.long 0x00 22. " MASK ,Access Mask Bits" "Not accessed,Accessed" textline " " bitfld.long 0x00 21. " ARB ,Access Arbitration Bits" "Not accessed,Accessed" bitfld.long 0x00 20. " CONTROL ,Access Control Bits" "Unchanged,Control bits" textline " " bitfld.long 0x00 19. " CLRINTPND ,Clear Interrupt Pending Bit" "Low,High" bitfld.long 0x00 18. " TXRQST/NEWDAT ,Access Transmission Request Bit" "Not requested,Requested" textline " " bitfld.long 0x00 17. " DATA_A ,Access Data Bytes 0-3" "Unchanged,Data bytes 0-3" bitfld.long 0x00 16. " DATA_B ,Access Data Bytes 4-7" "Unchanged,Data bytes 4-7" textline " " bitfld.long 0x00 15. " BUSY ,Busy Flag" "Reset,Set" bitfld.long 0x00 14. " DMAACTIVE ,Activation of DMA Feature for Subsequent Internal IF1 Update" "No active,Active" textline " " hexmask.long.byte 0x00 0.--7. 1. " MESSAGE_NUMBER ,Message Number" group.long 0x104++0x3 line.long 0x0 "IF1MSK,If1 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Not masked,Masked" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Not masked,Masked" textline " " bitfld.long 0x00 28. " MSK[28] ,Identifier Mask 28" "Not masked,Masked" bitfld.long 0x00 27. " MSK[27] ,Identifier Mask 27" "Not masked,Masked" bitfld.long 0x00 26. " MSK[26] ,Identifier Mask 26" "Not masked,Masked" textline " " bitfld.long 0x00 25. " MSK[25] ,Identifier Mask 25" "Not masked,Masked" bitfld.long 0x00 24. " MSK[24] ,Identifier Mask 24" "Not masked,Masked" bitfld.long 0x00 23. " MSK[23] ,Identifier Mask 23" "Not masked,Masked" textline " " bitfld.long 0x00 22. " MSK[22] ,Identifier Mask 22" "Not masked,Masked" bitfld.long 0x00 21. " MSK[21] ,Identifier Mask 21" "Not masked,Masked" bitfld.long 0x00 20. " MSK[20] ,Identifier Mask 20" "Not masked,Masked" textline " " bitfld.long 0x00 19. " MSK[19] ,Identifier Mask 19" "Not masked,Masked" bitfld.long 0x00 18. " MSK[18] ,Identifier Mask 18" "Not masked,Masked" bitfld.long 0x00 17. " MSK[17] ,Identifier Mask 17" "Not masked,Masked" textline " " bitfld.long 0x00 16. " MSK[16] ,Identifier Mask 16" "Not masked,Masked" bitfld.long 0x00 15. " MSK[15] ,Identifier Mask 15" "Not masked,Masked" bitfld.long 0x00 14. " MSK[14] ,Identifier Mask 14" "Not masked,Masked" textline " " bitfld.long 0x00 13. " MSK[13] ,Identifier Mask 13" "Not masked,Masked" bitfld.long 0x00 12. " MSK[12] ,Identifier Mask 12" "Not masked,Masked" bitfld.long 0x00 11. " MSK[11] ,Identifier Mask 11" "Not masked,Masked" textline " " bitfld.long 0x00 10. " MSK[10] ,Identifier Mask 10" "Not masked,Masked" bitfld.long 0x00 9. " MSK[9] ,Identifier Mask 9" "Not masked,Masked" bitfld.long 0x00 8. " MSK[8] ,Identifier Mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MSK[7] ,Identifier Mask 7" "Not masked,Masked" bitfld.long 0x00 6. " MSK[6] ,Identifier Mask 6" "Not masked,Masked" bitfld.long 0x00 5. " MSK[5] ,Identifier Mask 5" "Not masked,Masked" textline " " bitfld.long 0x00 4. " MSK[4] ,Identifier Mask 4" "Not masked,Masked" bitfld.long 0x00 3. " MSK[3] ,Identifier Mask 3" "Not masked,Masked" bitfld.long 0x00 2. " MSK[2] ,Identifier Mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " MSK[1] ,Identifier Mask 1" "Not masked,Masked" bitfld.long 0x00 0. " MSK[0] ,Identifier Mask 0" "Not masked,Masked" group.long 0x124++0x3 line.long 0x0 "IF2MSK,If2 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Not masked,Masked" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Not masked,Masked" textline " " bitfld.long 0x00 28. " MSK[28] ,Identifier Mask 28" "Not masked,Masked" bitfld.long 0x00 27. " MSK[27] ,Identifier Mask 27" "Not masked,Masked" bitfld.long 0x00 26. " MSK[26] ,Identifier Mask 26" "Not masked,Masked" textline " " bitfld.long 0x00 25. " MSK[25] ,Identifier Mask 25" "Not masked,Masked" bitfld.long 0x00 24. " MSK[24] ,Identifier Mask 24" "Not masked,Masked" bitfld.long 0x00 23. " MSK[23] ,Identifier Mask 23" "Not masked,Masked" textline " " bitfld.long 0x00 22. " MSK[22] ,Identifier Mask 22" "Not masked,Masked" bitfld.long 0x00 21. " MSK[21] ,Identifier Mask 21" "Not masked,Masked" bitfld.long 0x00 20. " MSK[20] ,Identifier Mask 20" "Not masked,Masked" textline " " bitfld.long 0x00 19. " MSK[19] ,Identifier Mask 19" "Not masked,Masked" bitfld.long 0x00 18. " MSK[18] ,Identifier Mask 18" "Not masked,Masked" bitfld.long 0x00 17. " MSK[17] ,Identifier Mask 17" "Not masked,Masked" textline " " bitfld.long 0x00 16. " MSK[16] ,Identifier Mask 16" "Not masked,Masked" bitfld.long 0x00 15. " MSK[15] ,Identifier Mask 15" "Not masked,Masked" bitfld.long 0x00 14. " MSK[14] ,Identifier Mask 14" "Not masked,Masked" textline " " bitfld.long 0x00 13. " MSK[13] ,Identifier Mask 13" "Not masked,Masked" bitfld.long 0x00 12. " MSK[12] ,Identifier Mask 12" "Not masked,Masked" bitfld.long 0x00 11. " MSK[11] ,Identifier Mask 11" "Not masked,Masked" textline " " bitfld.long 0x00 10. " MSK[10] ,Identifier Mask 10" "Not masked,Masked" bitfld.long 0x00 9. " MSK[9] ,Identifier Mask 9" "Not masked,Masked" bitfld.long 0x00 8. " MSK[8] ,Identifier Mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MSK[7] ,Identifier Mask 7" "Not masked,Masked" bitfld.long 0x00 6. " MSK[6] ,Identifier Mask 6" "Not masked,Masked" bitfld.long 0x00 5. " MSK[5] ,Identifier Mask 5" "Not masked,Masked" textline " " bitfld.long 0x00 4. " MSK[4] ,Identifier Mask 4" "Not masked,Masked" bitfld.long 0x00 3. " MSK[3] ,Identifier Mask 3" "Not masked,Masked" bitfld.long 0x00 2. " MSK[2] ,Identifier Mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " MSK[1] ,Identifier Mask 1" "Not masked,Masked" bitfld.long 0x00 0. " MSK[0] ,Identifier Mask 0" "Not masked,Masked" group.long 0x108++0x3 line.long 0x0 "IF1ARB,If1 Arbitation Register" bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Ignored,Used" bitfld.long 0x00 30. " XTD ,Extended Identifier" "11-bit-standard,29-bit-extended" bitfld.long 0x00 29. " DIR ,Message direction" "Receive,Transmit" textline " " bitfld.long 0x00 28. " ID[28] ,Message Identifier 28" "29-bit ID,11-bit ID" bitfld.long 0x00 27. " ID[27] ,Message Identifier 27" "29-bit ID,11-bit ID" bitfld.long 0x00 26. " ID[26] ,Message Identifier 26" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 25. " ID[25] ,Message Identifier 25" "29-bit ID,11-bit ID" bitfld.long 0x00 24. " ID[24] ,Message Identifier 24" "29-bit ID,11-bit ID" bitfld.long 0x00 23. " ID[23] ,Message Identifier 23" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 22. " ID[22] ,Message Identifier 22" "29-bit ID,11-bit ID" bitfld.long 0x00 21. " ID[21] ,Message Identifier 21" "29-bit ID,11-bit ID" bitfld.long 0x00 20. " ID[20] ,Message Identifier 20" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 19. " ID[19] ,Message Identifier 19" "29-bit ID,11-bit ID" bitfld.long 0x00 18. " ID[18] ,Message Identifier 18" "29-bit ID,11-bit ID" bitfld.long 0x00 17. " ID[17] ,Message Identifier 17" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 16. " ID[16] ,Message Identifier 16" "29-bit ID,11-bit ID" bitfld.long 0x00 15. " ID[15] ,Message Identifier 15" "29-bit ID,11-bit ID" bitfld.long 0x00 14. " ID[14] ,Message Identifier 14" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 13. " ID[13] ,Message Identifier 13" "29-bit ID,11-bit ID" bitfld.long 0x00 12. " ID[12] ,Message Identifier 12" "29-bit ID,11-bit ID" bitfld.long 0x00 11. " ID[11] ,Message Identifier 11" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 10. " ID[10] ,Message Identifier 10" "29-bit ID,11-bit ID" bitfld.long 0x00 9. " ID[9] ,Message Identifier 9" "29-bit ID,11-bit ID" bitfld.long 0x00 8. " ID[8] ,Message Identifier 8" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 7. " ID[7] ,Message Identifier 7" "29-bit ID,11-bit ID" bitfld.long 0x00 6. " ID[6] ,Message Identifier 6" "29-bit ID,11-bit ID" bitfld.long 0x00 5. " ID[5] ,Message Identifier 5" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 4. " ID[4] ,Message Identifier 4" "29-bit ID,11-bit ID" bitfld.long 0x00 3. " ID[3] ,Message Identifier 3" "29-bit ID,11-bit ID" bitfld.long 0x00 2. " ID[2] ,Message Identifier 2" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 1. " ID[1] ,Message Identifier 1" "29-bit ID,11-bit ID" bitfld.long 0x00 0. " ID[0] ,Message Identifier 0" "29-bit ID,11-bit ID" group.long 0x128++0x3 line.long 0x0 "IF2ARB,If2 Arbitation Register" bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Ignored,Used" bitfld.long 0x00 30. " XTD ,Extended Identifier" "11-bit-standard,29-bit-extended" bitfld.long 0x00 29. " DIR ,Message direction" "Receive,Transmit" textline " " bitfld.long 0x00 28. " ID[28] ,Message Identifier 28" "29-bit ID,11-bit ID" bitfld.long 0x00 27. " ID[27] ,Message Identifier 27" "29-bit ID,11-bit ID" bitfld.long 0x00 26. " ID[26] ,Message Identifier 26" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 25. " ID[25] ,Message Identifier 25" "29-bit ID,11-bit ID" bitfld.long 0x00 24. " ID[24] ,Message Identifier 24" "29-bit ID,11-bit ID" bitfld.long 0x00 23. " ID[23] ,Message Identifier 23" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 22. " ID[22] ,Message Identifier 22" "29-bit ID,11-bit ID" bitfld.long 0x00 21. " ID[21] ,Message Identifier 21" "29-bit ID,11-bit ID" bitfld.long 0x00 20. " ID[20] ,Message Identifier 20" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 19. " ID[19] ,Message Identifier 19" "29-bit ID,11-bit ID" bitfld.long 0x00 18. " ID[18] ,Message Identifier 18" "29-bit ID,11-bit ID" bitfld.long 0x00 17. " ID[17] ,Message Identifier 17" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 16. " ID[16] ,Message Identifier 16" "29-bit ID,11-bit ID" bitfld.long 0x00 15. " ID[15] ,Message Identifier 15" "29-bit ID,11-bit ID" bitfld.long 0x00 14. " ID[14] ,Message Identifier 14" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 13. " ID[13] ,Message Identifier 13" "29-bit ID,11-bit ID" bitfld.long 0x00 12. " ID[12] ,Message Identifier 12" "29-bit ID,11-bit ID" bitfld.long 0x00 11. " ID[11] ,Message Identifier 11" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 10. " ID[10] ,Message Identifier 10" "29-bit ID,11-bit ID" bitfld.long 0x00 9. " ID[9] ,Message Identifier 9" "29-bit ID,11-bit ID" bitfld.long 0x00 8. " ID[8] ,Message Identifier 8" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 7. " ID[7] ,Message Identifier 7" "29-bit ID,11-bit ID" bitfld.long 0x00 6. " ID[6] ,Message Identifier 6" "29-bit ID,11-bit ID" bitfld.long 0x00 5. " ID[5] ,Message Identifier 5" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 4. " ID[4] ,Message Identifier 4" "29-bit ID,11-bit ID" bitfld.long 0x00 3. " ID[3] ,Message Identifier 3" "29-bit ID,11-bit ID" bitfld.long 0x00 2. " ID[2] ,Message Identifier 2" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 1. " ID[1] ,Message Identifier 1" "29-bit ID,11-bit ID" bitfld.long 0x00 0. " ID[0] ,Message Identifier 0" "29-bit ID,11-bit ID" hgroup.long 0x10C++0x3 hide.long 0x0 "IF1MCTL,If1 Message Control Register" in hgroup.long 0x12C++0x3 hide.long 0x0 "IF2MCTL,If2 Message Control Register" in group.long 0x110++0x3 line.long 0x0 "IF1DATA,If1 Data A Register" hexmask.long.byte 0x00 24.--31. 1. " DATA_3 ,Data 3" hexmask.long.byte 0x00 16.--23. 1. " DATA_2 ,Data 2" textline " " hexmask.long.byte 0x00 8.--15. 1. " DATA_1 ,Data 1" hexmask.long.byte 0x00 0.--7. 1. " DATA_0 ,Data 0" group.long 0x114++0x3 line.long 0x0 "IF1DATB,If1 Data B Register" hexmask.long.byte 0x00 24.--31. 1. " DATA_7 ,Data 7" hexmask.long.byte 0x00 16.--23. 1. " DATA_6 ,Data 6" textline " " hexmask.long.byte 0x00 8.--15. 1. " DATA_5 ,Data 5" hexmask.long.byte 0x00 0.--7. 1. " DATA_4 ,Data 4" group.long 0x130++0x3 line.long 0x0 "IF2DATA,If2 Data A Register" hexmask.long.byte 0x00 24.--31. 1. " DATA_3 ,Data 3" hexmask.long.byte 0x00 16.--23. 1. " DATA_2 ,Data 2" textline " " hexmask.long.byte 0x00 8.--15. 1. " DATA_1 ,Data 1" hexmask.long.byte 0x00 0.--7. 1. " DATA_0 ,Data 0" group.long 0x134++0x3 line.long 0x0 "IF2DATB,If2 Data B Register" hexmask.long.byte 0x00 24.--31. 1. " DATA_7 ,Data 7" hexmask.long.byte 0x00 16.--23. 1. " DATA_6 ,Data 6" textline " " hexmask.long.byte 0x00 8.--15. 1. " DATA_5 ,Data 5" hexmask.long.byte 0x00 0.--7. 1. " DATA_4 ,Data 4" tree.end tree "IF 3" group.long 0x140++0x3 line.long 0x0 "IF3OBS,If3 Observation Register" bitfld.long 0x00 15. " IF3_UPD ,IF3 Update Data" "No,Yes" bitfld.long 0x00 12. " IF3_SDB ,IF3 Status of Data B read access" "No access,Access" bitfld.long 0x00 11. " IF3_SDA ,IF3 Status of Data A read access" "No access,Access" textline " " bitfld.long 0x00 10. " IF3_SC ,IF3 Status of Control bits read access" "No access,Access" bitfld.long 0x00 9. " IF3_SA ,IF3 Status of Arbitration data read access" "No access,Access" bitfld.long 0x00 8. " IF3_SM ,IF3 Status of Mask data read access" "No access,Access" textline " " bitfld.long 0x00 4. " DATA_B ,Data B read observation" "No,Yes" bitfld.long 0x00 3. " DATA_A ,Data A read observation" "No,Yes" bitfld.long 0x00 2. " CTRL ,Ctrl read observation" "No,Yes" textline " " bitfld.long 0x00 1. " ARB ,Arbitration data read observation" "No,Yes" bitfld.long 0x00 0. " MASK ,Mask data read observation" "No,Yes" group.long 0x144++0x3 line.long 0x0 "IF3MSK,If3 Mask Register" bitfld.long 0x00 31. " MXTD ,Mask Extended Identifier" "Not masked,Masked" bitfld.long 0x00 30. " MDIR ,Mask Message Direction" "Not masked,Masked" textline " " bitfld.long 0x00 28. " MSK[28] ,Identifier Mask 28" "Not masked,Masked" bitfld.long 0x00 27. " MSK[27] ,Identifier Mask 27" "Not masked,Masked" bitfld.long 0x00 26. " MSK[26] ,Identifier Mask 26" "Not masked,Masked" textline " " bitfld.long 0x00 25. " MSK[25] ,Identifier Mask 25" "Not masked,Masked" bitfld.long 0x00 24. " MSK[24] ,Identifier Mask 24" "Not masked,Masked" bitfld.long 0x00 23. " MSK[23] ,Identifier Mask 23" "Not masked,Masked" textline " " bitfld.long 0x00 22. " MSK[22] ,Identifier Mask 22" "Not masked,Masked" bitfld.long 0x00 21. " MSK[21] ,Identifier Mask 21" "Not masked,Masked" bitfld.long 0x00 20. " MSK[20] ,Identifier Mask 20" "Not masked,Masked" textline " " bitfld.long 0x00 19. " MSK[19] ,Identifier Mask 19" "Not masked,Masked" bitfld.long 0x00 18. " MSK[18] ,Identifier Mask 18" "Not masked,Masked" bitfld.long 0x00 17. " MSK[17] ,Identifier Mask 17" "Not masked,Masked" textline " " bitfld.long 0x00 16. " MSK[16] ,Identifier Mask 16" "Not masked,Masked" bitfld.long 0x00 15. " MSK[15] ,Identifier Mask 15" "Not masked,Masked" bitfld.long 0x00 14. " MSK[14] ,Identifier Mask 14" "Not masked,Masked" textline " " bitfld.long 0x00 13. " MSK[13] ,Identifier Mask 13" "Not masked,Masked" bitfld.long 0x00 12. " MSK[12] ,Identifier Mask 12" "Not masked,Masked" bitfld.long 0x00 11. " MSK[11] ,Identifier Mask 11" "Not masked,Masked" textline " " bitfld.long 0x00 10. " MSK[10] ,Identifier Mask 10" "Not masked,Masked" bitfld.long 0x00 9. " MSK[9] ,Identifier Mask 9" "Not masked,Masked" bitfld.long 0x00 8. " MSK[8] ,Identifier Mask 8" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MSK[7] ,Identifier Mask 7" "Not masked,Masked" bitfld.long 0x00 6. " MSK[6] ,Identifier Mask 6" "Not masked,Masked" bitfld.long 0x00 5. " MSK[5] ,Identifier Mask 5" "Not masked,Masked" textline " " bitfld.long 0x00 4. " MSK[4] ,Identifier Mask 4" "Not masked,Masked" bitfld.long 0x00 3. " MSK[3] ,Identifier Mask 3" "Not masked,Masked" bitfld.long 0x00 2. " MSK[2] ,Identifier Mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " MSK[1] ,Identifier Mask 1" "Not masked,Masked" bitfld.long 0x00 0. " MSK[0] ,Identifier Mask 0" "Not masked,Masked" group.long 0x148++0x3 line.long 0x0 "IF3ARB,If3 Arbitation Register" bitfld.long 0x00 31. " MSGVAL ,Message Valid" "Ignored,Used" bitfld.long 0x00 30. " XTD ,Extended Identifier" "11-bit-standard,29-bit-extended" bitfld.long 0x00 29. " DIR ,Message direction" "Receive,Transmit" textline " " bitfld.long 0x00 28. " ID[28] ,Message Identifier 28" "29-bit ID,11-bit ID" bitfld.long 0x00 27. " ID[27] ,Message Identifier 27" "29-bit ID,11-bit ID" bitfld.long 0x00 26. " ID[26] ,Message Identifier 26" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 25. " ID[25] ,Message Identifier 25" "29-bit ID,11-bit ID" bitfld.long 0x00 24. " ID[24] ,Message Identifier 24" "29-bit ID,11-bit ID" bitfld.long 0x00 23. " ID[23] ,Message Identifier 23" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 22. " ID[22] ,Message Identifier 22" "29-bit ID,11-bit ID" bitfld.long 0x00 21. " ID[21] ,Message Identifier 21" "29-bit ID,11-bit ID" bitfld.long 0x00 20. " ID[20] ,Message Identifier 20" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 19. " ID[19] ,Message Identifier 19" "29-bit ID,11-bit ID" bitfld.long 0x00 18. " ID[18] ,Message Identifier 18" "29-bit ID,11-bit ID" bitfld.long 0x00 17. " ID[17] ,Message Identifier 17" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 16. " ID[16] ,Message Identifier 16" "29-bit ID,11-bit ID" bitfld.long 0x00 15. " ID[15] ,Message Identifier 15" "29-bit ID,11-bit ID" bitfld.long 0x00 14. " ID[14] ,Message Identifier 14" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 13. " ID[13] ,Message Identifier 13" "29-bit ID,11-bit ID" bitfld.long 0x00 12. " ID[12] ,Message Identifier 12" "29-bit ID,11-bit ID" bitfld.long 0x00 11. " ID[11] ,Message Identifier 11" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 10. " ID[10] ,Message Identifier 10" "29-bit ID,11-bit ID" bitfld.long 0x00 9. " ID[9] ,Message Identifier 9" "29-bit ID,11-bit ID" bitfld.long 0x00 8. " ID[8] ,Message Identifier 8" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 7. " ID[7] ,Message Identifier 7" "29-bit ID,11-bit ID" bitfld.long 0x00 6. " ID[6] ,Message Identifier 6" "29-bit ID,11-bit ID" bitfld.long 0x00 5. " ID[5] ,Message Identifier 5" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 4. " ID[4] ,Message Identifier 4" "29-bit ID,11-bit ID" bitfld.long 0x00 3. " ID[3] ,Message Identifier 3" "29-bit ID,11-bit ID" bitfld.long 0x00 2. " ID[2] ,Message Identifier 2" "29-bit ID,11-bit ID" textline " " bitfld.long 0x00 1. " ID[1] ,Message Identifier 1" "29-bit ID,11-bit ID" bitfld.long 0x00 0. " ID[0] ,Message Identifier 0" "29-bit ID,11-bit ID" group.long 0x14C++0x3 line.long 0x0 "IF3MCTL,If3 Message Control Register" bitfld.long 0x00 15. " NEWDAT ,New Data" "Not written,Wrote" bitfld.long 0x00 14. " MSGLST ,Message Lost" "Not losted,Losted" bitfld.long 0x00 13. " INTPND ,Interrupt Pending" "Not pended,Pended" textline " " bitfld.long 0x00 12. " UMASK ,Use Acceptance Mask" "Not used,Used" bitfld.long 0x00 11. " TXIE ,Transmit Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 10. " RXIE ,Receive Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " RMTEN ,Remote Enable" "Disabled,Enabled" bitfld.long 0x00 8. " TXRQST ,Transmit Request" "Not requested,Requested" bitfld.long 0x00 7. " EOB ,Data Frame 0-8 bits" "0,1" textline " " bitfld.long 0x00 0.--3. " DLC[3:0] ,Data length code" "0-8 data bits,0-8 data bits,0-8 data bits,0-8 data bits,0-8 data bits,0-8 data bits,0-8 data bits,0-8 data bits,0-8 data bits,8 data bytes,8 data bytes,8 data bytes,8 data bytes,8 data bytes,8 data bytes,8 data bytes" group.long 0x150++0x3 line.long 0x0 "IF3DATA,If3 Data A Register" hexmask.long.byte 0x00 24.--31. 1. " DATA_3 ,Data 3" hexmask.long.byte 0x00 16.--23. 1. " DATA_2 ,Data 2" textline " " hexmask.long.byte 0x00 8.--15. 1. " DATA_1 ,Data 1" hexmask.long.byte 0x00 0.--7. 1. " DATA_0 ,Data 0" group.long 0x154++0x3 line.long 0x0 "IF3DATB,If3 Data B Register" hexmask.long.byte 0x00 24.--31. 1. " DATA_7 ,Data 7" hexmask.long.byte 0x00 16.--23. 1. " DATA_6 ,Data 6" textline " " hexmask.long.byte 0x00 8.--15. 1. " DATA_5 ,Data 5" hexmask.long.byte 0x00 0.--7. 1. " DATA_4 ,Data 4" group.long 0x160++0x3 line.long 0x0 "IF3UPD12,Update enable 1-2 Register" bitfld.long 0x00 31. " IF3UPDATEEN[32] ,IF3 Update Enabled Bit[32]" "Disabled,Enabled" bitfld.long 0x00 30. " IF3UPDATEEN[31] ,IF3 Update Enabled Bit[31]" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " IF3UPDATEEN[30] ,IF3 Update Enabled Bit[30]" "Disabled,Enabled" bitfld.long 0x00 28. " IF3UPDATEEN[29] ,IF3 Update Enabled Bit[29]" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " IF3UPDATEEN[28] ,IF3 Update Enabled Bit[28]" "Disabled,Enabled" bitfld.long 0x00 26. " IF3UPDATEEN[27] ,IF3 Update Enabled Bit[27]" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " IF3UPDATEEN[26] ,IF3 Update Enabled Bit[26]" "Disabled,Enabled" bitfld.long 0x00 24. " IF3UPDATEEN[25] ,IF3 Update Enabled Bit[25]" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " IF3UPDATEEN[24] ,IF3 Update Enabled Bit[24]" "Disabled,Enabled" bitfld.long 0x00 22. " IF3UPDATEEN[23] ,IF3 Update Enabled Bit[23]" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " IF3UPDATEEN[22] ,IF3 Update Enabled Bit[22]" "Disabled,Enabled" bitfld.long 0x00 20. " IF3UPDATEEN[21] ,IF3 Update Enabled Bit[21]" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " IF3UPDATEEN[20] ,IF3 Update Enabled Bit[20]" "Disabled,Enabled" bitfld.long 0x00 18. " IF3UPDATEEN[19] ,IF3 Update Enabled Bit[19]" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " IF3UPDATEEN[18] ,IF3 Update Enabled Bit[18]" "Disabled,Enabled" bitfld.long 0x00 16. " IF3UPDATEEN[17] ,IF3 Update Enabled Bit[17]" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " IF3UPDATEEN[16] ,IF3 Update Enabled Bit[16]" "Disabled,Enabled" bitfld.long 0x00 14. " IF3UPDATEEN[15] ,IF3 Update Enabled Bit[15]" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " IF3UPDATEEN[14] ,IF3 Update Enabled Bit[14]" "Disabled,Enabled" bitfld.long 0x00 12. " IF3UPDATEEN[13] ,IF3 Update Enabled Bit[13]" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " IF3UPDATEEN[12] ,IF3 Update Enabled Bit[12]" "Disabled,Enabled" bitfld.long 0x00 10. " IF3UPDATEEN[11] ,IF3 Update Enabled Bit[11]" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " IF3UPDATEEN[10] ,IF3 Update Enabled Bit[10]" "Disabled,Enabled" bitfld.long 0x00 8. " IF3UPDATEEN[9] ,IF3 Update Enabled Bit[9]" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " IF3UPDATEEN[8] ,IF3 Update Enabled Bit[8]" "Disabled,Enabled" bitfld.long 0x00 6. " IF3UPDATEEN[7] ,IF3 Update Enabled Bit[7]" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " IF3UPDATEEN[6] ,IF3 Update Enabled Bit[6]" "Disabled,Enabled" bitfld.long 0x00 4. " IF3UPDATEEN[5] ,IF3 Update Enabled Bit[5]" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " IF3UPDATEEN[4] ,IF3 Update Enabled Bit[4]" "Disabled,Enabled" bitfld.long 0x00 2. " IF3UPDATEEN[3] ,IF3 Update Enabled Bit[3]" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " IF3UPDATEEN[2] ,IF3 Update Enabled Bit[2]" "Disabled,Enabled" bitfld.long 0x00 0. " IF3UPDATEEN[1] ,IF3 Update Enabled Bit[1]" "Disabled,Enabled" group.long 0x164++0x3 line.long 0x0 "IF3UPD34,Update enable 3-4 Register" bitfld.long 0x00 31. " IF3UPDATEEN[64] ,IF3 Update Enabled Bit[64]" "Disabled,Enabled" bitfld.long 0x00 30. " IF3UPDATEEN[63] ,IF3 Update Enabled Bit[63]" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " IF3UPDATEEN[62] ,IF3 Update Enabled Bit[62]" "Disabled,Enabled" bitfld.long 0x00 28. " IF3UPDATEEN[61] ,IF3 Update Enabled Bit[61]" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " IF3UPDATEEN[60] ,IF3 Update Enabled Bit[60]" "Disabled,Enabled" bitfld.long 0x00 26. " IF3UPDATEEN[59] ,IF3 Update Enabled Bit[59]" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " IF3UPDATEEN[58] ,IF3 Update Enabled Bit[58]" "Disabled,Enabled" bitfld.long 0x00 24. " IF3UPDATEEN[57] ,IF3 Update Enabled Bit[57]" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " IF3UPDATEEN[56] ,IF3 Update Enabled Bit[56]" "Disabled,Enabled" bitfld.long 0x00 22. " IF3UPDATEEN[55] ,IF3 Update Enabled Bit[55]" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " IF3UPDATEEN[54] ,IF3 Update Enabled Bit[54]" "Disabled,Enabled" bitfld.long 0x00 20. " IF3UPDATEEN[53] ,IF3 Update Enabled Bit[53]" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " IF3UPDATEEN[52] ,IF3 Update Enabled Bit[52]" "Disabled,Enabled" bitfld.long 0x00 18. " IF3UPDATEEN[51] ,IF3 Update Enabled Bit[51]" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " IF3UPDATEEN[50] ,IF3 Update Enabled Bit[50]" "Disabled,Enabled" bitfld.long 0x00 16. " IF3UPDATEEN[49] ,IF3 Update Enabled Bit[49]" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " IF3UPDATEEN[48] ,IF3 Update Enabled Bit[48]" "Disabled,Enabled" bitfld.long 0x00 14. " IF3UPDATEEN[47] ,IF3 Update Enabled Bit[47]" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " IF3UPDATEEN[46] ,IF3 Update Enabled Bit[46]" "Disabled,Enabled" bitfld.long 0x00 12. " IF3UPDATEEN[45] ,IF3 Update Enabled Bit[45]" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " IF3UPDATEEN[44] ,IF3 Update Enabled Bit[44]" "Disabled,Enabled" bitfld.long 0x00 10. " IF3UPDATEEN[43] ,IF3 Update Enabled Bit[43]" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " IF3UPDATEEN[42] ,IF3 Update Enabled Bit[42]" "Disabled,Enabled" bitfld.long 0x00 8. " IF3UPDATEEN[41] ,IF3 Update Enabled Bit[41]" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " IF3UPDATEEN[40] ,IF3 Update Enabled Bit[40]" "Disabled,Enabled" bitfld.long 0x00 6. " IF3UPDATEEN[39] ,IF3 Update Enabled Bit[39]" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " IF3UPDATEEN[38] ,IF3 Update Enabled Bit[38]" "Disabled,Enabled" bitfld.long 0x00 4. " IF3UPDATEEN[37] ,IF3 Update Enabled Bit[37]" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " IF3UPDATEEN[36] ,IF3 Update Enabled Bit[36]" "Disabled,Enabled" bitfld.long 0x00 2. " IF3UPDATEEN[35] ,IF3 Update Enabled Bit[35]" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " IF3UPDATEEN[34] ,IF3 Update Enabled Bit[34]" "Disabled,Enabled" bitfld.long 0x00 0. " IF3UPDATEEN[33] ,IF3 Update Enabled Bit[33]" "Disabled,Enabled" group.long 0x168++0x3 line.long 0x0 "IF3UPD56,Update enable 5-6 Register" bitfld.long 0x00 31. " IF3UPDATEEN[96] ,IF3 Update Enabled Bit[96]" "Disabled,Enabled" bitfld.long 0x00 30. " IF3UPDATEEN[95] ,IF3 Update Enabled Bit[95]" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " IF3UPDATEEN[94] ,IF3 Update Enabled Bit[94]" "Disabled,Enabled" bitfld.long 0x00 28. " IF3UPDATEEN[93] ,IF3 Update Enabled Bit[93]" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " IF3UPDATEEN[92] ,IF3 Update Enabled Bit[92]" "Disabled,Enabled" bitfld.long 0x00 26. " IF3UPDATEEN[91] ,IF3 Update Enabled Bit[91]" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " IF3UPDATEEN[90] ,IF3 Update Enabled Bit[90]" "Disabled,Enabled" bitfld.long 0x00 24. " IF3UPDATEEN[89] ,IF3 Update Enabled Bit[89]" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " IF3UPDATEEN[88] ,IF3 Update Enabled Bit[88]" "Disabled,Enabled" bitfld.long 0x00 22. " IF3UPDATEEN[87] ,IF3 Update Enabled Bit[87]" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " IF3UPDATEEN[86] ,IF3 Update Enabled Bit[86]" "Disabled,Enabled" bitfld.long 0x00 20. " IF3UPDATEEN[85] ,IF3 Update Enabled Bit[85]" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " IF3UPDATEEN[84] ,IF3 Update Enabled Bit[84]" "Disabled,Enabled" bitfld.long 0x00 18. " IF3UPDATEEN[83] ,IF3 Update Enabled Bit[83]" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " IF3UPDATEEN[82] ,IF3 Update Enabled Bit[82]" "Disabled,Enabled" bitfld.long 0x00 16. " IF3UPDATEEN[81] ,IF3 Update Enabled Bit[81]" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " IF3UPDATEEN[80] ,IF3 Update Enabled Bit[80]" "Disabled,Enabled" bitfld.long 0x00 14. " IF3UPDATEEN[79] ,IF3 Update Enabled Bit[79]" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " IF3UPDATEEN[78] ,IF3 Update Enabled Bit[78]" "Disabled,Enabled" bitfld.long 0x00 12. " IF3UPDATEEN[77] ,IF3 Update Enabled Bit[77]" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " IF3UPDATEEN[76] ,IF3 Update Enabled Bit[76]" "Disabled,Enabled" bitfld.long 0x00 10. " IF3UPDATEEN[75] ,IF3 Update Enabled Bit[75]" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " IF3UPDATEEN[74] ,IF3 Update Enabled Bit[74]" "Disabled,Enabled" bitfld.long 0x00 8. " IF3UPDATEEN[73] ,IF3 Update Enabled Bit[73]" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " IF3UPDATEEN[72] ,IF3 Update Enabled Bit[72]" "Disabled,Enabled" bitfld.long 0x00 6. " IF3UPDATEEN[71] ,IF3 Update Enabled Bit[71]" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " IF3UPDATEEN[70] ,IF3 Update Enabled Bit[70]" "Disabled,Enabled" bitfld.long 0x00 4. " IF3UPDATEEN[69] ,IF3 Update Enabled Bit[69]" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " IF3UPDATEEN[68] ,IF3 Update Enabled Bit[68]" "Disabled,Enabled" bitfld.long 0x00 2. " IF3UPDATEEN[67] ,IF3 Update Enabled Bit[67]" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " IF3UPDATEEN[66] ,IF3 Update Enabled Bit[66]" "Disabled,Enabled" bitfld.long 0x00 0. " IF3UPDATEEN[65] ,IF3 Update Enabled Bit[65]" "Disabled,Enabled" group.long 0x16C++0x3 line.long 0x0 "IF3UPD78,Update enable 7-8 Register" bitfld.long 0x00 31. " IF3UPDATEEN[128] ,IF3 Update Enabled Bit[128]" "Disabled,Enabled" bitfld.long 0x00 30. " IF3UPDATEEN[127] ,IF3 Update Enabled Bit[127]" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " IF3UPDATEEN[126] ,IF3 Update Enabled Bit[126]" "Disabled,Enabled" bitfld.long 0x00 28. " IF3UPDATEEN[125] ,IF3 Update Enabled Bit[125]" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " IF3UPDATEEN[124] ,IF3 Update Enabled Bit[124]" "Disabled,Enabled" bitfld.long 0x00 26. " IF3UPDATEEN[123] ,IF3 Update Enabled Bit[123]" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " IF3UPDATEEN[122] ,IF3 Update Enabled Bit[122]" "Disabled,Enabled" bitfld.long 0x00 24. " IF3UPDATEEN[121] ,IF3 Update Enabled Bit[121]" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " IF3UPDATEEN[120] ,IF3 Update Enabled Bit[120]" "Disabled,Enabled" bitfld.long 0x00 22. " IF3UPDATEEN[119] ,IF3 Update Enabled Bit[119]" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " IF3UPDATEEN[118] ,IF3 Update Enabled Bit[118]" "Disabled,Enabled" bitfld.long 0x00 20. " IF3UPDATEEN[117] ,IF3 Update Enabled Bit[117]" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " IF3UPDATEEN[116] ,IF3 Update Enabled Bit[116]" "Disabled,Enabled" bitfld.long 0x00 18. " IF3UPDATEEN[115] ,IF3 Update Enabled Bit[115]" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " IF3UPDATEEN[114] ,IF3 Update Enabled Bit[114]" "Disabled,Enabled" bitfld.long 0x00 16. " IF3UPDATEEN[113] ,IF3 Update Enabled Bit[113]" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " IF3UPDATEEN[112] ,IF3 Update Enabled Bit[112]" "Disabled,Enabled" bitfld.long 0x00 14. " IF3UPDATEEN[111] ,IF3 Update Enabled Bit[111]" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " IF3UPDATEEN[110] ,IF3 Update Enabled Bit[110]" "Disabled,Enabled" bitfld.long 0x00 12. " IF3UPDATEEN[109] ,IF3 Update Enabled Bit[109]" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " IF3UPDATEEN[108] ,IF3 Update Enabled Bit[108]" "Disabled,Enabled" bitfld.long 0x00 10. " IF3UPDATEEN[107] ,IF3 Update Enabled Bit[107]" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " IF3UPDATEEN[106] ,IF3 Update Enabled Bit[106]" "Disabled,Enabled" bitfld.long 0x00 8. " IF3UPDATEEN[105] ,IF3 Update Enabled Bit[105]" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " IF3UPDATEEN[104] ,IF3 Update Enabled Bit[104]" "Disabled,Enabled" bitfld.long 0x00 6. " IF3UPDATEEN[103] ,IF3 Update Enabled Bit[103]" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " IF3UPDATEEN[102] ,IF3 Update Enabled Bit[102]" "Disabled,Enabled" bitfld.long 0x00 4. " IF3UPDATEEN[101] ,IF3 Update Enabled Bit[101]" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " IF3UPDATEEN[100] ,IF3 Update Enabled Bit[100]" "Disabled,Enabled" bitfld.long 0x00 2. " IF3UPDATEEN[99] ,IF3 Update Enabled Bit[99]" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " IF3UPDATEEN[98] ,IF3 Update Enabled Bit[98]" "Disabled,Enabled" bitfld.long 0x00 0. " IF3UPDATEEN[97] ,IF3 Update Enabled Bit[97]" "Disabled,Enabled" tree.end width 6. group.long 0x1E0++0x3 line.long 0x0 "TIOC,TX IO Control Register" bitfld.long 0x00 18. " PU ,CAN_TX Pullup/Pulldown select" "Pulldown,Pullup" bitfld.long 0x00 17. " PD ,CAN_TX pull disable" "Active,Disabled" bitfld.long 0x00 16. " OD ,CAN_TX open drain enable" "Push/pull,Open drain" textline " " bitfld.long 0x00 3. " FUNC ,CAN_TX function" "GIO,Functional" bitfld.long 0x00 2. " DIR ,CAN_TX data direction" "Input,Output" bitfld.long 0x00 1. " OUT ,CAN_TX data out write" "Low,High" textline " " bitfld.long 0x00 0. " IN ,CAN_TX data in" "Low,High" group.long 0x1E4++0x3 line.long 0x0 "RIOC,RX IO Control Register" bitfld.long 0x00 18. " PU ,CAN_TX Pullup/Pulldown select" "Pulldown,Pullup" bitfld.long 0x00 17. " PD ,CAN_TX pull disable" "Active,Disabled" bitfld.long 0x00 16. " OD ,CAN_TX open drain enable" "Push/pull,Open drain" textline " " bitfld.long 0x00 3. " FUNC ,CAN_TX function" "GIO,Functional" bitfld.long 0x00 2. " DIR ,CAN_TX data direction" "Input,Output" bitfld.long 0x00 1. " OUT ,CAN_TX data out write" "Low,High" textline " " bitfld.long 0x00 0. " IN ,CAN_TX data in" "Low,High" width 11. tree.end endif tree.end tree "SPI (Serial Peripheral Interface)" tree "MIBSPI1" base ad:0xFFF7F400 width 6. group.long 0x00++0x03 line.long 0x00 "GCR0,Global Control Register 0" bitfld.long 0x00 0. " NRESET ,This is the reset bit for the module" "Reset,No reset" if (((d.l(ad:0xFFF7F400+0x04))&0x03)==0x03) group.long 0x04++0x03 line.long 0x00 "GCR1,Global Control Register 1" bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI pin direction determination" "Input/output,Output/input" bitfld.long 0x00 24. " SPIEN ,SPI enable" "Not active,Active" bitfld.long 0x00 16. " LOOP_BACK ,Internal Loop-back test mode" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " POWERDOWN ,SPI state machines power down state enable" "Active,Power down" bitfld.long 0x00 1. " CLKMOD ,Clock mode" "External,Internal" elif (((d.l(ad:0xFFF7F400+0x04))&0x03)==0x02) group.long 0x04++0x03 line.long 0x00 "GCR1,Global Control Register 1" bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI pin direction determination" "Input/output,Output/input" bitfld.long 0x00 24. " SPIEN ,SPI enable" "Not active,Active" bitfld.long 0x00 8. " POWERDOWN ,SPI state machines power down state enable" "Active,Power down" textline " " bitfld.long 0x00 1. " CLKMOD ,Clock mode" "External,Internal" elif (((d.l(ad:0xFFF7F400+0x04))&0x03)==0x01) group.long 0x04++0x03 line.long 0x00 "GCR1,Global Control Register 1" bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI pin direction determination" "Input/output,Output/input" bitfld.long 0x00 24. " SPIEN ,SPI enable" "Not active,Active" bitfld.long 0x00 8. " POWERDOWN ,SPI state machines power down state enable" "Active,Power down" textline " " bitfld.long 0x00 1. " CLKMOD ,Clock mode" "External,Internal" else group.long 0x04++0x03 line.long 0x00 "GCR1,Global Control Register 1" bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI pin direction determination" "Input/output,Output/input" bitfld.long 0x00 24. " SPIEN ,SPI enable" "Not active,Active" bitfld.long 0x00 8. " POWERDOWN ,SPI state machines power down state enable" "Active,Power down" textline " " bitfld.long 0x00 1. " CLKMOD ,Clock mode" "External,Internal" endif if (((d.l(ad:0xFFF7F400+0x04))&0x01)==0x01) group.long 0x08++0x03 line.long 0x00 "INT0,Interrupt Register" bitfld.long 0x00 24. " ENABLE_HIGHZ ,/SPIENA pin High-z enable" "Disabled,Enabled" textline " " sif (cpu()!="RM42L432") bitfld.long 0x00 16. " DMA_REQ_EN ,DMA request enable" "Not used,Generated" endif textline " " bitfld.long 0x00 9. " TXINTENA ,Transmit interrupt enable" "Not generated,Generated" bitfld.long 0x00 8. " RXINTENA ,Receive interrupt enable" "Not generated,Generated" textline " " bitfld.long 0x00 6. " RXOVRNINTENA ,Overrun interrupt enable" "Not generated,Generated" bitfld.long 0x00 4. " BITERRENA ,Enables interrupt on bit error" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " DESYNCENA ,Enables interrupt on De-synchronized slave" "Disabled,Enabled" bitfld.long 0x00 2. " PARERRENA ,Enables interrupt on parity error" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " TIMEOUTENA ,Enables interrupt on ENA signal Time-out" "Disabled,Enabled" bitfld.long 0x00 0. " DLEN_ERR_ENA ,Data length error interrupt enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "INT0,Interrupt Register" bitfld.long 0x00 24. " ENABLE_HIGHZ ,/SPIENA pin High-z enable" "Disabled,Enabled" textline " " sif (cpu()!="RM42L432") bitfld.long 0x00 16. " DMA_REQ_EN ,DMA request enable" "Not used,Generated" endif textline " " bitfld.long 0x00 9. " TXINTENA ,Transmit interrupt enable" "Not generated,Generated" bitfld.long 0x00 8. " RXINTENA ,Receive interrupt enable" "Not generated,Generated" textline " " bitfld.long 0x00 6. " RXOVRNINTENA ,Overrun interrupt enable" "Not generated,Generated" bitfld.long 0x00 4. " BITERRENA ,Enables interrupt on bit error" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " PARERRENA ,Enables interrupt on parity error" "Disabled,Enabled" bitfld.long 0x00 1. " TIMEOUTENA ,Enables interrupt on ENA signal Time-out" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " DLEN_ERR_ENA ,Data length error interrupt enable" "Disabled,Enabled" endif if (((d.l(ad:0xFFF7F400+0x04))&0x01)==0x01) group.long 0x0C++0x03 line.long 0x00 "LVL,Interrupt Level Register" bitfld.long 0x00 9. " TXINTLVL ,Transmit interrupt level" "INT0,INT1" bitfld.long 0x00 8. " RXINTLVL ,Receive interrupt level" "INT0,INT1" bitfld.long 0x00 6. " RXOVRNINTLVL ,Receive overrun interrupt level" "INT0,INT1" textline " " bitfld.long 0x00 4. " BITERRLVL ,Bit error interrupt level" "INT0,INT1" bitfld.long 0x00 3. " DESYNCLVL ,De-synchronized slave interrupt level" "INT0,INT1" bitfld.long 0x00 2. " PARERRLVL ,Parity error interrupt level" "INT0,INT1" textline " " bitfld.long 0x00 1. " TIMEOUTLVL ,/SPIENA pin Time-out interrupt level" "INT0,INT1" bitfld.long 0x00 0. " DLEN_ERR_LVL ,Data length error interrupt enable level" "INT0,INT1" else group.long 0x0C++0x03 line.long 0x00 "LVL,Interrupt Level Register" bitfld.long 0x00 9. " TXINTLVL ,Transmit interrupt level" "INT0,INT1" bitfld.long 0x00 8. " RXINTLVL ,Receive interrupt level" "INT0,INT1" bitfld.long 0x00 6. " RXOVRNINTLVL ,Receive overrun interrupt level" "INT0,INT1" textline " " bitfld.long 0x00 4. " BITERRLVL ,Bit error interrupt level" "INT0,INT1" bitfld.long 0x00 2. " PARERRLVL ,Parity error interrupt level" "INT0,INT1" bitfld.long 0x00 1. " TIMEOUTLVL ,/SPIENA pin Time-out interrupt level" "INT0,INT1" textline " " bitfld.long 0x00 0. " DLEN_ERR_LVL ,Data length error interrupt enable level" "INT0,INT1" endif if (((d.l(ad:0xFFF7F400+0x04))&0x01)==0x01) group.long 0x10++0x03 line.long 0x00 "FLG,Flag Register" bitfld.long 0x00 24. " BUF_INIT_ACTIVE ,Multibuffer initialization active" "Finished,Not finished" bitfld.long 0x00 9. " TXINTFLG ,Transmitter empty interrupt flag" "Full,Empty" textline " " eventfld.long 0x00 8. " RXINTFLG ,Receiver full interrupt flag" "Empty,Full" eventfld.long 0x00 6. " RXOVRNINTFLG ,Receiver overrun flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 4. " BITERRFLG ,Internal transmit data and transmitted data mismatch" "Not occurred,Occurred" eventfld.long 0x00 3. " DESYNCFLG ,Slave device De-Synchronization" "Not detected,Detected" textline " " eventfld.long 0x00 2. " PARITYERRFLG ,Parity error flag" "Not detected,Detected" eventfld.long 0x00 1. " TIMEOUTFLG ,Time-out due to Non-activation of ENA signal" "Not occurred,Occurred" textline " " eventfld.long 0x00 0. " DLEN_ERR_FLG ,Data length error flag" "Not occurred,Occurred" else group.long 0x10++0x03 line.long 0x00 "FLG,Flag Register" bitfld.long 0x00 24. " BUF_INIT_ACTIVE ,Multibuffer initialization active" "Not completed,Completed" bitfld.long 0x00 9. " TXINTFLG ,Transmitter empty interrupt flag" "No empty,Empty" textline " " eventfld.long 0x00 8. " RXINTFLG ,Receiver full interrupt flag" "No full,Full" eventfld.long 0x00 6. " RXOVRNINTFLG ,Receiver overrun flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 4. " BITERRFLG ,Internal transmit data and transmitted data mismatch" "Not occurred,Occurred" eventfld.long 0x00 2. " PARITYERRFLG ,Parity error flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 1. " TIMEOUTFLG ,Time-out due to Non-activation of ENA signal" "Not occurred,Occurred" eventfld.long 0x00 0. " DLEN_ERR_FLG ,Data length error flag" "Not occurred,Occurred" endif width 13. tree "SPI Pin Control Registers" tree "SPI Pin Control Registers 0-5" group.long 0x14++0x03 line.long 0x00 "PC0,Pin Control Register 0" bitfld.long 0x00 31. " SOMIFUN7 ,Slave out master in function 7" "GPIO,Spi/mibspi" bitfld.long 0x00 30. " SOMIFUN6 ,Slave out master in function 6" "GPIO,Spi/mibspi" bitfld.long 0x00 29. " SOMIFUN5 ,Slave out master in function 5" "GPIO,Spi/mibspi" textline " " bitfld.long 0x00 28. " SOMIFUN4 ,Slave out master in function 4" "GPIO,Spi/mibspi" bitfld.long 0x00 27. " SOMIFUN3 ,Slave out master in function 3" "GPIO,Spi/mibspi" bitfld.long 0x00 26. " SOMIFUN2 ,Slave out master in function 2" "GPIO,Spi/mibspi" textline " " bitfld.long 0x00 25. " SOMIFUN1 ,Slave out master in function 1" "GPIO,Spi/mibspi" bitfld.long 0x00 24. " SOMIFUN0 ,Slave out master in function 0" "GPIO,Spi/mibspi" bitfld.long 0x00 23. " SIMOFUN7 ,Slave in master out function 7" "GPIO,Spi/mibspi" textline " " bitfld.long 0x00 22. " SIMOFUN6 ,Slave in master out function 6" "GPIO,Spi/mibspi" bitfld.long 0x00 21. " SIMOFUN5 ,Slave in master out function 5" "GPIO,Spi/mibspi" bitfld.long 0x00 20. " SIMOFUN4 ,Slave in master out function 4" "GPIO,Spi/mibspi" textline " " bitfld.long 0x00 19. " SIMOFUN3 ,Slave in master out function 3" "GPIO,Spi/mibspi" bitfld.long 0x00 18. " SIMOFUN2 ,Slave in master out function 2" "GPIO,Spi/mibspi" bitfld.long 0x00 17. " SIMOFUN1 ,Slave in master out function 1" "GPIO,Spi/mibspi" textline " " bitfld.long 0x00 16. " SIMOFUN0 ,Slave in master out function 0" "GPIO,Spi/mibspi" bitfld.long 0x00 11. " SOMIFUN0 ,Slave out master in function" "GPIO,Spi/mibspi" bitfld.long 0x00 10. " SIMOFUN0 ,Slave in master out function" "GPIO,Spi/mibspi" textline " " bitfld.long 0x00 9. " CLKFUN ,Spi/mibspi clock function" "GPIO,Spi/mibspi" bitfld.long 0x00 8. " ENAFUN ,/SPIENA function" "GPIO,Spi/mibspi" bitfld.long 0x00 7. " SCSFUN7 ,/SPISCS7 function" "GPIO,SPI" textline " " bitfld.long 0x00 6. " SCSFUN6 ,/SPISCS6 function" "GPIO,SPI" bitfld.long 0x00 5. " SCSFUN5 ,/SPISCS5 function" "GPIO,SPI" bitfld.long 0x00 4. " SCSFUN4 ,/SPISCS4 function" "GPIO,SPI" textline " " bitfld.long 0x00 3. " SCSFUN3 ,/SPISCS3 function" "GPIO,SPI" bitfld.long 0x00 2. " SCSFUN2 ,/SPISCS2 function" "GPIO,SPI" bitfld.long 0x00 1. " SCSFUN1 ,/SPISCS1 function" "GPIO,SPI" textline " " bitfld.long 0x00 0. " SCSFUN0 ,/SPISCS0 function" "GPIO,SPI" group.long 0x18++0x03 line.long 0x00 "PC1,Pin Control Register 1" bitfld.long 0x00 31. " SOMIDIR7 ,SPISOMI7 direction" "Input,Output" bitfld.long 0x00 30. " SOMIDIR6 ,SPISOMI6 direction" "Input,Output" bitfld.long 0x00 29. " SOMIDIR5 ,SPISOMI5 direction" "Input,Output" textline " " bitfld.long 0x00 28. " SOMIDIR4 ,SPISOMI4 direction" "Input,Output" bitfld.long 0x00 27. " SOMIDIR3 ,SPISOMI3 direction" "Input,Output" bitfld.long 0x00 26. " SOMIDIR2 ,SPISOMI2 direction" "Input,Output" textline " " bitfld.long 0x00 25. " SOMIDIR1 ,SPISOMI1 direction" "Input,Output" bitfld.long 0x00 24. " SOMIDIR0 ,SPISOMI0 direction" "Input,Output" bitfld.long 0x00 23. " SIMODIR7 ,SPISIMO7 direction" "Input,Output" textline " " bitfld.long 0x00 22. " SIMODIR6 ,SPISIMO6 direction" "Input,Output" bitfld.long 0x00 21. " SIMODIR5 ,SPISIMO5 direction" "Input,Output" bitfld.long 0x00 20. " SIMODIR4 ,SPISIMO4 direction" "Input,Output" textline " " bitfld.long 0x00 19. " SIMODIR3 ,SPISIMO3 direction" "Input,Output" bitfld.long 0x00 18. " SIMODIR2 ,SPISIMO2 direction" "Input,Output" bitfld.long 0x00 17. " SIMODIR1 ,SPISIMO1 direction" "Input,Output" textline " " bitfld.long 0x00 16. " SIMODIR0 ,SPISIMO0 direction" "Input,Output" bitfld.long 0x00 11. " SOMIDIR0 ,SPISOMI0 direction" "Input,Output" bitfld.long 0x00 10. " SIMODIR0 ,SPISIMO0 direction" "Input,Output" textline " " bitfld.long 0x00 9. " CLKDIR ,SPICLK direction" "Input,Output" bitfld.long 0x00 8. " ENADIR ,/SPIENA direction" "Input,Output" bitfld.long 0x00 7. " SCSDIR7 ,/SPISCS7 direction" "Input,Output" textline " " bitfld.long 0x00 6. " SCSDIR6 ,/SPISCS6 direction" "Input,Output" bitfld.long 0x00 5. " SCSDIR5 ,/SPISCS5 direction" "Input,Output" bitfld.long 0x00 4. " SCSDIR4 ,/SPISCS4 direction" "Input,Output" textline " " bitfld.long 0x00 3. " SCSDIR3 ,/SPISCS3 direction" "Input,Output" bitfld.long 0x00 2. " SCSDIR2 ,/SPISCS2 direction" "Input,Output" bitfld.long 0x00 1. " SCSDIR1 ,/SPISCS1 direction" "Input,Output" textline " " bitfld.long 0x00 0. " SCSDIR0 ,/SPISCS0 direction" "Input,Output" rgroup.long 0x1C++0x03 line.long 0x00 "PC2,Pin Control Register 2" bitfld.long 0x00 31. " SOMIDIN7 ,SPISOMI7 data in" "Low,High" bitfld.long 0x00 30. " SOMIDIN6 ,SPISOMI6 data in" "Low,High" bitfld.long 0x00 29. " SOMIDIN5 ,SPISOMI5 data in" "Low,High" textline " " bitfld.long 0x00 28. " SOMIDIN4 ,SPISOMI4 data in" "Low,High" bitfld.long 0x00 27. " SOMIDIN3 ,SPISOMI3 data in" "Low,High" bitfld.long 0x00 26. " SOMIDIN2 ,SPISOMI2 data in" "Low,High" textline " " bitfld.long 0x00 25. " SOMIDIN1 ,SPISOMI1 data in" "Low,High" bitfld.long 0x00 24. " SOMIDIN0 ,SPISOMI0 data in" "Low,High" bitfld.long 0x00 23. " SIMODIN7 ,SPISIMO7 data in" "Low,High" textline " " bitfld.long 0x00 22. " SIMODIN6 ,SPISIMO6 data in" "Low,High" bitfld.long 0x00 21. " SIMODIN5 ,SPISIMO5 data in" "Low,High" bitfld.long 0x00 20. " SIMODIN4 ,SPISIMO4 data in" "Low,High" textline " " bitfld.long 0x00 19. " SIMODIN3 ,SPISIMO3 data in" "Low,High" bitfld.long 0x00 18. " SIMODIN2 ,SPISIMO2 data in" "Low,High" bitfld.long 0x00 17. " SIMODIN1 ,SPISIMO1 data in" "Low,High" textline " " bitfld.long 0x00 16. " SIMODIN0 ,SPISIMO0 data in" "Low,High" bitfld.long 0x00 11. " SOMIDIN0 ,SPISOMI0 data in" "Low,High" bitfld.long 0x00 10. " SIMODIN0 ,SPISIMO0 data in" "Low,High" textline " " bitfld.long 0x00 9. " CLKDIN ,Clock data in" "Low,High" bitfld.long 0x00 8. " ENADIN ,/SPIENA data in" "Low,High" bitfld.long 0x00 7. " SCSDIN7 ,SPISCS7 data in" "Low,High" textline " " bitfld.long 0x00 6. " SCSDIN6 ,SPISCS6 data in" "Low,High" bitfld.long 0x00 5. " SCSDIN5 ,SPISCS5 data in" "Low,High" bitfld.long 0x00 4. " SCSDIN4 ,SPISCS4 data in" "Low,High" textline " " bitfld.long 0x00 3. " SCSDIN3 ,SPISCS3 data in" "Low,High" bitfld.long 0x00 2. " SCSDIN2 ,SPISCS2 data in" "Low,High" bitfld.long 0x00 1. " SCSDIN1 ,SPISCS1 data in" "Low,High" textline " " bitfld.long 0x00 0. " SCSDIN0 ,SPISCS0 data in" "Low,High" group.long 0x20++0x0B line.long 0x00 "PC3,Pin Control Register 3" bitfld.long 0x00 31. " SOMIDOUT7 ,SPISOMI7 dataout write" "Low,High" bitfld.long 0x00 30. " SOMIDOUT6 ,SPISOMI6 dataout write" "Low,High" textline " " bitfld.long 0x00 29. " SOMIDOUT5 ,SPISOMI5 dataout write" "Low,High" bitfld.long 0x00 28. " SOMIDOUT4 ,SPISOMI4 dataout write" "Low,High" textline " " bitfld.long 0x00 27. " SOMIDOUT3 ,SPISOMI3 dataout write" "Low,High" bitfld.long 0x00 26. " SOMIDOUT2 ,SPISOMI2 dataout write" "Low,High" textline " " bitfld.long 0x00 25. " SOMIDOUT1 ,SPISOMI1 dataout write" "Low,High" bitfld.long 0x00 24. " SOMIDOUT0 ,SPISOMI0 dataout write" "Low,High" textline " " bitfld.long 0x00 23. " SIMODOUT7 ,SPISIMO7 dataout write" "Low,High" bitfld.long 0x00 22. " SIMODOUT6 ,SPISIMO6 dataout write" "Low,High" textline " " bitfld.long 0x00 21. " SIMODOUT5 ,SPISIMO5 dataout write" "Low,High" bitfld.long 0x00 20. " SIMODOUT4 ,SPISIMO4 dataout write" "Low,High" textline " " bitfld.long 0x00 19. " SIMODOUT3 ,SPISIMO3 dataout write" "Low,High" bitfld.long 0x00 18. " SIMODOUT2 ,SPISIMO2 dataout write" "Low,High" textline " " bitfld.long 0x00 17. " SIMODOUT1 ,SPISIMO1 dataout write" "Low,High" bitfld.long 0x00 16. " SIMODOUT0 ,SPISIMO0 dataout write" "Low,High" textline " " bitfld.long 0x00 11. " SOMIDOUT0 ,SPISOMI0 dataout write" "Low,High" bitfld.long 0x00 10. " SIMODOUT0 ,SPISIMO0 dataout write" "Low,High" textline " " bitfld.long 0x00 9. " CLKDOUT ,SPICLK dataout write" "Low,High" bitfld.long 0x00 8. " ENADOUT ,/SPIENA dataout write" "Low,High" textline " " bitfld.long 0x00 7. " SCSDOUT7 ,SPISCS7 dataout write" "Low,High" bitfld.long 0x00 6. " SCSDOUT6 ,SPISCS6 dataout write" "Low,High" textline " " bitfld.long 0x00 5. " SCSDOUT5 ,SPISCS5 dataout write" "Low,High" bitfld.long 0x00 4. " SCSDOUT4 ,SPISCS4 dataout write" "Low,High" textline " " bitfld.long 0x00 3. " SCSDOUT3 ,SPISCS3 dataout write" "Low,High" bitfld.long 0x00 2. " SCSDOUT2 ,SPISCS2 dataout write" "Low,High" textline " " bitfld.long 0x00 1. " SCSDOUT1 ,SPISCS1 dataout write" "Low,High" bitfld.long 0x00 0. " SCSDOUT0 ,SPISCS0 dataout write" "Low,High" line.long 0x04 "PC4,Pin Control Register 4" bitfld.long 0x04 31. " SOMISET7 ,SPISOMI7 dataout set" "Not set,Set" bitfld.long 0x04 30. " SOMISET6 ,SPISOMI6 dataout set" "Not set,Set" textline " " bitfld.long 0x04 29. " SOMISET5 ,SPISOMI5 dataout set" "Not set,Set" bitfld.long 0x04 28. " SOMISET4 ,SPISOMI4 dataout set" "Not set,Set" textline " " bitfld.long 0x04 27. " SOMISET3 ,SPISOMI3 dataout set" "Not set,Set" bitfld.long 0x04 26. " SOMISET2 ,SPISOMI2 dataout set" "Not set,Set" textline " " bitfld.long 0x04 25. " SOMISET1 ,SPISOMI1 dataout set" "Not set,Set" bitfld.long 0x04 24. " SOMISET0 ,SPISOMI0 dataout set" "Not set,Set" textline " " bitfld.long 0x04 23. " SIMOSET7 ,SPISIMO7 dataout set" "Not set,Set" bitfld.long 0x04 22. " SIMOSET6 ,SPISIMO6 dataout set" "Not set,Set" textline " " bitfld.long 0x04 21. " SIMOSET5 ,SPISIMO5 dataout set" "Not set,Set" bitfld.long 0x04 20. " SIMOSET4 ,SPISIMO4 dataout set" "Not set,Set" textline " " bitfld.long 0x04 19. " SIMOSET3 ,SPISIMO3 dataout set" "Not set,Set" bitfld.long 0x04 18. " SIMOSET2 ,SPISIMO2 dataout set" "Not set,Set" textline " " bitfld.long 0x04 17. " SIMOSET1 ,SPISIMO1 dataout set" "Not set,Set" bitfld.long 0x04 16. " SIMOSET0 ,SPISIMO0 dataout set" "Not set,Set" textline " " bitfld.long 0x04 11. " SOMISET0 ,SPISOMI0 dataout set" "Not set,Set" bitfld.long 0x04 10. " SIMOSET0 ,SPISIMO0 dataout set" "Not set,Set" textline " " bitfld.long 0x04 9. " CLKSET ,SPICLK dataout set" "Not set,Set" bitfld.long 0x04 8. " ENASET ,/SPIENA dataout set" "Not set,Set" textline " " bitfld.long 0x04 7. " SCSSET7 ,SPISCS7 dataout set" "Not set,Set" bitfld.long 0x04 6. " SCSSET6 ,SPISCS6 dataout set" "Not set,Set" textline " " bitfld.long 0x04 5. " SCSSET5 ,SPISCS5 dataout set" "Not set,Set" bitfld.long 0x04 4. " SCSSET4 ,SPISCS4 dataout set" "Not set,Set" textline " " bitfld.long 0x04 3. " SCSSET3 ,SPISCS3 dataout set" "Not set,Set" bitfld.long 0x04 2. " SCSSET2 ,SPISCS2 dataout set" "Not set,Set" textline " " bitfld.long 0x04 1. " SCSSET1 ,SPISCS1 dataout set" "Not set,Set" bitfld.long 0x04 0. " SCSSET0 ,SPISCS0 dataout set" "Not set,Set" line.long 0x08 "PC5,Pin Control Register 5" bitfld.long 0x08 31. " SOMICLR7 ,SPISOMI7 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 30. " SOMICLR6 ,SPISOMI6 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 29. " SOMICLR5 ,SPISOMI5 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 28. " SOMICLR4 ,SPISOMI4 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 27. " SOMICLR3 ,SPISOMI3 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 26. " SOMICLR2 ,SPISOMI2 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 25. " SOMICLR1 ,SPISOMI1 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 24. " SOMICLR0 ,SPISOMI0 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 23. " SIMOCLR7 ,SPISIMO7 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 22. " SIMOCLR6 ,SPISIMO6 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 21. " SIMOCLR5 ,SPISIMO5 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 20. " SIMOCLR4 ,SPISIMO4 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 19. " SIMOCLR3 ,SPISIMO3 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 18. " SIMOCLR2 ,SPISIMO2 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 17. " SIMOCLR1 ,SPISIMO1 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 16. " SIMOCLR0 ,SPISIMO0 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 11. " SOMICLR0 ,SPISOMI0 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 10. " SIMOCLR0 ,SPISIMO0 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 9. " CLKCLR ,SPICLK dataout clear" "Not cleared,Cleared" bitfld.long 0x08 8. " ENACLR ,/SPIENA dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 7. " SCSCLR7 ,SPISCS7 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 6. " SCSCLR6 ,SPISCS6 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 5. " SCSCLR5 ,SPISCS5 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 4. " SCSCLR4 ,SPISCS4 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 3. " SCSCLR3 ,SPISCS3 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 2. " SCSCLR2 ,SPISCS2 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 1. " SCSCLR1 ,SPISCS1 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 0. " SCSCLR0 ,SPISCS0 dataout clear" "Not cleared,Cleared" tree.end tree "SPI Pin Control Registers 6-8" group.long 0x2C++0x03 line.long 0x00 "PC6,Pin Control Register 1" bitfld.long 0x00 31. " SOMIPDR7 ,SPISOMI7 open drain enable" "High,Tri-stated" bitfld.long 0x00 30. " SOMIPDR6 ,SPISOMI6 open drain enable" "High,Tri-stated" bitfld.long 0x00 29. " SOMIPDR5 ,SPISOMI5 open drain enable" "High,Tri-stated" textline " " bitfld.long 0x00 28. " SOMIPDR4 ,SPISOMI4 open drain enable" "High,Tri-stated" bitfld.long 0x00 27. " SOMIPDR3 ,SPISOMI3 open drain enable" "High,Tri-stated" bitfld.long 0x00 26. " SOMIPDR2 ,SPISOMI2 open drain enable" "High,Tri-stated" textline " " bitfld.long 0x00 25. " SOMIPDR1 ,SPISOMI1 open drain enable" "High,Tri-stated" bitfld.long 0x00 24. " SOMIPDR0 ,SPISOMI0 open drain enable" "High,Tri-stated" bitfld.long 0x00 23. " SIMOPDR7 ,SPISIMO7 open drain enable" "High,Tri-stated" textline " " bitfld.long 0x00 22. " SIMOPDR6 ,SPISIMO6 open drain enable" "High,Tri-stated" bitfld.long 0x00 21. " SIMOPDR5 ,SPISIMO5 open drain enable" "High,Tri-stated" bitfld.long 0x00 20. " SIMOPDR4 ,SPISIMO4 open drain enable" "High,Tri-stated" textline " " bitfld.long 0x00 19. " SIMOPDR3 ,SPISIMO3 open drain enable" "High,Tri-stated" bitfld.long 0x00 18. " SIMOPDR2 ,SPISIMO2 open drain enable" "High,Tri-stated" bitfld.long 0x00 17. " SIMOPDR1 ,SPISIMO1 open drain enable" "High,Tri-stated" textline " " bitfld.long 0x00 16. " SIMOPDR0 ,SPISIMO0 open drain enable" "High,Tri-stated" bitfld.long 0x00 11. " SOMIPDR0 ,SPISOMI0 open drain enable" "High,Tri-stated" bitfld.long 0x00 10. " SIMOPDR0 ,SPISIMO0 open drain enable" "High,Tri-stated" textline " " bitfld.long 0x00 9. " CLKPDR ,SPICLK open drain enable" "High,Tri-stated" bitfld.long 0x00 8. " ENAPDR ,/SPIENA open drain enable" "High,Tri-stated" bitfld.long 0x00 7. " SCSPDR7 ,/SPISCS7 open drain" "High,Tri-stated" textline " " bitfld.long 0x00 6. " SCSPDR6 ,/SPISCS6 open drain" "High,Tri-stated" bitfld.long 0x00 5. " SCSPDR5 ,/SPISCS5 open drain" "High,Tri-stated" bitfld.long 0x00 4. " SCSPDR4 ,/SPISCS4 open drain" "High,Tri-stated" textline " " bitfld.long 0x00 3. " SCSPDR3 ,/SPISCS3 open drain" "High,Tri-stated" bitfld.long 0x00 2. " SCSPDR2 ,/SPISCS2 open drain" "High,Tri-stated" bitfld.long 0x00 1. " SCSPDR1 ,/SPISCS1 open drain" "High,Tri-stated" textline " " bitfld.long 0x00 0. " SCSPDR0 ,/SPISCS0 open drain" "High,Tri-stated" group.long 0x30++0x03 line.long 0x00 "PC7,Pin Control Register 7" bitfld.long 0x00 31. " SOMIPDIS7 ,SPISOMI7 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 30. " SOMIPDIS6 ,SPISOMI6 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 29. " SOMIPDIS5 ,SPISOMI5 pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 28. " SOMIPDIS4 ,SPISOMI4 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 27. " SOMIPDIS3 ,SPISOMI3 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 26. " SOMIPDIS2 ,SPISOMI2 pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 25. " SOMIPDIS1 ,SPISOMI1 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 24. " SOMIPDIS0 ,SPISOMI0 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 23. " SIMOPDIS7 ,SPISIMO7 pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 22. " SIMOPDIS6 ,SPISIMO6 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 21. " SIMOPDIS5 ,SPISIMO5 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 20. " SIMOPDIS4 ,SPISIMO4 pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 19. " SIMOPDIS3 ,SPISIMO3 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 18. " SIMOPDIS2 ,SPISIMO2 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 17. " SIMOPDIS1 ,SPISIMO1 pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 16. " SIMOPDIS0 ,SPISIMO0 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 11. " SOMIPDIS0 ,SPISOMI0 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 10. " SIMOPDIS0 ,SPISIMO pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 9. " CLKPDIS ,SPICLK pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 8. " ENAPDIS ,SPIENA pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 7. " SCSPDIS7 ,SPISCS7 pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 6. " SCSPDIS6 ,SPISCS6 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 5. " SCSPDIS5 ,SPISCS5 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 4. " SCSPDIS4 ,SPISCS4 pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 3. " SCSPDIS3 ,SPISCS3 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 2. " SCSPDIS2 ,SPISCS2 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 1. " SCSPDIS1 ,SPISCS1 pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 0. " SCSPDIS0 ,SPISCS0 pull control enable/disable" "Enabled,Disabled" group.long 0x34++0x03 line.long 0x00 "PC8,Pin Control Register 8" bitfld.long 0x00 31. " SOMIPSEL7 ,SPISOMI7 pull select" "Pull down,Pull up" bitfld.long 0x00 30. " SOMIPSEL6 ,SPISOMI6 pull select" "Pull down,Pull up" bitfld.long 0x00 29. " SOMIPSEL5 ,SPISOMI5 pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 28. " SOMIPSEL4 ,SPISOMI4 pull select" "Pull down,Pull up" bitfld.long 0x00 27. " SOMIPSEL3 ,SPISOMI3 pull select" "Pull down,Pull up" bitfld.long 0x00 26. " SOMIPSEL2 ,SPISOMI2 pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 25. " SOMIPSEL1 ,SPISOMI1 pull select" "Pull down,Pull up" bitfld.long 0x00 24. " SOMIPSEL0 ,SPISOMI0 pull select" "Pull down,Pull up" bitfld.long 0x00 23. " SIMOPSEL7 ,SPISIMO7 pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 22. " SIMOPSEL6 ,SPISIMO6 pull select" "Pull down,Pull up" bitfld.long 0x00 21. " SIMOPSEL5 ,SPISIMO5 pull select" "Pull down,Pull up" bitfld.long 0x00 20. " SIMOPSEL4 ,SPISIMO4 pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 19. " SIMOPSEL3 ,SPISIMO3 pull select" "Pull down,Pull up" bitfld.long 0x00 18. " SIMOPSEL2 ,SPISIMO2 pull select" "Pull down,Pull up" bitfld.long 0x00 17. " SIMOPSEL1 ,SPISIMO1 pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 16. " SIMOPSEL0 ,SPISIMO0 pull select" "Pull down,Pull up" bitfld.long 0x00 11. " SOMIPSEL ,SPISOMI pull select" "Pull down,Pull up" bitfld.long 0x00 10. " SIMOPSEL ,SPISIMO pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 9. " CLKPSEL ,SPICLK pull select" "Pull down,Pull up" bitfld.long 0x00 8. " ENAPSEL ,SPIENA pull select" "Pull down,Pull up" bitfld.long 0x00 7. " SCSPSEL7 ,/SPISCS7 pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 6. " SCSPSEL6 ,/SPISCS6 pull select" "Pull down,Pull up" bitfld.long 0x00 5. " SCSPSEL5 ,/SPISCS5 pull select" "Pull down,Pull up" bitfld.long 0x00 4. " SCSPSEL4 ,/SPISCS4 pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 3. " SCSPSEL3 ,/SPISCS3 pull select" "Pull down,Pull up" bitfld.long 0x00 2. " SCSPSEL2 ,/SPISCS2 pull select" "Pull down,Pull up" bitfld.long 0x00 1. " SCSPSEL1 ,/SPISCS1 pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 0. " SCSPSEL0 ,/SPISCS0 pull select" "Pull down,Pull up" tree.end tree.end width 7. textline " " if (((d.l(ad:0xFFF7F400+0x04))&0x1000000)==0x1000000) group.long 0x38++0x03 line.long 0x00 "DAT0,Transmit Data Register 0" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI / mibspi transmit data" else rgroup.long 0x38++0x03 line.long 0x00 "DAT0,Transmit Data Register 0" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI / mibspi transmit data" endif if (((d.l(ad:0xFFF7F400+0x04))&0x01)==0x01) group.long 0x3C++0x03 line.long 0x00 "DAT1,Transmit Data Register 1" bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Not active,Active" bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled" bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" textline " " hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Spi/mibspi transmit data" else group.long 0x3C++0x03 line.long 0x00 "DAT1,Transmit Data Register 1" bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Spi/mibspi transmit data" endif hgroup.long 0x40++0x03 hide.long 0x00 "BUF,Receive Buffer Register" in if (((d.l(ad:0xFFF7F400+0x04))&0x01)==0x01) rgroup.long 0x44++0x03 line.long 0x00 "EMU,Emulation Register" bitfld.long 0x00 31. " RXEMPTY ,Receive data buffer empty" "No empty,Empty" bitfld.long 0x00 30. " RXOVR ,Receive data buffer overrun" "No overrun,Overrun" bitfld.long 0x00 29. " TXFULL ,Transmit data buffer full" "Empty,Full" textline " " bitfld.long 0x00 28. " BITERR ,Mismatch of internal transmit data and transmitted data" "Not occurred,Occurred" bitfld.long 0x00 27. " DESYNC ,De-synchronization of slave device" "No de-synchronized,De-synchronized" bitfld.long 0x00 26. " PARITYERR ,Calculated parity differs from received parity bit" "No error,Error" textline " " bitfld.long 0x00 25. " TIMEOUT ,Time-out due to Non-activation of ENA pin" "Not occurred,Occurred" bitfld.long 0x00 24. " DLENERR ,Data length error flag" "No error,Error" hexmask.long.byte 0x00 16.--23. 1. " LCSNR ,Last chip select number" textline " " hexmask.long.word 0x00 0.--15. 1. " RXDATA ,SPI receive data" else rgroup.long 0x44++0x03 line.long 0x00 "EMU,Emulation Register" bitfld.long 0x00 31. " RXEMPTY ,Receive data buffer empty" "No empty,Empty" bitfld.long 0x00 30. " RXOVR ,Receive data buffer overrun" "No overrun,Overrun" bitfld.long 0x00 29. " TXFULL ,Transmit data buffer full" "Empty,Full" textline " " bitfld.long 0x00 28. " BITERR ,Mismatch of internal transmit data and transmitted data" "Not occurred,Occurred" bitfld.long 0x00 26. " PARITYERR ,Calculated parity differs from received parity bit" "No error,Error" bitfld.long 0x00 24. " DLENERR ,Data length error flag" "No error,Error" textline " " hexmask.long.byte 0x00 16.--23. 1. " LCSNR ,Last chip select number" hexmask.long.word 0x00 0.--15. 1. " RXDATA ,SPI receive data" endif if (((d.l(ad:0xFFF7F400+0x04))&0x01)==0x01) group.long 0x48++0x03 line.long 0x00 "DELAY,Delay Register" hexmask.long.byte 0x00 24.--31. 1. " C2TDELAY ,Chip select active to transmit start delay" hexmask.long.byte 0x00 16.--23. 1. " T2CDELAY ,Transmit end to chip select inactive delay" hexmask.long.byte 0x00 8.--15. 1. " T2EDELAY ,Transmit data finished to ENA pin inactive time out" textline " " hexmask.long.byte 0x00 0.--7. 1. " C2EDELAY ,Chip select active to ENA signal active time out" else hgroup.long 0x48++0x03 hide.long 0x00 "DELAY,Delay Register" endif group.long 0x4C++0x03 line.long 0x00 "DEF,Default Chip Select Register" bitfld.long 0x00 7. " CSDEF7 ,Chip select default pattern 7" "Low,High" bitfld.long 0x00 6. " CSDEF6 ,Chip select default pattern 6" "Low,High" bitfld.long 0x00 5. " CSDEF5 ,Chip select default pattern 5" "Low,High" bitfld.long 0x00 4. " CSDEF4 ,Chip select default pattern 4" "Low,High" textline " " bitfld.long 0x00 3. " CSDEF3 ,Chip select default pattern 3" "Low,High" bitfld.long 0x00 2. " CSDEF2 ,Chip select default pattern 2" "Low,High" bitfld.long 0x00 1. " CSDEF1 ,Chip select default pattern 1" "Low,High" bitfld.long 0x00 0. " CSDEF0 ,Chip select default pattern 0" "Low,High" width 6. tree "SPI Data Format Registers" group.long 0x50++0x03 line.long 0x00 "FMT0,Data Format Register 0" bitfld.long 0x00 24.--29. " WDELAY0 ,Delay in between transmissions for data format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " PARPOL0 ,Parity polarity" "Even,Odd" bitfld.long 0x00 22. " PARITY0_ENA ,Parity enable for data format 0" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " WAITENA0 ,Master waits for ENA signal from slave for data format 0" "Not wait,Wait" bitfld.long 0x00 20. " SHIFTDIR0 ,Shift direction for data format 0" "MSB,LSB" bitfld.long 0x00 18. " DIS_CS_TIMERS0 ,Disable chipselect timers for this format register" "No,Yes" textline " " bitfld.long 0x00 17. " POLARITY0 ,SPI data format 0 clock polarity" "Low-inactive,High-inactive" bitfld.long 0x00 16. " PHASE0 ,SPI data format 0 clock delay" "Not delayed,Delayed" hexmask.long.byte 0x00 8.--15. 1. " PRESCALE0 ,SPI data format 0 prescaler" textline " " bitfld.long 0x00 0.--4. " CHARLEN0 ,SPI data format 0 data word length" ",,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..." group.long 0x54++0x03 line.long 0x00 "FMT1,Data Format Register 1" bitfld.long 0x00 24.--29. " WDELAY1 ,Delay in between transmissions for data format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " PARPOL1 ,Parity polarity" "Even,Odd" bitfld.long 0x00 22. " PARITY1_ENA ,Parity enable for data format 1" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " WAITENA1 ,Master waits for ENA signal from slave for data format 1" "Not wait,Wait" bitfld.long 0x00 20. " SHIFTDIR1 ,Shift direction for data format 1" "MSB,LSB" bitfld.long 0x00 18. " DIS_CS_TIMERS1 ,Disable chipselect timers for this format register" "No,Yes" textline " " bitfld.long 0x00 17. " POLARITY1 ,SPI data format 1 clock polarity" "Low-inactive,High-inactive" bitfld.long 0x00 16. " PHASE1 ,SPI data format 1 clock delay" "Not delayed,Delayed" hexmask.long.byte 0x00 8.--15. 1. " PRESCALE1 ,SPI data format 1 prescaler" textline " " bitfld.long 0x00 0.--4. " CHARLEN1 ,SPI data format 1 data word length" ",,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..." group.long 0x58++0x03 line.long 0x00 "FMT2,Data Format Register 2" bitfld.long 0x00 24.--29. " WDELAY2 ,Delay in between transmissions for data format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " PARPOL2 ,Parity polarity" "Even,Odd" bitfld.long 0x00 22. " PARITY2_ENA ,Parity enable for data format 2" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " WAITENA2 ,Master waits for ENA signal from slave for data format 2" "Not wait,Wait" bitfld.long 0x00 20. " SHIFTDIR2 ,Shift direction for data format 2" "MSB,LSB" bitfld.long 0x00 18. " DIS_CS_TIMERS2 ,Disable chipselect timers for this format register" "No,Yes" textline " " bitfld.long 0x00 17. " POLARITY2 ,SPI data format 2 clock polarity" "Low-inactive,High-inactive" bitfld.long 0x00 16. " PHASE2 ,SPI data format 2 clock delay" "Not delayed,Delayed" hexmask.long.byte 0x00 8.--15. 1. " PRESCALE2 ,SPI data format 2 prescaler" textline " " bitfld.long 0x00 0.--4. " CHARLEN2 ,SPI data format 2 data word length" ",,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..." group.long 0x5C++0x03 line.long 0x00 "FMT3,Data Format Register 3" bitfld.long 0x00 24.--29. " WDELAY3 ,Delay in between transmissions for data format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " PARPOL3 ,Parity polarity" "Even,Odd" bitfld.long 0x00 22. " PARITY3_ENA ,Parity enable for data format 3" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " WAITENA3 ,Master waits for ENA signal from slave for data format 3" "Not wait,Wait" bitfld.long 0x00 20. " SHIFTDIR3 ,Shift direction for data format 3" "MSB,LSB" bitfld.long 0x00 18. " DIS_CS_TIMERS3 ,Disable chipselect timers for this format register" "No,Yes" textline " " bitfld.long 0x00 17. " POLARITY3 ,SPI data format 3 clock polarity" "Low-inactive,High-inactive" bitfld.long 0x00 16. " PHASE3 ,SPI data format 3 clock delay" "Not delayed,Delayed" hexmask.long.byte 0x00 8.--15. 1. " PRESCALE3 ,SPI data format 3 prescaler" textline " " bitfld.long 0x00 0.--4. " CHARLEN3 ,SPI data format 3 data word length" ",,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..." tree.end width 12. tree "SPI Interrupt Vector Registers" if (((d.l(ad:0xFFF7F400+0x70))&0x01)==0x01) rgroup.long 0x60++0x03 line.long 0x00 "TGINTVECT0,Transfer Group Interrupt Vector Register 0" bitfld.long 0x00 1.--5. " INTVECT0 ,Interrupt vector for interrupt line INT0" "No interrupt,Interrupt of transfer group 0,Interrupt of transfer group 1,Interrupt of transfer group 2,Interrupt of transfer group 3,Interrupt of transfer group 4,Interrupt of transfer group 5,Interrupt of transfer group 6,Interrupt of transfer group 7,Interrupt of transfer group 8,Interrupt of transfer group 9,Interrupt of transfer group 10,Interrupt of transfer group 11,Interrupt of transfer group 12,Interrupt of transfer group 13,Interrupt of transfer group 14,Interrupt of transfer group 15,Interrupt/spiint0,,RXORN interrupt,?..." bitfld.long 0x00 0. " SUSPEND0 ,Transfer suspended/finished interrupt" "Suspended,Finished" else rgroup.long 0x60++0x03 line.long 0x00 "TGINTVECT0,Transfer Group Interrupt Vector Register 0" bitfld.long 0x00 1.--5. " INTVECT0 ,Interrupt vector for interrupt line INT0" "No interrupt,,,,,,,,,,,,,,,,,Interrupt/spiint0,Receive buffer full interrupt,Receive buffer overrun interrupt,Transmit buffer empty interrupt,?..." endif if (((d.l(ad:0xFFF7F400+0x70))&0x01)==0x01) rgroup.long 0x64++0x03 line.long 0x00 "TGINTVECT1,Transfer Group Interrupt Vector Register 1" bitfld.long 0x00 1.--5. " INTVECT1 ,Interrupt vector for interrupt line INT1" "No interrupt,Interrupt of transfer group 0,Interrupt of transfer group 1,Interrupt of transfer group 2,Interrupt of transfer group 3,Interrupt of transfer group 4,Interrupt of transfer group 5,Interrupt of transfer group 6,Interrupt of transfer group 7,Interrupt of transfer group 8,Interrupt of transfer group 9,Interrupt of transfer group 10,Interrupt of transfer group 11,Interrupt of transfer group 12,Interrupt of transfer group 13,Interrupt of transfer group 14,Interrupt of transfer group 15,Interrupt/spiint1,,RXORN interrupt,?..." bitfld.long 0x00 0. " SUSPEND1 ,Transfer suspended/finished interrupt" "Suspended,Finished" else rgroup.long 0x64++0x03 line.long 0x00 "TGINTVECT1,Transfer Group Interrupt Vector Register 1" bitfld.long 0x00 1.--5. " INTVECT1 ,Interrupt vector for interrupt line INT1" "No interrupt,,,,,,,,,,,,,,,,,Interrupt/spiint1,Receive buffer full interrupt,Receive buffer overrun interrupt,Transmit buffer empty interrupt,?..." endif tree.end width 8. textline " " if (((d.l(ad:0xFFF7F400+0x3C))&0x3000000)==0x00) group.long 0x6C++0x03 line.long 0x00 "PMCTRL,Parallel/modulo Mode Control Register" bitfld.long 0x00 5. " MOD_CLK_POL_0 ,Modulo mode SPICLK polarity" "Normal,Inverted" bitfld.long 0x00 2.--4. " MMODE_0 ,SPI data line selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..." bitfld.long 0x00 0.--1. " PMODE_0 ,Parallel mode" "1-data,2-data,4-data,8-data" elif (((d.l(ad:0xFFF7F400+0x3C))&0x3000000)==0x1000000) group.long 0x6C++0x03 line.long 0x00 "PMCTRL,Parallel/modulo Mode Control Register" bitfld.long 0x00 13. " MOD_CLK_POL_1 ,Modulo mode SPICLK polarity" "Normal,Inverted" bitfld.long 0x00 10.--12. " MMODE_1 ,SPI data line selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..." bitfld.long 0x00 8.--9. " PMODE_1 ,Parallel mode" "1-data,2-data,4-data,8-data" elif (((d.l((ad:0xFFF7F400+0x3C)))&0x3000000)==0x2000000) group.long 0x6C++0x03 line.long 0x00 "PMCTRL,Parallel/modulo Mode Control Register" bitfld.long 0x00 21. " MOD_CLK_POL_2 ,Modulo mode SPICLK polarity" "Normal,Inverted" bitfld.long 0x00 18.--20. " MMODE_2 ,SPI data line selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..." bitfld.long 0x00 16.--17. " PMODE_2 ,Parallel mode" "1-data,2-data,4-data,8-data" else group.long 0x6C++0x03 line.long 0x00 "PMCTRL,Parallel/modulo Mode Control Register" bitfld.long 0x00 29. " MOD_CLK_POL_3 ,Modulo mode SPICLK polarity" "Normal,Inverted" bitfld.long 0x00 26.--28. " MMODE_3 ,SPI data line selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..." bitfld.long 0x00 24.--25. " PMODE_3 ,Parallel mode" "1-data,2-data,4-data,8-data" endif width 11. tree "Mibspi Registers" group.long 0x70++0x03 line.long 0x00 "MIBSPIE,Mibspi Enable Register" bitfld.long 0x00 16. " RX_RAM_ACCESS ,Receive RAM access control bit" "RX not writable,R/W" bitfld.long 0x00 0. " MSPIENA ,Multibuffer mode enable" "Disabled,Enabled" if (((d.l(ad:0xFFF7F400+0x70))&0x01)==0x01) group.long 0x74++0x03 line.long 0x00 "TGITENST,Mibspi Transfer Group Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTEN_RDY15_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x04 30. " INTEN_RDY14_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 29. 0x00 29. 0x04 29. " INTEN_RDY13_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x04 28. " INTEN_RDY12_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. 0x00 27. 0x04 27. " INTEN_RDY11_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x04 26. " INTEN_RDY10_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x04 25. " INTEN_RDY9_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x04 24. " INTEN_RDY8_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. 0x00 23. 0x04 23. " INTEN_RDY7_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x04 22. " INTEN_RDY6_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. 0x00 21. 0x04 21. " INTEN_RDY5_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x04 20. " INTEN_RDY4_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x04 19. " INTEN_RDY3_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x04 18. " INTEN_RDY2_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. 0x00 17. 0x04 17. " INTEN_RDY1_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x04 16. " INTEN_RDY0_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 15. 0x00 15. 0x04 15. " INTEN_SUS15_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x04 14. " INTEN_SUS14_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x04 13. " INTEN_SUS13_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x04 12. " INTEN_SUS12_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 11. 0x00 11. 0x04 11. " INTEN_SUS11_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x04 10. " INTEN_SUS10_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. 0x00 9. 0x04 9. " INTEN_SUS9_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x04 8. " INTEN_SUS8_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x04 7. " INTEN_SUS7_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x04 6. " INTEN_SUS6_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x00 5. 0x04 5. " INTEN_SUS5_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x04 4. " INTEN_SUS4_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. 0x00 3. 0x04 3. " INTEN_SUS3_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x04 2. " INTEN_SUS2_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x04 1. " INTEN_SUS1_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " INTEN_SUS0_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" group.long 0x7C++0x03 line.long 0x00 "TGITLVST,Mibspi Transfer Group Interrupt Level Set Register" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTLVL_RDY15_SET/CLR ,Transfer group completed interrupt level 15" "INT0,INT1" setclrfld.long 0x00 30. 0x00 30. 0x04 30. " INTLVL_RDY14_SET/CLR ,Transfer group completed interrupt level 14" "INT0,INT1" textline " " setclrfld.long 0x00 29. 0x00 29. 0x04 29. " INTLVL_RDY13_SET/CLR ,Transfer group completed interrupt level 13" "INT0,INT1" setclrfld.long 0x00 28. 0x00 28. 0x04 28. " INTLVL_RDY12_SET/CLR ,Transfer group completed interrupt level 12" "INT0,INT1" textline " " setclrfld.long 0x00 27. 0x00 27. 0x04 27. " INTLVL_RDY11_SET/CLR ,Transfer group completed interrupt level 11" "INT0,INT1" setclrfld.long 0x00 26. 0x00 26. 0x04 26. " INTLVL_RDY10_SET/CLR ,Transfer group completed interrupt level 10" "INT0,INT1" textline " " setclrfld.long 0x00 25. 0x00 25. 0x04 25. " INTLVL_RDY9_SET/CLR ,Transfer group completed interrupt level set 9" "INT0,INT1" setclrfld.long 0x00 24. 0x00 24. 0x04 24. " INTLVL_RDY8_SET/CLR ,Transfer group completed interrupt level set 8" "INT0,INT1" textline " " setclrfld.long 0x00 23. 0x00 23. 0x04 23. " INTLVL_RDY7_SET/CLR ,Transfer group completed interrupt level set 7" "INT0,INT1" setclrfld.long 0x00 22. 0x00 22. 0x04 22. " INTLVL_RDY6_SET/CLR ,Transfer group completed interrupt level set 6" "INT0,INT1" textline " " setclrfld.long 0x00 21. 0x00 21. 0x04 21. " INTLVL_RDY5_SET/CLR ,Transfer group completed interrupt level set 5" "INT0,INT1" setclrfld.long 0x00 20. 0x00 20. 0x04 20. " INTLVL_RDY4_SET/CLR ,Transfer group completed interrupt level set 4" "INT0,INT1" textline " " setclrfld.long 0x00 19. 0x00 19. 0x04 19. " INTLVL_RDY3_SET/CLR ,Transfer group completed interrupt level set 3" "INT0,INT1" setclrfld.long 0x00 18. 0x00 18. 0x04 18. " INTLVL_RDY2_SET/CLR ,Transfer group completed interrupt level set 2" "INT0,INT1" textline " " setclrfld.long 0x00 17. 0x00 17. 0x04 17. " INTLVL_RDY1_SET/CLR ,Transfer group completed interrupt level set 1" "INT0,INT1" setclrfld.long 0x00 16. 0x00 16. 0x04 16. " INTLVL_RDY0_SET/CLR ,Transfer group completed interrupt level set 0" "INT0,INT1" textline " " setclrfld.long 0x00 15. 0x00 15. 0x04 15. " INTLVL_SUS15_SET/CLR ,Transfer group suspended interrupt level set 15" "INT0,INT1" setclrfld.long 0x00 14. 0x00 14. 0x04 14. " INTLVL_SUS14_SET/CLR ,Transfer group suspended interrupt level set 14" "INT0,INT1" textline " " setclrfld.long 0x00 13. 0x00 13. 0x04 13. " INTLVL_SUS13_SET/CLR ,Transfer group suspended interrupt level set 13" "INT0,INT1" setclrfld.long 0x00 12. 0x00 12. 0x04 12. " INTLVL_SUS12_SET/CLR ,Transfer group suspended interrupt level set 12" "INT0,INT1" textline " " setclrfld.long 0x00 11. 0x00 11. 0x04 11. " INTLVL_SUS11_SET/CLR ,Transfer group suspended interrupt level set 11" "INT0,INT1" setclrfld.long 0x00 10. 0x00 10. 0x04 10. " INTLVL_SUS10_SET/CLR ,Transfer group suspended interrupt level set 10" "INT0,INT1" textline " " setclrfld.long 0x00 9. 0x00 9. 0x04 9. " INTLVL_SUS9_SET/CLR ,Transfer group suspended interrupt level set 9" "INT0,INT1" setclrfld.long 0x00 8. 0x00 8. 0x04 8. " INTLVL_SUS8_SET/CLR ,Transfer group suspended interrupt level set 8" "INT0,INT1" textline " " setclrfld.long 0x00 7. 0x00 7. 0x04 7. " INTLVL_SUS7_SET/CLR ,Transfer group suspended interrupt level set 7" "INT0,INT1" setclrfld.long 0x00 6. 0x00 6. 0x04 6. " INTLVL_SUS6_SET/CLR ,Transfer group suspended interrupt level set 6" "INT0,INT1" textline " " setclrfld.long 0x00 5. 0x00 5. 0x04 5. " INTLVL_SUS5_SET/CLR ,Transfer group suspended interrupt level set 5" "INT0,INT1" setclrfld.long 0x00 4. 0x00 4. 0x04 4. " INTLVL_SUS4_SET/CLR ,Transfer group suspended interrupt level set 4" "INT0,INT1" textline " " setclrfld.long 0x00 3. 0x00 3. 0x04 3. " INTLVL_SUS3_SET/CLR ,Transfer group suspended interrupt level set 3" "INT0,INT1" setclrfld.long 0x00 2. 0x00 2. 0x04 2. " INTLVL_SUS2_SET/CLR ,Transfer group suspended interrupt level set 2" "INT0,INT1" textline " " setclrfld.long 0x00 1. 0x00 1. 0x04 1. " INTLVL_SUS1_SET/CLR ,Transfer group suspended interrupt level set 1" "INT0,INT1" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " INTLVL_SUS0_SET/CLR ,Transfer group suspended interrupt level set 0" "INT0,INT1" group.long 0x84++0x03 line.long 0x00 "TGINTFLAG,Transfer Group Interrupt Flag Register" eventfld.long 0x00 31. " INTFLGRDY15 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" eventfld.long 0x00 30. " INTFLGRDY14 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 29. " INTFLGRDY13 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" eventfld.long 0x00 28. " INTFLGRDY12 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 27. " INTFLGRDY11 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" eventfld.long 0x00 26. " INTFLGRDY10 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 25. " INTFLGRDY9 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" eventfld.long 0x00 24. " INTFLGRDY8 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 23. " INTFLGRDY7 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" eventfld.long 0x00 22. " INTFLGRDY6 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 21. " INTFLGRDY5 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" eventfld.long 0x00 20. " INTFLGRDY4 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 19. " INTFLGRDY3 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" eventfld.long 0x00 18. " INTFLGRDY2 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 17. " INTFLGRDY1 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" eventfld.long 0x00 16. " INTFLGRDY0 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 15. " INTFLGSUS15 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" eventfld.long 0x00 14. " INTFLGSUS14 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 13. " INTFLGSUS13 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" eventfld.long 0x00 12. " INTFLGSUS12 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 11. " INTFLGSUS11 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" eventfld.long 0x00 10. " INTFLGSUS10 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 9. " INTFLGSUS9 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" eventfld.long 0x00 8. " INTFLGSUS8 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 7. " INTFLGSUS7 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" eventfld.long 0x00 6. " INTFLGSUS6 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 5. " INTFLGSUS5 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" eventfld.long 0x00 4. " INTFLGSUS4 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " INTFLGSUS3 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" eventfld.long 0x00 2. " INTFLGSUS2 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 1. " INTFLGSUS1 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " INTFLGSUS0 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" group.long 0x90++0x03 line.long 0x00 "TICKCNT,Tick Count Register" bitfld.long 0x00 31. " TICKENA ,Tick counter enable" "Disabled,Enabled" bitfld.long 0x00 30. " RELOAD ,Re-load tick counter" "No effect,Reload" textline " " bitfld.long 0x00 28.--29. " CLKCTRL ,Tick counter clock source control" "Format 0,Format 1,Format 2,Format 3" hexmask.long.word 0x00 0.--15. 1. " TICKVALUE ,Initial value for tick counter" group.long 0x94++0x03 line.long 0x00 "LTGPEND,Last Transfer Group End Pointer" bitfld.long 0x00 24.--28. " TG_IN_SERVICE ,Transfer group currently being serviced by the sequencer" "Not serviced,Group0,Group1,Group2,Group3,Group4,Group5,Group6,Group7,Group8,Group9,Group10,Group11,Group12,Group13,Group14,Group15,?..." hexmask.long.byte 0x00 8.--14. 1. " LPEND ,Last transfer group end pointer" else hgroup.long 0x74++0x03 hide.long 0x00 "TGITENST,Mibspi Transfer Group Interrupt Enable Register" hgroup.long 0x7C++0x03 hide.long 0x00 "TGITLVST,Mibspi Transfer Group Interrupt Level Register" hgroup.long 0x84++0x03 hide.long 0x00 "TGINTFLAG,Transfer Group Interrupt Flag Register" hgroup.long 0x90++0x03 hide.long 0x00 "TICKCNT,Tick Count Register" hgroup.long 0x94++0x03 hide.long 0x00 "LTGPEND,Last Transfer Group End Pointer" endif width 20. tree "Mibspi Transfer Group Control Registers" if (((d.l(ad:0xFFF7F400+0x70))&0x01)==0x01) group.long 0x98++0x03 line.long 0x00 "TG0CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA0 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT0 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST0 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD0 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT0 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC0 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART0 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT0 ,Transfer group pointer to current buffer" group.long 0x9C++0x03 line.long 0x00 "TG1CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA1 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT1 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST1 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD1 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT1 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC1 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART1 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT1 ,Transfer group pointer to current buffer" group.long 0xA0++0x03 line.long 0x00 "TG2CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA2 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT2 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST2 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD2 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT2 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC2 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART2 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT2 ,Transfer group pointer to current buffer" group.long 0xA4++0x03 line.long 0x00 "TG3CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA3 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT3 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST3 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD3 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT3 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC3 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART3 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT3 ,Transfer group pointer to current buffer" group.long 0xA8++0x03 line.long 0x00 "TG4CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA4 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT4 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST4 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD4 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT4 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC4 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART4 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT4 ,Transfer group pointer to current buffer" group.long 0xAC++0x03 line.long 0x00 "TG5CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA5 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT5 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST5 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD5 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT5 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC5 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART5 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT5 ,Transfer group pointer to current buffer" group.long 0xB0++0x03 line.long 0x00 "TG6CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA6 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT6 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST6 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD6 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT6 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC6 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART6 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT6 ,Transfer group pointer to current buffer" group.long 0xB4++0x03 line.long 0x00 "TG7CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA7 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT7 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST7 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD7 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT7 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC7 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART7 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT7 ,Transfer group pointer to current buffer" group.long 0xB8++0x03 line.long 0x00 "TG8CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA8 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT8 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST8 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD8 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT8 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC8 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART8 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT8 ,Transfer group pointer to current buffer" group.long 0xBC++0x03 line.long 0x00 "TG9CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA9 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT9 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST9 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD9 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT9 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC9 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART9 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT9 ,Transfer group pointer to current buffer" group.long 0xC0++0x03 line.long 0x00 "TG10CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA10 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT10 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST10 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD10 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT10 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC10 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART10 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT10 ,Transfer group pointer to current buffer" group.long 0xC4++0x03 line.long 0x00 "TG11CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA11 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT11 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST11 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD11 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT11 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC11 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART11 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT11 ,Transfer group pointer to current buffer" group.long 0xC8++0x03 line.long 0x00 "TG12CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA12 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT12 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST12 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD12 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT12 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC12 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART12 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT12 ,Transfer group pointer to current buffer" group.long 0xCC++0x03 line.long 0x00 "TG13CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA13 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT13 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST13 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD13 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT13 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC13 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART13 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT13 ,Transfer group pointer to current buffer" group.long 0xD0++0x03 line.long 0x00 "TG14CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA14 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT14 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST14 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD14 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT14 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC14 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART14 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT14 ,Transfer group pointer to current buffer" group.long 0xD4++0x03 line.long 0x00 "TG15CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA15 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT15 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST15 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD15 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT15 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC15 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART15 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT15 ,Transfer group pointer to current buffer" else hgroup.long 0x98++0x03 hide.long 0x00 "TG0CTRL,Mibspi Transfer Group Control Register" hgroup.long 0x9C++0x03 hide.long 0x00 "TG1CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xA0++0x03 hide.long 0x00 "TG2CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xA4++0x03 hide.long 0x00 "TG3CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xA8++0x03 hide.long 0x00 "TG4CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xAC++0x03 hide.long 0x00 "TG5CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xB0++0x03 hide.long 0x00 "TG6CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xB4++0x03 hide.long 0x00 "TG7CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xB8++0x03 hide.long 0x00 "TG8CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xBC++0x03 hide.long 0x00 "TG9CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xC0++0x03 hide.long 0x00 "TG10CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xC4++0x03 hide.long 0x00 "TG11CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xC8++0x03 hide.long 0x00 "TG12CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xCC++0x03 hide.long 0x00 "TG13CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xD0++0x03 hide.long 0x00 "TG14CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xD4++0x03 hide.long 0x00 "TG15CTRL,Mibspi Transfer Group Control Register" endif tree.end textline " " sif (cpu()!="RM42L432") if ((((d.l(ad:0xFFF7F400+0x04))&0x01)==0x01)&&((d.l(ad:0xFFF7F400+0x70))&0x01)==0x01) group.long 0xD8++0x03 line.long 0x00 "DMA0CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT0 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 0" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID0 ,Buffer utilized for DMA transfer 0" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP0 ,Receive data DMA request map 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP0 ,Transmit data DMA channel 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA0 ,Receive data DMA channel enable 0" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA0 ,Transmit data DMA channel enable 0" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK0 ,Non-interleaved DMA block transfer 0" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT0 ,Initial count of DMA transfers 0" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT170 ,The 17th bit of COUNT field of DMA0COUNT register" "Low,High" bitfld.long 0x00 0.--5. " COUNT0 ,Actual number of remaining DMA transfer 0" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l(ad:0xFFF7F400+0x04))&0x01)==0x00)&&((d.l(ad:0xFFF7F400+0x70))&0x01)==0x01) group.long 0xD8++0x03 line.long 0x00 "DMA0CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT0 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 0" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID0 ,Buffer utilized for DMA transfer 0" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP0 ,Receive data DMA request map 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP0 ,Transmit data DMA channel 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA0 ,Receive data DMA channel enable 0" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA0 ,Transmit data DMA channel enable 0" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT0 ,Initial count of DMA transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT170 ,The 17th bit of COUNT field of DMA0COUNT register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT0 ,Actual number of remaining DMA transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xD8++0x03 hide.long 0x00 "DMA0CTRL,Mibspi DMA Channel Control Register" endif if ((((d.l(ad:0xFFF7F400+0x04))&0x01)==0x01)&&((d.l(ad:0xFFF7F400+0x70))&0x01)==0x01) group.long 0xDC++0x03 line.long 0x00 "DMA1CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT1 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 1" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID1 ,Buffer utilized for DMA transfer 1" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP1 ,Receive data DMA request map 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP1 ,Transmit data DMA channel 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA1 ,Receive data DMA channel enable 1" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA1 ,Transmit data DMA channel enable 1" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK1 ,Non-interleaved DMA block transfer 1" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT1 ,Initial count of DMA transfers 1" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT171 ,The 17th bit of COUNT field of DMA1COUNT register" "Low,High" bitfld.long 0x00 0.--5. " COUNT1 ,Actual number of remaining DMA transfer 1" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l(ad:0xFFF7F400+0x04))&0x01)==0x00)&&((d.l(ad:0xFFF7F400+0x70))&0x01)==0x01) group.long 0xDC++0x03 line.long 0x00 "DMA1CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT1 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 1" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID1 ,Buffer utilized for DMA transfer 1" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP1 ,Receive data DMA request map 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP1 ,Transmit data DMA channel 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA1 ,Receive data DMA channel enable 1" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA1 ,Transmit data DMA channel enable 1" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT1 ,Initial count of DMA transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT171 ,The 17th bit of COUNT field of DMA1COUNT register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT1 ,Actual number of remaining DMA transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xDC++0x03 hide.long 0x00 "DMA1CTRL,Mibspi DMA Channel Control Register" endif if ((((d.l(ad:0xFFF7F400+0x04))&0x01)==0x01)&&((d.l(ad:0xFFF7F400+0x70))&0x01)==0x01) group.long 0xE0++0x03 line.long 0x00 "DMA2CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT2 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 2" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID2 ,Buffer utilized for DMA transfer 2" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP2 ,Receive data DMA request map 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP2 ,Transmit data DMA channel 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA2 ,Receive data DMA channel enable 2" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA2 ,Transmit data DMA channel enable 2" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK2 ,Non-interleaved DMA block transfer 2" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT2 ,Initial count of DMA transfers 2" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT172 ,The 17th bit of COUNT field of DMA2COUNT register" "Low,High" bitfld.long 0x00 0.--5. " COUNT2 ,Actual number of remaining DMA transfer 2" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l(ad:0xFFF7F400+0x04))&0x01)==0x00)&&((d.l(ad:0xFFF7F400+0x70))&0x01)==0x01) group.long 0xE0++0x03 line.long 0x00 "DMA2CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT2 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 2" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID2 ,Buffer utilized for DMA transfer 2" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP2 ,Receive data DMA request map 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP2 ,Transmit data DMA channel 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA2 ,Receive data DMA channel enable 2" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA2 ,Transmit data DMA channel enable 2" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT2 ,Initial count of DMA transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT172 ,The 17th bit of COUNT field of DMA2COUNT register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT2 ,Actual number of remaining DMA transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xE0++0x03 hide.long 0x00 "DMA2CTRL,Mibspi DMA Channel Control Register" endif if ((((d.l(ad:0xFFF7F400+0x04))&0x01)==0x01)&&((d.l(ad:0xFFF7F400+0x70))&0x01)==0x01) group.long 0xE4++0x03 line.long 0x00 "DMA3CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT3 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 3" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID3 ,Buffer utilized for DMA transfer 3" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP3 ,Receive data DMA request map 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP3 ,Transmit data DMA channel 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA3 ,Receive data DMA channel enable 3" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA3 ,Transmit data DMA channel enable 3" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK3 ,Non-interleaved DMA block transfer 3" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT3 ,Initial count of DMA transfers 3" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT173 ,The 17th bit of COUNT field of DMA3COUNT register" "Low,High" bitfld.long 0x00 0.--5. " COUNT3 ,Actual number of remaining DMA transfer 3" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l(ad:0xFFF7F400+0x04))&0x01)==0x00)&&((d.l(ad:0xFFF7F400+0x70))&0x01)==0x01) group.long 0xE4++0x03 line.long 0x00 "DMA3CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT3 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 3" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID3 ,Buffer utilized for DMA transfer 3" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP3 ,Receive data DMA request map 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP3 ,Transmit data DMA channel 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA3 ,Receive data DMA channel enable 3" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA3 ,Transmit data DMA channel enable 3" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT3 ,Initial count of DMA transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT173 ,The 17th bit of COUNT field of DMA3COUNT register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT3 ,Actual number of remaining DMA transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xE4++0x03 hide.long 0x00 "DMA3CTRL,Mibspi DMA Channel Control Register" endif if ((((d.l(ad:0xFFF7F400+0x04))&0x01)==0x01)&&((d.l(ad:0xFFF7F400+0x70))&0x01)==0x01) group.long 0xE8++0x03 line.long 0x00 "DMA4CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT4 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 4" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID4 ,Buffer utilized for DMA transfer 4" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP4 ,Receive data DMA request map 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP4 ,Transmit data DMA channel 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA4 ,Receive data DMA channel enable 4" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA4 ,Transmit data DMA channel enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK4 ,Non-interleaved DMA block transfer 4" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT4 ,Initial count of DMA transfers 4" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT174 ,The 17th bit of COUNT field of DMA4COUNT register" "Low,High" bitfld.long 0x00 0.--5. " COUNT4 ,Actual number of remaining DMA transfer 4" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l(ad:0xFFF7F400+0x04))&0x01)==0x00)&&((d.l(ad:0xFFF7F400+0x70))&0x01)==0x01) group.long 0xE8++0x03 line.long 0x00 "DMA4CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT4 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 4" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID4 ,Buffer utilized for DMA transfer 4" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP4 ,Receive data DMA request map 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP4 ,Transmit data DMA channel 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA4 ,Receive data DMA channel enable 4" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA4 ,Transmit data DMA channel enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT4 ,Initial count of DMA transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT174 ,The 17th bit of COUNT field of DMA4COUNT register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT4 ,Actual number of remaining DMA transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xE8++0x03 hide.long 0x00 "DMA4CTRL,Mibspi DMA Channel Control Register" endif if ((((d.l(ad:0xFFF7F400+0x04))&0x01)==0x01)&&((d.l(ad:0xFFF7F400+0x70))&0x01)==0x01) group.long 0xEC++0x03 line.long 0x00 "DMA5CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT5 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 5" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID5 ,Buffer utilized for DMA transfer 5" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP5 ,Receive data DMA request map 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP5 ,Transmit data DMA channel 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA5 ,Receive data DMA channel enable 5" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA5 ,Transmit data DMA channel enable 5" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK5 ,Non-interleaved DMA block transfer 5" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT5 ,Initial count of DMA transfers 5" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT175 ,The 17th bit of COUNT field of DMA5COUNT register" "Low,High" bitfld.long 0x00 0.--5. " COUNT5 ,Actual number of remaining DMA transfer 5" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l(ad:0xFFF7F400+0x04))&0x01)==0x00)&&((d.l(ad:0xFFF7F400+0x70))&0x01)==0x01) group.long 0xEC++0x03 line.long 0x00 "DMA5CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT5 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 5" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID5 ,Buffer utilized for DMA transfer 5" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP5 ,Receive data DMA request map 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP5 ,Transmit data DMA channel 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA5 ,Receive data DMA channel enable 5" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA5 ,Transmit data DMA channel enable 5" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT5 ,Initial count of DMA transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT175 ,The 17th bit of COUNT field of DMA5COUNT register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT5 ,Actual number of remaining DMA transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xEC++0x03 hide.long 0x00 "DMA5CTRL,Mibspi DMA Channel Control Register" endif if ((((d.l(ad:0xFFF7F400+0x04))&0x01)==0x01)&&((d.l(ad:0xFFF7F400+0x70))&0x01)==0x01) group.long 0xF0++0x03 line.long 0x00 "DMA6CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT6 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 6" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID6 ,Buffer utilized for DMA transfer 6" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP6 ,Receive data DMA request map 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP6 ,Transmit data DMA channel 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA6 ,Receive data DMA channel enable 6" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA6 ,Transmit data DMA channel enable 6" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK6 ,Non-interleaved DMA block transfer 6" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT6 ,Initial count of DMA transfers 6" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT176 ,The 17th bit of COUNT field of DMA6COUNT register" "Low,High" bitfld.long 0x00 0.--5. " COUNT6 ,Actual number of remaining DMA transfer 6" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l(ad:0xFFF7F400+0x04))&0x01)==0x00)&&((d.l(ad:0xFFF7F400+0x70))&0x01)==0x01) group.long 0xF0++0x03 line.long 0x00 "DMA6CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT6 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 6" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID6 ,Buffer utilized for DMA transfer 6" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP6 ,Receive data DMA request map 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP6 ,Transmit data DMA channel 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA6 ,Receive data DMA channel enable 6" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA6 ,Transmit data DMA channel enable 6" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT6 ,Initial count of DMA transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT176 ,The 17th bit of COUNT field of DMA6COUNT register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT6 ,Actual number of remaining DMA transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xF0++0x03 hide.long 0x00 "DMA6CTRL,Mibspi DMA Channel Control Register" endif if ((((d.l(ad:0xFFF7F400+0x04))&0x01)==0x01)&&((d.l(ad:0xFFF7F400+0x70))&0x01)==0x01) group.long 0xF4++0x03 line.long 0x00 "DMA7CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT7 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 7" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID7 ,Buffer utilized for DMA transfer 7" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP7 ,Receive data DMA request map 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP7 ,Transmit data DMA channel 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA7 ,Receive data DMA channel enable 7" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA7 ,Transmit data DMA channel enable 7" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK7 ,Non-interleaved DMA block transfer 7" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT7 ,Initial count of DMA transfers 7" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT177 ,The 17th bit of COUNT field of DMA7COUNT register" "Low,High" bitfld.long 0x00 0.--5. " COUNT7 ,Actual number of remaining DMA transfer 7" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l(ad:0xFFF7F400+0x04))&0x01)==0x00)&&((d.l(ad:0xFFF7F400+0x70))&0x01)==0x01) group.long 0xF4++0x03 line.long 0x00 "DMA7CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT7 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 7" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID7 ,Buffer utilized for DMA transfer 7" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP7 ,Receive data DMA request map 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP7 ,Transmit data DMA channel 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA7 ,Receive data DMA channel enable 7" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA7 ,Transmit data DMA channel enable 7" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT7 ,Initial count of DMA transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT177 ,The 17th bit of COUNT field of DMA7COUNT register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT7 ,Actual number of remaining DMA transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xF4++0x03 hide.long 0x00 "DMA7CTRL,Mibspi DMA Channel Control Register" endif if (((d.l(ad:0xFFF7F400+0x70))&0x01)==0x01) group.long 0xF8++0x03 line.long 0x00 "DMA0COUNT,ICOUNT Register 0" hexmask.long.word 0x00 16.--31. 1. " ICOUNT0 ,Initial number of DMA transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT0 ,Actual number of remaining DMA transfer" else hgroup.long 0xF8++0x03 hide.long 0x00 "DMA0COUNT,ICOUNT Register 0" endif if (((d.l(ad:0xFFF7F400+0x70))&0x01)==0x01) group.long 0xFC++0x03 line.long 0x00 "DMA1COUNT,ICOUNT Register 1" hexmask.long.word 0x00 16.--31. 1. " ICOUNT1 ,Initial number of DMA transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT1 ,Actual number of remaining DMA transfer" else hgroup.long 0xFC++0x03 hide.long 0x00 "DMA1COUNT,ICOUNT Register 1" endif if (((d.l(ad:0xFFF7F400+0x70))&0x01)==0x01) group.long 0x100++0x03 line.long 0x00 "DMA2COUNT,ICOUNT Register 2" hexmask.long.word 0x00 16.--31. 1. " ICOUNT2 ,Initial number of DMA transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT2 ,Actual number of remaining DMA transfer" else hgroup.long 0x100++0x03 hide.long 0x00 "DMA2COUNT,ICOUNT Register 2" endif if (((d.l(ad:0xFFF7F400+0x70))&0x01)==0x01) group.long 0x104++0x03 line.long 0x00 "DMA3COUNT,ICOUNT Register 3" hexmask.long.word 0x00 16.--31. 1. " ICOUNT3 ,Initial number of DMA transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT3 ,Actual number of remaining DMA transfer" else hgroup.long 0x104++0x03 hide.long 0x00 "DMA3COUNT,ICOUNT Register 3" endif if (((d.l(ad:0xFFF7F400+0x70))&0x01)==0x01) group.long 0x108++0x03 line.long 0x00 "DMA4COUNT,ICOUNT Register 4" hexmask.long.word 0x00 16.--31. 1. " ICOUNT4 ,Initial number of DMA transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT4 ,Actual number of remaining DMA transfer" else hgroup.long 0x108++0x03 hide.long 0x00 "DMA4COUNT,ICOUNT Register 4" endif if (((d.l(ad:0xFFF7F400+0x70))&0x01)==0x01) group.long 0x10C++0x03 line.long 0x00 "DMA5COUNT,ICOUNT Register 5" hexmask.long.word 0x00 16.--31. 1. " ICOUNT5 ,Initial number of DMA transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT5 ,Actual number of remaining DMA transfer" else hgroup.long 0x10C++0x03 hide.long 0x00 "DMA5COUNT,ICOUNT Register 5" endif if (((d.l(ad:0xFFF7F400+0x70))&0x01)==0x01) group.long 0x110++0x03 line.long 0x00 "DMA6COUNT,ICOUNT Register 6" hexmask.long.word 0x00 16.--31. 1. " ICOUNT6 ,Initial number of DMA transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT6 ,Actual number of remaining DMA transfer" else hgroup.long 0x110++0x03 hide.long 0x00 "DMA6COUNT,ICOUNT Register 6" endif if (((d.l(ad:0xFFF7F400+0x70))&0x01)==0x01) group.long 0x114++0x03 line.long 0x00 "DMA7COUNT,ICOUNT Register 7" hexmask.long.word 0x00 16.--31. 1. " ICOUNT7 ,Initial number of DMA transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT7 ,Actual number of remaining DMA transfer" else hgroup.long 0x114++0x03 hide.long 0x00 "DMA7COUNT,ICOUNT Register 7" endif endif textline " " if (((d.l(ad:0xFFF7F400+0x70))&0x01)==0x01) sif (cpu()!="RM42L432") group.long 0x118++0x03 line.long 0x00 "DMACNTLEN,DMA LARGE COUNT Register" bitfld.long 0x00 0. " LARGE_COUNT ,Large count" "Modified,Not modified" endif group.long 0x120++0x03 line.long 0x00 "UERRCTRL,Uncorrectable Parity Error Control Register" sif cpuis("RM57L843-ZWT") bitfld.long 0x00 24.--27. " SBE_EVT_EN ,Single bit error event enable" ",,,,,Disabled,,,,,Enabled,?..." bitfld.long 0x00 16.--19. " EDAC_MODE ,These bits determine whether single bit errors (Sbe) detected by the SECDED block will be corrected or not" ",,,,,Disabled,,,,,Enabled,?..." textline " " endif bitfld.long 0x00 8. " PTESTEN ,Parity memory test enable" "Disabled,Enabled" bitfld.long 0x00 0.--3. " EDEN ,Error detection enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" hgroup.long 0x124++0x03 hide.long 0x00 "UERRSTAT,Uncorrectable Parity Error Status Register" in hgroup.long 0x128++0x03 hide.long 0x00 "UERRADDR1,Uncorrectable Parity Error Address Register" in hgroup.long 0x12C++0x03 hide.long 0x00 "UERRADDR0,Uncorrectable Parity Error Address Register" in hgroup.long 0x130++0x03 hide.long 0x00 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register" in else hgroup.long 0x118++0x03 hide.long 0x00 "DMACNTLEN,DMA LARGE COUNT Register" hgroup.long 0x120++0x03 hide.long 0x00 "UERRCTRL,Uncorrectable Parity Error Control Register" hgroup.long 0x124++0x03 hide.long 0x00 "UERRSTAT,Uncorrectable Parity Error Status Register" hgroup.long 0x128++0x03 hide.long 0x00 "UERRADDR1,Uncorrectable Parity Error Address Register" hgroup.long 0x12C++0x03 hide.long 0x00 "UERRADDR0,Uncorrectable Parity Error Address Register" hgroup.long 0x130++0x03 hide.long 0x00 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register" endif tree.end textline " " if ((((d.l(ad:0xFFF7F400+0x134))&0xF00)==0xA00)&&(((d.l(ad:0xFFF7F400+0x134))&0x02)==0x02)) group.long 0x134++0x03 line.long 0x00 "IOLPBKTSTCR,Spi/mibspi IO Loopback Test Control Register" bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" eventfld.long 0x00 24. " SCS_FAIL_FLG ,Analog loopback /SPISCS pin compare failure" "Not failed,Failed" textline " " bitfld.long 0x00 20. " CTRL_BITERR ,Inducing of BITERR during IO loopback test mode control" "Not affected,Flipped" bitfld.long 0x00 19. " CTRL_DESYNC ,Inducing of DESYNC error during IO loopback test mode control" "Not affected,Forced to 0" textline " " bitfld.long 0x00 18. " CTRL_PARERR ,Inducing of parity error during IO loopback test mode control" "Not affected,Flipped" bitfld.long 0x00 17. " CTRL_TIMEOUT ,Inducing of TIMEOUT error during IO loopback test mode control" "Not affected,Forced to 1" textline " " bitfld.long 0x00 16. " CTRL_DLENERR ,Inducing of data length error during IO loopback test mode control" "Not affected,Forced to 1" bitfld.long 0x00 3.--5. " ERR_SCS_PIN ,Error on chip select pin injection" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]" textline " " bitfld.long 0x00 2. " CTRL_SCS_PIN_ERR ,/SPISCS[7:0] pins error injection enable control" "Disabled,Enabled" bitfld.long 0x00 1. " LPBK_TYPE ,Module IO loopback type" "Digital,Analog" textline " " bitfld.long 0x00 0. " RXP_ENA ,Module analog loopback through receive pin enable" "Transmit,Receive" elif ((((d.l(ad:0xFFF7F400+0x134))&0xF00)==0xA00)&&(((d.l(ad:0xFFF7F400+0x134))&0x02)==0x00)) group.long 0x134++0x03 line.long 0x00 "IOLPBKTSTCR,Spi/mibspi IO Loopback Test Control Register" bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" eventfld.long 0x00 24. " SCS_FAIL_FLG ,Analog loopback /SPISCS pin compare failure" "Not failed,Failed" textline " " bitfld.long 0x00 20. " CTRL_BITERR ,Inducing of BITERR during IO loopback test mode control" "Not affected,Flipped" bitfld.long 0x00 19. " CTRL_DESYNC ,Inducing of DESYNC error during IO loopback test mode control" "Not affected,Forced to 0" textline " " bitfld.long 0x00 18. " CTRL_PARERR ,Inducing of parity error during IO loopback test mode control" "Not affected,Flipped" bitfld.long 0x00 17. " CTRL_TIMEOUT ,Inducing of TIMEOUT error during IO loopback test mode control" "Not affected,Forced to 1" textline " " bitfld.long 0x00 16. " CTRL_DLENERR ,Inducing of data length error during IO loopback test mode control" "Not affected,Forced to 1" bitfld.long 0x00 3.--5. " ERR_SCS_PIN ,Error on chip select pin injection" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]" textline " " bitfld.long 0x00 2. " CTRL_SCS_PIN_ERR ,/SPISCS[7:0] pins error injection enable control" "Disabled,Enabled" bitfld.long 0x00 1. " LPBK_TYPE ,Module IO loopback type" "Digital,Analog" else group.long 0x134++0x03 line.long 0x00 "IOLPBKTSTCR,Spi/mibspi IO Loopback Test Control Register" bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" endif sif (cpuis("RM46L*")||cpu()=="RM42L432"||cpuis("RM57L843-ZWT")) group.long 0x138++0x07 line.long 0x00 "EXTENDED_PRESCALE1,SPI Extended Prescale Register 1" hexmask.long.word 0x00 16.--26. 1. " EPRESCALE_FMT1 ,Extended prescale value for SPIFMT1" hexmask.long.word 0x00 0.--10. 1. " EPRESCALE_FMT0 ,Extended prescale value for SPIFMT0" line.long 0x04 "EXTENDED_PRESCALE2,SPI Extended Prescale Register 2" hexmask.long.word 0x04 16.--26. 1. " EPRESCALE_FMT3 ,Extended prescale value for SPIFMT1" hexmask.long.word 0x04 0.--10. 1. " EPRESCALE_FMT2 ,Extended prescale value for SPIFMT0" endif sif cpuis("RM57L843-ZWT") group.long 0x140++0x07 line.long 0x00 "ECCDIAG_CTRL,ECC Diagnostic Control Register" bitfld.long 0x00 0.--3. " ECCDIAG_EN ,ECC diagnostic mode enable key bits" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" line.long 0x04 "ECCDIAG_STAT,ECC Diagnostic Status Register" eventfld.long 0x04 17. " DEFLG[1] ,Double bit error flag" "No error,Error" eventfld.long 0x04 16. " DEFLG[0] ,Double bit error flag" "No error,Error" textline " " eventfld.long 0x04 1. " SEFLG[1] ,Single bit error flag" "No error,Error" eventfld.long 0x04 0. " SEFLG[0] ,Single bit error flag" "No error,Error" hgroup.long 0x148++0x07 hide.long 0x00 "SBERRADDR1,Single Bit Error Address Register - RXRAM" in hide.long 0x04 "SBERRADDR0,Single Bit Error Address Register - TXRAM" endif width 0x0B tree "Multi-Buffer RAM" base ad:0xFF0E0000 width 10. tree "Multi-buffer RAM Transmit Data Registers" group.long 0x0++0x03 line.long 0x00 "TXRAM0,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x4++0x03 line.long 0x00 "TXRAM1,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x8++0x03 line.long 0x00 "TXRAM2,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xC++0x03 line.long 0x00 "TXRAM3,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x10++0x03 line.long 0x00 "TXRAM4,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x14++0x03 line.long 0x00 "TXRAM5,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x18++0x03 line.long 0x00 "TXRAM6,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1C++0x03 line.long 0x00 "TXRAM7,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x20++0x03 line.long 0x00 "TXRAM8,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x24++0x03 line.long 0x00 "TXRAM9,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x28++0x03 line.long 0x00 "TXRAM10,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x2C++0x03 line.long 0x00 "TXRAM11,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x30++0x03 line.long 0x00 "TXRAM12,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x34++0x03 line.long 0x00 "TXRAM13,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x38++0x03 line.long 0x00 "TXRAM14,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x3C++0x03 line.long 0x00 "TXRAM15,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x40++0x03 line.long 0x00 "TXRAM16,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x44++0x03 line.long 0x00 "TXRAM17,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x48++0x03 line.long 0x00 "TXRAM18,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x4C++0x03 line.long 0x00 "TXRAM19,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x50++0x03 line.long 0x00 "TXRAM20,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x54++0x03 line.long 0x00 "TXRAM21,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x58++0x03 line.long 0x00 "TXRAM22,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x5C++0x03 line.long 0x00 "TXRAM23,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x60++0x03 line.long 0x00 "TXRAM24,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x64++0x03 line.long 0x00 "TXRAM25,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x68++0x03 line.long 0x00 "TXRAM26,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x6C++0x03 line.long 0x00 "TXRAM27,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x70++0x03 line.long 0x00 "TXRAM28,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x74++0x03 line.long 0x00 "TXRAM29,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x78++0x03 line.long 0x00 "TXRAM30,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x7C++0x03 line.long 0x00 "TXRAM31,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x80++0x03 line.long 0x00 "TXRAM32,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x84++0x03 line.long 0x00 "TXRAM33,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x88++0x03 line.long 0x00 "TXRAM34,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x8C++0x03 line.long 0x00 "TXRAM35,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x90++0x03 line.long 0x00 "TXRAM36,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x94++0x03 line.long 0x00 "TXRAM37,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x98++0x03 line.long 0x00 "TXRAM38,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x9C++0x03 line.long 0x00 "TXRAM39,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xA0++0x03 line.long 0x00 "TXRAM40,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xA4++0x03 line.long 0x00 "TXRAM41,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xA8++0x03 line.long 0x00 "TXRAM42,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xAC++0x03 line.long 0x00 "TXRAM43,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xB0++0x03 line.long 0x00 "TXRAM44,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xB4++0x03 line.long 0x00 "TXRAM45,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xB8++0x03 line.long 0x00 "TXRAM46,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xBC++0x03 line.long 0x00 "TXRAM47,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xC0++0x03 line.long 0x00 "TXRAM48,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xC4++0x03 line.long 0x00 "TXRAM49,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xC8++0x03 line.long 0x00 "TXRAM50,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xCC++0x03 line.long 0x00 "TXRAM51,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xD0++0x03 line.long 0x00 "TXRAM52,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xD4++0x03 line.long 0x00 "TXRAM53,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xD8++0x03 line.long 0x00 "TXRAM54,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xDC++0x03 line.long 0x00 "TXRAM55,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xE0++0x03 line.long 0x00 "TXRAM56,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xE4++0x03 line.long 0x00 "TXRAM57,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xE8++0x03 line.long 0x00 "TXRAM58,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xEC++0x03 line.long 0x00 "TXRAM59,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xF0++0x03 line.long 0x00 "TXRAM60,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xF4++0x03 line.long 0x00 "TXRAM61,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xF8++0x03 line.long 0x00 "TXRAM62,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xFC++0x03 line.long 0x00 "TXRAM63,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x100++0x03 line.long 0x00 "TXRAM64,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x104++0x03 line.long 0x00 "TXRAM65,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x108++0x03 line.long 0x00 "TXRAM66,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x10C++0x03 line.long 0x00 "TXRAM67,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x110++0x03 line.long 0x00 "TXRAM68,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x114++0x03 line.long 0x00 "TXRAM69,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x118++0x03 line.long 0x00 "TXRAM70,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x11C++0x03 line.long 0x00 "TXRAM71,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x120++0x03 line.long 0x00 "TXRAM72,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x124++0x03 line.long 0x00 "TXRAM73,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x128++0x03 line.long 0x00 "TXRAM74,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x12C++0x03 line.long 0x00 "TXRAM75,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x130++0x03 line.long 0x00 "TXRAM76,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x134++0x03 line.long 0x00 "TXRAM77,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x138++0x03 line.long 0x00 "TXRAM78,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x13C++0x03 line.long 0x00 "TXRAM79,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x140++0x03 line.long 0x00 "TXRAM80,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x144++0x03 line.long 0x00 "TXRAM81,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x148++0x03 line.long 0x00 "TXRAM82,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x14C++0x03 line.long 0x00 "TXRAM83,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x150++0x03 line.long 0x00 "TXRAM84,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x154++0x03 line.long 0x00 "TXRAM85,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x158++0x03 line.long 0x00 "TXRAM86,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x15C++0x03 line.long 0x00 "TXRAM87,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x160++0x03 line.long 0x00 "TXRAM88,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x164++0x03 line.long 0x00 "TXRAM89,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x168++0x03 line.long 0x00 "TXRAM90,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x16C++0x03 line.long 0x00 "TXRAM91,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x170++0x03 line.long 0x00 "TXRAM92,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x174++0x03 line.long 0x00 "TXRAM93,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x178++0x03 line.long 0x00 "TXRAM94,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x17C++0x03 line.long 0x00 "TXRAM95,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x180++0x03 line.long 0x00 "TXRAM96,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x184++0x03 line.long 0x00 "TXRAM97,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x188++0x03 line.long 0x00 "TXRAM98,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x18C++0x03 line.long 0x00 "TXRAM99,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x190++0x03 line.long 0x00 "TXRAM100,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x194++0x03 line.long 0x00 "TXRAM101,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x198++0x03 line.long 0x00 "TXRAM102,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x19C++0x03 line.long 0x00 "TXRAM103,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1A0++0x03 line.long 0x00 "TXRAM104,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1A4++0x03 line.long 0x00 "TXRAM105,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1A8++0x03 line.long 0x00 "TXRAM106,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1AC++0x03 line.long 0x00 "TXRAM107,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1B0++0x03 line.long 0x00 "TXRAM108,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1B4++0x03 line.long 0x00 "TXRAM109,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1B8++0x03 line.long 0x00 "TXRAM110,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1BC++0x03 line.long 0x00 "TXRAM111,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1C0++0x03 line.long 0x00 "TXRAM112,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1C4++0x03 line.long 0x00 "TXRAM113,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1C8++0x03 line.long 0x00 "TXRAM114,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1CC++0x03 line.long 0x00 "TXRAM115,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1D0++0x03 line.long 0x00 "TXRAM116,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1D4++0x03 line.long 0x00 "TXRAM117,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1D8++0x03 line.long 0x00 "TXRAM118,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1DC++0x03 line.long 0x00 "TXRAM119,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1E0++0x03 line.long 0x00 "TXRAM120,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1E4++0x03 line.long 0x00 "TXRAM121,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1E8++0x03 line.long 0x00 "TXRAM122,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1EC++0x03 line.long 0x00 "TXRAM123,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1F0++0x03 line.long 0x00 "TXRAM124,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1F4++0x03 line.long 0x00 "TXRAM125,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1F8++0x03 line.long 0x00 "TXRAM126,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1FC++0x03 line.long 0x00 "TXRAM127,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" tree.end tree "Multi-buffer RAM Receive Buffer Registers" hgroup.long 0x200++0x03 hide.long 0x00 "RXRAM0,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x204++0x03 hide.long 0x00 "RXRAM1,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x208++0x03 hide.long 0x00 "RXRAM2,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x20C++0x03 hide.long 0x00 "RXRAM3,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x210++0x03 hide.long 0x00 "RXRAM4,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x214++0x03 hide.long 0x00 "RXRAM5,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x218++0x03 hide.long 0x00 "RXRAM6,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x21C++0x03 hide.long 0x00 "RXRAM7,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x220++0x03 hide.long 0x00 "RXRAM8,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x224++0x03 hide.long 0x00 "RXRAM9,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x228++0x03 hide.long 0x00 "RXRAM10,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x22C++0x03 hide.long 0x00 "RXRAM11,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x230++0x03 hide.long 0x00 "RXRAM12,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x234++0x03 hide.long 0x00 "RXRAM13,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x238++0x03 hide.long 0x00 "RXRAM14,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x23C++0x03 hide.long 0x00 "RXRAM15,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x240++0x03 hide.long 0x00 "RXRAM16,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x244++0x03 hide.long 0x00 "RXRAM17,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x248++0x03 hide.long 0x00 "RXRAM18,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x24C++0x03 hide.long 0x00 "RXRAM19,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x250++0x03 hide.long 0x00 "RXRAM20,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x254++0x03 hide.long 0x00 "RXRAM21,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x258++0x03 hide.long 0x00 "RXRAM22,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x25C++0x03 hide.long 0x00 "RXRAM23,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x260++0x03 hide.long 0x00 "RXRAM24,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x264++0x03 hide.long 0x00 "RXRAM25,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x268++0x03 hide.long 0x00 "RXRAM26,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x26C++0x03 hide.long 0x00 "RXRAM27,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x270++0x03 hide.long 0x00 "RXRAM28,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x274++0x03 hide.long 0x00 "RXRAM29,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x278++0x03 hide.long 0x00 "RXRAM30,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x27C++0x03 hide.long 0x00 "RXRAM31,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x280++0x03 hide.long 0x00 "RXRAM32,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x284++0x03 hide.long 0x00 "RXRAM33,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x288++0x03 hide.long 0x00 "RXRAM34,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x28C++0x03 hide.long 0x00 "RXRAM35,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x290++0x03 hide.long 0x00 "RXRAM36,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x294++0x03 hide.long 0x00 "RXRAM37,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x298++0x03 hide.long 0x00 "RXRAM38,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x29C++0x03 hide.long 0x00 "RXRAM39,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2A0++0x03 hide.long 0x00 "RXRAM40,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2A4++0x03 hide.long 0x00 "RXRAM41,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2A8++0x03 hide.long 0x00 "RXRAM42,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2AC++0x03 hide.long 0x00 "RXRAM43,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2B0++0x03 hide.long 0x00 "RXRAM44,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2B4++0x03 hide.long 0x00 "RXRAM45,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2B8++0x03 hide.long 0x00 "RXRAM46,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2BC++0x03 hide.long 0x00 "RXRAM47,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2C0++0x03 hide.long 0x00 "RXRAM48,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2C4++0x03 hide.long 0x00 "RXRAM49,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2C8++0x03 hide.long 0x00 "RXRAM50,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2CC++0x03 hide.long 0x00 "RXRAM51,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2D0++0x03 hide.long 0x00 "RXRAM52,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2D4++0x03 hide.long 0x00 "RXRAM53,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2D8++0x03 hide.long 0x00 "RXRAM54,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2DC++0x03 hide.long 0x00 "RXRAM55,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2E0++0x03 hide.long 0x00 "RXRAM56,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2E4++0x03 hide.long 0x00 "RXRAM57,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2E8++0x03 hide.long 0x00 "RXRAM58,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2EC++0x03 hide.long 0x00 "RXRAM59,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2F0++0x03 hide.long 0x00 "RXRAM60,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2F4++0x03 hide.long 0x00 "RXRAM61,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2F8++0x03 hide.long 0x00 "RXRAM62,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2FC++0x03 hide.long 0x00 "RXRAM63,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x300++0x03 hide.long 0x00 "RXRAM64,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x304++0x03 hide.long 0x00 "RXRAM65,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x308++0x03 hide.long 0x00 "RXRAM66,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x30C++0x03 hide.long 0x00 "RXRAM67,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x310++0x03 hide.long 0x00 "RXRAM68,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x314++0x03 hide.long 0x00 "RXRAM69,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x318++0x03 hide.long 0x00 "RXRAM70,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x31C++0x03 hide.long 0x00 "RXRAM71,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x320++0x03 hide.long 0x00 "RXRAM72,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x324++0x03 hide.long 0x00 "RXRAM73,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x328++0x03 hide.long 0x00 "RXRAM74,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x32C++0x03 hide.long 0x00 "RXRAM75,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x330++0x03 hide.long 0x00 "RXRAM76,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x334++0x03 hide.long 0x00 "RXRAM77,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x338++0x03 hide.long 0x00 "RXRAM78,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x33C++0x03 hide.long 0x00 "RXRAM79,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x340++0x03 hide.long 0x00 "RXRAM80,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x344++0x03 hide.long 0x00 "RXRAM81,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x348++0x03 hide.long 0x00 "RXRAM82,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x34C++0x03 hide.long 0x00 "RXRAM83,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x350++0x03 hide.long 0x00 "RXRAM84,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x354++0x03 hide.long 0x00 "RXRAM85,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x358++0x03 hide.long 0x00 "RXRAM86,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x35C++0x03 hide.long 0x00 "RXRAM87,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x360++0x03 hide.long 0x00 "RXRAM88,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x364++0x03 hide.long 0x00 "RXRAM89,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x368++0x03 hide.long 0x00 "RXRAM90,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x36C++0x03 hide.long 0x00 "RXRAM91,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x370++0x03 hide.long 0x00 "RXRAM92,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x374++0x03 hide.long 0x00 "RXRAM93,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x378++0x03 hide.long 0x00 "RXRAM94,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x37C++0x03 hide.long 0x00 "RXRAM95,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x380++0x03 hide.long 0x00 "RXRAM96,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x384++0x03 hide.long 0x00 "RXRAM97,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x388++0x03 hide.long 0x00 "RXRAM98,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x38C++0x03 hide.long 0x00 "RXRAM99,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x390++0x03 hide.long 0x00 "RXRAM100,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x394++0x03 hide.long 0x00 "RXRAM101,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x398++0x03 hide.long 0x00 "RXRAM102,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x39C++0x03 hide.long 0x00 "RXRAM103,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3A0++0x03 hide.long 0x00 "RXRAM104,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3A4++0x03 hide.long 0x00 "RXRAM105,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3A8++0x03 hide.long 0x00 "RXRAM106,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3AC++0x03 hide.long 0x00 "RXRAM107,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3B0++0x03 hide.long 0x00 "RXRAM108,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3B4++0x03 hide.long 0x00 "RXRAM109,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3B8++0x03 hide.long 0x00 "RXRAM110,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3BC++0x03 hide.long 0x00 "RXRAM111,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3C0++0x03 hide.long 0x00 "RXRAM112,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3C4++0x03 hide.long 0x00 "RXRAM113,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3C8++0x03 hide.long 0x00 "RXRAM114,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3CC++0x03 hide.long 0x00 "RXRAM115,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3D0++0x03 hide.long 0x00 "RXRAM116,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3D4++0x03 hide.long 0x00 "RXRAM117,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3D8++0x03 hide.long 0x00 "RXRAM118,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3DC++0x03 hide.long 0x00 "RXRAM119,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3E0++0x03 hide.long 0x00 "RXRAM120,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3E4++0x03 hide.long 0x00 "RXRAM121,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3E8++0x03 hide.long 0x00 "RXRAM122,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3EC++0x03 hide.long 0x00 "RXRAM123,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3F0++0x03 hide.long 0x00 "RXRAM124,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3F4++0x03 hide.long 0x00 "RXRAM125,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3F8++0x03 hide.long 0x00 "RXRAM126,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3FC++0x03 hide.long 0x00 "RXRAM127,Multi-buffer RAM Receive Buffer Register" in tree.end width 0x0B tree.end tree.end tree "SPI2" base ad:0xFFF7F600 width 6. group.long 0x00++0x03 line.long 0x00 "GCR0,Global Control Register 0" bitfld.long 0x00 0. " NRESET ,This is the reset bit for the module" "Reset,No reset" if (((d.l(ad:0xFFF7F600+0x04))&0x03)==0x03) group.long 0x04++0x03 line.long 0x00 "GCR1,Global Control Register 1" bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI pin direction determination" "Input/output,Output/input" bitfld.long 0x00 24. " SPIEN ,SPI enable" "Not active,Active" bitfld.long 0x00 16. " LOOP_BACK ,Internal Loop-back test mode" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " POWERDOWN ,SPI state machines power down state enable" "Active,Power down" bitfld.long 0x00 1. " CLKMOD ,Clock mode" "External,Internal" elif (((d.l(ad:0xFFF7F600+0x04))&0x03)==0x02) group.long 0x04++0x03 line.long 0x00 "GCR1,Global Control Register 1" bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI pin direction determination" "Input/output,Output/input" bitfld.long 0x00 24. " SPIEN ,SPI enable" "Not active,Active" bitfld.long 0x00 8. " POWERDOWN ,SPI state machines power down state enable" "Active,Power down" textline " " bitfld.long 0x00 1. " CLKMOD ,Clock mode" "External,Internal" elif (((d.l(ad:0xFFF7F600+0x04))&0x03)==0x01) group.long 0x04++0x03 line.long 0x00 "GCR1,Global Control Register 1" bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI pin direction determination" "Input/output,Output/input" bitfld.long 0x00 24. " SPIEN ,SPI enable" "Not active,Active" bitfld.long 0x00 8. " POWERDOWN ,SPI state machines power down state enable" "Active,Power down" textline " " bitfld.long 0x00 1. " CLKMOD ,Clock mode" "External,Internal" else group.long 0x04++0x03 line.long 0x00 "GCR1,Global Control Register 1" bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI pin direction determination" "Input/output,Output/input" bitfld.long 0x00 24. " SPIEN ,SPI enable" "Not active,Active" bitfld.long 0x00 8. " POWERDOWN ,SPI state machines power down state enable" "Active,Power down" textline " " bitfld.long 0x00 1. " CLKMOD ,Clock mode" "External,Internal" endif if (((d.l(ad:0xFFF7F600+0x04))&0x01)==0x01) group.long 0x08++0x03 line.long 0x00 "INT0,Interrupt Register" bitfld.long 0x00 24. " ENABLE_HIGHZ ,/SPIENA pin High-z enable" "Disabled,Enabled" textline " " sif (cpu()!="RM42L432") bitfld.long 0x00 16. " DMA_REQ_EN ,DMA request enable" "Not used,Generated" endif textline " " bitfld.long 0x00 9. " TXINTENA ,Transmit interrupt enable" "Not generated,Generated" bitfld.long 0x00 8. " RXINTENA ,Receive interrupt enable" "Not generated,Generated" textline " " bitfld.long 0x00 6. " RXOVRNINTENA ,Overrun interrupt enable" "Not generated,Generated" bitfld.long 0x00 4. " BITERRENA ,Enables interrupt on bit error" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " DESYNCENA ,Enables interrupt on De-synchronized slave" "Disabled,Enabled" bitfld.long 0x00 2. " PARERRENA ,Enables interrupt on parity error" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " TIMEOUTENA ,Enables interrupt on ENA signal Time-out" "Disabled,Enabled" bitfld.long 0x00 0. " DLEN_ERR_ENA ,Data length error interrupt enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "INT0,Interrupt Register" bitfld.long 0x00 24. " ENABLE_HIGHZ ,/SPIENA pin High-z enable" "Disabled,Enabled" textline " " sif (cpu()!="RM42L432") bitfld.long 0x00 16. " DMA_REQ_EN ,DMA request enable" "Not used,Generated" endif textline " " bitfld.long 0x00 9. " TXINTENA ,Transmit interrupt enable" "Not generated,Generated" bitfld.long 0x00 8. " RXINTENA ,Receive interrupt enable" "Not generated,Generated" textline " " bitfld.long 0x00 6. " RXOVRNINTENA ,Overrun interrupt enable" "Not generated,Generated" bitfld.long 0x00 4. " BITERRENA ,Enables interrupt on bit error" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " PARERRENA ,Enables interrupt on parity error" "Disabled,Enabled" bitfld.long 0x00 1. " TIMEOUTENA ,Enables interrupt on ENA signal Time-out" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " DLEN_ERR_ENA ,Data length error interrupt enable" "Disabled,Enabled" endif if (((d.l(ad:0xFFF7F600+0x04))&0x01)==0x01) group.long 0x0C++0x03 line.long 0x00 "LVL,Interrupt Level Register" bitfld.long 0x00 9. " TXINTLVL ,Transmit interrupt level" "INT0,INT1" bitfld.long 0x00 8. " RXINTLVL ,Receive interrupt level" "INT0,INT1" bitfld.long 0x00 6. " RXOVRNINTLVL ,Receive overrun interrupt level" "INT0,INT1" textline " " bitfld.long 0x00 4. " BITERRLVL ,Bit error interrupt level" "INT0,INT1" bitfld.long 0x00 3. " DESYNCLVL ,De-synchronized slave interrupt level" "INT0,INT1" bitfld.long 0x00 2. " PARERRLVL ,Parity error interrupt level" "INT0,INT1" textline " " bitfld.long 0x00 1. " TIMEOUTLVL ,/SPIENA pin Time-out interrupt level" "INT0,INT1" bitfld.long 0x00 0. " DLEN_ERR_LVL ,Data length error interrupt enable level" "INT0,INT1" else group.long 0x0C++0x03 line.long 0x00 "LVL,Interrupt Level Register" bitfld.long 0x00 9. " TXINTLVL ,Transmit interrupt level" "INT0,INT1" bitfld.long 0x00 8. " RXINTLVL ,Receive interrupt level" "INT0,INT1" bitfld.long 0x00 6. " RXOVRNINTLVL ,Receive overrun interrupt level" "INT0,INT1" textline " " bitfld.long 0x00 4. " BITERRLVL ,Bit error interrupt level" "INT0,INT1" bitfld.long 0x00 2. " PARERRLVL ,Parity error interrupt level" "INT0,INT1" bitfld.long 0x00 1. " TIMEOUTLVL ,/SPIENA pin Time-out interrupt level" "INT0,INT1" textline " " bitfld.long 0x00 0. " DLEN_ERR_LVL ,Data length error interrupt enable level" "INT0,INT1" endif if (((d.l(ad:0xFFF7F600+0x04))&0x01)==0x01) group.long 0x10++0x03 line.long 0x00 "FLG,Flag Register" bitfld.long 0x00 24. " BUF_INIT_ACTIVE ,Multibuffer initialization active" "Finished,Not finished" bitfld.long 0x00 9. " TXINTFLG ,Transmitter empty interrupt flag" "Full,Empty" textline " " eventfld.long 0x00 8. " RXINTFLG ,Receiver full interrupt flag" "Empty,Full" eventfld.long 0x00 6. " RXOVRNINTFLG ,Receiver overrun flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 4. " BITERRFLG ,Internal transmit data and transmitted data mismatch" "Not occurred,Occurred" eventfld.long 0x00 3. " DESYNCFLG ,Slave device De-Synchronization" "Not detected,Detected" textline " " eventfld.long 0x00 2. " PARITYERRFLG ,Parity error flag" "Not detected,Detected" eventfld.long 0x00 1. " TIMEOUTFLG ,Time-out due to Non-activation of ENA signal" "Not occurred,Occurred" textline " " eventfld.long 0x00 0. " DLEN_ERR_FLG ,Data length error flag" "Not occurred,Occurred" else group.long 0x10++0x03 line.long 0x00 "FLG,Flag Register" bitfld.long 0x00 24. " BUF_INIT_ACTIVE ,Multibuffer initialization active" "Not completed,Completed" bitfld.long 0x00 9. " TXINTFLG ,Transmitter empty interrupt flag" "No empty,Empty" textline " " eventfld.long 0x00 8. " RXINTFLG ,Receiver full interrupt flag" "No full,Full" eventfld.long 0x00 6. " RXOVRNINTFLG ,Receiver overrun flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 4. " BITERRFLG ,Internal transmit data and transmitted data mismatch" "Not occurred,Occurred" eventfld.long 0x00 2. " PARITYERRFLG ,Parity error flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 1. " TIMEOUTFLG ,Time-out due to Non-activation of ENA signal" "Not occurred,Occurred" eventfld.long 0x00 0. " DLEN_ERR_FLG ,Data length error flag" "Not occurred,Occurred" endif width 13. tree "SPI Pin Control Registers" tree "SPI Pin Control Registers 0-5" group.long 0x14++0x03 line.long 0x00 "PC0,Pin Control Register 0" bitfld.long 0x00 31. " SOMIFUN7 ,Slave out master in function 7" "GPIO,Spi/mibspi" bitfld.long 0x00 30. " SOMIFUN6 ,Slave out master in function 6" "GPIO,Spi/mibspi" bitfld.long 0x00 29. " SOMIFUN5 ,Slave out master in function 5" "GPIO,Spi/mibspi" textline " " bitfld.long 0x00 28. " SOMIFUN4 ,Slave out master in function 4" "GPIO,Spi/mibspi" bitfld.long 0x00 27. " SOMIFUN3 ,Slave out master in function 3" "GPIO,Spi/mibspi" bitfld.long 0x00 26. " SOMIFUN2 ,Slave out master in function 2" "GPIO,Spi/mibspi" textline " " bitfld.long 0x00 25. " SOMIFUN1 ,Slave out master in function 1" "GPIO,Spi/mibspi" bitfld.long 0x00 24. " SOMIFUN0 ,Slave out master in function 0" "GPIO,Spi/mibspi" bitfld.long 0x00 23. " SIMOFUN7 ,Slave in master out function 7" "GPIO,Spi/mibspi" textline " " bitfld.long 0x00 22. " SIMOFUN6 ,Slave in master out function 6" "GPIO,Spi/mibspi" bitfld.long 0x00 21. " SIMOFUN5 ,Slave in master out function 5" "GPIO,Spi/mibspi" bitfld.long 0x00 20. " SIMOFUN4 ,Slave in master out function 4" "GPIO,Spi/mibspi" textline " " bitfld.long 0x00 19. " SIMOFUN3 ,Slave in master out function 3" "GPIO,Spi/mibspi" bitfld.long 0x00 18. " SIMOFUN2 ,Slave in master out function 2" "GPIO,Spi/mibspi" bitfld.long 0x00 17. " SIMOFUN1 ,Slave in master out function 1" "GPIO,Spi/mibspi" textline " " bitfld.long 0x00 16. " SIMOFUN0 ,Slave in master out function 0" "GPIO,Spi/mibspi" bitfld.long 0x00 11. " SOMIFUN0 ,Slave out master in function" "GPIO,Spi/mibspi" bitfld.long 0x00 10. " SIMOFUN0 ,Slave in master out function" "GPIO,Spi/mibspi" textline " " bitfld.long 0x00 9. " CLKFUN ,Spi/mibspi clock function" "GPIO,Spi/mibspi" bitfld.long 0x00 8. " ENAFUN ,/SPIENA function" "GPIO,Spi/mibspi" bitfld.long 0x00 7. " SCSFUN7 ,/SPISCS7 function" "GPIO,SPI" textline " " bitfld.long 0x00 6. " SCSFUN6 ,/SPISCS6 function" "GPIO,SPI" bitfld.long 0x00 5. " SCSFUN5 ,/SPISCS5 function" "GPIO,SPI" bitfld.long 0x00 4. " SCSFUN4 ,/SPISCS4 function" "GPIO,SPI" textline " " bitfld.long 0x00 3. " SCSFUN3 ,/SPISCS3 function" "GPIO,SPI" bitfld.long 0x00 2. " SCSFUN2 ,/SPISCS2 function" "GPIO,SPI" bitfld.long 0x00 1. " SCSFUN1 ,/SPISCS1 function" "GPIO,SPI" textline " " bitfld.long 0x00 0. " SCSFUN0 ,/SPISCS0 function" "GPIO,SPI" group.long 0x18++0x03 line.long 0x00 "PC1,Pin Control Register 1" bitfld.long 0x00 31. " SOMIDIR7 ,SPISOMI7 direction" "Input,Output" bitfld.long 0x00 30. " SOMIDIR6 ,SPISOMI6 direction" "Input,Output" bitfld.long 0x00 29. " SOMIDIR5 ,SPISOMI5 direction" "Input,Output" textline " " bitfld.long 0x00 28. " SOMIDIR4 ,SPISOMI4 direction" "Input,Output" bitfld.long 0x00 27. " SOMIDIR3 ,SPISOMI3 direction" "Input,Output" bitfld.long 0x00 26. " SOMIDIR2 ,SPISOMI2 direction" "Input,Output" textline " " bitfld.long 0x00 25. " SOMIDIR1 ,SPISOMI1 direction" "Input,Output" bitfld.long 0x00 24. " SOMIDIR0 ,SPISOMI0 direction" "Input,Output" bitfld.long 0x00 23. " SIMODIR7 ,SPISIMO7 direction" "Input,Output" textline " " bitfld.long 0x00 22. " SIMODIR6 ,SPISIMO6 direction" "Input,Output" bitfld.long 0x00 21. " SIMODIR5 ,SPISIMO5 direction" "Input,Output" bitfld.long 0x00 20. " SIMODIR4 ,SPISIMO4 direction" "Input,Output" textline " " bitfld.long 0x00 19. " SIMODIR3 ,SPISIMO3 direction" "Input,Output" bitfld.long 0x00 18. " SIMODIR2 ,SPISIMO2 direction" "Input,Output" bitfld.long 0x00 17. " SIMODIR1 ,SPISIMO1 direction" "Input,Output" textline " " bitfld.long 0x00 16. " SIMODIR0 ,SPISIMO0 direction" "Input,Output" bitfld.long 0x00 11. " SOMIDIR0 ,SPISOMI0 direction" "Input,Output" bitfld.long 0x00 10. " SIMODIR0 ,SPISIMO0 direction" "Input,Output" textline " " bitfld.long 0x00 9. " CLKDIR ,SPICLK direction" "Input,Output" bitfld.long 0x00 8. " ENADIR ,/SPIENA direction" "Input,Output" bitfld.long 0x00 7. " SCSDIR7 ,/SPISCS7 direction" "Input,Output" textline " " bitfld.long 0x00 6. " SCSDIR6 ,/SPISCS6 direction" "Input,Output" bitfld.long 0x00 5. " SCSDIR5 ,/SPISCS5 direction" "Input,Output" bitfld.long 0x00 4. " SCSDIR4 ,/SPISCS4 direction" "Input,Output" textline " " bitfld.long 0x00 3. " SCSDIR3 ,/SPISCS3 direction" "Input,Output" bitfld.long 0x00 2. " SCSDIR2 ,/SPISCS2 direction" "Input,Output" bitfld.long 0x00 1. " SCSDIR1 ,/SPISCS1 direction" "Input,Output" textline " " bitfld.long 0x00 0. " SCSDIR0 ,/SPISCS0 direction" "Input,Output" rgroup.long 0x1C++0x03 line.long 0x00 "PC2,Pin Control Register 2" bitfld.long 0x00 31. " SOMIDIN7 ,SPISOMI7 data in" "Low,High" bitfld.long 0x00 30. " SOMIDIN6 ,SPISOMI6 data in" "Low,High" bitfld.long 0x00 29. " SOMIDIN5 ,SPISOMI5 data in" "Low,High" textline " " bitfld.long 0x00 28. " SOMIDIN4 ,SPISOMI4 data in" "Low,High" bitfld.long 0x00 27. " SOMIDIN3 ,SPISOMI3 data in" "Low,High" bitfld.long 0x00 26. " SOMIDIN2 ,SPISOMI2 data in" "Low,High" textline " " bitfld.long 0x00 25. " SOMIDIN1 ,SPISOMI1 data in" "Low,High" bitfld.long 0x00 24. " SOMIDIN0 ,SPISOMI0 data in" "Low,High" bitfld.long 0x00 23. " SIMODIN7 ,SPISIMO7 data in" "Low,High" textline " " bitfld.long 0x00 22. " SIMODIN6 ,SPISIMO6 data in" "Low,High" bitfld.long 0x00 21. " SIMODIN5 ,SPISIMO5 data in" "Low,High" bitfld.long 0x00 20. " SIMODIN4 ,SPISIMO4 data in" "Low,High" textline " " bitfld.long 0x00 19. " SIMODIN3 ,SPISIMO3 data in" "Low,High" bitfld.long 0x00 18. " SIMODIN2 ,SPISIMO2 data in" "Low,High" bitfld.long 0x00 17. " SIMODIN1 ,SPISIMO1 data in" "Low,High" textline " " bitfld.long 0x00 16. " SIMODIN0 ,SPISIMO0 data in" "Low,High" bitfld.long 0x00 11. " SOMIDIN0 ,SPISOMI0 data in" "Low,High" bitfld.long 0x00 10. " SIMODIN0 ,SPISIMO0 data in" "Low,High" textline " " bitfld.long 0x00 9. " CLKDIN ,Clock data in" "Low,High" bitfld.long 0x00 8. " ENADIN ,/SPIENA data in" "Low,High" bitfld.long 0x00 7. " SCSDIN7 ,SPISCS7 data in" "Low,High" textline " " bitfld.long 0x00 6. " SCSDIN6 ,SPISCS6 data in" "Low,High" bitfld.long 0x00 5. " SCSDIN5 ,SPISCS5 data in" "Low,High" bitfld.long 0x00 4. " SCSDIN4 ,SPISCS4 data in" "Low,High" textline " " bitfld.long 0x00 3. " SCSDIN3 ,SPISCS3 data in" "Low,High" bitfld.long 0x00 2. " SCSDIN2 ,SPISCS2 data in" "Low,High" bitfld.long 0x00 1. " SCSDIN1 ,SPISCS1 data in" "Low,High" textline " " bitfld.long 0x00 0. " SCSDIN0 ,SPISCS0 data in" "Low,High" group.long 0x20++0x0B line.long 0x00 "PC3,Pin Control Register 3" bitfld.long 0x00 31. " SOMIDOUT7 ,SPISOMI7 dataout write" "Low,High" bitfld.long 0x00 30. " SOMIDOUT6 ,SPISOMI6 dataout write" "Low,High" textline " " bitfld.long 0x00 29. " SOMIDOUT5 ,SPISOMI5 dataout write" "Low,High" bitfld.long 0x00 28. " SOMIDOUT4 ,SPISOMI4 dataout write" "Low,High" textline " " bitfld.long 0x00 27. " SOMIDOUT3 ,SPISOMI3 dataout write" "Low,High" bitfld.long 0x00 26. " SOMIDOUT2 ,SPISOMI2 dataout write" "Low,High" textline " " bitfld.long 0x00 25. " SOMIDOUT1 ,SPISOMI1 dataout write" "Low,High" bitfld.long 0x00 24. " SOMIDOUT0 ,SPISOMI0 dataout write" "Low,High" textline " " bitfld.long 0x00 23. " SIMODOUT7 ,SPISIMO7 dataout write" "Low,High" bitfld.long 0x00 22. " SIMODOUT6 ,SPISIMO6 dataout write" "Low,High" textline " " bitfld.long 0x00 21. " SIMODOUT5 ,SPISIMO5 dataout write" "Low,High" bitfld.long 0x00 20. " SIMODOUT4 ,SPISIMO4 dataout write" "Low,High" textline " " bitfld.long 0x00 19. " SIMODOUT3 ,SPISIMO3 dataout write" "Low,High" bitfld.long 0x00 18. " SIMODOUT2 ,SPISIMO2 dataout write" "Low,High" textline " " bitfld.long 0x00 17. " SIMODOUT1 ,SPISIMO1 dataout write" "Low,High" bitfld.long 0x00 16. " SIMODOUT0 ,SPISIMO0 dataout write" "Low,High" textline " " bitfld.long 0x00 11. " SOMIDOUT0 ,SPISOMI0 dataout write" "Low,High" bitfld.long 0x00 10. " SIMODOUT0 ,SPISIMO0 dataout write" "Low,High" textline " " bitfld.long 0x00 9. " CLKDOUT ,SPICLK dataout write" "Low,High" bitfld.long 0x00 8. " ENADOUT ,/SPIENA dataout write" "Low,High" textline " " bitfld.long 0x00 7. " SCSDOUT7 ,SPISCS7 dataout write" "Low,High" bitfld.long 0x00 6. " SCSDOUT6 ,SPISCS6 dataout write" "Low,High" textline " " bitfld.long 0x00 5. " SCSDOUT5 ,SPISCS5 dataout write" "Low,High" bitfld.long 0x00 4. " SCSDOUT4 ,SPISCS4 dataout write" "Low,High" textline " " bitfld.long 0x00 3. " SCSDOUT3 ,SPISCS3 dataout write" "Low,High" bitfld.long 0x00 2. " SCSDOUT2 ,SPISCS2 dataout write" "Low,High" textline " " bitfld.long 0x00 1. " SCSDOUT1 ,SPISCS1 dataout write" "Low,High" bitfld.long 0x00 0. " SCSDOUT0 ,SPISCS0 dataout write" "Low,High" line.long 0x04 "PC4,Pin Control Register 4" bitfld.long 0x04 31. " SOMISET7 ,SPISOMI7 dataout set" "Not set,Set" bitfld.long 0x04 30. " SOMISET6 ,SPISOMI6 dataout set" "Not set,Set" textline " " bitfld.long 0x04 29. " SOMISET5 ,SPISOMI5 dataout set" "Not set,Set" bitfld.long 0x04 28. " SOMISET4 ,SPISOMI4 dataout set" "Not set,Set" textline " " bitfld.long 0x04 27. " SOMISET3 ,SPISOMI3 dataout set" "Not set,Set" bitfld.long 0x04 26. " SOMISET2 ,SPISOMI2 dataout set" "Not set,Set" textline " " bitfld.long 0x04 25. " SOMISET1 ,SPISOMI1 dataout set" "Not set,Set" bitfld.long 0x04 24. " SOMISET0 ,SPISOMI0 dataout set" "Not set,Set" textline " " bitfld.long 0x04 23. " SIMOSET7 ,SPISIMO7 dataout set" "Not set,Set" bitfld.long 0x04 22. " SIMOSET6 ,SPISIMO6 dataout set" "Not set,Set" textline " " bitfld.long 0x04 21. " SIMOSET5 ,SPISIMO5 dataout set" "Not set,Set" bitfld.long 0x04 20. " SIMOSET4 ,SPISIMO4 dataout set" "Not set,Set" textline " " bitfld.long 0x04 19. " SIMOSET3 ,SPISIMO3 dataout set" "Not set,Set" bitfld.long 0x04 18. " SIMOSET2 ,SPISIMO2 dataout set" "Not set,Set" textline " " bitfld.long 0x04 17. " SIMOSET1 ,SPISIMO1 dataout set" "Not set,Set" bitfld.long 0x04 16. " SIMOSET0 ,SPISIMO0 dataout set" "Not set,Set" textline " " bitfld.long 0x04 11. " SOMISET0 ,SPISOMI0 dataout set" "Not set,Set" bitfld.long 0x04 10. " SIMOSET0 ,SPISIMO0 dataout set" "Not set,Set" textline " " bitfld.long 0x04 9. " CLKSET ,SPICLK dataout set" "Not set,Set" bitfld.long 0x04 8. " ENASET ,/SPIENA dataout set" "Not set,Set" textline " " bitfld.long 0x04 7. " SCSSET7 ,SPISCS7 dataout set" "Not set,Set" bitfld.long 0x04 6. " SCSSET6 ,SPISCS6 dataout set" "Not set,Set" textline " " bitfld.long 0x04 5. " SCSSET5 ,SPISCS5 dataout set" "Not set,Set" bitfld.long 0x04 4. " SCSSET4 ,SPISCS4 dataout set" "Not set,Set" textline " " bitfld.long 0x04 3. " SCSSET3 ,SPISCS3 dataout set" "Not set,Set" bitfld.long 0x04 2. " SCSSET2 ,SPISCS2 dataout set" "Not set,Set" textline " " bitfld.long 0x04 1. " SCSSET1 ,SPISCS1 dataout set" "Not set,Set" bitfld.long 0x04 0. " SCSSET0 ,SPISCS0 dataout set" "Not set,Set" line.long 0x08 "PC5,Pin Control Register 5" bitfld.long 0x08 31. " SOMICLR7 ,SPISOMI7 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 30. " SOMICLR6 ,SPISOMI6 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 29. " SOMICLR5 ,SPISOMI5 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 28. " SOMICLR4 ,SPISOMI4 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 27. " SOMICLR3 ,SPISOMI3 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 26. " SOMICLR2 ,SPISOMI2 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 25. " SOMICLR1 ,SPISOMI1 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 24. " SOMICLR0 ,SPISOMI0 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 23. " SIMOCLR7 ,SPISIMO7 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 22. " SIMOCLR6 ,SPISIMO6 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 21. " SIMOCLR5 ,SPISIMO5 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 20. " SIMOCLR4 ,SPISIMO4 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 19. " SIMOCLR3 ,SPISIMO3 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 18. " SIMOCLR2 ,SPISIMO2 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 17. " SIMOCLR1 ,SPISIMO1 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 16. " SIMOCLR0 ,SPISIMO0 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 11. " SOMICLR0 ,SPISOMI0 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 10. " SIMOCLR0 ,SPISIMO0 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 9. " CLKCLR ,SPICLK dataout clear" "Not cleared,Cleared" bitfld.long 0x08 8. " ENACLR ,/SPIENA dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 7. " SCSCLR7 ,SPISCS7 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 6. " SCSCLR6 ,SPISCS6 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 5. " SCSCLR5 ,SPISCS5 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 4. " SCSCLR4 ,SPISCS4 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 3. " SCSCLR3 ,SPISCS3 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 2. " SCSCLR2 ,SPISCS2 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 1. " SCSCLR1 ,SPISCS1 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 0. " SCSCLR0 ,SPISCS0 dataout clear" "Not cleared,Cleared" tree.end tree "SPI Pin Control Registers 6-8" group.long 0x2C++0x03 line.long 0x00 "PC6,Pin Control Register 1" bitfld.long 0x00 31. " SOMIPDR7 ,SPISOMI7 open drain enable" "High,Tri-stated" bitfld.long 0x00 30. " SOMIPDR6 ,SPISOMI6 open drain enable" "High,Tri-stated" bitfld.long 0x00 29. " SOMIPDR5 ,SPISOMI5 open drain enable" "High,Tri-stated" textline " " bitfld.long 0x00 28. " SOMIPDR4 ,SPISOMI4 open drain enable" "High,Tri-stated" bitfld.long 0x00 27. " SOMIPDR3 ,SPISOMI3 open drain enable" "High,Tri-stated" bitfld.long 0x00 26. " SOMIPDR2 ,SPISOMI2 open drain enable" "High,Tri-stated" textline " " bitfld.long 0x00 25. " SOMIPDR1 ,SPISOMI1 open drain enable" "High,Tri-stated" bitfld.long 0x00 24. " SOMIPDR0 ,SPISOMI0 open drain enable" "High,Tri-stated" bitfld.long 0x00 23. " SIMOPDR7 ,SPISIMO7 open drain enable" "High,Tri-stated" textline " " bitfld.long 0x00 22. " SIMOPDR6 ,SPISIMO6 open drain enable" "High,Tri-stated" bitfld.long 0x00 21. " SIMOPDR5 ,SPISIMO5 open drain enable" "High,Tri-stated" bitfld.long 0x00 20. " SIMOPDR4 ,SPISIMO4 open drain enable" "High,Tri-stated" textline " " bitfld.long 0x00 19. " SIMOPDR3 ,SPISIMO3 open drain enable" "High,Tri-stated" bitfld.long 0x00 18. " SIMOPDR2 ,SPISIMO2 open drain enable" "High,Tri-stated" bitfld.long 0x00 17. " SIMOPDR1 ,SPISIMO1 open drain enable" "High,Tri-stated" textline " " bitfld.long 0x00 16. " SIMOPDR0 ,SPISIMO0 open drain enable" "High,Tri-stated" bitfld.long 0x00 11. " SOMIPDR0 ,SPISOMI0 open drain enable" "High,Tri-stated" bitfld.long 0x00 10. " SIMOPDR0 ,SPISIMO0 open drain enable" "High,Tri-stated" textline " " bitfld.long 0x00 9. " CLKPDR ,SPICLK open drain enable" "High,Tri-stated" bitfld.long 0x00 8. " ENAPDR ,/SPIENA open drain enable" "High,Tri-stated" bitfld.long 0x00 7. " SCSPDR7 ,/SPISCS7 open drain" "High,Tri-stated" textline " " bitfld.long 0x00 6. " SCSPDR6 ,/SPISCS6 open drain" "High,Tri-stated" bitfld.long 0x00 5. " SCSPDR5 ,/SPISCS5 open drain" "High,Tri-stated" bitfld.long 0x00 4. " SCSPDR4 ,/SPISCS4 open drain" "High,Tri-stated" textline " " bitfld.long 0x00 3. " SCSPDR3 ,/SPISCS3 open drain" "High,Tri-stated" bitfld.long 0x00 2. " SCSPDR2 ,/SPISCS2 open drain" "High,Tri-stated" bitfld.long 0x00 1. " SCSPDR1 ,/SPISCS1 open drain" "High,Tri-stated" textline " " bitfld.long 0x00 0. " SCSPDR0 ,/SPISCS0 open drain" "High,Tri-stated" group.long 0x30++0x03 line.long 0x00 "PC7,Pin Control Register 7" bitfld.long 0x00 31. " SOMIPDIS7 ,SPISOMI7 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 30. " SOMIPDIS6 ,SPISOMI6 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 29. " SOMIPDIS5 ,SPISOMI5 pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 28. " SOMIPDIS4 ,SPISOMI4 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 27. " SOMIPDIS3 ,SPISOMI3 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 26. " SOMIPDIS2 ,SPISOMI2 pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 25. " SOMIPDIS1 ,SPISOMI1 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 24. " SOMIPDIS0 ,SPISOMI0 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 23. " SIMOPDIS7 ,SPISIMO7 pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 22. " SIMOPDIS6 ,SPISIMO6 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 21. " SIMOPDIS5 ,SPISIMO5 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 20. " SIMOPDIS4 ,SPISIMO4 pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 19. " SIMOPDIS3 ,SPISIMO3 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 18. " SIMOPDIS2 ,SPISIMO2 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 17. " SIMOPDIS1 ,SPISIMO1 pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 16. " SIMOPDIS0 ,SPISIMO0 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 11. " SOMIPDIS0 ,SPISOMI0 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 10. " SIMOPDIS0 ,SPISIMO pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 9. " CLKPDIS ,SPICLK pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 8. " ENAPDIS ,SPIENA pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 7. " SCSPDIS7 ,SPISCS7 pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 6. " SCSPDIS6 ,SPISCS6 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 5. " SCSPDIS5 ,SPISCS5 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 4. " SCSPDIS4 ,SPISCS4 pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 3. " SCSPDIS3 ,SPISCS3 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 2. " SCSPDIS2 ,SPISCS2 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 1. " SCSPDIS1 ,SPISCS1 pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 0. " SCSPDIS0 ,SPISCS0 pull control enable/disable" "Enabled,Disabled" group.long 0x34++0x03 line.long 0x00 "PC8,Pin Control Register 8" bitfld.long 0x00 31. " SOMIPSEL7 ,SPISOMI7 pull select" "Pull down,Pull up" bitfld.long 0x00 30. " SOMIPSEL6 ,SPISOMI6 pull select" "Pull down,Pull up" bitfld.long 0x00 29. " SOMIPSEL5 ,SPISOMI5 pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 28. " SOMIPSEL4 ,SPISOMI4 pull select" "Pull down,Pull up" bitfld.long 0x00 27. " SOMIPSEL3 ,SPISOMI3 pull select" "Pull down,Pull up" bitfld.long 0x00 26. " SOMIPSEL2 ,SPISOMI2 pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 25. " SOMIPSEL1 ,SPISOMI1 pull select" "Pull down,Pull up" bitfld.long 0x00 24. " SOMIPSEL0 ,SPISOMI0 pull select" "Pull down,Pull up" bitfld.long 0x00 23. " SIMOPSEL7 ,SPISIMO7 pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 22. " SIMOPSEL6 ,SPISIMO6 pull select" "Pull down,Pull up" bitfld.long 0x00 21. " SIMOPSEL5 ,SPISIMO5 pull select" "Pull down,Pull up" bitfld.long 0x00 20. " SIMOPSEL4 ,SPISIMO4 pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 19. " SIMOPSEL3 ,SPISIMO3 pull select" "Pull down,Pull up" bitfld.long 0x00 18. " SIMOPSEL2 ,SPISIMO2 pull select" "Pull down,Pull up" bitfld.long 0x00 17. " SIMOPSEL1 ,SPISIMO1 pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 16. " SIMOPSEL0 ,SPISIMO0 pull select" "Pull down,Pull up" bitfld.long 0x00 11. " SOMIPSEL ,SPISOMI pull select" "Pull down,Pull up" bitfld.long 0x00 10. " SIMOPSEL ,SPISIMO pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 9. " CLKPSEL ,SPICLK pull select" "Pull down,Pull up" bitfld.long 0x00 8. " ENAPSEL ,SPIENA pull select" "Pull down,Pull up" bitfld.long 0x00 7. " SCSPSEL7 ,/SPISCS7 pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 6. " SCSPSEL6 ,/SPISCS6 pull select" "Pull down,Pull up" bitfld.long 0x00 5. " SCSPSEL5 ,/SPISCS5 pull select" "Pull down,Pull up" bitfld.long 0x00 4. " SCSPSEL4 ,/SPISCS4 pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 3. " SCSPSEL3 ,/SPISCS3 pull select" "Pull down,Pull up" bitfld.long 0x00 2. " SCSPSEL2 ,/SPISCS2 pull select" "Pull down,Pull up" bitfld.long 0x00 1. " SCSPSEL1 ,/SPISCS1 pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 0. " SCSPSEL0 ,/SPISCS0 pull select" "Pull down,Pull up" tree.end tree.end width 7. textline " " if (((d.l(ad:0xFFF7F600+0x04))&0x1000000)==0x1000000) group.long 0x38++0x03 line.long 0x00 "DAT0,Transmit Data Register 0" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI / mibspi transmit data" else rgroup.long 0x38++0x03 line.long 0x00 "DAT0,Transmit Data Register 0" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI / mibspi transmit data" endif if (((d.l(ad:0xFFF7F600+0x04))&0x01)==0x01) group.long 0x3C++0x03 line.long 0x00 "DAT1,Transmit Data Register 1" bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Not active,Active" bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled" bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" textline " " hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Spi/mibspi transmit data" else group.long 0x3C++0x03 line.long 0x00 "DAT1,Transmit Data Register 1" bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Spi/mibspi transmit data" endif hgroup.long 0x40++0x03 hide.long 0x00 "BUF,Receive Buffer Register" in if (((d.l(ad:0xFFF7F600+0x04))&0x01)==0x01) rgroup.long 0x44++0x03 line.long 0x00 "EMU,Emulation Register" bitfld.long 0x00 31. " RXEMPTY ,Receive data buffer empty" "No empty,Empty" bitfld.long 0x00 30. " RXOVR ,Receive data buffer overrun" "No overrun,Overrun" bitfld.long 0x00 29. " TXFULL ,Transmit data buffer full" "Empty,Full" textline " " bitfld.long 0x00 28. " BITERR ,Mismatch of internal transmit data and transmitted data" "Not occurred,Occurred" bitfld.long 0x00 27. " DESYNC ,De-synchronization of slave device" "No de-synchronized,De-synchronized" bitfld.long 0x00 26. " PARITYERR ,Calculated parity differs from received parity bit" "No error,Error" textline " " bitfld.long 0x00 25. " TIMEOUT ,Time-out due to Non-activation of ENA pin" "Not occurred,Occurred" bitfld.long 0x00 24. " DLENERR ,Data length error flag" "No error,Error" hexmask.long.byte 0x00 16.--23. 1. " LCSNR ,Last chip select number" textline " " hexmask.long.word 0x00 0.--15. 1. " RXDATA ,SPI receive data" else rgroup.long 0x44++0x03 line.long 0x00 "EMU,Emulation Register" bitfld.long 0x00 31. " RXEMPTY ,Receive data buffer empty" "No empty,Empty" bitfld.long 0x00 30. " RXOVR ,Receive data buffer overrun" "No overrun,Overrun" bitfld.long 0x00 29. " TXFULL ,Transmit data buffer full" "Empty,Full" textline " " bitfld.long 0x00 28. " BITERR ,Mismatch of internal transmit data and transmitted data" "Not occurred,Occurred" bitfld.long 0x00 26. " PARITYERR ,Calculated parity differs from received parity bit" "No error,Error" bitfld.long 0x00 24. " DLENERR ,Data length error flag" "No error,Error" textline " " hexmask.long.byte 0x00 16.--23. 1. " LCSNR ,Last chip select number" hexmask.long.word 0x00 0.--15. 1. " RXDATA ,SPI receive data" endif if (((d.l(ad:0xFFF7F600+0x04))&0x01)==0x01) group.long 0x48++0x03 line.long 0x00 "DELAY,Delay Register" hexmask.long.byte 0x00 24.--31. 1. " C2TDELAY ,Chip select active to transmit start delay" hexmask.long.byte 0x00 16.--23. 1. " T2CDELAY ,Transmit end to chip select inactive delay" hexmask.long.byte 0x00 8.--15. 1. " T2EDELAY ,Transmit data finished to ENA pin inactive time out" textline " " hexmask.long.byte 0x00 0.--7. 1. " C2EDELAY ,Chip select active to ENA signal active time out" else hgroup.long 0x48++0x03 hide.long 0x00 "DELAY,Delay Register" endif group.long 0x4C++0x03 line.long 0x00 "DEF,Default Chip Select Register" bitfld.long 0x00 7. " CSDEF7 ,Chip select default pattern 7" "Low,High" bitfld.long 0x00 6. " CSDEF6 ,Chip select default pattern 6" "Low,High" bitfld.long 0x00 5. " CSDEF5 ,Chip select default pattern 5" "Low,High" bitfld.long 0x00 4. " CSDEF4 ,Chip select default pattern 4" "Low,High" textline " " bitfld.long 0x00 3. " CSDEF3 ,Chip select default pattern 3" "Low,High" bitfld.long 0x00 2. " CSDEF2 ,Chip select default pattern 2" "Low,High" bitfld.long 0x00 1. " CSDEF1 ,Chip select default pattern 1" "Low,High" bitfld.long 0x00 0. " CSDEF0 ,Chip select default pattern 0" "Low,High" width 6. tree "SPI Data Format Registers" group.long 0x50++0x03 line.long 0x00 "FMT0,Data Format Register 0" bitfld.long 0x00 24.--29. " WDELAY0 ,Delay in between transmissions for data format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " PARPOL0 ,Parity polarity" "Even,Odd" bitfld.long 0x00 22. " PARITY0_ENA ,Parity enable for data format 0" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " WAITENA0 ,Master waits for ENA signal from slave for data format 0" "Not wait,Wait" bitfld.long 0x00 20. " SHIFTDIR0 ,Shift direction for data format 0" "MSB,LSB" bitfld.long 0x00 18. " DIS_CS_TIMERS0 ,Disable chipselect timers for this format register" "No,Yes" textline " " bitfld.long 0x00 17. " POLARITY0 ,SPI data format 0 clock polarity" "Low-inactive,High-inactive" bitfld.long 0x00 16. " PHASE0 ,SPI data format 0 clock delay" "Not delayed,Delayed" hexmask.long.byte 0x00 8.--15. 1. " PRESCALE0 ,SPI data format 0 prescaler" textline " " bitfld.long 0x00 0.--4. " CHARLEN0 ,SPI data format 0 data word length" ",,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..." group.long 0x54++0x03 line.long 0x00 "FMT1,Data Format Register 1" bitfld.long 0x00 24.--29. " WDELAY1 ,Delay in between transmissions for data format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " PARPOL1 ,Parity polarity" "Even,Odd" bitfld.long 0x00 22. " PARITY1_ENA ,Parity enable for data format 1" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " WAITENA1 ,Master waits for ENA signal from slave for data format 1" "Not wait,Wait" bitfld.long 0x00 20. " SHIFTDIR1 ,Shift direction for data format 1" "MSB,LSB" bitfld.long 0x00 18. " DIS_CS_TIMERS1 ,Disable chipselect timers for this format register" "No,Yes" textline " " bitfld.long 0x00 17. " POLARITY1 ,SPI data format 1 clock polarity" "Low-inactive,High-inactive" bitfld.long 0x00 16. " PHASE1 ,SPI data format 1 clock delay" "Not delayed,Delayed" hexmask.long.byte 0x00 8.--15. 1. " PRESCALE1 ,SPI data format 1 prescaler" textline " " bitfld.long 0x00 0.--4. " CHARLEN1 ,SPI data format 1 data word length" ",,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..." group.long 0x58++0x03 line.long 0x00 "FMT2,Data Format Register 2" bitfld.long 0x00 24.--29. " WDELAY2 ,Delay in between transmissions for data format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " PARPOL2 ,Parity polarity" "Even,Odd" bitfld.long 0x00 22. " PARITY2_ENA ,Parity enable for data format 2" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " WAITENA2 ,Master waits for ENA signal from slave for data format 2" "Not wait,Wait" bitfld.long 0x00 20. " SHIFTDIR2 ,Shift direction for data format 2" "MSB,LSB" bitfld.long 0x00 18. " DIS_CS_TIMERS2 ,Disable chipselect timers for this format register" "No,Yes" textline " " bitfld.long 0x00 17. " POLARITY2 ,SPI data format 2 clock polarity" "Low-inactive,High-inactive" bitfld.long 0x00 16. " PHASE2 ,SPI data format 2 clock delay" "Not delayed,Delayed" hexmask.long.byte 0x00 8.--15. 1. " PRESCALE2 ,SPI data format 2 prescaler" textline " " bitfld.long 0x00 0.--4. " CHARLEN2 ,SPI data format 2 data word length" ",,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..." group.long 0x5C++0x03 line.long 0x00 "FMT3,Data Format Register 3" bitfld.long 0x00 24.--29. " WDELAY3 ,Delay in between transmissions for data format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " PARPOL3 ,Parity polarity" "Even,Odd" bitfld.long 0x00 22. " PARITY3_ENA ,Parity enable for data format 3" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " WAITENA3 ,Master waits for ENA signal from slave for data format 3" "Not wait,Wait" bitfld.long 0x00 20. " SHIFTDIR3 ,Shift direction for data format 3" "MSB,LSB" bitfld.long 0x00 18. " DIS_CS_TIMERS3 ,Disable chipselect timers for this format register" "No,Yes" textline " " bitfld.long 0x00 17. " POLARITY3 ,SPI data format 3 clock polarity" "Low-inactive,High-inactive" bitfld.long 0x00 16. " PHASE3 ,SPI data format 3 clock delay" "Not delayed,Delayed" hexmask.long.byte 0x00 8.--15. 1. " PRESCALE3 ,SPI data format 3 prescaler" textline " " bitfld.long 0x00 0.--4. " CHARLEN3 ,SPI data format 3 data word length" ",,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..." tree.end width 12. tree "SPI Interrupt Vector Registers" if (((d.l(ad:0xFFF7F600+0x70))&0x01)==0x01) rgroup.long 0x60++0x03 line.long 0x00 "TGINTVECT0,Transfer Group Interrupt Vector Register 0" bitfld.long 0x00 1.--5. " INTVECT0 ,Interrupt vector for interrupt line INT0" "No interrupt,Interrupt of transfer group 0,Interrupt of transfer group 1,Interrupt of transfer group 2,Interrupt of transfer group 3,Interrupt of transfer group 4,Interrupt of transfer group 5,Interrupt of transfer group 6,Interrupt of transfer group 7,Interrupt of transfer group 8,Interrupt of transfer group 9,Interrupt of transfer group 10,Interrupt of transfer group 11,Interrupt of transfer group 12,Interrupt of transfer group 13,Interrupt of transfer group 14,Interrupt of transfer group 15,Interrupt/spiint0,,RXORN interrupt,?..." bitfld.long 0x00 0. " SUSPEND0 ,Transfer suspended/finished interrupt" "Suspended,Finished" else rgroup.long 0x60++0x03 line.long 0x00 "TGINTVECT0,Transfer Group Interrupt Vector Register 0" bitfld.long 0x00 1.--5. " INTVECT0 ,Interrupt vector for interrupt line INT0" "No interrupt,,,,,,,,,,,,,,,,,Interrupt/spiint0,Receive buffer full interrupt,Receive buffer overrun interrupt,Transmit buffer empty interrupt,?..." endif if (((d.l(ad:0xFFF7F600+0x70))&0x01)==0x01) rgroup.long 0x64++0x03 line.long 0x00 "TGINTVECT1,Transfer Group Interrupt Vector Register 1" bitfld.long 0x00 1.--5. " INTVECT1 ,Interrupt vector for interrupt line INT1" "No interrupt,Interrupt of transfer group 0,Interrupt of transfer group 1,Interrupt of transfer group 2,Interrupt of transfer group 3,Interrupt of transfer group 4,Interrupt of transfer group 5,Interrupt of transfer group 6,Interrupt of transfer group 7,Interrupt of transfer group 8,Interrupt of transfer group 9,Interrupt of transfer group 10,Interrupt of transfer group 11,Interrupt of transfer group 12,Interrupt of transfer group 13,Interrupt of transfer group 14,Interrupt of transfer group 15,Interrupt/spiint1,,RXORN interrupt,?..." bitfld.long 0x00 0. " SUSPEND1 ,Transfer suspended/finished interrupt" "Suspended,Finished" else rgroup.long 0x64++0x03 line.long 0x00 "TGINTVECT1,Transfer Group Interrupt Vector Register 1" bitfld.long 0x00 1.--5. " INTVECT1 ,Interrupt vector for interrupt line INT1" "No interrupt,,,,,,,,,,,,,,,,,Interrupt/spiint1,Receive buffer full interrupt,Receive buffer overrun interrupt,Transmit buffer empty interrupt,?..." endif tree.end width 8. textline " " if (((d.l(ad:0xFFF7F600+0x3C))&0x3000000)==0x00) group.long 0x6C++0x03 line.long 0x00 "PMCTRL,Parallel/modulo Mode Control Register" bitfld.long 0x00 5. " MOD_CLK_POL_0 ,Modulo mode SPICLK polarity" "Normal,Inverted" bitfld.long 0x00 2.--4. " MMODE_0 ,SPI data line selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..." bitfld.long 0x00 0.--1. " PMODE_0 ,Parallel mode" "1-data,2-data,4-data,8-data" elif (((d.l(ad:0xFFF7F600+0x3C))&0x3000000)==0x1000000) group.long 0x6C++0x03 line.long 0x00 "PMCTRL,Parallel/modulo Mode Control Register" bitfld.long 0x00 13. " MOD_CLK_POL_1 ,Modulo mode SPICLK polarity" "Normal,Inverted" bitfld.long 0x00 10.--12. " MMODE_1 ,SPI data line selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..." bitfld.long 0x00 8.--9. " PMODE_1 ,Parallel mode" "1-data,2-data,4-data,8-data" elif (((d.l((ad:0xFFF7F600+0x3C)))&0x3000000)==0x2000000) group.long 0x6C++0x03 line.long 0x00 "PMCTRL,Parallel/modulo Mode Control Register" bitfld.long 0x00 21. " MOD_CLK_POL_2 ,Modulo mode SPICLK polarity" "Normal,Inverted" bitfld.long 0x00 18.--20. " MMODE_2 ,SPI data line selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..." bitfld.long 0x00 16.--17. " PMODE_2 ,Parallel mode" "1-data,2-data,4-data,8-data" else group.long 0x6C++0x03 line.long 0x00 "PMCTRL,Parallel/modulo Mode Control Register" bitfld.long 0x00 29. " MOD_CLK_POL_3 ,Modulo mode SPICLK polarity" "Normal,Inverted" bitfld.long 0x00 26.--28. " MMODE_3 ,SPI data line selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..." bitfld.long 0x00 24.--25. " PMODE_3 ,Parallel mode" "1-data,2-data,4-data,8-data" endif width 11. tree "Mibspi Registers" group.long 0x70++0x03 line.long 0x00 "MIBSPIE,Mibspi Enable Register" bitfld.long 0x00 16. " RX_RAM_ACCESS ,Receive RAM access control bit" "RX not writable,R/W" bitfld.long 0x00 0. " MSPIENA ,Multibuffer mode enable" "Disabled,Enabled" if (((d.l(ad:0xFFF7F600+0x70))&0x01)==0x01) group.long 0x74++0x03 line.long 0x00 "TGITENST,Mibspi Transfer Group Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTEN_RDY15_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x04 30. " INTEN_RDY14_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 29. 0x00 29. 0x04 29. " INTEN_RDY13_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x04 28. " INTEN_RDY12_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. 0x00 27. 0x04 27. " INTEN_RDY11_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x04 26. " INTEN_RDY10_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x04 25. " INTEN_RDY9_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x04 24. " INTEN_RDY8_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. 0x00 23. 0x04 23. " INTEN_RDY7_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x04 22. " INTEN_RDY6_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. 0x00 21. 0x04 21. " INTEN_RDY5_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x04 20. " INTEN_RDY4_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x04 19. " INTEN_RDY3_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x04 18. " INTEN_RDY2_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. 0x00 17. 0x04 17. " INTEN_RDY1_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x04 16. " INTEN_RDY0_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 15. 0x00 15. 0x04 15. " INTEN_SUS15_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x04 14. " INTEN_SUS14_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x04 13. " INTEN_SUS13_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x04 12. " INTEN_SUS12_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 11. 0x00 11. 0x04 11. " INTEN_SUS11_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x04 10. " INTEN_SUS10_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. 0x00 9. 0x04 9. " INTEN_SUS9_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x04 8. " INTEN_SUS8_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x04 7. " INTEN_SUS7_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x04 6. " INTEN_SUS6_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x00 5. 0x04 5. " INTEN_SUS5_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x04 4. " INTEN_SUS4_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. 0x00 3. 0x04 3. " INTEN_SUS3_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x04 2. " INTEN_SUS2_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x04 1. " INTEN_SUS1_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " INTEN_SUS0_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" group.long 0x7C++0x03 line.long 0x00 "TGITLVST,Mibspi Transfer Group Interrupt Level Set Register" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTLVL_RDY15_SET/CLR ,Transfer group completed interrupt level 15" "INT0,INT1" setclrfld.long 0x00 30. 0x00 30. 0x04 30. " INTLVL_RDY14_SET/CLR ,Transfer group completed interrupt level 14" "INT0,INT1" textline " " setclrfld.long 0x00 29. 0x00 29. 0x04 29. " INTLVL_RDY13_SET/CLR ,Transfer group completed interrupt level 13" "INT0,INT1" setclrfld.long 0x00 28. 0x00 28. 0x04 28. " INTLVL_RDY12_SET/CLR ,Transfer group completed interrupt level 12" "INT0,INT1" textline " " setclrfld.long 0x00 27. 0x00 27. 0x04 27. " INTLVL_RDY11_SET/CLR ,Transfer group completed interrupt level 11" "INT0,INT1" setclrfld.long 0x00 26. 0x00 26. 0x04 26. " INTLVL_RDY10_SET/CLR ,Transfer group completed interrupt level 10" "INT0,INT1" textline " " setclrfld.long 0x00 25. 0x00 25. 0x04 25. " INTLVL_RDY9_SET/CLR ,Transfer group completed interrupt level set 9" "INT0,INT1" setclrfld.long 0x00 24. 0x00 24. 0x04 24. " INTLVL_RDY8_SET/CLR ,Transfer group completed interrupt level set 8" "INT0,INT1" textline " " setclrfld.long 0x00 23. 0x00 23. 0x04 23. " INTLVL_RDY7_SET/CLR ,Transfer group completed interrupt level set 7" "INT0,INT1" setclrfld.long 0x00 22. 0x00 22. 0x04 22. " INTLVL_RDY6_SET/CLR ,Transfer group completed interrupt level set 6" "INT0,INT1" textline " " setclrfld.long 0x00 21. 0x00 21. 0x04 21. " INTLVL_RDY5_SET/CLR ,Transfer group completed interrupt level set 5" "INT0,INT1" setclrfld.long 0x00 20. 0x00 20. 0x04 20. " INTLVL_RDY4_SET/CLR ,Transfer group completed interrupt level set 4" "INT0,INT1" textline " " setclrfld.long 0x00 19. 0x00 19. 0x04 19. " INTLVL_RDY3_SET/CLR ,Transfer group completed interrupt level set 3" "INT0,INT1" setclrfld.long 0x00 18. 0x00 18. 0x04 18. " INTLVL_RDY2_SET/CLR ,Transfer group completed interrupt level set 2" "INT0,INT1" textline " " setclrfld.long 0x00 17. 0x00 17. 0x04 17. " INTLVL_RDY1_SET/CLR ,Transfer group completed interrupt level set 1" "INT0,INT1" setclrfld.long 0x00 16. 0x00 16. 0x04 16. " INTLVL_RDY0_SET/CLR ,Transfer group completed interrupt level set 0" "INT0,INT1" textline " " setclrfld.long 0x00 15. 0x00 15. 0x04 15. " INTLVL_SUS15_SET/CLR ,Transfer group suspended interrupt level set 15" "INT0,INT1" setclrfld.long 0x00 14. 0x00 14. 0x04 14. " INTLVL_SUS14_SET/CLR ,Transfer group suspended interrupt level set 14" "INT0,INT1" textline " " setclrfld.long 0x00 13. 0x00 13. 0x04 13. " INTLVL_SUS13_SET/CLR ,Transfer group suspended interrupt level set 13" "INT0,INT1" setclrfld.long 0x00 12. 0x00 12. 0x04 12. " INTLVL_SUS12_SET/CLR ,Transfer group suspended interrupt level set 12" "INT0,INT1" textline " " setclrfld.long 0x00 11. 0x00 11. 0x04 11. " INTLVL_SUS11_SET/CLR ,Transfer group suspended interrupt level set 11" "INT0,INT1" setclrfld.long 0x00 10. 0x00 10. 0x04 10. " INTLVL_SUS10_SET/CLR ,Transfer group suspended interrupt level set 10" "INT0,INT1" textline " " setclrfld.long 0x00 9. 0x00 9. 0x04 9. " INTLVL_SUS9_SET/CLR ,Transfer group suspended interrupt level set 9" "INT0,INT1" setclrfld.long 0x00 8. 0x00 8. 0x04 8. " INTLVL_SUS8_SET/CLR ,Transfer group suspended interrupt level set 8" "INT0,INT1" textline " " setclrfld.long 0x00 7. 0x00 7. 0x04 7. " INTLVL_SUS7_SET/CLR ,Transfer group suspended interrupt level set 7" "INT0,INT1" setclrfld.long 0x00 6. 0x00 6. 0x04 6. " INTLVL_SUS6_SET/CLR ,Transfer group suspended interrupt level set 6" "INT0,INT1" textline " " setclrfld.long 0x00 5. 0x00 5. 0x04 5. " INTLVL_SUS5_SET/CLR ,Transfer group suspended interrupt level set 5" "INT0,INT1" setclrfld.long 0x00 4. 0x00 4. 0x04 4. " INTLVL_SUS4_SET/CLR ,Transfer group suspended interrupt level set 4" "INT0,INT1" textline " " setclrfld.long 0x00 3. 0x00 3. 0x04 3. " INTLVL_SUS3_SET/CLR ,Transfer group suspended interrupt level set 3" "INT0,INT1" setclrfld.long 0x00 2. 0x00 2. 0x04 2. " INTLVL_SUS2_SET/CLR ,Transfer group suspended interrupt level set 2" "INT0,INT1" textline " " setclrfld.long 0x00 1. 0x00 1. 0x04 1. " INTLVL_SUS1_SET/CLR ,Transfer group suspended interrupt level set 1" "INT0,INT1" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " INTLVL_SUS0_SET/CLR ,Transfer group suspended interrupt level set 0" "INT0,INT1" group.long 0x84++0x03 line.long 0x00 "TGINTFLAG,Transfer Group Interrupt Flag Register" eventfld.long 0x00 31. " INTFLGRDY15 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" eventfld.long 0x00 30. " INTFLGRDY14 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 29. " INTFLGRDY13 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" eventfld.long 0x00 28. " INTFLGRDY12 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 27. " INTFLGRDY11 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" eventfld.long 0x00 26. " INTFLGRDY10 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 25. " INTFLGRDY9 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" eventfld.long 0x00 24. " INTFLGRDY8 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 23. " INTFLGRDY7 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" eventfld.long 0x00 22. " INTFLGRDY6 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 21. " INTFLGRDY5 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" eventfld.long 0x00 20. " INTFLGRDY4 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 19. " INTFLGRDY3 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" eventfld.long 0x00 18. " INTFLGRDY2 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 17. " INTFLGRDY1 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" eventfld.long 0x00 16. " INTFLGRDY0 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 15. " INTFLGSUS15 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" eventfld.long 0x00 14. " INTFLGSUS14 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 13. " INTFLGSUS13 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" eventfld.long 0x00 12. " INTFLGSUS12 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 11. " INTFLGSUS11 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" eventfld.long 0x00 10. " INTFLGSUS10 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 9. " INTFLGSUS9 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" eventfld.long 0x00 8. " INTFLGSUS8 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 7. " INTFLGSUS7 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" eventfld.long 0x00 6. " INTFLGSUS6 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 5. " INTFLGSUS5 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" eventfld.long 0x00 4. " INTFLGSUS4 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " INTFLGSUS3 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" eventfld.long 0x00 2. " INTFLGSUS2 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 1. " INTFLGSUS1 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " INTFLGSUS0 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" group.long 0x90++0x03 line.long 0x00 "TICKCNT,Tick Count Register" bitfld.long 0x00 31. " TICKENA ,Tick counter enable" "Disabled,Enabled" bitfld.long 0x00 30. " RELOAD ,Re-load tick counter" "No effect,Reload" textline " " bitfld.long 0x00 28.--29. " CLKCTRL ,Tick counter clock source control" "Format 0,Format 1,Format 2,Format 3" hexmask.long.word 0x00 0.--15. 1. " TICKVALUE ,Initial value for tick counter" group.long 0x94++0x03 line.long 0x00 "LTGPEND,Last Transfer Group End Pointer" bitfld.long 0x00 24.--28. " TG_IN_SERVICE ,Transfer group currently being serviced by the sequencer" "Not serviced,Group0,Group1,Group2,Group3,Group4,Group5,Group6,Group7,Group8,Group9,Group10,Group11,Group12,Group13,Group14,Group15,?..." hexmask.long.byte 0x00 8.--14. 1. " LPEND ,Last transfer group end pointer" else hgroup.long 0x74++0x03 hide.long 0x00 "TGITENST,Mibspi Transfer Group Interrupt Enable Register" hgroup.long 0x7C++0x03 hide.long 0x00 "TGITLVST,Mibspi Transfer Group Interrupt Level Register" hgroup.long 0x84++0x03 hide.long 0x00 "TGINTFLAG,Transfer Group Interrupt Flag Register" hgroup.long 0x90++0x03 hide.long 0x00 "TICKCNT,Tick Count Register" hgroup.long 0x94++0x03 hide.long 0x00 "LTGPEND,Last Transfer Group End Pointer" endif width 20. tree "Mibspi Transfer Group Control Registers" if (((d.l(ad:0xFFF7F600+0x70))&0x01)==0x01) group.long 0x98++0x03 line.long 0x00 "TG0CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA0 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT0 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST0 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD0 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT0 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC0 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART0 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT0 ,Transfer group pointer to current buffer" group.long 0x9C++0x03 line.long 0x00 "TG1CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA1 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT1 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST1 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD1 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT1 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC1 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART1 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT1 ,Transfer group pointer to current buffer" group.long 0xA0++0x03 line.long 0x00 "TG2CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA2 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT2 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST2 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD2 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT2 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC2 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART2 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT2 ,Transfer group pointer to current buffer" group.long 0xA4++0x03 line.long 0x00 "TG3CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA3 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT3 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST3 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD3 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT3 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC3 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART3 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT3 ,Transfer group pointer to current buffer" group.long 0xA8++0x03 line.long 0x00 "TG4CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA4 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT4 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST4 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD4 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT4 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC4 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART4 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT4 ,Transfer group pointer to current buffer" group.long 0xAC++0x03 line.long 0x00 "TG5CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA5 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT5 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST5 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD5 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT5 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC5 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART5 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT5 ,Transfer group pointer to current buffer" group.long 0xB0++0x03 line.long 0x00 "TG6CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA6 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT6 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST6 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD6 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT6 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC6 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART6 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT6 ,Transfer group pointer to current buffer" group.long 0xB4++0x03 line.long 0x00 "TG7CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA7 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT7 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST7 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD7 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT7 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC7 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART7 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT7 ,Transfer group pointer to current buffer" group.long 0xB8++0x03 line.long 0x00 "TG8CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA8 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT8 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST8 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD8 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT8 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC8 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART8 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT8 ,Transfer group pointer to current buffer" group.long 0xBC++0x03 line.long 0x00 "TG9CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA9 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT9 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST9 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD9 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT9 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC9 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART9 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT9 ,Transfer group pointer to current buffer" group.long 0xC0++0x03 line.long 0x00 "TG10CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA10 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT10 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST10 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD10 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT10 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC10 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART10 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT10 ,Transfer group pointer to current buffer" group.long 0xC4++0x03 line.long 0x00 "TG11CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA11 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT11 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST11 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD11 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT11 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC11 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART11 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT11 ,Transfer group pointer to current buffer" group.long 0xC8++0x03 line.long 0x00 "TG12CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA12 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT12 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST12 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD12 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT12 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC12 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART12 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT12 ,Transfer group pointer to current buffer" group.long 0xCC++0x03 line.long 0x00 "TG13CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA13 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT13 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST13 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD13 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT13 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC13 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART13 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT13 ,Transfer group pointer to current buffer" group.long 0xD0++0x03 line.long 0x00 "TG14CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA14 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT14 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST14 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD14 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT14 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC14 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART14 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT14 ,Transfer group pointer to current buffer" group.long 0xD4++0x03 line.long 0x00 "TG15CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA15 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT15 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST15 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD15 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT15 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC15 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART15 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT15 ,Transfer group pointer to current buffer" else hgroup.long 0x98++0x03 hide.long 0x00 "TG0CTRL,Mibspi Transfer Group Control Register" hgroup.long 0x9C++0x03 hide.long 0x00 "TG1CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xA0++0x03 hide.long 0x00 "TG2CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xA4++0x03 hide.long 0x00 "TG3CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xA8++0x03 hide.long 0x00 "TG4CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xAC++0x03 hide.long 0x00 "TG5CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xB0++0x03 hide.long 0x00 "TG6CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xB4++0x03 hide.long 0x00 "TG7CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xB8++0x03 hide.long 0x00 "TG8CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xBC++0x03 hide.long 0x00 "TG9CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xC0++0x03 hide.long 0x00 "TG10CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xC4++0x03 hide.long 0x00 "TG11CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xC8++0x03 hide.long 0x00 "TG12CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xCC++0x03 hide.long 0x00 "TG13CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xD0++0x03 hide.long 0x00 "TG14CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xD4++0x03 hide.long 0x00 "TG15CTRL,Mibspi Transfer Group Control Register" endif tree.end textline " " sif (cpu()!="RM42L432") if ((((d.l(ad:0xFFF7F600+0x04))&0x01)==0x01)&&((d.l(ad:0xFFF7F600+0x70))&0x01)==0x01) group.long 0xD8++0x03 line.long 0x00 "DMA0CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT0 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 0" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID0 ,Buffer utilized for DMA transfer 0" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP0 ,Receive data DMA request map 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP0 ,Transmit data DMA channel 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA0 ,Receive data DMA channel enable 0" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA0 ,Transmit data DMA channel enable 0" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK0 ,Non-interleaved DMA block transfer 0" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT0 ,Initial count of DMA transfers 0" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT170 ,The 17th bit of COUNT field of DMA0COUNT register" "Low,High" bitfld.long 0x00 0.--5. " COUNT0 ,Actual number of remaining DMA transfer 0" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l(ad:0xFFF7F600+0x04))&0x01)==0x00)&&((d.l(ad:0xFFF7F600+0x70))&0x01)==0x01) group.long 0xD8++0x03 line.long 0x00 "DMA0CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT0 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 0" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID0 ,Buffer utilized for DMA transfer 0" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP0 ,Receive data DMA request map 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP0 ,Transmit data DMA channel 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA0 ,Receive data DMA channel enable 0" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA0 ,Transmit data DMA channel enable 0" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT0 ,Initial count of DMA transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT170 ,The 17th bit of COUNT field of DMA0COUNT register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT0 ,Actual number of remaining DMA transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xD8++0x03 hide.long 0x00 "DMA0CTRL,Mibspi DMA Channel Control Register" endif if ((((d.l(ad:0xFFF7F600+0x04))&0x01)==0x01)&&((d.l(ad:0xFFF7F600+0x70))&0x01)==0x01) group.long 0xDC++0x03 line.long 0x00 "DMA1CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT1 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 1" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID1 ,Buffer utilized for DMA transfer 1" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP1 ,Receive data DMA request map 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP1 ,Transmit data DMA channel 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA1 ,Receive data DMA channel enable 1" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA1 ,Transmit data DMA channel enable 1" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK1 ,Non-interleaved DMA block transfer 1" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT1 ,Initial count of DMA transfers 1" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT171 ,The 17th bit of COUNT field of DMA1COUNT register" "Low,High" bitfld.long 0x00 0.--5. " COUNT1 ,Actual number of remaining DMA transfer 1" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l(ad:0xFFF7F600+0x04))&0x01)==0x00)&&((d.l(ad:0xFFF7F600+0x70))&0x01)==0x01) group.long 0xDC++0x03 line.long 0x00 "DMA1CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT1 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 1" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID1 ,Buffer utilized for DMA transfer 1" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP1 ,Receive data DMA request map 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP1 ,Transmit data DMA channel 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA1 ,Receive data DMA channel enable 1" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA1 ,Transmit data DMA channel enable 1" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT1 ,Initial count of DMA transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT171 ,The 17th bit of COUNT field of DMA1COUNT register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT1 ,Actual number of remaining DMA transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xDC++0x03 hide.long 0x00 "DMA1CTRL,Mibspi DMA Channel Control Register" endif if ((((d.l(ad:0xFFF7F600+0x04))&0x01)==0x01)&&((d.l(ad:0xFFF7F600+0x70))&0x01)==0x01) group.long 0xE0++0x03 line.long 0x00 "DMA2CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT2 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 2" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID2 ,Buffer utilized for DMA transfer 2" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP2 ,Receive data DMA request map 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP2 ,Transmit data DMA channel 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA2 ,Receive data DMA channel enable 2" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA2 ,Transmit data DMA channel enable 2" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK2 ,Non-interleaved DMA block transfer 2" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT2 ,Initial count of DMA transfers 2" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT172 ,The 17th bit of COUNT field of DMA2COUNT register" "Low,High" bitfld.long 0x00 0.--5. " COUNT2 ,Actual number of remaining DMA transfer 2" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l(ad:0xFFF7F600+0x04))&0x01)==0x00)&&((d.l(ad:0xFFF7F600+0x70))&0x01)==0x01) group.long 0xE0++0x03 line.long 0x00 "DMA2CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT2 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 2" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID2 ,Buffer utilized for DMA transfer 2" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP2 ,Receive data DMA request map 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP2 ,Transmit data DMA channel 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA2 ,Receive data DMA channel enable 2" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA2 ,Transmit data DMA channel enable 2" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT2 ,Initial count of DMA transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT172 ,The 17th bit of COUNT field of DMA2COUNT register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT2 ,Actual number of remaining DMA transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xE0++0x03 hide.long 0x00 "DMA2CTRL,Mibspi DMA Channel Control Register" endif if ((((d.l(ad:0xFFF7F600+0x04))&0x01)==0x01)&&((d.l(ad:0xFFF7F600+0x70))&0x01)==0x01) group.long 0xE4++0x03 line.long 0x00 "DMA3CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT3 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 3" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID3 ,Buffer utilized for DMA transfer 3" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP3 ,Receive data DMA request map 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP3 ,Transmit data DMA channel 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA3 ,Receive data DMA channel enable 3" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA3 ,Transmit data DMA channel enable 3" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK3 ,Non-interleaved DMA block transfer 3" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT3 ,Initial count of DMA transfers 3" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT173 ,The 17th bit of COUNT field of DMA3COUNT register" "Low,High" bitfld.long 0x00 0.--5. " COUNT3 ,Actual number of remaining DMA transfer 3" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l(ad:0xFFF7F600+0x04))&0x01)==0x00)&&((d.l(ad:0xFFF7F600+0x70))&0x01)==0x01) group.long 0xE4++0x03 line.long 0x00 "DMA3CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT3 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 3" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID3 ,Buffer utilized for DMA transfer 3" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP3 ,Receive data DMA request map 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP3 ,Transmit data DMA channel 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA3 ,Receive data DMA channel enable 3" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA3 ,Transmit data DMA channel enable 3" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT3 ,Initial count of DMA transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT173 ,The 17th bit of COUNT field of DMA3COUNT register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT3 ,Actual number of remaining DMA transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xE4++0x03 hide.long 0x00 "DMA3CTRL,Mibspi DMA Channel Control Register" endif if ((((d.l(ad:0xFFF7F600+0x04))&0x01)==0x01)&&((d.l(ad:0xFFF7F600+0x70))&0x01)==0x01) group.long 0xE8++0x03 line.long 0x00 "DMA4CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT4 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 4" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID4 ,Buffer utilized for DMA transfer 4" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP4 ,Receive data DMA request map 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP4 ,Transmit data DMA channel 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA4 ,Receive data DMA channel enable 4" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA4 ,Transmit data DMA channel enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK4 ,Non-interleaved DMA block transfer 4" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT4 ,Initial count of DMA transfers 4" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT174 ,The 17th bit of COUNT field of DMA4COUNT register" "Low,High" bitfld.long 0x00 0.--5. " COUNT4 ,Actual number of remaining DMA transfer 4" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l(ad:0xFFF7F600+0x04))&0x01)==0x00)&&((d.l(ad:0xFFF7F600+0x70))&0x01)==0x01) group.long 0xE8++0x03 line.long 0x00 "DMA4CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT4 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 4" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID4 ,Buffer utilized for DMA transfer 4" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP4 ,Receive data DMA request map 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP4 ,Transmit data DMA channel 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA4 ,Receive data DMA channel enable 4" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA4 ,Transmit data DMA channel enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT4 ,Initial count of DMA transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT174 ,The 17th bit of COUNT field of DMA4COUNT register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT4 ,Actual number of remaining DMA transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xE8++0x03 hide.long 0x00 "DMA4CTRL,Mibspi DMA Channel Control Register" endif if ((((d.l(ad:0xFFF7F600+0x04))&0x01)==0x01)&&((d.l(ad:0xFFF7F600+0x70))&0x01)==0x01) group.long 0xEC++0x03 line.long 0x00 "DMA5CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT5 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 5" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID5 ,Buffer utilized for DMA transfer 5" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP5 ,Receive data DMA request map 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP5 ,Transmit data DMA channel 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA5 ,Receive data DMA channel enable 5" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA5 ,Transmit data DMA channel enable 5" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK5 ,Non-interleaved DMA block transfer 5" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT5 ,Initial count of DMA transfers 5" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT175 ,The 17th bit of COUNT field of DMA5COUNT register" "Low,High" bitfld.long 0x00 0.--5. " COUNT5 ,Actual number of remaining DMA transfer 5" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l(ad:0xFFF7F600+0x04))&0x01)==0x00)&&((d.l(ad:0xFFF7F600+0x70))&0x01)==0x01) group.long 0xEC++0x03 line.long 0x00 "DMA5CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT5 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 5" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID5 ,Buffer utilized for DMA transfer 5" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP5 ,Receive data DMA request map 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP5 ,Transmit data DMA channel 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA5 ,Receive data DMA channel enable 5" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA5 ,Transmit data DMA channel enable 5" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT5 ,Initial count of DMA transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT175 ,The 17th bit of COUNT field of DMA5COUNT register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT5 ,Actual number of remaining DMA transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xEC++0x03 hide.long 0x00 "DMA5CTRL,Mibspi DMA Channel Control Register" endif if ((((d.l(ad:0xFFF7F600+0x04))&0x01)==0x01)&&((d.l(ad:0xFFF7F600+0x70))&0x01)==0x01) group.long 0xF0++0x03 line.long 0x00 "DMA6CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT6 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 6" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID6 ,Buffer utilized for DMA transfer 6" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP6 ,Receive data DMA request map 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP6 ,Transmit data DMA channel 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA6 ,Receive data DMA channel enable 6" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA6 ,Transmit data DMA channel enable 6" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK6 ,Non-interleaved DMA block transfer 6" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT6 ,Initial count of DMA transfers 6" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT176 ,The 17th bit of COUNT field of DMA6COUNT register" "Low,High" bitfld.long 0x00 0.--5. " COUNT6 ,Actual number of remaining DMA transfer 6" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l(ad:0xFFF7F600+0x04))&0x01)==0x00)&&((d.l(ad:0xFFF7F600+0x70))&0x01)==0x01) group.long 0xF0++0x03 line.long 0x00 "DMA6CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT6 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 6" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID6 ,Buffer utilized for DMA transfer 6" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP6 ,Receive data DMA request map 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP6 ,Transmit data DMA channel 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA6 ,Receive data DMA channel enable 6" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA6 ,Transmit data DMA channel enable 6" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT6 ,Initial count of DMA transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT176 ,The 17th bit of COUNT field of DMA6COUNT register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT6 ,Actual number of remaining DMA transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xF0++0x03 hide.long 0x00 "DMA6CTRL,Mibspi DMA Channel Control Register" endif if ((((d.l(ad:0xFFF7F600+0x04))&0x01)==0x01)&&((d.l(ad:0xFFF7F600+0x70))&0x01)==0x01) group.long 0xF4++0x03 line.long 0x00 "DMA7CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT7 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 7" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID7 ,Buffer utilized for DMA transfer 7" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP7 ,Receive data DMA request map 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP7 ,Transmit data DMA channel 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA7 ,Receive data DMA channel enable 7" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA7 ,Transmit data DMA channel enable 7" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK7 ,Non-interleaved DMA block transfer 7" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT7 ,Initial count of DMA transfers 7" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT177 ,The 17th bit of COUNT field of DMA7COUNT register" "Low,High" bitfld.long 0x00 0.--5. " COUNT7 ,Actual number of remaining DMA transfer 7" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l(ad:0xFFF7F600+0x04))&0x01)==0x00)&&((d.l(ad:0xFFF7F600+0x70))&0x01)==0x01) group.long 0xF4++0x03 line.long 0x00 "DMA7CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT7 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 7" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID7 ,Buffer utilized for DMA transfer 7" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP7 ,Receive data DMA request map 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP7 ,Transmit data DMA channel 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA7 ,Receive data DMA channel enable 7" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA7 ,Transmit data DMA channel enable 7" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT7 ,Initial count of DMA transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT177 ,The 17th bit of COUNT field of DMA7COUNT register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT7 ,Actual number of remaining DMA transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xF4++0x03 hide.long 0x00 "DMA7CTRL,Mibspi DMA Channel Control Register" endif if (((d.l(ad:0xFFF7F600+0x70))&0x01)==0x01) group.long 0xF8++0x03 line.long 0x00 "DMA0COUNT,ICOUNT Register 0" hexmask.long.word 0x00 16.--31. 1. " ICOUNT0 ,Initial number of DMA transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT0 ,Actual number of remaining DMA transfer" else hgroup.long 0xF8++0x03 hide.long 0x00 "DMA0COUNT,ICOUNT Register 0" endif if (((d.l(ad:0xFFF7F600+0x70))&0x01)==0x01) group.long 0xFC++0x03 line.long 0x00 "DMA1COUNT,ICOUNT Register 1" hexmask.long.word 0x00 16.--31. 1. " ICOUNT1 ,Initial number of DMA transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT1 ,Actual number of remaining DMA transfer" else hgroup.long 0xFC++0x03 hide.long 0x00 "DMA1COUNT,ICOUNT Register 1" endif if (((d.l(ad:0xFFF7F600+0x70))&0x01)==0x01) group.long 0x100++0x03 line.long 0x00 "DMA2COUNT,ICOUNT Register 2" hexmask.long.word 0x00 16.--31. 1. " ICOUNT2 ,Initial number of DMA transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT2 ,Actual number of remaining DMA transfer" else hgroup.long 0x100++0x03 hide.long 0x00 "DMA2COUNT,ICOUNT Register 2" endif if (((d.l(ad:0xFFF7F600+0x70))&0x01)==0x01) group.long 0x104++0x03 line.long 0x00 "DMA3COUNT,ICOUNT Register 3" hexmask.long.word 0x00 16.--31. 1. " ICOUNT3 ,Initial number of DMA transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT3 ,Actual number of remaining DMA transfer" else hgroup.long 0x104++0x03 hide.long 0x00 "DMA3COUNT,ICOUNT Register 3" endif if (((d.l(ad:0xFFF7F600+0x70))&0x01)==0x01) group.long 0x108++0x03 line.long 0x00 "DMA4COUNT,ICOUNT Register 4" hexmask.long.word 0x00 16.--31. 1. " ICOUNT4 ,Initial number of DMA transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT4 ,Actual number of remaining DMA transfer" else hgroup.long 0x108++0x03 hide.long 0x00 "DMA4COUNT,ICOUNT Register 4" endif if (((d.l(ad:0xFFF7F600+0x70))&0x01)==0x01) group.long 0x10C++0x03 line.long 0x00 "DMA5COUNT,ICOUNT Register 5" hexmask.long.word 0x00 16.--31. 1. " ICOUNT5 ,Initial number of DMA transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT5 ,Actual number of remaining DMA transfer" else hgroup.long 0x10C++0x03 hide.long 0x00 "DMA5COUNT,ICOUNT Register 5" endif if (((d.l(ad:0xFFF7F600+0x70))&0x01)==0x01) group.long 0x110++0x03 line.long 0x00 "DMA6COUNT,ICOUNT Register 6" hexmask.long.word 0x00 16.--31. 1. " ICOUNT6 ,Initial number of DMA transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT6 ,Actual number of remaining DMA transfer" else hgroup.long 0x110++0x03 hide.long 0x00 "DMA6COUNT,ICOUNT Register 6" endif if (((d.l(ad:0xFFF7F600+0x70))&0x01)==0x01) group.long 0x114++0x03 line.long 0x00 "DMA7COUNT,ICOUNT Register 7" hexmask.long.word 0x00 16.--31. 1. " ICOUNT7 ,Initial number of DMA transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT7 ,Actual number of remaining DMA transfer" else hgroup.long 0x114++0x03 hide.long 0x00 "DMA7COUNT,ICOUNT Register 7" endif endif textline " " if (((d.l(ad:0xFFF7F600+0x70))&0x01)==0x01) sif (cpu()!="RM42L432") group.long 0x118++0x03 line.long 0x00 "DMACNTLEN,DMA LARGE COUNT Register" bitfld.long 0x00 0. " LARGE_COUNT ,Large count" "Modified,Not modified" endif group.long 0x120++0x03 line.long 0x00 "UERRCTRL,Uncorrectable Parity Error Control Register" sif cpuis("RM57L843-ZWT") bitfld.long 0x00 24.--27. " SBE_EVT_EN ,Single bit error event enable" ",,,,,Disabled,,,,,Enabled,?..." bitfld.long 0x00 16.--19. " EDAC_MODE ,These bits determine whether single bit errors (Sbe) detected by the SECDED block will be corrected or not" ",,,,,Disabled,,,,,Enabled,?..." textline " " endif bitfld.long 0x00 8. " PTESTEN ,Parity memory test enable" "Disabled,Enabled" bitfld.long 0x00 0.--3. " EDEN ,Error detection enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" hgroup.long 0x124++0x03 hide.long 0x00 "UERRSTAT,Uncorrectable Parity Error Status Register" in hgroup.long 0x128++0x03 hide.long 0x00 "UERRADDR1,Uncorrectable Parity Error Address Register" in hgroup.long 0x12C++0x03 hide.long 0x00 "UERRADDR0,Uncorrectable Parity Error Address Register" in hgroup.long 0x130++0x03 hide.long 0x00 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register" in else hgroup.long 0x118++0x03 hide.long 0x00 "DMACNTLEN,DMA LARGE COUNT Register" hgroup.long 0x120++0x03 hide.long 0x00 "UERRCTRL,Uncorrectable Parity Error Control Register" hgroup.long 0x124++0x03 hide.long 0x00 "UERRSTAT,Uncorrectable Parity Error Status Register" hgroup.long 0x128++0x03 hide.long 0x00 "UERRADDR1,Uncorrectable Parity Error Address Register" hgroup.long 0x12C++0x03 hide.long 0x00 "UERRADDR0,Uncorrectable Parity Error Address Register" hgroup.long 0x130++0x03 hide.long 0x00 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register" endif tree.end textline " " if ((((d.l(ad:0xFFF7F600+0x134))&0xF00)==0xA00)&&(((d.l(ad:0xFFF7F600+0x134))&0x02)==0x02)) group.long 0x134++0x03 line.long 0x00 "IOLPBKTSTCR,Spi/mibspi IO Loopback Test Control Register" bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" eventfld.long 0x00 24. " SCS_FAIL_FLG ,Analog loopback /SPISCS pin compare failure" "Not failed,Failed" textline " " bitfld.long 0x00 20. " CTRL_BITERR ,Inducing of BITERR during IO loopback test mode control" "Not affected,Flipped" bitfld.long 0x00 19. " CTRL_DESYNC ,Inducing of DESYNC error during IO loopback test mode control" "Not affected,Forced to 0" textline " " bitfld.long 0x00 18. " CTRL_PARERR ,Inducing of parity error during IO loopback test mode control" "Not affected,Flipped" bitfld.long 0x00 17. " CTRL_TIMEOUT ,Inducing of TIMEOUT error during IO loopback test mode control" "Not affected,Forced to 1" textline " " bitfld.long 0x00 16. " CTRL_DLENERR ,Inducing of data length error during IO loopback test mode control" "Not affected,Forced to 1" bitfld.long 0x00 3.--5. " ERR_SCS_PIN ,Error on chip select pin injection" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]" textline " " bitfld.long 0x00 2. " CTRL_SCS_PIN_ERR ,/SPISCS[7:0] pins error injection enable control" "Disabled,Enabled" bitfld.long 0x00 1. " LPBK_TYPE ,Module IO loopback type" "Digital,Analog" textline " " bitfld.long 0x00 0. " RXP_ENA ,Module analog loopback through receive pin enable" "Transmit,Receive" elif ((((d.l(ad:0xFFF7F600+0x134))&0xF00)==0xA00)&&(((d.l(ad:0xFFF7F600+0x134))&0x02)==0x00)) group.long 0x134++0x03 line.long 0x00 "IOLPBKTSTCR,Spi/mibspi IO Loopback Test Control Register" bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" eventfld.long 0x00 24. " SCS_FAIL_FLG ,Analog loopback /SPISCS pin compare failure" "Not failed,Failed" textline " " bitfld.long 0x00 20. " CTRL_BITERR ,Inducing of BITERR during IO loopback test mode control" "Not affected,Flipped" bitfld.long 0x00 19. " CTRL_DESYNC ,Inducing of DESYNC error during IO loopback test mode control" "Not affected,Forced to 0" textline " " bitfld.long 0x00 18. " CTRL_PARERR ,Inducing of parity error during IO loopback test mode control" "Not affected,Flipped" bitfld.long 0x00 17. " CTRL_TIMEOUT ,Inducing of TIMEOUT error during IO loopback test mode control" "Not affected,Forced to 1" textline " " bitfld.long 0x00 16. " CTRL_DLENERR ,Inducing of data length error during IO loopback test mode control" "Not affected,Forced to 1" bitfld.long 0x00 3.--5. " ERR_SCS_PIN ,Error on chip select pin injection" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]" textline " " bitfld.long 0x00 2. " CTRL_SCS_PIN_ERR ,/SPISCS[7:0] pins error injection enable control" "Disabled,Enabled" bitfld.long 0x00 1. " LPBK_TYPE ,Module IO loopback type" "Digital,Analog" else group.long 0x134++0x03 line.long 0x00 "IOLPBKTSTCR,Spi/mibspi IO Loopback Test Control Register" bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" endif sif (cpuis("RM46L*")||cpu()=="RM42L432"||cpuis("RM57L843-ZWT")) group.long 0x138++0x07 line.long 0x00 "EXTENDED_PRESCALE1,SPI Extended Prescale Register 1" hexmask.long.word 0x00 16.--26. 1. " EPRESCALE_FMT1 ,Extended prescale value for SPIFMT1" hexmask.long.word 0x00 0.--10. 1. " EPRESCALE_FMT0 ,Extended prescale value for SPIFMT0" line.long 0x04 "EXTENDED_PRESCALE2,SPI Extended Prescale Register 2" hexmask.long.word 0x04 16.--26. 1. " EPRESCALE_FMT3 ,Extended prescale value for SPIFMT1" hexmask.long.word 0x04 0.--10. 1. " EPRESCALE_FMT2 ,Extended prescale value for SPIFMT0" endif sif cpuis("RM57L843-ZWT") group.long 0x140++0x07 line.long 0x00 "ECCDIAG_CTRL,ECC Diagnostic Control Register" bitfld.long 0x00 0.--3. " ECCDIAG_EN ,ECC diagnostic mode enable key bits" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" line.long 0x04 "ECCDIAG_STAT,ECC Diagnostic Status Register" eventfld.long 0x04 17. " DEFLG[1] ,Double bit error flag" "No error,Error" eventfld.long 0x04 16. " DEFLG[0] ,Double bit error flag" "No error,Error" textline " " eventfld.long 0x04 1. " SEFLG[1] ,Single bit error flag" "No error,Error" eventfld.long 0x04 0. " SEFLG[0] ,Single bit error flag" "No error,Error" hgroup.long 0x148++0x07 hide.long 0x00 "SBERRADDR1,Single Bit Error Address Register - RXRAM" in hide.long 0x04 "SBERRADDR0,Single Bit Error Address Register - TXRAM" endif width 0x0B tree.end sif (cpu()=="RM42L432") tree "SPI3" base ad:0xFFF7F800 width 6. group.long 0x00++0x03 line.long 0x00 "GCR0,Global Control Register 0" bitfld.long 0x00 0. " NRESET ,This is the reset bit for the module" "Reset,No reset" if (((d.l(ad:0xFFF7F800+0x04))&0x03)==0x03) group.long 0x04++0x03 line.long 0x00 "GCR1,Global Control Register 1" bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI pin direction determination" "Input/output,Output/input" bitfld.long 0x00 24. " SPIEN ,SPI enable" "Not active,Active" bitfld.long 0x00 16. " LOOP_BACK ,Internal Loop-back test mode" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " POWERDOWN ,SPI state machines power down state enable" "Active,Power down" bitfld.long 0x00 1. " CLKMOD ,Clock mode" "External,Internal" elif (((d.l(ad:0xFFF7F800+0x04))&0x03)==0x02) group.long 0x04++0x03 line.long 0x00 "GCR1,Global Control Register 1" bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI pin direction determination" "Input/output,Output/input" bitfld.long 0x00 24. " SPIEN ,SPI enable" "Not active,Active" bitfld.long 0x00 8. " POWERDOWN ,SPI state machines power down state enable" "Active,Power down" textline " " bitfld.long 0x00 1. " CLKMOD ,Clock mode" "External,Internal" elif (((d.l(ad:0xFFF7F800+0x04))&0x03)==0x01) group.long 0x04++0x03 line.long 0x00 "GCR1,Global Control Register 1" bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI pin direction determination" "Input/output,Output/input" bitfld.long 0x00 24. " SPIEN ,SPI enable" "Not active,Active" bitfld.long 0x00 8. " POWERDOWN ,SPI state machines power down state enable" "Active,Power down" textline " " bitfld.long 0x00 1. " CLKMOD ,Clock mode" "External,Internal" else group.long 0x04++0x03 line.long 0x00 "GCR1,Global Control Register 1" bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI pin direction determination" "Input/output,Output/input" bitfld.long 0x00 24. " SPIEN ,SPI enable" "Not active,Active" bitfld.long 0x00 8. " POWERDOWN ,SPI state machines power down state enable" "Active,Power down" textline " " bitfld.long 0x00 1. " CLKMOD ,Clock mode" "External,Internal" endif if (((d.l(ad:0xFFF7F800+0x04))&0x01)==0x01) group.long 0x08++0x03 line.long 0x00 "INT0,Interrupt Register" bitfld.long 0x00 24. " ENABLE_HIGHZ ,/SPIENA pin High-z enable" "Disabled,Enabled" textline " " sif (cpu()!="RM42L432") bitfld.long 0x00 16. " DMA_REQ_EN ,DMA request enable" "Not used,Generated" endif textline " " bitfld.long 0x00 9. " TXINTENA ,Transmit interrupt enable" "Not generated,Generated" bitfld.long 0x00 8. " RXINTENA ,Receive interrupt enable" "Not generated,Generated" textline " " bitfld.long 0x00 6. " RXOVRNINTENA ,Overrun interrupt enable" "Not generated,Generated" bitfld.long 0x00 4. " BITERRENA ,Enables interrupt on bit error" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " DESYNCENA ,Enables interrupt on De-synchronized slave" "Disabled,Enabled" bitfld.long 0x00 2. " PARERRENA ,Enables interrupt on parity error" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " TIMEOUTENA ,Enables interrupt on ENA signal Time-out" "Disabled,Enabled" bitfld.long 0x00 0. " DLEN_ERR_ENA ,Data length error interrupt enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "INT0,Interrupt Register" bitfld.long 0x00 24. " ENABLE_HIGHZ ,/SPIENA pin High-z enable" "Disabled,Enabled" textline " " sif (cpu()!="RM42L432") bitfld.long 0x00 16. " DMA_REQ_EN ,DMA request enable" "Not used,Generated" endif textline " " bitfld.long 0x00 9. " TXINTENA ,Transmit interrupt enable" "Not generated,Generated" bitfld.long 0x00 8. " RXINTENA ,Receive interrupt enable" "Not generated,Generated" textline " " bitfld.long 0x00 6. " RXOVRNINTENA ,Overrun interrupt enable" "Not generated,Generated" bitfld.long 0x00 4. " BITERRENA ,Enables interrupt on bit error" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " PARERRENA ,Enables interrupt on parity error" "Disabled,Enabled" bitfld.long 0x00 1. " TIMEOUTENA ,Enables interrupt on ENA signal Time-out" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " DLEN_ERR_ENA ,Data length error interrupt enable" "Disabled,Enabled" endif if (((d.l(ad:0xFFF7F800+0x04))&0x01)==0x01) group.long 0x0C++0x03 line.long 0x00 "LVL,Interrupt Level Register" bitfld.long 0x00 9. " TXINTLVL ,Transmit interrupt level" "INT0,INT1" bitfld.long 0x00 8. " RXINTLVL ,Receive interrupt level" "INT0,INT1" bitfld.long 0x00 6. " RXOVRNINTLVL ,Receive overrun interrupt level" "INT0,INT1" textline " " bitfld.long 0x00 4. " BITERRLVL ,Bit error interrupt level" "INT0,INT1" bitfld.long 0x00 3. " DESYNCLVL ,De-synchronized slave interrupt level" "INT0,INT1" bitfld.long 0x00 2. " PARERRLVL ,Parity error interrupt level" "INT0,INT1" textline " " bitfld.long 0x00 1. " TIMEOUTLVL ,/SPIENA pin Time-out interrupt level" "INT0,INT1" bitfld.long 0x00 0. " DLEN_ERR_LVL ,Data length error interrupt enable level" "INT0,INT1" else group.long 0x0C++0x03 line.long 0x00 "LVL,Interrupt Level Register" bitfld.long 0x00 9. " TXINTLVL ,Transmit interrupt level" "INT0,INT1" bitfld.long 0x00 8. " RXINTLVL ,Receive interrupt level" "INT0,INT1" bitfld.long 0x00 6. " RXOVRNINTLVL ,Receive overrun interrupt level" "INT0,INT1" textline " " bitfld.long 0x00 4. " BITERRLVL ,Bit error interrupt level" "INT0,INT1" bitfld.long 0x00 2. " PARERRLVL ,Parity error interrupt level" "INT0,INT1" bitfld.long 0x00 1. " TIMEOUTLVL ,/SPIENA pin Time-out interrupt level" "INT0,INT1" textline " " bitfld.long 0x00 0. " DLEN_ERR_LVL ,Data length error interrupt enable level" "INT0,INT1" endif if (((d.l(ad:0xFFF7F800+0x04))&0x01)==0x01) group.long 0x10++0x03 line.long 0x00 "FLG,Flag Register" bitfld.long 0x00 24. " BUF_INIT_ACTIVE ,Multibuffer initialization active" "Finished,Not finished" bitfld.long 0x00 9. " TXINTFLG ,Transmitter empty interrupt flag" "Full,Empty" textline " " eventfld.long 0x00 8. " RXINTFLG ,Receiver full interrupt flag" "Empty,Full" eventfld.long 0x00 6. " RXOVRNINTFLG ,Receiver overrun flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 4. " BITERRFLG ,Internal transmit data and transmitted data mismatch" "Not occurred,Occurred" eventfld.long 0x00 3. " DESYNCFLG ,Slave device De-Synchronization" "Not detected,Detected" textline " " eventfld.long 0x00 2. " PARITYERRFLG ,Parity error flag" "Not detected,Detected" eventfld.long 0x00 1. " TIMEOUTFLG ,Time-out due to Non-activation of ENA signal" "Not occurred,Occurred" textline " " eventfld.long 0x00 0. " DLEN_ERR_FLG ,Data length error flag" "Not occurred,Occurred" else group.long 0x10++0x03 line.long 0x00 "FLG,Flag Register" bitfld.long 0x00 24. " BUF_INIT_ACTIVE ,Multibuffer initialization active" "Not completed,Completed" bitfld.long 0x00 9. " TXINTFLG ,Transmitter empty interrupt flag" "No empty,Empty" textline " " eventfld.long 0x00 8. " RXINTFLG ,Receiver full interrupt flag" "No full,Full" eventfld.long 0x00 6. " RXOVRNINTFLG ,Receiver overrun flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 4. " BITERRFLG ,Internal transmit data and transmitted data mismatch" "Not occurred,Occurred" eventfld.long 0x00 2. " PARITYERRFLG ,Parity error flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 1. " TIMEOUTFLG ,Time-out due to Non-activation of ENA signal" "Not occurred,Occurred" eventfld.long 0x00 0. " DLEN_ERR_FLG ,Data length error flag" "Not occurred,Occurred" endif width 13. tree "SPI Pin Control Registers" tree "SPI Pin Control Registers 0-5" group.long 0x14++0x03 line.long 0x00 "PC0,Pin Control Register 0" bitfld.long 0x00 31. " SOMIFUN7 ,Slave out master in function 7" "GPIO,Spi/mibspi" bitfld.long 0x00 30. " SOMIFUN6 ,Slave out master in function 6" "GPIO,Spi/mibspi" bitfld.long 0x00 29. " SOMIFUN5 ,Slave out master in function 5" "GPIO,Spi/mibspi" textline " " bitfld.long 0x00 28. " SOMIFUN4 ,Slave out master in function 4" "GPIO,Spi/mibspi" bitfld.long 0x00 27. " SOMIFUN3 ,Slave out master in function 3" "GPIO,Spi/mibspi" bitfld.long 0x00 26. " SOMIFUN2 ,Slave out master in function 2" "GPIO,Spi/mibspi" textline " " bitfld.long 0x00 25. " SOMIFUN1 ,Slave out master in function 1" "GPIO,Spi/mibspi" bitfld.long 0x00 24. " SOMIFUN0 ,Slave out master in function 0" "GPIO,Spi/mibspi" bitfld.long 0x00 23. " SIMOFUN7 ,Slave in master out function 7" "GPIO,Spi/mibspi" textline " " bitfld.long 0x00 22. " SIMOFUN6 ,Slave in master out function 6" "GPIO,Spi/mibspi" bitfld.long 0x00 21. " SIMOFUN5 ,Slave in master out function 5" "GPIO,Spi/mibspi" bitfld.long 0x00 20. " SIMOFUN4 ,Slave in master out function 4" "GPIO,Spi/mibspi" textline " " bitfld.long 0x00 19. " SIMOFUN3 ,Slave in master out function 3" "GPIO,Spi/mibspi" bitfld.long 0x00 18. " SIMOFUN2 ,Slave in master out function 2" "GPIO,Spi/mibspi" bitfld.long 0x00 17. " SIMOFUN1 ,Slave in master out function 1" "GPIO,Spi/mibspi" textline " " bitfld.long 0x00 16. " SIMOFUN0 ,Slave in master out function 0" "GPIO,Spi/mibspi" bitfld.long 0x00 11. " SOMIFUN0 ,Slave out master in function" "GPIO,Spi/mibspi" bitfld.long 0x00 10. " SIMOFUN0 ,Slave in master out function" "GPIO,Spi/mibspi" textline " " bitfld.long 0x00 9. " CLKFUN ,Spi/mibspi clock function" "GPIO,Spi/mibspi" bitfld.long 0x00 8. " ENAFUN ,/SPIENA function" "GPIO,Spi/mibspi" bitfld.long 0x00 7. " SCSFUN7 ,/SPISCS7 function" "GPIO,SPI" textline " " bitfld.long 0x00 6. " SCSFUN6 ,/SPISCS6 function" "GPIO,SPI" bitfld.long 0x00 5. " SCSFUN5 ,/SPISCS5 function" "GPIO,SPI" bitfld.long 0x00 4. " SCSFUN4 ,/SPISCS4 function" "GPIO,SPI" textline " " bitfld.long 0x00 3. " SCSFUN3 ,/SPISCS3 function" "GPIO,SPI" bitfld.long 0x00 2. " SCSFUN2 ,/SPISCS2 function" "GPIO,SPI" bitfld.long 0x00 1. " SCSFUN1 ,/SPISCS1 function" "GPIO,SPI" textline " " bitfld.long 0x00 0. " SCSFUN0 ,/SPISCS0 function" "GPIO,SPI" group.long 0x18++0x03 line.long 0x00 "PC1,Pin Control Register 1" bitfld.long 0x00 31. " SOMIDIR7 ,SPISOMI7 direction" "Input,Output" bitfld.long 0x00 30. " SOMIDIR6 ,SPISOMI6 direction" "Input,Output" bitfld.long 0x00 29. " SOMIDIR5 ,SPISOMI5 direction" "Input,Output" textline " " bitfld.long 0x00 28. " SOMIDIR4 ,SPISOMI4 direction" "Input,Output" bitfld.long 0x00 27. " SOMIDIR3 ,SPISOMI3 direction" "Input,Output" bitfld.long 0x00 26. " SOMIDIR2 ,SPISOMI2 direction" "Input,Output" textline " " bitfld.long 0x00 25. " SOMIDIR1 ,SPISOMI1 direction" "Input,Output" bitfld.long 0x00 24. " SOMIDIR0 ,SPISOMI0 direction" "Input,Output" bitfld.long 0x00 23. " SIMODIR7 ,SPISIMO7 direction" "Input,Output" textline " " bitfld.long 0x00 22. " SIMODIR6 ,SPISIMO6 direction" "Input,Output" bitfld.long 0x00 21. " SIMODIR5 ,SPISIMO5 direction" "Input,Output" bitfld.long 0x00 20. " SIMODIR4 ,SPISIMO4 direction" "Input,Output" textline " " bitfld.long 0x00 19. " SIMODIR3 ,SPISIMO3 direction" "Input,Output" bitfld.long 0x00 18. " SIMODIR2 ,SPISIMO2 direction" "Input,Output" bitfld.long 0x00 17. " SIMODIR1 ,SPISIMO1 direction" "Input,Output" textline " " bitfld.long 0x00 16. " SIMODIR0 ,SPISIMO0 direction" "Input,Output" bitfld.long 0x00 11. " SOMIDIR0 ,SPISOMI0 direction" "Input,Output" bitfld.long 0x00 10. " SIMODIR0 ,SPISIMO0 direction" "Input,Output" textline " " bitfld.long 0x00 9. " CLKDIR ,SPICLK direction" "Input,Output" bitfld.long 0x00 8. " ENADIR ,/SPIENA direction" "Input,Output" bitfld.long 0x00 7. " SCSDIR7 ,/SPISCS7 direction" "Input,Output" textline " " bitfld.long 0x00 6. " SCSDIR6 ,/SPISCS6 direction" "Input,Output" bitfld.long 0x00 5. " SCSDIR5 ,/SPISCS5 direction" "Input,Output" bitfld.long 0x00 4. " SCSDIR4 ,/SPISCS4 direction" "Input,Output" textline " " bitfld.long 0x00 3. " SCSDIR3 ,/SPISCS3 direction" "Input,Output" bitfld.long 0x00 2. " SCSDIR2 ,/SPISCS2 direction" "Input,Output" bitfld.long 0x00 1. " SCSDIR1 ,/SPISCS1 direction" "Input,Output" textline " " bitfld.long 0x00 0. " SCSDIR0 ,/SPISCS0 direction" "Input,Output" rgroup.long 0x1C++0x03 line.long 0x00 "PC2,Pin Control Register 2" bitfld.long 0x00 31. " SOMIDIN7 ,SPISOMI7 data in" "Low,High" bitfld.long 0x00 30. " SOMIDIN6 ,SPISOMI6 data in" "Low,High" bitfld.long 0x00 29. " SOMIDIN5 ,SPISOMI5 data in" "Low,High" textline " " bitfld.long 0x00 28. " SOMIDIN4 ,SPISOMI4 data in" "Low,High" bitfld.long 0x00 27. " SOMIDIN3 ,SPISOMI3 data in" "Low,High" bitfld.long 0x00 26. " SOMIDIN2 ,SPISOMI2 data in" "Low,High" textline " " bitfld.long 0x00 25. " SOMIDIN1 ,SPISOMI1 data in" "Low,High" bitfld.long 0x00 24. " SOMIDIN0 ,SPISOMI0 data in" "Low,High" bitfld.long 0x00 23. " SIMODIN7 ,SPISIMO7 data in" "Low,High" textline " " bitfld.long 0x00 22. " SIMODIN6 ,SPISIMO6 data in" "Low,High" bitfld.long 0x00 21. " SIMODIN5 ,SPISIMO5 data in" "Low,High" bitfld.long 0x00 20. " SIMODIN4 ,SPISIMO4 data in" "Low,High" textline " " bitfld.long 0x00 19. " SIMODIN3 ,SPISIMO3 data in" "Low,High" bitfld.long 0x00 18. " SIMODIN2 ,SPISIMO2 data in" "Low,High" bitfld.long 0x00 17. " SIMODIN1 ,SPISIMO1 data in" "Low,High" textline " " bitfld.long 0x00 16. " SIMODIN0 ,SPISIMO0 data in" "Low,High" bitfld.long 0x00 11. " SOMIDIN0 ,SPISOMI0 data in" "Low,High" bitfld.long 0x00 10. " SIMODIN0 ,SPISIMO0 data in" "Low,High" textline " " bitfld.long 0x00 9. " CLKDIN ,Clock data in" "Low,High" bitfld.long 0x00 8. " ENADIN ,/SPIENA data in" "Low,High" bitfld.long 0x00 7. " SCSDIN7 ,SPISCS7 data in" "Low,High" textline " " bitfld.long 0x00 6. " SCSDIN6 ,SPISCS6 data in" "Low,High" bitfld.long 0x00 5. " SCSDIN5 ,SPISCS5 data in" "Low,High" bitfld.long 0x00 4. " SCSDIN4 ,SPISCS4 data in" "Low,High" textline " " bitfld.long 0x00 3. " SCSDIN3 ,SPISCS3 data in" "Low,High" bitfld.long 0x00 2. " SCSDIN2 ,SPISCS2 data in" "Low,High" bitfld.long 0x00 1. " SCSDIN1 ,SPISCS1 data in" "Low,High" textline " " bitfld.long 0x00 0. " SCSDIN0 ,SPISCS0 data in" "Low,High" group.long 0x20++0x0B line.long 0x00 "PC3,Pin Control Register 3" bitfld.long 0x00 31. " SOMIDOUT7 ,SPISOMI7 dataout write" "Low,High" bitfld.long 0x00 30. " SOMIDOUT6 ,SPISOMI6 dataout write" "Low,High" textline " " bitfld.long 0x00 29. " SOMIDOUT5 ,SPISOMI5 dataout write" "Low,High" bitfld.long 0x00 28. " SOMIDOUT4 ,SPISOMI4 dataout write" "Low,High" textline " " bitfld.long 0x00 27. " SOMIDOUT3 ,SPISOMI3 dataout write" "Low,High" bitfld.long 0x00 26. " SOMIDOUT2 ,SPISOMI2 dataout write" "Low,High" textline " " bitfld.long 0x00 25. " SOMIDOUT1 ,SPISOMI1 dataout write" "Low,High" bitfld.long 0x00 24. " SOMIDOUT0 ,SPISOMI0 dataout write" "Low,High" textline " " bitfld.long 0x00 23. " SIMODOUT7 ,SPISIMO7 dataout write" "Low,High" bitfld.long 0x00 22. " SIMODOUT6 ,SPISIMO6 dataout write" "Low,High" textline " " bitfld.long 0x00 21. " SIMODOUT5 ,SPISIMO5 dataout write" "Low,High" bitfld.long 0x00 20. " SIMODOUT4 ,SPISIMO4 dataout write" "Low,High" textline " " bitfld.long 0x00 19. " SIMODOUT3 ,SPISIMO3 dataout write" "Low,High" bitfld.long 0x00 18. " SIMODOUT2 ,SPISIMO2 dataout write" "Low,High" textline " " bitfld.long 0x00 17. " SIMODOUT1 ,SPISIMO1 dataout write" "Low,High" bitfld.long 0x00 16. " SIMODOUT0 ,SPISIMO0 dataout write" "Low,High" textline " " bitfld.long 0x00 11. " SOMIDOUT0 ,SPISOMI0 dataout write" "Low,High" bitfld.long 0x00 10. " SIMODOUT0 ,SPISIMO0 dataout write" "Low,High" textline " " bitfld.long 0x00 9. " CLKDOUT ,SPICLK dataout write" "Low,High" bitfld.long 0x00 8. " ENADOUT ,/SPIENA dataout write" "Low,High" textline " " bitfld.long 0x00 7. " SCSDOUT7 ,SPISCS7 dataout write" "Low,High" bitfld.long 0x00 6. " SCSDOUT6 ,SPISCS6 dataout write" "Low,High" textline " " bitfld.long 0x00 5. " SCSDOUT5 ,SPISCS5 dataout write" "Low,High" bitfld.long 0x00 4. " SCSDOUT4 ,SPISCS4 dataout write" "Low,High" textline " " bitfld.long 0x00 3. " SCSDOUT3 ,SPISCS3 dataout write" "Low,High" bitfld.long 0x00 2. " SCSDOUT2 ,SPISCS2 dataout write" "Low,High" textline " " bitfld.long 0x00 1. " SCSDOUT1 ,SPISCS1 dataout write" "Low,High" bitfld.long 0x00 0. " SCSDOUT0 ,SPISCS0 dataout write" "Low,High" line.long 0x04 "PC4,Pin Control Register 4" bitfld.long 0x04 31. " SOMISET7 ,SPISOMI7 dataout set" "Not set,Set" bitfld.long 0x04 30. " SOMISET6 ,SPISOMI6 dataout set" "Not set,Set" textline " " bitfld.long 0x04 29. " SOMISET5 ,SPISOMI5 dataout set" "Not set,Set" bitfld.long 0x04 28. " SOMISET4 ,SPISOMI4 dataout set" "Not set,Set" textline " " bitfld.long 0x04 27. " SOMISET3 ,SPISOMI3 dataout set" "Not set,Set" bitfld.long 0x04 26. " SOMISET2 ,SPISOMI2 dataout set" "Not set,Set" textline " " bitfld.long 0x04 25. " SOMISET1 ,SPISOMI1 dataout set" "Not set,Set" bitfld.long 0x04 24. " SOMISET0 ,SPISOMI0 dataout set" "Not set,Set" textline " " bitfld.long 0x04 23. " SIMOSET7 ,SPISIMO7 dataout set" "Not set,Set" bitfld.long 0x04 22. " SIMOSET6 ,SPISIMO6 dataout set" "Not set,Set" textline " " bitfld.long 0x04 21. " SIMOSET5 ,SPISIMO5 dataout set" "Not set,Set" bitfld.long 0x04 20. " SIMOSET4 ,SPISIMO4 dataout set" "Not set,Set" textline " " bitfld.long 0x04 19. " SIMOSET3 ,SPISIMO3 dataout set" "Not set,Set" bitfld.long 0x04 18. " SIMOSET2 ,SPISIMO2 dataout set" "Not set,Set" textline " " bitfld.long 0x04 17. " SIMOSET1 ,SPISIMO1 dataout set" "Not set,Set" bitfld.long 0x04 16. " SIMOSET0 ,SPISIMO0 dataout set" "Not set,Set" textline " " bitfld.long 0x04 11. " SOMISET0 ,SPISOMI0 dataout set" "Not set,Set" bitfld.long 0x04 10. " SIMOSET0 ,SPISIMO0 dataout set" "Not set,Set" textline " " bitfld.long 0x04 9. " CLKSET ,SPICLK dataout set" "Not set,Set" bitfld.long 0x04 8. " ENASET ,/SPIENA dataout set" "Not set,Set" textline " " bitfld.long 0x04 7. " SCSSET7 ,SPISCS7 dataout set" "Not set,Set" bitfld.long 0x04 6. " SCSSET6 ,SPISCS6 dataout set" "Not set,Set" textline " " bitfld.long 0x04 5. " SCSSET5 ,SPISCS5 dataout set" "Not set,Set" bitfld.long 0x04 4. " SCSSET4 ,SPISCS4 dataout set" "Not set,Set" textline " " bitfld.long 0x04 3. " SCSSET3 ,SPISCS3 dataout set" "Not set,Set" bitfld.long 0x04 2. " SCSSET2 ,SPISCS2 dataout set" "Not set,Set" textline " " bitfld.long 0x04 1. " SCSSET1 ,SPISCS1 dataout set" "Not set,Set" bitfld.long 0x04 0. " SCSSET0 ,SPISCS0 dataout set" "Not set,Set" line.long 0x08 "PC5,Pin Control Register 5" bitfld.long 0x08 31. " SOMICLR7 ,SPISOMI7 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 30. " SOMICLR6 ,SPISOMI6 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 29. " SOMICLR5 ,SPISOMI5 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 28. " SOMICLR4 ,SPISOMI4 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 27. " SOMICLR3 ,SPISOMI3 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 26. " SOMICLR2 ,SPISOMI2 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 25. " SOMICLR1 ,SPISOMI1 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 24. " SOMICLR0 ,SPISOMI0 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 23. " SIMOCLR7 ,SPISIMO7 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 22. " SIMOCLR6 ,SPISIMO6 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 21. " SIMOCLR5 ,SPISIMO5 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 20. " SIMOCLR4 ,SPISIMO4 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 19. " SIMOCLR3 ,SPISIMO3 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 18. " SIMOCLR2 ,SPISIMO2 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 17. " SIMOCLR1 ,SPISIMO1 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 16. " SIMOCLR0 ,SPISIMO0 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 11. " SOMICLR0 ,SPISOMI0 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 10. " SIMOCLR0 ,SPISIMO0 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 9. " CLKCLR ,SPICLK dataout clear" "Not cleared,Cleared" bitfld.long 0x08 8. " ENACLR ,/SPIENA dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 7. " SCSCLR7 ,SPISCS7 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 6. " SCSCLR6 ,SPISCS6 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 5. " SCSCLR5 ,SPISCS5 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 4. " SCSCLR4 ,SPISCS4 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 3. " SCSCLR3 ,SPISCS3 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 2. " SCSCLR2 ,SPISCS2 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 1. " SCSCLR1 ,SPISCS1 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 0. " SCSCLR0 ,SPISCS0 dataout clear" "Not cleared,Cleared" tree.end tree "SPI Pin Control Registers 6-8" group.long 0x2C++0x03 line.long 0x00 "PC6,Pin Control Register 1" bitfld.long 0x00 31. " SOMIPDR7 ,SPISOMI7 open drain enable" "High,Tri-stated" bitfld.long 0x00 30. " SOMIPDR6 ,SPISOMI6 open drain enable" "High,Tri-stated" bitfld.long 0x00 29. " SOMIPDR5 ,SPISOMI5 open drain enable" "High,Tri-stated" textline " " bitfld.long 0x00 28. " SOMIPDR4 ,SPISOMI4 open drain enable" "High,Tri-stated" bitfld.long 0x00 27. " SOMIPDR3 ,SPISOMI3 open drain enable" "High,Tri-stated" bitfld.long 0x00 26. " SOMIPDR2 ,SPISOMI2 open drain enable" "High,Tri-stated" textline " " bitfld.long 0x00 25. " SOMIPDR1 ,SPISOMI1 open drain enable" "High,Tri-stated" bitfld.long 0x00 24. " SOMIPDR0 ,SPISOMI0 open drain enable" "High,Tri-stated" bitfld.long 0x00 23. " SIMOPDR7 ,SPISIMO7 open drain enable" "High,Tri-stated" textline " " bitfld.long 0x00 22. " SIMOPDR6 ,SPISIMO6 open drain enable" "High,Tri-stated" bitfld.long 0x00 21. " SIMOPDR5 ,SPISIMO5 open drain enable" "High,Tri-stated" bitfld.long 0x00 20. " SIMOPDR4 ,SPISIMO4 open drain enable" "High,Tri-stated" textline " " bitfld.long 0x00 19. " SIMOPDR3 ,SPISIMO3 open drain enable" "High,Tri-stated" bitfld.long 0x00 18. " SIMOPDR2 ,SPISIMO2 open drain enable" "High,Tri-stated" bitfld.long 0x00 17. " SIMOPDR1 ,SPISIMO1 open drain enable" "High,Tri-stated" textline " " bitfld.long 0x00 16. " SIMOPDR0 ,SPISIMO0 open drain enable" "High,Tri-stated" bitfld.long 0x00 11. " SOMIPDR0 ,SPISOMI0 open drain enable" "High,Tri-stated" bitfld.long 0x00 10. " SIMOPDR0 ,SPISIMO0 open drain enable" "High,Tri-stated" textline " " bitfld.long 0x00 9. " CLKPDR ,SPICLK open drain enable" "High,Tri-stated" bitfld.long 0x00 8. " ENAPDR ,/SPIENA open drain enable" "High,Tri-stated" bitfld.long 0x00 7. " SCSPDR7 ,/SPISCS7 open drain" "High,Tri-stated" textline " " bitfld.long 0x00 6. " SCSPDR6 ,/SPISCS6 open drain" "High,Tri-stated" bitfld.long 0x00 5. " SCSPDR5 ,/SPISCS5 open drain" "High,Tri-stated" bitfld.long 0x00 4. " SCSPDR4 ,/SPISCS4 open drain" "High,Tri-stated" textline " " bitfld.long 0x00 3. " SCSPDR3 ,/SPISCS3 open drain" "High,Tri-stated" bitfld.long 0x00 2. " SCSPDR2 ,/SPISCS2 open drain" "High,Tri-stated" bitfld.long 0x00 1. " SCSPDR1 ,/SPISCS1 open drain" "High,Tri-stated" textline " " bitfld.long 0x00 0. " SCSPDR0 ,/SPISCS0 open drain" "High,Tri-stated" group.long 0x30++0x03 line.long 0x00 "PC7,Pin Control Register 7" bitfld.long 0x00 31. " SOMIPDIS7 ,SPISOMI7 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 30. " SOMIPDIS6 ,SPISOMI6 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 29. " SOMIPDIS5 ,SPISOMI5 pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 28. " SOMIPDIS4 ,SPISOMI4 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 27. " SOMIPDIS3 ,SPISOMI3 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 26. " SOMIPDIS2 ,SPISOMI2 pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 25. " SOMIPDIS1 ,SPISOMI1 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 24. " SOMIPDIS0 ,SPISOMI0 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 23. " SIMOPDIS7 ,SPISIMO7 pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 22. " SIMOPDIS6 ,SPISIMO6 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 21. " SIMOPDIS5 ,SPISIMO5 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 20. " SIMOPDIS4 ,SPISIMO4 pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 19. " SIMOPDIS3 ,SPISIMO3 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 18. " SIMOPDIS2 ,SPISIMO2 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 17. " SIMOPDIS1 ,SPISIMO1 pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 16. " SIMOPDIS0 ,SPISIMO0 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 11. " SOMIPDIS0 ,SPISOMI0 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 10. " SIMOPDIS0 ,SPISIMO pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 9. " CLKPDIS ,SPICLK pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 8. " ENAPDIS ,SPIENA pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 7. " SCSPDIS7 ,SPISCS7 pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 6. " SCSPDIS6 ,SPISCS6 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 5. " SCSPDIS5 ,SPISCS5 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 4. " SCSPDIS4 ,SPISCS4 pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 3. " SCSPDIS3 ,SPISCS3 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 2. " SCSPDIS2 ,SPISCS2 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 1. " SCSPDIS1 ,SPISCS1 pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 0. " SCSPDIS0 ,SPISCS0 pull control enable/disable" "Enabled,Disabled" group.long 0x34++0x03 line.long 0x00 "PC8,Pin Control Register 8" bitfld.long 0x00 31. " SOMIPSEL7 ,SPISOMI7 pull select" "Pull down,Pull up" bitfld.long 0x00 30. " SOMIPSEL6 ,SPISOMI6 pull select" "Pull down,Pull up" bitfld.long 0x00 29. " SOMIPSEL5 ,SPISOMI5 pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 28. " SOMIPSEL4 ,SPISOMI4 pull select" "Pull down,Pull up" bitfld.long 0x00 27. " SOMIPSEL3 ,SPISOMI3 pull select" "Pull down,Pull up" bitfld.long 0x00 26. " SOMIPSEL2 ,SPISOMI2 pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 25. " SOMIPSEL1 ,SPISOMI1 pull select" "Pull down,Pull up" bitfld.long 0x00 24. " SOMIPSEL0 ,SPISOMI0 pull select" "Pull down,Pull up" bitfld.long 0x00 23. " SIMOPSEL7 ,SPISIMO7 pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 22. " SIMOPSEL6 ,SPISIMO6 pull select" "Pull down,Pull up" bitfld.long 0x00 21. " SIMOPSEL5 ,SPISIMO5 pull select" "Pull down,Pull up" bitfld.long 0x00 20. " SIMOPSEL4 ,SPISIMO4 pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 19. " SIMOPSEL3 ,SPISIMO3 pull select" "Pull down,Pull up" bitfld.long 0x00 18. " SIMOPSEL2 ,SPISIMO2 pull select" "Pull down,Pull up" bitfld.long 0x00 17. " SIMOPSEL1 ,SPISIMO1 pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 16. " SIMOPSEL0 ,SPISIMO0 pull select" "Pull down,Pull up" bitfld.long 0x00 11. " SOMIPSEL ,SPISOMI pull select" "Pull down,Pull up" bitfld.long 0x00 10. " SIMOPSEL ,SPISIMO pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 9. " CLKPSEL ,SPICLK pull select" "Pull down,Pull up" bitfld.long 0x00 8. " ENAPSEL ,SPIENA pull select" "Pull down,Pull up" bitfld.long 0x00 7. " SCSPSEL7 ,/SPISCS7 pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 6. " SCSPSEL6 ,/SPISCS6 pull select" "Pull down,Pull up" bitfld.long 0x00 5. " SCSPSEL5 ,/SPISCS5 pull select" "Pull down,Pull up" bitfld.long 0x00 4. " SCSPSEL4 ,/SPISCS4 pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 3. " SCSPSEL3 ,/SPISCS3 pull select" "Pull down,Pull up" bitfld.long 0x00 2. " SCSPSEL2 ,/SPISCS2 pull select" "Pull down,Pull up" bitfld.long 0x00 1. " SCSPSEL1 ,/SPISCS1 pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 0. " SCSPSEL0 ,/SPISCS0 pull select" "Pull down,Pull up" tree.end tree.end width 7. textline " " if (((d.l(ad:0xFFF7F800+0x04))&0x1000000)==0x1000000) group.long 0x38++0x03 line.long 0x00 "DAT0,Transmit Data Register 0" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI / mibspi transmit data" else rgroup.long 0x38++0x03 line.long 0x00 "DAT0,Transmit Data Register 0" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI / mibspi transmit data" endif if (((d.l(ad:0xFFF7F800+0x04))&0x01)==0x01) group.long 0x3C++0x03 line.long 0x00 "DAT1,Transmit Data Register 1" bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Not active,Active" bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled" bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" textline " " hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Spi/mibspi transmit data" else group.long 0x3C++0x03 line.long 0x00 "DAT1,Transmit Data Register 1" bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Spi/mibspi transmit data" endif hgroup.long 0x40++0x03 hide.long 0x00 "BUF,Receive Buffer Register" in if (((d.l(ad:0xFFF7F800+0x04))&0x01)==0x01) rgroup.long 0x44++0x03 line.long 0x00 "EMU,Emulation Register" bitfld.long 0x00 31. " RXEMPTY ,Receive data buffer empty" "No empty,Empty" bitfld.long 0x00 30. " RXOVR ,Receive data buffer overrun" "No overrun,Overrun" bitfld.long 0x00 29. " TXFULL ,Transmit data buffer full" "Empty,Full" textline " " bitfld.long 0x00 28. " BITERR ,Mismatch of internal transmit data and transmitted data" "Not occurred,Occurred" bitfld.long 0x00 27. " DESYNC ,De-synchronization of slave device" "No de-synchronized,De-synchronized" bitfld.long 0x00 26. " PARITYERR ,Calculated parity differs from received parity bit" "No error,Error" textline " " bitfld.long 0x00 25. " TIMEOUT ,Time-out due to Non-activation of ENA pin" "Not occurred,Occurred" bitfld.long 0x00 24. " DLENERR ,Data length error flag" "No error,Error" hexmask.long.byte 0x00 16.--23. 1. " LCSNR ,Last chip select number" textline " " hexmask.long.word 0x00 0.--15. 1. " RXDATA ,SPI receive data" else rgroup.long 0x44++0x03 line.long 0x00 "EMU,Emulation Register" bitfld.long 0x00 31. " RXEMPTY ,Receive data buffer empty" "No empty,Empty" bitfld.long 0x00 30. " RXOVR ,Receive data buffer overrun" "No overrun,Overrun" bitfld.long 0x00 29. " TXFULL ,Transmit data buffer full" "Empty,Full" textline " " bitfld.long 0x00 28. " BITERR ,Mismatch of internal transmit data and transmitted data" "Not occurred,Occurred" bitfld.long 0x00 26. " PARITYERR ,Calculated parity differs from received parity bit" "No error,Error" bitfld.long 0x00 24. " DLENERR ,Data length error flag" "No error,Error" textline " " hexmask.long.byte 0x00 16.--23. 1. " LCSNR ,Last chip select number" hexmask.long.word 0x00 0.--15. 1. " RXDATA ,SPI receive data" endif if (((d.l(ad:0xFFF7F800+0x04))&0x01)==0x01) group.long 0x48++0x03 line.long 0x00 "DELAY,Delay Register" hexmask.long.byte 0x00 24.--31. 1. " C2TDELAY ,Chip select active to transmit start delay" hexmask.long.byte 0x00 16.--23. 1. " T2CDELAY ,Transmit end to chip select inactive delay" hexmask.long.byte 0x00 8.--15. 1. " T2EDELAY ,Transmit data finished to ENA pin inactive time out" textline " " hexmask.long.byte 0x00 0.--7. 1. " C2EDELAY ,Chip select active to ENA signal active time out" else hgroup.long 0x48++0x03 hide.long 0x00 "DELAY,Delay Register" endif group.long 0x4C++0x03 line.long 0x00 "DEF,Default Chip Select Register" bitfld.long 0x00 7. " CSDEF7 ,Chip select default pattern 7" "Low,High" bitfld.long 0x00 6. " CSDEF6 ,Chip select default pattern 6" "Low,High" bitfld.long 0x00 5. " CSDEF5 ,Chip select default pattern 5" "Low,High" bitfld.long 0x00 4. " CSDEF4 ,Chip select default pattern 4" "Low,High" textline " " bitfld.long 0x00 3. " CSDEF3 ,Chip select default pattern 3" "Low,High" bitfld.long 0x00 2. " CSDEF2 ,Chip select default pattern 2" "Low,High" bitfld.long 0x00 1. " CSDEF1 ,Chip select default pattern 1" "Low,High" bitfld.long 0x00 0. " CSDEF0 ,Chip select default pattern 0" "Low,High" width 6. tree "SPI Data Format Registers" group.long 0x50++0x03 line.long 0x00 "FMT0,Data Format Register 0" bitfld.long 0x00 24.--29. " WDELAY0 ,Delay in between transmissions for data format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " PARPOL0 ,Parity polarity" "Even,Odd" bitfld.long 0x00 22. " PARITY0_ENA ,Parity enable for data format 0" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " WAITENA0 ,Master waits for ENA signal from slave for data format 0" "Not wait,Wait" bitfld.long 0x00 20. " SHIFTDIR0 ,Shift direction for data format 0" "MSB,LSB" bitfld.long 0x00 18. " DIS_CS_TIMERS0 ,Disable chipselect timers for this format register" "No,Yes" textline " " bitfld.long 0x00 17. " POLARITY0 ,SPI data format 0 clock polarity" "Low-inactive,High-inactive" bitfld.long 0x00 16. " PHASE0 ,SPI data format 0 clock delay" "Not delayed,Delayed" hexmask.long.byte 0x00 8.--15. 1. " PRESCALE0 ,SPI data format 0 prescaler" textline " " bitfld.long 0x00 0.--4. " CHARLEN0 ,SPI data format 0 data word length" ",,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..." group.long 0x54++0x03 line.long 0x00 "FMT1,Data Format Register 1" bitfld.long 0x00 24.--29. " WDELAY1 ,Delay in between transmissions for data format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " PARPOL1 ,Parity polarity" "Even,Odd" bitfld.long 0x00 22. " PARITY1_ENA ,Parity enable for data format 1" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " WAITENA1 ,Master waits for ENA signal from slave for data format 1" "Not wait,Wait" bitfld.long 0x00 20. " SHIFTDIR1 ,Shift direction for data format 1" "MSB,LSB" bitfld.long 0x00 18. " DIS_CS_TIMERS1 ,Disable chipselect timers for this format register" "No,Yes" textline " " bitfld.long 0x00 17. " POLARITY1 ,SPI data format 1 clock polarity" "Low-inactive,High-inactive" bitfld.long 0x00 16. " PHASE1 ,SPI data format 1 clock delay" "Not delayed,Delayed" hexmask.long.byte 0x00 8.--15. 1. " PRESCALE1 ,SPI data format 1 prescaler" textline " " bitfld.long 0x00 0.--4. " CHARLEN1 ,SPI data format 1 data word length" ",,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..." group.long 0x58++0x03 line.long 0x00 "FMT2,Data Format Register 2" bitfld.long 0x00 24.--29. " WDELAY2 ,Delay in between transmissions for data format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " PARPOL2 ,Parity polarity" "Even,Odd" bitfld.long 0x00 22. " PARITY2_ENA ,Parity enable for data format 2" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " WAITENA2 ,Master waits for ENA signal from slave for data format 2" "Not wait,Wait" bitfld.long 0x00 20. " SHIFTDIR2 ,Shift direction for data format 2" "MSB,LSB" bitfld.long 0x00 18. " DIS_CS_TIMERS2 ,Disable chipselect timers for this format register" "No,Yes" textline " " bitfld.long 0x00 17. " POLARITY2 ,SPI data format 2 clock polarity" "Low-inactive,High-inactive" bitfld.long 0x00 16. " PHASE2 ,SPI data format 2 clock delay" "Not delayed,Delayed" hexmask.long.byte 0x00 8.--15. 1. " PRESCALE2 ,SPI data format 2 prescaler" textline " " bitfld.long 0x00 0.--4. " CHARLEN2 ,SPI data format 2 data word length" ",,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..." group.long 0x5C++0x03 line.long 0x00 "FMT3,Data Format Register 3" bitfld.long 0x00 24.--29. " WDELAY3 ,Delay in between transmissions for data format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " PARPOL3 ,Parity polarity" "Even,Odd" bitfld.long 0x00 22. " PARITY3_ENA ,Parity enable for data format 3" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " WAITENA3 ,Master waits for ENA signal from slave for data format 3" "Not wait,Wait" bitfld.long 0x00 20. " SHIFTDIR3 ,Shift direction for data format 3" "MSB,LSB" bitfld.long 0x00 18. " DIS_CS_TIMERS3 ,Disable chipselect timers for this format register" "No,Yes" textline " " bitfld.long 0x00 17. " POLARITY3 ,SPI data format 3 clock polarity" "Low-inactive,High-inactive" bitfld.long 0x00 16. " PHASE3 ,SPI data format 3 clock delay" "Not delayed,Delayed" hexmask.long.byte 0x00 8.--15. 1. " PRESCALE3 ,SPI data format 3 prescaler" textline " " bitfld.long 0x00 0.--4. " CHARLEN3 ,SPI data format 3 data word length" ",,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..." tree.end width 12. tree "SPI Interrupt Vector Registers" if (((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) rgroup.long 0x60++0x03 line.long 0x00 "TGINTVECT0,Transfer Group Interrupt Vector Register 0" bitfld.long 0x00 1.--5. " INTVECT0 ,Interrupt vector for interrupt line INT0" "No interrupt,Interrupt of transfer group 0,Interrupt of transfer group 1,Interrupt of transfer group 2,Interrupt of transfer group 3,Interrupt of transfer group 4,Interrupt of transfer group 5,Interrupt of transfer group 6,Interrupt of transfer group 7,Interrupt of transfer group 8,Interrupt of transfer group 9,Interrupt of transfer group 10,Interrupt of transfer group 11,Interrupt of transfer group 12,Interrupt of transfer group 13,Interrupt of transfer group 14,Interrupt of transfer group 15,Interrupt/spiint0,,RXORN interrupt,?..." bitfld.long 0x00 0. " SUSPEND0 ,Transfer suspended/finished interrupt" "Suspended,Finished" else rgroup.long 0x60++0x03 line.long 0x00 "TGINTVECT0,Transfer Group Interrupt Vector Register 0" bitfld.long 0x00 1.--5. " INTVECT0 ,Interrupt vector for interrupt line INT0" "No interrupt,,,,,,,,,,,,,,,,,Interrupt/spiint0,Receive buffer full interrupt,Receive buffer overrun interrupt,Transmit buffer empty interrupt,?..." endif if (((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) rgroup.long 0x64++0x03 line.long 0x00 "TGINTVECT1,Transfer Group Interrupt Vector Register 1" bitfld.long 0x00 1.--5. " INTVECT1 ,Interrupt vector for interrupt line INT1" "No interrupt,Interrupt of transfer group 0,Interrupt of transfer group 1,Interrupt of transfer group 2,Interrupt of transfer group 3,Interrupt of transfer group 4,Interrupt of transfer group 5,Interrupt of transfer group 6,Interrupt of transfer group 7,Interrupt of transfer group 8,Interrupt of transfer group 9,Interrupt of transfer group 10,Interrupt of transfer group 11,Interrupt of transfer group 12,Interrupt of transfer group 13,Interrupt of transfer group 14,Interrupt of transfer group 15,Interrupt/spiint1,,RXORN interrupt,?..." bitfld.long 0x00 0. " SUSPEND1 ,Transfer suspended/finished interrupt" "Suspended,Finished" else rgroup.long 0x64++0x03 line.long 0x00 "TGINTVECT1,Transfer Group Interrupt Vector Register 1" bitfld.long 0x00 1.--5. " INTVECT1 ,Interrupt vector for interrupt line INT1" "No interrupt,,,,,,,,,,,,,,,,,Interrupt/spiint1,Receive buffer full interrupt,Receive buffer overrun interrupt,Transmit buffer empty interrupt,?..." endif tree.end width 8. textline " " if (((d.l(ad:0xFFF7F800+0x3C))&0x3000000)==0x00) group.long 0x6C++0x03 line.long 0x00 "PMCTRL,Parallel/modulo Mode Control Register" bitfld.long 0x00 5. " MOD_CLK_POL_0 ,Modulo mode SPICLK polarity" "Normal,Inverted" bitfld.long 0x00 2.--4. " MMODE_0 ,SPI data line selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..." bitfld.long 0x00 0.--1. " PMODE_0 ,Parallel mode" "1-data,2-data,4-data,8-data" elif (((d.l(ad:0xFFF7F800+0x3C))&0x3000000)==0x1000000) group.long 0x6C++0x03 line.long 0x00 "PMCTRL,Parallel/modulo Mode Control Register" bitfld.long 0x00 13. " MOD_CLK_POL_1 ,Modulo mode SPICLK polarity" "Normal,Inverted" bitfld.long 0x00 10.--12. " MMODE_1 ,SPI data line selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..." bitfld.long 0x00 8.--9. " PMODE_1 ,Parallel mode" "1-data,2-data,4-data,8-data" elif (((d.l((ad:0xFFF7F800+0x3C)))&0x3000000)==0x2000000) group.long 0x6C++0x03 line.long 0x00 "PMCTRL,Parallel/modulo Mode Control Register" bitfld.long 0x00 21. " MOD_CLK_POL_2 ,Modulo mode SPICLK polarity" "Normal,Inverted" bitfld.long 0x00 18.--20. " MMODE_2 ,SPI data line selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..." bitfld.long 0x00 16.--17. " PMODE_2 ,Parallel mode" "1-data,2-data,4-data,8-data" else group.long 0x6C++0x03 line.long 0x00 "PMCTRL,Parallel/modulo Mode Control Register" bitfld.long 0x00 29. " MOD_CLK_POL_3 ,Modulo mode SPICLK polarity" "Normal,Inverted" bitfld.long 0x00 26.--28. " MMODE_3 ,SPI data line selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..." bitfld.long 0x00 24.--25. " PMODE_3 ,Parallel mode" "1-data,2-data,4-data,8-data" endif width 11. tree "Mibspi Registers" group.long 0x70++0x03 line.long 0x00 "MIBSPIE,Mibspi Enable Register" bitfld.long 0x00 16. " RX_RAM_ACCESS ,Receive RAM access control bit" "RX not writable,R/W" bitfld.long 0x00 0. " MSPIENA ,Multibuffer mode enable" "Disabled,Enabled" if (((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) group.long 0x74++0x03 line.long 0x00 "TGITENST,Mibspi Transfer Group Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTEN_RDY15_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x04 30. " INTEN_RDY14_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 29. 0x00 29. 0x04 29. " INTEN_RDY13_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x04 28. " INTEN_RDY12_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. 0x00 27. 0x04 27. " INTEN_RDY11_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x04 26. " INTEN_RDY10_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x04 25. " INTEN_RDY9_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x04 24. " INTEN_RDY8_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. 0x00 23. 0x04 23. " INTEN_RDY7_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x04 22. " INTEN_RDY6_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. 0x00 21. 0x04 21. " INTEN_RDY5_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x04 20. " INTEN_RDY4_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x04 19. " INTEN_RDY3_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x04 18. " INTEN_RDY2_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. 0x00 17. 0x04 17. " INTEN_RDY1_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x04 16. " INTEN_RDY0_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 15. 0x00 15. 0x04 15. " INTEN_SUS15_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x04 14. " INTEN_SUS14_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x04 13. " INTEN_SUS13_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x04 12. " INTEN_SUS12_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 11. 0x00 11. 0x04 11. " INTEN_SUS11_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x04 10. " INTEN_SUS10_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. 0x00 9. 0x04 9. " INTEN_SUS9_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x04 8. " INTEN_SUS8_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x04 7. " INTEN_SUS7_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x04 6. " INTEN_SUS6_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x00 5. 0x04 5. " INTEN_SUS5_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x04 4. " INTEN_SUS4_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. 0x00 3. 0x04 3. " INTEN_SUS3_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x04 2. " INTEN_SUS2_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x04 1. " INTEN_SUS1_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " INTEN_SUS0_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" group.long 0x7C++0x03 line.long 0x00 "TGITLVST,Mibspi Transfer Group Interrupt Level Set Register" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTLVL_RDY15_SET/CLR ,Transfer group completed interrupt level 15" "INT0,INT1" setclrfld.long 0x00 30. 0x00 30. 0x04 30. " INTLVL_RDY14_SET/CLR ,Transfer group completed interrupt level 14" "INT0,INT1" textline " " setclrfld.long 0x00 29. 0x00 29. 0x04 29. " INTLVL_RDY13_SET/CLR ,Transfer group completed interrupt level 13" "INT0,INT1" setclrfld.long 0x00 28. 0x00 28. 0x04 28. " INTLVL_RDY12_SET/CLR ,Transfer group completed interrupt level 12" "INT0,INT1" textline " " setclrfld.long 0x00 27. 0x00 27. 0x04 27. " INTLVL_RDY11_SET/CLR ,Transfer group completed interrupt level 11" "INT0,INT1" setclrfld.long 0x00 26. 0x00 26. 0x04 26. " INTLVL_RDY10_SET/CLR ,Transfer group completed interrupt level 10" "INT0,INT1" textline " " setclrfld.long 0x00 25. 0x00 25. 0x04 25. " INTLVL_RDY9_SET/CLR ,Transfer group completed interrupt level set 9" "INT0,INT1" setclrfld.long 0x00 24. 0x00 24. 0x04 24. " INTLVL_RDY8_SET/CLR ,Transfer group completed interrupt level set 8" "INT0,INT1" textline " " setclrfld.long 0x00 23. 0x00 23. 0x04 23. " INTLVL_RDY7_SET/CLR ,Transfer group completed interrupt level set 7" "INT0,INT1" setclrfld.long 0x00 22. 0x00 22. 0x04 22. " INTLVL_RDY6_SET/CLR ,Transfer group completed interrupt level set 6" "INT0,INT1" textline " " setclrfld.long 0x00 21. 0x00 21. 0x04 21. " INTLVL_RDY5_SET/CLR ,Transfer group completed interrupt level set 5" "INT0,INT1" setclrfld.long 0x00 20. 0x00 20. 0x04 20. " INTLVL_RDY4_SET/CLR ,Transfer group completed interrupt level set 4" "INT0,INT1" textline " " setclrfld.long 0x00 19. 0x00 19. 0x04 19. " INTLVL_RDY3_SET/CLR ,Transfer group completed interrupt level set 3" "INT0,INT1" setclrfld.long 0x00 18. 0x00 18. 0x04 18. " INTLVL_RDY2_SET/CLR ,Transfer group completed interrupt level set 2" "INT0,INT1" textline " " setclrfld.long 0x00 17. 0x00 17. 0x04 17. " INTLVL_RDY1_SET/CLR ,Transfer group completed interrupt level set 1" "INT0,INT1" setclrfld.long 0x00 16. 0x00 16. 0x04 16. " INTLVL_RDY0_SET/CLR ,Transfer group completed interrupt level set 0" "INT0,INT1" textline " " setclrfld.long 0x00 15. 0x00 15. 0x04 15. " INTLVL_SUS15_SET/CLR ,Transfer group suspended interrupt level set 15" "INT0,INT1" setclrfld.long 0x00 14. 0x00 14. 0x04 14. " INTLVL_SUS14_SET/CLR ,Transfer group suspended interrupt level set 14" "INT0,INT1" textline " " setclrfld.long 0x00 13. 0x00 13. 0x04 13. " INTLVL_SUS13_SET/CLR ,Transfer group suspended interrupt level set 13" "INT0,INT1" setclrfld.long 0x00 12. 0x00 12. 0x04 12. " INTLVL_SUS12_SET/CLR ,Transfer group suspended interrupt level set 12" "INT0,INT1" textline " " setclrfld.long 0x00 11. 0x00 11. 0x04 11. " INTLVL_SUS11_SET/CLR ,Transfer group suspended interrupt level set 11" "INT0,INT1" setclrfld.long 0x00 10. 0x00 10. 0x04 10. " INTLVL_SUS10_SET/CLR ,Transfer group suspended interrupt level set 10" "INT0,INT1" textline " " setclrfld.long 0x00 9. 0x00 9. 0x04 9. " INTLVL_SUS9_SET/CLR ,Transfer group suspended interrupt level set 9" "INT0,INT1" setclrfld.long 0x00 8. 0x00 8. 0x04 8. " INTLVL_SUS8_SET/CLR ,Transfer group suspended interrupt level set 8" "INT0,INT1" textline " " setclrfld.long 0x00 7. 0x00 7. 0x04 7. " INTLVL_SUS7_SET/CLR ,Transfer group suspended interrupt level set 7" "INT0,INT1" setclrfld.long 0x00 6. 0x00 6. 0x04 6. " INTLVL_SUS6_SET/CLR ,Transfer group suspended interrupt level set 6" "INT0,INT1" textline " " setclrfld.long 0x00 5. 0x00 5. 0x04 5. " INTLVL_SUS5_SET/CLR ,Transfer group suspended interrupt level set 5" "INT0,INT1" setclrfld.long 0x00 4. 0x00 4. 0x04 4. " INTLVL_SUS4_SET/CLR ,Transfer group suspended interrupt level set 4" "INT0,INT1" textline " " setclrfld.long 0x00 3. 0x00 3. 0x04 3. " INTLVL_SUS3_SET/CLR ,Transfer group suspended interrupt level set 3" "INT0,INT1" setclrfld.long 0x00 2. 0x00 2. 0x04 2. " INTLVL_SUS2_SET/CLR ,Transfer group suspended interrupt level set 2" "INT0,INT1" textline " " setclrfld.long 0x00 1. 0x00 1. 0x04 1. " INTLVL_SUS1_SET/CLR ,Transfer group suspended interrupt level set 1" "INT0,INT1" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " INTLVL_SUS0_SET/CLR ,Transfer group suspended interrupt level set 0" "INT0,INT1" group.long 0x84++0x03 line.long 0x00 "TGINTFLAG,Transfer Group Interrupt Flag Register" eventfld.long 0x00 31. " INTFLGRDY15 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" eventfld.long 0x00 30. " INTFLGRDY14 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 29. " INTFLGRDY13 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" eventfld.long 0x00 28. " INTFLGRDY12 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 27. " INTFLGRDY11 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" eventfld.long 0x00 26. " INTFLGRDY10 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 25. " INTFLGRDY9 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" eventfld.long 0x00 24. " INTFLGRDY8 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 23. " INTFLGRDY7 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" eventfld.long 0x00 22. " INTFLGRDY6 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 21. " INTFLGRDY5 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" eventfld.long 0x00 20. " INTFLGRDY4 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 19. " INTFLGRDY3 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" eventfld.long 0x00 18. " INTFLGRDY2 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 17. " INTFLGRDY1 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" eventfld.long 0x00 16. " INTFLGRDY0 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 15. " INTFLGSUS15 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" eventfld.long 0x00 14. " INTFLGSUS14 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 13. " INTFLGSUS13 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" eventfld.long 0x00 12. " INTFLGSUS12 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 11. " INTFLGSUS11 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" eventfld.long 0x00 10. " INTFLGSUS10 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 9. " INTFLGSUS9 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" eventfld.long 0x00 8. " INTFLGSUS8 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 7. " INTFLGSUS7 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" eventfld.long 0x00 6. " INTFLGSUS6 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 5. " INTFLGSUS5 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" eventfld.long 0x00 4. " INTFLGSUS4 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " INTFLGSUS3 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" eventfld.long 0x00 2. " INTFLGSUS2 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 1. " INTFLGSUS1 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " INTFLGSUS0 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" group.long 0x90++0x03 line.long 0x00 "TICKCNT,Tick Count Register" bitfld.long 0x00 31. " TICKENA ,Tick counter enable" "Disabled,Enabled" bitfld.long 0x00 30. " RELOAD ,Re-load tick counter" "No effect,Reload" textline " " bitfld.long 0x00 28.--29. " CLKCTRL ,Tick counter clock source control" "Format 0,Format 1,Format 2,Format 3" hexmask.long.word 0x00 0.--15. 1. " TICKVALUE ,Initial value for tick counter" group.long 0x94++0x03 line.long 0x00 "LTGPEND,Last Transfer Group End Pointer" bitfld.long 0x00 24.--28. " TG_IN_SERVICE ,Transfer group currently being serviced by the sequencer" "Not serviced,Group0,Group1,Group2,Group3,Group4,Group5,Group6,Group7,Group8,Group9,Group10,Group11,Group12,Group13,Group14,Group15,?..." hexmask.long.byte 0x00 8.--14. 1. " LPEND ,Last transfer group end pointer" else hgroup.long 0x74++0x03 hide.long 0x00 "TGITENST,Mibspi Transfer Group Interrupt Enable Register" hgroup.long 0x7C++0x03 hide.long 0x00 "TGITLVST,Mibspi Transfer Group Interrupt Level Register" hgroup.long 0x84++0x03 hide.long 0x00 "TGINTFLAG,Transfer Group Interrupt Flag Register" hgroup.long 0x90++0x03 hide.long 0x00 "TICKCNT,Tick Count Register" hgroup.long 0x94++0x03 hide.long 0x00 "LTGPEND,Last Transfer Group End Pointer" endif width 20. tree "Mibspi Transfer Group Control Registers" if (((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) group.long 0x98++0x03 line.long 0x00 "TG0CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA0 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT0 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST0 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD0 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT0 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC0 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART0 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT0 ,Transfer group pointer to current buffer" group.long 0x9C++0x03 line.long 0x00 "TG1CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA1 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT1 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST1 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD1 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT1 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC1 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART1 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT1 ,Transfer group pointer to current buffer" group.long 0xA0++0x03 line.long 0x00 "TG2CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA2 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT2 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST2 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD2 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT2 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC2 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART2 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT2 ,Transfer group pointer to current buffer" group.long 0xA4++0x03 line.long 0x00 "TG3CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA3 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT3 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST3 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD3 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT3 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC3 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART3 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT3 ,Transfer group pointer to current buffer" group.long 0xA8++0x03 line.long 0x00 "TG4CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA4 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT4 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST4 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD4 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT4 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC4 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART4 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT4 ,Transfer group pointer to current buffer" group.long 0xAC++0x03 line.long 0x00 "TG5CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA5 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT5 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST5 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD5 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT5 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC5 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART5 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT5 ,Transfer group pointer to current buffer" group.long 0xB0++0x03 line.long 0x00 "TG6CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA6 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT6 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST6 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD6 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT6 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC6 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART6 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT6 ,Transfer group pointer to current buffer" group.long 0xB4++0x03 line.long 0x00 "TG7CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA7 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT7 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST7 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD7 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT7 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC7 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART7 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT7 ,Transfer group pointer to current buffer" group.long 0xB8++0x03 line.long 0x00 "TG8CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA8 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT8 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST8 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD8 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT8 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC8 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART8 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT8 ,Transfer group pointer to current buffer" group.long 0xBC++0x03 line.long 0x00 "TG9CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA9 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT9 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST9 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD9 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT9 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC9 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART9 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT9 ,Transfer group pointer to current buffer" group.long 0xC0++0x03 line.long 0x00 "TG10CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA10 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT10 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST10 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD10 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT10 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC10 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART10 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT10 ,Transfer group pointer to current buffer" group.long 0xC4++0x03 line.long 0x00 "TG11CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA11 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT11 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST11 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD11 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT11 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC11 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART11 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT11 ,Transfer group pointer to current buffer" group.long 0xC8++0x03 line.long 0x00 "TG12CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA12 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT12 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST12 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD12 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT12 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC12 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART12 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT12 ,Transfer group pointer to current buffer" group.long 0xCC++0x03 line.long 0x00 "TG13CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA13 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT13 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST13 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD13 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT13 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC13 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART13 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT13 ,Transfer group pointer to current buffer" group.long 0xD0++0x03 line.long 0x00 "TG14CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA14 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT14 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST14 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD14 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT14 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC14 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART14 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT14 ,Transfer group pointer to current buffer" group.long 0xD4++0x03 line.long 0x00 "TG15CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA15 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT15 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST15 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD15 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT15 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC15 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART15 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT15 ,Transfer group pointer to current buffer" else hgroup.long 0x98++0x03 hide.long 0x00 "TG0CTRL,Mibspi Transfer Group Control Register" hgroup.long 0x9C++0x03 hide.long 0x00 "TG1CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xA0++0x03 hide.long 0x00 "TG2CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xA4++0x03 hide.long 0x00 "TG3CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xA8++0x03 hide.long 0x00 "TG4CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xAC++0x03 hide.long 0x00 "TG5CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xB0++0x03 hide.long 0x00 "TG6CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xB4++0x03 hide.long 0x00 "TG7CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xB8++0x03 hide.long 0x00 "TG8CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xBC++0x03 hide.long 0x00 "TG9CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xC0++0x03 hide.long 0x00 "TG10CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xC4++0x03 hide.long 0x00 "TG11CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xC8++0x03 hide.long 0x00 "TG12CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xCC++0x03 hide.long 0x00 "TG13CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xD0++0x03 hide.long 0x00 "TG14CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xD4++0x03 hide.long 0x00 "TG15CTRL,Mibspi Transfer Group Control Register" endif tree.end textline " " sif (cpu()!="RM42L432") if ((((d.l(ad:0xFFF7F800+0x04))&0x01)==0x01)&&((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) group.long 0xD8++0x03 line.long 0x00 "DMA0CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT0 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 0" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID0 ,Buffer utilized for DMA transfer 0" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP0 ,Receive data DMA request map 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP0 ,Transmit data DMA channel 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA0 ,Receive data DMA channel enable 0" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA0 ,Transmit data DMA channel enable 0" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK0 ,Non-interleaved DMA block transfer 0" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT0 ,Initial count of DMA transfers 0" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT170 ,The 17th bit of COUNT field of DMA0COUNT register" "Low,High" bitfld.long 0x00 0.--5. " COUNT0 ,Actual number of remaining DMA transfer 0" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l(ad:0xFFF7F800+0x04))&0x01)==0x00)&&((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) group.long 0xD8++0x03 line.long 0x00 "DMA0CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT0 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 0" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID0 ,Buffer utilized for DMA transfer 0" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP0 ,Receive data DMA request map 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP0 ,Transmit data DMA channel 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA0 ,Receive data DMA channel enable 0" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA0 ,Transmit data DMA channel enable 0" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT0 ,Initial count of DMA transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT170 ,The 17th bit of COUNT field of DMA0COUNT register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT0 ,Actual number of remaining DMA transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xD8++0x03 hide.long 0x00 "DMA0CTRL,Mibspi DMA Channel Control Register" endif if ((((d.l(ad:0xFFF7F800+0x04))&0x01)==0x01)&&((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) group.long 0xDC++0x03 line.long 0x00 "DMA1CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT1 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 1" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID1 ,Buffer utilized for DMA transfer 1" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP1 ,Receive data DMA request map 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP1 ,Transmit data DMA channel 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA1 ,Receive data DMA channel enable 1" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA1 ,Transmit data DMA channel enable 1" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK1 ,Non-interleaved DMA block transfer 1" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT1 ,Initial count of DMA transfers 1" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT171 ,The 17th bit of COUNT field of DMA1COUNT register" "Low,High" bitfld.long 0x00 0.--5. " COUNT1 ,Actual number of remaining DMA transfer 1" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l(ad:0xFFF7F800+0x04))&0x01)==0x00)&&((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) group.long 0xDC++0x03 line.long 0x00 "DMA1CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT1 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 1" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID1 ,Buffer utilized for DMA transfer 1" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP1 ,Receive data DMA request map 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP1 ,Transmit data DMA channel 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA1 ,Receive data DMA channel enable 1" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA1 ,Transmit data DMA channel enable 1" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT1 ,Initial count of DMA transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT171 ,The 17th bit of COUNT field of DMA1COUNT register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT1 ,Actual number of remaining DMA transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xDC++0x03 hide.long 0x00 "DMA1CTRL,Mibspi DMA Channel Control Register" endif if ((((d.l(ad:0xFFF7F800+0x04))&0x01)==0x01)&&((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) group.long 0xE0++0x03 line.long 0x00 "DMA2CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT2 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 2" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID2 ,Buffer utilized for DMA transfer 2" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP2 ,Receive data DMA request map 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP2 ,Transmit data DMA channel 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA2 ,Receive data DMA channel enable 2" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA2 ,Transmit data DMA channel enable 2" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK2 ,Non-interleaved DMA block transfer 2" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT2 ,Initial count of DMA transfers 2" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT172 ,The 17th bit of COUNT field of DMA2COUNT register" "Low,High" bitfld.long 0x00 0.--5. " COUNT2 ,Actual number of remaining DMA transfer 2" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l(ad:0xFFF7F800+0x04))&0x01)==0x00)&&((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) group.long 0xE0++0x03 line.long 0x00 "DMA2CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT2 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 2" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID2 ,Buffer utilized for DMA transfer 2" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP2 ,Receive data DMA request map 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP2 ,Transmit data DMA channel 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA2 ,Receive data DMA channel enable 2" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA2 ,Transmit data DMA channel enable 2" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT2 ,Initial count of DMA transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT172 ,The 17th bit of COUNT field of DMA2COUNT register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT2 ,Actual number of remaining DMA transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xE0++0x03 hide.long 0x00 "DMA2CTRL,Mibspi DMA Channel Control Register" endif if ((((d.l(ad:0xFFF7F800+0x04))&0x01)==0x01)&&((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) group.long 0xE4++0x03 line.long 0x00 "DMA3CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT3 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 3" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID3 ,Buffer utilized for DMA transfer 3" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP3 ,Receive data DMA request map 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP3 ,Transmit data DMA channel 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA3 ,Receive data DMA channel enable 3" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA3 ,Transmit data DMA channel enable 3" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK3 ,Non-interleaved DMA block transfer 3" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT3 ,Initial count of DMA transfers 3" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT173 ,The 17th bit of COUNT field of DMA3COUNT register" "Low,High" bitfld.long 0x00 0.--5. " COUNT3 ,Actual number of remaining DMA transfer 3" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l(ad:0xFFF7F800+0x04))&0x01)==0x00)&&((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) group.long 0xE4++0x03 line.long 0x00 "DMA3CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT3 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 3" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID3 ,Buffer utilized for DMA transfer 3" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP3 ,Receive data DMA request map 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP3 ,Transmit data DMA channel 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA3 ,Receive data DMA channel enable 3" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA3 ,Transmit data DMA channel enable 3" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT3 ,Initial count of DMA transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT173 ,The 17th bit of COUNT field of DMA3COUNT register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT3 ,Actual number of remaining DMA transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xE4++0x03 hide.long 0x00 "DMA3CTRL,Mibspi DMA Channel Control Register" endif if ((((d.l(ad:0xFFF7F800+0x04))&0x01)==0x01)&&((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) group.long 0xE8++0x03 line.long 0x00 "DMA4CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT4 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 4" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID4 ,Buffer utilized for DMA transfer 4" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP4 ,Receive data DMA request map 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP4 ,Transmit data DMA channel 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA4 ,Receive data DMA channel enable 4" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA4 ,Transmit data DMA channel enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK4 ,Non-interleaved DMA block transfer 4" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT4 ,Initial count of DMA transfers 4" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT174 ,The 17th bit of COUNT field of DMA4COUNT register" "Low,High" bitfld.long 0x00 0.--5. " COUNT4 ,Actual number of remaining DMA transfer 4" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l(ad:0xFFF7F800+0x04))&0x01)==0x00)&&((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) group.long 0xE8++0x03 line.long 0x00 "DMA4CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT4 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 4" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID4 ,Buffer utilized for DMA transfer 4" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP4 ,Receive data DMA request map 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP4 ,Transmit data DMA channel 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA4 ,Receive data DMA channel enable 4" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA4 ,Transmit data DMA channel enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT4 ,Initial count of DMA transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT174 ,The 17th bit of COUNT field of DMA4COUNT register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT4 ,Actual number of remaining DMA transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xE8++0x03 hide.long 0x00 "DMA4CTRL,Mibspi DMA Channel Control Register" endif if ((((d.l(ad:0xFFF7F800+0x04))&0x01)==0x01)&&((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) group.long 0xEC++0x03 line.long 0x00 "DMA5CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT5 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 5" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID5 ,Buffer utilized for DMA transfer 5" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP5 ,Receive data DMA request map 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP5 ,Transmit data DMA channel 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA5 ,Receive data DMA channel enable 5" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA5 ,Transmit data DMA channel enable 5" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK5 ,Non-interleaved DMA block transfer 5" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT5 ,Initial count of DMA transfers 5" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT175 ,The 17th bit of COUNT field of DMA5COUNT register" "Low,High" bitfld.long 0x00 0.--5. " COUNT5 ,Actual number of remaining DMA transfer 5" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l(ad:0xFFF7F800+0x04))&0x01)==0x00)&&((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) group.long 0xEC++0x03 line.long 0x00 "DMA5CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT5 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 5" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID5 ,Buffer utilized for DMA transfer 5" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP5 ,Receive data DMA request map 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP5 ,Transmit data DMA channel 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA5 ,Receive data DMA channel enable 5" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA5 ,Transmit data DMA channel enable 5" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT5 ,Initial count of DMA transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT175 ,The 17th bit of COUNT field of DMA5COUNT register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT5 ,Actual number of remaining DMA transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xEC++0x03 hide.long 0x00 "DMA5CTRL,Mibspi DMA Channel Control Register" endif if ((((d.l(ad:0xFFF7F800+0x04))&0x01)==0x01)&&((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) group.long 0xF0++0x03 line.long 0x00 "DMA6CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT6 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 6" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID6 ,Buffer utilized for DMA transfer 6" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP6 ,Receive data DMA request map 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP6 ,Transmit data DMA channel 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA6 ,Receive data DMA channel enable 6" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA6 ,Transmit data DMA channel enable 6" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK6 ,Non-interleaved DMA block transfer 6" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT6 ,Initial count of DMA transfers 6" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT176 ,The 17th bit of COUNT field of DMA6COUNT register" "Low,High" bitfld.long 0x00 0.--5. " COUNT6 ,Actual number of remaining DMA transfer 6" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l(ad:0xFFF7F800+0x04))&0x01)==0x00)&&((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) group.long 0xF0++0x03 line.long 0x00 "DMA6CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT6 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 6" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID6 ,Buffer utilized for DMA transfer 6" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP6 ,Receive data DMA request map 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP6 ,Transmit data DMA channel 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA6 ,Receive data DMA channel enable 6" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA6 ,Transmit data DMA channel enable 6" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT6 ,Initial count of DMA transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT176 ,The 17th bit of COUNT field of DMA6COUNT register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT6 ,Actual number of remaining DMA transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xF0++0x03 hide.long 0x00 "DMA6CTRL,Mibspi DMA Channel Control Register" endif if ((((d.l(ad:0xFFF7F800+0x04))&0x01)==0x01)&&((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) group.long 0xF4++0x03 line.long 0x00 "DMA7CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT7 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 7" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID7 ,Buffer utilized for DMA transfer 7" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP7 ,Receive data DMA request map 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP7 ,Transmit data DMA channel 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA7 ,Receive data DMA channel enable 7" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA7 ,Transmit data DMA channel enable 7" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK7 ,Non-interleaved DMA block transfer 7" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT7 ,Initial count of DMA transfers 7" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT177 ,The 17th bit of COUNT field of DMA7COUNT register" "Low,High" bitfld.long 0x00 0.--5. " COUNT7 ,Actual number of remaining DMA transfer 7" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l(ad:0xFFF7F800+0x04))&0x01)==0x00)&&((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) group.long 0xF4++0x03 line.long 0x00 "DMA7CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT7 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 7" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID7 ,Buffer utilized for DMA transfer 7" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP7 ,Receive data DMA request map 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP7 ,Transmit data DMA channel 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA7 ,Receive data DMA channel enable 7" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA7 ,Transmit data DMA channel enable 7" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT7 ,Initial count of DMA transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT177 ,The 17th bit of COUNT field of DMA7COUNT register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT7 ,Actual number of remaining DMA transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xF4++0x03 hide.long 0x00 "DMA7CTRL,Mibspi DMA Channel Control Register" endif if (((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) group.long 0xF8++0x03 line.long 0x00 "DMA0COUNT,ICOUNT Register 0" hexmask.long.word 0x00 16.--31. 1. " ICOUNT0 ,Initial number of DMA transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT0 ,Actual number of remaining DMA transfer" else hgroup.long 0xF8++0x03 hide.long 0x00 "DMA0COUNT,ICOUNT Register 0" endif if (((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) group.long 0xFC++0x03 line.long 0x00 "DMA1COUNT,ICOUNT Register 1" hexmask.long.word 0x00 16.--31. 1. " ICOUNT1 ,Initial number of DMA transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT1 ,Actual number of remaining DMA transfer" else hgroup.long 0xFC++0x03 hide.long 0x00 "DMA1COUNT,ICOUNT Register 1" endif if (((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) group.long 0x100++0x03 line.long 0x00 "DMA2COUNT,ICOUNT Register 2" hexmask.long.word 0x00 16.--31. 1. " ICOUNT2 ,Initial number of DMA transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT2 ,Actual number of remaining DMA transfer" else hgroup.long 0x100++0x03 hide.long 0x00 "DMA2COUNT,ICOUNT Register 2" endif if (((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) group.long 0x104++0x03 line.long 0x00 "DMA3COUNT,ICOUNT Register 3" hexmask.long.word 0x00 16.--31. 1. " ICOUNT3 ,Initial number of DMA transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT3 ,Actual number of remaining DMA transfer" else hgroup.long 0x104++0x03 hide.long 0x00 "DMA3COUNT,ICOUNT Register 3" endif if (((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) group.long 0x108++0x03 line.long 0x00 "DMA4COUNT,ICOUNT Register 4" hexmask.long.word 0x00 16.--31. 1. " ICOUNT4 ,Initial number of DMA transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT4 ,Actual number of remaining DMA transfer" else hgroup.long 0x108++0x03 hide.long 0x00 "DMA4COUNT,ICOUNT Register 4" endif if (((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) group.long 0x10C++0x03 line.long 0x00 "DMA5COUNT,ICOUNT Register 5" hexmask.long.word 0x00 16.--31. 1. " ICOUNT5 ,Initial number of DMA transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT5 ,Actual number of remaining DMA transfer" else hgroup.long 0x10C++0x03 hide.long 0x00 "DMA5COUNT,ICOUNT Register 5" endif if (((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) group.long 0x110++0x03 line.long 0x00 "DMA6COUNT,ICOUNT Register 6" hexmask.long.word 0x00 16.--31. 1. " ICOUNT6 ,Initial number of DMA transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT6 ,Actual number of remaining DMA transfer" else hgroup.long 0x110++0x03 hide.long 0x00 "DMA6COUNT,ICOUNT Register 6" endif if (((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) group.long 0x114++0x03 line.long 0x00 "DMA7COUNT,ICOUNT Register 7" hexmask.long.word 0x00 16.--31. 1. " ICOUNT7 ,Initial number of DMA transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT7 ,Actual number of remaining DMA transfer" else hgroup.long 0x114++0x03 hide.long 0x00 "DMA7COUNT,ICOUNT Register 7" endif endif textline " " if (((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) sif (cpu()!="RM42L432") group.long 0x118++0x03 line.long 0x00 "DMACNTLEN,DMA LARGE COUNT Register" bitfld.long 0x00 0. " LARGE_COUNT ,Large count" "Modified,Not modified" endif group.long 0x120++0x03 line.long 0x00 "UERRCTRL,Uncorrectable Parity Error Control Register" sif cpuis("RM57L843-ZWT") bitfld.long 0x00 24.--27. " SBE_EVT_EN ,Single bit error event enable" ",,,,,Disabled,,,,,Enabled,?..." bitfld.long 0x00 16.--19. " EDAC_MODE ,These bits determine whether single bit errors (Sbe) detected by the SECDED block will be corrected or not" ",,,,,Disabled,,,,,Enabled,?..." textline " " endif bitfld.long 0x00 8. " PTESTEN ,Parity memory test enable" "Disabled,Enabled" bitfld.long 0x00 0.--3. " EDEN ,Error detection enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" hgroup.long 0x124++0x03 hide.long 0x00 "UERRSTAT,Uncorrectable Parity Error Status Register" in hgroup.long 0x128++0x03 hide.long 0x00 "UERRADDR1,Uncorrectable Parity Error Address Register" in hgroup.long 0x12C++0x03 hide.long 0x00 "UERRADDR0,Uncorrectable Parity Error Address Register" in hgroup.long 0x130++0x03 hide.long 0x00 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register" in else hgroup.long 0x118++0x03 hide.long 0x00 "DMACNTLEN,DMA LARGE COUNT Register" hgroup.long 0x120++0x03 hide.long 0x00 "UERRCTRL,Uncorrectable Parity Error Control Register" hgroup.long 0x124++0x03 hide.long 0x00 "UERRSTAT,Uncorrectable Parity Error Status Register" hgroup.long 0x128++0x03 hide.long 0x00 "UERRADDR1,Uncorrectable Parity Error Address Register" hgroup.long 0x12C++0x03 hide.long 0x00 "UERRADDR0,Uncorrectable Parity Error Address Register" hgroup.long 0x130++0x03 hide.long 0x00 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register" endif tree.end textline " " if ((((d.l(ad:0xFFF7F800+0x134))&0xF00)==0xA00)&&(((d.l(ad:0xFFF7F800+0x134))&0x02)==0x02)) group.long 0x134++0x03 line.long 0x00 "IOLPBKTSTCR,Spi/mibspi IO Loopback Test Control Register" bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" eventfld.long 0x00 24. " SCS_FAIL_FLG ,Analog loopback /SPISCS pin compare failure" "Not failed,Failed" textline " " bitfld.long 0x00 20. " CTRL_BITERR ,Inducing of BITERR during IO loopback test mode control" "Not affected,Flipped" bitfld.long 0x00 19. " CTRL_DESYNC ,Inducing of DESYNC error during IO loopback test mode control" "Not affected,Forced to 0" textline " " bitfld.long 0x00 18. " CTRL_PARERR ,Inducing of parity error during IO loopback test mode control" "Not affected,Flipped" bitfld.long 0x00 17. " CTRL_TIMEOUT ,Inducing of TIMEOUT error during IO loopback test mode control" "Not affected,Forced to 1" textline " " bitfld.long 0x00 16. " CTRL_DLENERR ,Inducing of data length error during IO loopback test mode control" "Not affected,Forced to 1" bitfld.long 0x00 3.--5. " ERR_SCS_PIN ,Error on chip select pin injection" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]" textline " " bitfld.long 0x00 2. " CTRL_SCS_PIN_ERR ,/SPISCS[7:0] pins error injection enable control" "Disabled,Enabled" bitfld.long 0x00 1. " LPBK_TYPE ,Module IO loopback type" "Digital,Analog" textline " " bitfld.long 0x00 0. " RXP_ENA ,Module analog loopback through receive pin enable" "Transmit,Receive" elif ((((d.l(ad:0xFFF7F800+0x134))&0xF00)==0xA00)&&(((d.l(ad:0xFFF7F800+0x134))&0x02)==0x00)) group.long 0x134++0x03 line.long 0x00 "IOLPBKTSTCR,Spi/mibspi IO Loopback Test Control Register" bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" eventfld.long 0x00 24. " SCS_FAIL_FLG ,Analog loopback /SPISCS pin compare failure" "Not failed,Failed" textline " " bitfld.long 0x00 20. " CTRL_BITERR ,Inducing of BITERR during IO loopback test mode control" "Not affected,Flipped" bitfld.long 0x00 19. " CTRL_DESYNC ,Inducing of DESYNC error during IO loopback test mode control" "Not affected,Forced to 0" textline " " bitfld.long 0x00 18. " CTRL_PARERR ,Inducing of parity error during IO loopback test mode control" "Not affected,Flipped" bitfld.long 0x00 17. " CTRL_TIMEOUT ,Inducing of TIMEOUT error during IO loopback test mode control" "Not affected,Forced to 1" textline " " bitfld.long 0x00 16. " CTRL_DLENERR ,Inducing of data length error during IO loopback test mode control" "Not affected,Forced to 1" bitfld.long 0x00 3.--5. " ERR_SCS_PIN ,Error on chip select pin injection" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]" textline " " bitfld.long 0x00 2. " CTRL_SCS_PIN_ERR ,/SPISCS[7:0] pins error injection enable control" "Disabled,Enabled" bitfld.long 0x00 1. " LPBK_TYPE ,Module IO loopback type" "Digital,Analog" else group.long 0x134++0x03 line.long 0x00 "IOLPBKTSTCR,Spi/mibspi IO Loopback Test Control Register" bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" endif sif (cpuis("RM46L*")||cpu()=="RM42L432"||cpuis("RM57L843-ZWT")) group.long 0x138++0x07 line.long 0x00 "EXTENDED_PRESCALE1,SPI Extended Prescale Register 1" hexmask.long.word 0x00 16.--26. 1. " EPRESCALE_FMT1 ,Extended prescale value for SPIFMT1" hexmask.long.word 0x00 0.--10. 1. " EPRESCALE_FMT0 ,Extended prescale value for SPIFMT0" line.long 0x04 "EXTENDED_PRESCALE2,SPI Extended Prescale Register 2" hexmask.long.word 0x04 16.--26. 1. " EPRESCALE_FMT3 ,Extended prescale value for SPIFMT1" hexmask.long.word 0x04 0.--10. 1. " EPRESCALE_FMT2 ,Extended prescale value for SPIFMT0" endif sif cpuis("RM57L843-ZWT") group.long 0x140++0x07 line.long 0x00 "ECCDIAG_CTRL,ECC Diagnostic Control Register" bitfld.long 0x00 0.--3. " ECCDIAG_EN ,ECC diagnostic mode enable key bits" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" line.long 0x04 "ECCDIAG_STAT,ECC Diagnostic Status Register" eventfld.long 0x04 17. " DEFLG[1] ,Double bit error flag" "No error,Error" eventfld.long 0x04 16. " DEFLG[0] ,Double bit error flag" "No error,Error" textline " " eventfld.long 0x04 1. " SEFLG[1] ,Single bit error flag" "No error,Error" eventfld.long 0x04 0. " SEFLG[0] ,Single bit error flag" "No error,Error" hgroup.long 0x148++0x07 hide.long 0x00 "SBERRADDR1,Single Bit Error Address Register - RXRAM" in hide.long 0x04 "SBERRADDR0,Single Bit Error Address Register - TXRAM" endif width 0x0B tree.end else tree "MIBSPI3" base ad:0xFFF7F800 width 6. group.long 0x00++0x03 line.long 0x00 "GCR0,Global Control Register 0" bitfld.long 0x00 0. " NRESET ,This is the reset bit for the module" "Reset,No reset" if (((d.l(ad:0xFFF7F800+0x04))&0x03)==0x03) group.long 0x04++0x03 line.long 0x00 "GCR1,Global Control Register 1" bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI pin direction determination" "Input/output,Output/input" bitfld.long 0x00 24. " SPIEN ,SPI enable" "Not active,Active" bitfld.long 0x00 16. " LOOP_BACK ,Internal Loop-back test mode" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " POWERDOWN ,SPI state machines power down state enable" "Active,Power down" bitfld.long 0x00 1. " CLKMOD ,Clock mode" "External,Internal" elif (((d.l(ad:0xFFF7F800+0x04))&0x03)==0x02) group.long 0x04++0x03 line.long 0x00 "GCR1,Global Control Register 1" bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI pin direction determination" "Input/output,Output/input" bitfld.long 0x00 24. " SPIEN ,SPI enable" "Not active,Active" bitfld.long 0x00 8. " POWERDOWN ,SPI state machines power down state enable" "Active,Power down" textline " " bitfld.long 0x00 1. " CLKMOD ,Clock mode" "External,Internal" elif (((d.l(ad:0xFFF7F800+0x04))&0x03)==0x01) group.long 0x04++0x03 line.long 0x00 "GCR1,Global Control Register 1" bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI pin direction determination" "Input/output,Output/input" bitfld.long 0x00 24. " SPIEN ,SPI enable" "Not active,Active" bitfld.long 0x00 8. " POWERDOWN ,SPI state machines power down state enable" "Active,Power down" textline " " bitfld.long 0x00 1. " CLKMOD ,Clock mode" "External,Internal" else group.long 0x04++0x03 line.long 0x00 "GCR1,Global Control Register 1" bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI pin direction determination" "Input/output,Output/input" bitfld.long 0x00 24. " SPIEN ,SPI enable" "Not active,Active" bitfld.long 0x00 8. " POWERDOWN ,SPI state machines power down state enable" "Active,Power down" textline " " bitfld.long 0x00 1. " CLKMOD ,Clock mode" "External,Internal" endif if (((d.l(ad:0xFFF7F800+0x04))&0x01)==0x01) group.long 0x08++0x03 line.long 0x00 "INT0,Interrupt Register" bitfld.long 0x00 24. " ENABLE_HIGHZ ,/SPIENA pin High-z enable" "Disabled,Enabled" textline " " sif (cpu()!="RM42L432") bitfld.long 0x00 16. " DMA_REQ_EN ,DMA request enable" "Not used,Generated" endif textline " " bitfld.long 0x00 9. " TXINTENA ,Transmit interrupt enable" "Not generated,Generated" bitfld.long 0x00 8. " RXINTENA ,Receive interrupt enable" "Not generated,Generated" textline " " bitfld.long 0x00 6. " RXOVRNINTENA ,Overrun interrupt enable" "Not generated,Generated" bitfld.long 0x00 4. " BITERRENA ,Enables interrupt on bit error" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " DESYNCENA ,Enables interrupt on De-synchronized slave" "Disabled,Enabled" bitfld.long 0x00 2. " PARERRENA ,Enables interrupt on parity error" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " TIMEOUTENA ,Enables interrupt on ENA signal Time-out" "Disabled,Enabled" bitfld.long 0x00 0. " DLEN_ERR_ENA ,Data length error interrupt enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "INT0,Interrupt Register" bitfld.long 0x00 24. " ENABLE_HIGHZ ,/SPIENA pin High-z enable" "Disabled,Enabled" textline " " sif (cpu()!="RM42L432") bitfld.long 0x00 16. " DMA_REQ_EN ,DMA request enable" "Not used,Generated" endif textline " " bitfld.long 0x00 9. " TXINTENA ,Transmit interrupt enable" "Not generated,Generated" bitfld.long 0x00 8. " RXINTENA ,Receive interrupt enable" "Not generated,Generated" textline " " bitfld.long 0x00 6. " RXOVRNINTENA ,Overrun interrupt enable" "Not generated,Generated" bitfld.long 0x00 4. " BITERRENA ,Enables interrupt on bit error" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " PARERRENA ,Enables interrupt on parity error" "Disabled,Enabled" bitfld.long 0x00 1. " TIMEOUTENA ,Enables interrupt on ENA signal Time-out" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " DLEN_ERR_ENA ,Data length error interrupt enable" "Disabled,Enabled" endif if (((d.l(ad:0xFFF7F800+0x04))&0x01)==0x01) group.long 0x0C++0x03 line.long 0x00 "LVL,Interrupt Level Register" bitfld.long 0x00 9. " TXINTLVL ,Transmit interrupt level" "INT0,INT1" bitfld.long 0x00 8. " RXINTLVL ,Receive interrupt level" "INT0,INT1" bitfld.long 0x00 6. " RXOVRNINTLVL ,Receive overrun interrupt level" "INT0,INT1" textline " " bitfld.long 0x00 4. " BITERRLVL ,Bit error interrupt level" "INT0,INT1" bitfld.long 0x00 3. " DESYNCLVL ,De-synchronized slave interrupt level" "INT0,INT1" bitfld.long 0x00 2. " PARERRLVL ,Parity error interrupt level" "INT0,INT1" textline " " bitfld.long 0x00 1. " TIMEOUTLVL ,/SPIENA pin Time-out interrupt level" "INT0,INT1" bitfld.long 0x00 0. " DLEN_ERR_LVL ,Data length error interrupt enable level" "INT0,INT1" else group.long 0x0C++0x03 line.long 0x00 "LVL,Interrupt Level Register" bitfld.long 0x00 9. " TXINTLVL ,Transmit interrupt level" "INT0,INT1" bitfld.long 0x00 8. " RXINTLVL ,Receive interrupt level" "INT0,INT1" bitfld.long 0x00 6. " RXOVRNINTLVL ,Receive overrun interrupt level" "INT0,INT1" textline " " bitfld.long 0x00 4. " BITERRLVL ,Bit error interrupt level" "INT0,INT1" bitfld.long 0x00 2. " PARERRLVL ,Parity error interrupt level" "INT0,INT1" bitfld.long 0x00 1. " TIMEOUTLVL ,/SPIENA pin Time-out interrupt level" "INT0,INT1" textline " " bitfld.long 0x00 0. " DLEN_ERR_LVL ,Data length error interrupt enable level" "INT0,INT1" endif if (((d.l(ad:0xFFF7F800+0x04))&0x01)==0x01) group.long 0x10++0x03 line.long 0x00 "FLG,Flag Register" bitfld.long 0x00 24. " BUF_INIT_ACTIVE ,Multibuffer initialization active" "Finished,Not finished" bitfld.long 0x00 9. " TXINTFLG ,Transmitter empty interrupt flag" "Full,Empty" textline " " eventfld.long 0x00 8. " RXINTFLG ,Receiver full interrupt flag" "Empty,Full" eventfld.long 0x00 6. " RXOVRNINTFLG ,Receiver overrun flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 4. " BITERRFLG ,Internal transmit data and transmitted data mismatch" "Not occurred,Occurred" eventfld.long 0x00 3. " DESYNCFLG ,Slave device De-Synchronization" "Not detected,Detected" textline " " eventfld.long 0x00 2. " PARITYERRFLG ,Parity error flag" "Not detected,Detected" eventfld.long 0x00 1. " TIMEOUTFLG ,Time-out due to Non-activation of ENA signal" "Not occurred,Occurred" textline " " eventfld.long 0x00 0. " DLEN_ERR_FLG ,Data length error flag" "Not occurred,Occurred" else group.long 0x10++0x03 line.long 0x00 "FLG,Flag Register" bitfld.long 0x00 24. " BUF_INIT_ACTIVE ,Multibuffer initialization active" "Not completed,Completed" bitfld.long 0x00 9. " TXINTFLG ,Transmitter empty interrupt flag" "No empty,Empty" textline " " eventfld.long 0x00 8. " RXINTFLG ,Receiver full interrupt flag" "No full,Full" eventfld.long 0x00 6. " RXOVRNINTFLG ,Receiver overrun flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 4. " BITERRFLG ,Internal transmit data and transmitted data mismatch" "Not occurred,Occurred" eventfld.long 0x00 2. " PARITYERRFLG ,Parity error flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 1. " TIMEOUTFLG ,Time-out due to Non-activation of ENA signal" "Not occurred,Occurred" eventfld.long 0x00 0. " DLEN_ERR_FLG ,Data length error flag" "Not occurred,Occurred" endif width 13. tree "SPI Pin Control Registers" tree "SPI Pin Control Registers 0-5" group.long 0x14++0x03 line.long 0x00 "PC0,Pin Control Register 0" bitfld.long 0x00 31. " SOMIFUN7 ,Slave out master in function 7" "GPIO,Spi/mibspi" bitfld.long 0x00 30. " SOMIFUN6 ,Slave out master in function 6" "GPIO,Spi/mibspi" bitfld.long 0x00 29. " SOMIFUN5 ,Slave out master in function 5" "GPIO,Spi/mibspi" textline " " bitfld.long 0x00 28. " SOMIFUN4 ,Slave out master in function 4" "GPIO,Spi/mibspi" bitfld.long 0x00 27. " SOMIFUN3 ,Slave out master in function 3" "GPIO,Spi/mibspi" bitfld.long 0x00 26. " SOMIFUN2 ,Slave out master in function 2" "GPIO,Spi/mibspi" textline " " bitfld.long 0x00 25. " SOMIFUN1 ,Slave out master in function 1" "GPIO,Spi/mibspi" bitfld.long 0x00 24. " SOMIFUN0 ,Slave out master in function 0" "GPIO,Spi/mibspi" bitfld.long 0x00 23. " SIMOFUN7 ,Slave in master out function 7" "GPIO,Spi/mibspi" textline " " bitfld.long 0x00 22. " SIMOFUN6 ,Slave in master out function 6" "GPIO,Spi/mibspi" bitfld.long 0x00 21. " SIMOFUN5 ,Slave in master out function 5" "GPIO,Spi/mibspi" bitfld.long 0x00 20. " SIMOFUN4 ,Slave in master out function 4" "GPIO,Spi/mibspi" textline " " bitfld.long 0x00 19. " SIMOFUN3 ,Slave in master out function 3" "GPIO,Spi/mibspi" bitfld.long 0x00 18. " SIMOFUN2 ,Slave in master out function 2" "GPIO,Spi/mibspi" bitfld.long 0x00 17. " SIMOFUN1 ,Slave in master out function 1" "GPIO,Spi/mibspi" textline " " bitfld.long 0x00 16. " SIMOFUN0 ,Slave in master out function 0" "GPIO,Spi/mibspi" bitfld.long 0x00 11. " SOMIFUN0 ,Slave out master in function" "GPIO,Spi/mibspi" bitfld.long 0x00 10. " SIMOFUN0 ,Slave in master out function" "GPIO,Spi/mibspi" textline " " bitfld.long 0x00 9. " CLKFUN ,Spi/mibspi clock function" "GPIO,Spi/mibspi" bitfld.long 0x00 8. " ENAFUN ,/SPIENA function" "GPIO,Spi/mibspi" bitfld.long 0x00 7. " SCSFUN7 ,/SPISCS7 function" "GPIO,SPI" textline " " bitfld.long 0x00 6. " SCSFUN6 ,/SPISCS6 function" "GPIO,SPI" bitfld.long 0x00 5. " SCSFUN5 ,/SPISCS5 function" "GPIO,SPI" bitfld.long 0x00 4. " SCSFUN4 ,/SPISCS4 function" "GPIO,SPI" textline " " bitfld.long 0x00 3. " SCSFUN3 ,/SPISCS3 function" "GPIO,SPI" bitfld.long 0x00 2. " SCSFUN2 ,/SPISCS2 function" "GPIO,SPI" bitfld.long 0x00 1. " SCSFUN1 ,/SPISCS1 function" "GPIO,SPI" textline " " bitfld.long 0x00 0. " SCSFUN0 ,/SPISCS0 function" "GPIO,SPI" group.long 0x18++0x03 line.long 0x00 "PC1,Pin Control Register 1" bitfld.long 0x00 31. " SOMIDIR7 ,SPISOMI7 direction" "Input,Output" bitfld.long 0x00 30. " SOMIDIR6 ,SPISOMI6 direction" "Input,Output" bitfld.long 0x00 29. " SOMIDIR5 ,SPISOMI5 direction" "Input,Output" textline " " bitfld.long 0x00 28. " SOMIDIR4 ,SPISOMI4 direction" "Input,Output" bitfld.long 0x00 27. " SOMIDIR3 ,SPISOMI3 direction" "Input,Output" bitfld.long 0x00 26. " SOMIDIR2 ,SPISOMI2 direction" "Input,Output" textline " " bitfld.long 0x00 25. " SOMIDIR1 ,SPISOMI1 direction" "Input,Output" bitfld.long 0x00 24. " SOMIDIR0 ,SPISOMI0 direction" "Input,Output" bitfld.long 0x00 23. " SIMODIR7 ,SPISIMO7 direction" "Input,Output" textline " " bitfld.long 0x00 22. " SIMODIR6 ,SPISIMO6 direction" "Input,Output" bitfld.long 0x00 21. " SIMODIR5 ,SPISIMO5 direction" "Input,Output" bitfld.long 0x00 20. " SIMODIR4 ,SPISIMO4 direction" "Input,Output" textline " " bitfld.long 0x00 19. " SIMODIR3 ,SPISIMO3 direction" "Input,Output" bitfld.long 0x00 18. " SIMODIR2 ,SPISIMO2 direction" "Input,Output" bitfld.long 0x00 17. " SIMODIR1 ,SPISIMO1 direction" "Input,Output" textline " " bitfld.long 0x00 16. " SIMODIR0 ,SPISIMO0 direction" "Input,Output" bitfld.long 0x00 11. " SOMIDIR0 ,SPISOMI0 direction" "Input,Output" bitfld.long 0x00 10. " SIMODIR0 ,SPISIMO0 direction" "Input,Output" textline " " bitfld.long 0x00 9. " CLKDIR ,SPICLK direction" "Input,Output" bitfld.long 0x00 8. " ENADIR ,/SPIENA direction" "Input,Output" bitfld.long 0x00 7. " SCSDIR7 ,/SPISCS7 direction" "Input,Output" textline " " bitfld.long 0x00 6. " SCSDIR6 ,/SPISCS6 direction" "Input,Output" bitfld.long 0x00 5. " SCSDIR5 ,/SPISCS5 direction" "Input,Output" bitfld.long 0x00 4. " SCSDIR4 ,/SPISCS4 direction" "Input,Output" textline " " bitfld.long 0x00 3. " SCSDIR3 ,/SPISCS3 direction" "Input,Output" bitfld.long 0x00 2. " SCSDIR2 ,/SPISCS2 direction" "Input,Output" bitfld.long 0x00 1. " SCSDIR1 ,/SPISCS1 direction" "Input,Output" textline " " bitfld.long 0x00 0. " SCSDIR0 ,/SPISCS0 direction" "Input,Output" rgroup.long 0x1C++0x03 line.long 0x00 "PC2,Pin Control Register 2" bitfld.long 0x00 31. " SOMIDIN7 ,SPISOMI7 data in" "Low,High" bitfld.long 0x00 30. " SOMIDIN6 ,SPISOMI6 data in" "Low,High" bitfld.long 0x00 29. " SOMIDIN5 ,SPISOMI5 data in" "Low,High" textline " " bitfld.long 0x00 28. " SOMIDIN4 ,SPISOMI4 data in" "Low,High" bitfld.long 0x00 27. " SOMIDIN3 ,SPISOMI3 data in" "Low,High" bitfld.long 0x00 26. " SOMIDIN2 ,SPISOMI2 data in" "Low,High" textline " " bitfld.long 0x00 25. " SOMIDIN1 ,SPISOMI1 data in" "Low,High" bitfld.long 0x00 24. " SOMIDIN0 ,SPISOMI0 data in" "Low,High" bitfld.long 0x00 23. " SIMODIN7 ,SPISIMO7 data in" "Low,High" textline " " bitfld.long 0x00 22. " SIMODIN6 ,SPISIMO6 data in" "Low,High" bitfld.long 0x00 21. " SIMODIN5 ,SPISIMO5 data in" "Low,High" bitfld.long 0x00 20. " SIMODIN4 ,SPISIMO4 data in" "Low,High" textline " " bitfld.long 0x00 19. " SIMODIN3 ,SPISIMO3 data in" "Low,High" bitfld.long 0x00 18. " SIMODIN2 ,SPISIMO2 data in" "Low,High" bitfld.long 0x00 17. " SIMODIN1 ,SPISIMO1 data in" "Low,High" textline " " bitfld.long 0x00 16. " SIMODIN0 ,SPISIMO0 data in" "Low,High" bitfld.long 0x00 11. " SOMIDIN0 ,SPISOMI0 data in" "Low,High" bitfld.long 0x00 10. " SIMODIN0 ,SPISIMO0 data in" "Low,High" textline " " bitfld.long 0x00 9. " CLKDIN ,Clock data in" "Low,High" bitfld.long 0x00 8. " ENADIN ,/SPIENA data in" "Low,High" bitfld.long 0x00 7. " SCSDIN7 ,SPISCS7 data in" "Low,High" textline " " bitfld.long 0x00 6. " SCSDIN6 ,SPISCS6 data in" "Low,High" bitfld.long 0x00 5. " SCSDIN5 ,SPISCS5 data in" "Low,High" bitfld.long 0x00 4. " SCSDIN4 ,SPISCS4 data in" "Low,High" textline " " bitfld.long 0x00 3. " SCSDIN3 ,SPISCS3 data in" "Low,High" bitfld.long 0x00 2. " SCSDIN2 ,SPISCS2 data in" "Low,High" bitfld.long 0x00 1. " SCSDIN1 ,SPISCS1 data in" "Low,High" textline " " bitfld.long 0x00 0. " SCSDIN0 ,SPISCS0 data in" "Low,High" group.long 0x20++0x0B line.long 0x00 "PC3,Pin Control Register 3" bitfld.long 0x00 31. " SOMIDOUT7 ,SPISOMI7 dataout write" "Low,High" bitfld.long 0x00 30. " SOMIDOUT6 ,SPISOMI6 dataout write" "Low,High" textline " " bitfld.long 0x00 29. " SOMIDOUT5 ,SPISOMI5 dataout write" "Low,High" bitfld.long 0x00 28. " SOMIDOUT4 ,SPISOMI4 dataout write" "Low,High" textline " " bitfld.long 0x00 27. " SOMIDOUT3 ,SPISOMI3 dataout write" "Low,High" bitfld.long 0x00 26. " SOMIDOUT2 ,SPISOMI2 dataout write" "Low,High" textline " " bitfld.long 0x00 25. " SOMIDOUT1 ,SPISOMI1 dataout write" "Low,High" bitfld.long 0x00 24. " SOMIDOUT0 ,SPISOMI0 dataout write" "Low,High" textline " " bitfld.long 0x00 23. " SIMODOUT7 ,SPISIMO7 dataout write" "Low,High" bitfld.long 0x00 22. " SIMODOUT6 ,SPISIMO6 dataout write" "Low,High" textline " " bitfld.long 0x00 21. " SIMODOUT5 ,SPISIMO5 dataout write" "Low,High" bitfld.long 0x00 20. " SIMODOUT4 ,SPISIMO4 dataout write" "Low,High" textline " " bitfld.long 0x00 19. " SIMODOUT3 ,SPISIMO3 dataout write" "Low,High" bitfld.long 0x00 18. " SIMODOUT2 ,SPISIMO2 dataout write" "Low,High" textline " " bitfld.long 0x00 17. " SIMODOUT1 ,SPISIMO1 dataout write" "Low,High" bitfld.long 0x00 16. " SIMODOUT0 ,SPISIMO0 dataout write" "Low,High" textline " " bitfld.long 0x00 11. " SOMIDOUT0 ,SPISOMI0 dataout write" "Low,High" bitfld.long 0x00 10. " SIMODOUT0 ,SPISIMO0 dataout write" "Low,High" textline " " bitfld.long 0x00 9. " CLKDOUT ,SPICLK dataout write" "Low,High" bitfld.long 0x00 8. " ENADOUT ,/SPIENA dataout write" "Low,High" textline " " bitfld.long 0x00 7. " SCSDOUT7 ,SPISCS7 dataout write" "Low,High" bitfld.long 0x00 6. " SCSDOUT6 ,SPISCS6 dataout write" "Low,High" textline " " bitfld.long 0x00 5. " SCSDOUT5 ,SPISCS5 dataout write" "Low,High" bitfld.long 0x00 4. " SCSDOUT4 ,SPISCS4 dataout write" "Low,High" textline " " bitfld.long 0x00 3. " SCSDOUT3 ,SPISCS3 dataout write" "Low,High" bitfld.long 0x00 2. " SCSDOUT2 ,SPISCS2 dataout write" "Low,High" textline " " bitfld.long 0x00 1. " SCSDOUT1 ,SPISCS1 dataout write" "Low,High" bitfld.long 0x00 0. " SCSDOUT0 ,SPISCS0 dataout write" "Low,High" line.long 0x04 "PC4,Pin Control Register 4" bitfld.long 0x04 31. " SOMISET7 ,SPISOMI7 dataout set" "Not set,Set" bitfld.long 0x04 30. " SOMISET6 ,SPISOMI6 dataout set" "Not set,Set" textline " " bitfld.long 0x04 29. " SOMISET5 ,SPISOMI5 dataout set" "Not set,Set" bitfld.long 0x04 28. " SOMISET4 ,SPISOMI4 dataout set" "Not set,Set" textline " " bitfld.long 0x04 27. " SOMISET3 ,SPISOMI3 dataout set" "Not set,Set" bitfld.long 0x04 26. " SOMISET2 ,SPISOMI2 dataout set" "Not set,Set" textline " " bitfld.long 0x04 25. " SOMISET1 ,SPISOMI1 dataout set" "Not set,Set" bitfld.long 0x04 24. " SOMISET0 ,SPISOMI0 dataout set" "Not set,Set" textline " " bitfld.long 0x04 23. " SIMOSET7 ,SPISIMO7 dataout set" "Not set,Set" bitfld.long 0x04 22. " SIMOSET6 ,SPISIMO6 dataout set" "Not set,Set" textline " " bitfld.long 0x04 21. " SIMOSET5 ,SPISIMO5 dataout set" "Not set,Set" bitfld.long 0x04 20. " SIMOSET4 ,SPISIMO4 dataout set" "Not set,Set" textline " " bitfld.long 0x04 19. " SIMOSET3 ,SPISIMO3 dataout set" "Not set,Set" bitfld.long 0x04 18. " SIMOSET2 ,SPISIMO2 dataout set" "Not set,Set" textline " " bitfld.long 0x04 17. " SIMOSET1 ,SPISIMO1 dataout set" "Not set,Set" bitfld.long 0x04 16. " SIMOSET0 ,SPISIMO0 dataout set" "Not set,Set" textline " " bitfld.long 0x04 11. " SOMISET0 ,SPISOMI0 dataout set" "Not set,Set" bitfld.long 0x04 10. " SIMOSET0 ,SPISIMO0 dataout set" "Not set,Set" textline " " bitfld.long 0x04 9. " CLKSET ,SPICLK dataout set" "Not set,Set" bitfld.long 0x04 8. " ENASET ,/SPIENA dataout set" "Not set,Set" textline " " bitfld.long 0x04 7. " SCSSET7 ,SPISCS7 dataout set" "Not set,Set" bitfld.long 0x04 6. " SCSSET6 ,SPISCS6 dataout set" "Not set,Set" textline " " bitfld.long 0x04 5. " SCSSET5 ,SPISCS5 dataout set" "Not set,Set" bitfld.long 0x04 4. " SCSSET4 ,SPISCS4 dataout set" "Not set,Set" textline " " bitfld.long 0x04 3. " SCSSET3 ,SPISCS3 dataout set" "Not set,Set" bitfld.long 0x04 2. " SCSSET2 ,SPISCS2 dataout set" "Not set,Set" textline " " bitfld.long 0x04 1. " SCSSET1 ,SPISCS1 dataout set" "Not set,Set" bitfld.long 0x04 0. " SCSSET0 ,SPISCS0 dataout set" "Not set,Set" line.long 0x08 "PC5,Pin Control Register 5" bitfld.long 0x08 31. " SOMICLR7 ,SPISOMI7 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 30. " SOMICLR6 ,SPISOMI6 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 29. " SOMICLR5 ,SPISOMI5 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 28. " SOMICLR4 ,SPISOMI4 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 27. " SOMICLR3 ,SPISOMI3 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 26. " SOMICLR2 ,SPISOMI2 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 25. " SOMICLR1 ,SPISOMI1 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 24. " SOMICLR0 ,SPISOMI0 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 23. " SIMOCLR7 ,SPISIMO7 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 22. " SIMOCLR6 ,SPISIMO6 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 21. " SIMOCLR5 ,SPISIMO5 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 20. " SIMOCLR4 ,SPISIMO4 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 19. " SIMOCLR3 ,SPISIMO3 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 18. " SIMOCLR2 ,SPISIMO2 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 17. " SIMOCLR1 ,SPISIMO1 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 16. " SIMOCLR0 ,SPISIMO0 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 11. " SOMICLR0 ,SPISOMI0 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 10. " SIMOCLR0 ,SPISIMO0 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 9. " CLKCLR ,SPICLK dataout clear" "Not cleared,Cleared" bitfld.long 0x08 8. " ENACLR ,/SPIENA dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 7. " SCSCLR7 ,SPISCS7 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 6. " SCSCLR6 ,SPISCS6 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 5. " SCSCLR5 ,SPISCS5 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 4. " SCSCLR4 ,SPISCS4 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 3. " SCSCLR3 ,SPISCS3 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 2. " SCSCLR2 ,SPISCS2 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 1. " SCSCLR1 ,SPISCS1 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 0. " SCSCLR0 ,SPISCS0 dataout clear" "Not cleared,Cleared" tree.end tree "SPI Pin Control Registers 6-8" group.long 0x2C++0x03 line.long 0x00 "PC6,Pin Control Register 1" bitfld.long 0x00 31. " SOMIPDR7 ,SPISOMI7 open drain enable" "High,Tri-stated" bitfld.long 0x00 30. " SOMIPDR6 ,SPISOMI6 open drain enable" "High,Tri-stated" bitfld.long 0x00 29. " SOMIPDR5 ,SPISOMI5 open drain enable" "High,Tri-stated" textline " " bitfld.long 0x00 28. " SOMIPDR4 ,SPISOMI4 open drain enable" "High,Tri-stated" bitfld.long 0x00 27. " SOMIPDR3 ,SPISOMI3 open drain enable" "High,Tri-stated" bitfld.long 0x00 26. " SOMIPDR2 ,SPISOMI2 open drain enable" "High,Tri-stated" textline " " bitfld.long 0x00 25. " SOMIPDR1 ,SPISOMI1 open drain enable" "High,Tri-stated" bitfld.long 0x00 24. " SOMIPDR0 ,SPISOMI0 open drain enable" "High,Tri-stated" bitfld.long 0x00 23. " SIMOPDR7 ,SPISIMO7 open drain enable" "High,Tri-stated" textline " " bitfld.long 0x00 22. " SIMOPDR6 ,SPISIMO6 open drain enable" "High,Tri-stated" bitfld.long 0x00 21. " SIMOPDR5 ,SPISIMO5 open drain enable" "High,Tri-stated" bitfld.long 0x00 20. " SIMOPDR4 ,SPISIMO4 open drain enable" "High,Tri-stated" textline " " bitfld.long 0x00 19. " SIMOPDR3 ,SPISIMO3 open drain enable" "High,Tri-stated" bitfld.long 0x00 18. " SIMOPDR2 ,SPISIMO2 open drain enable" "High,Tri-stated" bitfld.long 0x00 17. " SIMOPDR1 ,SPISIMO1 open drain enable" "High,Tri-stated" textline " " bitfld.long 0x00 16. " SIMOPDR0 ,SPISIMO0 open drain enable" "High,Tri-stated" bitfld.long 0x00 11. " SOMIPDR0 ,SPISOMI0 open drain enable" "High,Tri-stated" bitfld.long 0x00 10. " SIMOPDR0 ,SPISIMO0 open drain enable" "High,Tri-stated" textline " " bitfld.long 0x00 9. " CLKPDR ,SPICLK open drain enable" "High,Tri-stated" bitfld.long 0x00 8. " ENAPDR ,/SPIENA open drain enable" "High,Tri-stated" bitfld.long 0x00 7. " SCSPDR7 ,/SPISCS7 open drain" "High,Tri-stated" textline " " bitfld.long 0x00 6. " SCSPDR6 ,/SPISCS6 open drain" "High,Tri-stated" bitfld.long 0x00 5. " SCSPDR5 ,/SPISCS5 open drain" "High,Tri-stated" bitfld.long 0x00 4. " SCSPDR4 ,/SPISCS4 open drain" "High,Tri-stated" textline " " bitfld.long 0x00 3. " SCSPDR3 ,/SPISCS3 open drain" "High,Tri-stated" bitfld.long 0x00 2. " SCSPDR2 ,/SPISCS2 open drain" "High,Tri-stated" bitfld.long 0x00 1. " SCSPDR1 ,/SPISCS1 open drain" "High,Tri-stated" textline " " bitfld.long 0x00 0. " SCSPDR0 ,/SPISCS0 open drain" "High,Tri-stated" group.long 0x30++0x03 line.long 0x00 "PC7,Pin Control Register 7" bitfld.long 0x00 31. " SOMIPDIS7 ,SPISOMI7 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 30. " SOMIPDIS6 ,SPISOMI6 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 29. " SOMIPDIS5 ,SPISOMI5 pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 28. " SOMIPDIS4 ,SPISOMI4 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 27. " SOMIPDIS3 ,SPISOMI3 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 26. " SOMIPDIS2 ,SPISOMI2 pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 25. " SOMIPDIS1 ,SPISOMI1 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 24. " SOMIPDIS0 ,SPISOMI0 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 23. " SIMOPDIS7 ,SPISIMO7 pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 22. " SIMOPDIS6 ,SPISIMO6 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 21. " SIMOPDIS5 ,SPISIMO5 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 20. " SIMOPDIS4 ,SPISIMO4 pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 19. " SIMOPDIS3 ,SPISIMO3 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 18. " SIMOPDIS2 ,SPISIMO2 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 17. " SIMOPDIS1 ,SPISIMO1 pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 16. " SIMOPDIS0 ,SPISIMO0 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 11. " SOMIPDIS0 ,SPISOMI0 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 10. " SIMOPDIS0 ,SPISIMO pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 9. " CLKPDIS ,SPICLK pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 8. " ENAPDIS ,SPIENA pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 7. " SCSPDIS7 ,SPISCS7 pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 6. " SCSPDIS6 ,SPISCS6 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 5. " SCSPDIS5 ,SPISCS5 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 4. " SCSPDIS4 ,SPISCS4 pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 3. " SCSPDIS3 ,SPISCS3 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 2. " SCSPDIS2 ,SPISCS2 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 1. " SCSPDIS1 ,SPISCS1 pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 0. " SCSPDIS0 ,SPISCS0 pull control enable/disable" "Enabled,Disabled" group.long 0x34++0x03 line.long 0x00 "PC8,Pin Control Register 8" bitfld.long 0x00 31. " SOMIPSEL7 ,SPISOMI7 pull select" "Pull down,Pull up" bitfld.long 0x00 30. " SOMIPSEL6 ,SPISOMI6 pull select" "Pull down,Pull up" bitfld.long 0x00 29. " SOMIPSEL5 ,SPISOMI5 pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 28. " SOMIPSEL4 ,SPISOMI4 pull select" "Pull down,Pull up" bitfld.long 0x00 27. " SOMIPSEL3 ,SPISOMI3 pull select" "Pull down,Pull up" bitfld.long 0x00 26. " SOMIPSEL2 ,SPISOMI2 pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 25. " SOMIPSEL1 ,SPISOMI1 pull select" "Pull down,Pull up" bitfld.long 0x00 24. " SOMIPSEL0 ,SPISOMI0 pull select" "Pull down,Pull up" bitfld.long 0x00 23. " SIMOPSEL7 ,SPISIMO7 pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 22. " SIMOPSEL6 ,SPISIMO6 pull select" "Pull down,Pull up" bitfld.long 0x00 21. " SIMOPSEL5 ,SPISIMO5 pull select" "Pull down,Pull up" bitfld.long 0x00 20. " SIMOPSEL4 ,SPISIMO4 pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 19. " SIMOPSEL3 ,SPISIMO3 pull select" "Pull down,Pull up" bitfld.long 0x00 18. " SIMOPSEL2 ,SPISIMO2 pull select" "Pull down,Pull up" bitfld.long 0x00 17. " SIMOPSEL1 ,SPISIMO1 pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 16. " SIMOPSEL0 ,SPISIMO0 pull select" "Pull down,Pull up" bitfld.long 0x00 11. " SOMIPSEL ,SPISOMI pull select" "Pull down,Pull up" bitfld.long 0x00 10. " SIMOPSEL ,SPISIMO pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 9. " CLKPSEL ,SPICLK pull select" "Pull down,Pull up" bitfld.long 0x00 8. " ENAPSEL ,SPIENA pull select" "Pull down,Pull up" bitfld.long 0x00 7. " SCSPSEL7 ,/SPISCS7 pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 6. " SCSPSEL6 ,/SPISCS6 pull select" "Pull down,Pull up" bitfld.long 0x00 5. " SCSPSEL5 ,/SPISCS5 pull select" "Pull down,Pull up" bitfld.long 0x00 4. " SCSPSEL4 ,/SPISCS4 pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 3. " SCSPSEL3 ,/SPISCS3 pull select" "Pull down,Pull up" bitfld.long 0x00 2. " SCSPSEL2 ,/SPISCS2 pull select" "Pull down,Pull up" bitfld.long 0x00 1. " SCSPSEL1 ,/SPISCS1 pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 0. " SCSPSEL0 ,/SPISCS0 pull select" "Pull down,Pull up" tree.end tree.end width 7. textline " " if (((d.l(ad:0xFFF7F800+0x04))&0x1000000)==0x1000000) group.long 0x38++0x03 line.long 0x00 "DAT0,Transmit Data Register 0" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI / mibspi transmit data" else rgroup.long 0x38++0x03 line.long 0x00 "DAT0,Transmit Data Register 0" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI / mibspi transmit data" endif if (((d.l(ad:0xFFF7F800+0x04))&0x01)==0x01) group.long 0x3C++0x03 line.long 0x00 "DAT1,Transmit Data Register 1" bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Not active,Active" bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled" bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" textline " " hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Spi/mibspi transmit data" else group.long 0x3C++0x03 line.long 0x00 "DAT1,Transmit Data Register 1" bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Spi/mibspi transmit data" endif hgroup.long 0x40++0x03 hide.long 0x00 "BUF,Receive Buffer Register" in if (((d.l(ad:0xFFF7F800+0x04))&0x01)==0x01) rgroup.long 0x44++0x03 line.long 0x00 "EMU,Emulation Register" bitfld.long 0x00 31. " RXEMPTY ,Receive data buffer empty" "No empty,Empty" bitfld.long 0x00 30. " RXOVR ,Receive data buffer overrun" "No overrun,Overrun" bitfld.long 0x00 29. " TXFULL ,Transmit data buffer full" "Empty,Full" textline " " bitfld.long 0x00 28. " BITERR ,Mismatch of internal transmit data and transmitted data" "Not occurred,Occurred" bitfld.long 0x00 27. " DESYNC ,De-synchronization of slave device" "No de-synchronized,De-synchronized" bitfld.long 0x00 26. " PARITYERR ,Calculated parity differs from received parity bit" "No error,Error" textline " " bitfld.long 0x00 25. " TIMEOUT ,Time-out due to Non-activation of ENA pin" "Not occurred,Occurred" bitfld.long 0x00 24. " DLENERR ,Data length error flag" "No error,Error" hexmask.long.byte 0x00 16.--23. 1. " LCSNR ,Last chip select number" textline " " hexmask.long.word 0x00 0.--15. 1. " RXDATA ,SPI receive data" else rgroup.long 0x44++0x03 line.long 0x00 "EMU,Emulation Register" bitfld.long 0x00 31. " RXEMPTY ,Receive data buffer empty" "No empty,Empty" bitfld.long 0x00 30. " RXOVR ,Receive data buffer overrun" "No overrun,Overrun" bitfld.long 0x00 29. " TXFULL ,Transmit data buffer full" "Empty,Full" textline " " bitfld.long 0x00 28. " BITERR ,Mismatch of internal transmit data and transmitted data" "Not occurred,Occurred" bitfld.long 0x00 26. " PARITYERR ,Calculated parity differs from received parity bit" "No error,Error" bitfld.long 0x00 24. " DLENERR ,Data length error flag" "No error,Error" textline " " hexmask.long.byte 0x00 16.--23. 1. " LCSNR ,Last chip select number" hexmask.long.word 0x00 0.--15. 1. " RXDATA ,SPI receive data" endif if (((d.l(ad:0xFFF7F800+0x04))&0x01)==0x01) group.long 0x48++0x03 line.long 0x00 "DELAY,Delay Register" hexmask.long.byte 0x00 24.--31. 1. " C2TDELAY ,Chip select active to transmit start delay" hexmask.long.byte 0x00 16.--23. 1. " T2CDELAY ,Transmit end to chip select inactive delay" hexmask.long.byte 0x00 8.--15. 1. " T2EDELAY ,Transmit data finished to ENA pin inactive time out" textline " " hexmask.long.byte 0x00 0.--7. 1. " C2EDELAY ,Chip select active to ENA signal active time out" else hgroup.long 0x48++0x03 hide.long 0x00 "DELAY,Delay Register" endif group.long 0x4C++0x03 line.long 0x00 "DEF,Default Chip Select Register" bitfld.long 0x00 7. " CSDEF7 ,Chip select default pattern 7" "Low,High" bitfld.long 0x00 6. " CSDEF6 ,Chip select default pattern 6" "Low,High" bitfld.long 0x00 5. " CSDEF5 ,Chip select default pattern 5" "Low,High" bitfld.long 0x00 4. " CSDEF4 ,Chip select default pattern 4" "Low,High" textline " " bitfld.long 0x00 3. " CSDEF3 ,Chip select default pattern 3" "Low,High" bitfld.long 0x00 2. " CSDEF2 ,Chip select default pattern 2" "Low,High" bitfld.long 0x00 1. " CSDEF1 ,Chip select default pattern 1" "Low,High" bitfld.long 0x00 0. " CSDEF0 ,Chip select default pattern 0" "Low,High" width 6. tree "SPI Data Format Registers" group.long 0x50++0x03 line.long 0x00 "FMT0,Data Format Register 0" bitfld.long 0x00 24.--29. " WDELAY0 ,Delay in between transmissions for data format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " PARPOL0 ,Parity polarity" "Even,Odd" bitfld.long 0x00 22. " PARITY0_ENA ,Parity enable for data format 0" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " WAITENA0 ,Master waits for ENA signal from slave for data format 0" "Not wait,Wait" bitfld.long 0x00 20. " SHIFTDIR0 ,Shift direction for data format 0" "MSB,LSB" bitfld.long 0x00 18. " DIS_CS_TIMERS0 ,Disable chipselect timers for this format register" "No,Yes" textline " " bitfld.long 0x00 17. " POLARITY0 ,SPI data format 0 clock polarity" "Low-inactive,High-inactive" bitfld.long 0x00 16. " PHASE0 ,SPI data format 0 clock delay" "Not delayed,Delayed" hexmask.long.byte 0x00 8.--15. 1. " PRESCALE0 ,SPI data format 0 prescaler" textline " " bitfld.long 0x00 0.--4. " CHARLEN0 ,SPI data format 0 data word length" ",,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..." group.long 0x54++0x03 line.long 0x00 "FMT1,Data Format Register 1" bitfld.long 0x00 24.--29. " WDELAY1 ,Delay in between transmissions for data format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " PARPOL1 ,Parity polarity" "Even,Odd" bitfld.long 0x00 22. " PARITY1_ENA ,Parity enable for data format 1" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " WAITENA1 ,Master waits for ENA signal from slave for data format 1" "Not wait,Wait" bitfld.long 0x00 20. " SHIFTDIR1 ,Shift direction for data format 1" "MSB,LSB" bitfld.long 0x00 18. " DIS_CS_TIMERS1 ,Disable chipselect timers for this format register" "No,Yes" textline " " bitfld.long 0x00 17. " POLARITY1 ,SPI data format 1 clock polarity" "Low-inactive,High-inactive" bitfld.long 0x00 16. " PHASE1 ,SPI data format 1 clock delay" "Not delayed,Delayed" hexmask.long.byte 0x00 8.--15. 1. " PRESCALE1 ,SPI data format 1 prescaler" textline " " bitfld.long 0x00 0.--4. " CHARLEN1 ,SPI data format 1 data word length" ",,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..." group.long 0x58++0x03 line.long 0x00 "FMT2,Data Format Register 2" bitfld.long 0x00 24.--29. " WDELAY2 ,Delay in between transmissions for data format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " PARPOL2 ,Parity polarity" "Even,Odd" bitfld.long 0x00 22. " PARITY2_ENA ,Parity enable for data format 2" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " WAITENA2 ,Master waits for ENA signal from slave for data format 2" "Not wait,Wait" bitfld.long 0x00 20. " SHIFTDIR2 ,Shift direction for data format 2" "MSB,LSB" bitfld.long 0x00 18. " DIS_CS_TIMERS2 ,Disable chipselect timers for this format register" "No,Yes" textline " " bitfld.long 0x00 17. " POLARITY2 ,SPI data format 2 clock polarity" "Low-inactive,High-inactive" bitfld.long 0x00 16. " PHASE2 ,SPI data format 2 clock delay" "Not delayed,Delayed" hexmask.long.byte 0x00 8.--15. 1. " PRESCALE2 ,SPI data format 2 prescaler" textline " " bitfld.long 0x00 0.--4. " CHARLEN2 ,SPI data format 2 data word length" ",,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..." group.long 0x5C++0x03 line.long 0x00 "FMT3,Data Format Register 3" bitfld.long 0x00 24.--29. " WDELAY3 ,Delay in between transmissions for data format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " PARPOL3 ,Parity polarity" "Even,Odd" bitfld.long 0x00 22. " PARITY3_ENA ,Parity enable for data format 3" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " WAITENA3 ,Master waits for ENA signal from slave for data format 3" "Not wait,Wait" bitfld.long 0x00 20. " SHIFTDIR3 ,Shift direction for data format 3" "MSB,LSB" bitfld.long 0x00 18. " DIS_CS_TIMERS3 ,Disable chipselect timers for this format register" "No,Yes" textline " " bitfld.long 0x00 17. " POLARITY3 ,SPI data format 3 clock polarity" "Low-inactive,High-inactive" bitfld.long 0x00 16. " PHASE3 ,SPI data format 3 clock delay" "Not delayed,Delayed" hexmask.long.byte 0x00 8.--15. 1. " PRESCALE3 ,SPI data format 3 prescaler" textline " " bitfld.long 0x00 0.--4. " CHARLEN3 ,SPI data format 3 data word length" ",,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..." tree.end width 12. tree "SPI Interrupt Vector Registers" if (((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) rgroup.long 0x60++0x03 line.long 0x00 "TGINTVECT0,Transfer Group Interrupt Vector Register 0" bitfld.long 0x00 1.--5. " INTVECT0 ,Interrupt vector for interrupt line INT0" "No interrupt,Interrupt of transfer group 0,Interrupt of transfer group 1,Interrupt of transfer group 2,Interrupt of transfer group 3,Interrupt of transfer group 4,Interrupt of transfer group 5,Interrupt of transfer group 6,Interrupt of transfer group 7,Interrupt of transfer group 8,Interrupt of transfer group 9,Interrupt of transfer group 10,Interrupt of transfer group 11,Interrupt of transfer group 12,Interrupt of transfer group 13,Interrupt of transfer group 14,Interrupt of transfer group 15,Interrupt/spiint0,,RXORN interrupt,?..." bitfld.long 0x00 0. " SUSPEND0 ,Transfer suspended/finished interrupt" "Suspended,Finished" else rgroup.long 0x60++0x03 line.long 0x00 "TGINTVECT0,Transfer Group Interrupt Vector Register 0" bitfld.long 0x00 1.--5. " INTVECT0 ,Interrupt vector for interrupt line INT0" "No interrupt,,,,,,,,,,,,,,,,,Interrupt/spiint0,Receive buffer full interrupt,Receive buffer overrun interrupt,Transmit buffer empty interrupt,?..." endif if (((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) rgroup.long 0x64++0x03 line.long 0x00 "TGINTVECT1,Transfer Group Interrupt Vector Register 1" bitfld.long 0x00 1.--5. " INTVECT1 ,Interrupt vector for interrupt line INT1" "No interrupt,Interrupt of transfer group 0,Interrupt of transfer group 1,Interrupt of transfer group 2,Interrupt of transfer group 3,Interrupt of transfer group 4,Interrupt of transfer group 5,Interrupt of transfer group 6,Interrupt of transfer group 7,Interrupt of transfer group 8,Interrupt of transfer group 9,Interrupt of transfer group 10,Interrupt of transfer group 11,Interrupt of transfer group 12,Interrupt of transfer group 13,Interrupt of transfer group 14,Interrupt of transfer group 15,Interrupt/spiint1,,RXORN interrupt,?..." bitfld.long 0x00 0. " SUSPEND1 ,Transfer suspended/finished interrupt" "Suspended,Finished" else rgroup.long 0x64++0x03 line.long 0x00 "TGINTVECT1,Transfer Group Interrupt Vector Register 1" bitfld.long 0x00 1.--5. " INTVECT1 ,Interrupt vector for interrupt line INT1" "No interrupt,,,,,,,,,,,,,,,,,Interrupt/spiint1,Receive buffer full interrupt,Receive buffer overrun interrupt,Transmit buffer empty interrupt,?..." endif tree.end width 8. textline " " if (((d.l(ad:0xFFF7F800+0x3C))&0x3000000)==0x00) group.long 0x6C++0x03 line.long 0x00 "PMCTRL,Parallel/modulo Mode Control Register" bitfld.long 0x00 5. " MOD_CLK_POL_0 ,Modulo mode SPICLK polarity" "Normal,Inverted" bitfld.long 0x00 2.--4. " MMODE_0 ,SPI data line selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..." bitfld.long 0x00 0.--1. " PMODE_0 ,Parallel mode" "1-data,2-data,4-data,8-data" elif (((d.l(ad:0xFFF7F800+0x3C))&0x3000000)==0x1000000) group.long 0x6C++0x03 line.long 0x00 "PMCTRL,Parallel/modulo Mode Control Register" bitfld.long 0x00 13. " MOD_CLK_POL_1 ,Modulo mode SPICLK polarity" "Normal,Inverted" bitfld.long 0x00 10.--12. " MMODE_1 ,SPI data line selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..." bitfld.long 0x00 8.--9. " PMODE_1 ,Parallel mode" "1-data,2-data,4-data,8-data" elif (((d.l((ad:0xFFF7F800+0x3C)))&0x3000000)==0x2000000) group.long 0x6C++0x03 line.long 0x00 "PMCTRL,Parallel/modulo Mode Control Register" bitfld.long 0x00 21. " MOD_CLK_POL_2 ,Modulo mode SPICLK polarity" "Normal,Inverted" bitfld.long 0x00 18.--20. " MMODE_2 ,SPI data line selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..." bitfld.long 0x00 16.--17. " PMODE_2 ,Parallel mode" "1-data,2-data,4-data,8-data" else group.long 0x6C++0x03 line.long 0x00 "PMCTRL,Parallel/modulo Mode Control Register" bitfld.long 0x00 29. " MOD_CLK_POL_3 ,Modulo mode SPICLK polarity" "Normal,Inverted" bitfld.long 0x00 26.--28. " MMODE_3 ,SPI data line selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..." bitfld.long 0x00 24.--25. " PMODE_3 ,Parallel mode" "1-data,2-data,4-data,8-data" endif width 11. tree "Mibspi Registers" group.long 0x70++0x03 line.long 0x00 "MIBSPIE,Mibspi Enable Register" bitfld.long 0x00 16. " RX_RAM_ACCESS ,Receive RAM access control bit" "RX not writable,R/W" bitfld.long 0x00 0. " MSPIENA ,Multibuffer mode enable" "Disabled,Enabled" if (((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) group.long 0x74++0x03 line.long 0x00 "TGITENST,Mibspi Transfer Group Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTEN_RDY15_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x04 30. " INTEN_RDY14_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 29. 0x00 29. 0x04 29. " INTEN_RDY13_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x04 28. " INTEN_RDY12_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. 0x00 27. 0x04 27. " INTEN_RDY11_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x04 26. " INTEN_RDY10_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x04 25. " INTEN_RDY9_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x04 24. " INTEN_RDY8_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. 0x00 23. 0x04 23. " INTEN_RDY7_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x04 22. " INTEN_RDY6_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. 0x00 21. 0x04 21. " INTEN_RDY5_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x04 20. " INTEN_RDY4_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x04 19. " INTEN_RDY3_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x04 18. " INTEN_RDY2_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. 0x00 17. 0x04 17. " INTEN_RDY1_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x04 16. " INTEN_RDY0_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 15. 0x00 15. 0x04 15. " INTEN_SUS15_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x04 14. " INTEN_SUS14_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x04 13. " INTEN_SUS13_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x04 12. " INTEN_SUS12_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 11. 0x00 11. 0x04 11. " INTEN_SUS11_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x04 10. " INTEN_SUS10_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. 0x00 9. 0x04 9. " INTEN_SUS9_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x04 8. " INTEN_SUS8_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x04 7. " INTEN_SUS7_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x04 6. " INTEN_SUS6_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x00 5. 0x04 5. " INTEN_SUS5_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x04 4. " INTEN_SUS4_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. 0x00 3. 0x04 3. " INTEN_SUS3_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x04 2. " INTEN_SUS2_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x04 1. " INTEN_SUS1_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " INTEN_SUS0_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" group.long 0x7C++0x03 line.long 0x00 "TGITLVST,Mibspi Transfer Group Interrupt Level Set Register" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTLVL_RDY15_SET/CLR ,Transfer group completed interrupt level 15" "INT0,INT1" setclrfld.long 0x00 30. 0x00 30. 0x04 30. " INTLVL_RDY14_SET/CLR ,Transfer group completed interrupt level 14" "INT0,INT1" textline " " setclrfld.long 0x00 29. 0x00 29. 0x04 29. " INTLVL_RDY13_SET/CLR ,Transfer group completed interrupt level 13" "INT0,INT1" setclrfld.long 0x00 28. 0x00 28. 0x04 28. " INTLVL_RDY12_SET/CLR ,Transfer group completed interrupt level 12" "INT0,INT1" textline " " setclrfld.long 0x00 27. 0x00 27. 0x04 27. " INTLVL_RDY11_SET/CLR ,Transfer group completed interrupt level 11" "INT0,INT1" setclrfld.long 0x00 26. 0x00 26. 0x04 26. " INTLVL_RDY10_SET/CLR ,Transfer group completed interrupt level 10" "INT0,INT1" textline " " setclrfld.long 0x00 25. 0x00 25. 0x04 25. " INTLVL_RDY9_SET/CLR ,Transfer group completed interrupt level set 9" "INT0,INT1" setclrfld.long 0x00 24. 0x00 24. 0x04 24. " INTLVL_RDY8_SET/CLR ,Transfer group completed interrupt level set 8" "INT0,INT1" textline " " setclrfld.long 0x00 23. 0x00 23. 0x04 23. " INTLVL_RDY7_SET/CLR ,Transfer group completed interrupt level set 7" "INT0,INT1" setclrfld.long 0x00 22. 0x00 22. 0x04 22. " INTLVL_RDY6_SET/CLR ,Transfer group completed interrupt level set 6" "INT0,INT1" textline " " setclrfld.long 0x00 21. 0x00 21. 0x04 21. " INTLVL_RDY5_SET/CLR ,Transfer group completed interrupt level set 5" "INT0,INT1" setclrfld.long 0x00 20. 0x00 20. 0x04 20. " INTLVL_RDY4_SET/CLR ,Transfer group completed interrupt level set 4" "INT0,INT1" textline " " setclrfld.long 0x00 19. 0x00 19. 0x04 19. " INTLVL_RDY3_SET/CLR ,Transfer group completed interrupt level set 3" "INT0,INT1" setclrfld.long 0x00 18. 0x00 18. 0x04 18. " INTLVL_RDY2_SET/CLR ,Transfer group completed interrupt level set 2" "INT0,INT1" textline " " setclrfld.long 0x00 17. 0x00 17. 0x04 17. " INTLVL_RDY1_SET/CLR ,Transfer group completed interrupt level set 1" "INT0,INT1" setclrfld.long 0x00 16. 0x00 16. 0x04 16. " INTLVL_RDY0_SET/CLR ,Transfer group completed interrupt level set 0" "INT0,INT1" textline " " setclrfld.long 0x00 15. 0x00 15. 0x04 15. " INTLVL_SUS15_SET/CLR ,Transfer group suspended interrupt level set 15" "INT0,INT1" setclrfld.long 0x00 14. 0x00 14. 0x04 14. " INTLVL_SUS14_SET/CLR ,Transfer group suspended interrupt level set 14" "INT0,INT1" textline " " setclrfld.long 0x00 13. 0x00 13. 0x04 13. " INTLVL_SUS13_SET/CLR ,Transfer group suspended interrupt level set 13" "INT0,INT1" setclrfld.long 0x00 12. 0x00 12. 0x04 12. " INTLVL_SUS12_SET/CLR ,Transfer group suspended interrupt level set 12" "INT0,INT1" textline " " setclrfld.long 0x00 11. 0x00 11. 0x04 11. " INTLVL_SUS11_SET/CLR ,Transfer group suspended interrupt level set 11" "INT0,INT1" setclrfld.long 0x00 10. 0x00 10. 0x04 10. " INTLVL_SUS10_SET/CLR ,Transfer group suspended interrupt level set 10" "INT0,INT1" textline " " setclrfld.long 0x00 9. 0x00 9. 0x04 9. " INTLVL_SUS9_SET/CLR ,Transfer group suspended interrupt level set 9" "INT0,INT1" setclrfld.long 0x00 8. 0x00 8. 0x04 8. " INTLVL_SUS8_SET/CLR ,Transfer group suspended interrupt level set 8" "INT0,INT1" textline " " setclrfld.long 0x00 7. 0x00 7. 0x04 7. " INTLVL_SUS7_SET/CLR ,Transfer group suspended interrupt level set 7" "INT0,INT1" setclrfld.long 0x00 6. 0x00 6. 0x04 6. " INTLVL_SUS6_SET/CLR ,Transfer group suspended interrupt level set 6" "INT0,INT1" textline " " setclrfld.long 0x00 5. 0x00 5. 0x04 5. " INTLVL_SUS5_SET/CLR ,Transfer group suspended interrupt level set 5" "INT0,INT1" setclrfld.long 0x00 4. 0x00 4. 0x04 4. " INTLVL_SUS4_SET/CLR ,Transfer group suspended interrupt level set 4" "INT0,INT1" textline " " setclrfld.long 0x00 3. 0x00 3. 0x04 3. " INTLVL_SUS3_SET/CLR ,Transfer group suspended interrupt level set 3" "INT0,INT1" setclrfld.long 0x00 2. 0x00 2. 0x04 2. " INTLVL_SUS2_SET/CLR ,Transfer group suspended interrupt level set 2" "INT0,INT1" textline " " setclrfld.long 0x00 1. 0x00 1. 0x04 1. " INTLVL_SUS1_SET/CLR ,Transfer group suspended interrupt level set 1" "INT0,INT1" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " INTLVL_SUS0_SET/CLR ,Transfer group suspended interrupt level set 0" "INT0,INT1" group.long 0x84++0x03 line.long 0x00 "TGINTFLAG,Transfer Group Interrupt Flag Register" eventfld.long 0x00 31. " INTFLGRDY15 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" eventfld.long 0x00 30. " INTFLGRDY14 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 29. " INTFLGRDY13 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" eventfld.long 0x00 28. " INTFLGRDY12 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 27. " INTFLGRDY11 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" eventfld.long 0x00 26. " INTFLGRDY10 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 25. " INTFLGRDY9 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" eventfld.long 0x00 24. " INTFLGRDY8 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 23. " INTFLGRDY7 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" eventfld.long 0x00 22. " INTFLGRDY6 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 21. " INTFLGRDY5 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" eventfld.long 0x00 20. " INTFLGRDY4 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 19. " INTFLGRDY3 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" eventfld.long 0x00 18. " INTFLGRDY2 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 17. " INTFLGRDY1 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" eventfld.long 0x00 16. " INTFLGRDY0 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 15. " INTFLGSUS15 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" eventfld.long 0x00 14. " INTFLGSUS14 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 13. " INTFLGSUS13 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" eventfld.long 0x00 12. " INTFLGSUS12 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 11. " INTFLGSUS11 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" eventfld.long 0x00 10. " INTFLGSUS10 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 9. " INTFLGSUS9 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" eventfld.long 0x00 8. " INTFLGSUS8 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 7. " INTFLGSUS7 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" eventfld.long 0x00 6. " INTFLGSUS6 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 5. " INTFLGSUS5 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" eventfld.long 0x00 4. " INTFLGSUS4 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " INTFLGSUS3 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" eventfld.long 0x00 2. " INTFLGSUS2 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 1. " INTFLGSUS1 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " INTFLGSUS0 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" group.long 0x90++0x03 line.long 0x00 "TICKCNT,Tick Count Register" bitfld.long 0x00 31. " TICKENA ,Tick counter enable" "Disabled,Enabled" bitfld.long 0x00 30. " RELOAD ,Re-load tick counter" "No effect,Reload" textline " " bitfld.long 0x00 28.--29. " CLKCTRL ,Tick counter clock source control" "Format 0,Format 1,Format 2,Format 3" hexmask.long.word 0x00 0.--15. 1. " TICKVALUE ,Initial value for tick counter" group.long 0x94++0x03 line.long 0x00 "LTGPEND,Last Transfer Group End Pointer" bitfld.long 0x00 24.--28. " TG_IN_SERVICE ,Transfer group currently being serviced by the sequencer" "Not serviced,Group0,Group1,Group2,Group3,Group4,Group5,Group6,Group7,Group8,Group9,Group10,Group11,Group12,Group13,Group14,Group15,?..." hexmask.long.byte 0x00 8.--14. 1. " LPEND ,Last transfer group end pointer" else hgroup.long 0x74++0x03 hide.long 0x00 "TGITENST,Mibspi Transfer Group Interrupt Enable Register" hgroup.long 0x7C++0x03 hide.long 0x00 "TGITLVST,Mibspi Transfer Group Interrupt Level Register" hgroup.long 0x84++0x03 hide.long 0x00 "TGINTFLAG,Transfer Group Interrupt Flag Register" hgroup.long 0x90++0x03 hide.long 0x00 "TICKCNT,Tick Count Register" hgroup.long 0x94++0x03 hide.long 0x00 "LTGPEND,Last Transfer Group End Pointer" endif width 20. tree "Mibspi Transfer Group Control Registers" if (((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) group.long 0x98++0x03 line.long 0x00 "TG0CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA0 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT0 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST0 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD0 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT0 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC0 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART0 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT0 ,Transfer group pointer to current buffer" group.long 0x9C++0x03 line.long 0x00 "TG1CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA1 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT1 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST1 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD1 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT1 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC1 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART1 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT1 ,Transfer group pointer to current buffer" group.long 0xA0++0x03 line.long 0x00 "TG2CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA2 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT2 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST2 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD2 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT2 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC2 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART2 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT2 ,Transfer group pointer to current buffer" group.long 0xA4++0x03 line.long 0x00 "TG3CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA3 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT3 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST3 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD3 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT3 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC3 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART3 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT3 ,Transfer group pointer to current buffer" group.long 0xA8++0x03 line.long 0x00 "TG4CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA4 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT4 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST4 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD4 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT4 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC4 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART4 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT4 ,Transfer group pointer to current buffer" group.long 0xAC++0x03 line.long 0x00 "TG5CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA5 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT5 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST5 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD5 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT5 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC5 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART5 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT5 ,Transfer group pointer to current buffer" group.long 0xB0++0x03 line.long 0x00 "TG6CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA6 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT6 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST6 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD6 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT6 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC6 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART6 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT6 ,Transfer group pointer to current buffer" group.long 0xB4++0x03 line.long 0x00 "TG7CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA7 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT7 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST7 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD7 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT7 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC7 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART7 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT7 ,Transfer group pointer to current buffer" group.long 0xB8++0x03 line.long 0x00 "TG8CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA8 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT8 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST8 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD8 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT8 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC8 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART8 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT8 ,Transfer group pointer to current buffer" group.long 0xBC++0x03 line.long 0x00 "TG9CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA9 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT9 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST9 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD9 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT9 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC9 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART9 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT9 ,Transfer group pointer to current buffer" group.long 0xC0++0x03 line.long 0x00 "TG10CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA10 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT10 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST10 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD10 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT10 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC10 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART10 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT10 ,Transfer group pointer to current buffer" group.long 0xC4++0x03 line.long 0x00 "TG11CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA11 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT11 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST11 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD11 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT11 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC11 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART11 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT11 ,Transfer group pointer to current buffer" group.long 0xC8++0x03 line.long 0x00 "TG12CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA12 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT12 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST12 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD12 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT12 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC12 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART12 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT12 ,Transfer group pointer to current buffer" group.long 0xCC++0x03 line.long 0x00 "TG13CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA13 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT13 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST13 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD13 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT13 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC13 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART13 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT13 ,Transfer group pointer to current buffer" group.long 0xD0++0x03 line.long 0x00 "TG14CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA14 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT14 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST14 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD14 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT14 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC14 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART14 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT14 ,Transfer group pointer to current buffer" group.long 0xD4++0x03 line.long 0x00 "TG15CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA15 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT15 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST15 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD15 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT15 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC15 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART15 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT15 ,Transfer group pointer to current buffer" else hgroup.long 0x98++0x03 hide.long 0x00 "TG0CTRL,Mibspi Transfer Group Control Register" hgroup.long 0x9C++0x03 hide.long 0x00 "TG1CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xA0++0x03 hide.long 0x00 "TG2CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xA4++0x03 hide.long 0x00 "TG3CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xA8++0x03 hide.long 0x00 "TG4CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xAC++0x03 hide.long 0x00 "TG5CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xB0++0x03 hide.long 0x00 "TG6CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xB4++0x03 hide.long 0x00 "TG7CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xB8++0x03 hide.long 0x00 "TG8CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xBC++0x03 hide.long 0x00 "TG9CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xC0++0x03 hide.long 0x00 "TG10CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xC4++0x03 hide.long 0x00 "TG11CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xC8++0x03 hide.long 0x00 "TG12CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xCC++0x03 hide.long 0x00 "TG13CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xD0++0x03 hide.long 0x00 "TG14CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xD4++0x03 hide.long 0x00 "TG15CTRL,Mibspi Transfer Group Control Register" endif tree.end textline " " sif (cpu()!="RM42L432") if ((((d.l(ad:0xFFF7F800+0x04))&0x01)==0x01)&&((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) group.long 0xD8++0x03 line.long 0x00 "DMA0CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT0 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 0" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID0 ,Buffer utilized for DMA transfer 0" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP0 ,Receive data DMA request map 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP0 ,Transmit data DMA channel 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA0 ,Receive data DMA channel enable 0" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA0 ,Transmit data DMA channel enable 0" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK0 ,Non-interleaved DMA block transfer 0" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT0 ,Initial count of DMA transfers 0" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT170 ,The 17th bit of COUNT field of DMA0COUNT register" "Low,High" bitfld.long 0x00 0.--5. " COUNT0 ,Actual number of remaining DMA transfer 0" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l(ad:0xFFF7F800+0x04))&0x01)==0x00)&&((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) group.long 0xD8++0x03 line.long 0x00 "DMA0CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT0 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 0" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID0 ,Buffer utilized for DMA transfer 0" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP0 ,Receive data DMA request map 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP0 ,Transmit data DMA channel 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA0 ,Receive data DMA channel enable 0" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA0 ,Transmit data DMA channel enable 0" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT0 ,Initial count of DMA transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT170 ,The 17th bit of COUNT field of DMA0COUNT register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT0 ,Actual number of remaining DMA transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xD8++0x03 hide.long 0x00 "DMA0CTRL,Mibspi DMA Channel Control Register" endif if ((((d.l(ad:0xFFF7F800+0x04))&0x01)==0x01)&&((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) group.long 0xDC++0x03 line.long 0x00 "DMA1CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT1 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 1" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID1 ,Buffer utilized for DMA transfer 1" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP1 ,Receive data DMA request map 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP1 ,Transmit data DMA channel 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA1 ,Receive data DMA channel enable 1" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA1 ,Transmit data DMA channel enable 1" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK1 ,Non-interleaved DMA block transfer 1" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT1 ,Initial count of DMA transfers 1" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT171 ,The 17th bit of COUNT field of DMA1COUNT register" "Low,High" bitfld.long 0x00 0.--5. " COUNT1 ,Actual number of remaining DMA transfer 1" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l(ad:0xFFF7F800+0x04))&0x01)==0x00)&&((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) group.long 0xDC++0x03 line.long 0x00 "DMA1CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT1 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 1" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID1 ,Buffer utilized for DMA transfer 1" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP1 ,Receive data DMA request map 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP1 ,Transmit data DMA channel 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA1 ,Receive data DMA channel enable 1" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA1 ,Transmit data DMA channel enable 1" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT1 ,Initial count of DMA transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT171 ,The 17th bit of COUNT field of DMA1COUNT register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT1 ,Actual number of remaining DMA transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xDC++0x03 hide.long 0x00 "DMA1CTRL,Mibspi DMA Channel Control Register" endif if ((((d.l(ad:0xFFF7F800+0x04))&0x01)==0x01)&&((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) group.long 0xE0++0x03 line.long 0x00 "DMA2CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT2 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 2" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID2 ,Buffer utilized for DMA transfer 2" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP2 ,Receive data DMA request map 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP2 ,Transmit data DMA channel 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA2 ,Receive data DMA channel enable 2" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA2 ,Transmit data DMA channel enable 2" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK2 ,Non-interleaved DMA block transfer 2" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT2 ,Initial count of DMA transfers 2" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT172 ,The 17th bit of COUNT field of DMA2COUNT register" "Low,High" bitfld.long 0x00 0.--5. " COUNT2 ,Actual number of remaining DMA transfer 2" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l(ad:0xFFF7F800+0x04))&0x01)==0x00)&&((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) group.long 0xE0++0x03 line.long 0x00 "DMA2CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT2 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 2" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID2 ,Buffer utilized for DMA transfer 2" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP2 ,Receive data DMA request map 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP2 ,Transmit data DMA channel 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA2 ,Receive data DMA channel enable 2" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA2 ,Transmit data DMA channel enable 2" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT2 ,Initial count of DMA transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT172 ,The 17th bit of COUNT field of DMA2COUNT register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT2 ,Actual number of remaining DMA transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xE0++0x03 hide.long 0x00 "DMA2CTRL,Mibspi DMA Channel Control Register" endif if ((((d.l(ad:0xFFF7F800+0x04))&0x01)==0x01)&&((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) group.long 0xE4++0x03 line.long 0x00 "DMA3CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT3 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 3" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID3 ,Buffer utilized for DMA transfer 3" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP3 ,Receive data DMA request map 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP3 ,Transmit data DMA channel 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA3 ,Receive data DMA channel enable 3" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA3 ,Transmit data DMA channel enable 3" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK3 ,Non-interleaved DMA block transfer 3" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT3 ,Initial count of DMA transfers 3" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT173 ,The 17th bit of COUNT field of DMA3COUNT register" "Low,High" bitfld.long 0x00 0.--5. " COUNT3 ,Actual number of remaining DMA transfer 3" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l(ad:0xFFF7F800+0x04))&0x01)==0x00)&&((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) group.long 0xE4++0x03 line.long 0x00 "DMA3CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT3 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 3" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID3 ,Buffer utilized for DMA transfer 3" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP3 ,Receive data DMA request map 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP3 ,Transmit data DMA channel 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA3 ,Receive data DMA channel enable 3" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA3 ,Transmit data DMA channel enable 3" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT3 ,Initial count of DMA transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT173 ,The 17th bit of COUNT field of DMA3COUNT register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT3 ,Actual number of remaining DMA transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xE4++0x03 hide.long 0x00 "DMA3CTRL,Mibspi DMA Channel Control Register" endif if ((((d.l(ad:0xFFF7F800+0x04))&0x01)==0x01)&&((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) group.long 0xE8++0x03 line.long 0x00 "DMA4CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT4 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 4" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID4 ,Buffer utilized for DMA transfer 4" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP4 ,Receive data DMA request map 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP4 ,Transmit data DMA channel 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA4 ,Receive data DMA channel enable 4" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA4 ,Transmit data DMA channel enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK4 ,Non-interleaved DMA block transfer 4" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT4 ,Initial count of DMA transfers 4" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT174 ,The 17th bit of COUNT field of DMA4COUNT register" "Low,High" bitfld.long 0x00 0.--5. " COUNT4 ,Actual number of remaining DMA transfer 4" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l(ad:0xFFF7F800+0x04))&0x01)==0x00)&&((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) group.long 0xE8++0x03 line.long 0x00 "DMA4CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT4 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 4" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID4 ,Buffer utilized for DMA transfer 4" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP4 ,Receive data DMA request map 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP4 ,Transmit data DMA channel 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA4 ,Receive data DMA channel enable 4" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA4 ,Transmit data DMA channel enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT4 ,Initial count of DMA transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT174 ,The 17th bit of COUNT field of DMA4COUNT register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT4 ,Actual number of remaining DMA transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xE8++0x03 hide.long 0x00 "DMA4CTRL,Mibspi DMA Channel Control Register" endif if ((((d.l(ad:0xFFF7F800+0x04))&0x01)==0x01)&&((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) group.long 0xEC++0x03 line.long 0x00 "DMA5CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT5 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 5" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID5 ,Buffer utilized for DMA transfer 5" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP5 ,Receive data DMA request map 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP5 ,Transmit data DMA channel 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA5 ,Receive data DMA channel enable 5" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA5 ,Transmit data DMA channel enable 5" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK5 ,Non-interleaved DMA block transfer 5" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT5 ,Initial count of DMA transfers 5" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT175 ,The 17th bit of COUNT field of DMA5COUNT register" "Low,High" bitfld.long 0x00 0.--5. " COUNT5 ,Actual number of remaining DMA transfer 5" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l(ad:0xFFF7F800+0x04))&0x01)==0x00)&&((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) group.long 0xEC++0x03 line.long 0x00 "DMA5CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT5 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 5" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID5 ,Buffer utilized for DMA transfer 5" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP5 ,Receive data DMA request map 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP5 ,Transmit data DMA channel 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA5 ,Receive data DMA channel enable 5" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA5 ,Transmit data DMA channel enable 5" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT5 ,Initial count of DMA transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT175 ,The 17th bit of COUNT field of DMA5COUNT register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT5 ,Actual number of remaining DMA transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xEC++0x03 hide.long 0x00 "DMA5CTRL,Mibspi DMA Channel Control Register" endif if ((((d.l(ad:0xFFF7F800+0x04))&0x01)==0x01)&&((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) group.long 0xF0++0x03 line.long 0x00 "DMA6CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT6 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 6" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID6 ,Buffer utilized for DMA transfer 6" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP6 ,Receive data DMA request map 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP6 ,Transmit data DMA channel 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA6 ,Receive data DMA channel enable 6" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA6 ,Transmit data DMA channel enable 6" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK6 ,Non-interleaved DMA block transfer 6" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT6 ,Initial count of DMA transfers 6" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT176 ,The 17th bit of COUNT field of DMA6COUNT register" "Low,High" bitfld.long 0x00 0.--5. " COUNT6 ,Actual number of remaining DMA transfer 6" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l(ad:0xFFF7F800+0x04))&0x01)==0x00)&&((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) group.long 0xF0++0x03 line.long 0x00 "DMA6CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT6 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 6" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID6 ,Buffer utilized for DMA transfer 6" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP6 ,Receive data DMA request map 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP6 ,Transmit data DMA channel 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA6 ,Receive data DMA channel enable 6" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA6 ,Transmit data DMA channel enable 6" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT6 ,Initial count of DMA transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT176 ,The 17th bit of COUNT field of DMA6COUNT register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT6 ,Actual number of remaining DMA transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xF0++0x03 hide.long 0x00 "DMA6CTRL,Mibspi DMA Channel Control Register" endif if ((((d.l(ad:0xFFF7F800+0x04))&0x01)==0x01)&&((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) group.long 0xF4++0x03 line.long 0x00 "DMA7CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT7 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 7" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID7 ,Buffer utilized for DMA transfer 7" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP7 ,Receive data DMA request map 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP7 ,Transmit data DMA channel 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA7 ,Receive data DMA channel enable 7" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA7 ,Transmit data DMA channel enable 7" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK7 ,Non-interleaved DMA block transfer 7" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT7 ,Initial count of DMA transfers 7" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT177 ,The 17th bit of COUNT field of DMA7COUNT register" "Low,High" bitfld.long 0x00 0.--5. " COUNT7 ,Actual number of remaining DMA transfer 7" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l(ad:0xFFF7F800+0x04))&0x01)==0x00)&&((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) group.long 0xF4++0x03 line.long 0x00 "DMA7CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT7 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 7" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID7 ,Buffer utilized for DMA transfer 7" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP7 ,Receive data DMA request map 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP7 ,Transmit data DMA channel 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA7 ,Receive data DMA channel enable 7" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA7 ,Transmit data DMA channel enable 7" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT7 ,Initial count of DMA transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT177 ,The 17th bit of COUNT field of DMA7COUNT register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT7 ,Actual number of remaining DMA transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xF4++0x03 hide.long 0x00 "DMA7CTRL,Mibspi DMA Channel Control Register" endif if (((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) group.long 0xF8++0x03 line.long 0x00 "DMA0COUNT,ICOUNT Register 0" hexmask.long.word 0x00 16.--31. 1. " ICOUNT0 ,Initial number of DMA transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT0 ,Actual number of remaining DMA transfer" else hgroup.long 0xF8++0x03 hide.long 0x00 "DMA0COUNT,ICOUNT Register 0" endif if (((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) group.long 0xFC++0x03 line.long 0x00 "DMA1COUNT,ICOUNT Register 1" hexmask.long.word 0x00 16.--31. 1. " ICOUNT1 ,Initial number of DMA transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT1 ,Actual number of remaining DMA transfer" else hgroup.long 0xFC++0x03 hide.long 0x00 "DMA1COUNT,ICOUNT Register 1" endif if (((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) group.long 0x100++0x03 line.long 0x00 "DMA2COUNT,ICOUNT Register 2" hexmask.long.word 0x00 16.--31. 1. " ICOUNT2 ,Initial number of DMA transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT2 ,Actual number of remaining DMA transfer" else hgroup.long 0x100++0x03 hide.long 0x00 "DMA2COUNT,ICOUNT Register 2" endif if (((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) group.long 0x104++0x03 line.long 0x00 "DMA3COUNT,ICOUNT Register 3" hexmask.long.word 0x00 16.--31. 1. " ICOUNT3 ,Initial number of DMA transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT3 ,Actual number of remaining DMA transfer" else hgroup.long 0x104++0x03 hide.long 0x00 "DMA3COUNT,ICOUNT Register 3" endif if (((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) group.long 0x108++0x03 line.long 0x00 "DMA4COUNT,ICOUNT Register 4" hexmask.long.word 0x00 16.--31. 1. " ICOUNT4 ,Initial number of DMA transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT4 ,Actual number of remaining DMA transfer" else hgroup.long 0x108++0x03 hide.long 0x00 "DMA4COUNT,ICOUNT Register 4" endif if (((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) group.long 0x10C++0x03 line.long 0x00 "DMA5COUNT,ICOUNT Register 5" hexmask.long.word 0x00 16.--31. 1. " ICOUNT5 ,Initial number of DMA transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT5 ,Actual number of remaining DMA transfer" else hgroup.long 0x10C++0x03 hide.long 0x00 "DMA5COUNT,ICOUNT Register 5" endif if (((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) group.long 0x110++0x03 line.long 0x00 "DMA6COUNT,ICOUNT Register 6" hexmask.long.word 0x00 16.--31. 1. " ICOUNT6 ,Initial number of DMA transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT6 ,Actual number of remaining DMA transfer" else hgroup.long 0x110++0x03 hide.long 0x00 "DMA6COUNT,ICOUNT Register 6" endif if (((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) group.long 0x114++0x03 line.long 0x00 "DMA7COUNT,ICOUNT Register 7" hexmask.long.word 0x00 16.--31. 1. " ICOUNT7 ,Initial number of DMA transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT7 ,Actual number of remaining DMA transfer" else hgroup.long 0x114++0x03 hide.long 0x00 "DMA7COUNT,ICOUNT Register 7" endif endif textline " " if (((d.l(ad:0xFFF7F800+0x70))&0x01)==0x01) sif (cpu()!="RM42L432") group.long 0x118++0x03 line.long 0x00 "DMACNTLEN,DMA LARGE COUNT Register" bitfld.long 0x00 0. " LARGE_COUNT ,Large count" "Modified,Not modified" endif group.long 0x120++0x03 line.long 0x00 "UERRCTRL,Uncorrectable Parity Error Control Register" sif cpuis("RM57L843-ZWT") bitfld.long 0x00 24.--27. " SBE_EVT_EN ,Single bit error event enable" ",,,,,Disabled,,,,,Enabled,?..." bitfld.long 0x00 16.--19. " EDAC_MODE ,These bits determine whether single bit errors (Sbe) detected by the SECDED block will be corrected or not" ",,,,,Disabled,,,,,Enabled,?..." textline " " endif bitfld.long 0x00 8. " PTESTEN ,Parity memory test enable" "Disabled,Enabled" bitfld.long 0x00 0.--3. " EDEN ,Error detection enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" hgroup.long 0x124++0x03 hide.long 0x00 "UERRSTAT,Uncorrectable Parity Error Status Register" in hgroup.long 0x128++0x03 hide.long 0x00 "UERRADDR1,Uncorrectable Parity Error Address Register" in hgroup.long 0x12C++0x03 hide.long 0x00 "UERRADDR0,Uncorrectable Parity Error Address Register" in hgroup.long 0x130++0x03 hide.long 0x00 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register" in else hgroup.long 0x118++0x03 hide.long 0x00 "DMACNTLEN,DMA LARGE COUNT Register" hgroup.long 0x120++0x03 hide.long 0x00 "UERRCTRL,Uncorrectable Parity Error Control Register" hgroup.long 0x124++0x03 hide.long 0x00 "UERRSTAT,Uncorrectable Parity Error Status Register" hgroup.long 0x128++0x03 hide.long 0x00 "UERRADDR1,Uncorrectable Parity Error Address Register" hgroup.long 0x12C++0x03 hide.long 0x00 "UERRADDR0,Uncorrectable Parity Error Address Register" hgroup.long 0x130++0x03 hide.long 0x00 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register" endif tree.end textline " " if ((((d.l(ad:0xFFF7F800+0x134))&0xF00)==0xA00)&&(((d.l(ad:0xFFF7F800+0x134))&0x02)==0x02)) group.long 0x134++0x03 line.long 0x00 "IOLPBKTSTCR,Spi/mibspi IO Loopback Test Control Register" bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" eventfld.long 0x00 24. " SCS_FAIL_FLG ,Analog loopback /SPISCS pin compare failure" "Not failed,Failed" textline " " bitfld.long 0x00 20. " CTRL_BITERR ,Inducing of BITERR during IO loopback test mode control" "Not affected,Flipped" bitfld.long 0x00 19. " CTRL_DESYNC ,Inducing of DESYNC error during IO loopback test mode control" "Not affected,Forced to 0" textline " " bitfld.long 0x00 18. " CTRL_PARERR ,Inducing of parity error during IO loopback test mode control" "Not affected,Flipped" bitfld.long 0x00 17. " CTRL_TIMEOUT ,Inducing of TIMEOUT error during IO loopback test mode control" "Not affected,Forced to 1" textline " " bitfld.long 0x00 16. " CTRL_DLENERR ,Inducing of data length error during IO loopback test mode control" "Not affected,Forced to 1" bitfld.long 0x00 3.--5. " ERR_SCS_PIN ,Error on chip select pin injection" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]" textline " " bitfld.long 0x00 2. " CTRL_SCS_PIN_ERR ,/SPISCS[7:0] pins error injection enable control" "Disabled,Enabled" bitfld.long 0x00 1. " LPBK_TYPE ,Module IO loopback type" "Digital,Analog" textline " " bitfld.long 0x00 0. " RXP_ENA ,Module analog loopback through receive pin enable" "Transmit,Receive" elif ((((d.l(ad:0xFFF7F800+0x134))&0xF00)==0xA00)&&(((d.l(ad:0xFFF7F800+0x134))&0x02)==0x00)) group.long 0x134++0x03 line.long 0x00 "IOLPBKTSTCR,Spi/mibspi IO Loopback Test Control Register" bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" eventfld.long 0x00 24. " SCS_FAIL_FLG ,Analog loopback /SPISCS pin compare failure" "Not failed,Failed" textline " " bitfld.long 0x00 20. " CTRL_BITERR ,Inducing of BITERR during IO loopback test mode control" "Not affected,Flipped" bitfld.long 0x00 19. " CTRL_DESYNC ,Inducing of DESYNC error during IO loopback test mode control" "Not affected,Forced to 0" textline " " bitfld.long 0x00 18. " CTRL_PARERR ,Inducing of parity error during IO loopback test mode control" "Not affected,Flipped" bitfld.long 0x00 17. " CTRL_TIMEOUT ,Inducing of TIMEOUT error during IO loopback test mode control" "Not affected,Forced to 1" textline " " bitfld.long 0x00 16. " CTRL_DLENERR ,Inducing of data length error during IO loopback test mode control" "Not affected,Forced to 1" bitfld.long 0x00 3.--5. " ERR_SCS_PIN ,Error on chip select pin injection" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]" textline " " bitfld.long 0x00 2. " CTRL_SCS_PIN_ERR ,/SPISCS[7:0] pins error injection enable control" "Disabled,Enabled" bitfld.long 0x00 1. " LPBK_TYPE ,Module IO loopback type" "Digital,Analog" else group.long 0x134++0x03 line.long 0x00 "IOLPBKTSTCR,Spi/mibspi IO Loopback Test Control Register" bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" endif sif (cpuis("RM46L*")||cpu()=="RM42L432"||cpuis("RM57L843-ZWT")) group.long 0x138++0x07 line.long 0x00 "EXTENDED_PRESCALE1,SPI Extended Prescale Register 1" hexmask.long.word 0x00 16.--26. 1. " EPRESCALE_FMT1 ,Extended prescale value for SPIFMT1" hexmask.long.word 0x00 0.--10. 1. " EPRESCALE_FMT0 ,Extended prescale value for SPIFMT0" line.long 0x04 "EXTENDED_PRESCALE2,SPI Extended Prescale Register 2" hexmask.long.word 0x04 16.--26. 1. " EPRESCALE_FMT3 ,Extended prescale value for SPIFMT1" hexmask.long.word 0x04 0.--10. 1. " EPRESCALE_FMT2 ,Extended prescale value for SPIFMT0" endif sif cpuis("RM57L843-ZWT") group.long 0x140++0x07 line.long 0x00 "ECCDIAG_CTRL,ECC Diagnostic Control Register" bitfld.long 0x00 0.--3. " ECCDIAG_EN ,ECC diagnostic mode enable key bits" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" line.long 0x04 "ECCDIAG_STAT,ECC Diagnostic Status Register" eventfld.long 0x04 17. " DEFLG[1] ,Double bit error flag" "No error,Error" eventfld.long 0x04 16. " DEFLG[0] ,Double bit error flag" "No error,Error" textline " " eventfld.long 0x04 1. " SEFLG[1] ,Single bit error flag" "No error,Error" eventfld.long 0x04 0. " SEFLG[0] ,Single bit error flag" "No error,Error" hgroup.long 0x148++0x07 hide.long 0x00 "SBERRADDR1,Single Bit Error Address Register - RXRAM" in hide.long 0x04 "SBERRADDR0,Single Bit Error Address Register - TXRAM" endif width 0x0B tree "Multi-Buffer RAM" base ad:0xFF0C0000 width 10. tree "Multi-buffer RAM Transmit Data Registers" group.long 0x0++0x03 line.long 0x00 "TXRAM0,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x4++0x03 line.long 0x00 "TXRAM1,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x8++0x03 line.long 0x00 "TXRAM2,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xC++0x03 line.long 0x00 "TXRAM3,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x10++0x03 line.long 0x00 "TXRAM4,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x14++0x03 line.long 0x00 "TXRAM5,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x18++0x03 line.long 0x00 "TXRAM6,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1C++0x03 line.long 0x00 "TXRAM7,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x20++0x03 line.long 0x00 "TXRAM8,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x24++0x03 line.long 0x00 "TXRAM9,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x28++0x03 line.long 0x00 "TXRAM10,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x2C++0x03 line.long 0x00 "TXRAM11,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x30++0x03 line.long 0x00 "TXRAM12,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x34++0x03 line.long 0x00 "TXRAM13,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x38++0x03 line.long 0x00 "TXRAM14,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x3C++0x03 line.long 0x00 "TXRAM15,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x40++0x03 line.long 0x00 "TXRAM16,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x44++0x03 line.long 0x00 "TXRAM17,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x48++0x03 line.long 0x00 "TXRAM18,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x4C++0x03 line.long 0x00 "TXRAM19,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x50++0x03 line.long 0x00 "TXRAM20,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x54++0x03 line.long 0x00 "TXRAM21,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x58++0x03 line.long 0x00 "TXRAM22,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x5C++0x03 line.long 0x00 "TXRAM23,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x60++0x03 line.long 0x00 "TXRAM24,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x64++0x03 line.long 0x00 "TXRAM25,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x68++0x03 line.long 0x00 "TXRAM26,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x6C++0x03 line.long 0x00 "TXRAM27,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x70++0x03 line.long 0x00 "TXRAM28,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x74++0x03 line.long 0x00 "TXRAM29,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x78++0x03 line.long 0x00 "TXRAM30,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x7C++0x03 line.long 0x00 "TXRAM31,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x80++0x03 line.long 0x00 "TXRAM32,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x84++0x03 line.long 0x00 "TXRAM33,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x88++0x03 line.long 0x00 "TXRAM34,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x8C++0x03 line.long 0x00 "TXRAM35,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x90++0x03 line.long 0x00 "TXRAM36,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x94++0x03 line.long 0x00 "TXRAM37,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x98++0x03 line.long 0x00 "TXRAM38,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x9C++0x03 line.long 0x00 "TXRAM39,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xA0++0x03 line.long 0x00 "TXRAM40,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xA4++0x03 line.long 0x00 "TXRAM41,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xA8++0x03 line.long 0x00 "TXRAM42,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xAC++0x03 line.long 0x00 "TXRAM43,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xB0++0x03 line.long 0x00 "TXRAM44,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xB4++0x03 line.long 0x00 "TXRAM45,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xB8++0x03 line.long 0x00 "TXRAM46,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xBC++0x03 line.long 0x00 "TXRAM47,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xC0++0x03 line.long 0x00 "TXRAM48,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xC4++0x03 line.long 0x00 "TXRAM49,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xC8++0x03 line.long 0x00 "TXRAM50,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xCC++0x03 line.long 0x00 "TXRAM51,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xD0++0x03 line.long 0x00 "TXRAM52,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xD4++0x03 line.long 0x00 "TXRAM53,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xD8++0x03 line.long 0x00 "TXRAM54,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xDC++0x03 line.long 0x00 "TXRAM55,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xE0++0x03 line.long 0x00 "TXRAM56,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xE4++0x03 line.long 0x00 "TXRAM57,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xE8++0x03 line.long 0x00 "TXRAM58,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xEC++0x03 line.long 0x00 "TXRAM59,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xF0++0x03 line.long 0x00 "TXRAM60,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xF4++0x03 line.long 0x00 "TXRAM61,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xF8++0x03 line.long 0x00 "TXRAM62,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xFC++0x03 line.long 0x00 "TXRAM63,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x100++0x03 line.long 0x00 "TXRAM64,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x104++0x03 line.long 0x00 "TXRAM65,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x108++0x03 line.long 0x00 "TXRAM66,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x10C++0x03 line.long 0x00 "TXRAM67,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x110++0x03 line.long 0x00 "TXRAM68,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x114++0x03 line.long 0x00 "TXRAM69,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x118++0x03 line.long 0x00 "TXRAM70,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x11C++0x03 line.long 0x00 "TXRAM71,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x120++0x03 line.long 0x00 "TXRAM72,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x124++0x03 line.long 0x00 "TXRAM73,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x128++0x03 line.long 0x00 "TXRAM74,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x12C++0x03 line.long 0x00 "TXRAM75,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x130++0x03 line.long 0x00 "TXRAM76,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x134++0x03 line.long 0x00 "TXRAM77,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x138++0x03 line.long 0x00 "TXRAM78,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x13C++0x03 line.long 0x00 "TXRAM79,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x140++0x03 line.long 0x00 "TXRAM80,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x144++0x03 line.long 0x00 "TXRAM81,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x148++0x03 line.long 0x00 "TXRAM82,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x14C++0x03 line.long 0x00 "TXRAM83,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x150++0x03 line.long 0x00 "TXRAM84,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x154++0x03 line.long 0x00 "TXRAM85,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x158++0x03 line.long 0x00 "TXRAM86,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x15C++0x03 line.long 0x00 "TXRAM87,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x160++0x03 line.long 0x00 "TXRAM88,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x164++0x03 line.long 0x00 "TXRAM89,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x168++0x03 line.long 0x00 "TXRAM90,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x16C++0x03 line.long 0x00 "TXRAM91,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x170++0x03 line.long 0x00 "TXRAM92,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x174++0x03 line.long 0x00 "TXRAM93,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x178++0x03 line.long 0x00 "TXRAM94,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x17C++0x03 line.long 0x00 "TXRAM95,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x180++0x03 line.long 0x00 "TXRAM96,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x184++0x03 line.long 0x00 "TXRAM97,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x188++0x03 line.long 0x00 "TXRAM98,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x18C++0x03 line.long 0x00 "TXRAM99,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x190++0x03 line.long 0x00 "TXRAM100,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x194++0x03 line.long 0x00 "TXRAM101,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x198++0x03 line.long 0x00 "TXRAM102,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x19C++0x03 line.long 0x00 "TXRAM103,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1A0++0x03 line.long 0x00 "TXRAM104,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1A4++0x03 line.long 0x00 "TXRAM105,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1A8++0x03 line.long 0x00 "TXRAM106,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1AC++0x03 line.long 0x00 "TXRAM107,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1B0++0x03 line.long 0x00 "TXRAM108,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1B4++0x03 line.long 0x00 "TXRAM109,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1B8++0x03 line.long 0x00 "TXRAM110,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1BC++0x03 line.long 0x00 "TXRAM111,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1C0++0x03 line.long 0x00 "TXRAM112,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1C4++0x03 line.long 0x00 "TXRAM113,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1C8++0x03 line.long 0x00 "TXRAM114,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1CC++0x03 line.long 0x00 "TXRAM115,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1D0++0x03 line.long 0x00 "TXRAM116,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1D4++0x03 line.long 0x00 "TXRAM117,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1D8++0x03 line.long 0x00 "TXRAM118,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1DC++0x03 line.long 0x00 "TXRAM119,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1E0++0x03 line.long 0x00 "TXRAM120,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1E4++0x03 line.long 0x00 "TXRAM121,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1E8++0x03 line.long 0x00 "TXRAM122,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1EC++0x03 line.long 0x00 "TXRAM123,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1F0++0x03 line.long 0x00 "TXRAM124,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1F4++0x03 line.long 0x00 "TXRAM125,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1F8++0x03 line.long 0x00 "TXRAM126,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1FC++0x03 line.long 0x00 "TXRAM127,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" tree.end tree "Multi-buffer RAM Receive Buffer Registers" hgroup.long 0x200++0x03 hide.long 0x00 "RXRAM0,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x204++0x03 hide.long 0x00 "RXRAM1,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x208++0x03 hide.long 0x00 "RXRAM2,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x20C++0x03 hide.long 0x00 "RXRAM3,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x210++0x03 hide.long 0x00 "RXRAM4,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x214++0x03 hide.long 0x00 "RXRAM5,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x218++0x03 hide.long 0x00 "RXRAM6,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x21C++0x03 hide.long 0x00 "RXRAM7,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x220++0x03 hide.long 0x00 "RXRAM8,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x224++0x03 hide.long 0x00 "RXRAM9,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x228++0x03 hide.long 0x00 "RXRAM10,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x22C++0x03 hide.long 0x00 "RXRAM11,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x230++0x03 hide.long 0x00 "RXRAM12,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x234++0x03 hide.long 0x00 "RXRAM13,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x238++0x03 hide.long 0x00 "RXRAM14,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x23C++0x03 hide.long 0x00 "RXRAM15,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x240++0x03 hide.long 0x00 "RXRAM16,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x244++0x03 hide.long 0x00 "RXRAM17,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x248++0x03 hide.long 0x00 "RXRAM18,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x24C++0x03 hide.long 0x00 "RXRAM19,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x250++0x03 hide.long 0x00 "RXRAM20,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x254++0x03 hide.long 0x00 "RXRAM21,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x258++0x03 hide.long 0x00 "RXRAM22,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x25C++0x03 hide.long 0x00 "RXRAM23,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x260++0x03 hide.long 0x00 "RXRAM24,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x264++0x03 hide.long 0x00 "RXRAM25,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x268++0x03 hide.long 0x00 "RXRAM26,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x26C++0x03 hide.long 0x00 "RXRAM27,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x270++0x03 hide.long 0x00 "RXRAM28,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x274++0x03 hide.long 0x00 "RXRAM29,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x278++0x03 hide.long 0x00 "RXRAM30,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x27C++0x03 hide.long 0x00 "RXRAM31,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x280++0x03 hide.long 0x00 "RXRAM32,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x284++0x03 hide.long 0x00 "RXRAM33,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x288++0x03 hide.long 0x00 "RXRAM34,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x28C++0x03 hide.long 0x00 "RXRAM35,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x290++0x03 hide.long 0x00 "RXRAM36,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x294++0x03 hide.long 0x00 "RXRAM37,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x298++0x03 hide.long 0x00 "RXRAM38,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x29C++0x03 hide.long 0x00 "RXRAM39,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2A0++0x03 hide.long 0x00 "RXRAM40,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2A4++0x03 hide.long 0x00 "RXRAM41,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2A8++0x03 hide.long 0x00 "RXRAM42,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2AC++0x03 hide.long 0x00 "RXRAM43,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2B0++0x03 hide.long 0x00 "RXRAM44,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2B4++0x03 hide.long 0x00 "RXRAM45,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2B8++0x03 hide.long 0x00 "RXRAM46,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2BC++0x03 hide.long 0x00 "RXRAM47,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2C0++0x03 hide.long 0x00 "RXRAM48,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2C4++0x03 hide.long 0x00 "RXRAM49,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2C8++0x03 hide.long 0x00 "RXRAM50,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2CC++0x03 hide.long 0x00 "RXRAM51,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2D0++0x03 hide.long 0x00 "RXRAM52,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2D4++0x03 hide.long 0x00 "RXRAM53,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2D8++0x03 hide.long 0x00 "RXRAM54,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2DC++0x03 hide.long 0x00 "RXRAM55,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2E0++0x03 hide.long 0x00 "RXRAM56,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2E4++0x03 hide.long 0x00 "RXRAM57,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2E8++0x03 hide.long 0x00 "RXRAM58,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2EC++0x03 hide.long 0x00 "RXRAM59,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2F0++0x03 hide.long 0x00 "RXRAM60,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2F4++0x03 hide.long 0x00 "RXRAM61,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2F8++0x03 hide.long 0x00 "RXRAM62,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2FC++0x03 hide.long 0x00 "RXRAM63,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x300++0x03 hide.long 0x00 "RXRAM64,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x304++0x03 hide.long 0x00 "RXRAM65,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x308++0x03 hide.long 0x00 "RXRAM66,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x30C++0x03 hide.long 0x00 "RXRAM67,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x310++0x03 hide.long 0x00 "RXRAM68,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x314++0x03 hide.long 0x00 "RXRAM69,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x318++0x03 hide.long 0x00 "RXRAM70,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x31C++0x03 hide.long 0x00 "RXRAM71,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x320++0x03 hide.long 0x00 "RXRAM72,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x324++0x03 hide.long 0x00 "RXRAM73,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x328++0x03 hide.long 0x00 "RXRAM74,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x32C++0x03 hide.long 0x00 "RXRAM75,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x330++0x03 hide.long 0x00 "RXRAM76,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x334++0x03 hide.long 0x00 "RXRAM77,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x338++0x03 hide.long 0x00 "RXRAM78,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x33C++0x03 hide.long 0x00 "RXRAM79,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x340++0x03 hide.long 0x00 "RXRAM80,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x344++0x03 hide.long 0x00 "RXRAM81,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x348++0x03 hide.long 0x00 "RXRAM82,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x34C++0x03 hide.long 0x00 "RXRAM83,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x350++0x03 hide.long 0x00 "RXRAM84,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x354++0x03 hide.long 0x00 "RXRAM85,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x358++0x03 hide.long 0x00 "RXRAM86,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x35C++0x03 hide.long 0x00 "RXRAM87,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x360++0x03 hide.long 0x00 "RXRAM88,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x364++0x03 hide.long 0x00 "RXRAM89,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x368++0x03 hide.long 0x00 "RXRAM90,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x36C++0x03 hide.long 0x00 "RXRAM91,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x370++0x03 hide.long 0x00 "RXRAM92,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x374++0x03 hide.long 0x00 "RXRAM93,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x378++0x03 hide.long 0x00 "RXRAM94,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x37C++0x03 hide.long 0x00 "RXRAM95,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x380++0x03 hide.long 0x00 "RXRAM96,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x384++0x03 hide.long 0x00 "RXRAM97,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x388++0x03 hide.long 0x00 "RXRAM98,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x38C++0x03 hide.long 0x00 "RXRAM99,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x390++0x03 hide.long 0x00 "RXRAM100,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x394++0x03 hide.long 0x00 "RXRAM101,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x398++0x03 hide.long 0x00 "RXRAM102,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x39C++0x03 hide.long 0x00 "RXRAM103,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3A0++0x03 hide.long 0x00 "RXRAM104,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3A4++0x03 hide.long 0x00 "RXRAM105,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3A8++0x03 hide.long 0x00 "RXRAM106,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3AC++0x03 hide.long 0x00 "RXRAM107,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3B0++0x03 hide.long 0x00 "RXRAM108,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3B4++0x03 hide.long 0x00 "RXRAM109,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3B8++0x03 hide.long 0x00 "RXRAM110,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3BC++0x03 hide.long 0x00 "RXRAM111,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3C0++0x03 hide.long 0x00 "RXRAM112,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3C4++0x03 hide.long 0x00 "RXRAM113,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3C8++0x03 hide.long 0x00 "RXRAM114,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3CC++0x03 hide.long 0x00 "RXRAM115,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3D0++0x03 hide.long 0x00 "RXRAM116,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3D4++0x03 hide.long 0x00 "RXRAM117,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3D8++0x03 hide.long 0x00 "RXRAM118,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3DC++0x03 hide.long 0x00 "RXRAM119,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3E0++0x03 hide.long 0x00 "RXRAM120,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3E4++0x03 hide.long 0x00 "RXRAM121,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3E8++0x03 hide.long 0x00 "RXRAM122,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3EC++0x03 hide.long 0x00 "RXRAM123,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3F0++0x03 hide.long 0x00 "RXRAM124,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3F4++0x03 hide.long 0x00 "RXRAM125,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3F8++0x03 hide.long 0x00 "RXRAM126,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3FC++0x03 hide.long 0x00 "RXRAM127,Multi-buffer RAM Receive Buffer Register" in tree.end width 0x0B tree.end tree.end tree "SPI4" base ad:0xFFF7FA00 width 6. group.long 0x00++0x03 line.long 0x00 "GCR0,Global Control Register 0" bitfld.long 0x00 0. " NRESET ,This is the reset bit for the module" "Reset,No reset" if (((d.l(ad:0xFFF7FA00+0x04))&0x03)==0x03) group.long 0x04++0x03 line.long 0x00 "GCR1,Global Control Register 1" bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI pin direction determination" "Input/output,Output/input" bitfld.long 0x00 24. " SPIEN ,SPI enable" "Not active,Active" bitfld.long 0x00 16. " LOOP_BACK ,Internal Loop-back test mode" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " POWERDOWN ,SPI state machines power down state enable" "Active,Power down" bitfld.long 0x00 1. " CLKMOD ,Clock mode" "External,Internal" elif (((d.l(ad:0xFFF7FA00+0x04))&0x03)==0x02) group.long 0x04++0x03 line.long 0x00 "GCR1,Global Control Register 1" bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI pin direction determination" "Input/output,Output/input" bitfld.long 0x00 24. " SPIEN ,SPI enable" "Not active,Active" bitfld.long 0x00 8. " POWERDOWN ,SPI state machines power down state enable" "Active,Power down" textline " " bitfld.long 0x00 1. " CLKMOD ,Clock mode" "External,Internal" elif (((d.l(ad:0xFFF7FA00+0x04))&0x03)==0x01) group.long 0x04++0x03 line.long 0x00 "GCR1,Global Control Register 1" bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI pin direction determination" "Input/output,Output/input" bitfld.long 0x00 24. " SPIEN ,SPI enable" "Not active,Active" bitfld.long 0x00 8. " POWERDOWN ,SPI state machines power down state enable" "Active,Power down" textline " " bitfld.long 0x00 1. " CLKMOD ,Clock mode" "External,Internal" else group.long 0x04++0x03 line.long 0x00 "GCR1,Global Control Register 1" bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI pin direction determination" "Input/output,Output/input" bitfld.long 0x00 24. " SPIEN ,SPI enable" "Not active,Active" bitfld.long 0x00 8. " POWERDOWN ,SPI state machines power down state enable" "Active,Power down" textline " " bitfld.long 0x00 1. " CLKMOD ,Clock mode" "External,Internal" endif if (((d.l(ad:0xFFF7FA00+0x04))&0x01)==0x01) group.long 0x08++0x03 line.long 0x00 "INT0,Interrupt Register" bitfld.long 0x00 24. " ENABLE_HIGHZ ,/SPIENA pin High-z enable" "Disabled,Enabled" textline " " sif (cpu()!="RM42L432") bitfld.long 0x00 16. " DMA_REQ_EN ,DMA request enable" "Not used,Generated" endif textline " " bitfld.long 0x00 9. " TXINTENA ,Transmit interrupt enable" "Not generated,Generated" bitfld.long 0x00 8. " RXINTENA ,Receive interrupt enable" "Not generated,Generated" textline " " bitfld.long 0x00 6. " RXOVRNINTENA ,Overrun interrupt enable" "Not generated,Generated" bitfld.long 0x00 4. " BITERRENA ,Enables interrupt on bit error" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " DESYNCENA ,Enables interrupt on De-synchronized slave" "Disabled,Enabled" bitfld.long 0x00 2. " PARERRENA ,Enables interrupt on parity error" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " TIMEOUTENA ,Enables interrupt on ENA signal Time-out" "Disabled,Enabled" bitfld.long 0x00 0. " DLEN_ERR_ENA ,Data length error interrupt enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "INT0,Interrupt Register" bitfld.long 0x00 24. " ENABLE_HIGHZ ,/SPIENA pin High-z enable" "Disabled,Enabled" textline " " sif (cpu()!="RM42L432") bitfld.long 0x00 16. " DMA_REQ_EN ,DMA request enable" "Not used,Generated" endif textline " " bitfld.long 0x00 9. " TXINTENA ,Transmit interrupt enable" "Not generated,Generated" bitfld.long 0x00 8. " RXINTENA ,Receive interrupt enable" "Not generated,Generated" textline " " bitfld.long 0x00 6. " RXOVRNINTENA ,Overrun interrupt enable" "Not generated,Generated" bitfld.long 0x00 4. " BITERRENA ,Enables interrupt on bit error" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " PARERRENA ,Enables interrupt on parity error" "Disabled,Enabled" bitfld.long 0x00 1. " TIMEOUTENA ,Enables interrupt on ENA signal Time-out" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " DLEN_ERR_ENA ,Data length error interrupt enable" "Disabled,Enabled" endif if (((d.l(ad:0xFFF7FA00+0x04))&0x01)==0x01) group.long 0x0C++0x03 line.long 0x00 "LVL,Interrupt Level Register" bitfld.long 0x00 9. " TXINTLVL ,Transmit interrupt level" "INT0,INT1" bitfld.long 0x00 8. " RXINTLVL ,Receive interrupt level" "INT0,INT1" bitfld.long 0x00 6. " RXOVRNINTLVL ,Receive overrun interrupt level" "INT0,INT1" textline " " bitfld.long 0x00 4. " BITERRLVL ,Bit error interrupt level" "INT0,INT1" bitfld.long 0x00 3. " DESYNCLVL ,De-synchronized slave interrupt level" "INT0,INT1" bitfld.long 0x00 2. " PARERRLVL ,Parity error interrupt level" "INT0,INT1" textline " " bitfld.long 0x00 1. " TIMEOUTLVL ,/SPIENA pin Time-out interrupt level" "INT0,INT1" bitfld.long 0x00 0. " DLEN_ERR_LVL ,Data length error interrupt enable level" "INT0,INT1" else group.long 0x0C++0x03 line.long 0x00 "LVL,Interrupt Level Register" bitfld.long 0x00 9. " TXINTLVL ,Transmit interrupt level" "INT0,INT1" bitfld.long 0x00 8. " RXINTLVL ,Receive interrupt level" "INT0,INT1" bitfld.long 0x00 6. " RXOVRNINTLVL ,Receive overrun interrupt level" "INT0,INT1" textline " " bitfld.long 0x00 4. " BITERRLVL ,Bit error interrupt level" "INT0,INT1" bitfld.long 0x00 2. " PARERRLVL ,Parity error interrupt level" "INT0,INT1" bitfld.long 0x00 1. " TIMEOUTLVL ,/SPIENA pin Time-out interrupt level" "INT0,INT1" textline " " bitfld.long 0x00 0. " DLEN_ERR_LVL ,Data length error interrupt enable level" "INT0,INT1" endif if (((d.l(ad:0xFFF7FA00+0x04))&0x01)==0x01) group.long 0x10++0x03 line.long 0x00 "FLG,Flag Register" bitfld.long 0x00 24. " BUF_INIT_ACTIVE ,Multibuffer initialization active" "Finished,Not finished" bitfld.long 0x00 9. " TXINTFLG ,Transmitter empty interrupt flag" "Full,Empty" textline " " eventfld.long 0x00 8. " RXINTFLG ,Receiver full interrupt flag" "Empty,Full" eventfld.long 0x00 6. " RXOVRNINTFLG ,Receiver overrun flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 4. " BITERRFLG ,Internal transmit data and transmitted data mismatch" "Not occurred,Occurred" eventfld.long 0x00 3. " DESYNCFLG ,Slave device De-Synchronization" "Not detected,Detected" textline " " eventfld.long 0x00 2. " PARITYERRFLG ,Parity error flag" "Not detected,Detected" eventfld.long 0x00 1. " TIMEOUTFLG ,Time-out due to Non-activation of ENA signal" "Not occurred,Occurred" textline " " eventfld.long 0x00 0. " DLEN_ERR_FLG ,Data length error flag" "Not occurred,Occurred" else group.long 0x10++0x03 line.long 0x00 "FLG,Flag Register" bitfld.long 0x00 24. " BUF_INIT_ACTIVE ,Multibuffer initialization active" "Not completed,Completed" bitfld.long 0x00 9. " TXINTFLG ,Transmitter empty interrupt flag" "No empty,Empty" textline " " eventfld.long 0x00 8. " RXINTFLG ,Receiver full interrupt flag" "No full,Full" eventfld.long 0x00 6. " RXOVRNINTFLG ,Receiver overrun flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 4. " BITERRFLG ,Internal transmit data and transmitted data mismatch" "Not occurred,Occurred" eventfld.long 0x00 2. " PARITYERRFLG ,Parity error flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 1. " TIMEOUTFLG ,Time-out due to Non-activation of ENA signal" "Not occurred,Occurred" eventfld.long 0x00 0. " DLEN_ERR_FLG ,Data length error flag" "Not occurred,Occurred" endif width 13. tree "SPI Pin Control Registers" tree "SPI Pin Control Registers 0-5" group.long 0x14++0x03 line.long 0x00 "PC0,Pin Control Register 0" bitfld.long 0x00 31. " SOMIFUN7 ,Slave out master in function 7" "GPIO,Spi/mibspi" bitfld.long 0x00 30. " SOMIFUN6 ,Slave out master in function 6" "GPIO,Spi/mibspi" bitfld.long 0x00 29. " SOMIFUN5 ,Slave out master in function 5" "GPIO,Spi/mibspi" textline " " bitfld.long 0x00 28. " SOMIFUN4 ,Slave out master in function 4" "GPIO,Spi/mibspi" bitfld.long 0x00 27. " SOMIFUN3 ,Slave out master in function 3" "GPIO,Spi/mibspi" bitfld.long 0x00 26. " SOMIFUN2 ,Slave out master in function 2" "GPIO,Spi/mibspi" textline " " bitfld.long 0x00 25. " SOMIFUN1 ,Slave out master in function 1" "GPIO,Spi/mibspi" bitfld.long 0x00 24. " SOMIFUN0 ,Slave out master in function 0" "GPIO,Spi/mibspi" bitfld.long 0x00 23. " SIMOFUN7 ,Slave in master out function 7" "GPIO,Spi/mibspi" textline " " bitfld.long 0x00 22. " SIMOFUN6 ,Slave in master out function 6" "GPIO,Spi/mibspi" bitfld.long 0x00 21. " SIMOFUN5 ,Slave in master out function 5" "GPIO,Spi/mibspi" bitfld.long 0x00 20. " SIMOFUN4 ,Slave in master out function 4" "GPIO,Spi/mibspi" textline " " bitfld.long 0x00 19. " SIMOFUN3 ,Slave in master out function 3" "GPIO,Spi/mibspi" bitfld.long 0x00 18. " SIMOFUN2 ,Slave in master out function 2" "GPIO,Spi/mibspi" bitfld.long 0x00 17. " SIMOFUN1 ,Slave in master out function 1" "GPIO,Spi/mibspi" textline " " bitfld.long 0x00 16. " SIMOFUN0 ,Slave in master out function 0" "GPIO,Spi/mibspi" bitfld.long 0x00 11. " SOMIFUN0 ,Slave out master in function" "GPIO,Spi/mibspi" bitfld.long 0x00 10. " SIMOFUN0 ,Slave in master out function" "GPIO,Spi/mibspi" textline " " bitfld.long 0x00 9. " CLKFUN ,Spi/mibspi clock function" "GPIO,Spi/mibspi" bitfld.long 0x00 8. " ENAFUN ,/SPIENA function" "GPIO,Spi/mibspi" bitfld.long 0x00 7. " SCSFUN7 ,/SPISCS7 function" "GPIO,SPI" textline " " bitfld.long 0x00 6. " SCSFUN6 ,/SPISCS6 function" "GPIO,SPI" bitfld.long 0x00 5. " SCSFUN5 ,/SPISCS5 function" "GPIO,SPI" bitfld.long 0x00 4. " SCSFUN4 ,/SPISCS4 function" "GPIO,SPI" textline " " bitfld.long 0x00 3. " SCSFUN3 ,/SPISCS3 function" "GPIO,SPI" bitfld.long 0x00 2. " SCSFUN2 ,/SPISCS2 function" "GPIO,SPI" bitfld.long 0x00 1. " SCSFUN1 ,/SPISCS1 function" "GPIO,SPI" textline " " bitfld.long 0x00 0. " SCSFUN0 ,/SPISCS0 function" "GPIO,SPI" group.long 0x18++0x03 line.long 0x00 "PC1,Pin Control Register 1" bitfld.long 0x00 31. " SOMIDIR7 ,SPISOMI7 direction" "Input,Output" bitfld.long 0x00 30. " SOMIDIR6 ,SPISOMI6 direction" "Input,Output" bitfld.long 0x00 29. " SOMIDIR5 ,SPISOMI5 direction" "Input,Output" textline " " bitfld.long 0x00 28. " SOMIDIR4 ,SPISOMI4 direction" "Input,Output" bitfld.long 0x00 27. " SOMIDIR3 ,SPISOMI3 direction" "Input,Output" bitfld.long 0x00 26. " SOMIDIR2 ,SPISOMI2 direction" "Input,Output" textline " " bitfld.long 0x00 25. " SOMIDIR1 ,SPISOMI1 direction" "Input,Output" bitfld.long 0x00 24. " SOMIDIR0 ,SPISOMI0 direction" "Input,Output" bitfld.long 0x00 23. " SIMODIR7 ,SPISIMO7 direction" "Input,Output" textline " " bitfld.long 0x00 22. " SIMODIR6 ,SPISIMO6 direction" "Input,Output" bitfld.long 0x00 21. " SIMODIR5 ,SPISIMO5 direction" "Input,Output" bitfld.long 0x00 20. " SIMODIR4 ,SPISIMO4 direction" "Input,Output" textline " " bitfld.long 0x00 19. " SIMODIR3 ,SPISIMO3 direction" "Input,Output" bitfld.long 0x00 18. " SIMODIR2 ,SPISIMO2 direction" "Input,Output" bitfld.long 0x00 17. " SIMODIR1 ,SPISIMO1 direction" "Input,Output" textline " " bitfld.long 0x00 16. " SIMODIR0 ,SPISIMO0 direction" "Input,Output" bitfld.long 0x00 11. " SOMIDIR0 ,SPISOMI0 direction" "Input,Output" bitfld.long 0x00 10. " SIMODIR0 ,SPISIMO0 direction" "Input,Output" textline " " bitfld.long 0x00 9. " CLKDIR ,SPICLK direction" "Input,Output" bitfld.long 0x00 8. " ENADIR ,/SPIENA direction" "Input,Output" bitfld.long 0x00 7. " SCSDIR7 ,/SPISCS7 direction" "Input,Output" textline " " bitfld.long 0x00 6. " SCSDIR6 ,/SPISCS6 direction" "Input,Output" bitfld.long 0x00 5. " SCSDIR5 ,/SPISCS5 direction" "Input,Output" bitfld.long 0x00 4. " SCSDIR4 ,/SPISCS4 direction" "Input,Output" textline " " bitfld.long 0x00 3. " SCSDIR3 ,/SPISCS3 direction" "Input,Output" bitfld.long 0x00 2. " SCSDIR2 ,/SPISCS2 direction" "Input,Output" bitfld.long 0x00 1. " SCSDIR1 ,/SPISCS1 direction" "Input,Output" textline " " bitfld.long 0x00 0. " SCSDIR0 ,/SPISCS0 direction" "Input,Output" rgroup.long 0x1C++0x03 line.long 0x00 "PC2,Pin Control Register 2" bitfld.long 0x00 31. " SOMIDIN7 ,SPISOMI7 data in" "Low,High" bitfld.long 0x00 30. " SOMIDIN6 ,SPISOMI6 data in" "Low,High" bitfld.long 0x00 29. " SOMIDIN5 ,SPISOMI5 data in" "Low,High" textline " " bitfld.long 0x00 28. " SOMIDIN4 ,SPISOMI4 data in" "Low,High" bitfld.long 0x00 27. " SOMIDIN3 ,SPISOMI3 data in" "Low,High" bitfld.long 0x00 26. " SOMIDIN2 ,SPISOMI2 data in" "Low,High" textline " " bitfld.long 0x00 25. " SOMIDIN1 ,SPISOMI1 data in" "Low,High" bitfld.long 0x00 24. " SOMIDIN0 ,SPISOMI0 data in" "Low,High" bitfld.long 0x00 23. " SIMODIN7 ,SPISIMO7 data in" "Low,High" textline " " bitfld.long 0x00 22. " SIMODIN6 ,SPISIMO6 data in" "Low,High" bitfld.long 0x00 21. " SIMODIN5 ,SPISIMO5 data in" "Low,High" bitfld.long 0x00 20. " SIMODIN4 ,SPISIMO4 data in" "Low,High" textline " " bitfld.long 0x00 19. " SIMODIN3 ,SPISIMO3 data in" "Low,High" bitfld.long 0x00 18. " SIMODIN2 ,SPISIMO2 data in" "Low,High" bitfld.long 0x00 17. " SIMODIN1 ,SPISIMO1 data in" "Low,High" textline " " bitfld.long 0x00 16. " SIMODIN0 ,SPISIMO0 data in" "Low,High" bitfld.long 0x00 11. " SOMIDIN0 ,SPISOMI0 data in" "Low,High" bitfld.long 0x00 10. " SIMODIN0 ,SPISIMO0 data in" "Low,High" textline " " bitfld.long 0x00 9. " CLKDIN ,Clock data in" "Low,High" bitfld.long 0x00 8. " ENADIN ,/SPIENA data in" "Low,High" bitfld.long 0x00 7. " SCSDIN7 ,SPISCS7 data in" "Low,High" textline " " bitfld.long 0x00 6. " SCSDIN6 ,SPISCS6 data in" "Low,High" bitfld.long 0x00 5. " SCSDIN5 ,SPISCS5 data in" "Low,High" bitfld.long 0x00 4. " SCSDIN4 ,SPISCS4 data in" "Low,High" textline " " bitfld.long 0x00 3. " SCSDIN3 ,SPISCS3 data in" "Low,High" bitfld.long 0x00 2. " SCSDIN2 ,SPISCS2 data in" "Low,High" bitfld.long 0x00 1. " SCSDIN1 ,SPISCS1 data in" "Low,High" textline " " bitfld.long 0x00 0. " SCSDIN0 ,SPISCS0 data in" "Low,High" group.long 0x20++0x0B line.long 0x00 "PC3,Pin Control Register 3" bitfld.long 0x00 31. " SOMIDOUT7 ,SPISOMI7 dataout write" "Low,High" bitfld.long 0x00 30. " SOMIDOUT6 ,SPISOMI6 dataout write" "Low,High" textline " " bitfld.long 0x00 29. " SOMIDOUT5 ,SPISOMI5 dataout write" "Low,High" bitfld.long 0x00 28. " SOMIDOUT4 ,SPISOMI4 dataout write" "Low,High" textline " " bitfld.long 0x00 27. " SOMIDOUT3 ,SPISOMI3 dataout write" "Low,High" bitfld.long 0x00 26. " SOMIDOUT2 ,SPISOMI2 dataout write" "Low,High" textline " " bitfld.long 0x00 25. " SOMIDOUT1 ,SPISOMI1 dataout write" "Low,High" bitfld.long 0x00 24. " SOMIDOUT0 ,SPISOMI0 dataout write" "Low,High" textline " " bitfld.long 0x00 23. " SIMODOUT7 ,SPISIMO7 dataout write" "Low,High" bitfld.long 0x00 22. " SIMODOUT6 ,SPISIMO6 dataout write" "Low,High" textline " " bitfld.long 0x00 21. " SIMODOUT5 ,SPISIMO5 dataout write" "Low,High" bitfld.long 0x00 20. " SIMODOUT4 ,SPISIMO4 dataout write" "Low,High" textline " " bitfld.long 0x00 19. " SIMODOUT3 ,SPISIMO3 dataout write" "Low,High" bitfld.long 0x00 18. " SIMODOUT2 ,SPISIMO2 dataout write" "Low,High" textline " " bitfld.long 0x00 17. " SIMODOUT1 ,SPISIMO1 dataout write" "Low,High" bitfld.long 0x00 16. " SIMODOUT0 ,SPISIMO0 dataout write" "Low,High" textline " " bitfld.long 0x00 11. " SOMIDOUT0 ,SPISOMI0 dataout write" "Low,High" bitfld.long 0x00 10. " SIMODOUT0 ,SPISIMO0 dataout write" "Low,High" textline " " bitfld.long 0x00 9. " CLKDOUT ,SPICLK dataout write" "Low,High" bitfld.long 0x00 8. " ENADOUT ,/SPIENA dataout write" "Low,High" textline " " bitfld.long 0x00 7. " SCSDOUT7 ,SPISCS7 dataout write" "Low,High" bitfld.long 0x00 6. " SCSDOUT6 ,SPISCS6 dataout write" "Low,High" textline " " bitfld.long 0x00 5. " SCSDOUT5 ,SPISCS5 dataout write" "Low,High" bitfld.long 0x00 4. " SCSDOUT4 ,SPISCS4 dataout write" "Low,High" textline " " bitfld.long 0x00 3. " SCSDOUT3 ,SPISCS3 dataout write" "Low,High" bitfld.long 0x00 2. " SCSDOUT2 ,SPISCS2 dataout write" "Low,High" textline " " bitfld.long 0x00 1. " SCSDOUT1 ,SPISCS1 dataout write" "Low,High" bitfld.long 0x00 0. " SCSDOUT0 ,SPISCS0 dataout write" "Low,High" line.long 0x04 "PC4,Pin Control Register 4" bitfld.long 0x04 31. " SOMISET7 ,SPISOMI7 dataout set" "Not set,Set" bitfld.long 0x04 30. " SOMISET6 ,SPISOMI6 dataout set" "Not set,Set" textline " " bitfld.long 0x04 29. " SOMISET5 ,SPISOMI5 dataout set" "Not set,Set" bitfld.long 0x04 28. " SOMISET4 ,SPISOMI4 dataout set" "Not set,Set" textline " " bitfld.long 0x04 27. " SOMISET3 ,SPISOMI3 dataout set" "Not set,Set" bitfld.long 0x04 26. " SOMISET2 ,SPISOMI2 dataout set" "Not set,Set" textline " " bitfld.long 0x04 25. " SOMISET1 ,SPISOMI1 dataout set" "Not set,Set" bitfld.long 0x04 24. " SOMISET0 ,SPISOMI0 dataout set" "Not set,Set" textline " " bitfld.long 0x04 23. " SIMOSET7 ,SPISIMO7 dataout set" "Not set,Set" bitfld.long 0x04 22. " SIMOSET6 ,SPISIMO6 dataout set" "Not set,Set" textline " " bitfld.long 0x04 21. " SIMOSET5 ,SPISIMO5 dataout set" "Not set,Set" bitfld.long 0x04 20. " SIMOSET4 ,SPISIMO4 dataout set" "Not set,Set" textline " " bitfld.long 0x04 19. " SIMOSET3 ,SPISIMO3 dataout set" "Not set,Set" bitfld.long 0x04 18. " SIMOSET2 ,SPISIMO2 dataout set" "Not set,Set" textline " " bitfld.long 0x04 17. " SIMOSET1 ,SPISIMO1 dataout set" "Not set,Set" bitfld.long 0x04 16. " SIMOSET0 ,SPISIMO0 dataout set" "Not set,Set" textline " " bitfld.long 0x04 11. " SOMISET0 ,SPISOMI0 dataout set" "Not set,Set" bitfld.long 0x04 10. " SIMOSET0 ,SPISIMO0 dataout set" "Not set,Set" textline " " bitfld.long 0x04 9. " CLKSET ,SPICLK dataout set" "Not set,Set" bitfld.long 0x04 8. " ENASET ,/SPIENA dataout set" "Not set,Set" textline " " bitfld.long 0x04 7. " SCSSET7 ,SPISCS7 dataout set" "Not set,Set" bitfld.long 0x04 6. " SCSSET6 ,SPISCS6 dataout set" "Not set,Set" textline " " bitfld.long 0x04 5. " SCSSET5 ,SPISCS5 dataout set" "Not set,Set" bitfld.long 0x04 4. " SCSSET4 ,SPISCS4 dataout set" "Not set,Set" textline " " bitfld.long 0x04 3. " SCSSET3 ,SPISCS3 dataout set" "Not set,Set" bitfld.long 0x04 2. " SCSSET2 ,SPISCS2 dataout set" "Not set,Set" textline " " bitfld.long 0x04 1. " SCSSET1 ,SPISCS1 dataout set" "Not set,Set" bitfld.long 0x04 0. " SCSSET0 ,SPISCS0 dataout set" "Not set,Set" line.long 0x08 "PC5,Pin Control Register 5" bitfld.long 0x08 31. " SOMICLR7 ,SPISOMI7 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 30. " SOMICLR6 ,SPISOMI6 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 29. " SOMICLR5 ,SPISOMI5 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 28. " SOMICLR4 ,SPISOMI4 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 27. " SOMICLR3 ,SPISOMI3 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 26. " SOMICLR2 ,SPISOMI2 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 25. " SOMICLR1 ,SPISOMI1 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 24. " SOMICLR0 ,SPISOMI0 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 23. " SIMOCLR7 ,SPISIMO7 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 22. " SIMOCLR6 ,SPISIMO6 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 21. " SIMOCLR5 ,SPISIMO5 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 20. " SIMOCLR4 ,SPISIMO4 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 19. " SIMOCLR3 ,SPISIMO3 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 18. " SIMOCLR2 ,SPISIMO2 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 17. " SIMOCLR1 ,SPISIMO1 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 16. " SIMOCLR0 ,SPISIMO0 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 11. " SOMICLR0 ,SPISOMI0 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 10. " SIMOCLR0 ,SPISIMO0 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 9. " CLKCLR ,SPICLK dataout clear" "Not cleared,Cleared" bitfld.long 0x08 8. " ENACLR ,/SPIENA dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 7. " SCSCLR7 ,SPISCS7 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 6. " SCSCLR6 ,SPISCS6 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 5. " SCSCLR5 ,SPISCS5 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 4. " SCSCLR4 ,SPISCS4 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 3. " SCSCLR3 ,SPISCS3 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 2. " SCSCLR2 ,SPISCS2 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 1. " SCSCLR1 ,SPISCS1 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 0. " SCSCLR0 ,SPISCS0 dataout clear" "Not cleared,Cleared" tree.end tree "SPI Pin Control Registers 6-8" group.long 0x2C++0x03 line.long 0x00 "PC6,Pin Control Register 1" bitfld.long 0x00 31. " SOMIPDR7 ,SPISOMI7 open drain enable" "High,Tri-stated" bitfld.long 0x00 30. " SOMIPDR6 ,SPISOMI6 open drain enable" "High,Tri-stated" bitfld.long 0x00 29. " SOMIPDR5 ,SPISOMI5 open drain enable" "High,Tri-stated" textline " " bitfld.long 0x00 28. " SOMIPDR4 ,SPISOMI4 open drain enable" "High,Tri-stated" bitfld.long 0x00 27. " SOMIPDR3 ,SPISOMI3 open drain enable" "High,Tri-stated" bitfld.long 0x00 26. " SOMIPDR2 ,SPISOMI2 open drain enable" "High,Tri-stated" textline " " bitfld.long 0x00 25. " SOMIPDR1 ,SPISOMI1 open drain enable" "High,Tri-stated" bitfld.long 0x00 24. " SOMIPDR0 ,SPISOMI0 open drain enable" "High,Tri-stated" bitfld.long 0x00 23. " SIMOPDR7 ,SPISIMO7 open drain enable" "High,Tri-stated" textline " " bitfld.long 0x00 22. " SIMOPDR6 ,SPISIMO6 open drain enable" "High,Tri-stated" bitfld.long 0x00 21. " SIMOPDR5 ,SPISIMO5 open drain enable" "High,Tri-stated" bitfld.long 0x00 20. " SIMOPDR4 ,SPISIMO4 open drain enable" "High,Tri-stated" textline " " bitfld.long 0x00 19. " SIMOPDR3 ,SPISIMO3 open drain enable" "High,Tri-stated" bitfld.long 0x00 18. " SIMOPDR2 ,SPISIMO2 open drain enable" "High,Tri-stated" bitfld.long 0x00 17. " SIMOPDR1 ,SPISIMO1 open drain enable" "High,Tri-stated" textline " " bitfld.long 0x00 16. " SIMOPDR0 ,SPISIMO0 open drain enable" "High,Tri-stated" bitfld.long 0x00 11. " SOMIPDR0 ,SPISOMI0 open drain enable" "High,Tri-stated" bitfld.long 0x00 10. " SIMOPDR0 ,SPISIMO0 open drain enable" "High,Tri-stated" textline " " bitfld.long 0x00 9. " CLKPDR ,SPICLK open drain enable" "High,Tri-stated" bitfld.long 0x00 8. " ENAPDR ,/SPIENA open drain enable" "High,Tri-stated" bitfld.long 0x00 7. " SCSPDR7 ,/SPISCS7 open drain" "High,Tri-stated" textline " " bitfld.long 0x00 6. " SCSPDR6 ,/SPISCS6 open drain" "High,Tri-stated" bitfld.long 0x00 5. " SCSPDR5 ,/SPISCS5 open drain" "High,Tri-stated" bitfld.long 0x00 4. " SCSPDR4 ,/SPISCS4 open drain" "High,Tri-stated" textline " " bitfld.long 0x00 3. " SCSPDR3 ,/SPISCS3 open drain" "High,Tri-stated" bitfld.long 0x00 2. " SCSPDR2 ,/SPISCS2 open drain" "High,Tri-stated" bitfld.long 0x00 1. " SCSPDR1 ,/SPISCS1 open drain" "High,Tri-stated" textline " " bitfld.long 0x00 0. " SCSPDR0 ,/SPISCS0 open drain" "High,Tri-stated" group.long 0x30++0x03 line.long 0x00 "PC7,Pin Control Register 7" bitfld.long 0x00 31. " SOMIPDIS7 ,SPISOMI7 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 30. " SOMIPDIS6 ,SPISOMI6 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 29. " SOMIPDIS5 ,SPISOMI5 pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 28. " SOMIPDIS4 ,SPISOMI4 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 27. " SOMIPDIS3 ,SPISOMI3 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 26. " SOMIPDIS2 ,SPISOMI2 pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 25. " SOMIPDIS1 ,SPISOMI1 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 24. " SOMIPDIS0 ,SPISOMI0 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 23. " SIMOPDIS7 ,SPISIMO7 pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 22. " SIMOPDIS6 ,SPISIMO6 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 21. " SIMOPDIS5 ,SPISIMO5 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 20. " SIMOPDIS4 ,SPISIMO4 pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 19. " SIMOPDIS3 ,SPISIMO3 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 18. " SIMOPDIS2 ,SPISIMO2 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 17. " SIMOPDIS1 ,SPISIMO1 pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 16. " SIMOPDIS0 ,SPISIMO0 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 11. " SOMIPDIS0 ,SPISOMI0 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 10. " SIMOPDIS0 ,SPISIMO pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 9. " CLKPDIS ,SPICLK pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 8. " ENAPDIS ,SPIENA pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 7. " SCSPDIS7 ,SPISCS7 pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 6. " SCSPDIS6 ,SPISCS6 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 5. " SCSPDIS5 ,SPISCS5 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 4. " SCSPDIS4 ,SPISCS4 pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 3. " SCSPDIS3 ,SPISCS3 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 2. " SCSPDIS2 ,SPISCS2 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 1. " SCSPDIS1 ,SPISCS1 pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 0. " SCSPDIS0 ,SPISCS0 pull control enable/disable" "Enabled,Disabled" group.long 0x34++0x03 line.long 0x00 "PC8,Pin Control Register 8" bitfld.long 0x00 31. " SOMIPSEL7 ,SPISOMI7 pull select" "Pull down,Pull up" bitfld.long 0x00 30. " SOMIPSEL6 ,SPISOMI6 pull select" "Pull down,Pull up" bitfld.long 0x00 29. " SOMIPSEL5 ,SPISOMI5 pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 28. " SOMIPSEL4 ,SPISOMI4 pull select" "Pull down,Pull up" bitfld.long 0x00 27. " SOMIPSEL3 ,SPISOMI3 pull select" "Pull down,Pull up" bitfld.long 0x00 26. " SOMIPSEL2 ,SPISOMI2 pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 25. " SOMIPSEL1 ,SPISOMI1 pull select" "Pull down,Pull up" bitfld.long 0x00 24. " SOMIPSEL0 ,SPISOMI0 pull select" "Pull down,Pull up" bitfld.long 0x00 23. " SIMOPSEL7 ,SPISIMO7 pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 22. " SIMOPSEL6 ,SPISIMO6 pull select" "Pull down,Pull up" bitfld.long 0x00 21. " SIMOPSEL5 ,SPISIMO5 pull select" "Pull down,Pull up" bitfld.long 0x00 20. " SIMOPSEL4 ,SPISIMO4 pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 19. " SIMOPSEL3 ,SPISIMO3 pull select" "Pull down,Pull up" bitfld.long 0x00 18. " SIMOPSEL2 ,SPISIMO2 pull select" "Pull down,Pull up" bitfld.long 0x00 17. " SIMOPSEL1 ,SPISIMO1 pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 16. " SIMOPSEL0 ,SPISIMO0 pull select" "Pull down,Pull up" bitfld.long 0x00 11. " SOMIPSEL ,SPISOMI pull select" "Pull down,Pull up" bitfld.long 0x00 10. " SIMOPSEL ,SPISIMO pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 9. " CLKPSEL ,SPICLK pull select" "Pull down,Pull up" bitfld.long 0x00 8. " ENAPSEL ,SPIENA pull select" "Pull down,Pull up" bitfld.long 0x00 7. " SCSPSEL7 ,/SPISCS7 pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 6. " SCSPSEL6 ,/SPISCS6 pull select" "Pull down,Pull up" bitfld.long 0x00 5. " SCSPSEL5 ,/SPISCS5 pull select" "Pull down,Pull up" bitfld.long 0x00 4. " SCSPSEL4 ,/SPISCS4 pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 3. " SCSPSEL3 ,/SPISCS3 pull select" "Pull down,Pull up" bitfld.long 0x00 2. " SCSPSEL2 ,/SPISCS2 pull select" "Pull down,Pull up" bitfld.long 0x00 1. " SCSPSEL1 ,/SPISCS1 pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 0. " SCSPSEL0 ,/SPISCS0 pull select" "Pull down,Pull up" tree.end tree.end width 7. textline " " if (((d.l(ad:0xFFF7FA00+0x04))&0x1000000)==0x1000000) group.long 0x38++0x03 line.long 0x00 "DAT0,Transmit Data Register 0" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI / mibspi transmit data" else rgroup.long 0x38++0x03 line.long 0x00 "DAT0,Transmit Data Register 0" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI / mibspi transmit data" endif if (((d.l(ad:0xFFF7FA00+0x04))&0x01)==0x01) group.long 0x3C++0x03 line.long 0x00 "DAT1,Transmit Data Register 1" bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Not active,Active" bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled" bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" textline " " hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Spi/mibspi transmit data" else group.long 0x3C++0x03 line.long 0x00 "DAT1,Transmit Data Register 1" bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Spi/mibspi transmit data" endif hgroup.long 0x40++0x03 hide.long 0x00 "BUF,Receive Buffer Register" in if (((d.l(ad:0xFFF7FA00+0x04))&0x01)==0x01) rgroup.long 0x44++0x03 line.long 0x00 "EMU,Emulation Register" bitfld.long 0x00 31. " RXEMPTY ,Receive data buffer empty" "No empty,Empty" bitfld.long 0x00 30. " RXOVR ,Receive data buffer overrun" "No overrun,Overrun" bitfld.long 0x00 29. " TXFULL ,Transmit data buffer full" "Empty,Full" textline " " bitfld.long 0x00 28. " BITERR ,Mismatch of internal transmit data and transmitted data" "Not occurred,Occurred" bitfld.long 0x00 27. " DESYNC ,De-synchronization of slave device" "No de-synchronized,De-synchronized" bitfld.long 0x00 26. " PARITYERR ,Calculated parity differs from received parity bit" "No error,Error" textline " " bitfld.long 0x00 25. " TIMEOUT ,Time-out due to Non-activation of ENA pin" "Not occurred,Occurred" bitfld.long 0x00 24. " DLENERR ,Data length error flag" "No error,Error" hexmask.long.byte 0x00 16.--23. 1. " LCSNR ,Last chip select number" textline " " hexmask.long.word 0x00 0.--15. 1. " RXDATA ,SPI receive data" else rgroup.long 0x44++0x03 line.long 0x00 "EMU,Emulation Register" bitfld.long 0x00 31. " RXEMPTY ,Receive data buffer empty" "No empty,Empty" bitfld.long 0x00 30. " RXOVR ,Receive data buffer overrun" "No overrun,Overrun" bitfld.long 0x00 29. " TXFULL ,Transmit data buffer full" "Empty,Full" textline " " bitfld.long 0x00 28. " BITERR ,Mismatch of internal transmit data and transmitted data" "Not occurred,Occurred" bitfld.long 0x00 26. " PARITYERR ,Calculated parity differs from received parity bit" "No error,Error" bitfld.long 0x00 24. " DLENERR ,Data length error flag" "No error,Error" textline " " hexmask.long.byte 0x00 16.--23. 1. " LCSNR ,Last chip select number" hexmask.long.word 0x00 0.--15. 1. " RXDATA ,SPI receive data" endif if (((d.l(ad:0xFFF7FA00+0x04))&0x01)==0x01) group.long 0x48++0x03 line.long 0x00 "DELAY,Delay Register" hexmask.long.byte 0x00 24.--31. 1. " C2TDELAY ,Chip select active to transmit start delay" hexmask.long.byte 0x00 16.--23. 1. " T2CDELAY ,Transmit end to chip select inactive delay" hexmask.long.byte 0x00 8.--15. 1. " T2EDELAY ,Transmit data finished to ENA pin inactive time out" textline " " hexmask.long.byte 0x00 0.--7. 1. " C2EDELAY ,Chip select active to ENA signal active time out" else hgroup.long 0x48++0x03 hide.long 0x00 "DELAY,Delay Register" endif group.long 0x4C++0x03 line.long 0x00 "DEF,Default Chip Select Register" bitfld.long 0x00 7. " CSDEF7 ,Chip select default pattern 7" "Low,High" bitfld.long 0x00 6. " CSDEF6 ,Chip select default pattern 6" "Low,High" bitfld.long 0x00 5. " CSDEF5 ,Chip select default pattern 5" "Low,High" bitfld.long 0x00 4. " CSDEF4 ,Chip select default pattern 4" "Low,High" textline " " bitfld.long 0x00 3. " CSDEF3 ,Chip select default pattern 3" "Low,High" bitfld.long 0x00 2. " CSDEF2 ,Chip select default pattern 2" "Low,High" bitfld.long 0x00 1. " CSDEF1 ,Chip select default pattern 1" "Low,High" bitfld.long 0x00 0. " CSDEF0 ,Chip select default pattern 0" "Low,High" width 6. tree "SPI Data Format Registers" group.long 0x50++0x03 line.long 0x00 "FMT0,Data Format Register 0" bitfld.long 0x00 24.--29. " WDELAY0 ,Delay in between transmissions for data format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " PARPOL0 ,Parity polarity" "Even,Odd" bitfld.long 0x00 22. " PARITY0_ENA ,Parity enable for data format 0" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " WAITENA0 ,Master waits for ENA signal from slave for data format 0" "Not wait,Wait" bitfld.long 0x00 20. " SHIFTDIR0 ,Shift direction for data format 0" "MSB,LSB" bitfld.long 0x00 18. " DIS_CS_TIMERS0 ,Disable chipselect timers for this format register" "No,Yes" textline " " bitfld.long 0x00 17. " POLARITY0 ,SPI data format 0 clock polarity" "Low-inactive,High-inactive" bitfld.long 0x00 16. " PHASE0 ,SPI data format 0 clock delay" "Not delayed,Delayed" hexmask.long.byte 0x00 8.--15. 1. " PRESCALE0 ,SPI data format 0 prescaler" textline " " bitfld.long 0x00 0.--4. " CHARLEN0 ,SPI data format 0 data word length" ",,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..." group.long 0x54++0x03 line.long 0x00 "FMT1,Data Format Register 1" bitfld.long 0x00 24.--29. " WDELAY1 ,Delay in between transmissions for data format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " PARPOL1 ,Parity polarity" "Even,Odd" bitfld.long 0x00 22. " PARITY1_ENA ,Parity enable for data format 1" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " WAITENA1 ,Master waits for ENA signal from slave for data format 1" "Not wait,Wait" bitfld.long 0x00 20. " SHIFTDIR1 ,Shift direction for data format 1" "MSB,LSB" bitfld.long 0x00 18. " DIS_CS_TIMERS1 ,Disable chipselect timers for this format register" "No,Yes" textline " " bitfld.long 0x00 17. " POLARITY1 ,SPI data format 1 clock polarity" "Low-inactive,High-inactive" bitfld.long 0x00 16. " PHASE1 ,SPI data format 1 clock delay" "Not delayed,Delayed" hexmask.long.byte 0x00 8.--15. 1. " PRESCALE1 ,SPI data format 1 prescaler" textline " " bitfld.long 0x00 0.--4. " CHARLEN1 ,SPI data format 1 data word length" ",,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..." group.long 0x58++0x03 line.long 0x00 "FMT2,Data Format Register 2" bitfld.long 0x00 24.--29. " WDELAY2 ,Delay in between transmissions for data format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " PARPOL2 ,Parity polarity" "Even,Odd" bitfld.long 0x00 22. " PARITY2_ENA ,Parity enable for data format 2" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " WAITENA2 ,Master waits for ENA signal from slave for data format 2" "Not wait,Wait" bitfld.long 0x00 20. " SHIFTDIR2 ,Shift direction for data format 2" "MSB,LSB" bitfld.long 0x00 18. " DIS_CS_TIMERS2 ,Disable chipselect timers for this format register" "No,Yes" textline " " bitfld.long 0x00 17. " POLARITY2 ,SPI data format 2 clock polarity" "Low-inactive,High-inactive" bitfld.long 0x00 16. " PHASE2 ,SPI data format 2 clock delay" "Not delayed,Delayed" hexmask.long.byte 0x00 8.--15. 1. " PRESCALE2 ,SPI data format 2 prescaler" textline " " bitfld.long 0x00 0.--4. " CHARLEN2 ,SPI data format 2 data word length" ",,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..." group.long 0x5C++0x03 line.long 0x00 "FMT3,Data Format Register 3" bitfld.long 0x00 24.--29. " WDELAY3 ,Delay in between transmissions for data format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " PARPOL3 ,Parity polarity" "Even,Odd" bitfld.long 0x00 22. " PARITY3_ENA ,Parity enable for data format 3" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " WAITENA3 ,Master waits for ENA signal from slave for data format 3" "Not wait,Wait" bitfld.long 0x00 20. " SHIFTDIR3 ,Shift direction for data format 3" "MSB,LSB" bitfld.long 0x00 18. " DIS_CS_TIMERS3 ,Disable chipselect timers for this format register" "No,Yes" textline " " bitfld.long 0x00 17. " POLARITY3 ,SPI data format 3 clock polarity" "Low-inactive,High-inactive" bitfld.long 0x00 16. " PHASE3 ,SPI data format 3 clock delay" "Not delayed,Delayed" hexmask.long.byte 0x00 8.--15. 1. " PRESCALE3 ,SPI data format 3 prescaler" textline " " bitfld.long 0x00 0.--4. " CHARLEN3 ,SPI data format 3 data word length" ",,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..." tree.end width 12. tree "SPI Interrupt Vector Registers" if (((d.l(ad:0xFFF7FA00+0x70))&0x01)==0x01) rgroup.long 0x60++0x03 line.long 0x00 "TGINTVECT0,Transfer Group Interrupt Vector Register 0" bitfld.long 0x00 1.--5. " INTVECT0 ,Interrupt vector for interrupt line INT0" "No interrupt,Interrupt of transfer group 0,Interrupt of transfer group 1,Interrupt of transfer group 2,Interrupt of transfer group 3,Interrupt of transfer group 4,Interrupt of transfer group 5,Interrupt of transfer group 6,Interrupt of transfer group 7,Interrupt of transfer group 8,Interrupt of transfer group 9,Interrupt of transfer group 10,Interrupt of transfer group 11,Interrupt of transfer group 12,Interrupt of transfer group 13,Interrupt of transfer group 14,Interrupt of transfer group 15,Interrupt/spiint0,,RXORN interrupt,?..." bitfld.long 0x00 0. " SUSPEND0 ,Transfer suspended/finished interrupt" "Suspended,Finished" else rgroup.long 0x60++0x03 line.long 0x00 "TGINTVECT0,Transfer Group Interrupt Vector Register 0" bitfld.long 0x00 1.--5. " INTVECT0 ,Interrupt vector for interrupt line INT0" "No interrupt,,,,,,,,,,,,,,,,,Interrupt/spiint0,Receive buffer full interrupt,Receive buffer overrun interrupt,Transmit buffer empty interrupt,?..." endif if (((d.l(ad:0xFFF7FA00+0x70))&0x01)==0x01) rgroup.long 0x64++0x03 line.long 0x00 "TGINTVECT1,Transfer Group Interrupt Vector Register 1" bitfld.long 0x00 1.--5. " INTVECT1 ,Interrupt vector for interrupt line INT1" "No interrupt,Interrupt of transfer group 0,Interrupt of transfer group 1,Interrupt of transfer group 2,Interrupt of transfer group 3,Interrupt of transfer group 4,Interrupt of transfer group 5,Interrupt of transfer group 6,Interrupt of transfer group 7,Interrupt of transfer group 8,Interrupt of transfer group 9,Interrupt of transfer group 10,Interrupt of transfer group 11,Interrupt of transfer group 12,Interrupt of transfer group 13,Interrupt of transfer group 14,Interrupt of transfer group 15,Interrupt/spiint1,,RXORN interrupt,?..." bitfld.long 0x00 0. " SUSPEND1 ,Transfer suspended/finished interrupt" "Suspended,Finished" else rgroup.long 0x64++0x03 line.long 0x00 "TGINTVECT1,Transfer Group Interrupt Vector Register 1" bitfld.long 0x00 1.--5. " INTVECT1 ,Interrupt vector for interrupt line INT1" "No interrupt,,,,,,,,,,,,,,,,,Interrupt/spiint1,Receive buffer full interrupt,Receive buffer overrun interrupt,Transmit buffer empty interrupt,?..." endif tree.end width 8. textline " " if (((d.l(ad:0xFFF7FA00+0x3C))&0x3000000)==0x00) group.long 0x6C++0x03 line.long 0x00 "PMCTRL,Parallel/modulo Mode Control Register" bitfld.long 0x00 5. " MOD_CLK_POL_0 ,Modulo mode SPICLK polarity" "Normal,Inverted" bitfld.long 0x00 2.--4. " MMODE_0 ,SPI data line selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..." bitfld.long 0x00 0.--1. " PMODE_0 ,Parallel mode" "1-data,2-data,4-data,8-data" elif (((d.l(ad:0xFFF7FA00+0x3C))&0x3000000)==0x1000000) group.long 0x6C++0x03 line.long 0x00 "PMCTRL,Parallel/modulo Mode Control Register" bitfld.long 0x00 13. " MOD_CLK_POL_1 ,Modulo mode SPICLK polarity" "Normal,Inverted" bitfld.long 0x00 10.--12. " MMODE_1 ,SPI data line selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..." bitfld.long 0x00 8.--9. " PMODE_1 ,Parallel mode" "1-data,2-data,4-data,8-data" elif (((d.l((ad:0xFFF7FA00+0x3C)))&0x3000000)==0x2000000) group.long 0x6C++0x03 line.long 0x00 "PMCTRL,Parallel/modulo Mode Control Register" bitfld.long 0x00 21. " MOD_CLK_POL_2 ,Modulo mode SPICLK polarity" "Normal,Inverted" bitfld.long 0x00 18.--20. " MMODE_2 ,SPI data line selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..." bitfld.long 0x00 16.--17. " PMODE_2 ,Parallel mode" "1-data,2-data,4-data,8-data" else group.long 0x6C++0x03 line.long 0x00 "PMCTRL,Parallel/modulo Mode Control Register" bitfld.long 0x00 29. " MOD_CLK_POL_3 ,Modulo mode SPICLK polarity" "Normal,Inverted" bitfld.long 0x00 26.--28. " MMODE_3 ,SPI data line selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..." bitfld.long 0x00 24.--25. " PMODE_3 ,Parallel mode" "1-data,2-data,4-data,8-data" endif width 11. tree "Mibspi Registers" group.long 0x70++0x03 line.long 0x00 "MIBSPIE,Mibspi Enable Register" bitfld.long 0x00 16. " RX_RAM_ACCESS ,Receive RAM access control bit" "RX not writable,R/W" bitfld.long 0x00 0. " MSPIENA ,Multibuffer mode enable" "Disabled,Enabled" if (((d.l(ad:0xFFF7FA00+0x70))&0x01)==0x01) group.long 0x74++0x03 line.long 0x00 "TGITENST,Mibspi Transfer Group Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTEN_RDY15_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x04 30. " INTEN_RDY14_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 29. 0x00 29. 0x04 29. " INTEN_RDY13_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x04 28. " INTEN_RDY12_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. 0x00 27. 0x04 27. " INTEN_RDY11_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x04 26. " INTEN_RDY10_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x04 25. " INTEN_RDY9_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x04 24. " INTEN_RDY8_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. 0x00 23. 0x04 23. " INTEN_RDY7_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x04 22. " INTEN_RDY6_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. 0x00 21. 0x04 21. " INTEN_RDY5_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x04 20. " INTEN_RDY4_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x04 19. " INTEN_RDY3_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x04 18. " INTEN_RDY2_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. 0x00 17. 0x04 17. " INTEN_RDY1_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x04 16. " INTEN_RDY0_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 15. 0x00 15. 0x04 15. " INTEN_SUS15_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x04 14. " INTEN_SUS14_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x04 13. " INTEN_SUS13_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x04 12. " INTEN_SUS12_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 11. 0x00 11. 0x04 11. " INTEN_SUS11_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x04 10. " INTEN_SUS10_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. 0x00 9. 0x04 9. " INTEN_SUS9_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x04 8. " INTEN_SUS8_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x04 7. " INTEN_SUS7_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x04 6. " INTEN_SUS6_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x00 5. 0x04 5. " INTEN_SUS5_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x04 4. " INTEN_SUS4_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. 0x00 3. 0x04 3. " INTEN_SUS3_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x04 2. " INTEN_SUS2_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x04 1. " INTEN_SUS1_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " INTEN_SUS0_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" group.long 0x7C++0x03 line.long 0x00 "TGITLVST,Mibspi Transfer Group Interrupt Level Set Register" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTLVL_RDY15_SET/CLR ,Transfer group completed interrupt level 15" "INT0,INT1" setclrfld.long 0x00 30. 0x00 30. 0x04 30. " INTLVL_RDY14_SET/CLR ,Transfer group completed interrupt level 14" "INT0,INT1" textline " " setclrfld.long 0x00 29. 0x00 29. 0x04 29. " INTLVL_RDY13_SET/CLR ,Transfer group completed interrupt level 13" "INT0,INT1" setclrfld.long 0x00 28. 0x00 28. 0x04 28. " INTLVL_RDY12_SET/CLR ,Transfer group completed interrupt level 12" "INT0,INT1" textline " " setclrfld.long 0x00 27. 0x00 27. 0x04 27. " INTLVL_RDY11_SET/CLR ,Transfer group completed interrupt level 11" "INT0,INT1" setclrfld.long 0x00 26. 0x00 26. 0x04 26. " INTLVL_RDY10_SET/CLR ,Transfer group completed interrupt level 10" "INT0,INT1" textline " " setclrfld.long 0x00 25. 0x00 25. 0x04 25. " INTLVL_RDY9_SET/CLR ,Transfer group completed interrupt level set 9" "INT0,INT1" setclrfld.long 0x00 24. 0x00 24. 0x04 24. " INTLVL_RDY8_SET/CLR ,Transfer group completed interrupt level set 8" "INT0,INT1" textline " " setclrfld.long 0x00 23. 0x00 23. 0x04 23. " INTLVL_RDY7_SET/CLR ,Transfer group completed interrupt level set 7" "INT0,INT1" setclrfld.long 0x00 22. 0x00 22. 0x04 22. " INTLVL_RDY6_SET/CLR ,Transfer group completed interrupt level set 6" "INT0,INT1" textline " " setclrfld.long 0x00 21. 0x00 21. 0x04 21. " INTLVL_RDY5_SET/CLR ,Transfer group completed interrupt level set 5" "INT0,INT1" setclrfld.long 0x00 20. 0x00 20. 0x04 20. " INTLVL_RDY4_SET/CLR ,Transfer group completed interrupt level set 4" "INT0,INT1" textline " " setclrfld.long 0x00 19. 0x00 19. 0x04 19. " INTLVL_RDY3_SET/CLR ,Transfer group completed interrupt level set 3" "INT0,INT1" setclrfld.long 0x00 18. 0x00 18. 0x04 18. " INTLVL_RDY2_SET/CLR ,Transfer group completed interrupt level set 2" "INT0,INT1" textline " " setclrfld.long 0x00 17. 0x00 17. 0x04 17. " INTLVL_RDY1_SET/CLR ,Transfer group completed interrupt level set 1" "INT0,INT1" setclrfld.long 0x00 16. 0x00 16. 0x04 16. " INTLVL_RDY0_SET/CLR ,Transfer group completed interrupt level set 0" "INT0,INT1" textline " " setclrfld.long 0x00 15. 0x00 15. 0x04 15. " INTLVL_SUS15_SET/CLR ,Transfer group suspended interrupt level set 15" "INT0,INT1" setclrfld.long 0x00 14. 0x00 14. 0x04 14. " INTLVL_SUS14_SET/CLR ,Transfer group suspended interrupt level set 14" "INT0,INT1" textline " " setclrfld.long 0x00 13. 0x00 13. 0x04 13. " INTLVL_SUS13_SET/CLR ,Transfer group suspended interrupt level set 13" "INT0,INT1" setclrfld.long 0x00 12. 0x00 12. 0x04 12. " INTLVL_SUS12_SET/CLR ,Transfer group suspended interrupt level set 12" "INT0,INT1" textline " " setclrfld.long 0x00 11. 0x00 11. 0x04 11. " INTLVL_SUS11_SET/CLR ,Transfer group suspended interrupt level set 11" "INT0,INT1" setclrfld.long 0x00 10. 0x00 10. 0x04 10. " INTLVL_SUS10_SET/CLR ,Transfer group suspended interrupt level set 10" "INT0,INT1" textline " " setclrfld.long 0x00 9. 0x00 9. 0x04 9. " INTLVL_SUS9_SET/CLR ,Transfer group suspended interrupt level set 9" "INT0,INT1" setclrfld.long 0x00 8. 0x00 8. 0x04 8. " INTLVL_SUS8_SET/CLR ,Transfer group suspended interrupt level set 8" "INT0,INT1" textline " " setclrfld.long 0x00 7. 0x00 7. 0x04 7. " INTLVL_SUS7_SET/CLR ,Transfer group suspended interrupt level set 7" "INT0,INT1" setclrfld.long 0x00 6. 0x00 6. 0x04 6. " INTLVL_SUS6_SET/CLR ,Transfer group suspended interrupt level set 6" "INT0,INT1" textline " " setclrfld.long 0x00 5. 0x00 5. 0x04 5. " INTLVL_SUS5_SET/CLR ,Transfer group suspended interrupt level set 5" "INT0,INT1" setclrfld.long 0x00 4. 0x00 4. 0x04 4. " INTLVL_SUS4_SET/CLR ,Transfer group suspended interrupt level set 4" "INT0,INT1" textline " " setclrfld.long 0x00 3. 0x00 3. 0x04 3. " INTLVL_SUS3_SET/CLR ,Transfer group suspended interrupt level set 3" "INT0,INT1" setclrfld.long 0x00 2. 0x00 2. 0x04 2. " INTLVL_SUS2_SET/CLR ,Transfer group suspended interrupt level set 2" "INT0,INT1" textline " " setclrfld.long 0x00 1. 0x00 1. 0x04 1. " INTLVL_SUS1_SET/CLR ,Transfer group suspended interrupt level set 1" "INT0,INT1" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " INTLVL_SUS0_SET/CLR ,Transfer group suspended interrupt level set 0" "INT0,INT1" group.long 0x84++0x03 line.long 0x00 "TGINTFLAG,Transfer Group Interrupt Flag Register" eventfld.long 0x00 31. " INTFLGRDY15 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" eventfld.long 0x00 30. " INTFLGRDY14 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 29. " INTFLGRDY13 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" eventfld.long 0x00 28. " INTFLGRDY12 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 27. " INTFLGRDY11 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" eventfld.long 0x00 26. " INTFLGRDY10 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 25. " INTFLGRDY9 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" eventfld.long 0x00 24. " INTFLGRDY8 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 23. " INTFLGRDY7 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" eventfld.long 0x00 22. " INTFLGRDY6 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 21. " INTFLGRDY5 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" eventfld.long 0x00 20. " INTFLGRDY4 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 19. " INTFLGRDY3 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" eventfld.long 0x00 18. " INTFLGRDY2 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 17. " INTFLGRDY1 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" eventfld.long 0x00 16. " INTFLGRDY0 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 15. " INTFLGSUS15 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" eventfld.long 0x00 14. " INTFLGSUS14 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 13. " INTFLGSUS13 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" eventfld.long 0x00 12. " INTFLGSUS12 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 11. " INTFLGSUS11 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" eventfld.long 0x00 10. " INTFLGSUS10 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 9. " INTFLGSUS9 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" eventfld.long 0x00 8. " INTFLGSUS8 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 7. " INTFLGSUS7 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" eventfld.long 0x00 6. " INTFLGSUS6 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 5. " INTFLGSUS5 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" eventfld.long 0x00 4. " INTFLGSUS4 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " INTFLGSUS3 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" eventfld.long 0x00 2. " INTFLGSUS2 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 1. " INTFLGSUS1 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " INTFLGSUS0 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" group.long 0x90++0x03 line.long 0x00 "TICKCNT,Tick Count Register" bitfld.long 0x00 31. " TICKENA ,Tick counter enable" "Disabled,Enabled" bitfld.long 0x00 30. " RELOAD ,Re-load tick counter" "No effect,Reload" textline " " bitfld.long 0x00 28.--29. " CLKCTRL ,Tick counter clock source control" "Format 0,Format 1,Format 2,Format 3" hexmask.long.word 0x00 0.--15. 1. " TICKVALUE ,Initial value for tick counter" group.long 0x94++0x03 line.long 0x00 "LTGPEND,Last Transfer Group End Pointer" bitfld.long 0x00 24.--28. " TG_IN_SERVICE ,Transfer group currently being serviced by the sequencer" "Not serviced,Group0,Group1,Group2,Group3,Group4,Group5,Group6,Group7,Group8,Group9,Group10,Group11,Group12,Group13,Group14,Group15,?..." hexmask.long.byte 0x00 8.--14. 1. " LPEND ,Last transfer group end pointer" else hgroup.long 0x74++0x03 hide.long 0x00 "TGITENST,Mibspi Transfer Group Interrupt Enable Register" hgroup.long 0x7C++0x03 hide.long 0x00 "TGITLVST,Mibspi Transfer Group Interrupt Level Register" hgroup.long 0x84++0x03 hide.long 0x00 "TGINTFLAG,Transfer Group Interrupt Flag Register" hgroup.long 0x90++0x03 hide.long 0x00 "TICKCNT,Tick Count Register" hgroup.long 0x94++0x03 hide.long 0x00 "LTGPEND,Last Transfer Group End Pointer" endif width 20. tree "Mibspi Transfer Group Control Registers" if (((d.l(ad:0xFFF7FA00+0x70))&0x01)==0x01) group.long 0x98++0x03 line.long 0x00 "TG0CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA0 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT0 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST0 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD0 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT0 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC0 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART0 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT0 ,Transfer group pointer to current buffer" group.long 0x9C++0x03 line.long 0x00 "TG1CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA1 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT1 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST1 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD1 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT1 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC1 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART1 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT1 ,Transfer group pointer to current buffer" group.long 0xA0++0x03 line.long 0x00 "TG2CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA2 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT2 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST2 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD2 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT2 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC2 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART2 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT2 ,Transfer group pointer to current buffer" group.long 0xA4++0x03 line.long 0x00 "TG3CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA3 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT3 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST3 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD3 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT3 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC3 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART3 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT3 ,Transfer group pointer to current buffer" group.long 0xA8++0x03 line.long 0x00 "TG4CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA4 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT4 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST4 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD4 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT4 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC4 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART4 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT4 ,Transfer group pointer to current buffer" group.long 0xAC++0x03 line.long 0x00 "TG5CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA5 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT5 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST5 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD5 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT5 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC5 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART5 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT5 ,Transfer group pointer to current buffer" group.long 0xB0++0x03 line.long 0x00 "TG6CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA6 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT6 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST6 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD6 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT6 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC6 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART6 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT6 ,Transfer group pointer to current buffer" group.long 0xB4++0x03 line.long 0x00 "TG7CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA7 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT7 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST7 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD7 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT7 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC7 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART7 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT7 ,Transfer group pointer to current buffer" group.long 0xB8++0x03 line.long 0x00 "TG8CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA8 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT8 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST8 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD8 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT8 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC8 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART8 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT8 ,Transfer group pointer to current buffer" group.long 0xBC++0x03 line.long 0x00 "TG9CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA9 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT9 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST9 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD9 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT9 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC9 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART9 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT9 ,Transfer group pointer to current buffer" group.long 0xC0++0x03 line.long 0x00 "TG10CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA10 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT10 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST10 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD10 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT10 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC10 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART10 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT10 ,Transfer group pointer to current buffer" group.long 0xC4++0x03 line.long 0x00 "TG11CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA11 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT11 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST11 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD11 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT11 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC11 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART11 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT11 ,Transfer group pointer to current buffer" group.long 0xC8++0x03 line.long 0x00 "TG12CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA12 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT12 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST12 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD12 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT12 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC12 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART12 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT12 ,Transfer group pointer to current buffer" group.long 0xCC++0x03 line.long 0x00 "TG13CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA13 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT13 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST13 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD13 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT13 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC13 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART13 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT13 ,Transfer group pointer to current buffer" group.long 0xD0++0x03 line.long 0x00 "TG14CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA14 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT14 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST14 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD14 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT14 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC14 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART14 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT14 ,Transfer group pointer to current buffer" group.long 0xD4++0x03 line.long 0x00 "TG15CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA15 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT15 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST15 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD15 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT15 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC15 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART15 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT15 ,Transfer group pointer to current buffer" else hgroup.long 0x98++0x03 hide.long 0x00 "TG0CTRL,Mibspi Transfer Group Control Register" hgroup.long 0x9C++0x03 hide.long 0x00 "TG1CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xA0++0x03 hide.long 0x00 "TG2CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xA4++0x03 hide.long 0x00 "TG3CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xA8++0x03 hide.long 0x00 "TG4CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xAC++0x03 hide.long 0x00 "TG5CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xB0++0x03 hide.long 0x00 "TG6CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xB4++0x03 hide.long 0x00 "TG7CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xB8++0x03 hide.long 0x00 "TG8CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xBC++0x03 hide.long 0x00 "TG9CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xC0++0x03 hide.long 0x00 "TG10CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xC4++0x03 hide.long 0x00 "TG11CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xC8++0x03 hide.long 0x00 "TG12CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xCC++0x03 hide.long 0x00 "TG13CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xD0++0x03 hide.long 0x00 "TG14CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xD4++0x03 hide.long 0x00 "TG15CTRL,Mibspi Transfer Group Control Register" endif tree.end textline " " sif (cpu()!="RM42L432") if ((((d.l(ad:0xFFF7FA00+0x04))&0x01)==0x01)&&((d.l(ad:0xFFF7FA00+0x70))&0x01)==0x01) group.long 0xD8++0x03 line.long 0x00 "DMA0CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT0 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 0" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID0 ,Buffer utilized for DMA transfer 0" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP0 ,Receive data DMA request map 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP0 ,Transmit data DMA channel 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA0 ,Receive data DMA channel enable 0" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA0 ,Transmit data DMA channel enable 0" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK0 ,Non-interleaved DMA block transfer 0" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT0 ,Initial count of DMA transfers 0" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT170 ,The 17th bit of COUNT field of DMA0COUNT register" "Low,High" bitfld.long 0x00 0.--5. " COUNT0 ,Actual number of remaining DMA transfer 0" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l(ad:0xFFF7FA00+0x04))&0x01)==0x00)&&((d.l(ad:0xFFF7FA00+0x70))&0x01)==0x01) group.long 0xD8++0x03 line.long 0x00 "DMA0CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT0 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 0" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID0 ,Buffer utilized for DMA transfer 0" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP0 ,Receive data DMA request map 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP0 ,Transmit data DMA channel 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA0 ,Receive data DMA channel enable 0" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA0 ,Transmit data DMA channel enable 0" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT0 ,Initial count of DMA transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT170 ,The 17th bit of COUNT field of DMA0COUNT register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT0 ,Actual number of remaining DMA transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xD8++0x03 hide.long 0x00 "DMA0CTRL,Mibspi DMA Channel Control Register" endif if ((((d.l(ad:0xFFF7FA00+0x04))&0x01)==0x01)&&((d.l(ad:0xFFF7FA00+0x70))&0x01)==0x01) group.long 0xDC++0x03 line.long 0x00 "DMA1CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT1 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 1" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID1 ,Buffer utilized for DMA transfer 1" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP1 ,Receive data DMA request map 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP1 ,Transmit data DMA channel 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA1 ,Receive data DMA channel enable 1" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA1 ,Transmit data DMA channel enable 1" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK1 ,Non-interleaved DMA block transfer 1" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT1 ,Initial count of DMA transfers 1" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT171 ,The 17th bit of COUNT field of DMA1COUNT register" "Low,High" bitfld.long 0x00 0.--5. " COUNT1 ,Actual number of remaining DMA transfer 1" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l(ad:0xFFF7FA00+0x04))&0x01)==0x00)&&((d.l(ad:0xFFF7FA00+0x70))&0x01)==0x01) group.long 0xDC++0x03 line.long 0x00 "DMA1CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT1 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 1" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID1 ,Buffer utilized for DMA transfer 1" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP1 ,Receive data DMA request map 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP1 ,Transmit data DMA channel 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA1 ,Receive data DMA channel enable 1" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA1 ,Transmit data DMA channel enable 1" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT1 ,Initial count of DMA transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT171 ,The 17th bit of COUNT field of DMA1COUNT register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT1 ,Actual number of remaining DMA transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xDC++0x03 hide.long 0x00 "DMA1CTRL,Mibspi DMA Channel Control Register" endif if ((((d.l(ad:0xFFF7FA00+0x04))&0x01)==0x01)&&((d.l(ad:0xFFF7FA00+0x70))&0x01)==0x01) group.long 0xE0++0x03 line.long 0x00 "DMA2CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT2 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 2" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID2 ,Buffer utilized for DMA transfer 2" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP2 ,Receive data DMA request map 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP2 ,Transmit data DMA channel 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA2 ,Receive data DMA channel enable 2" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA2 ,Transmit data DMA channel enable 2" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK2 ,Non-interleaved DMA block transfer 2" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT2 ,Initial count of DMA transfers 2" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT172 ,The 17th bit of COUNT field of DMA2COUNT register" "Low,High" bitfld.long 0x00 0.--5. " COUNT2 ,Actual number of remaining DMA transfer 2" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l(ad:0xFFF7FA00+0x04))&0x01)==0x00)&&((d.l(ad:0xFFF7FA00+0x70))&0x01)==0x01) group.long 0xE0++0x03 line.long 0x00 "DMA2CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT2 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 2" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID2 ,Buffer utilized for DMA transfer 2" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP2 ,Receive data DMA request map 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP2 ,Transmit data DMA channel 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA2 ,Receive data DMA channel enable 2" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA2 ,Transmit data DMA channel enable 2" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT2 ,Initial count of DMA transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT172 ,The 17th bit of COUNT field of DMA2COUNT register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT2 ,Actual number of remaining DMA transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xE0++0x03 hide.long 0x00 "DMA2CTRL,Mibspi DMA Channel Control Register" endif if ((((d.l(ad:0xFFF7FA00+0x04))&0x01)==0x01)&&((d.l(ad:0xFFF7FA00+0x70))&0x01)==0x01) group.long 0xE4++0x03 line.long 0x00 "DMA3CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT3 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 3" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID3 ,Buffer utilized for DMA transfer 3" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP3 ,Receive data DMA request map 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP3 ,Transmit data DMA channel 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA3 ,Receive data DMA channel enable 3" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA3 ,Transmit data DMA channel enable 3" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK3 ,Non-interleaved DMA block transfer 3" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT3 ,Initial count of DMA transfers 3" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT173 ,The 17th bit of COUNT field of DMA3COUNT register" "Low,High" bitfld.long 0x00 0.--5. " COUNT3 ,Actual number of remaining DMA transfer 3" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l(ad:0xFFF7FA00+0x04))&0x01)==0x00)&&((d.l(ad:0xFFF7FA00+0x70))&0x01)==0x01) group.long 0xE4++0x03 line.long 0x00 "DMA3CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT3 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 3" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID3 ,Buffer utilized for DMA transfer 3" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP3 ,Receive data DMA request map 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP3 ,Transmit data DMA channel 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA3 ,Receive data DMA channel enable 3" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA3 ,Transmit data DMA channel enable 3" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT3 ,Initial count of DMA transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT173 ,The 17th bit of COUNT field of DMA3COUNT register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT3 ,Actual number of remaining DMA transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xE4++0x03 hide.long 0x00 "DMA3CTRL,Mibspi DMA Channel Control Register" endif if ((((d.l(ad:0xFFF7FA00+0x04))&0x01)==0x01)&&((d.l(ad:0xFFF7FA00+0x70))&0x01)==0x01) group.long 0xE8++0x03 line.long 0x00 "DMA4CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT4 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 4" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID4 ,Buffer utilized for DMA transfer 4" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP4 ,Receive data DMA request map 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP4 ,Transmit data DMA channel 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA4 ,Receive data DMA channel enable 4" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA4 ,Transmit data DMA channel enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK4 ,Non-interleaved DMA block transfer 4" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT4 ,Initial count of DMA transfers 4" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT174 ,The 17th bit of COUNT field of DMA4COUNT register" "Low,High" bitfld.long 0x00 0.--5. " COUNT4 ,Actual number of remaining DMA transfer 4" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l(ad:0xFFF7FA00+0x04))&0x01)==0x00)&&((d.l(ad:0xFFF7FA00+0x70))&0x01)==0x01) group.long 0xE8++0x03 line.long 0x00 "DMA4CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT4 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 4" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID4 ,Buffer utilized for DMA transfer 4" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP4 ,Receive data DMA request map 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP4 ,Transmit data DMA channel 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA4 ,Receive data DMA channel enable 4" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA4 ,Transmit data DMA channel enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT4 ,Initial count of DMA transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT174 ,The 17th bit of COUNT field of DMA4COUNT register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT4 ,Actual number of remaining DMA transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xE8++0x03 hide.long 0x00 "DMA4CTRL,Mibspi DMA Channel Control Register" endif if ((((d.l(ad:0xFFF7FA00+0x04))&0x01)==0x01)&&((d.l(ad:0xFFF7FA00+0x70))&0x01)==0x01) group.long 0xEC++0x03 line.long 0x00 "DMA5CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT5 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 5" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID5 ,Buffer utilized for DMA transfer 5" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP5 ,Receive data DMA request map 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP5 ,Transmit data DMA channel 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA5 ,Receive data DMA channel enable 5" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA5 ,Transmit data DMA channel enable 5" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK5 ,Non-interleaved DMA block transfer 5" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT5 ,Initial count of DMA transfers 5" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT175 ,The 17th bit of COUNT field of DMA5COUNT register" "Low,High" bitfld.long 0x00 0.--5. " COUNT5 ,Actual number of remaining DMA transfer 5" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l(ad:0xFFF7FA00+0x04))&0x01)==0x00)&&((d.l(ad:0xFFF7FA00+0x70))&0x01)==0x01) group.long 0xEC++0x03 line.long 0x00 "DMA5CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT5 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 5" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID5 ,Buffer utilized for DMA transfer 5" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP5 ,Receive data DMA request map 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP5 ,Transmit data DMA channel 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA5 ,Receive data DMA channel enable 5" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA5 ,Transmit data DMA channel enable 5" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT5 ,Initial count of DMA transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT175 ,The 17th bit of COUNT field of DMA5COUNT register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT5 ,Actual number of remaining DMA transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xEC++0x03 hide.long 0x00 "DMA5CTRL,Mibspi DMA Channel Control Register" endif if ((((d.l(ad:0xFFF7FA00+0x04))&0x01)==0x01)&&((d.l(ad:0xFFF7FA00+0x70))&0x01)==0x01) group.long 0xF0++0x03 line.long 0x00 "DMA6CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT6 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 6" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID6 ,Buffer utilized for DMA transfer 6" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP6 ,Receive data DMA request map 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP6 ,Transmit data DMA channel 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA6 ,Receive data DMA channel enable 6" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA6 ,Transmit data DMA channel enable 6" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK6 ,Non-interleaved DMA block transfer 6" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT6 ,Initial count of DMA transfers 6" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT176 ,The 17th bit of COUNT field of DMA6COUNT register" "Low,High" bitfld.long 0x00 0.--5. " COUNT6 ,Actual number of remaining DMA transfer 6" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l(ad:0xFFF7FA00+0x04))&0x01)==0x00)&&((d.l(ad:0xFFF7FA00+0x70))&0x01)==0x01) group.long 0xF0++0x03 line.long 0x00 "DMA6CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT6 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 6" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID6 ,Buffer utilized for DMA transfer 6" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP6 ,Receive data DMA request map 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP6 ,Transmit data DMA channel 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA6 ,Receive data DMA channel enable 6" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA6 ,Transmit data DMA channel enable 6" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT6 ,Initial count of DMA transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT176 ,The 17th bit of COUNT field of DMA6COUNT register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT6 ,Actual number of remaining DMA transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xF0++0x03 hide.long 0x00 "DMA6CTRL,Mibspi DMA Channel Control Register" endif if ((((d.l(ad:0xFFF7FA00+0x04))&0x01)==0x01)&&((d.l(ad:0xFFF7FA00+0x70))&0x01)==0x01) group.long 0xF4++0x03 line.long 0x00 "DMA7CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT7 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 7" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID7 ,Buffer utilized for DMA transfer 7" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP7 ,Receive data DMA request map 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP7 ,Transmit data DMA channel 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA7 ,Receive data DMA channel enable 7" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA7 ,Transmit data DMA channel enable 7" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK7 ,Non-interleaved DMA block transfer 7" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT7 ,Initial count of DMA transfers 7" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT177 ,The 17th bit of COUNT field of DMA7COUNT register" "Low,High" bitfld.long 0x00 0.--5. " COUNT7 ,Actual number of remaining DMA transfer 7" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l(ad:0xFFF7FA00+0x04))&0x01)==0x00)&&((d.l(ad:0xFFF7FA00+0x70))&0x01)==0x01) group.long 0xF4++0x03 line.long 0x00 "DMA7CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT7 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 7" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID7 ,Buffer utilized for DMA transfer 7" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP7 ,Receive data DMA request map 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP7 ,Transmit data DMA channel 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA7 ,Receive data DMA channel enable 7" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA7 ,Transmit data DMA channel enable 7" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT7 ,Initial count of DMA transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT177 ,The 17th bit of COUNT field of DMA7COUNT register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT7 ,Actual number of remaining DMA transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xF4++0x03 hide.long 0x00 "DMA7CTRL,Mibspi DMA Channel Control Register" endif if (((d.l(ad:0xFFF7FA00+0x70))&0x01)==0x01) group.long 0xF8++0x03 line.long 0x00 "DMA0COUNT,ICOUNT Register 0" hexmask.long.word 0x00 16.--31. 1. " ICOUNT0 ,Initial number of DMA transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT0 ,Actual number of remaining DMA transfer" else hgroup.long 0xF8++0x03 hide.long 0x00 "DMA0COUNT,ICOUNT Register 0" endif if (((d.l(ad:0xFFF7FA00+0x70))&0x01)==0x01) group.long 0xFC++0x03 line.long 0x00 "DMA1COUNT,ICOUNT Register 1" hexmask.long.word 0x00 16.--31. 1. " ICOUNT1 ,Initial number of DMA transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT1 ,Actual number of remaining DMA transfer" else hgroup.long 0xFC++0x03 hide.long 0x00 "DMA1COUNT,ICOUNT Register 1" endif if (((d.l(ad:0xFFF7FA00+0x70))&0x01)==0x01) group.long 0x100++0x03 line.long 0x00 "DMA2COUNT,ICOUNT Register 2" hexmask.long.word 0x00 16.--31. 1. " ICOUNT2 ,Initial number of DMA transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT2 ,Actual number of remaining DMA transfer" else hgroup.long 0x100++0x03 hide.long 0x00 "DMA2COUNT,ICOUNT Register 2" endif if (((d.l(ad:0xFFF7FA00+0x70))&0x01)==0x01) group.long 0x104++0x03 line.long 0x00 "DMA3COUNT,ICOUNT Register 3" hexmask.long.word 0x00 16.--31. 1. " ICOUNT3 ,Initial number of DMA transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT3 ,Actual number of remaining DMA transfer" else hgroup.long 0x104++0x03 hide.long 0x00 "DMA3COUNT,ICOUNT Register 3" endif if (((d.l(ad:0xFFF7FA00+0x70))&0x01)==0x01) group.long 0x108++0x03 line.long 0x00 "DMA4COUNT,ICOUNT Register 4" hexmask.long.word 0x00 16.--31. 1. " ICOUNT4 ,Initial number of DMA transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT4 ,Actual number of remaining DMA transfer" else hgroup.long 0x108++0x03 hide.long 0x00 "DMA4COUNT,ICOUNT Register 4" endif if (((d.l(ad:0xFFF7FA00+0x70))&0x01)==0x01) group.long 0x10C++0x03 line.long 0x00 "DMA5COUNT,ICOUNT Register 5" hexmask.long.word 0x00 16.--31. 1. " ICOUNT5 ,Initial number of DMA transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT5 ,Actual number of remaining DMA transfer" else hgroup.long 0x10C++0x03 hide.long 0x00 "DMA5COUNT,ICOUNT Register 5" endif if (((d.l(ad:0xFFF7FA00+0x70))&0x01)==0x01) group.long 0x110++0x03 line.long 0x00 "DMA6COUNT,ICOUNT Register 6" hexmask.long.word 0x00 16.--31. 1. " ICOUNT6 ,Initial number of DMA transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT6 ,Actual number of remaining DMA transfer" else hgroup.long 0x110++0x03 hide.long 0x00 "DMA6COUNT,ICOUNT Register 6" endif if (((d.l(ad:0xFFF7FA00+0x70))&0x01)==0x01) group.long 0x114++0x03 line.long 0x00 "DMA7COUNT,ICOUNT Register 7" hexmask.long.word 0x00 16.--31. 1. " ICOUNT7 ,Initial number of DMA transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT7 ,Actual number of remaining DMA transfer" else hgroup.long 0x114++0x03 hide.long 0x00 "DMA7COUNT,ICOUNT Register 7" endif endif textline " " if (((d.l(ad:0xFFF7FA00+0x70))&0x01)==0x01) sif (cpu()!="RM42L432") group.long 0x118++0x03 line.long 0x00 "DMACNTLEN,DMA LARGE COUNT Register" bitfld.long 0x00 0. " LARGE_COUNT ,Large count" "Modified,Not modified" endif group.long 0x120++0x03 line.long 0x00 "UERRCTRL,Uncorrectable Parity Error Control Register" sif cpuis("RM57L843-ZWT") bitfld.long 0x00 24.--27. " SBE_EVT_EN ,Single bit error event enable" ",,,,,Disabled,,,,,Enabled,?..." bitfld.long 0x00 16.--19. " EDAC_MODE ,These bits determine whether single bit errors (Sbe) detected by the SECDED block will be corrected or not" ",,,,,Disabled,,,,,Enabled,?..." textline " " endif bitfld.long 0x00 8. " PTESTEN ,Parity memory test enable" "Disabled,Enabled" bitfld.long 0x00 0.--3. " EDEN ,Error detection enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" hgroup.long 0x124++0x03 hide.long 0x00 "UERRSTAT,Uncorrectable Parity Error Status Register" in hgroup.long 0x128++0x03 hide.long 0x00 "UERRADDR1,Uncorrectable Parity Error Address Register" in hgroup.long 0x12C++0x03 hide.long 0x00 "UERRADDR0,Uncorrectable Parity Error Address Register" in hgroup.long 0x130++0x03 hide.long 0x00 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register" in else hgroup.long 0x118++0x03 hide.long 0x00 "DMACNTLEN,DMA LARGE COUNT Register" hgroup.long 0x120++0x03 hide.long 0x00 "UERRCTRL,Uncorrectable Parity Error Control Register" hgroup.long 0x124++0x03 hide.long 0x00 "UERRSTAT,Uncorrectable Parity Error Status Register" hgroup.long 0x128++0x03 hide.long 0x00 "UERRADDR1,Uncorrectable Parity Error Address Register" hgroup.long 0x12C++0x03 hide.long 0x00 "UERRADDR0,Uncorrectable Parity Error Address Register" hgroup.long 0x130++0x03 hide.long 0x00 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register" endif tree.end textline " " if ((((d.l(ad:0xFFF7FA00+0x134))&0xF00)==0xA00)&&(((d.l(ad:0xFFF7FA00+0x134))&0x02)==0x02)) group.long 0x134++0x03 line.long 0x00 "IOLPBKTSTCR,Spi/mibspi IO Loopback Test Control Register" bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" eventfld.long 0x00 24. " SCS_FAIL_FLG ,Analog loopback /SPISCS pin compare failure" "Not failed,Failed" textline " " bitfld.long 0x00 20. " CTRL_BITERR ,Inducing of BITERR during IO loopback test mode control" "Not affected,Flipped" bitfld.long 0x00 19. " CTRL_DESYNC ,Inducing of DESYNC error during IO loopback test mode control" "Not affected,Forced to 0" textline " " bitfld.long 0x00 18. " CTRL_PARERR ,Inducing of parity error during IO loopback test mode control" "Not affected,Flipped" bitfld.long 0x00 17. " CTRL_TIMEOUT ,Inducing of TIMEOUT error during IO loopback test mode control" "Not affected,Forced to 1" textline " " bitfld.long 0x00 16. " CTRL_DLENERR ,Inducing of data length error during IO loopback test mode control" "Not affected,Forced to 1" bitfld.long 0x00 3.--5. " ERR_SCS_PIN ,Error on chip select pin injection" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]" textline " " bitfld.long 0x00 2. " CTRL_SCS_PIN_ERR ,/SPISCS[7:0] pins error injection enable control" "Disabled,Enabled" bitfld.long 0x00 1. " LPBK_TYPE ,Module IO loopback type" "Digital,Analog" textline " " bitfld.long 0x00 0. " RXP_ENA ,Module analog loopback through receive pin enable" "Transmit,Receive" elif ((((d.l(ad:0xFFF7FA00+0x134))&0xF00)==0xA00)&&(((d.l(ad:0xFFF7FA00+0x134))&0x02)==0x00)) group.long 0x134++0x03 line.long 0x00 "IOLPBKTSTCR,Spi/mibspi IO Loopback Test Control Register" bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" eventfld.long 0x00 24. " SCS_FAIL_FLG ,Analog loopback /SPISCS pin compare failure" "Not failed,Failed" textline " " bitfld.long 0x00 20. " CTRL_BITERR ,Inducing of BITERR during IO loopback test mode control" "Not affected,Flipped" bitfld.long 0x00 19. " CTRL_DESYNC ,Inducing of DESYNC error during IO loopback test mode control" "Not affected,Forced to 0" textline " " bitfld.long 0x00 18. " CTRL_PARERR ,Inducing of parity error during IO loopback test mode control" "Not affected,Flipped" bitfld.long 0x00 17. " CTRL_TIMEOUT ,Inducing of TIMEOUT error during IO loopback test mode control" "Not affected,Forced to 1" textline " " bitfld.long 0x00 16. " CTRL_DLENERR ,Inducing of data length error during IO loopback test mode control" "Not affected,Forced to 1" bitfld.long 0x00 3.--5. " ERR_SCS_PIN ,Error on chip select pin injection" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]" textline " " bitfld.long 0x00 2. " CTRL_SCS_PIN_ERR ,/SPISCS[7:0] pins error injection enable control" "Disabled,Enabled" bitfld.long 0x00 1. " LPBK_TYPE ,Module IO loopback type" "Digital,Analog" else group.long 0x134++0x03 line.long 0x00 "IOLPBKTSTCR,Spi/mibspi IO Loopback Test Control Register" bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" endif sif (cpuis("RM46L*")||cpu()=="RM42L432"||cpuis("RM57L843-ZWT")) group.long 0x138++0x07 line.long 0x00 "EXTENDED_PRESCALE1,SPI Extended Prescale Register 1" hexmask.long.word 0x00 16.--26. 1. " EPRESCALE_FMT1 ,Extended prescale value for SPIFMT1" hexmask.long.word 0x00 0.--10. 1. " EPRESCALE_FMT0 ,Extended prescale value for SPIFMT0" line.long 0x04 "EXTENDED_PRESCALE2,SPI Extended Prescale Register 2" hexmask.long.word 0x04 16.--26. 1. " EPRESCALE_FMT3 ,Extended prescale value for SPIFMT1" hexmask.long.word 0x04 0.--10. 1. " EPRESCALE_FMT2 ,Extended prescale value for SPIFMT0" endif sif cpuis("RM57L843-ZWT") group.long 0x140++0x07 line.long 0x00 "ECCDIAG_CTRL,ECC Diagnostic Control Register" bitfld.long 0x00 0.--3. " ECCDIAG_EN ,ECC diagnostic mode enable key bits" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" line.long 0x04 "ECCDIAG_STAT,ECC Diagnostic Status Register" eventfld.long 0x04 17. " DEFLG[1] ,Double bit error flag" "No error,Error" eventfld.long 0x04 16. " DEFLG[0] ,Double bit error flag" "No error,Error" textline " " eventfld.long 0x04 1. " SEFLG[1] ,Single bit error flag" "No error,Error" eventfld.long 0x04 0. " SEFLG[0] ,Single bit error flag" "No error,Error" hgroup.long 0x148++0x07 hide.long 0x00 "SBERRADDR1,Single Bit Error Address Register - RXRAM" in hide.long 0x04 "SBERRADDR0,Single Bit Error Address Register - TXRAM" endif width 0x0B tree.end tree "MIBSPIP5" base ad:0xFFF7FC00 width 6. group.long 0x00++0x03 line.long 0x00 "GCR0,Global Control Register 0" bitfld.long 0x00 0. " NRESET ,This is the reset bit for the module" "Reset,No reset" if (((d.l(ad:0xFFF7FC00+0x04))&0x03)==0x03) group.long 0x04++0x03 line.long 0x00 "GCR1,Global Control Register 1" bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI pin direction determination" "Input/output,Output/input" bitfld.long 0x00 24. " SPIEN ,SPI enable" "Not active,Active" bitfld.long 0x00 16. " LOOP_BACK ,Internal Loop-back test mode" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " POWERDOWN ,SPI state machines power down state enable" "Active,Power down" bitfld.long 0x00 1. " CLKMOD ,Clock mode" "External,Internal" elif (((d.l(ad:0xFFF7FC00+0x04))&0x03)==0x02) group.long 0x04++0x03 line.long 0x00 "GCR1,Global Control Register 1" bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI pin direction determination" "Input/output,Output/input" bitfld.long 0x00 24. " SPIEN ,SPI enable" "Not active,Active" bitfld.long 0x00 8. " POWERDOWN ,SPI state machines power down state enable" "Active,Power down" textline " " bitfld.long 0x00 1. " CLKMOD ,Clock mode" "External,Internal" elif (((d.l(ad:0xFFF7FC00+0x04))&0x03)==0x01) group.long 0x04++0x03 line.long 0x00 "GCR1,Global Control Register 1" bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI pin direction determination" "Input/output,Output/input" bitfld.long 0x00 24. " SPIEN ,SPI enable" "Not active,Active" bitfld.long 0x00 8. " POWERDOWN ,SPI state machines power down state enable" "Active,Power down" textline " " bitfld.long 0x00 1. " CLKMOD ,Clock mode" "External,Internal" else group.long 0x04++0x03 line.long 0x00 "GCR1,Global Control Register 1" bitfld.long 0x00 0. " MASTER ,SPISIMO/SPISOMI pin direction determination" "Input/output,Output/input" bitfld.long 0x00 24. " SPIEN ,SPI enable" "Not active,Active" bitfld.long 0x00 8. " POWERDOWN ,SPI state machines power down state enable" "Active,Power down" textline " " bitfld.long 0x00 1. " CLKMOD ,Clock mode" "External,Internal" endif if (((d.l(ad:0xFFF7FC00+0x04))&0x01)==0x01) group.long 0x08++0x03 line.long 0x00 "INT0,Interrupt Register" bitfld.long 0x00 24. " ENABLE_HIGHZ ,/SPIENA pin High-z enable" "Disabled,Enabled" textline " " sif (cpu()!="RM42L432") bitfld.long 0x00 16. " DMA_REQ_EN ,DMA request enable" "Not used,Generated" endif textline " " bitfld.long 0x00 9. " TXINTENA ,Transmit interrupt enable" "Not generated,Generated" bitfld.long 0x00 8. " RXINTENA ,Receive interrupt enable" "Not generated,Generated" textline " " bitfld.long 0x00 6. " RXOVRNINTENA ,Overrun interrupt enable" "Not generated,Generated" bitfld.long 0x00 4. " BITERRENA ,Enables interrupt on bit error" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " DESYNCENA ,Enables interrupt on De-synchronized slave" "Disabled,Enabled" bitfld.long 0x00 2. " PARERRENA ,Enables interrupt on parity error" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " TIMEOUTENA ,Enables interrupt on ENA signal Time-out" "Disabled,Enabled" bitfld.long 0x00 0. " DLEN_ERR_ENA ,Data length error interrupt enable" "Disabled,Enabled" else group.long 0x08++0x03 line.long 0x00 "INT0,Interrupt Register" bitfld.long 0x00 24. " ENABLE_HIGHZ ,/SPIENA pin High-z enable" "Disabled,Enabled" textline " " sif (cpu()!="RM42L432") bitfld.long 0x00 16. " DMA_REQ_EN ,DMA request enable" "Not used,Generated" endif textline " " bitfld.long 0x00 9. " TXINTENA ,Transmit interrupt enable" "Not generated,Generated" bitfld.long 0x00 8. " RXINTENA ,Receive interrupt enable" "Not generated,Generated" textline " " bitfld.long 0x00 6. " RXOVRNINTENA ,Overrun interrupt enable" "Not generated,Generated" bitfld.long 0x00 4. " BITERRENA ,Enables interrupt on bit error" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " PARERRENA ,Enables interrupt on parity error" "Disabled,Enabled" bitfld.long 0x00 1. " TIMEOUTENA ,Enables interrupt on ENA signal Time-out" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " DLEN_ERR_ENA ,Data length error interrupt enable" "Disabled,Enabled" endif if (((d.l(ad:0xFFF7FC00+0x04))&0x01)==0x01) group.long 0x0C++0x03 line.long 0x00 "LVL,Interrupt Level Register" bitfld.long 0x00 9. " TXINTLVL ,Transmit interrupt level" "INT0,INT1" bitfld.long 0x00 8. " RXINTLVL ,Receive interrupt level" "INT0,INT1" bitfld.long 0x00 6. " RXOVRNINTLVL ,Receive overrun interrupt level" "INT0,INT1" textline " " bitfld.long 0x00 4. " BITERRLVL ,Bit error interrupt level" "INT0,INT1" bitfld.long 0x00 3. " DESYNCLVL ,De-synchronized slave interrupt level" "INT0,INT1" bitfld.long 0x00 2. " PARERRLVL ,Parity error interrupt level" "INT0,INT1" textline " " bitfld.long 0x00 1. " TIMEOUTLVL ,/SPIENA pin Time-out interrupt level" "INT0,INT1" bitfld.long 0x00 0. " DLEN_ERR_LVL ,Data length error interrupt enable level" "INT0,INT1" else group.long 0x0C++0x03 line.long 0x00 "LVL,Interrupt Level Register" bitfld.long 0x00 9. " TXINTLVL ,Transmit interrupt level" "INT0,INT1" bitfld.long 0x00 8. " RXINTLVL ,Receive interrupt level" "INT0,INT1" bitfld.long 0x00 6. " RXOVRNINTLVL ,Receive overrun interrupt level" "INT0,INT1" textline " " bitfld.long 0x00 4. " BITERRLVL ,Bit error interrupt level" "INT0,INT1" bitfld.long 0x00 2. " PARERRLVL ,Parity error interrupt level" "INT0,INT1" bitfld.long 0x00 1. " TIMEOUTLVL ,/SPIENA pin Time-out interrupt level" "INT0,INT1" textline " " bitfld.long 0x00 0. " DLEN_ERR_LVL ,Data length error interrupt enable level" "INT0,INT1" endif if (((d.l(ad:0xFFF7FC00+0x04))&0x01)==0x01) group.long 0x10++0x03 line.long 0x00 "FLG,Flag Register" bitfld.long 0x00 24. " BUF_INIT_ACTIVE ,Multibuffer initialization active" "Finished,Not finished" bitfld.long 0x00 9. " TXINTFLG ,Transmitter empty interrupt flag" "Full,Empty" textline " " eventfld.long 0x00 8. " RXINTFLG ,Receiver full interrupt flag" "Empty,Full" eventfld.long 0x00 6. " RXOVRNINTFLG ,Receiver overrun flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 4. " BITERRFLG ,Internal transmit data and transmitted data mismatch" "Not occurred,Occurred" eventfld.long 0x00 3. " DESYNCFLG ,Slave device De-Synchronization" "Not detected,Detected" textline " " eventfld.long 0x00 2. " PARITYERRFLG ,Parity error flag" "Not detected,Detected" eventfld.long 0x00 1. " TIMEOUTFLG ,Time-out due to Non-activation of ENA signal" "Not occurred,Occurred" textline " " eventfld.long 0x00 0. " DLEN_ERR_FLG ,Data length error flag" "Not occurred,Occurred" else group.long 0x10++0x03 line.long 0x00 "FLG,Flag Register" bitfld.long 0x00 24. " BUF_INIT_ACTIVE ,Multibuffer initialization active" "Not completed,Completed" bitfld.long 0x00 9. " TXINTFLG ,Transmitter empty interrupt flag" "No empty,Empty" textline " " eventfld.long 0x00 8. " RXINTFLG ,Receiver full interrupt flag" "No full,Full" eventfld.long 0x00 6. " RXOVRNINTFLG ,Receiver overrun flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 4. " BITERRFLG ,Internal transmit data and transmitted data mismatch" "Not occurred,Occurred" eventfld.long 0x00 2. " PARITYERRFLG ,Parity error flag" "Not occurred,Occurred" textline " " eventfld.long 0x00 1. " TIMEOUTFLG ,Time-out due to Non-activation of ENA signal" "Not occurred,Occurred" eventfld.long 0x00 0. " DLEN_ERR_FLG ,Data length error flag" "Not occurred,Occurred" endif width 13. tree "SPI Pin Control Registers" tree "SPI Pin Control Registers 0-5" group.long 0x14++0x03 line.long 0x00 "PC0,Pin Control Register 0" bitfld.long 0x00 31. " SOMIFUN7 ,Slave out master in function 7" "GPIO,Spi/mibspi" bitfld.long 0x00 30. " SOMIFUN6 ,Slave out master in function 6" "GPIO,Spi/mibspi" bitfld.long 0x00 29. " SOMIFUN5 ,Slave out master in function 5" "GPIO,Spi/mibspi" textline " " bitfld.long 0x00 28. " SOMIFUN4 ,Slave out master in function 4" "GPIO,Spi/mibspi" bitfld.long 0x00 27. " SOMIFUN3 ,Slave out master in function 3" "GPIO,Spi/mibspi" bitfld.long 0x00 26. " SOMIFUN2 ,Slave out master in function 2" "GPIO,Spi/mibspi" textline " " bitfld.long 0x00 25. " SOMIFUN1 ,Slave out master in function 1" "GPIO,Spi/mibspi" bitfld.long 0x00 24. " SOMIFUN0 ,Slave out master in function 0" "GPIO,Spi/mibspi" bitfld.long 0x00 23. " SIMOFUN7 ,Slave in master out function 7" "GPIO,Spi/mibspi" textline " " bitfld.long 0x00 22. " SIMOFUN6 ,Slave in master out function 6" "GPIO,Spi/mibspi" bitfld.long 0x00 21. " SIMOFUN5 ,Slave in master out function 5" "GPIO,Spi/mibspi" bitfld.long 0x00 20. " SIMOFUN4 ,Slave in master out function 4" "GPIO,Spi/mibspi" textline " " bitfld.long 0x00 19. " SIMOFUN3 ,Slave in master out function 3" "GPIO,Spi/mibspi" bitfld.long 0x00 18. " SIMOFUN2 ,Slave in master out function 2" "GPIO,Spi/mibspi" bitfld.long 0x00 17. " SIMOFUN1 ,Slave in master out function 1" "GPIO,Spi/mibspi" textline " " bitfld.long 0x00 16. " SIMOFUN0 ,Slave in master out function 0" "GPIO,Spi/mibspi" bitfld.long 0x00 11. " SOMIFUN0 ,Slave out master in function" "GPIO,Spi/mibspi" bitfld.long 0x00 10. " SIMOFUN0 ,Slave in master out function" "GPIO,Spi/mibspi" textline " " bitfld.long 0x00 9. " CLKFUN ,Spi/mibspi clock function" "GPIO,Spi/mibspi" bitfld.long 0x00 8. " ENAFUN ,/SPIENA function" "GPIO,Spi/mibspi" bitfld.long 0x00 7. " SCSFUN7 ,/SPISCS7 function" "GPIO,SPI" textline " " bitfld.long 0x00 6. " SCSFUN6 ,/SPISCS6 function" "GPIO,SPI" bitfld.long 0x00 5. " SCSFUN5 ,/SPISCS5 function" "GPIO,SPI" bitfld.long 0x00 4. " SCSFUN4 ,/SPISCS4 function" "GPIO,SPI" textline " " bitfld.long 0x00 3. " SCSFUN3 ,/SPISCS3 function" "GPIO,SPI" bitfld.long 0x00 2. " SCSFUN2 ,/SPISCS2 function" "GPIO,SPI" bitfld.long 0x00 1. " SCSFUN1 ,/SPISCS1 function" "GPIO,SPI" textline " " bitfld.long 0x00 0. " SCSFUN0 ,/SPISCS0 function" "GPIO,SPI" group.long 0x18++0x03 line.long 0x00 "PC1,Pin Control Register 1" bitfld.long 0x00 31. " SOMIDIR7 ,SPISOMI7 direction" "Input,Output" bitfld.long 0x00 30. " SOMIDIR6 ,SPISOMI6 direction" "Input,Output" bitfld.long 0x00 29. " SOMIDIR5 ,SPISOMI5 direction" "Input,Output" textline " " bitfld.long 0x00 28. " SOMIDIR4 ,SPISOMI4 direction" "Input,Output" bitfld.long 0x00 27. " SOMIDIR3 ,SPISOMI3 direction" "Input,Output" bitfld.long 0x00 26. " SOMIDIR2 ,SPISOMI2 direction" "Input,Output" textline " " bitfld.long 0x00 25. " SOMIDIR1 ,SPISOMI1 direction" "Input,Output" bitfld.long 0x00 24. " SOMIDIR0 ,SPISOMI0 direction" "Input,Output" bitfld.long 0x00 23. " SIMODIR7 ,SPISIMO7 direction" "Input,Output" textline " " bitfld.long 0x00 22. " SIMODIR6 ,SPISIMO6 direction" "Input,Output" bitfld.long 0x00 21. " SIMODIR5 ,SPISIMO5 direction" "Input,Output" bitfld.long 0x00 20. " SIMODIR4 ,SPISIMO4 direction" "Input,Output" textline " " bitfld.long 0x00 19. " SIMODIR3 ,SPISIMO3 direction" "Input,Output" bitfld.long 0x00 18. " SIMODIR2 ,SPISIMO2 direction" "Input,Output" bitfld.long 0x00 17. " SIMODIR1 ,SPISIMO1 direction" "Input,Output" textline " " bitfld.long 0x00 16. " SIMODIR0 ,SPISIMO0 direction" "Input,Output" bitfld.long 0x00 11. " SOMIDIR0 ,SPISOMI0 direction" "Input,Output" bitfld.long 0x00 10. " SIMODIR0 ,SPISIMO0 direction" "Input,Output" textline " " bitfld.long 0x00 9. " CLKDIR ,SPICLK direction" "Input,Output" bitfld.long 0x00 8. " ENADIR ,/SPIENA direction" "Input,Output" bitfld.long 0x00 7. " SCSDIR7 ,/SPISCS7 direction" "Input,Output" textline " " bitfld.long 0x00 6. " SCSDIR6 ,/SPISCS6 direction" "Input,Output" bitfld.long 0x00 5. " SCSDIR5 ,/SPISCS5 direction" "Input,Output" bitfld.long 0x00 4. " SCSDIR4 ,/SPISCS4 direction" "Input,Output" textline " " bitfld.long 0x00 3. " SCSDIR3 ,/SPISCS3 direction" "Input,Output" bitfld.long 0x00 2. " SCSDIR2 ,/SPISCS2 direction" "Input,Output" bitfld.long 0x00 1. " SCSDIR1 ,/SPISCS1 direction" "Input,Output" textline " " bitfld.long 0x00 0. " SCSDIR0 ,/SPISCS0 direction" "Input,Output" rgroup.long 0x1C++0x03 line.long 0x00 "PC2,Pin Control Register 2" bitfld.long 0x00 31. " SOMIDIN7 ,SPISOMI7 data in" "Low,High" bitfld.long 0x00 30. " SOMIDIN6 ,SPISOMI6 data in" "Low,High" bitfld.long 0x00 29. " SOMIDIN5 ,SPISOMI5 data in" "Low,High" textline " " bitfld.long 0x00 28. " SOMIDIN4 ,SPISOMI4 data in" "Low,High" bitfld.long 0x00 27. " SOMIDIN3 ,SPISOMI3 data in" "Low,High" bitfld.long 0x00 26. " SOMIDIN2 ,SPISOMI2 data in" "Low,High" textline " " bitfld.long 0x00 25. " SOMIDIN1 ,SPISOMI1 data in" "Low,High" bitfld.long 0x00 24. " SOMIDIN0 ,SPISOMI0 data in" "Low,High" bitfld.long 0x00 23. " SIMODIN7 ,SPISIMO7 data in" "Low,High" textline " " bitfld.long 0x00 22. " SIMODIN6 ,SPISIMO6 data in" "Low,High" bitfld.long 0x00 21. " SIMODIN5 ,SPISIMO5 data in" "Low,High" bitfld.long 0x00 20. " SIMODIN4 ,SPISIMO4 data in" "Low,High" textline " " bitfld.long 0x00 19. " SIMODIN3 ,SPISIMO3 data in" "Low,High" bitfld.long 0x00 18. " SIMODIN2 ,SPISIMO2 data in" "Low,High" bitfld.long 0x00 17. " SIMODIN1 ,SPISIMO1 data in" "Low,High" textline " " bitfld.long 0x00 16. " SIMODIN0 ,SPISIMO0 data in" "Low,High" bitfld.long 0x00 11. " SOMIDIN0 ,SPISOMI0 data in" "Low,High" bitfld.long 0x00 10. " SIMODIN0 ,SPISIMO0 data in" "Low,High" textline " " bitfld.long 0x00 9. " CLKDIN ,Clock data in" "Low,High" bitfld.long 0x00 8. " ENADIN ,/SPIENA data in" "Low,High" bitfld.long 0x00 7. " SCSDIN7 ,SPISCS7 data in" "Low,High" textline " " bitfld.long 0x00 6. " SCSDIN6 ,SPISCS6 data in" "Low,High" bitfld.long 0x00 5. " SCSDIN5 ,SPISCS5 data in" "Low,High" bitfld.long 0x00 4. " SCSDIN4 ,SPISCS4 data in" "Low,High" textline " " bitfld.long 0x00 3. " SCSDIN3 ,SPISCS3 data in" "Low,High" bitfld.long 0x00 2. " SCSDIN2 ,SPISCS2 data in" "Low,High" bitfld.long 0x00 1. " SCSDIN1 ,SPISCS1 data in" "Low,High" textline " " bitfld.long 0x00 0. " SCSDIN0 ,SPISCS0 data in" "Low,High" group.long 0x20++0x0B line.long 0x00 "PC3,Pin Control Register 3" bitfld.long 0x00 31. " SOMIDOUT7 ,SPISOMI7 dataout write" "Low,High" bitfld.long 0x00 30. " SOMIDOUT6 ,SPISOMI6 dataout write" "Low,High" textline " " bitfld.long 0x00 29. " SOMIDOUT5 ,SPISOMI5 dataout write" "Low,High" bitfld.long 0x00 28. " SOMIDOUT4 ,SPISOMI4 dataout write" "Low,High" textline " " bitfld.long 0x00 27. " SOMIDOUT3 ,SPISOMI3 dataout write" "Low,High" bitfld.long 0x00 26. " SOMIDOUT2 ,SPISOMI2 dataout write" "Low,High" textline " " bitfld.long 0x00 25. " SOMIDOUT1 ,SPISOMI1 dataout write" "Low,High" bitfld.long 0x00 24. " SOMIDOUT0 ,SPISOMI0 dataout write" "Low,High" textline " " bitfld.long 0x00 23. " SIMODOUT7 ,SPISIMO7 dataout write" "Low,High" bitfld.long 0x00 22. " SIMODOUT6 ,SPISIMO6 dataout write" "Low,High" textline " " bitfld.long 0x00 21. " SIMODOUT5 ,SPISIMO5 dataout write" "Low,High" bitfld.long 0x00 20. " SIMODOUT4 ,SPISIMO4 dataout write" "Low,High" textline " " bitfld.long 0x00 19. " SIMODOUT3 ,SPISIMO3 dataout write" "Low,High" bitfld.long 0x00 18. " SIMODOUT2 ,SPISIMO2 dataout write" "Low,High" textline " " bitfld.long 0x00 17. " SIMODOUT1 ,SPISIMO1 dataout write" "Low,High" bitfld.long 0x00 16. " SIMODOUT0 ,SPISIMO0 dataout write" "Low,High" textline " " bitfld.long 0x00 11. " SOMIDOUT0 ,SPISOMI0 dataout write" "Low,High" bitfld.long 0x00 10. " SIMODOUT0 ,SPISIMO0 dataout write" "Low,High" textline " " bitfld.long 0x00 9. " CLKDOUT ,SPICLK dataout write" "Low,High" bitfld.long 0x00 8. " ENADOUT ,/SPIENA dataout write" "Low,High" textline " " bitfld.long 0x00 7. " SCSDOUT7 ,SPISCS7 dataout write" "Low,High" bitfld.long 0x00 6. " SCSDOUT6 ,SPISCS6 dataout write" "Low,High" textline " " bitfld.long 0x00 5. " SCSDOUT5 ,SPISCS5 dataout write" "Low,High" bitfld.long 0x00 4. " SCSDOUT4 ,SPISCS4 dataout write" "Low,High" textline " " bitfld.long 0x00 3. " SCSDOUT3 ,SPISCS3 dataout write" "Low,High" bitfld.long 0x00 2. " SCSDOUT2 ,SPISCS2 dataout write" "Low,High" textline " " bitfld.long 0x00 1. " SCSDOUT1 ,SPISCS1 dataout write" "Low,High" bitfld.long 0x00 0. " SCSDOUT0 ,SPISCS0 dataout write" "Low,High" line.long 0x04 "PC4,Pin Control Register 4" bitfld.long 0x04 31. " SOMISET7 ,SPISOMI7 dataout set" "Not set,Set" bitfld.long 0x04 30. " SOMISET6 ,SPISOMI6 dataout set" "Not set,Set" textline " " bitfld.long 0x04 29. " SOMISET5 ,SPISOMI5 dataout set" "Not set,Set" bitfld.long 0x04 28. " SOMISET4 ,SPISOMI4 dataout set" "Not set,Set" textline " " bitfld.long 0x04 27. " SOMISET3 ,SPISOMI3 dataout set" "Not set,Set" bitfld.long 0x04 26. " SOMISET2 ,SPISOMI2 dataout set" "Not set,Set" textline " " bitfld.long 0x04 25. " SOMISET1 ,SPISOMI1 dataout set" "Not set,Set" bitfld.long 0x04 24. " SOMISET0 ,SPISOMI0 dataout set" "Not set,Set" textline " " bitfld.long 0x04 23. " SIMOSET7 ,SPISIMO7 dataout set" "Not set,Set" bitfld.long 0x04 22. " SIMOSET6 ,SPISIMO6 dataout set" "Not set,Set" textline " " bitfld.long 0x04 21. " SIMOSET5 ,SPISIMO5 dataout set" "Not set,Set" bitfld.long 0x04 20. " SIMOSET4 ,SPISIMO4 dataout set" "Not set,Set" textline " " bitfld.long 0x04 19. " SIMOSET3 ,SPISIMO3 dataout set" "Not set,Set" bitfld.long 0x04 18. " SIMOSET2 ,SPISIMO2 dataout set" "Not set,Set" textline " " bitfld.long 0x04 17. " SIMOSET1 ,SPISIMO1 dataout set" "Not set,Set" bitfld.long 0x04 16. " SIMOSET0 ,SPISIMO0 dataout set" "Not set,Set" textline " " bitfld.long 0x04 11. " SOMISET0 ,SPISOMI0 dataout set" "Not set,Set" bitfld.long 0x04 10. " SIMOSET0 ,SPISIMO0 dataout set" "Not set,Set" textline " " bitfld.long 0x04 9. " CLKSET ,SPICLK dataout set" "Not set,Set" bitfld.long 0x04 8. " ENASET ,/SPIENA dataout set" "Not set,Set" textline " " bitfld.long 0x04 7. " SCSSET7 ,SPISCS7 dataout set" "Not set,Set" bitfld.long 0x04 6. " SCSSET6 ,SPISCS6 dataout set" "Not set,Set" textline " " bitfld.long 0x04 5. " SCSSET5 ,SPISCS5 dataout set" "Not set,Set" bitfld.long 0x04 4. " SCSSET4 ,SPISCS4 dataout set" "Not set,Set" textline " " bitfld.long 0x04 3. " SCSSET3 ,SPISCS3 dataout set" "Not set,Set" bitfld.long 0x04 2. " SCSSET2 ,SPISCS2 dataout set" "Not set,Set" textline " " bitfld.long 0x04 1. " SCSSET1 ,SPISCS1 dataout set" "Not set,Set" bitfld.long 0x04 0. " SCSSET0 ,SPISCS0 dataout set" "Not set,Set" line.long 0x08 "PC5,Pin Control Register 5" bitfld.long 0x08 31. " SOMICLR7 ,SPISOMI7 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 30. " SOMICLR6 ,SPISOMI6 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 29. " SOMICLR5 ,SPISOMI5 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 28. " SOMICLR4 ,SPISOMI4 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 27. " SOMICLR3 ,SPISOMI3 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 26. " SOMICLR2 ,SPISOMI2 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 25. " SOMICLR1 ,SPISOMI1 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 24. " SOMICLR0 ,SPISOMI0 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 23. " SIMOCLR7 ,SPISIMO7 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 22. " SIMOCLR6 ,SPISIMO6 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 21. " SIMOCLR5 ,SPISIMO5 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 20. " SIMOCLR4 ,SPISIMO4 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 19. " SIMOCLR3 ,SPISIMO3 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 18. " SIMOCLR2 ,SPISIMO2 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 17. " SIMOCLR1 ,SPISIMO1 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 16. " SIMOCLR0 ,SPISIMO0 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 11. " SOMICLR0 ,SPISOMI0 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 10. " SIMOCLR0 ,SPISIMO0 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 9. " CLKCLR ,SPICLK dataout clear" "Not cleared,Cleared" bitfld.long 0x08 8. " ENACLR ,/SPIENA dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 7. " SCSCLR7 ,SPISCS7 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 6. " SCSCLR6 ,SPISCS6 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 5. " SCSCLR5 ,SPISCS5 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 4. " SCSCLR4 ,SPISCS4 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 3. " SCSCLR3 ,SPISCS3 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 2. " SCSCLR2 ,SPISCS2 dataout clear" "Not cleared,Cleared" textline " " bitfld.long 0x08 1. " SCSCLR1 ,SPISCS1 dataout clear" "Not cleared,Cleared" bitfld.long 0x08 0. " SCSCLR0 ,SPISCS0 dataout clear" "Not cleared,Cleared" tree.end tree "SPI Pin Control Registers 6-8" group.long 0x2C++0x03 line.long 0x00 "PC6,Pin Control Register 1" bitfld.long 0x00 31. " SOMIPDR7 ,SPISOMI7 open drain enable" "High,Tri-stated" bitfld.long 0x00 30. " SOMIPDR6 ,SPISOMI6 open drain enable" "High,Tri-stated" bitfld.long 0x00 29. " SOMIPDR5 ,SPISOMI5 open drain enable" "High,Tri-stated" textline " " bitfld.long 0x00 28. " SOMIPDR4 ,SPISOMI4 open drain enable" "High,Tri-stated" bitfld.long 0x00 27. " SOMIPDR3 ,SPISOMI3 open drain enable" "High,Tri-stated" bitfld.long 0x00 26. " SOMIPDR2 ,SPISOMI2 open drain enable" "High,Tri-stated" textline " " bitfld.long 0x00 25. " SOMIPDR1 ,SPISOMI1 open drain enable" "High,Tri-stated" bitfld.long 0x00 24. " SOMIPDR0 ,SPISOMI0 open drain enable" "High,Tri-stated" bitfld.long 0x00 23. " SIMOPDR7 ,SPISIMO7 open drain enable" "High,Tri-stated" textline " " bitfld.long 0x00 22. " SIMOPDR6 ,SPISIMO6 open drain enable" "High,Tri-stated" bitfld.long 0x00 21. " SIMOPDR5 ,SPISIMO5 open drain enable" "High,Tri-stated" bitfld.long 0x00 20. " SIMOPDR4 ,SPISIMO4 open drain enable" "High,Tri-stated" textline " " bitfld.long 0x00 19. " SIMOPDR3 ,SPISIMO3 open drain enable" "High,Tri-stated" bitfld.long 0x00 18. " SIMOPDR2 ,SPISIMO2 open drain enable" "High,Tri-stated" bitfld.long 0x00 17. " SIMOPDR1 ,SPISIMO1 open drain enable" "High,Tri-stated" textline " " bitfld.long 0x00 16. " SIMOPDR0 ,SPISIMO0 open drain enable" "High,Tri-stated" bitfld.long 0x00 11. " SOMIPDR0 ,SPISOMI0 open drain enable" "High,Tri-stated" bitfld.long 0x00 10. " SIMOPDR0 ,SPISIMO0 open drain enable" "High,Tri-stated" textline " " bitfld.long 0x00 9. " CLKPDR ,SPICLK open drain enable" "High,Tri-stated" bitfld.long 0x00 8. " ENAPDR ,/SPIENA open drain enable" "High,Tri-stated" bitfld.long 0x00 7. " SCSPDR7 ,/SPISCS7 open drain" "High,Tri-stated" textline " " bitfld.long 0x00 6. " SCSPDR6 ,/SPISCS6 open drain" "High,Tri-stated" bitfld.long 0x00 5. " SCSPDR5 ,/SPISCS5 open drain" "High,Tri-stated" bitfld.long 0x00 4. " SCSPDR4 ,/SPISCS4 open drain" "High,Tri-stated" textline " " bitfld.long 0x00 3. " SCSPDR3 ,/SPISCS3 open drain" "High,Tri-stated" bitfld.long 0x00 2. " SCSPDR2 ,/SPISCS2 open drain" "High,Tri-stated" bitfld.long 0x00 1. " SCSPDR1 ,/SPISCS1 open drain" "High,Tri-stated" textline " " bitfld.long 0x00 0. " SCSPDR0 ,/SPISCS0 open drain" "High,Tri-stated" group.long 0x30++0x03 line.long 0x00 "PC7,Pin Control Register 7" bitfld.long 0x00 31. " SOMIPDIS7 ,SPISOMI7 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 30. " SOMIPDIS6 ,SPISOMI6 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 29. " SOMIPDIS5 ,SPISOMI5 pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 28. " SOMIPDIS4 ,SPISOMI4 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 27. " SOMIPDIS3 ,SPISOMI3 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 26. " SOMIPDIS2 ,SPISOMI2 pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 25. " SOMIPDIS1 ,SPISOMI1 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 24. " SOMIPDIS0 ,SPISOMI0 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 23. " SIMOPDIS7 ,SPISIMO7 pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 22. " SIMOPDIS6 ,SPISIMO6 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 21. " SIMOPDIS5 ,SPISIMO5 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 20. " SIMOPDIS4 ,SPISIMO4 pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 19. " SIMOPDIS3 ,SPISIMO3 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 18. " SIMOPDIS2 ,SPISIMO2 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 17. " SIMOPDIS1 ,SPISIMO1 pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 16. " SIMOPDIS0 ,SPISIMO0 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 11. " SOMIPDIS0 ,SPISOMI0 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 10. " SIMOPDIS0 ,SPISIMO pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 9. " CLKPDIS ,SPICLK pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 8. " ENAPDIS ,SPIENA pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 7. " SCSPDIS7 ,SPISCS7 pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 6. " SCSPDIS6 ,SPISCS6 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 5. " SCSPDIS5 ,SPISCS5 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 4. " SCSPDIS4 ,SPISCS4 pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 3. " SCSPDIS3 ,SPISCS3 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 2. " SCSPDIS2 ,SPISCS2 pull control enable/disable" "Enabled,Disabled" bitfld.long 0x00 1. " SCSPDIS1 ,SPISCS1 pull control enable/disable" "Enabled,Disabled" textline " " bitfld.long 0x00 0. " SCSPDIS0 ,SPISCS0 pull control enable/disable" "Enabled,Disabled" group.long 0x34++0x03 line.long 0x00 "PC8,Pin Control Register 8" bitfld.long 0x00 31. " SOMIPSEL7 ,SPISOMI7 pull select" "Pull down,Pull up" bitfld.long 0x00 30. " SOMIPSEL6 ,SPISOMI6 pull select" "Pull down,Pull up" bitfld.long 0x00 29. " SOMIPSEL5 ,SPISOMI5 pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 28. " SOMIPSEL4 ,SPISOMI4 pull select" "Pull down,Pull up" bitfld.long 0x00 27. " SOMIPSEL3 ,SPISOMI3 pull select" "Pull down,Pull up" bitfld.long 0x00 26. " SOMIPSEL2 ,SPISOMI2 pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 25. " SOMIPSEL1 ,SPISOMI1 pull select" "Pull down,Pull up" bitfld.long 0x00 24. " SOMIPSEL0 ,SPISOMI0 pull select" "Pull down,Pull up" bitfld.long 0x00 23. " SIMOPSEL7 ,SPISIMO7 pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 22. " SIMOPSEL6 ,SPISIMO6 pull select" "Pull down,Pull up" bitfld.long 0x00 21. " SIMOPSEL5 ,SPISIMO5 pull select" "Pull down,Pull up" bitfld.long 0x00 20. " SIMOPSEL4 ,SPISIMO4 pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 19. " SIMOPSEL3 ,SPISIMO3 pull select" "Pull down,Pull up" bitfld.long 0x00 18. " SIMOPSEL2 ,SPISIMO2 pull select" "Pull down,Pull up" bitfld.long 0x00 17. " SIMOPSEL1 ,SPISIMO1 pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 16. " SIMOPSEL0 ,SPISIMO0 pull select" "Pull down,Pull up" bitfld.long 0x00 11. " SOMIPSEL ,SPISOMI pull select" "Pull down,Pull up" bitfld.long 0x00 10. " SIMOPSEL ,SPISIMO pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 9. " CLKPSEL ,SPICLK pull select" "Pull down,Pull up" bitfld.long 0x00 8. " ENAPSEL ,SPIENA pull select" "Pull down,Pull up" bitfld.long 0x00 7. " SCSPSEL7 ,/SPISCS7 pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 6. " SCSPSEL6 ,/SPISCS6 pull select" "Pull down,Pull up" bitfld.long 0x00 5. " SCSPSEL5 ,/SPISCS5 pull select" "Pull down,Pull up" bitfld.long 0x00 4. " SCSPSEL4 ,/SPISCS4 pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 3. " SCSPSEL3 ,/SPISCS3 pull select" "Pull down,Pull up" bitfld.long 0x00 2. " SCSPSEL2 ,/SPISCS2 pull select" "Pull down,Pull up" bitfld.long 0x00 1. " SCSPSEL1 ,/SPISCS1 pull select" "Pull down,Pull up" textline " " bitfld.long 0x00 0. " SCSPSEL0 ,/SPISCS0 pull select" "Pull down,Pull up" tree.end tree.end width 7. textline " " if (((d.l(ad:0xFFF7FC00+0x04))&0x1000000)==0x1000000) group.long 0x38++0x03 line.long 0x00 "DAT0,Transmit Data Register 0" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI / mibspi transmit data" else rgroup.long 0x38++0x03 line.long 0x00 "DAT0,Transmit Data Register 0" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,SPI / mibspi transmit data" endif if (((d.l(ad:0xFFF7FC00+0x04))&0x01)==0x01) group.long 0x3C++0x03 line.long 0x00 "DAT1,Transmit Data Register 1" bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Not active,Active" bitfld.long 0x00 26. " WDEL ,Enable the delay counter at the end of the current transaction" "Disabled,Enabled" bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" textline " " hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Spi/mibspi transmit data" else group.long 0x3C++0x03 line.long 0x00 "DAT1,Transmit Data Register 1" bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Spi/mibspi transmit data" endif hgroup.long 0x40++0x03 hide.long 0x00 "BUF,Receive Buffer Register" in if (((d.l(ad:0xFFF7FC00+0x04))&0x01)==0x01) rgroup.long 0x44++0x03 line.long 0x00 "EMU,Emulation Register" bitfld.long 0x00 31. " RXEMPTY ,Receive data buffer empty" "No empty,Empty" bitfld.long 0x00 30. " RXOVR ,Receive data buffer overrun" "No overrun,Overrun" bitfld.long 0x00 29. " TXFULL ,Transmit data buffer full" "Empty,Full" textline " " bitfld.long 0x00 28. " BITERR ,Mismatch of internal transmit data and transmitted data" "Not occurred,Occurred" bitfld.long 0x00 27. " DESYNC ,De-synchronization of slave device" "No de-synchronized,De-synchronized" bitfld.long 0x00 26. " PARITYERR ,Calculated parity differs from received parity bit" "No error,Error" textline " " bitfld.long 0x00 25. " TIMEOUT ,Time-out due to Non-activation of ENA pin" "Not occurred,Occurred" bitfld.long 0x00 24. " DLENERR ,Data length error flag" "No error,Error" hexmask.long.byte 0x00 16.--23. 1. " LCSNR ,Last chip select number" textline " " hexmask.long.word 0x00 0.--15. 1. " RXDATA ,SPI receive data" else rgroup.long 0x44++0x03 line.long 0x00 "EMU,Emulation Register" bitfld.long 0x00 31. " RXEMPTY ,Receive data buffer empty" "No empty,Empty" bitfld.long 0x00 30. " RXOVR ,Receive data buffer overrun" "No overrun,Overrun" bitfld.long 0x00 29. " TXFULL ,Transmit data buffer full" "Empty,Full" textline " " bitfld.long 0x00 28. " BITERR ,Mismatch of internal transmit data and transmitted data" "Not occurred,Occurred" bitfld.long 0x00 26. " PARITYERR ,Calculated parity differs from received parity bit" "No error,Error" bitfld.long 0x00 24. " DLENERR ,Data length error flag" "No error,Error" textline " " hexmask.long.byte 0x00 16.--23. 1. " LCSNR ,Last chip select number" hexmask.long.word 0x00 0.--15. 1. " RXDATA ,SPI receive data" endif if (((d.l(ad:0xFFF7FC00+0x04))&0x01)==0x01) group.long 0x48++0x03 line.long 0x00 "DELAY,Delay Register" hexmask.long.byte 0x00 24.--31. 1. " C2TDELAY ,Chip select active to transmit start delay" hexmask.long.byte 0x00 16.--23. 1. " T2CDELAY ,Transmit end to chip select inactive delay" hexmask.long.byte 0x00 8.--15. 1. " T2EDELAY ,Transmit data finished to ENA pin inactive time out" textline " " hexmask.long.byte 0x00 0.--7. 1. " C2EDELAY ,Chip select active to ENA signal active time out" else hgroup.long 0x48++0x03 hide.long 0x00 "DELAY,Delay Register" endif group.long 0x4C++0x03 line.long 0x00 "DEF,Default Chip Select Register" bitfld.long 0x00 7. " CSDEF7 ,Chip select default pattern 7" "Low,High" bitfld.long 0x00 6. " CSDEF6 ,Chip select default pattern 6" "Low,High" bitfld.long 0x00 5. " CSDEF5 ,Chip select default pattern 5" "Low,High" bitfld.long 0x00 4. " CSDEF4 ,Chip select default pattern 4" "Low,High" textline " " bitfld.long 0x00 3. " CSDEF3 ,Chip select default pattern 3" "Low,High" bitfld.long 0x00 2. " CSDEF2 ,Chip select default pattern 2" "Low,High" bitfld.long 0x00 1. " CSDEF1 ,Chip select default pattern 1" "Low,High" bitfld.long 0x00 0. " CSDEF0 ,Chip select default pattern 0" "Low,High" width 6. tree "SPI Data Format Registers" group.long 0x50++0x03 line.long 0x00 "FMT0,Data Format Register 0" bitfld.long 0x00 24.--29. " WDELAY0 ,Delay in between transmissions for data format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " PARPOL0 ,Parity polarity" "Even,Odd" bitfld.long 0x00 22. " PARITY0_ENA ,Parity enable for data format 0" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " WAITENA0 ,Master waits for ENA signal from slave for data format 0" "Not wait,Wait" bitfld.long 0x00 20. " SHIFTDIR0 ,Shift direction for data format 0" "MSB,LSB" bitfld.long 0x00 18. " DIS_CS_TIMERS0 ,Disable chipselect timers for this format register" "No,Yes" textline " " bitfld.long 0x00 17. " POLARITY0 ,SPI data format 0 clock polarity" "Low-inactive,High-inactive" bitfld.long 0x00 16. " PHASE0 ,SPI data format 0 clock delay" "Not delayed,Delayed" hexmask.long.byte 0x00 8.--15. 1. " PRESCALE0 ,SPI data format 0 prescaler" textline " " bitfld.long 0x00 0.--4. " CHARLEN0 ,SPI data format 0 data word length" ",,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..." group.long 0x54++0x03 line.long 0x00 "FMT1,Data Format Register 1" bitfld.long 0x00 24.--29. " WDELAY1 ,Delay in between transmissions for data format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " PARPOL1 ,Parity polarity" "Even,Odd" bitfld.long 0x00 22. " PARITY1_ENA ,Parity enable for data format 1" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " WAITENA1 ,Master waits for ENA signal from slave for data format 1" "Not wait,Wait" bitfld.long 0x00 20. " SHIFTDIR1 ,Shift direction for data format 1" "MSB,LSB" bitfld.long 0x00 18. " DIS_CS_TIMERS1 ,Disable chipselect timers for this format register" "No,Yes" textline " " bitfld.long 0x00 17. " POLARITY1 ,SPI data format 1 clock polarity" "Low-inactive,High-inactive" bitfld.long 0x00 16. " PHASE1 ,SPI data format 1 clock delay" "Not delayed,Delayed" hexmask.long.byte 0x00 8.--15. 1. " PRESCALE1 ,SPI data format 1 prescaler" textline " " bitfld.long 0x00 0.--4. " CHARLEN1 ,SPI data format 1 data word length" ",,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..." group.long 0x58++0x03 line.long 0x00 "FMT2,Data Format Register 2" bitfld.long 0x00 24.--29. " WDELAY2 ,Delay in between transmissions for data format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " PARPOL2 ,Parity polarity" "Even,Odd" bitfld.long 0x00 22. " PARITY2_ENA ,Parity enable for data format 2" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " WAITENA2 ,Master waits for ENA signal from slave for data format 2" "Not wait,Wait" bitfld.long 0x00 20. " SHIFTDIR2 ,Shift direction for data format 2" "MSB,LSB" bitfld.long 0x00 18. " DIS_CS_TIMERS2 ,Disable chipselect timers for this format register" "No,Yes" textline " " bitfld.long 0x00 17. " POLARITY2 ,SPI data format 2 clock polarity" "Low-inactive,High-inactive" bitfld.long 0x00 16. " PHASE2 ,SPI data format 2 clock delay" "Not delayed,Delayed" hexmask.long.byte 0x00 8.--15. 1. " PRESCALE2 ,SPI data format 2 prescaler" textline " " bitfld.long 0x00 0.--4. " CHARLEN2 ,SPI data format 2 data word length" ",,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..." group.long 0x5C++0x03 line.long 0x00 "FMT3,Data Format Register 3" bitfld.long 0x00 24.--29. " WDELAY3 ,Delay in between transmissions for data format" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 23. " PARPOL3 ,Parity polarity" "Even,Odd" bitfld.long 0x00 22. " PARITY3_ENA ,Parity enable for data format 3" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " WAITENA3 ,Master waits for ENA signal from slave for data format 3" "Not wait,Wait" bitfld.long 0x00 20. " SHIFTDIR3 ,Shift direction for data format 3" "MSB,LSB" bitfld.long 0x00 18. " DIS_CS_TIMERS3 ,Disable chipselect timers for this format register" "No,Yes" textline " " bitfld.long 0x00 17. " POLARITY3 ,SPI data format 3 clock polarity" "Low-inactive,High-inactive" bitfld.long 0x00 16. " PHASE3 ,SPI data format 3 clock delay" "Not delayed,Delayed" hexmask.long.byte 0x00 8.--15. 1. " PRESCALE3 ,SPI data format 3 prescaler" textline " " bitfld.long 0x00 0.--4. " CHARLEN3 ,SPI data format 3 data word length" ",,2-bit,3-bit,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,?..." tree.end width 12. tree "SPI Interrupt Vector Registers" if (((d.l(ad:0xFFF7FC00+0x70))&0x01)==0x01) rgroup.long 0x60++0x03 line.long 0x00 "TGINTVECT0,Transfer Group Interrupt Vector Register 0" bitfld.long 0x00 1.--5. " INTVECT0 ,Interrupt vector for interrupt line INT0" "No interrupt,Interrupt of transfer group 0,Interrupt of transfer group 1,Interrupt of transfer group 2,Interrupt of transfer group 3,Interrupt of transfer group 4,Interrupt of transfer group 5,Interrupt of transfer group 6,Interrupt of transfer group 7,Interrupt of transfer group 8,Interrupt of transfer group 9,Interrupt of transfer group 10,Interrupt of transfer group 11,Interrupt of transfer group 12,Interrupt of transfer group 13,Interrupt of transfer group 14,Interrupt of transfer group 15,Interrupt/spiint0,,RXORN interrupt,?..." bitfld.long 0x00 0. " SUSPEND0 ,Transfer suspended/finished interrupt" "Suspended,Finished" else rgroup.long 0x60++0x03 line.long 0x00 "TGINTVECT0,Transfer Group Interrupt Vector Register 0" bitfld.long 0x00 1.--5. " INTVECT0 ,Interrupt vector for interrupt line INT0" "No interrupt,,,,,,,,,,,,,,,,,Interrupt/spiint0,Receive buffer full interrupt,Receive buffer overrun interrupt,Transmit buffer empty interrupt,?..." endif if (((d.l(ad:0xFFF7FC00+0x70))&0x01)==0x01) rgroup.long 0x64++0x03 line.long 0x00 "TGINTVECT1,Transfer Group Interrupt Vector Register 1" bitfld.long 0x00 1.--5. " INTVECT1 ,Interrupt vector for interrupt line INT1" "No interrupt,Interrupt of transfer group 0,Interrupt of transfer group 1,Interrupt of transfer group 2,Interrupt of transfer group 3,Interrupt of transfer group 4,Interrupt of transfer group 5,Interrupt of transfer group 6,Interrupt of transfer group 7,Interrupt of transfer group 8,Interrupt of transfer group 9,Interrupt of transfer group 10,Interrupt of transfer group 11,Interrupt of transfer group 12,Interrupt of transfer group 13,Interrupt of transfer group 14,Interrupt of transfer group 15,Interrupt/spiint1,,RXORN interrupt,?..." bitfld.long 0x00 0. " SUSPEND1 ,Transfer suspended/finished interrupt" "Suspended,Finished" else rgroup.long 0x64++0x03 line.long 0x00 "TGINTVECT1,Transfer Group Interrupt Vector Register 1" bitfld.long 0x00 1.--5. " INTVECT1 ,Interrupt vector for interrupt line INT1" "No interrupt,,,,,,,,,,,,,,,,,Interrupt/spiint1,Receive buffer full interrupt,Receive buffer overrun interrupt,Transmit buffer empty interrupt,?..." endif tree.end width 8. textline " " if (((d.l(ad:0xFFF7FC00+0x3C))&0x3000000)==0x00) group.long 0x6C++0x03 line.long 0x00 "PMCTRL,Parallel/modulo Mode Control Register" bitfld.long 0x00 5. " MOD_CLK_POL_0 ,Modulo mode SPICLK polarity" "Normal,Inverted" bitfld.long 0x00 2.--4. " MMODE_0 ,SPI data line selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..." bitfld.long 0x00 0.--1. " PMODE_0 ,Parallel mode" "1-data,2-data,4-data,8-data" elif (((d.l(ad:0xFFF7FC00+0x3C))&0x3000000)==0x1000000) group.long 0x6C++0x03 line.long 0x00 "PMCTRL,Parallel/modulo Mode Control Register" bitfld.long 0x00 13. " MOD_CLK_POL_1 ,Modulo mode SPICLK polarity" "Normal,Inverted" bitfld.long 0x00 10.--12. " MMODE_1 ,SPI data line selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..." bitfld.long 0x00 8.--9. " PMODE_1 ,Parallel mode" "1-data,2-data,4-data,8-data" elif (((d.l((ad:0xFFF7FC00+0x3C)))&0x3000000)==0x2000000) group.long 0x6C++0x03 line.long 0x00 "PMCTRL,Parallel/modulo Mode Control Register" bitfld.long 0x00 21. " MOD_CLK_POL_2 ,Modulo mode SPICLK polarity" "Normal,Inverted" bitfld.long 0x00 18.--20. " MMODE_2 ,SPI data line selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..." bitfld.long 0x00 16.--17. " PMODE_2 ,Parallel mode" "1-data,2-data,4-data,8-data" else group.long 0x6C++0x03 line.long 0x00 "PMCTRL,Parallel/modulo Mode Control Register" bitfld.long 0x00 29. " MOD_CLK_POL_3 ,Modulo mode SPICLK polarity" "Normal,Inverted" bitfld.long 0x00 26.--28. " MMODE_3 ,SPI data line selection" "1-data,2-data,3-data,4-data,5-data,6-data,?..." bitfld.long 0x00 24.--25. " PMODE_3 ,Parallel mode" "1-data,2-data,4-data,8-data" endif width 11. tree "Mibspi Registers" group.long 0x70++0x03 line.long 0x00 "MIBSPIE,Mibspi Enable Register" bitfld.long 0x00 16. " RX_RAM_ACCESS ,Receive RAM access control bit" "RX not writable,R/W" bitfld.long 0x00 0. " MSPIENA ,Multibuffer mode enable" "Disabled,Enabled" if (((d.l(ad:0xFFF7FC00+0x70))&0x01)==0x01) group.long 0x74++0x03 line.long 0x00 "TGITENST,Mibspi Transfer Group Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTEN_RDY15_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x04 30. " INTEN_RDY14_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 29. 0x00 29. 0x04 29. " INTEN_RDY13_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x04 28. " INTEN_RDY12_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. 0x00 27. 0x04 27. " INTEN_RDY11_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x04 26. " INTEN_RDY10_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x04 25. " INTEN_RDY9_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x04 24. " INTEN_RDY8_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 23. 0x00 23. 0x04 23. " INTEN_RDY7_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x04 22. " INTEN_RDY6_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 21. 0x00 21. 0x04 21. " INTEN_RDY5_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x04 20. " INTEN_RDY4_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x04 19. " INTEN_RDY3_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x04 18. " INTEN_RDY2_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. 0x00 17. 0x04 17. " INTEN_RDY1_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x04 16. " INTEN_RDY0_SET/CLR ,Transfer group interrupt enable when transfer finished" "Disabled,Enabled" textline " " setclrfld.long 0x00 15. 0x00 15. 0x04 15. " INTEN_SUS15_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x04 14. " INTEN_SUS14_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x04 13. " INTEN_SUS13_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x04 12. " INTEN_SUS12_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 11. 0x00 11. 0x04 11. " INTEN_SUS11_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x04 10. " INTEN_SUS10_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. 0x00 9. 0x04 9. " INTEN_SUS9_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x04 8. " INTEN_SUS8_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x04 7. " INTEN_SUS7_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x04 6. " INTEN_SUS6_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 5. 0x00 5. 0x04 5. " INTEN_SUS5_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x04 4. " INTEN_SUS4_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 3. 0x00 3. 0x04 3. " INTEN_SUS3_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x04 2. " INTEN_SUS2_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x04 1. " INTEN_SUS1_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " INTEN_SUS0_SET/CLR ,Transfer group interrupt enable when transfer suspended" "Disabled,Enabled" group.long 0x7C++0x03 line.long 0x00 "TGITLVST,Mibspi Transfer Group Interrupt Level Set Register" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " INTLVL_RDY15_SET/CLR ,Transfer group completed interrupt level 15" "INT0,INT1" setclrfld.long 0x00 30. 0x00 30. 0x04 30. " INTLVL_RDY14_SET/CLR ,Transfer group completed interrupt level 14" "INT0,INT1" textline " " setclrfld.long 0x00 29. 0x00 29. 0x04 29. " INTLVL_RDY13_SET/CLR ,Transfer group completed interrupt level 13" "INT0,INT1" setclrfld.long 0x00 28. 0x00 28. 0x04 28. " INTLVL_RDY12_SET/CLR ,Transfer group completed interrupt level 12" "INT0,INT1" textline " " setclrfld.long 0x00 27. 0x00 27. 0x04 27. " INTLVL_RDY11_SET/CLR ,Transfer group completed interrupt level 11" "INT0,INT1" setclrfld.long 0x00 26. 0x00 26. 0x04 26. " INTLVL_RDY10_SET/CLR ,Transfer group completed interrupt level 10" "INT0,INT1" textline " " setclrfld.long 0x00 25. 0x00 25. 0x04 25. " INTLVL_RDY9_SET/CLR ,Transfer group completed interrupt level set 9" "INT0,INT1" setclrfld.long 0x00 24. 0x00 24. 0x04 24. " INTLVL_RDY8_SET/CLR ,Transfer group completed interrupt level set 8" "INT0,INT1" textline " " setclrfld.long 0x00 23. 0x00 23. 0x04 23. " INTLVL_RDY7_SET/CLR ,Transfer group completed interrupt level set 7" "INT0,INT1" setclrfld.long 0x00 22. 0x00 22. 0x04 22. " INTLVL_RDY6_SET/CLR ,Transfer group completed interrupt level set 6" "INT0,INT1" textline " " setclrfld.long 0x00 21. 0x00 21. 0x04 21. " INTLVL_RDY5_SET/CLR ,Transfer group completed interrupt level set 5" "INT0,INT1" setclrfld.long 0x00 20. 0x00 20. 0x04 20. " INTLVL_RDY4_SET/CLR ,Transfer group completed interrupt level set 4" "INT0,INT1" textline " " setclrfld.long 0x00 19. 0x00 19. 0x04 19. " INTLVL_RDY3_SET/CLR ,Transfer group completed interrupt level set 3" "INT0,INT1" setclrfld.long 0x00 18. 0x00 18. 0x04 18. " INTLVL_RDY2_SET/CLR ,Transfer group completed interrupt level set 2" "INT0,INT1" textline " " setclrfld.long 0x00 17. 0x00 17. 0x04 17. " INTLVL_RDY1_SET/CLR ,Transfer group completed interrupt level set 1" "INT0,INT1" setclrfld.long 0x00 16. 0x00 16. 0x04 16. " INTLVL_RDY0_SET/CLR ,Transfer group completed interrupt level set 0" "INT0,INT1" textline " " setclrfld.long 0x00 15. 0x00 15. 0x04 15. " INTLVL_SUS15_SET/CLR ,Transfer group suspended interrupt level set 15" "INT0,INT1" setclrfld.long 0x00 14. 0x00 14. 0x04 14. " INTLVL_SUS14_SET/CLR ,Transfer group suspended interrupt level set 14" "INT0,INT1" textline " " setclrfld.long 0x00 13. 0x00 13. 0x04 13. " INTLVL_SUS13_SET/CLR ,Transfer group suspended interrupt level set 13" "INT0,INT1" setclrfld.long 0x00 12. 0x00 12. 0x04 12. " INTLVL_SUS12_SET/CLR ,Transfer group suspended interrupt level set 12" "INT0,INT1" textline " " setclrfld.long 0x00 11. 0x00 11. 0x04 11. " INTLVL_SUS11_SET/CLR ,Transfer group suspended interrupt level set 11" "INT0,INT1" setclrfld.long 0x00 10. 0x00 10. 0x04 10. " INTLVL_SUS10_SET/CLR ,Transfer group suspended interrupt level set 10" "INT0,INT1" textline " " setclrfld.long 0x00 9. 0x00 9. 0x04 9. " INTLVL_SUS9_SET/CLR ,Transfer group suspended interrupt level set 9" "INT0,INT1" setclrfld.long 0x00 8. 0x00 8. 0x04 8. " INTLVL_SUS8_SET/CLR ,Transfer group suspended interrupt level set 8" "INT0,INT1" textline " " setclrfld.long 0x00 7. 0x00 7. 0x04 7. " INTLVL_SUS7_SET/CLR ,Transfer group suspended interrupt level set 7" "INT0,INT1" setclrfld.long 0x00 6. 0x00 6. 0x04 6. " INTLVL_SUS6_SET/CLR ,Transfer group suspended interrupt level set 6" "INT0,INT1" textline " " setclrfld.long 0x00 5. 0x00 5. 0x04 5. " INTLVL_SUS5_SET/CLR ,Transfer group suspended interrupt level set 5" "INT0,INT1" setclrfld.long 0x00 4. 0x00 4. 0x04 4. " INTLVL_SUS4_SET/CLR ,Transfer group suspended interrupt level set 4" "INT0,INT1" textline " " setclrfld.long 0x00 3. 0x00 3. 0x04 3. " INTLVL_SUS3_SET/CLR ,Transfer group suspended interrupt level set 3" "INT0,INT1" setclrfld.long 0x00 2. 0x00 2. 0x04 2. " INTLVL_SUS2_SET/CLR ,Transfer group suspended interrupt level set 2" "INT0,INT1" textline " " setclrfld.long 0x00 1. 0x00 1. 0x04 1. " INTLVL_SUS1_SET/CLR ,Transfer group suspended interrupt level set 1" "INT0,INT1" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " INTLVL_SUS0_SET/CLR ,Transfer group suspended interrupt level set 0" "INT0,INT1" group.long 0x84++0x03 line.long 0x00 "TGINTFLAG,Transfer Group Interrupt Flag Register" eventfld.long 0x00 31. " INTFLGRDY15 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" eventfld.long 0x00 30. " INTFLGRDY14 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 29. " INTFLGRDY13 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" eventfld.long 0x00 28. " INTFLGRDY12 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 27. " INTFLGRDY11 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" eventfld.long 0x00 26. " INTFLGRDY10 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 25. " INTFLGRDY9 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" eventfld.long 0x00 24. " INTFLGRDY8 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 23. " INTFLGRDY7 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" eventfld.long 0x00 22. " INTFLGRDY6 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 21. " INTFLGRDY5 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" eventfld.long 0x00 20. " INTFLGRDY4 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 19. " INTFLGRDY3 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" eventfld.long 0x00 18. " INTFLGRDY2 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 17. " INTFLGRDY1 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" eventfld.long 0x00 16. " INTFLGRDY0 ,Transfer group interrupt flag for transfer finished interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 15. " INTFLGSUS15 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" eventfld.long 0x00 14. " INTFLGSUS14 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 13. " INTFLGSUS13 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" eventfld.long 0x00 12. " INTFLGSUS12 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 11. " INTFLGSUS11 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" eventfld.long 0x00 10. " INTFLGSUS10 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 9. " INTFLGSUS9 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" eventfld.long 0x00 8. " INTFLGSUS8 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 7. " INTFLGSUS7 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" eventfld.long 0x00 6. " INTFLGSUS6 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 5. " INTFLGSUS5 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" eventfld.long 0x00 4. " INTFLGSUS4 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " INTFLGSUS3 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" eventfld.long 0x00 2. " INTFLGSUS2 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 1. " INTFLGSUS1 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " INTFLGSUS0 ,Transfer group interrupt flag for transfer suspend interrupt" "No interrupt,Interrupt" group.long 0x90++0x03 line.long 0x00 "TICKCNT,Tick Count Register" bitfld.long 0x00 31. " TICKENA ,Tick counter enable" "Disabled,Enabled" bitfld.long 0x00 30. " RELOAD ,Re-load tick counter" "No effect,Reload" textline " " bitfld.long 0x00 28.--29. " CLKCTRL ,Tick counter clock source control" "Format 0,Format 1,Format 2,Format 3" hexmask.long.word 0x00 0.--15. 1. " TICKVALUE ,Initial value for tick counter" group.long 0x94++0x03 line.long 0x00 "LTGPEND,Last Transfer Group End Pointer" bitfld.long 0x00 24.--28. " TG_IN_SERVICE ,Transfer group currently being serviced by the sequencer" "Not serviced,Group0,Group1,Group2,Group3,Group4,Group5,Group6,Group7,Group8,Group9,Group10,Group11,Group12,Group13,Group14,Group15,?..." hexmask.long.byte 0x00 8.--14. 1. " LPEND ,Last transfer group end pointer" else hgroup.long 0x74++0x03 hide.long 0x00 "TGITENST,Mibspi Transfer Group Interrupt Enable Register" hgroup.long 0x7C++0x03 hide.long 0x00 "TGITLVST,Mibspi Transfer Group Interrupt Level Register" hgroup.long 0x84++0x03 hide.long 0x00 "TGINTFLAG,Transfer Group Interrupt Flag Register" hgroup.long 0x90++0x03 hide.long 0x00 "TICKCNT,Tick Count Register" hgroup.long 0x94++0x03 hide.long 0x00 "LTGPEND,Last Transfer Group End Pointer" endif width 20. tree "Mibspi Transfer Group Control Registers" if (((d.l(ad:0xFFF7FC00+0x70))&0x01)==0x01) group.long 0x98++0x03 line.long 0x00 "TG0CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA0 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT0 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST0 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD0 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT0 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC0 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART0 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT0 ,Transfer group pointer to current buffer" group.long 0x9C++0x03 line.long 0x00 "TG1CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA1 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT1 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST1 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD1 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT1 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC1 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART1 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT1 ,Transfer group pointer to current buffer" group.long 0xA0++0x03 line.long 0x00 "TG2CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA2 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT2 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST2 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD2 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT2 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC2 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART2 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT2 ,Transfer group pointer to current buffer" group.long 0xA4++0x03 line.long 0x00 "TG3CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA3 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT3 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST3 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD3 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT3 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC3 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART3 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT3 ,Transfer group pointer to current buffer" group.long 0xA8++0x03 line.long 0x00 "TG4CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA4 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT4 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST4 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD4 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT4 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC4 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART4 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT4 ,Transfer group pointer to current buffer" group.long 0xAC++0x03 line.long 0x00 "TG5CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA5 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT5 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST5 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD5 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT5 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC5 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART5 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT5 ,Transfer group pointer to current buffer" group.long 0xB0++0x03 line.long 0x00 "TG6CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA6 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT6 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST6 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD6 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT6 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC6 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART6 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT6 ,Transfer group pointer to current buffer" group.long 0xB4++0x03 line.long 0x00 "TG7CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA7 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT7 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST7 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD7 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT7 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC7 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART7 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT7 ,Transfer group pointer to current buffer" group.long 0xB8++0x03 line.long 0x00 "TG8CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA8 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT8 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST8 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD8 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT8 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC8 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART8 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT8 ,Transfer group pointer to current buffer" group.long 0xBC++0x03 line.long 0x00 "TG9CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA9 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT9 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST9 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD9 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT9 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC9 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART9 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT9 ,Transfer group pointer to current buffer" group.long 0xC0++0x03 line.long 0x00 "TG10CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA10 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT10 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST10 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD10 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT10 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC10 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART10 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT10 ,Transfer group pointer to current buffer" group.long 0xC4++0x03 line.long 0x00 "TG11CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA11 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT11 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST11 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD11 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT11 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC11 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART11 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT11 ,Transfer group pointer to current buffer" group.long 0xC8++0x03 line.long 0x00 "TG12CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA12 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT12 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST12 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD12 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT12 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC12 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART12 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT12 ,Transfer group pointer to current buffer" group.long 0xCC++0x03 line.long 0x00 "TG13CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA13 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT13 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST13 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD13 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT13 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC13 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART13 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT13 ,Transfer group pointer to current buffer" group.long 0xD0++0x03 line.long 0x00 "TG14CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA14 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT14 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST14 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD14 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT14 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC14 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART14 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT14 ,Transfer group pointer to current buffer" group.long 0xD4++0x03 line.long 0x00 "TG15CTRL,Mibspi Transfer Group Control Register" bitfld.long 0x00 31. " TGENA15 ,Transfer group enable" "Disabled,Enabled" bitfld.long 0x00 30. " ONESHOT15 ,Single transfer for this transfer group enable" "Disabled,Enabled" bitfld.long 0x00 29. " PRST15 ,Transfer group pointer reset mode" "No reset,Reset" textline " " bitfld.long 0x00 28. " TGTD15 ,Transfer group triggered" "Not triggered,Triggered" bitfld.long 0x00 20.--23. " TRIGEVT15 ,Type of trigger event" "Never,Rising edge,Falling edge,Both edges,,High,Low,Always,?..." bitfld.long 0x00 16.--19. " TRIGSRC15 ,Trigger source" "Disabled,EXT0,EXT1,EXT2,EXT3,EXT4,EXT5,EXT6,EXT7,EXT8,EXT9,EXT10,EXT11,EXT12,EXT13,TICK" textline " " hexmask.long.byte 0x00 8.--14. 1. " PSTART15 ,Transfer group start address" hexmask.long.byte 0x00 0.--6. 1. " PCURRENT15 ,Transfer group pointer to current buffer" else hgroup.long 0x98++0x03 hide.long 0x00 "TG0CTRL,Mibspi Transfer Group Control Register" hgroup.long 0x9C++0x03 hide.long 0x00 "TG1CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xA0++0x03 hide.long 0x00 "TG2CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xA4++0x03 hide.long 0x00 "TG3CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xA8++0x03 hide.long 0x00 "TG4CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xAC++0x03 hide.long 0x00 "TG5CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xB0++0x03 hide.long 0x00 "TG6CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xB4++0x03 hide.long 0x00 "TG7CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xB8++0x03 hide.long 0x00 "TG8CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xBC++0x03 hide.long 0x00 "TG9CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xC0++0x03 hide.long 0x00 "TG10CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xC4++0x03 hide.long 0x00 "TG11CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xC8++0x03 hide.long 0x00 "TG12CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xCC++0x03 hide.long 0x00 "TG13CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xD0++0x03 hide.long 0x00 "TG14CTRL,Mibspi Transfer Group Control Register" hgroup.long 0xD4++0x03 hide.long 0x00 "TG15CTRL,Mibspi Transfer Group Control Register" endif tree.end textline " " sif (cpu()!="RM42L432") if ((((d.l(ad:0xFFF7FC00+0x04))&0x01)==0x01)&&((d.l(ad:0xFFF7FC00+0x70))&0x01)==0x01) group.long 0xD8++0x03 line.long 0x00 "DMA0CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT0 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 0" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID0 ,Buffer utilized for DMA transfer 0" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP0 ,Receive data DMA request map 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP0 ,Transmit data DMA channel 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA0 ,Receive data DMA channel enable 0" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA0 ,Transmit data DMA channel enable 0" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK0 ,Non-interleaved DMA block transfer 0" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT0 ,Initial count of DMA transfers 0" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT170 ,The 17th bit of COUNT field of DMA0COUNT register" "Low,High" bitfld.long 0x00 0.--5. " COUNT0 ,Actual number of remaining DMA transfer 0" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l(ad:0xFFF7FC00+0x04))&0x01)==0x00)&&((d.l(ad:0xFFF7FC00+0x70))&0x01)==0x01) group.long 0xD8++0x03 line.long 0x00 "DMA0CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT0 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 0" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID0 ,Buffer utilized for DMA transfer 0" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP0 ,Receive data DMA request map 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP0 ,Transmit data DMA channel 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA0 ,Receive data DMA channel enable 0" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA0 ,Transmit data DMA channel enable 0" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT0 ,Initial count of DMA transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT170 ,The 17th bit of COUNT field of DMA0COUNT register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT0 ,Actual number of remaining DMA transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xD8++0x03 hide.long 0x00 "DMA0CTRL,Mibspi DMA Channel Control Register" endif if ((((d.l(ad:0xFFF7FC00+0x04))&0x01)==0x01)&&((d.l(ad:0xFFF7FC00+0x70))&0x01)==0x01) group.long 0xDC++0x03 line.long 0x00 "DMA1CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT1 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 1" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID1 ,Buffer utilized for DMA transfer 1" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP1 ,Receive data DMA request map 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP1 ,Transmit data DMA channel 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA1 ,Receive data DMA channel enable 1" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA1 ,Transmit data DMA channel enable 1" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK1 ,Non-interleaved DMA block transfer 1" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT1 ,Initial count of DMA transfers 1" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT171 ,The 17th bit of COUNT field of DMA1COUNT register" "Low,High" bitfld.long 0x00 0.--5. " COUNT1 ,Actual number of remaining DMA transfer 1" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l(ad:0xFFF7FC00+0x04))&0x01)==0x00)&&((d.l(ad:0xFFF7FC00+0x70))&0x01)==0x01) group.long 0xDC++0x03 line.long 0x00 "DMA1CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT1 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 1" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID1 ,Buffer utilized for DMA transfer 1" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP1 ,Receive data DMA request map 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP1 ,Transmit data DMA channel 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA1 ,Receive data DMA channel enable 1" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA1 ,Transmit data DMA channel enable 1" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT1 ,Initial count of DMA transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT171 ,The 17th bit of COUNT field of DMA1COUNT register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT1 ,Actual number of remaining DMA transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xDC++0x03 hide.long 0x00 "DMA1CTRL,Mibspi DMA Channel Control Register" endif if ((((d.l(ad:0xFFF7FC00+0x04))&0x01)==0x01)&&((d.l(ad:0xFFF7FC00+0x70))&0x01)==0x01) group.long 0xE0++0x03 line.long 0x00 "DMA2CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT2 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 2" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID2 ,Buffer utilized for DMA transfer 2" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP2 ,Receive data DMA request map 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP2 ,Transmit data DMA channel 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA2 ,Receive data DMA channel enable 2" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA2 ,Transmit data DMA channel enable 2" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK2 ,Non-interleaved DMA block transfer 2" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT2 ,Initial count of DMA transfers 2" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT172 ,The 17th bit of COUNT field of DMA2COUNT register" "Low,High" bitfld.long 0x00 0.--5. " COUNT2 ,Actual number of remaining DMA transfer 2" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l(ad:0xFFF7FC00+0x04))&0x01)==0x00)&&((d.l(ad:0xFFF7FC00+0x70))&0x01)==0x01) group.long 0xE0++0x03 line.long 0x00 "DMA2CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT2 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 2" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID2 ,Buffer utilized for DMA transfer 2" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP2 ,Receive data DMA request map 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP2 ,Transmit data DMA channel 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA2 ,Receive data DMA channel enable 2" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA2 ,Transmit data DMA channel enable 2" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT2 ,Initial count of DMA transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT172 ,The 17th bit of COUNT field of DMA2COUNT register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT2 ,Actual number of remaining DMA transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xE0++0x03 hide.long 0x00 "DMA2CTRL,Mibspi DMA Channel Control Register" endif if ((((d.l(ad:0xFFF7FC00+0x04))&0x01)==0x01)&&((d.l(ad:0xFFF7FC00+0x70))&0x01)==0x01) group.long 0xE4++0x03 line.long 0x00 "DMA3CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT3 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 3" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID3 ,Buffer utilized for DMA transfer 3" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP3 ,Receive data DMA request map 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP3 ,Transmit data DMA channel 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA3 ,Receive data DMA channel enable 3" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA3 ,Transmit data DMA channel enable 3" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK3 ,Non-interleaved DMA block transfer 3" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT3 ,Initial count of DMA transfers 3" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT173 ,The 17th bit of COUNT field of DMA3COUNT register" "Low,High" bitfld.long 0x00 0.--5. " COUNT3 ,Actual number of remaining DMA transfer 3" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l(ad:0xFFF7FC00+0x04))&0x01)==0x00)&&((d.l(ad:0xFFF7FC00+0x70))&0x01)==0x01) group.long 0xE4++0x03 line.long 0x00 "DMA3CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT3 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 3" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID3 ,Buffer utilized for DMA transfer 3" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP3 ,Receive data DMA request map 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP3 ,Transmit data DMA channel 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA3 ,Receive data DMA channel enable 3" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA3 ,Transmit data DMA channel enable 3" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT3 ,Initial count of DMA transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT173 ,The 17th bit of COUNT field of DMA3COUNT register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT3 ,Actual number of remaining DMA transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xE4++0x03 hide.long 0x00 "DMA3CTRL,Mibspi DMA Channel Control Register" endif if ((((d.l(ad:0xFFF7FC00+0x04))&0x01)==0x01)&&((d.l(ad:0xFFF7FC00+0x70))&0x01)==0x01) group.long 0xE8++0x03 line.long 0x00 "DMA4CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT4 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 4" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID4 ,Buffer utilized for DMA transfer 4" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP4 ,Receive data DMA request map 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP4 ,Transmit data DMA channel 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA4 ,Receive data DMA channel enable 4" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA4 ,Transmit data DMA channel enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK4 ,Non-interleaved DMA block transfer 4" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT4 ,Initial count of DMA transfers 4" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT174 ,The 17th bit of COUNT field of DMA4COUNT register" "Low,High" bitfld.long 0x00 0.--5. " COUNT4 ,Actual number of remaining DMA transfer 4" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l(ad:0xFFF7FC00+0x04))&0x01)==0x00)&&((d.l(ad:0xFFF7FC00+0x70))&0x01)==0x01) group.long 0xE8++0x03 line.long 0x00 "DMA4CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT4 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 4" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID4 ,Buffer utilized for DMA transfer 4" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP4 ,Receive data DMA request map 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP4 ,Transmit data DMA channel 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA4 ,Receive data DMA channel enable 4" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA4 ,Transmit data DMA channel enable 4" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT4 ,Initial count of DMA transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT174 ,The 17th bit of COUNT field of DMA4COUNT register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT4 ,Actual number of remaining DMA transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xE8++0x03 hide.long 0x00 "DMA4CTRL,Mibspi DMA Channel Control Register" endif if ((((d.l(ad:0xFFF7FC00+0x04))&0x01)==0x01)&&((d.l(ad:0xFFF7FC00+0x70))&0x01)==0x01) group.long 0xEC++0x03 line.long 0x00 "DMA5CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT5 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 5" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID5 ,Buffer utilized for DMA transfer 5" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP5 ,Receive data DMA request map 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP5 ,Transmit data DMA channel 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA5 ,Receive data DMA channel enable 5" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA5 ,Transmit data DMA channel enable 5" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK5 ,Non-interleaved DMA block transfer 5" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT5 ,Initial count of DMA transfers 5" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT175 ,The 17th bit of COUNT field of DMA5COUNT register" "Low,High" bitfld.long 0x00 0.--5. " COUNT5 ,Actual number of remaining DMA transfer 5" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l(ad:0xFFF7FC00+0x04))&0x01)==0x00)&&((d.l(ad:0xFFF7FC00+0x70))&0x01)==0x01) group.long 0xEC++0x03 line.long 0x00 "DMA5CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT5 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 5" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID5 ,Buffer utilized for DMA transfer 5" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP5 ,Receive data DMA request map 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP5 ,Transmit data DMA channel 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA5 ,Receive data DMA channel enable 5" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA5 ,Transmit data DMA channel enable 5" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT5 ,Initial count of DMA transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT175 ,The 17th bit of COUNT field of DMA5COUNT register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT5 ,Actual number of remaining DMA transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xEC++0x03 hide.long 0x00 "DMA5CTRL,Mibspi DMA Channel Control Register" endif if ((((d.l(ad:0xFFF7FC00+0x04))&0x01)==0x01)&&((d.l(ad:0xFFF7FC00+0x70))&0x01)==0x01) group.long 0xF0++0x03 line.long 0x00 "DMA6CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT6 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 6" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID6 ,Buffer utilized for DMA transfer 6" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP6 ,Receive data DMA request map 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP6 ,Transmit data DMA channel 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA6 ,Receive data DMA channel enable 6" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA6 ,Transmit data DMA channel enable 6" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK6 ,Non-interleaved DMA block transfer 6" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT6 ,Initial count of DMA transfers 6" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT176 ,The 17th bit of COUNT field of DMA6COUNT register" "Low,High" bitfld.long 0x00 0.--5. " COUNT6 ,Actual number of remaining DMA transfer 6" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l(ad:0xFFF7FC00+0x04))&0x01)==0x00)&&((d.l(ad:0xFFF7FC00+0x70))&0x01)==0x01) group.long 0xF0++0x03 line.long 0x00 "DMA6CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT6 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 6" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID6 ,Buffer utilized for DMA transfer 6" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP6 ,Receive data DMA request map 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP6 ,Transmit data DMA channel 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA6 ,Receive data DMA channel enable 6" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA6 ,Transmit data DMA channel enable 6" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT6 ,Initial count of DMA transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT176 ,The 17th bit of COUNT field of DMA6COUNT register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT6 ,Actual number of remaining DMA transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xF0++0x03 hide.long 0x00 "DMA6CTRL,Mibspi DMA Channel Control Register" endif if ((((d.l(ad:0xFFF7FC00+0x04))&0x01)==0x01)&&((d.l(ad:0xFFF7FC00+0x70))&0x01)==0x01) group.long 0xF4++0x03 line.long 0x00 "DMA7CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT7 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 7" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID7 ,Buffer utilized for DMA transfer 7" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP7 ,Receive data DMA request map 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP7 ,Transmit data DMA channel 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA7 ,Receive data DMA channel enable 7" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA7 ,Transmit data DMA channel enable 7" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " NOBRK7 ,Non-interleaved DMA block transfer 7" "Interleaved,Not interleaved" bitfld.long 0x00 8.--12. " ICOUNT7 ,Initial count of DMA transfers 7" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" textline " " bitfld.long 0x00 6. " COUNT_BIT177 ,The 17th bit of COUNT field of DMA7COUNT register" "Low,High" bitfld.long 0x00 0.--5. " COUNT7 ,Actual number of remaining DMA transfer 7" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" elif ((((d.l(ad:0xFFF7FC00+0x04))&0x01)==0x00)&&((d.l(ad:0xFFF7FC00+0x70))&0x01)==0x01) group.long 0xF4++0x03 line.long 0x00 "DMA7CTRL,Mibspi DMA Channel Control Register" bitfld.long 0x00 31. " ONESHOT7 ,Auto-Disable of DMA channel after ICOUNT+1 transfers 7" "Disabled,Enabled" hexmask.long.byte 0x00 24.--30. 1. " BUFID7 ,Buffer utilized for DMA transfer 7" textline " " bitfld.long 0x00 20.--23. " RXDMA_MAP7 ,Receive data DMA request map 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." bitfld.long 0x00 16.--19. " TXDMA_MAP7 ,Transmit data DMA channel 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,?..." textline " " bitfld.long 0x00 15. " RXDMAENA7 ,Receive data DMA channel enable 7" "Disabled,Enabled" bitfld.long 0x00 14. " TXDMAENA7 ,Transmit data DMA channel enable 7" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--12. " ICOUNT7 ,Initial count of DMA transfers" "1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers" bitfld.long 0x00 6. " COUNT_BIT177 ,The 17th bit of COUNT field of DMA7COUNT register" "Low,High" textline " " bitfld.long 0x00 0.--5. " COUNT7 ,Actual number of remaining DMA transfer" "No transfer,1 transfer,2 transfers,3 transfers,4 transfers,5 transfers,6 transfers,7 transfers,8 transfers,9 transfers,10 transfers,11 transfers,12 transfers,13 transfers,14 transfers,15 transfers,16 transfers,17 transfers,18 transfers,19 transfers,20 transfers,21 transfers,22 transfers,23 transfers,24 transfers,25 transfers,26 transfers,27 transfers,28 transfers,29 transfers,30 transfers,31 transfers,32 transfers,33 transfers,34 transfers,35 transfers,36 transfers,37 transfers,38 transfers,39 transfers,40 transfers,41 transfers,42 transfers,43 transfers,44 transfers,45 transfers,46 transfers,47 transfers,48 transfers,49 transfers,50 transfers,51 transfers,52 transfers,53 transfers,54 transfers,55 transfers,56 transfers,57 transfers,58 transfers,59 transfers,60 transfers,61 transfers,62 transfers,63 transfers" else hgroup.long 0xF4++0x03 hide.long 0x00 "DMA7CTRL,Mibspi DMA Channel Control Register" endif if (((d.l(ad:0xFFF7FC00+0x70))&0x01)==0x01) group.long 0xF8++0x03 line.long 0x00 "DMA0COUNT,ICOUNT Register 0" hexmask.long.word 0x00 16.--31. 1. " ICOUNT0 ,Initial number of DMA transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT0 ,Actual number of remaining DMA transfer" else hgroup.long 0xF8++0x03 hide.long 0x00 "DMA0COUNT,ICOUNT Register 0" endif if (((d.l(ad:0xFFF7FC00+0x70))&0x01)==0x01) group.long 0xFC++0x03 line.long 0x00 "DMA1COUNT,ICOUNT Register 1" hexmask.long.word 0x00 16.--31. 1. " ICOUNT1 ,Initial number of DMA transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT1 ,Actual number of remaining DMA transfer" else hgroup.long 0xFC++0x03 hide.long 0x00 "DMA1COUNT,ICOUNT Register 1" endif if (((d.l(ad:0xFFF7FC00+0x70))&0x01)==0x01) group.long 0x100++0x03 line.long 0x00 "DMA2COUNT,ICOUNT Register 2" hexmask.long.word 0x00 16.--31. 1. " ICOUNT2 ,Initial number of DMA transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT2 ,Actual number of remaining DMA transfer" else hgroup.long 0x100++0x03 hide.long 0x00 "DMA2COUNT,ICOUNT Register 2" endif if (((d.l(ad:0xFFF7FC00+0x70))&0x01)==0x01) group.long 0x104++0x03 line.long 0x00 "DMA3COUNT,ICOUNT Register 3" hexmask.long.word 0x00 16.--31. 1. " ICOUNT3 ,Initial number of DMA transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT3 ,Actual number of remaining DMA transfer" else hgroup.long 0x104++0x03 hide.long 0x00 "DMA3COUNT,ICOUNT Register 3" endif if (((d.l(ad:0xFFF7FC00+0x70))&0x01)==0x01) group.long 0x108++0x03 line.long 0x00 "DMA4COUNT,ICOUNT Register 4" hexmask.long.word 0x00 16.--31. 1. " ICOUNT4 ,Initial number of DMA transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT4 ,Actual number of remaining DMA transfer" else hgroup.long 0x108++0x03 hide.long 0x00 "DMA4COUNT,ICOUNT Register 4" endif if (((d.l(ad:0xFFF7FC00+0x70))&0x01)==0x01) group.long 0x10C++0x03 line.long 0x00 "DMA5COUNT,ICOUNT Register 5" hexmask.long.word 0x00 16.--31. 1. " ICOUNT5 ,Initial number of DMA transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT5 ,Actual number of remaining DMA transfer" else hgroup.long 0x10C++0x03 hide.long 0x00 "DMA5COUNT,ICOUNT Register 5" endif if (((d.l(ad:0xFFF7FC00+0x70))&0x01)==0x01) group.long 0x110++0x03 line.long 0x00 "DMA6COUNT,ICOUNT Register 6" hexmask.long.word 0x00 16.--31. 1. " ICOUNT6 ,Initial number of DMA transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT6 ,Actual number of remaining DMA transfer" else hgroup.long 0x110++0x03 hide.long 0x00 "DMA6COUNT,ICOUNT Register 6" endif if (((d.l(ad:0xFFF7FC00+0x70))&0x01)==0x01) group.long 0x114++0x03 line.long 0x00 "DMA7COUNT,ICOUNT Register 7" hexmask.long.word 0x00 16.--31. 1. " ICOUNT7 ,Initial number of DMA transfers" hexmask.long.word 0x00 0.--15. 1. " COUNT7 ,Actual number of remaining DMA transfer" else hgroup.long 0x114++0x03 hide.long 0x00 "DMA7COUNT,ICOUNT Register 7" endif endif textline " " if (((d.l(ad:0xFFF7FC00+0x70))&0x01)==0x01) sif (cpu()!="RM42L432") group.long 0x118++0x03 line.long 0x00 "DMACNTLEN,DMA LARGE COUNT Register" bitfld.long 0x00 0. " LARGE_COUNT ,Large count" "Modified,Not modified" endif group.long 0x120++0x03 line.long 0x00 "UERRCTRL,Uncorrectable Parity Error Control Register" sif cpuis("RM57L843-ZWT") bitfld.long 0x00 24.--27. " SBE_EVT_EN ,Single bit error event enable" ",,,,,Disabled,,,,,Enabled,?..." bitfld.long 0x00 16.--19. " EDAC_MODE ,These bits determine whether single bit errors (Sbe) detected by the SECDED block will be corrected or not" ",,,,,Disabled,,,,,Enabled,?..." textline " " endif bitfld.long 0x00 8. " PTESTEN ,Parity memory test enable" "Disabled,Enabled" bitfld.long 0x00 0.--3. " EDEN ,Error detection enable" "Enabled,Enabled,Enabled,Enabled,Enabled,Disabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled,Enabled" hgroup.long 0x124++0x03 hide.long 0x00 "UERRSTAT,Uncorrectable Parity Error Status Register" in hgroup.long 0x128++0x03 hide.long 0x00 "UERRADDR1,Uncorrectable Parity Error Address Register" in hgroup.long 0x12C++0x03 hide.long 0x00 "UERRADDR0,Uncorrectable Parity Error Address Register" in hgroup.long 0x130++0x03 hide.long 0x00 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register" in else hgroup.long 0x118++0x03 hide.long 0x00 "DMACNTLEN,DMA LARGE COUNT Register" hgroup.long 0x120++0x03 hide.long 0x00 "UERRCTRL,Uncorrectable Parity Error Control Register" hgroup.long 0x124++0x03 hide.long 0x00 "UERRSTAT,Uncorrectable Parity Error Status Register" hgroup.long 0x128++0x03 hide.long 0x00 "UERRADDR1,Uncorrectable Parity Error Address Register" hgroup.long 0x12C++0x03 hide.long 0x00 "UERRADDR0,Uncorrectable Parity Error Address Register" hgroup.long 0x130++0x03 hide.long 0x00 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register" endif tree.end textline " " if ((((d.l(ad:0xFFF7FC00+0x134))&0xF00)==0xA00)&&(((d.l(ad:0xFFF7FC00+0x134))&0x02)==0x02)) group.long 0x134++0x03 line.long 0x00 "IOLPBKTSTCR,Spi/mibspi IO Loopback Test Control Register" bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" eventfld.long 0x00 24. " SCS_FAIL_FLG ,Analog loopback /SPISCS pin compare failure" "Not failed,Failed" textline " " bitfld.long 0x00 20. " CTRL_BITERR ,Inducing of BITERR during IO loopback test mode control" "Not affected,Flipped" bitfld.long 0x00 19. " CTRL_DESYNC ,Inducing of DESYNC error during IO loopback test mode control" "Not affected,Forced to 0" textline " " bitfld.long 0x00 18. " CTRL_PARERR ,Inducing of parity error during IO loopback test mode control" "Not affected,Flipped" bitfld.long 0x00 17. " CTRL_TIMEOUT ,Inducing of TIMEOUT error during IO loopback test mode control" "Not affected,Forced to 1" textline " " bitfld.long 0x00 16. " CTRL_DLENERR ,Inducing of data length error during IO loopback test mode control" "Not affected,Forced to 1" bitfld.long 0x00 3.--5. " ERR_SCS_PIN ,Error on chip select pin injection" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]" textline " " bitfld.long 0x00 2. " CTRL_SCS_PIN_ERR ,/SPISCS[7:0] pins error injection enable control" "Disabled,Enabled" bitfld.long 0x00 1. " LPBK_TYPE ,Module IO loopback type" "Digital,Analog" textline " " bitfld.long 0x00 0. " RXP_ENA ,Module analog loopback through receive pin enable" "Transmit,Receive" elif ((((d.l(ad:0xFFF7FC00+0x134))&0xF00)==0xA00)&&(((d.l(ad:0xFFF7FC00+0x134))&0x02)==0x00)) group.long 0x134++0x03 line.long 0x00 "IOLPBKTSTCR,Spi/mibspi IO Loopback Test Control Register" bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" eventfld.long 0x00 24. " SCS_FAIL_FLG ,Analog loopback /SPISCS pin compare failure" "Not failed,Failed" textline " " bitfld.long 0x00 20. " CTRL_BITERR ,Inducing of BITERR during IO loopback test mode control" "Not affected,Flipped" bitfld.long 0x00 19. " CTRL_DESYNC ,Inducing of DESYNC error during IO loopback test mode control" "Not affected,Forced to 0" textline " " bitfld.long 0x00 18. " CTRL_PARERR ,Inducing of parity error during IO loopback test mode control" "Not affected,Flipped" bitfld.long 0x00 17. " CTRL_TIMEOUT ,Inducing of TIMEOUT error during IO loopback test mode control" "Not affected,Forced to 1" textline " " bitfld.long 0x00 16. " CTRL_DLENERR ,Inducing of data length error during IO loopback test mode control" "Not affected,Forced to 1" bitfld.long 0x00 3.--5. " ERR_SCS_PIN ,Error on chip select pin injection" "/SPISCS[0],/SPISCS[1],/SPISCS[2],/SPISCS[3],/SPISCS[4],/SPISCS[5],/SPISCS[6],/SPISCS[7]" textline " " bitfld.long 0x00 2. " CTRL_SCS_PIN_ERR ,/SPISCS[7:0] pins error injection enable control" "Disabled,Enabled" bitfld.long 0x00 1. " LPBK_TYPE ,Module IO loopback type" "Digital,Analog" else group.long 0x134++0x03 line.long 0x00 "IOLPBKTSTCR,Spi/mibspi IO Loopback Test Control Register" bitfld.long 0x00 8.--11. " IOLPBKTSTENA ,Module I/O loopback test enable key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" endif sif (cpuis("RM46L*")||cpu()=="RM42L432"||cpuis("RM57L843-ZWT")) group.long 0x138++0x07 line.long 0x00 "EXTENDED_PRESCALE1,SPI Extended Prescale Register 1" hexmask.long.word 0x00 16.--26. 1. " EPRESCALE_FMT1 ,Extended prescale value for SPIFMT1" hexmask.long.word 0x00 0.--10. 1. " EPRESCALE_FMT0 ,Extended prescale value for SPIFMT0" line.long 0x04 "EXTENDED_PRESCALE2,SPI Extended Prescale Register 2" hexmask.long.word 0x04 16.--26. 1. " EPRESCALE_FMT3 ,Extended prescale value for SPIFMT1" hexmask.long.word 0x04 0.--10. 1. " EPRESCALE_FMT2 ,Extended prescale value for SPIFMT0" endif sif cpuis("RM57L843-ZWT") group.long 0x140++0x07 line.long 0x00 "ECCDIAG_CTRL,ECC Diagnostic Control Register" bitfld.long 0x00 0.--3. " ECCDIAG_EN ,ECC diagnostic mode enable key bits" "Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled" line.long 0x04 "ECCDIAG_STAT,ECC Diagnostic Status Register" eventfld.long 0x04 17. " DEFLG[1] ,Double bit error flag" "No error,Error" eventfld.long 0x04 16. " DEFLG[0] ,Double bit error flag" "No error,Error" textline " " eventfld.long 0x04 1. " SEFLG[1] ,Single bit error flag" "No error,Error" eventfld.long 0x04 0. " SEFLG[0] ,Single bit error flag" "No error,Error" hgroup.long 0x148++0x07 hide.long 0x00 "SBERRADDR1,Single Bit Error Address Register - RXRAM" in hide.long 0x04 "SBERRADDR0,Single Bit Error Address Register - TXRAM" endif width 0x0B tree "Multi-Buffer RAM" base ad:0xFF0E0000 width 10. tree "Multi-buffer RAM Transmit Data Registers" group.long 0x0++0x03 line.long 0x00 "TXRAM0,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x4++0x03 line.long 0x00 "TXRAM1,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x8++0x03 line.long 0x00 "TXRAM2,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xC++0x03 line.long 0x00 "TXRAM3,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x10++0x03 line.long 0x00 "TXRAM4,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x14++0x03 line.long 0x00 "TXRAM5,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x18++0x03 line.long 0x00 "TXRAM6,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1C++0x03 line.long 0x00 "TXRAM7,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x20++0x03 line.long 0x00 "TXRAM8,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x24++0x03 line.long 0x00 "TXRAM9,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x28++0x03 line.long 0x00 "TXRAM10,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x2C++0x03 line.long 0x00 "TXRAM11,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x30++0x03 line.long 0x00 "TXRAM12,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x34++0x03 line.long 0x00 "TXRAM13,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x38++0x03 line.long 0x00 "TXRAM14,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x3C++0x03 line.long 0x00 "TXRAM15,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x40++0x03 line.long 0x00 "TXRAM16,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x44++0x03 line.long 0x00 "TXRAM17,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x48++0x03 line.long 0x00 "TXRAM18,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x4C++0x03 line.long 0x00 "TXRAM19,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x50++0x03 line.long 0x00 "TXRAM20,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x54++0x03 line.long 0x00 "TXRAM21,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x58++0x03 line.long 0x00 "TXRAM22,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x5C++0x03 line.long 0x00 "TXRAM23,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x60++0x03 line.long 0x00 "TXRAM24,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x64++0x03 line.long 0x00 "TXRAM25,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x68++0x03 line.long 0x00 "TXRAM26,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x6C++0x03 line.long 0x00 "TXRAM27,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x70++0x03 line.long 0x00 "TXRAM28,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x74++0x03 line.long 0x00 "TXRAM29,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x78++0x03 line.long 0x00 "TXRAM30,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x7C++0x03 line.long 0x00 "TXRAM31,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x80++0x03 line.long 0x00 "TXRAM32,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x84++0x03 line.long 0x00 "TXRAM33,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x88++0x03 line.long 0x00 "TXRAM34,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x8C++0x03 line.long 0x00 "TXRAM35,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x90++0x03 line.long 0x00 "TXRAM36,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x94++0x03 line.long 0x00 "TXRAM37,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x98++0x03 line.long 0x00 "TXRAM38,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x9C++0x03 line.long 0x00 "TXRAM39,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xA0++0x03 line.long 0x00 "TXRAM40,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xA4++0x03 line.long 0x00 "TXRAM41,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xA8++0x03 line.long 0x00 "TXRAM42,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xAC++0x03 line.long 0x00 "TXRAM43,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xB0++0x03 line.long 0x00 "TXRAM44,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xB4++0x03 line.long 0x00 "TXRAM45,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xB8++0x03 line.long 0x00 "TXRAM46,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xBC++0x03 line.long 0x00 "TXRAM47,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xC0++0x03 line.long 0x00 "TXRAM48,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xC4++0x03 line.long 0x00 "TXRAM49,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xC8++0x03 line.long 0x00 "TXRAM50,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xCC++0x03 line.long 0x00 "TXRAM51,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xD0++0x03 line.long 0x00 "TXRAM52,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xD4++0x03 line.long 0x00 "TXRAM53,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xD8++0x03 line.long 0x00 "TXRAM54,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xDC++0x03 line.long 0x00 "TXRAM55,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xE0++0x03 line.long 0x00 "TXRAM56,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xE4++0x03 line.long 0x00 "TXRAM57,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xE8++0x03 line.long 0x00 "TXRAM58,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xEC++0x03 line.long 0x00 "TXRAM59,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xF0++0x03 line.long 0x00 "TXRAM60,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xF4++0x03 line.long 0x00 "TXRAM61,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xF8++0x03 line.long 0x00 "TXRAM62,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0xFC++0x03 line.long 0x00 "TXRAM63,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x100++0x03 line.long 0x00 "TXRAM64,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x104++0x03 line.long 0x00 "TXRAM65,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x108++0x03 line.long 0x00 "TXRAM66,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x10C++0x03 line.long 0x00 "TXRAM67,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x110++0x03 line.long 0x00 "TXRAM68,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x114++0x03 line.long 0x00 "TXRAM69,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x118++0x03 line.long 0x00 "TXRAM70,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x11C++0x03 line.long 0x00 "TXRAM71,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x120++0x03 line.long 0x00 "TXRAM72,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x124++0x03 line.long 0x00 "TXRAM73,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x128++0x03 line.long 0x00 "TXRAM74,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x12C++0x03 line.long 0x00 "TXRAM75,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x130++0x03 line.long 0x00 "TXRAM76,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x134++0x03 line.long 0x00 "TXRAM77,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x138++0x03 line.long 0x00 "TXRAM78,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x13C++0x03 line.long 0x00 "TXRAM79,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x140++0x03 line.long 0x00 "TXRAM80,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x144++0x03 line.long 0x00 "TXRAM81,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x148++0x03 line.long 0x00 "TXRAM82,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x14C++0x03 line.long 0x00 "TXRAM83,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x150++0x03 line.long 0x00 "TXRAM84,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x154++0x03 line.long 0x00 "TXRAM85,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x158++0x03 line.long 0x00 "TXRAM86,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x15C++0x03 line.long 0x00 "TXRAM87,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x160++0x03 line.long 0x00 "TXRAM88,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x164++0x03 line.long 0x00 "TXRAM89,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x168++0x03 line.long 0x00 "TXRAM90,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x16C++0x03 line.long 0x00 "TXRAM91,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x170++0x03 line.long 0x00 "TXRAM92,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x174++0x03 line.long 0x00 "TXRAM93,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x178++0x03 line.long 0x00 "TXRAM94,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x17C++0x03 line.long 0x00 "TXRAM95,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x180++0x03 line.long 0x00 "TXRAM96,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x184++0x03 line.long 0x00 "TXRAM97,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x188++0x03 line.long 0x00 "TXRAM98,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x18C++0x03 line.long 0x00 "TXRAM99,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x190++0x03 line.long 0x00 "TXRAM100,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x194++0x03 line.long 0x00 "TXRAM101,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x198++0x03 line.long 0x00 "TXRAM102,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x19C++0x03 line.long 0x00 "TXRAM103,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1A0++0x03 line.long 0x00 "TXRAM104,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1A4++0x03 line.long 0x00 "TXRAM105,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1A8++0x03 line.long 0x00 "TXRAM106,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1AC++0x03 line.long 0x00 "TXRAM107,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1B0++0x03 line.long 0x00 "TXRAM108,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1B4++0x03 line.long 0x00 "TXRAM109,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1B8++0x03 line.long 0x00 "TXRAM110,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1BC++0x03 line.long 0x00 "TXRAM111,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1C0++0x03 line.long 0x00 "TXRAM112,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1C4++0x03 line.long 0x00 "TXRAM113,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1C8++0x03 line.long 0x00 "TXRAM114,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1CC++0x03 line.long 0x00 "TXRAM115,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1D0++0x03 line.long 0x00 "TXRAM116,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1D4++0x03 line.long 0x00 "TXRAM117,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1D8++0x03 line.long 0x00 "TXRAM118,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1DC++0x03 line.long 0x00 "TXRAM119,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1E0++0x03 line.long 0x00 "TXRAM120,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1E4++0x03 line.long 0x00 "TXRAM121,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1E8++0x03 line.long 0x00 "TXRAM122,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1EC++0x03 line.long 0x00 "TXRAM123,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1F0++0x03 line.long 0x00 "TXRAM124,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1F4++0x03 line.long 0x00 "TXRAM125,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1F8++0x03 line.long 0x00 "TXRAM126,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" group.long 0x1FC++0x03 line.long 0x00 "TXRAM127,Multi-buffer RAM Transmit Data Register" bitfld.long 0x00 29.--31. " BUFMODE ,Specify conditions that are recognized by the sequencer to initiate transfers of each buffer word" "Disabled,Skip single-transfer,Skip overwrite-protect,Skip single-transfer overwrite-protect,Continuous,Suspend single-transfer,Suspend overwrite-protect,Suspend single-transfer overwrite-protect" newline bitfld.long 0x00 28. " CSHOLD ,Chip select hold mode" "Deactivated,Held active" newline bitfld.long 0x00 27. " LOCK ,Lock two consecutive buffer words" "Not locked,Locked" bitfld.long 0x00 26. " WDEL ,Delay counter at the end of the current transaction enable" "Disabled,Enabled" newline bitfld.long 0x00 24.--25. " DFSEL ,Data word format select" "0,1,2,3" newline hexmask.long.byte 0x00 16.--23. 1. " CSNR ,Chip select number" hexmask.long.word 0x00 0.--15. 1. " TXDATA ,Transfer data" tree.end tree "Multi-buffer RAM Receive Buffer Registers" hgroup.long 0x200++0x03 hide.long 0x00 "RXRAM0,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x204++0x03 hide.long 0x00 "RXRAM1,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x208++0x03 hide.long 0x00 "RXRAM2,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x20C++0x03 hide.long 0x00 "RXRAM3,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x210++0x03 hide.long 0x00 "RXRAM4,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x214++0x03 hide.long 0x00 "RXRAM5,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x218++0x03 hide.long 0x00 "RXRAM6,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x21C++0x03 hide.long 0x00 "RXRAM7,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x220++0x03 hide.long 0x00 "RXRAM8,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x224++0x03 hide.long 0x00 "RXRAM9,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x228++0x03 hide.long 0x00 "RXRAM10,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x22C++0x03 hide.long 0x00 "RXRAM11,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x230++0x03 hide.long 0x00 "RXRAM12,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x234++0x03 hide.long 0x00 "RXRAM13,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x238++0x03 hide.long 0x00 "RXRAM14,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x23C++0x03 hide.long 0x00 "RXRAM15,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x240++0x03 hide.long 0x00 "RXRAM16,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x244++0x03 hide.long 0x00 "RXRAM17,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x248++0x03 hide.long 0x00 "RXRAM18,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x24C++0x03 hide.long 0x00 "RXRAM19,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x250++0x03 hide.long 0x00 "RXRAM20,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x254++0x03 hide.long 0x00 "RXRAM21,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x258++0x03 hide.long 0x00 "RXRAM22,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x25C++0x03 hide.long 0x00 "RXRAM23,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x260++0x03 hide.long 0x00 "RXRAM24,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x264++0x03 hide.long 0x00 "RXRAM25,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x268++0x03 hide.long 0x00 "RXRAM26,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x26C++0x03 hide.long 0x00 "RXRAM27,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x270++0x03 hide.long 0x00 "RXRAM28,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x274++0x03 hide.long 0x00 "RXRAM29,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x278++0x03 hide.long 0x00 "RXRAM30,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x27C++0x03 hide.long 0x00 "RXRAM31,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x280++0x03 hide.long 0x00 "RXRAM32,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x284++0x03 hide.long 0x00 "RXRAM33,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x288++0x03 hide.long 0x00 "RXRAM34,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x28C++0x03 hide.long 0x00 "RXRAM35,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x290++0x03 hide.long 0x00 "RXRAM36,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x294++0x03 hide.long 0x00 "RXRAM37,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x298++0x03 hide.long 0x00 "RXRAM38,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x29C++0x03 hide.long 0x00 "RXRAM39,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2A0++0x03 hide.long 0x00 "RXRAM40,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2A4++0x03 hide.long 0x00 "RXRAM41,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2A8++0x03 hide.long 0x00 "RXRAM42,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2AC++0x03 hide.long 0x00 "RXRAM43,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2B0++0x03 hide.long 0x00 "RXRAM44,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2B4++0x03 hide.long 0x00 "RXRAM45,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2B8++0x03 hide.long 0x00 "RXRAM46,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2BC++0x03 hide.long 0x00 "RXRAM47,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2C0++0x03 hide.long 0x00 "RXRAM48,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2C4++0x03 hide.long 0x00 "RXRAM49,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2C8++0x03 hide.long 0x00 "RXRAM50,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2CC++0x03 hide.long 0x00 "RXRAM51,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2D0++0x03 hide.long 0x00 "RXRAM52,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2D4++0x03 hide.long 0x00 "RXRAM53,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2D8++0x03 hide.long 0x00 "RXRAM54,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2DC++0x03 hide.long 0x00 "RXRAM55,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2E0++0x03 hide.long 0x00 "RXRAM56,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2E4++0x03 hide.long 0x00 "RXRAM57,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2E8++0x03 hide.long 0x00 "RXRAM58,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2EC++0x03 hide.long 0x00 "RXRAM59,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2F0++0x03 hide.long 0x00 "RXRAM60,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2F4++0x03 hide.long 0x00 "RXRAM61,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2F8++0x03 hide.long 0x00 "RXRAM62,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x2FC++0x03 hide.long 0x00 "RXRAM63,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x300++0x03 hide.long 0x00 "RXRAM64,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x304++0x03 hide.long 0x00 "RXRAM65,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x308++0x03 hide.long 0x00 "RXRAM66,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x30C++0x03 hide.long 0x00 "RXRAM67,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x310++0x03 hide.long 0x00 "RXRAM68,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x314++0x03 hide.long 0x00 "RXRAM69,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x318++0x03 hide.long 0x00 "RXRAM70,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x31C++0x03 hide.long 0x00 "RXRAM71,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x320++0x03 hide.long 0x00 "RXRAM72,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x324++0x03 hide.long 0x00 "RXRAM73,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x328++0x03 hide.long 0x00 "RXRAM74,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x32C++0x03 hide.long 0x00 "RXRAM75,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x330++0x03 hide.long 0x00 "RXRAM76,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x334++0x03 hide.long 0x00 "RXRAM77,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x338++0x03 hide.long 0x00 "RXRAM78,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x33C++0x03 hide.long 0x00 "RXRAM79,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x340++0x03 hide.long 0x00 "RXRAM80,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x344++0x03 hide.long 0x00 "RXRAM81,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x348++0x03 hide.long 0x00 "RXRAM82,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x34C++0x03 hide.long 0x00 "RXRAM83,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x350++0x03 hide.long 0x00 "RXRAM84,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x354++0x03 hide.long 0x00 "RXRAM85,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x358++0x03 hide.long 0x00 "RXRAM86,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x35C++0x03 hide.long 0x00 "RXRAM87,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x360++0x03 hide.long 0x00 "RXRAM88,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x364++0x03 hide.long 0x00 "RXRAM89,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x368++0x03 hide.long 0x00 "RXRAM90,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x36C++0x03 hide.long 0x00 "RXRAM91,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x370++0x03 hide.long 0x00 "RXRAM92,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x374++0x03 hide.long 0x00 "RXRAM93,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x378++0x03 hide.long 0x00 "RXRAM94,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x37C++0x03 hide.long 0x00 "RXRAM95,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x380++0x03 hide.long 0x00 "RXRAM96,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x384++0x03 hide.long 0x00 "RXRAM97,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x388++0x03 hide.long 0x00 "RXRAM98,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x38C++0x03 hide.long 0x00 "RXRAM99,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x390++0x03 hide.long 0x00 "RXRAM100,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x394++0x03 hide.long 0x00 "RXRAM101,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x398++0x03 hide.long 0x00 "RXRAM102,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x39C++0x03 hide.long 0x00 "RXRAM103,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3A0++0x03 hide.long 0x00 "RXRAM104,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3A4++0x03 hide.long 0x00 "RXRAM105,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3A8++0x03 hide.long 0x00 "RXRAM106,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3AC++0x03 hide.long 0x00 "RXRAM107,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3B0++0x03 hide.long 0x00 "RXRAM108,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3B4++0x03 hide.long 0x00 "RXRAM109,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3B8++0x03 hide.long 0x00 "RXRAM110,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3BC++0x03 hide.long 0x00 "RXRAM111,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3C0++0x03 hide.long 0x00 "RXRAM112,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3C4++0x03 hide.long 0x00 "RXRAM113,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3C8++0x03 hide.long 0x00 "RXRAM114,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3CC++0x03 hide.long 0x00 "RXRAM115,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3D0++0x03 hide.long 0x00 "RXRAM116,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3D4++0x03 hide.long 0x00 "RXRAM117,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3D8++0x03 hide.long 0x00 "RXRAM118,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3DC++0x03 hide.long 0x00 "RXRAM119,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3E0++0x03 hide.long 0x00 "RXRAM120,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3E4++0x03 hide.long 0x00 "RXRAM121,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3E8++0x03 hide.long 0x00 "RXRAM122,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3EC++0x03 hide.long 0x00 "RXRAM123,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3F0++0x03 hide.long 0x00 "RXRAM124,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3F4++0x03 hide.long 0x00 "RXRAM125,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3F8++0x03 hide.long 0x00 "RXRAM126,Multi-buffer RAM Receive Buffer Register" in hgroup.long 0x3FC++0x03 hide.long 0x00 "RXRAM127,Multi-buffer RAM Receive Buffer Register" in tree.end width 0x0B tree.end tree.end endif tree.end tree "SCI/LIN (Serial Communication Interface / Local Interconnect Network)" base ad:0xFFF7E400 width 8. group.long 0x00++0x3 line.long 0x0 "GCR0,Global Control Register" bitfld.long 0x00 0. " RESET ,SCI Module Reset" "Under reset,Out of reset" if ((d.l(ad:0xFFF7E400+0x4)&0x44000000)==0x44000000) group.long 0x04++0x3 line.long 0x0 "GCR1,Global Control Register" bitfld.long 0x00 25. " TXENA ,SCI Transmitter Enable" "Disabled,Enabled" bitfld.long 0x00 24. " RXENA ,SCI Receiver Enable" "Prevented,Allowed" textline " " bitfld.long 0x00 17. " CONT ,Continue on Suspend" "Frozen,Continue" bitfld.long 0x00 16. " LOOP_BACK ,LOOP BACK Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " STOP_EXT_FRAME ,Stop Extended Frame Communication" "Not stopped,Stopped" bitfld.long 0x00 12. " HGEN_CTRL ,LIN Mode Bit (Type of Mask Filtering Comparison)" "ID-Byte,ID-Slave task byte" textline " " bitfld.long 0x00 11. " CTYPE ,LIN Mode Bit (Classic/Enhanced)" "Classic,Enhanced" bitfld.long 0x00 10. " MBUF_MODE ,Receive/Transmit Buffer Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " ADAPT ,LIN Mode Bit (Automatic Baudrate Adjustment)" "Disabled,Enabled" bitfld.long 0x00 8. " SLEEP ,SCI Sleep Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SW_NRESET ,Software Reset" "Reset,Ready" bitfld.long 0x00 6. " LIN_MODE ,LIN MODE Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " CLOCK ,SCI Internal Clock Enable" "Slave,Master" bitfld.long 0x00 4. " STOP ,SCI Number of Stop Bits" "1 bit,2 bits" textline " " bitfld.long 0x00 2. " PARITY_ENA ,ID-Parity Enable" "Disabled,Enabled" bitfld.long 0x00 3. " PARITY ,SCI Parity Odd/Even Selection" "Odd,Even" textline " " bitfld.long 0x00 1. " TIMING_MODE ,SCI Timing Mode Bit" "Synchronous,Asynchronous" bitfld.long 0x00 0. " COMM_MODE ,SCI/BLIN Communication Mode Bit ID4 and ID5 Use" "Not used,Used" elif ((d.l(ad:0xFFF7E400+0x4)&0x44000000)==0x40000000) group.long 0x04++0x3 line.long 0x0 "GCR1,Global Control Register" bitfld.long 0x00 25. " TXENA ,SCI Transmitter Enable" "Disabled,Enabled" bitfld.long 0x00 24. " RXENA ,SCI Receiver Enable" "Prevented,Allowed" textline " " bitfld.long 0x00 17. " CONT ,Continue on Suspend" "Frozen,Continue" bitfld.long 0x00 16. " LOOP_BACK ,LOOP BACK Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " STOP_EXT_FRAME ,Stop Extended Frame Communication" "Not stopped,Stopped" bitfld.long 0x00 12. " HGEN_CTRL ,LIN Mode Bit (Type of Mask Filtering Comparison)" "ID-Byte,ID-SlaveTask" textline " " bitfld.long 0x00 11. " CTYPE ,LIN Mode Bit (Classic/Enhanced)" "Classic,Enhanced" bitfld.long 0x00 10. " MBUF_MODE ,Receive/Transmit Buffer Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " ADAPT ,LIN Mode Bit (Automatic Baudrate Adjustment)" "Disabled,Enabled" bitfld.long 0x00 8. " SLEEP ,SCI Sleep Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SW_NRESET ,Software Reset" "Reset,Ready" bitfld.long 0x00 6. " LIN_MODE ,LIN MODE Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " CLOCK ,SCI Internal Clock Enable" "Slave,Master" bitfld.long 0x00 4. " STOP ,SCI Number of Stop Bits" "1 bit,2 bits" textline " " bitfld.long 0x00 2. " PARITY_ENA ,ID-Parity Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " TIMING_MODE ,SCI Timing Mode Bit" "Synchronous,Asynchronous" bitfld.long 0x00 0. " COMM_MODE ,SCI/BLIN Communication Mode Bit ID4 and ID5 Use" "Not used,Used" elif (((d.l(ad:0xFFF7E400+0x4))&0x44000000)==0x04000000) group.long 0x04++0x3 line.long 0x0 "GCR1,Global Control Register" bitfld.long 0x00 25. " TXENA ,SCI Transmitter Enable" "Disabled,Enabled" bitfld.long 0x00 24. " RXENA ,SCI Receiver Enable" "Prevented,Allowed" textline " " bitfld.long 0x00 17. " CONT ,Continue on Suspend" "Frozen,Continue" bitfld.long 0x00 16. " LOOP_BACK ,LOOP BACK Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " MBUF_MODE ,Receive/Transmit Buffer Enable" "Disabled,Enabled" bitfld.long 0x00 8. " SLEEP ,SCI Sleep Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SW_NRESET ,Software Reset" "Reset,Ready" bitfld.long 0x00 6. " LIN_MODE ,LIN MODE Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " CLOCK ,SCI Internal Clock Enable" "External,Internal" bitfld.long 0x00 4. " STOP ,SCI Number of Stop Bits" "1 bit,2 bits" textline " " bitfld.long 0x00 2. " PARITY_ENA ,Parity Enable" "Disabled,Enabled" bitfld.long 0x00 3. " PARITY ,SCI Parity Odd/Even Selection" "Odd,Even" textline " " bitfld.long 0x00 1. " TIMING_MODE ,SCI Timing Mode Bit" "Synchronous,Asynchronous" bitfld.long 0x00 0. " COMM_MODE ,SCI/BLIN Communication Mode Bit" "Idle-line,Address-bit" else group.long 0x04++0x3 line.long 0x0 "GCR1,Global Control Register" bitfld.long 0x00 25. " TXENA ,SCI Transmitter Enable" "Disabled,Enabled" bitfld.long 0x00 24. " RXENA ,SCI Receiver Enable" "Prevented,Allowed" textline " " bitfld.long 0x00 17. " CONT ,Continue on Suspend" "Frozen,Continue" bitfld.long 0x00 16. " LOOP_BACK ,LOOP BACK Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " MBUF_MODE ,Receive/Transmit Buffer Enable" "Disabled,Enabled" bitfld.long 0x00 8. " SLEEP ,SCI Sleep Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SW_NRESET ,Software Reset" "Reset,Ready" bitfld.long 0x00 6. " LIN_MODE ,LIN MODE Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " CLOCK ,SCI Internal Clock Enable" "External,Internal" bitfld.long 0x00 4. " STOP ,SCI Number of Stop Bits" "1 bit,2 bits" textline " " bitfld.long 0x00 2. " PARITY_ENA ,Parity Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " TIMING_MODE ,SCI Timing Mode Bit" "Synchronous,Asynchronous" bitfld.long 0x00 0. " COMM_MODE ,SCI/BLIN Communication Mode Bit" "Idle-line,Address-bit" endif width 8. if ((d.l(ad:0xFFF7E400+0x4)&0x40000000)==0x40000000) group.long 0x08++0x3 line.long 0x0 "GCR2,Global Control Register" bitfld.long 0x00 17. " CC ,Compare Checksum" "No effect,Compared" bitfld.long 0x00 16. " SC ,Send Checksum" "No effect,Compared" textline " " bitfld.long 0x00 8. " GEN_WU ,Generate Wakeup Signal" "No effect,Generated" bitfld.long 0x00 0. " POWERDOWN ,POWERDOWN" "Normal,Local low-power" else group.long 0x08++0x3 line.long 0x0 "GCR2,Global Control Register" bitfld.long 0x00 8. " GEN_WU ,Generate Wakeup Signal" "No effect,Generated" textline " " bitfld.long 0x00 0. " POWERDOWN ,POWERDOWN" "Normal,Local low-power" endif width 11. tree "SCI Interrupt Registers" if ((d.l(ad:0xFFF7E400+0x4)&0x40000000)==0x40000000) group.long 0x0C++0x3 line.long 0x0 "SETINT,Interrupt Register" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " BE_INT_set/clr ,Bit Error Interrupt" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x04 30. " PBE_INT_set/clr ,Physical Bus Error Interrupt" "Disabled,Enabled" textline " " setclrfld.long 0x00 29. 0x00 29. 0x04 29. " CE_INT_set/clr ,Checksum-Error Interrupt" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x04 28. " ISFE_INT_set/clr ,Inconsistent-Synch-Field-Error Interrupt" "Disabled,Enabled" textline " " setclrfld.long 0x00 27. 0x00 27. 0x04 27. " NRE_INT_set/clr ,No-Reponse-Error Interrupt" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT_set/clr ,Framing-Error Interrupt" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT_set/clr ,Overrun-Error Interrupt" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT_set/clr ,Parity Interrupt" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. 0x00 17. 0x04 17. " RX_DMA_set/clr ,Receive DMA" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x04 16. " TX_DMA_set/clr ,Transmit DMA" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x04 13. " ID_INT_set/clr ,ID Interrupt" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT_set/clr ,Receiver Interrupt Enable" "Disabled,Enabled" textline " " setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT_set/clr ,Transmitter Interrupt" "Disabled,Enabled" setclrfld.long 0x00 7. 0x00 7. 0x04 7. " TOA3WUS_INT_set/clr ,Timeout After 3 Wakeup Signals Interrupt" "Disabled,Enabled" textline " " setclrfld.long 0x00 6. 0x00 6. 0x04 6. " TOAWUS_INT_set/clr ,Timeout After Wakeup Signal Interrupt" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x04 4. " TIMEOUT_INT_set/clr ,Timeout Interrupt" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT_set/clr ,Wake-up Interrupt" "Disabled,Enabled" else group.long 0x0C++0x3 line.long 0x0 "SETINT,Interrupt Register" setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT_set/clr ,Framing-Error Interrupt" "Disabled,Enabled" setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT_set/clr ,Overrun-Error Interrupt" "Disabled,Enabled" textline " " setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT_set/clr ,Parity Interrupt" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x04 18. " RX_DMA_ALL_set/clr ,Receive DMA All" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. 0x00 17. 0x04 17. " RX_DMA_set/clr ,Receive DMA" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x04 16. " TX_DMA_set/clr ,Transmit DMA" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT_set/clr ,Receiver Interrupt Enable" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT_set/clr ,Transmitter Interrupt" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT_set/clr ,Wake-up Interrupt" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " BRKDT_INT_set/clr ,Break-detect Interrupt" "Disabled,Enabled" endif width 11. if ((d.l(ad:0xFFF7E400+0x4)&0x40000000)==0x40000000) group.long 0x14++0x3 line.long 0x0 "SETINTLVL,Interrupt Level Register" setclrfld.long 0x00 31. 0x00 31. 0x04 31. " BE_INT_LVL_set/clr ,Bit Error Interrupt Level" "INT0,INT1" setclrfld.long 0x00 30. 0x00 30. 0x04 30. " PBE_INT_LVL_set/clr ,Physical Bus Error Interrupt Level" "INT0,INT1" textline " " setclrfld.long 0x00 29. 0x00 29. 0x04 29. " CE_INT_LVL_set/clr ,Checksum-Error Interrupt Level" "INT0,INT1" setclrfld.long 0x00 28. 0x00 28. 0x04 28. " ISFE_INT_LVL_set/clr ,Inconsistent-Synch-Field-Error Interrupt Level" "INT0,INT1" textline " " setclrfld.long 0x00 27. 0x00 27. 0x04 27. " NRE_INT_LVL_set/clr ,No-Reponse-Error Interrupt Level" "INT0,INT1" setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT_LVL_set/clr ,Framing-Error Interrupt Level" "INT0,INT1" textline " " setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT_LVL_set/clr ,Overrun-Error Interrupt Level" "INT0,INT1" setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT_LVL_set/clr ,Parity Error Interrupt Level" "INT0,INT1" textline " " setclrfld.long 0x00 13. 0x00 13. 0x04 13. " ID_INT_LVL_set/clr ,ID Interrupt Level" "INT0,INT1" setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT_LVL_set/clr ,Receiver Interrupt Level" "INT0,INT1" textline " " setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT_LVL_set/clr ,Transmitter Interrupt Level" "INT0,INT1" setclrfld.long 0x00 7. 0x00 7. 0x04 7. " TOA3WUS_INT_LVL_set/clr ,Timeout After 3 Wakeup Signals Interrupt" "INT0,INT1" textline " " setclrfld.long 0x00 6. 0x00 6. 0x04 6. " TOAWUS_INT_LVL_set/clr ,Timeout After Wakeup Signal Interrupt Level" "INT0,INT1" setclrfld.long 0x00 4. 0x00 4. 0x04 4. " TIMEOUT_INT_LVL_set/clr ,Timeout Interrupt Level" "INT0,INT1" textline " " setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT_LVL_set/clr ,Wake-up Interrupt Level" "INT0,INT1" else group.long 0x14++0x3 line.long 0x0 "SETINTLVL,Interrupt Level Register" setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT_LVL_set/clr ,Framing-Error Interrupt Level" "INT0,INT1" setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT_LVL_set/clr ,Overrun-Error Interrupt Level" "INT0,INT1" textline " " setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT_LVL_set/clr ,Parity Error Interrupt Level" "INT0,INT1" setclrfld.long 0x00 18. 0x00 18. 0x04 18. " RX_DMA_ALL_INT_LVL_set/clr ,Receive DMA All Interrupt Level" "INT0,INT1" textline " " setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT_LVL_set/clr ,Receiver Interrupt Level" "INT0,INT1" setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT_LVL_set/clr ,Transmitter Interrupt Level" "INT0,INT1" textline " " setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT_LVL_set/clr ,Wake-up Interrupt Level" "INT0,INT1" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " BRKDT_INT_set/clr ,Break-Detect Interrupt Level" "INT0,INT1" endif tree.end textline " " width 8. if ((d.l(ad:0xFFF7E400+0x4)&0x40000000)==0x40000000) group.long 0x1C++0x3 line.long 0x0 "FLR,Flags Register" eventfld.long 0x00 31. " BE ,Bit Error Flag" "Not detected,Detected" eventfld.long 0x00 30. " PBE ,Physiscal Bus Error Flag" "Not detected,Detected" textline " " eventfld.long 0x00 29. " CE ,Checksum Error Flag" "Not detected,Detected" eventfld.long 0x00 28. " ISFE ,Inconsistent Synch Field Error Flag" "Not detected,Detected" textline " " eventfld.long 0x00 27. " NRE ,No-Response Error Flag" "Not detected,Detected" eventfld.long 0x00 26. " FE ,Framing Error Flag" "Not detected,Detected" textline " " eventfld.long 0x00 25. " OE ,Overrun Error Flag" "Not detected,Detected" eventfld.long 0x00 24. " PE ,Parity Error Flag" "Not detected,Detected" textline " " eventfld.long 0x00 14. " ID_RX_FLAG ,Identifier On Receive Flag" "Not received,Received" eventfld.long 0x00 13. " ID_TX_FLAG ,Identifier On Transmit Flag" "Not received,Received" textline " " bitfld.long 0x00 11. " TX_EMPTY ,Transmitter Empty Flag" "Not empty,Empty" eventfld.long 0x00 9. " RXRDY ,Receiver Ready Flag" "Not ready,Ready" textline " " bitfld.long 0x00 8. " TXRDY ,Transmitter Buffer Register Ready Flag" "Full,Ready" eventfld.long 0x00 7. " TOA3WUS ,Timeout After 3 Wakeup Signals Flag" "No timeout,Timeout" textline " " eventfld.long 0x00 6. " TOAWUS ,Timeout After Wakeup Signal Flag" "No timeout,Timeout" eventfld.long 0x00 4. " TIMEOUT ,LIN Bus IDLE Timeout Flag" "Not detected,Detected" textline " " bitfld.long 0x00 3. " BUSY_FLAG ,BUSY Flag" "Not busy,Busy" eventfld.long 0x00 1. " WAKEUP ,Wake-up Flag" "No wake up,Wake up" else group.long 0x1C++0x3 line.long 0x0 "FLR,Flags Register" eventfld.long 0x00 31. " BE ,Bit Error Flag" "Not detected,Detected" textline " " eventfld.long 0x00 26. " FE ,Framing Error Flag" "Not detected,Detected" textline " " eventfld.long 0x00 25. " OE ,Overrun Error Flag" "Not detected,Detected" eventfld.long 0x00 24. " PE ,Parity Error Flag" "Not detected,Detected" textline " " bitfld.long 0x00 12. " RXWAKE ,Receiver Wakeup Detect Flag" "Not address,Address" bitfld.long 0x00 11. " TX_EMPTY ,Transmitter Empty Flag" "Not empty,Empty" textline " " bitfld.long 0x00 10. " TXWAKE ,SCI Transmitter Wakeup Method Select" "Data,Address" eventfld.long 0x00 9. " RXRDY ,Receiver Ready Flag" "Not ready,Ready" textline " " bitfld.long 0x00 8. " TXRDY ,Transmitter Buffer Register Ready Flag (SCITD)" "Full,Ready" bitfld.long 0x00 3. " BUSY_FLAG ,BUSY Flag" "Not busy,Busy" textline " " bitfld.long 0x00 2. " IDLE ,SCI Receiver in Idle State" "Not detected,Detected" eventfld.long 0x00 1. " WAKEUP ,Wake-up Flag" "No wake up,Wake up" textline " " eventfld.long 0x00 0. " BRKDT ,SCI Break-Detect Flag" "Not detected,Detected" endif width 9. tree "SCI Interrupt Vector Offset Registers" hgroup.long 0x20++0x3 hide.long 0x0 "INVECT0,Interrupt Vector Offset 0" in hgroup.long 0x24++0x3 hide.long 0x0 "INVECT1,Interrupt Vector Offset 1" in group.long 0x28++0x3 tree.end textline " " width 8. if ((d.l(ad:0xFFF7E400+0x4)&0x40000000)==0x40000000) group.long 0x28++0x3 line.long 0x0 "FORMAT,Format Control Register" bitfld.long 0x00 16.--18. " LENGTH ,Frame Length Control Bits" "1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes" elif (((d.l(ad:0xFFF7E400+0x4)&0x40000000)==0x0)&&(((d.l(ad:0xFFF7E400+0x04))&0x040000)==0x040000)) group.long 0x28++0x3 line.long 0x0 "FORMAT,Format Control Register" bitfld.long 0x00 16.--18. " LENGTH ,Frame Length Control Bits" "1 character,2 characters,3 characters,4 characters,5 characters,6 characters,7 characters,8 characters" bitfld.long 0x00 0.--2. " CHAR ,Character Length Control Bits" "1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits" else group.long 0x28++0x3 line.long 0x0 "FORMAT,Format Control Register" bitfld.long 0x00 0.--2. " CHAR ,Character Length Control Bits" "1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits" endif group.long 0x2C++0x3 line.long 0x0 "BRSR,Baud Rate Selection Register" hexmask.long.byte 0x00 28.--30. 1. " U ,SCI/BLIN Super Fractional Divider Selection" hexmask.long.byte 0x00 24.--27. 1. " M ,SCI/BLIN 4-bit Fractional Divider Selection" hexmask.long.tbyte 0x00 0.--23. 1. " PRESCALER_P ,SCI/BLIN 24-bit Integer Prescaler Selection" width 4. tree "SCI Data Buffer Registers" rgroup.long 0x30++0x3 line.long 0x0 "ED,SCI Data Buffer" hexmask.long.byte 0x00 0.--7. 1. " ED ,Emulation Data" hgroup.long 0x34++0x3 hide.long 0x0 "RD,SCI Data Buffer" in group.long 0x38++0x3 line.long 0x0 "TD,SCI Data Buffer" hexmask.long.byte 0x00 0.--7. 1. " TD ,Transmit Data" tree.end tree "SCI Pin I/O Control Registers" width 6. if ((d.l(ad:0xFFF7E400+0x4)&0x40000000)==0x40000000) group.long 0x3C++0x3 line.long 0x0 "PIO0,Pin I/O Control Register 0" bitfld.long 0x00 2. " TX_FUNC ,Defines the Function of Pin SCITX" "GPIO,SCITX" bitfld.long 0x00 1. " RX_FUNC ,Defines the Function of Pin SCIRX" "GPIO,SCIRX" sif (cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&cpu()!="RM48L550-ZWT"&&cpu()!="RM42L432") textline " " bitfld.long 0x00 0. " CLK_FUNC ,Clock Function" "GPIO,?..." endif else group.long 0x3C++0x3 line.long 0x0 "PIO0,Pin I/O Control Register 0" bitfld.long 0x00 2. " TX_FUNC ,Defines the Function of Pin SCITX" "GPIO,SCITX" bitfld.long 0x00 1. " RX_FUNC ,Defines the Function of Pin SCIRX" "GPIO,SCIRX" sif (cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&cpu()!="RM48L550-ZWT"&&cpu()!="RM42L432") textline " " bitfld.long 0x00 0. " CLK_FUNC ,Clock Function" "GPIO,SCICLK" endif endif if ((d.l(ad:0xFFF7E400+0x3c)&0x01000000)==0x0) group.long 0x40++0x3 line.long 0x0 "PIO1,Pin I/O Control Register 1" bitfld.long 0x00 2. " TX_DIR ,Transmit Direction" "Input,Output" bitfld.long 0x00 1. " RX_DIR ,Receive Direction" "Input,Output" sif (cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&cpu()!="RM48L550-ZWT"&&cpu()!="RM42L432") textline " " bitfld.long 0x00 0. " CLK_DIR ,Clock Data Direction" "Input,Output" endif elif (((d.l(ad:0xFFF7E400+0x3c)&0x01000000)==0x01000000)&&((d.l(ad:0xFFF7E400+0x4)&0x60000000)==0x20000000)) group.long 0x40++0x3 line.long 0x0 "PIO1,Pin I/O Control Register 1" bitfld.long 0x00 2. " TX_DIR ,Transmit Direction" "Input,Output" bitfld.long 0x00 1. " RX_DIR ,Receive Direction" "Input,Output" sif (cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&cpu()!="RM48L550-ZWT"&&cpu()!="RM42L432") textline " " bitfld.long 0x00 0. " CLK_DIR ,Clock Data Direction" "Not output,Output" endif elif (((d.l(ad:0xFFF7E400+0x3c)&0x01000000)==0x01000000)&&((d.l(ad:0xFFF7E400+0x4)&0x60000000)==0x0)) group.long 0x40++0x3 line.long 0x0 "PIO1,Pin I/O Control Register 1" bitfld.long 0x00 2. " TX_DIR ,Transmit Direction" "Input,Output" bitfld.long 0x00 1. " RX_DIR ,Receive Direction" "Input,Output" sif (cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&cpu()!="RM48L550-ZWT"&&cpu()!="RM42L432") textline " " bitfld.long 0x00 0. " CLK_DIR ,Clock Data Direction" "Input,Not input" endif else group.long 0x40++0x3 line.long 0x0 "PIO1,Pin I/O Control Register 1" bitfld.long 0x00 2. " TX_DIR ,Transmit Direction" "Input,Output" bitfld.long 0x00 1. " RX_DIR ,Receive Direction" "Input,Output" sif (cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&cpu()!="RM48L550-ZWT"&&cpu()!="RM42L432") textline " " bitfld.long 0x00 0. " CLK_DIR ,Clock Data Direction" "Input,Output" endif endif rgroup.long 0x44++0x3 line.long 0x0 "PIO2,Pin I/O Control Register 2" bitfld.long 0x00 2. " TX_IN ,Contains Current Value on the SCITX Pin" "Low,High" bitfld.long 0x00 1. " RX_IN ,Contains Current Value on the SCIRX Pin" "Low,High" sif (cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&cpu()!="RM48L550-ZWT"&&cpu()!="RM42L432") textline " " bitfld.long 0x00 0. " CLK_IN ,Contains the Current Value on Pin SCICLK" "Low,High" endif width 6. group.long 0x48++0x3 line.long 0x0 "PIO3,Pin I/O Control Register 3" setclrfld.long 0x00 2. 0x04 2. 0x08 2. " TX_OUT_set/clr ,SCITX Pin Data Output" "Low,High" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " RX_OUT_set/clr ,SCIRX Pin Data Output" "Low,High" sif (cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&cpu()!="RM48L550-ZWT"&&cpu()!="RM42L432") textline " " setclrfld.long 0x00 0. 0x00 0. 0x08 0. " CLK_OUT_set/clr ,SCICLK Pin Data Output" "Low,High" endif width 6. sif (cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&cpu()!="RM48L550-ZWT"&&cpu()!="RM42L432") group.long 0x54++0x3 line.long 0x0 "PIO6,Pin I/O Control Register 6" bitfld.long 0x00 2. " TX_PDR ,TX Open Drain Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RX_PDR ,RX Open Drain Enable" "Disabled,Enabled" else group.long 0x54++0x3 line.long 0x0 "PIO6,Pin I/O Control Register 6" bitfld.long 0x00 2. " TX_ODR ,TX Open Drain Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RX_ODR ,RX Open Drain Enable" "Disabled,Enabled" sif (cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&cpu()!="RM48L550-ZWT"&&cpu()!="RM42L432") textline " " bitfld.long 0x00 0. " CLK_ODR ,CLK Open Drain Enable" "Disabled,Enabled" endif endif group.long 0x58++0x3 line.long 0x0 "PIO7,Pin I/O Control Register 7" bitfld.long 0x00 2. " TX_PD ,TX Pin Pull Control Disable" "No,Yes" bitfld.long 0x00 1. " RX_PD ,RX Pin Pull Control Disable" "No,Yes" sif (cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&cpu()!="RM48L550-ZWT"&&cpu()!="RM42L432") textline " " bitfld.long 0x00 0. " CLK_PD ,CLK Pin Pull Control Disable" "No,Yes" endif group.long 0x5C++0x3 line.long 0x0 "PIO8,Pin I/O Control Register 8" bitfld.long 0x00 2. " TX_PSL ,TX Pin Pull Select" "Pull down,Pull up" bitfld.long 0x00 1. " RX_PSL ,RX Pin Pull Select" "Pull down,Pull up" sif (cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE"&&cpu()!="RM48L550-ZWT"&&cpu()!="RM42L432") textline " " bitfld.long 0x00 0. " CLK_PSL ,CLK Pin Pull Select" "Pull down,Pull up" endif tree.end tree "BLIN Registers" width 9. if ((d.l(ad:0xFFF7E400+0x4)&0x40000000)==0x40000000) group.long 0x60++0x3 line.long 0x0 "LINCOMP,BLINCOMPARE Register" bitfld.long 0x00 8.--9. " SDEL ,2-bit Synch Delimiter Compare" "1 bit,2 bits,3 bits,4 bits" bitfld.long 0x00 0.--2. " SBREAK ,3-bit Synch Break Extend" "Not extended,1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits" else hgroup.long 0x60++0x3 hide.long 0x0 "LINCOMP,BLINCOMPARE Register" endif hgroup.long 0x64++0x3 hide.long 0x0 "LINRD0,LINRD0 Register" in hgroup.long 0x68++0x3 hide.long 0x0 "LINRD1,LINRD1 Register" in width 9. if ((d.l(ad:0xFFF7E400+0x4)&0x40000000)==0x40000000) group.long 0x6C++0x3 line.long 0x0 "LINMASK,LINMASK Register" bitfld.long 0x00 23. " RX_ID_MASK7 ,RX ID Mask 7" "Not masked,Masked" bitfld.long 0x00 22. " RX_ID_MASK6 ,RX ID Mask 6" "Not masked,Masked" textline " " bitfld.long 0x00 21. " RX_ID_MASK5 ,RX ID Mask 5" "Not masked,Masked" bitfld.long 0x00 20. " RX_ID_MASK4 ,RX ID Mask 4" "Not masked,Masked" textline " " bitfld.long 0x00 19. " RX_ID_MASK3 ,RX ID Mask 3" "Not masked,Masked" bitfld.long 0x00 18. " RX_ID_MASK2 ,RX ID Mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 17. " RX_ID_MASK1 ,RX ID Mask 1" "Not masked,Masked" bitfld.long 0x00 16. " RX_ID_MASK0 ,RX ID Mask 0" "Not masked,Masked" textline " " bitfld.long 0x00 7. " TX_ID_MASK7 ,TX ID Mask 7" "Not masked,Masked" bitfld.long 0x00 6. " TX_ID_MASK6 ,TX ID Mask 6" "Not masked,Masked" textline " " bitfld.long 0x00 5. " TX_ID_MASK5 ,TX ID Mask 5" "Not masked,Masked" bitfld.long 0x00 4. " TX_ID_MASK4 ,TX ID Mask 4" "Not masked,Masked" textline " " bitfld.long 0x00 3. " TX_ID_MASK3 ,TX ID Mask 3" "Not masked,Masked" bitfld.long 0x00 2. " TX_ID_MASK2 ,TX ID Mask 2" "Not masked,Masked" textline " " bitfld.long 0x00 1. " TX_ID_MASK1 ,TX ID Mask 1" "Not masked,Masked" bitfld.long 0x00 0. " TX_ID_MASK0 ,TX ID Mask 0" "Not masked,Masked" else hgroup.long 0x6C++0x3 hide.long 0x0 "LINMASK,LINMASK Register" endif width 9. if ((d.l(ad:0xFFF7E400+0x4)&0x40000000)==0x40000000) group.long 0x70++0x3 line.long 0x0 "LINID,LINID Register" hexmask.long.byte 0x00 16.--23. 1. " RECEIVED_ID ,Received Identifier" hexmask.long.byte 0x00 8.--15. 1. " ID_SLAVETASK_BYTE ,Identifier Slave Task Byte" hexmask.long.byte 0x00 0.--7. 1. " ID_BYTE ,Identifier Byte" else hgroup.long 0x70++0x3 hide.long 0x0 "LINID,LINID Register" endif width 9. group.long 0x74++0x3 line.long 0x0 "LINTD0,LINTD0 Register" hexmask.long.byte 0x00 24.--31. 1. " TD0 ,8-bit Transmit Buffer 0" hexmask.long.byte 0x00 16.--23. 1. " TD1 ,8-bit Transmit Buffer 1" hexmask.long.byte 0x00 8.--15. 1. " TD2 ,8-bit Transmit Buffer 2" hexmask.long.byte 0x00 0.--7. 1. " TD3 ,8-bit Transmit Buffer 3" group.long 0x78++0x3 line.long 0x0 "LINTD1,LINTD1 Register" hexmask.long.byte 0x00 24.--31. 1. " TD4 ,8-bit Transmit Buffer 4" hexmask.long.byte 0x00 16.--23. 1. " TD5 ,8-bit Transmit Buffer 5" hexmask.long.byte 0x00 8.--15. 1. " TD6 ,8-bit Transmit Buffer 6" hexmask.long.byte 0x00 0.--7. 1. " TD7 ,8-bit Transmit Buffer 7" tree.end textline " " width 11. if ((d.l(ad:0xFFF7E400+0x4)&0x40000000)==0x40000000) group.long 0x7C++0x3 line.long 0x0 "MBRSR,Maximum Baud Rate Selection Register" hexmask.long.word 0x00 0.--12. 1. " MBR ,Maximum Baud Rate Prescaler" else hgroup.long 0x7C++0x3 hide.long 0x0 "MBRSR,Maximum Baud Rate Selection Register" endif sif (cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE"&&cpu()!="RM46L852-PGE"&&cpu()!="RM46L852-ZWT"&&cpu()!="RM46L850-PGE"&&cpu()!="RM46L850-ZWT"&&cpu()!="RM46L840-ZWT"&&cpu()!="RM46L840-PGE"&&cpu()!="RM46L830-ZWT"&&cpu()!="RM46L830-PGE"&&cpu()!="RM46L450-ZWT"&&cpu()!="RM46L450-PGE"&&cpu()!="RM46L440-ZWT"&&cpu()!="RM46L440-PGE"&&cpu()!="RM46L430-ZWT"&&cpu()!="RM46L430-PGE") group.long 0x80++0x3 line.long 0x0 "PIO9,Pin I/O Control Register 9" bitfld.long 0x00 2. " TX_SL ,This Bit Controls the Slew Rate for the SCITX Pin" "Normal,Slew" bitfld.long 0x00 1. " RX_SL ,This Bit Controls the Slew Rate for the SCIRX Pin" "Normal,Slew" bitfld.long 0x00 0. " CLK_SL ,This Bit Controls the Slew Rate for the SCICLK Pin" "Normal,Slew" endif width 11. if ((d.l(ad:0xFFF7E400+0x4)&0x40000000)==0x40000000) group.long 0x90++0x3 line.long 0x0 "IODFTCTRL,IODFT for BLIN Moduler" bitfld.long 0x00 31. " BEEN ,Bit Error Enable" "Disabled,Enabled" bitfld.long 0x00 30. " PBEEN ,Physical Bus Error Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " CEEN ,Checksum Error Enable" "Disabled,Enabled" bitfld.long 0x00 28. " ISFEEN ,Inconsistent Synch Field Error Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " FEEN ,Frame Error Enable" "Disabled,Enabled" bitfld.long 0x00 19.--20. " PSM ,PIN SAMPLE MASK" "No mask,TBIT_CENTER,TBIT_CENTER + SCLK,TBIT_CENTER + 2 SCLK" textline " " bitfld.long 0x00 16.--18. " TX_SHIFT ,Transmit Shift" "No delay,1 SCLK,2 SCLKs,3 SCLKs,4 SCLKs,5 SCLKs,6 SCLKs,7 SCLKs" bitfld.long 0x00 8.--11. " IODFTENA ,IO DFT Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" textline " " bitfld.long 0x00 1. " LPBENA ,Module Loopback Enable" "Analog,Digital" bitfld.long 0x00 0. " RXPENA ,Module Analog Loopback Through Receive/Transmit Pin Enable" "Transmit,Receive" else group.long 0x90++0x3 line.long 0x0 "IODFTCTRL,IODFT for BLIN Moduler" bitfld.long 0x00 26. " FEEN ,Frame Error Enable" "Disabled,Enabled" bitfld.long 0x00 25. " PEEN ,Parity Error Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " BDEEN ,Break Detect Error Enable" "Disabled,Enabled" bitfld.long 0x00 19.--20. " PSM ,PIN SAMPLE MASK" "No mask,TBIT_CENTER,TBIT_CENTER + SCLK,TBIT_CENTER + 2 SCLK" textline " " bitfld.long 0x00 16.--18. " TX_SHIFT ,Transmit Shift" "No delay,1 SCLK,2 SCLKs,3 SCLKs,4 SCLKs,5 SCLKs,6 SCLKs,7 SCLKs" bitfld.long 0x00 8.--11. " IODFTENA ,IO DFT Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" textline " " bitfld.long 0x00 1. " LPBENA ,Module Loopback Enable" "Analog,Digital" bitfld.long 0x00 0. " RXPENA ,Module Analog Loopback Through Receive/Transmit Pin Enable" "Transmit,Receive" endif width 0xb tree.end sif (cpu()!="RM42L432") tree "SCI (Serial Communication Interface)" base ad:0xFFF7E500 width 11. group.long 0x00++0x3 line.long 0x0 "GCR0,Global Control Register" bitfld.long 0x00 0. " RESET ,SCI Module Reset" "Under reset,Out of reset" group.long 0x04++0x3 line.long 0x0 "GCR1,Global Control Register" bitfld.long 0x00 25. " TXENA ,SCI Transmitter Enable" "Disabled,Enabled" bitfld.long 0x00 24. " RXENA ,SCI Receiver Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " CONT ,Continue on Suspend" "Frozen,Continue" bitfld.long 0x00 16. " LOOP_BACK ,LOOP BACK Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " POWERDOWN ,Automatic Baudrate Adjustment" "Disabled,Enabled" bitfld.long 0x00 8. " SLEEP ,SCI Sleep Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " SW_nRESET ,Software Reset" "Reset,Ready" bitfld.long 0x00 5. " CLOCK ,SCI Internal Clock Enable" "External,Internal" textline " " bitfld.long 0x00 4. " STOP ,SCI Number of Stop Bits" "1 bit,2 bits" bitfld.long 0x00 3. " PARITY ,SCI Parity Odd/Even Selection" "Odd,Even" textline " " bitfld.long 0x00 2. " PARITY_ENA ,ID-Parity Enable" "Disabled,Enabled" bitfld.long 0x00 1. " TIMING_MODE ,SCI Timing Mode Bit" "Synchronous,Asynchronous" textline " " bitfld.long 0x00 0. " COMM_MODE ,SCI Communication mode bit" "Address-bit,Idle-line" group.long 0x0C++0x3 line.long 0x0 "SETINT,Interrupt Register" setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT_set/clr ,Framing-Error Interrupt" "Disabled,Enabled" setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT_set/clr ,Overrun-Error Interrupt" "Disabled,Enabled" textline " " setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT_set/clr ,Parity Interrupt" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x04 18. " RX_DMA_ALL_set/clr ,Receive DMA All" "Disabled,Enabled" textline " " setclrfld.long 0x00 17. 0x00 17. 0x04 17. " RX_DMA_set/clr ,Receive DMA" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x04 16. " TX_DMA_set/clr ,Transmit DMA" "Disabled,Enabled" textline " " setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT_set/clr ,Receiver Interrupt Enable" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT_set/clr ,Transmitter Interrupt" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT_set/clr ,Wake-up Interrupt" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " BRKDT_INT_set/clr ,Break-detect Interrupt" "Disabled,Enabled" group.long 0x14++0x3 line.long 0x0 "SETINTLVL,Interrupt Level Register" setclrfld.long 0x00 26. 0x00 26. 0x04 26. " FE_INT_LVL_set/clr ,Framing-Error Interrupt Level" "INT0,INT1" setclrfld.long 0x00 25. 0x00 25. 0x04 25. " OE_INT_LVL_set/clr ,Overrun-Error Interrupt Level" "INT0,INT1" textline " " setclrfld.long 0x00 24. 0x00 24. 0x04 24. " PE_INT_LVL_set/clr ,Parity Error Interrupt Level" "INT0,INT1" setclrfld.long 0x00 18. 0x00 18. 0x04 18. " RX_DMA_ALL_INT_LVL_set/clr ,Receive DMA All Interrupt Level" "INT0,INT1" textline " " setclrfld.long 0x00 9. 0x00 9. 0x04 9. " RX_INT_LVL_set/clr ,Receiver Interrupt Level" "INT0,INT1" setclrfld.long 0x00 8. 0x00 8. 0x04 8. " TX_INT_LVL_set/clr ,Transmitter Interrupt Level" "INT0,INT1" textline " " setclrfld.long 0x00 1. 0x00 1. 0x04 1. " WAKEUP_INT_LVL_set/clr ,Wake-up Interrupt Level" "INT0,INT1" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " BRKDT_INT_set/clr ,Break-Detect Interrupt Level" "INT0,INT1" group.long 0x1C++0x3 line.long 0x0 "FLR,Flags Register" eventfld.long 0x00 26. " FE ,Framing Error Flag" "Not detected,Detected" textline " " eventfld.long 0x00 25. " OE ,Overrun Error Flag" "Not detected,Detected" eventfld.long 0x00 24. " PE ,Parity Error Flag" "Not detected,Detected" textline " " bitfld.long 0x00 12. " RX_WAKE ,Receiver Wakeup Detect Flag" "Not address,Address" bitfld.long 0x00 11. " TX_EMPTY ,Transmitter Empty Flag" "Not empty,Empty" textline " " bitfld.long 0x00 10. " TXWAKE ,SCI Transmitter Wakeup Method Select" "Data,Address" eventfld.long 0x00 9. " RXRDY ,Receiver Ready Flag" "Not ready,Ready" textline " " bitfld.long 0x00 8. " TXRDY ,Transmitter Buffer Register Ready Flag (SCITD)" "Full,Ready" bitfld.long 0x00 3. " BUSY_flag ,BUSY Flag" "Not busy,Busy" textline " " bitfld.long 0x00 2. " IDLE ,SCI Receiver in Idle State" "Not detected,Detected" eventfld.long 0x00 1. " WAKEUP ,Wake-up Flag" "No wake up,Wake up" textline " " eventfld.long 0x00 0. " BRKDT ,SCI Break-Detect Flag" "Not detected,Detected" hgroup.long 0x20++0x3 hide.long 0x0 "INVECT0,Interrupt Vector Offset 0" in hgroup.long 0x24++0x3 hide.long 0x0 "INVECT1,Interrupt Vector Offset 1" in group.long 0x28++0x3 group.long 0x28++0x3 line.long 0x0 "FORMAT,Format Control Register" bitfld.long 0x00 0.--2. " CHAR ,Character Length Control Bits" "1 bit,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits" group.long 0x2C++0x3 line.long 0x0 "BRS,Baud Rate Selection Register" hexmask.long.tbyte 0x00 0.--23. 1. " BAUD ,SCI 24-bit baud selection" rgroup.long 0x30++0x3 line.long 0x0 "ED,SCI Data Buffer" hexmask.long.byte 0x00 0.--7. 1. " ED ,Emulation Data" hgroup.long 0x34++0x3 hide.long 0x0 "RD,SCI Data Buffer" in group.long 0x38++0x3 line.long 0x0 "TD,SCI Data Buffer" hexmask.long.byte 0x00 0.--7. 1. " TD ,Transmit Data" group.long 0x3C++0x3 line.long 0x0 "PIO0,Pin I/O Control Register 0" bitfld.long 0x00 2. " TX_FUNC ,Defines the Function of Pin SCITX" "GPIO,SCITX" bitfld.long 0x00 1. " RX_FUNC ,Defines the Function of Pin SCIRX" "GPIO,SCIRX" group.long 0x40++0x3 line.long 0x0 "PIO1,Pin I/O Control Register 1" bitfld.long 0x00 2. " TX_DIR ,Transmit Direction" "Input,Output" bitfld.long 0x00 1. " RX_DIR ,Receive Direction" "Input,Output" rgroup.long 0x44++0x3 line.long 0x0 "PIO2,Pin I/O Control Register 2" bitfld.long 0x00 2. " TX_IN ,Contains Current Value on the SCITX Pin" "Low,High" bitfld.long 0x00 1. " RX_IN ,Contains Current Value on the SCIRX Pin" "Low,High" group.long 0x48++0x3 line.long 0x0 "PIO3,Pin I/O Control Register 3" bitfld.long 0x00 2. " TX_PDR ,TX Open Drain Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RX_PDR ,RX Open Drain Enable" "Disabled,Enabled" group.long 0x4C++0x3 line.long 0x0 "PIO4,Pin I/O Control Register 6" bitfld.long 0x00 2. " TX_SET ,Transmit pin set" "Low,High" bitfld.long 0x00 1. " RX_SET ,Receive pin set" "Low,High" group.long 0x50++0x3 line.long 0x0 "PIO5,Pin I/O Control Register 6" bitfld.long 0x00 2. " TX_CLR ,TX Open Drain Enable" "Low,High" bitfld.long 0x00 1. " RX_CLR ,RX Open Drain Enable" "Low,High" group.long 0x54++0x3 line.long 0x0 "PIO6,Pin I/O Control Register 6" bitfld.long 0x00 2. " TX_PDR ,TX Open Drain Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RX_PDR ,RX Open Drain Enable" "Disabled,Enabled" group.long 0x58++0x3 line.long 0x0 "PIO7,Pin I/O Control Register 7" bitfld.long 0x00 2. " TX_PD ,TX Pin Pull Control Disable" "No,Yes" bitfld.long 0x00 1. " RX_PD ,RX Pin Pull Control Disable" "No,Yes" group.long 0x5C++0x3 line.long 0x0 "PIO8,Pin I/O Control Register 8" bitfld.long 0x00 2. " TX_PSL ,TX Pin Pull Select" "Pull down,Pull up" bitfld.long 0x00 1. " RX_PSL ,RX Pin Pull Select" "Pull down,Pull up" group.long 0x90++0x3 line.long 0x0 "IODFTCTRL,IODFT for BLIN Moduler" bitfld.long 0x00 26. " FEN ,Frame Error Enable" "Disabled,Enabled" bitfld.long 0x00 25. " PEN ,Parity Error Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " BEKD_TENA ,Break Detect Error Enable" "Disabled,Enabled" bitfld.long 0x00 19.--20. " PSM ,PIN SAMPLE MASK" "No mask,Invert 7th SCLK,Invert 8th SCLK,Invert 9th SCLK" textline " " bitfld.long 0x00 16.--18. " TX_SHIFT ,Transmit Shift" "No delay,1 SCLK,2 SCLKs,3 SCLKs,4 SCLKs,5 SCLKs,6 SCLKs,No delay" bitfld.long 0x00 8.--11. " IODFTENA ,IO DFT Enable Key" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" textline " " bitfld.long 0x00 1. " LPBENA ,Module Loopback Enable" "Analog,Digital" bitfld.long 0x00 0. " RXPENA ,Module Analog Loopback Through Receive/Transmit Pin Enable" "Transmit,Receive" width 0xb tree.end tree "I2C (Inter-Integrated Circuit)" base ad:0xFFF7D400 width 14. sif (cpuis("RM48L950*")) if (((per.w(ad:0xFFF7D400+0x24))&0x010000)==0x010000) group.word 0x00++0x01 line.word 0x00 "I2COAR,I2C Own Address Manager" hexmask.word 0x00 0.--9. 1. " OA(9-0) ,Own address" else group.word 0x00++0x01 line.word 0x00 "I2COAR,I2C Own Address Manager" hexmask.word.byte 0x00 0.--6. 1. " OA(6-0) ,Own address" endif elif (cpu()=="TMS570LS3137-EP") if (((per.w.be(ad:0xFFF7D400+0x24))&0x100)==0x100) group.word 0x00++0x01 line.word 0x00 "I2COAR,I2C Own Address Manager" hexmask.word 0x00 0.--9. 1. " OA ,Own address" else group.word 0x00++0x01 line.word 0x00 "I2COAR,I2C Own Address Manager" hexmask.word.byte 0x00 0.--6. 1. " OA ,Own address" endif else if (((per.w(ad:0xFFF7D400+0x24))&0x100)==0x100) group.word 0x00++0x01 line.word 0x00 "I2COAR,I2C Own Address Manager" hexmask.word 0x00 0.--9. 1. " OA(9-0) ,Own address" else group.word 0x00++0x01 line.word 0x00 "I2COAR,I2C Own Address Manager" hexmask.word.byte 0x00 0.--6. 1. " OA(6-0) ,Own address" endif endif group.word 0x04++0x01 line.word 0x00 "I2CIMR,I2C Interrupt Mask Register" bitfld.word 0x00 6. " AASEN ,Address as slave interrupt enable" "Disabled,Enabled" bitfld.word 0x00 5. " SCDEN ,Stop condition interrupt enable" "Disabled,Enabled" newline bitfld.word 0x00 4. " TXRDYEN ,Transmit data ready interrupt enable" "Disabled,Enabled" bitfld.word 0x00 3. " RXRDYEN ,Receive data ready interrupt enable" "Disabled,Enabled" newline bitfld.word 0x00 2. " ARDYEN ,Register access ready interrupt enable" "Disabled,Enabled" bitfld.word 0x00 1. " NACKEN ,No acknowledgement interrupt enable" "Disabled,Enabled" newline bitfld.word 0x00 0. " ALEN ,Arbitration lost interrupt enable" "Disabled,Enabled" group.word 0x08++0x01 line.word 0x00 "I2CSTR,I2C Status Register" sif (cpu()=="TMS570LS3137-EP") eventfld.word 0x00 14. " SDIR ,Slave direction" "Receiver,Transmitter" eventfld.word 0x00 13. " NACKSNT ,No acknowledge sent" "Not sent,Sent" newline rbitfld.word 0x00 12. " BB ,Bus busy" "Not busy,Busy" rbitfld.word 0x00 11. " RSFULL ,Receiver shift full" "Not full,Full" newline bitfld.word 0x00 10. " XSMT ,Transmit shift empty" "Empty,Not empty" rbitfld.word 0x00 9. " AAS ,Address as slave" "Not slave,Slave" newline rbitfld.word 0x00 8. " AD0 ,Address zero status" "Not detected,Detected" else eventfld.word 0x00 14. " SDIR ,Slave transmitter direction enable" "Disabled,Enabled" eventfld.word 0x00 13. " NACKSNT ,No acknowledge sent" "Not sent,Sent" newline bitfld.word 0x00 12. " BB ,Bus busy" "Not busy,Busy" bitfld.word 0x00 11. " RSFULL ,Receiver shift full" "Not full,Full" newline bitfld.word 0x00 10. " XSMT ,Transmit shift empty not" "Empty,Not empty" bitfld.word 0x00 9. " AAS ,Address as slave" "Disabled,Enabled" newline bitfld.word 0x00 8. " AD0 ,Address zero status" "Not detected,Detected" endif eventfld.word 0x00 5. " SCD ,Stop condition detect interrupt flag" "No interrupt,Interrupt" newline sif (cpu()=="TMS570LS3137-EP") bitfld.word 0x00 4. " TXRDY ,Transmit data ready interrupt flag" "No interrupt,Interrupt" else eventfld.word 0x00 4. " TXRDY ,Transmit data ready interrupt flag" "No interrupt,Interrupt" endif eventfld.word 0x00 3. " RXRDY ,Receive data ready interrupt flag" "No interrupt,Interrupt" newline eventfld.word 0x00 2. " ARDY ,Register access ready interrupt flag" "No interrupt,Interrupt" eventfld.word 0x00 1. " NACK ,No acknowledgement interrupt" "No interrupt,Interrupt" newline eventfld.word 0x00 0. " AL ,Arbitration lost interrupt flag" "No interrupt,Interrupt" group.word 0x0C++0x01 line.word 0x00 "I2CCKL,I2C Clock Divider Low Register" group.word 0x10++0x01 line.word 0x00 "I2CCKH,I2C Clock Control High Register" group.word 0x14++0x01 line.word 0x00 "I2CCNT,I2C Data Count Register" hgroup.word 0x18++0x01 hide.word 0x00 "I2CDRR,I2C Data Receive Register" in sif (cpuis("RM48L950*")) if (((per.w(ad:0xFFF7D400+0x24))&0x010000)==0x010000) group.word 0x1C++0x01 line.word 0x00 "I2CSAR,I2C Slave Address Register" hexmask.word 0x00 0.--9. 1. " SA ,Receive data" else group.word 0x1C++0x01 line.word 0x00 "I2CSAR,I2C Slave Address Register" hexmask.word.byte 0x00 0.--6. 1. " SA ,Receive data" endif elif (cpu()=="TMS570LS3137-EP") if (((per.w.be(ad:0xFFF7D400+0x24))&0x100)==0x100) group.word 0x1C++0x01 line.word 0x00 "I2CSAR,I2C Slave Address Register" hexmask.word 0x00 0.--9. 1. " SA ,Receive data" else group.word 0x1C++0x01 line.word 0x00 "I2CSAR,I2C Slave Address Register" hexmask.word.byte 0x00 0.--6. 1. " SA ,Receive data" endif else if (((per.w(ad:0xFFF7D400+0x24))&0x100)==0x100) group.word 0x1C++0x01 line.word 0x00 "I2CSAR,I2C Slave Address Register" hexmask.word 0x00 0.--9. 1. " SA ,Receive data" else group.word 0x1C++0x01 line.word 0x00 "I2CSAR,I2C Slave Address Register" hexmask.word.byte 0x00 0.--6. 1. " SA ,Receive data" endif endif group.word 0x20++0x01 line.word 0x00 "I2CDXR,I2C Data Transmit Register" hexmask.word.byte 0x00 0.--7. 1. " DATATX ,Transmit data" sif (cpuis("RM48L950*")) if (((per.w(ad:0xFFF7D400+0x24))&0x08060000)==0x000) group.word 0x24++0x01 line.word 0x00 "I2CMDR,I2C Mode Register" bitfld.word 0x00 15. " NACKMOD ,No-acknowledge (NACK) mode" "Disabled,Enabled" bitfld.word 0x00 14. " FREE ,Free running bit" "Disabled,Enabled" newline bitfld.word 0x00 10. " MST ,Master/slave mode bit" "Slave,Master" bitfld.word 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit" newline bitfld.word 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing" newline bitfld.word 0x00 5. " nIRS ,I2C reset enable bit" "Disabled,Enabled" newline bitfld.word 0x00 3. " FDF ,Free data format enable bit (not supported in digital loop back mode [this.DLB = 1])" "Disabled,Enabled" newline bitfld.word 0x00 0.--2. " BC[2-0] ,Bit count" "9,,3,4,5,6,7,8" elif (((per.w(ad:0xFFF7D400+0x24))&0x08060000)==0x08000000) group.word 0x24++0x01 line.word 0x00 "I2CMDR,I2C Mode Register" bitfld.word 0x00 15. " NACKMOD ,No-acknowledge (NACK) mode" "Disabled,Enabled" bitfld.word 0x00 14. " FREE ,Free running bit" "Disabled,Enabled" newline bitfld.word 0x00 10. " MST ,Master/slave mode bit" "Slave,Master" bitfld.word 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit" newline bitfld.word 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing" newline bitfld.word 0x00 5. " nIRS ,I2C reset enable bit" "Disabled,Enabled" newline bitfld.word 0x00 3. " FDF ,Free data format enable bit (not supported in digital loop back mode [this.DLB = 1])" "Disabled,Enabled" newline bitfld.word 0x00 0.--2. " BC[2-0] ,Bit count" "8,,2,3,4,5,6,7" elif (((per.w(ad:0xFFF7D400+0x24))&0x08060000)==0x08040000) group.word 0x24++0x01 line.word 0x00 "I2CMDR,I2C Mode Register" bitfld.word 0x00 15. " NACKMOD ,No-acknowledge (NACK) mode" "Disabled,Enabled" bitfld.word 0x00 14. " FREE ,Free running bit" "Disabled,Enabled" newline bitfld.word 0x00 13. " STT ,Start condition" "Disabled,Enabled" bitfld.word 0x00 11. " STP ,Stop condition" "Disabled,Enabled" newline bitfld.word 0x00 10. " MST ,Master/slave mode bit" "Slave,Master" bitfld.word 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit" newline bitfld.word 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing" bitfld.word 0x00 7. " RM ,Repeat mode enable bit" "Disabled,Enabled" newline bitfld.word 0x00 5. " nIRS ,I2C reset enable bit" "Disabled,Enabled" newline bitfld.word 0x00 4. " STB ,Start byte mode enable" "Disabled,Enabled" newline bitfld.word 0x00 3. " FDF ,Free data format enable bit (not supported in digital loop back mode [this.DLB = 1])" "Disabled,Enabled" newline bitfld.word 0x00 0.--2. " BC[2-0] ,Bit count" "8,,2,3,4,5,6,7" elif (((per.w(ad:0xFFF7D400+0x24))&0x08060000)==0x040000) group.word 0x24++0x01 line.word 0x00 "I2CMDR,I2C Mode Register" bitfld.word 0x00 15. " NACKMOD ,No-acknowledge (NACK) mode" "Disabled,Enabled" bitfld.word 0x00 14. " FREE ,Free running bit" "Disabled,Enabled" newline bitfld.word 0x00 13. " STT ,Start condition" "Disabled,Enabled" bitfld.word 0x00 11. " STP ,Stop condition" "Disabled,Enabled" newline bitfld.word 0x00 10. " MST ,Master/slave mode bit" "Slave,Master" bitfld.word 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit" newline bitfld.word 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing" bitfld.word 0x00 7. " RM ,Repeat mode enable bit" "Disabled,Enabled" newline bitfld.word 0x00 5. " nIRS ,I2C reset enable bit" "Disabled,Enabled" newline bitfld.word 0x00 4. " STB ,Start byte mode enable" "Disabled,Enabled" newline bitfld.word 0x00 3. " FDF ,Free data format enable bit (not supported in digital loop back mode [this.DLB = 1])" "Disabled,Enabled" newline bitfld.word 0x00 0.--2. " BC[2-0] ,Bit count" "9,,3,4,5,6,7,8" elif (((per.w(ad:0xFFF7D400+0x24))&0x08060000)==0x060000) group.word 0x24++0x01 line.word 0x00 "I2CMDR,I2C Mode Register" bitfld.word 0x00 15. " NACKMOD ,No-acknowledge (NACK) mode" "Disabled,Enabled" bitfld.word 0x00 14. " FREE ,Free running bit" "Disabled,Enabled" newline bitfld.word 0x00 13. " STT ,Start condition" "Disabled,Enabled" bitfld.word 0x00 11. " STP ,Stop condition" "Disabled,Enabled" newline bitfld.word 0x00 10. " MST ,Master/slave mode bit" "Slave,Master" bitfld.word 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit" newline bitfld.word 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing" bitfld.word 0x00 7. " RM ,Repeat mode enable bit" "Disabled,Enabled" newline bitfld.word 0x00 6. " DLB ,Digital loop back enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " nIRS ,I2C reset enable bit" "Disabled,Enabled" newline bitfld.word 0x00 4. " STB ,Start byte mode enable" "Disabled,Enabled" newline bitfld.word 0x00 3. " FDF ,Free data format enable bit (not supported in digital loop back mode [this.DLB = 1])" "Disabled,Enabled" newline bitfld.word 0x00 0.--2. " BC[2-0] ,Bit count" "9,,3,4,5,6,7,8" elif (((per.w(ad:0xFFF7D400+0x24))&0x08060000)==0x08060000) group.word 0x24++0x01 line.word 0x00 "I2CMDR,I2C Mode Register" bitfld.word 0x00 15. " NACKMOD ,No-acknowledge (NACK) mode" "Disabled,Enabled" bitfld.word 0x00 14. " FREE ,Free running bit" "Disabled,Enabled" newline bitfld.word 0x00 13. " STT ,Start condition" "Disabled,Enabled" bitfld.word 0x00 11. " STP ,Stop condition" "Disabled,Enabled" newline bitfld.word 0x00 10. " MST ,Master/slave mode bit" "Slave,Master" bitfld.word 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit" newline bitfld.word 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing" bitfld.word 0x00 7. " RM ,Repeat mode enable bit" "Disabled,Enabled" newline bitfld.word 0x00 6. " DLB ,Digital loop back enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " nIRS ,I2C reset enable bit" "Disabled,Enabled" newline bitfld.word 0x00 4. " STB ,Start byte mode enable" "Disabled,Enabled" newline bitfld.word 0x00 3. " FDF ,Free data format enable bit (not supported in digital loop back mode [this.DLB = 1])" "Disabled,Enabled" newline bitfld.word 0x00 0.--2. " BC[2-0] ,Bit count" "8,,2,3,4,5,6,7" elif (((per.w(ad:0xFFF7D400+0x24))&0x08060000)==0x08020000) group.word 0x24++0x01 line.word 0x00 "I2CMDR,I2C Mode Register" bitfld.word 0x00 15. " NACKMOD ,No-acknowledge (NACK) mode" "Disabled,Enabled" bitfld.word 0x00 14. " FREE ,Free running bit" "Disabled,Enabled" newline bitfld.word 0x00 10. " MST ,Master/slave mode bit" "Slave,Master" bitfld.word 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit" newline bitfld.word 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing" newline bitfld.word 0x00 5. " nIRS ,I2C reset enable bit" "Disabled,Enabled" newline bitfld.word 0x00 3. " FDF ,Free data format enable bit (not supported in digital loop back mode [this.DLB = 1])" "Disabled,Enabled" newline bitfld.word 0x00 0.--2. " BC[2-0] ,Bit count" "8,,2,3,4,5,6,7" else group.word 0x24++0x01 line.word 0x00 "I2CMDR,I2C Mode Register" bitfld.word 0x00 15. " NACKMOD ,No-acknowledge (NACK) mode" "Disabled,Enabled" bitfld.word 0x00 14. " FREE ,Free running bit" "Disabled,Enabled" newline bitfld.word 0x00 10. " MST ,Master/slave mode bit" "Slave,Master" bitfld.word 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit" newline bitfld.word 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing" newline bitfld.word 0x00 5. " nIRS ,I2C reset enable bit" "Disabled,Enabled" newline bitfld.word 0x00 3. " FDF ,Free data format enable bit (not supported in digital loop back mode [this.DLB = 1])" "Disabled,Enabled" newline bitfld.word 0x00 0.--2. " BC[2-0] ,Bit count" "9,,3,4,5,6,7,8" endif elif (cpu()=="TMS570LS3137-EP") if (((per.w.be(ad:0xFFF7D400+0x24))&0x600)==0x00) group.word 0x24++0x01 line.word 0x00 "I2CMDR,I2C Mode Register" bitfld.word 0x00 15. " NACKMOD ,No-acknowledge (NACK) mode" "Disabled,Enabled" bitfld.word 0x00 14. " FREE ,Free running bit" "Disabled,Enabled" newline newline bitfld.word 0x00 10. " MST ,Master/slave mode bit" "Slave,Master" bitfld.word 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit" newline bitfld.word 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing" newline bitfld.word 0x00 5. " NIRS ,I2C reset enable bit" "Disabled,Enabled" newline bitfld.word 0x00 3. " FDF ,Free data format enable bit (excluding the acknowledge bit)" "Disabled,Enabled" newline bitfld.word 0x00 0.--2. " BC[2-0] ,Bit count" "8,,2,3,4,5,6,7" elif (((per.w.be(ad:0xFFF7D400+0x24))&0x600)==0x400) group.word 0x24++0x01 line.word 0x00 "I2CMDR,I2C Mode Register" bitfld.word 0x00 15. " NACKMOD ,No-acknowledge (NACK) mode" "Disabled,Enabled" bitfld.word 0x00 14. " FREE ,Free running bit" "Disabled,Enabled" newline bitfld.word 0x00 13. " STT ,Start condition" "Disabled,Enabled" bitfld.word 0x00 11. " STP ,Stop condition" "Disabled,Enabled" newline bitfld.word 0x00 10. " MST ,Master/slave mode bit" "Slave,Master" bitfld.word 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit" newline bitfld.word 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing" bitfld.word 0x00 7. " RM ,Repeat mode enable bit" "Disabled,Enabled" newline bitfld.word 0x00 5. " NIRS ,I2C reset enable bit" "Disabled,Enabled" newline bitfld.word 0x00 4. " STB ,Start byte mode enable" "Disabled,Enabled" newline bitfld.word 0x00 3. " FDF ,Free data format enable bit (excluding the acknowledge bit)" "Disabled,Enabled" newline bitfld.word 0x00 0.--2. " BC[2-0] ,Bit count" "8,,2,3,4,5,6,7" elif (((per.w.be(ad:0xFFF7D400+0x24))&0x600)==0x600) group.word 0x24++0x01 line.word 0x00 "I2CMDR,I2C Mode Register" bitfld.word 0x00 14. " FREE ,Free running bit" "Disabled,Enabled" newline bitfld.word 0x00 13. " STT ,Start condition" "Disabled,Enabled" bitfld.word 0x00 11. " STP ,Stop condition" "Disabled,Enabled" newline bitfld.word 0x00 10. " MST ,Master/slave mode bit" "Slave,Master" bitfld.word 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit" newline bitfld.word 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing" bitfld.word 0x00 7. " RM ,Repeat mode enable bit" "Disabled,Enabled" newline bitfld.word 0x00 6. " DLB ,Digital loop back enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " NIRS ,I2C reset enable bit" "Disabled,Enabled" newline bitfld.word 0x00 4. " STB ,Start byte mode enable" "Disabled,Enabled" newline bitfld.word 0x00 3. " FDF ,Free data format enable bit (excluding the acknowledge bit)" "Disabled,Enabled" newline bitfld.word 0x00 0.--2. " BC[2-0] ,Bit count" "8,,2,3,4,5,6,7" else group.word 0x24++0x01 line.word 0x00 "I2CMDR,I2C Mode Register" bitfld.word 0x00 14. " FREE ,Free running bit" "Disabled,Enabled" newline newline bitfld.word 0x00 10. " MST ,Master/slave mode bit" "Slave,Master" bitfld.word 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit" newline bitfld.word 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing" newline bitfld.word 0x00 5. " NIRS ,I2C reset enable bit" "Disabled,Enabled" newline bitfld.word 0x00 3. " FDF ,Free data format enable bit (excluding the acknowledge bit)" "Disabled,Enabled" newline bitfld.word 0x00 0.--2. " BC[2-0] ,Bit count" "8,,2,3,4,5,6,7" endif else if (((per.w(ad:0xFFF7D400+0x24))&0x608)==0x00) group.word 0x24++0x01 line.word 0x00 "I2CMDR,I2C Mode Register" bitfld.word 0x00 15. " NACKMOD ,No-acknowledge (NACK) mode" "Disabled,Enabled" bitfld.word 0x00 14. " FREE ,Free running bit" "Disabled,Enabled" newline bitfld.word 0x00 10. " MST ,Master/slave mode bit" "Slave,Master" bitfld.word 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit" newline bitfld.word 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing" newline bitfld.word 0x00 5. " nIRS ,I2C reset enable bit" "Disabled,Enabled" newline bitfld.word 0x00 3. " FDF ,Free data format enable bit (not supported in digital loop back mode [this.DLB = 1])" "Disabled,Enabled" newline bitfld.word 0x00 0.--2. " BC[2-0] ,Bit count" "9,,3,4,5,6,7,8" elif (((per.w(ad:0xFFF7D400+0x24))&0x608)==0x008) group.word 0x24++0x01 line.word 0x00 "I2CMDR,I2C Mode Register" bitfld.word 0x00 15. " NACKMOD ,No-acknowledge (NACK) mode" "Disabled,Enabled" bitfld.word 0x00 14. " FREE ,Free running bit" "Disabled,Enabled" newline bitfld.word 0x00 10. " MST ,Master/slave mode bit" "Slave,Master" bitfld.word 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit" newline bitfld.word 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing" newline bitfld.word 0x00 5. " nIRS ,I2C reset enable bit" "Disabled,Enabled" newline bitfld.word 0x00 3. " FDF ,Free data format enable bit (not supported in digital loop back mode [this.DLB = 1])" "Disabled,Enabled" newline bitfld.word 0x00 0.--2. " BC[2-0] ,Bit count" "8,,2,3,4,5,6,7" elif (((per.w(ad:0xFFF7D400+0x24))&0x608)==0x408) group.word 0x24++0x01 line.word 0x00 "I2CMDR,I2C Mode Register" bitfld.word 0x00 15. " NACKMOD ,No-acknowledge (NACK) mode" "Disabled,Enabled" bitfld.word 0x00 14. " FREE ,Free running bit" "Disabled,Enabled" newline bitfld.word 0x00 13. " STT ,Start condition" "Disabled,Enabled" bitfld.word 0x00 11. " STP ,Stop condition" "Disabled,Enabled" newline bitfld.word 0x00 10. " MST ,Master/slave mode bit" "Slave,Master" bitfld.word 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit" newline bitfld.word 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing" bitfld.word 0x00 7. " RM ,Repeat mode enable bit" "Disabled,Enabled" newline bitfld.word 0x00 5. " nIRS ,I2C reset enable bit" "Disabled,Enabled" newline bitfld.word 0x00 4. " STB ,Start byte mode enable" "Disabled,Enabled" newline bitfld.word 0x00 3. " FDF ,Free data format enable bit (not supported in digital loop back mode [this.DLB = 1])" "Disabled,Enabled" newline bitfld.word 0x00 0.--2. " BC[2-0] ,Bit count" "8,,2,3,4,5,6,7" elif (((per.w(ad:0xFFF7D400+0x24))&0x608)==0x400) group.word 0x24++0x01 line.word 0x00 "I2CMDR,I2C Mode Register" bitfld.word 0x00 15. " NACKMOD ,No-acknowledge (NACK) mode" "Disabled,Enabled" bitfld.word 0x00 14. " FREE ,Free running bit" "Disabled,Enabled" newline bitfld.word 0x00 13. " STT ,Start condition" "Disabled,Enabled" bitfld.word 0x00 11. " STP ,Stop condition" "Disabled,Enabled" newline bitfld.word 0x00 10. " MST ,Master/slave mode bit" "Slave,Master" bitfld.word 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit" newline bitfld.word 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing" bitfld.word 0x00 7. " RM ,Repeat mode enable bit" "Disabled,Enabled" newline bitfld.word 0x00 5. " nIRS ,I2C reset enable bit" "Disabled,Enabled" newline bitfld.word 0x00 4. " STB ,Start byte mode enable" "Disabled,Enabled" newline bitfld.word 0x00 3. " FDF ,Free data format enable bit (not supported in digital loop back mode [this.DLB = 1])" "Disabled,Enabled" newline bitfld.word 0x00 0.--2. " BC[2-0] ,Bit count" "9,,3,4,5,6,7,8" elif (((per.w(ad:0xFFF7D400+0x24))&0x608)==0x600) group.word 0x24++0x01 line.word 0x00 "I2CMDR,I2C Mode Register" bitfld.word 0x00 15. " NACKMOD ,No-acknowledge (NACK) mode" "Disabled,Enabled" bitfld.word 0x00 14. " FREE ,Free running bit" "Disabled,Enabled" newline bitfld.word 0x00 13. " STT ,Start condition" "Disabled,Enabled" bitfld.word 0x00 11. " STP ,Stop condition" "Disabled,Enabled" newline bitfld.word 0x00 10. " MST ,Master/slave mode bit" "Slave,Master" bitfld.word 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit" newline bitfld.word 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing" bitfld.word 0x00 7. " RM ,Repeat mode enable bit" "Disabled,Enabled" newline bitfld.word 0x00 6. " DLB ,Digital loop back enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " nIRS ,I2C reset enable bit" "Disabled,Enabled" newline bitfld.word 0x00 4. " STB ,Start byte mode enable" "Disabled,Enabled" newline bitfld.word 0x00 3. " FDF ,Free data format enable bit (not supported in digital loop back mode [this.DLB = 1])" "Disabled,Enabled" newline bitfld.word 0x00 0.--2. " BC[2-0] ,Bit count" "9,,3,4,5,6,7,8" elif (((per.w(ad:0xFFF7D400+0x24))&0x608)==0x608) group.word 0x24++0x01 line.word 0x00 "I2CMDR,I2C Mode Register" bitfld.word 0x00 15. " NACKMOD ,No-acknowledge (NACK) mode" "Disabled,Enabled" bitfld.word 0x00 14. " FREE ,Free running bit" "Disabled,Enabled" newline bitfld.word 0x00 13. " STT ,Start condition" "Disabled,Enabled" bitfld.word 0x00 11. " STP ,Stop condition" "Disabled,Enabled" newline bitfld.word 0x00 10. " MST ,Master/slave mode bit" "Slave,Master" bitfld.word 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit" newline bitfld.word 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing" bitfld.word 0x00 7. " RM ,Repeat mode enable bit" "Disabled,Enabled" newline bitfld.word 0x00 6. " DLB ,Digital loop back enable bit" "Disabled,Enabled" bitfld.word 0x00 5. " nIRS ,I2C reset enable bit" "Disabled,Enabled" newline bitfld.word 0x00 4. " STB ,Start byte mode enable" "Disabled,Enabled" newline bitfld.word 0x00 3. " FDF ,Free data format enable bit (not supported in digital loop back mode [this.DLB = 1])" "Disabled,Enabled" newline bitfld.word 0x00 0.--2. " BC[2-0] ,Bit count" "8,,2,3,4,5,6,7" elif (((per.w(ad:0xFFF7D400+0x24))&0x608)==0x208) group.word 0x24++0x01 line.word 0x00 "I2CMDR,I2C Mode Register" bitfld.word 0x00 15. " NACKMOD ,No-acknowledge (NACK) mode" "Disabled,Enabled" bitfld.word 0x00 14. " FREE ,Free running bit" "Disabled,Enabled" newline bitfld.word 0x00 10. " MST ,Master/slave mode bit" "Slave,Master" bitfld.word 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit" newline bitfld.word 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing" newline bitfld.word 0x00 5. " nIRS ,I2C reset enable bit" "Disabled,Enabled" newline bitfld.word 0x00 3. " FDF ,Free data format enable bit" "Disabled,Enabled" newline bitfld.word 0x00 0.--2. " BC ,Bit count" "8,,2,3,4,5,6,7" else group.word 0x24++0x01 line.word 0x00 "I2CMDR,I2C Mode Register" bitfld.word 0x00 15. " NACKMOD ,No-acknowledge (NACK) mode" "Disabled,Enabled" bitfld.word 0x00 14. " FREE ,Free running bit" "Disabled,Enabled" newline bitfld.word 0x00 10. " MST ,Master/slave mode bit" "Slave,Master" bitfld.word 0x00 9. " TRX ,Transmit/receive bit" "Receive,Transmit" newline bitfld.word 0x00 8. " XA ,Expand address enable bit" "7-bit addressing,10-bit addressing" newline bitfld.word 0x00 5. " nIRS ,I2C reset enable bit" "Disabled,Enabled" newline bitfld.word 0x00 3. " FDF ,Free data format enable bit (not supported in digital loop back mode [this.DLB = 1])" "Disabled,Enabled" newline bitfld.word 0x00 0.--2. " BC[2-0] ,Bit count" "9,,3,4,5,6,7,8" endif endif hgroup.word 0x28++0x01 hide.word 0x00 "I2CIVR,I2C Interrupt Vector Register" in group.word 0x2C++0x01 line.word 0x00 "I2CEMDR,I2C Extended Mode Register" bitfld.word 0x00 1. " IGNACK ,Ignore NACK mode" "Disabled,Enabled" bitfld.word 0x00 0. " BCM ,Backwards compatibility mode" "Disabled,Enabled" group.word 0x30++0x01 line.word 0x00 "I2CPSC,I2C Prescale Register" hexmask.word.byte 0x00 0.--7. 1. " PSC ,Prescale" rgroup.word 0x34++0x01 line.word 0x00 "I2CPID1,I2C Peripheral ID Register 1" hexmask.word.byte 0x00 8.--15. 1. " CLASS ,Peripheral class" hexmask.word.byte 0x00 0.--7. 1. " REVISION ,Revision level of the I2C" sif cpuis("TMS570LS3137-EP") rgroup.word 0x38++0x01 line.word 0x00 "I2CPID2,I2C Peripheral ID Register 2" hexmask.word.byte 0x00 0.--7. 1. " TYPE ,Peripheral type" else group.word 0x38++0x01 line.word 0x00 "I2CPID2,I2C Peripheral ID Register 2" hexmask.word.byte 0x00 0.--7. 1. " TYPE ,Peripheral type" endif group.word 0x3C++0x01 line.word 0x00 "I2CDMACR,I2C DMA Control Register" bitfld.word 0x00 1. " TXDMAEN ,Transmitter DMA enable" "Disabled,Enabled" bitfld.word 0x00 0. " RXDMAEN ,Receive DMA enable" "Disabled,Enabled" group.word 0x48++0x01 line.word 0x00 "I2CPFNC,I2C Pin Function Register" bitfld.word 0x00 0. " PINFUNC ,SDA and SCL pin function" "I2C,I/O" group.word 0x4C++0x01 line.word 0x00 "I2CPDIR,I2C Pin Direction Register" bitfld.word 0x00 1. " SDADIR ,SDA direction" "Input,Output" bitfld.word 0x00 0. " SCLDIR ,SCL direction" "Input,Output" rgroup.word 0x50++0x01 line.word 0x00 "I2CDIN,I2C Data Input Register" bitfld.word 0x00 1. " SDAIN ,Serial data in" "Low,High" bitfld.word 0x00 0. " SCLIN ,Serial clock data in" "Low,High" group.word 0x54++0x01 line.word 0x00 "I2CDOUT,I2C Data Output Register" bitfld.word 0x00 1. " SDAOUT ,SDA data output" "Low,High" bitfld.word 0x00 0. " SCLOUT ,SCL data output" "Low,High" group.word 0x58++0x01 line.word 0x00 "I2CD_SET/CLR,I2C Data Register" setclrfld.word 0x00 1. 0x00 1. 0x04 1. " SDA ,Serial data" "Not set,Set" setclrfld.word 0x00 0. 0x00 0. 0x04 0. " SCL ,Serial clock" "Not set,Set" group.word 0x60++0x01 line.word 0x00 "I2CPDR,I2C Pin Open Drain Register" bitfld.word 0x00 1. " SDAPDR ,SDA pin open drain disable" "No,Yes" bitfld.word 0x00 0. " SCLPDR ,SCL pin open drain disable" "No,Yes" group.word 0x64++0x01 line.word 0x00 "I2CPDIS,I2C Pull Disable Register" bitfld.word 0x00 1. " SDAPDIS ,SDA pull disable" "No,Yes" bitfld.word 0x00 0. " SCLPDIS ,SCL pull disable" "No,Yes" group.word 0x68++0x01 line.word 0x00 "I2CPSEL,I2C Pull Select Register" bitfld.word 0x00 1. " SDAPSEL ,SDA pull select" "Pull down,Pull up" bitfld.word 0x00 0. " SCLPSEL ,SCL pull select" "Pull down,Pull up" group.word 0x6C++0x01 line.word 0x00 "I2CSRS,I2C Pins Slew Rate Select Register" bitfld.word 0x00 1. " SDASRS ,SDA slew rate select" "Slow,Normal" bitfld.word 0x00 0. " SCLSRS ,SCL slew rate select" "Slow,Normal" width 0x0B tree.end sif (cpu()=="RM48L952-PGE"||cpu()=="RM48L952-ZWT"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L540-PGE"||cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM48L550-ZWT") tree "EMAC/MDIO (Ethernet Media Access Controller)" tree "EMAC Control Module Registers" base ad:0xFCF78800 width 16. rgroup.long 0x0++0x3 line.long 0x0 "REVID,Transmit Identification and Version Register" group.long 0x4++0x3 line.long 0x0 "SOFTRESET,EMAC Control Module Software Reset Register" bitfld.long 0x0 0. " RESET ,Software reset bit for the EMAC Control Module" "No reset,Reset" group.long 0xC++0x3 line.long 0x0 "INTCONTROL,EMAC Control Module Interrupt Control Register" bitfld.long 0x00 17. " C0TXPACEEN ,Enable pacing for TX interrupt pulse generation" "Disabled,Enabled" bitfld.long 0x00 16. " C0RXPACEEN ,Enable pacing for RX interrupt pulse generation" "Disabled,Enabled" textline " " hexmask.long.word 0x00 0.--11. 1. " INTPRESCALE ,Number of internal EMAC module reference clock" group.long 0x10++0x03 line.long 0x00 "C0RXTHRESHEN,EMAC Control Module Receive Threshold Interrupt Enable Register" bitfld.long 0x00 7. " RXCH7THRESHEN ,Enable C0RXTHRESHPULSE interrupt generation for RX Channel 7" "Disabled,Enabled" bitfld.long 0x00 6. " RXCH6THRESHEN ,Enable C0RXTHRESHPULSE interrupt generation for RX Channel 6" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " RXCH5THRESHEN ,Enable C0RXTHRESHPULSE interrupt generation for RX Channel 5" "Disabled,Enabled" bitfld.long 0x00 4. " RXCH4THRESHEN ,Enable C0RXTHRESHPULSE interrupt generation for RX Channel 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " RXCH3THRESHEN ,Enable C0RXTHRESHPULSE interrupt generation for RX Channel 3" "Disabled,Enabled" bitfld.long 0x00 2. " RXCH2THRESHEN ,Enable C0RXTHRESHPULSE interrupt generation for RX Channel 2" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " RXCH1THRESHEN ,Enable C0RXTHRESHPULSE interrupt generation for RX Channel 1" "Disabled,Enabled" bitfld.long 0x00 0. " RXCH0THRESHEN ,Enable C0RXTHRESHPULSE interrupt generation for RX Channel 0" "Disabled,Enabled" group.long 0x14++0x03 line.long 0x00 "C0TXEN,EMAC Control Module Receive Interrupt Enable Registers" bitfld.long 0x00 7. " RXCH7EN ,Enable C0RXPULSE interrupt generation for RX Channel 7" "Disabled,Enabled" bitfld.long 0x00 6. " RXCH6EN ,Enable C0RXPULSE interrupt generation for RX Channel 6" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " RXCH5EN ,Enable C0RXPULSE interrupt generation for RX Channel 5" "Disabled,Enabled" bitfld.long 0x00 4. " RXCH4EN ,Enable C0RXPULSE interrupt generation for RX Channel 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " RXCH3EN ,Enable C0RXPULSE interrupt generation for RX Channel 3" "Disabled,Enabled" bitfld.long 0x00 2. " RXCH2EN ,Enable C0RXPULSE interrupt generation for RX Channel 2" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " RXCH1EN ,Enable C0RXPULSE interrupt generation for RX Channel 1" "Disabled,Enabled" bitfld.long 0x00 0. " RXCH0EN ,Enable C0RXPULSE interrupt generation for RX Channel 0" "Disabled,Enabled" group.long 0x18++0x03 line.long 0x00 "C0RXEN,EMAC Control Module Transmit Interrupt Enable Registers" bitfld.long 0x00 7. " TXCH7EN ,Enable C0TXPULSE interrupt generation for TX Channel 7" "Disabled,Enabled" bitfld.long 0x00 6. " TXCH6EN ,Enable C0TXPULSE interrupt generation for TX Channel 6" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " TXCH5EN ,Enable C0TXPULSE interrupt generation for TX Channel 5" "Disabled,Enabled" bitfld.long 0x00 4. " TXCH4EN ,Enable C0TXPULSE interrupt generation for TX Channel 4" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " TXCH3EN ,Enable C0TXPULSE interrupt generation for TX Channel 3" "Disabled,Enabled" bitfld.long 0x00 2. " TXCH2EN ,Enable C0TXPULSE interrupt generation for TX Channel 2" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " TXCH1EN ,Enable C0TXPULSE interrupt generation for TX Channel 1" "Disabled,Enabled" bitfld.long 0x00 0. " TXCH0EN ,Enable C0TXPULSE interrupt generation for TX Channel 0" "Disabled,Enabled" group.long 0x1C++0x03 line.long 0x00 "C0MISCEN,EMAC Control Module Miscellaneous Interrupt Enable Registers" bitfld.long 0x00 3. " STATPENDEN ,Enable C0MISCPULSE interrupt generation when EMAC statistics interrupts are generated" "Disabled,Enabled" bitfld.long 0x00 2. " HOSTPENDEN ,Enable C0MISCPULSE interrupt generation when EMAC host interrupts are generated" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " LINKINT0EN ,Enable C0MISCPULSE interrupt generation when MDIO LINKINT0 interrupts" "Disabled,Enabled" bitfld.long 0x00 0. " USERINT0EN ,Enable C0MISCPULSE interrupt generation when MDIO USERINT0 interrupts" "Disabled,Enabled" group.long 0x40++0x03 line.long 0x00 "C0RXTHRESHSTAT,EMAC Control Module Receive Threshold Interrupt Status Registers" bitfld.long 0x00 7. " RXCH7THRESHSTAT ,Interrupt status for RX Channel 7 masked by the C0RXTHRESHEN register" "No interrupt,Interrupt" bitfld.long 0x00 6. " RXCH6THRESHSTAT ,Interrupt status for RX Channel 6 masked by the C0RXTHRESHEN register" "No interrupt,Interrupt" textline " " bitfld.long 0x00 5. " RXCH5THRESHSTAT ,Interrupt status for RX Channel 5 masked by the C0RXTHRESHEN register" "No interrupt,Interrupt" bitfld.long 0x00 4. " RXCH4THRESHSTAT ,Interrupt status for RX Channel 4 masked by the C0RXTHRESHEN register" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " RXCH3THRESHSTAT ,Interrupt status for RX Channel 3 masked by the C0RXTHRESHEN register" "No interrupt,Interrupt" bitfld.long 0x00 2. " RXCH2THRESHSTAT ,Interrupt status for RX Channel 2 masked by the C0RXTHRESHEN register" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " RXCH1THRESHSTAT ,Interrupt status for RX Channel 1 masked by the C0RXTHRESHEN register" "No interrupt,Interrupt" bitfld.long 0x00 0. " RXCH0THRESHSTAT ,Interrupt status for RX Channel 0 masked by the C0RXTHRESHEN register" "No interrupt,Interrupt" group.long 0x44++0x03 line.long 0x00 "C0RXSTAT,EMAC Control Module Receive Interrupt Status Registers" bitfld.long 0x00 7. " RXCH7STAT ,Interrupt status for RX Channel 7 masked by the C0RXEN register" "No interrupt,Interrupt" bitfld.long 0x00 6. " RXCH6STAT ,Interrupt status for RX Channel 6 masked by the C0RXEN register" "No interrupt,Interrupt" textline " " bitfld.long 0x00 5. " RXCH5STAT ,Interrupt status for RX Channel 5 masked by the C0RXEN register" "No interrupt,Interrupt" bitfld.long 0x00 4. " RXCH4STAT ,Interrupt status for RX Channel 4 masked by the C0RXEN register" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " RXCH3STAT ,Interrupt status for RX Channel 3 masked by the C0RXEN register" "No interrupt,Interrupt" bitfld.long 0x00 2. " RXCH2STAT ,Interrupt status for RX Channel 2 masked by the C0RXEN register" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " RXCH1STAT ,Interrupt status for RX Channel 1 masked by the C0RXEN register" "No interrupt,Interrupt" bitfld.long 0x00 0. " RXCH0STAT ,Interrupt status for RX Channel 0 masked by the C0RXEN register" "No interrupt,Interrupt" group.long 0x48++0x03 line.long 0x00 "C0TXSTAT,EMAC Control Module Transmit Interrupt Status Registers" bitfld.long 0x00 7. " TXCH7STAT ,Interrupt status for TX Channel 7 masked by the C0TXEN register" "No interrupt,Interrupt" bitfld.long 0x00 6. " TXCH6STAT ,Interrupt status for TX Channel 6 masked by the C0TXEN register" "No interrupt,Interrupt" textline " " bitfld.long 0x00 5. " TXCH5STAT ,Interrupt status for TX Channel 5 masked by the C0TXEN register" "No interrupt,Interrupt" bitfld.long 0x00 4. " TXCH4STAT ,Interrupt status for TX Channel 4 masked by the C0TXEN register" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " TXCH3STAT ,Interrupt status for TX Channel 3 masked by the C0TXEN register" "No interrupt,Interrupt" bitfld.long 0x00 2. " TXCH2STAT ,Interrupt status for TX Channel 2 masked by the C0TXEN register" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " TXCH1STAT ,Interrupt status for TX Channel 1 masked by the C0TXEN register" "No interrupt,Interrupt" bitfld.long 0x00 0. " TXCH0STAT ,Interrupt status for TX Channel 0 masked by the C0TXEN register" "No interrupt,Interrupt" group.long 0x4C++0x03 line.long 0x00 "C0MISCSTAT,EMAC Control Module Miscellaneous Interrupt Status Registers" bitfld.long 0x00 3. " STATPENDSTAT ,Interrupt status for EMAC STATPEND masked by the C0MISCEN register" "No interrupt,Interrupt" bitfld.long 0x00 2. " HOSTPENDSTAT ,Interrupt status for EMAC HOSTPEND masked by the C0MISCEN register" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " LINKINT0STAT ,Interrupt status for MDIO LINKINT0 masked by the C0MISCEN register" "No interrupt,Interrupt" bitfld.long 0x00 0. " USERINT0STAT ,Interrupt status for MDIO USERINT0 masked by the C0MISCEN register" "No interrupt,Interrupt" group.long 0x70++0x07 line.long 0x00 "C0RXIMAX,EMAC Control Module Receive Interrupts Per Millisecond Registers" bitfld.long 0x00 0.--5. " RXIMAX ,RXIMAX is the desired number of C0RXPULSE interrupts generated per millisecond" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "C0TXIMAX,EMAC Control Module Transmit Interrupts Per Millisecond Registers" bitfld.long 0x04 0.--5. " TXIMAX ,TXIMAX is the desired number of C0RXPULSE interrupts generated per millisecond" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" width 11. tree.end tree "MDIO (Management Data Input/Output)" base ad:0xFCF78900 width 18. rgroup.long 0x0++0x3 line.long 0x0 "REV,MDIO Version Register" sif (cpuis("TMS570LS1227*")) group.long 0x4++0x3 line.long 0x0 "CONTROL,MDIO Control Register" rbitfld.long 0x00 31. " IDLE ,State machine IDLE status bit" "Not idle,Idle" bitfld.long 0x00 30. " ENABLE ,State machine enable control bit" "Disabled,Enabled" textline " " rbitfld.long 0x00 24.--28. " HIGHEST_USER_CHANNEL ,Highest user channel that is available in the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " PREAMBLE ,Preamble disable" "No,Yes" textline " " eventfld.long 0x00 19. " FAULT ,Fault indicator" "No error,Error" bitfld.long 0x00 18. " FAULTENB ,Fault detect enable" "Disabled,Enabled" textline " " hexmask.long.word 0x00 0.--15. 1. " CLKDIV ,Clock Divider bits" else group.long 0x4++0x3 line.long 0x0 "CONTROL,MDIO Control Register" bitfld.long 0x00 31. " IDLE ,State machine IDLE status bit" "Not idle,Idle" bitfld.long 0x00 30. " ENABLE ,State machine enable control bit" "Disabled,Enabled" textline " " bitfld.long 0x00 24.--28. " HIGHEST_USER_CHANNEL ,Highest user channel that is available in the module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " PREAMBLE ,Preamble disable" "No,Yes" textline " " eventfld.long 0x00 19. " FAULT ,Fault indicator" "No error,Error" bitfld.long 0x00 18. " FAULTENB ,Fault detect enable" "Disabled,Enabled" textline " " hexmask.long.word 0x00 0.--15. 1. " CLKDIV ,Clock Divider bits" endif group.long 0x8++0x3 line.long 0x0 "ALIVE,PHY Acknowledge Status Register" eventfld.long 0x00 31. " ALIVE[31] ,PHY access acknowledge bit 31" "Not acknowledged,Acknowledged" eventfld.long 0x00 30. " ALIVE[30] ,PHY access acknowledge bit 30" "Not acknowledged,Acknowledged" textline " " eventfld.long 0x00 29. " ALIVE[29] ,PHY access acknowledge bit 29" "Not acknowledged,Acknowledged" eventfld.long 0x00 28. " ALIVE[28] ,PHY access acknowledge bit 28" "Not acknowledged,Acknowledged" textline " " eventfld.long 0x00 27. " ALIVE[27] ,PHY access acknowledge bit 27" "Not acknowledged,Acknowledged" eventfld.long 0x00 26. " ALIVE[26] ,PHY access acknowledge bit 26" "Not acknowledged,Acknowledged" textline " " eventfld.long 0x00 25. " ALIVE[25] ,PHY access acknowledge bit 25" "Not acknowledged,Acknowledged" eventfld.long 0x00 24. " ALIVE[24] ,PHY access acknowledge bit 24" "Not acknowledged,Acknowledged" textline " " eventfld.long 0x00 23. " ALIVE[23] ,PHY access acknowledge bit 23" "Not acknowledged,Acknowledged" eventfld.long 0x00 22. " ALIVE[22] ,PHY access acknowledge bit 22" "Not acknowledged,Acknowledged" textline " " eventfld.long 0x00 21. " ALIVE[21] ,PHY access acknowledge bit 21" "Not acknowledged,Acknowledged" eventfld.long 0x00 20. " ALIVE[20] ,PHY access acknowledge bit 20" "Not acknowledged,Acknowledged" textline " " eventfld.long 0x00 19. " ALIVE[19] ,PHY access acknowledge bit 19" "Not acknowledged,Acknowledged" eventfld.long 0x00 18. " ALIVE[18] ,PHY access acknowledge bit 18" "Not acknowledged,Acknowledged" textline " " eventfld.long 0x00 17. " ALIVE[17] ,PHY access acknowledge bit 17" "Not acknowledged,Acknowledged" eventfld.long 0x00 16. " ALIVE[16] ,PHY access acknowledge bit 16" "Not acknowledged,Acknowledged" textline " " eventfld.long 0x00 15. " ALIVE[15] ,PHY access acknowledge bit 15" "Not acknowledged,Acknowledged" eventfld.long 0x00 14. " ALIVE[14] ,PHY access acknowledge bit 14" "Not acknowledged,Acknowledged" textline " " eventfld.long 0x00 13. " ALIVE[13] ,PHY access acknowledge bit 13" "Not acknowledged,Acknowledged" eventfld.long 0x00 12. " ALIVE[12] ,PHY access acknowledge bit 12" "Not acknowledged,Acknowledged" textline " " eventfld.long 0x00 11. " ALIVE[11] ,PHY access acknowledge bit 11" "Not acknowledged,Acknowledged" eventfld.long 0x00 10. " ALIVE[10] ,PHY access acknowledge bit 10" "Not acknowledged,Acknowledged" textline " " eventfld.long 0x00 9. " ALIVE[9] ,PHY access acknowledge bit 9" "Not acknowledged,Acknowledged" eventfld.long 0x00 8. " ALIVE[8] ,PHY access acknowledge bit 8" "Not acknowledged,Acknowledged" textline " " eventfld.long 0x00 7. " ALIVE[7] ,PHY access acknowledge bit 7" "Not acknowledged,Acknowledged" eventfld.long 0x00 6. " ALIVE[6] ,PHY access acknowledge bit 6" "Not acknowledged,Acknowledged" textline " " eventfld.long 0x00 5. " ALIVE[5] ,PHY access acknowledge bit 5" "Not acknowledged,Acknowledged" eventfld.long 0x00 4. " ALIVE[4] ,PHY access acknowledge bit 4" "Not acknowledged,Acknowledged" textline " " eventfld.long 0x00 3. " ALIVE[3] ,PHY access acknowledge bit 3" "Not acknowledged,Acknowledged" eventfld.long 0x00 2. " ALIVE[2] ,PHY access acknowledge bit 2" "Not acknowledged,Acknowledged" textline " " eventfld.long 0x00 1. " ALIVE[1] ,PHY access acknowledge bit 1" "Not acknowledged,Acknowledged" eventfld.long 0x00 0. " ALIVE[0] ,PHY access acknowledge bit 0" "Not acknowledged,Acknowledged" rgroup.long 0xC++0x3 line.long 0x0 "LINK,PHY Link Status Register" bitfld.long 0x00 31. " LINK[31] ,PHY read transaction acknowledge bit 31" "Not acknowledged,Acknowledged" bitfld.long 0x00 30. " LINK[30] ,PHY read transaction acknowledge bit 30" "Not acknowledged,Acknowledged" textline " " bitfld.long 0x00 29. " LINK[29] ,PHY read transaction acknowledge bit 29" "Not acknowledged,Acknowledged" bitfld.long 0x00 28. " LINK[28] ,PHY read transaction acknowledge bit 28" "Not acknowledged,Acknowledged" textline " " bitfld.long 0x00 27. " LINK[27] ,PHY read transaction acknowledge bit 27" "Not acknowledged,Acknowledged" bitfld.long 0x00 26. " LINK[26] ,PHY read transaction acknowledge bit 26" "Not acknowledged,Acknowledged" textline " " bitfld.long 0x00 25. " LINK[25] ,PHY read transaction acknowledge bit 25" "Not acknowledged,Acknowledged" bitfld.long 0x00 24. " LINK[24] ,PHY read transaction acknowledge bit 24" "Not acknowledged,Acknowledged" textline " " bitfld.long 0x00 23. " LINK[23] ,PHY read transaction acknowledge bit 23" "Not acknowledged,Acknowledged" bitfld.long 0x00 22. " LINK[22] ,PHY read transaction acknowledge bit 22" "Not acknowledged,Acknowledged" textline " " bitfld.long 0x00 21. " LINK[21] ,PHY read transaction acknowledge bit 21" "Not acknowledged,Acknowledged" bitfld.long 0x00 20. " LINK[20] ,PHY read transaction acknowledge bit 20" "Not acknowledged,Acknowledged" textline " " bitfld.long 0x00 19. " LINK[19] ,PHY read transaction acknowledge bit 19" "Not acknowledged,Acknowledged" bitfld.long 0x00 18. " LINK[18] ,PHY read transaction acknowledge bit 18" "Not acknowledged,Acknowledged" textline " " bitfld.long 0x00 17. " LINK[17] ,PHY read transaction acknowledge bit 17" "Not acknowledged,Acknowledged" bitfld.long 0x00 16. " LINK[16] ,PHY read transaction acknowledge bit 16" "Not acknowledged,Acknowledged" textline " " bitfld.long 0x00 15. " LINK[15] ,PHY read transaction acknowledge bit 15" "Not acknowledged,Acknowledged" bitfld.long 0x00 14. " LINK[14] ,PHY read transaction acknowledge bit 14" "Not acknowledged,Acknowledged" textline " " bitfld.long 0x00 13. " LINK[13] ,PHY read transaction acknowledge bit 13" "Not acknowledged,Acknowledged" bitfld.long 0x00 12. " LINK[12] ,PHY read transaction acknowledge bit 12" "Not acknowledged,Acknowledged" textline " " bitfld.long 0x00 11. " LINK[11] ,PHY read transaction acknowledge bit 11" "Not acknowledged,Acknowledged" bitfld.long 0x00 10. " LINK[10] ,PHY read transaction acknowledge bit 10" "Not acknowledged,Acknowledged" textline " " bitfld.long 0x00 9. " LINK[9] ,PHY read transaction acknowledge bit 9" "Not acknowledged,Acknowledged" bitfld.long 0x00 8. " LINK[8] ,PHY read transaction acknowledge bit 8" "Not acknowledged,Acknowledged" textline " " bitfld.long 0x00 7. " LINK[7] ,PHY read transaction acknowledge bit 7" "Not acknowledged,Acknowledged" bitfld.long 0x00 6. " LINK[6] ,PHY read transaction acknowledge bit 6" "Not acknowledged,Acknowledged" textline " " bitfld.long 0x00 5. " LINK[5] ,PHY read transaction acknowledge bit 5" "Not acknowledged,Acknowledged" bitfld.long 0x00 4. " LINK[4] ,PHY read transaction acknowledge bit 4" "Not acknowledged,Acknowledged" textline " " bitfld.long 0x00 3. " LINK[3] ,PHY read transaction acknowledge bit 3" "Not acknowledged,Acknowledged" bitfld.long 0x00 2. " LINK[2] ,PHY read transaction acknowledge bit 2" "Not acknowledged,Acknowledged" textline " " bitfld.long 0x00 1. " LINK[1] ,PHY read transaction acknowledge bit 1" "Not acknowledged,Acknowledged" bitfld.long 0x00 0. " LINK[0] ,PHY read transaction acknowledge bit 0" "Not acknowledged,Acknowledged" group.long 0x10++0x3 line.long 0x0 "LINKINTRAW,MDIO Link Interrupt Raw Register" eventfld.long 0x00 1. " USERPHY1 ,MDIO Link change event raw value" "Not changed,Changed" eventfld.long 0x00 0. " USERPHY0 ,MDIO Link change event raw value" "Not changed,Changed" group.long 0x14++0x3 line.long 0x0 "LINKINTMASKED,MDIO Link Interrupt Masked Register" eventfld.long 0x00 1. " USERPHY1 ,MDIO Link change interrupt masked value" "Not changed,Changed" eventfld.long 0x00 0. " USERPHY0 ,MDIO Link change interrupt masked value" "Not changed,Changed" group.long 0x20++0x3 line.long 0x0 "USERINTRAW,MDIO User Interrupt Raw Register" eventfld.long 0x00 1. " USERACCESS1 ,MDIO User command complete event bit" "Not completed,Completed" eventfld.long 0x00 0. " USERACCESS0 ,MDIO User command complete event bit" "Not completed,Completed" group.long 0x24++0x3 line.long 0x0 "USERINTMASKED,MDIO User Interrupt Masked Register Set/Clr" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " USERACCESS1_set/clr ,Masked value of MDIO User command complete interrupt" "Not completed,Completed" setclrfld.long 0x00 0. 0x04 0. 0x08 0. " USERACCESS0_set/clr ,Masked value of MDIO User command complete interrupt" "Not completed,Completed" group.long 0x80++0x3 line.long 0x0 "USERACCESS0,MDIO User Access Register 0" bitfld.long 0x0 31. " GO ,Writing a 1 causes MDIO state machine to start an MDIO access sequence" "0,1" bitfld.long 0x0 30. " WRITE ,Write Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 29. " ACK ,PHY ACK of read transaction" "0,1" bitfld.long 0x0 21.--25. " REGADR ,Register Address. Specifies PHY register to be accessed for transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 16.--20. " PHYADR ,PHY Address. Specifies PHY to be accessed for transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 0.--15. 1. " DATA ,User Data. Data to be read or written to PHY register" group.long 0x84++0x3 line.long 0x0 "USERPHYSEL0,MDIO User PHY Select REG0" bitfld.long 0x0 7. " LINKSEL ,Link status determination; 1 to determine link status using MLINK pin" "0,1" bitfld.long 0x0 6. " LINKINTENB ,Link change interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x0 0.--4. " PHYADRMON ,Register Address. Specifies PHY register to be accessed for transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x88++0x3 line.long 0x0 "USERACCESS1,MDIO User Access Register 1" bitfld.long 0x0 31. " GO ,Writing a 1 causes MDIO state machine to start an MDIO access sequence" "0,1" bitfld.long 0x0 30. " WRITE ,Write Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 29. " ACK ,PHY ACK of read transaction" "0,1" bitfld.long 0x0 21.--25. " REGADR ,Register Address. Specifies PHY register to be accessed for transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0 16.--20. " PHYADR ,PHY Address. Specifies PHY to be accessed for transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x0 0.--15. 1. " DATA ,User Data. Data to be read or written to PHY register" group.long 0x8C++0x3 line.long 0x0 "USERPHYSEL1,MDIO User PHY Select REG1" bitfld.long 0x0 7. " LINKSEL ,Link status determination; 1 to determine link status using MLINK pin" "0,1" bitfld.long 0x0 6. " LINKINTENB ,Link change interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x0 0.--4. " PHYADRMON ,Register Address. Specifies PHY register to be accessed for transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 11. tree.end tree "EMAC (Ethernet Media Access Controller)" base ad:0xFCF78000 width 19. rgroup.long 0x0++0x3 line.long 0x0 "TXREVID,Transmit Identification and Version Register" group.long 0x4++0x3 line.long 0x0 "TXCONTROL,Transmit Control Register" bitfld.long 0x0 0. " TXEN ,Transmit enable" "Disabled,Enabled" group.long 0x8++0x3 line.long 0x0 "TXTEARDOWN,Transmit Teardown Register" bitfld.long 0x0 0.--2. " TXTDNCH ,TX teardown channed" "0,1,2,3,4,5,6,7" rgroup.long 0x10++0x3 line.long 0x0 "RXREVID,RX Identification and Version Register" group.long 0x14++0x3 line.long 0x0 "RXCONTROL,RX Control Register" bitfld.long 0x0 0. " RXEN ,RX DMA enable" "Disabled,Enabled" group.long 0x18++0x3 line.long 0x0 "RXTEARDOWN,RX Teardown Register" bitfld.long 0x0 0.--2. " RXTDNCH ,RX teardown channel" "0,1,2,3,4,5,6,7" rgroup.long 0x80++0x3 line.long 0x0 "TXINTSTATRAW,Transmit Interrupt Status Register" bitfld.long 0x0 7. " TX7PEND ,TX7PEND raw interrupt read (before mask)" "No interrupt,Interrupt" bitfld.long 0x0 6. " TX6PEND ,TX6PEND raw interrupt read (before mask)" "No interrupt,Interrupt" textline " " bitfld.long 0x0 5. " TX5PEND ,TX5PEND raw interrupt read (before mask)" "No interrupt,Interrupt" bitfld.long 0x0 4. " TX4PEND ,TX4PEND raw interrupt read (before mask)" "No interrupt,Interrupt" textline " " bitfld.long 0x0 3. " TX3PEND ,TX3PEND raw interrupt read (before mask)" "No interrupt,Interrupt" bitfld.long 0x0 2. " TX2PEND ,TX2PEND raw interrupt read (before mask)" "No interrupt,Interrupt" textline " " bitfld.long 0x0 1. " TX1PEND ,TX1PEND raw interrupt read (before mask)" "No interrupt,Interrupt" bitfld.long 0x0 0. " TX0PEND ,TX0PEND raw interrupt read (before mask)" "No interrupt,Interrupt" group.long 0x84++0x3 line.long 0x0 "TXINTSTATMASKED,Transmit Interrupt Status Register Masked" setclrfld.long 0x0 7. 0x4 7. 0x8 7. " TX7PEND_SETCLR ,TX7PEND masked interrupt read" "No interrupt,Interrupt" setclrfld.long 0x0 6. 0x4 6. 0x8 6. " TX6PEND_SETCLR ,TX6PEND masked interrupt read" "No interrupt,Interrupt" textline " " setclrfld.long 0x0 5. 0x4 5. 0x8 5. " TX5PEND_SETCLR ,TX5PEND masked interrupt read" "No interrupt,Interrupt" setclrfld.long 0x0 4. 0x4 4. 0x8 4. " TX4PEND_SETCLR ,TX4PEND masked interrupt read" "No interrupt,Interrupt" textline " " setclrfld.long 0x0 3. 0x4 3. 0x8 3. " TX3PEND_SETCLR ,TX3PEND masked interrupt read" "No interrupt,Interrupt" setclrfld.long 0x0 2. 0x4 2. 0x8 2. " TX2PEND_SETCLR ,TX2PEND masked interrupt read" "No interrupt,Interrupt" textline " " setclrfld.long 0x0 1. 0x4 1. 0x8 1. " TX1PEND_SETCLR ,TX1PEND masked interrupt read" "No interrupt,Interrupt" setclrfld.long 0x0 0. 0x4 0. 0x8 0. " TX0PEND_SETCLR ,TX0PEND masked interrupt read" "No interrupt,Interrupt" sif (cpuis("TMS570LS1227*")) rgroup.long 0x90++0x3 else group.long 0x90++0x3 endif line.long 0x0 "MACINVECTOR,MAC Input Vector Register" bitfld.long 0x0 27. " STATPEND ,Status Pending" "0,1" bitfld.long 0x0 26. " HOSTPEND ,Host Pending" "0,1" textline " " bitfld.long 0x0 25. " LINKINT0 ,MDIO Link Int" "0,1" bitfld.long 0x0 24. " USERINT0 ,MDIO User Int" "0,1" textline " " hexmask.long.byte 0x0 16.--23. 1. " TXPEND ,TX Pend[7:0]" hexmask.long.byte 0x0 8.--15. 1. " RXTHRESHPEND ,RX Thresh Pend[7:0]" textline " " hexmask.long.byte 0x0 0.--7. 1. " RXPEND ,RX Pend[7:0]" group.long 0x94++0x3 line.long 0x0 "MACEOIVECTOR,MAC End of Interrupt Vector" bitfld.long 0x00 0.--4. " INTVECT ,MAC End Of Interrupt Vector" "C0RXTHRESH,C0RX,C0TX,C0MISC,C1RXTHRESH,C1RX,C1TX,C1MISC,C2RXTHRESH,C2RX,C2TX,C2MISC,?..." sif (cpuis("TMS570LS1227*")) rgroup.long 0xA0++0x3 else group.long 0xA0++0x3 endif line.long 0x0 "RXINTSTATRAW,Receive Interrupt Status Register Raw" bitfld.long 0x0 15. " RX7THRESHPEND ,RX7THRESHPEND raw interrupt read (before mask)" "No interrupt,Interrupt" bitfld.long 0x0 14. " RX6THRESHPEND ,RX6THRESHPEND raw interrupt read (before mask)" "No interrupt,Interrupt" bitfld.long 0x0 13. " RX5THRESHPEND ,RX5THRESHPEND raw interrupt read (before mask)" "No interrupt,Interrupt" textline " " bitfld.long 0x0 12. " RX4THRESHPEND ,RX4THRESHPEND raw interrupt read (before mask)" "No interrupt,Interrupt" bitfld.long 0x0 11. " RX3THRESHPEND ,RX3THRESHPEND raw interrupt read (before mask)" "No interrupt,Interrupt" bitfld.long 0x0 10. " RX2THRESHPEND ,RX2THRESHPEND raw interrupt read (before mask)" "No interrupt,Interrupt" textline " " bitfld.long 0x0 9. " RX1THRESHPEND ,RX1THRESHPEND raw interrupt read (before mask)" "No interrupt,Interrupt" bitfld.long 0x0 8. " RX0THRESHPEND ,RX0THRESHPEND raw interrupt read (before mask)" "No interrupt,Interrupt" bitfld.long 0x0 7. " RX7PEND ,RX7PEND raw interrupt read (before mask)" "No interrupt,Interrupt" textline " " bitfld.long 0x0 6. " RX6PEND ,RX6PEND raw interrupt read (before mask)" "No interrupt,Interrupt" bitfld.long 0x0 5. " RX5PEND ,RX5PEND raw interrupt read (before mask)" "No interrupt,Interrupt" bitfld.long 0x0 4. " RX4PEND ,RX4PEND raw interrupt read (before mask)" "No interrupt,Interrupt" textline " " bitfld.long 0x0 3. " RX3PEND ,RX3PEND raw interrupt read (before mask)" "No interrupt,Interrupt" bitfld.long 0x0 2. " RX2PEND ,RX2PEND raw interrupt read (before mask)" "No interrupt,Interrupt" bitfld.long 0x0 1. " RX1PEND ,RX1PEND raw interrupt read (before mask)" "No interrupt,Interrupt" textline " " bitfld.long 0x0 0. " RX0PEND ,RX0PEND raw interrupt read (before mask)" "No interrupt,Interrupt" group.long 0xA4++0x3 line.long 0x0 "RXINTSTATMASKED,Receive Interrupt Status Register Masked" setclrfld.long 0x0 15. 0x4 15. 0x8 15. " RX7THRESHPEND_SETCLR ,RX7THRESHPEND masked interrupt read" "No interrupt,Interrupt" setclrfld.long 0x0 14. 0x4 14. 0x8 14. " RX6THRESHPEND_SETCLR ,RX6THRESHPEND masked interrupt read" "No interrupt,Interrupt" setclrfld.long 0x0 13. 0x4 13. 0x8 13. " RX5THRESHPEND_SETCLR ,RX5THRESHPEND masked interrupt read" "No interrupt,Interrupt" textline " " setclrfld.long 0x0 12. 0x4 12. 0x8 12. " RX4THRESHPEND_SETCLR ,RX4THRESHPEND masked interrupt read" "No interrupt,Interrupt" setclrfld.long 0x0 11. 0x4 11. 0x8 11. " RX3THRESHPEND_SETCLR ,RX3THRESHPEND masked interrupt read" "No interrupt,Interrupt" setclrfld.long 0x0 10. 0x4 10. 0x8 10. " RX2THRESHPEND_SETCLR ,RX2THRESHPEND masked interrupt read" "No interrupt,Interrupt" textline " " setclrfld.long 0x0 9. 0x4 9. 0x8 9. " RX1THRESHPEND_SETCLR ,RX1THRESHPEND masked interrupt read" "No interrupt,Interrupt" setclrfld.long 0x0 8. 0x4 8. 0x8 8. " RX0THRESHPEND_SETCLR ,RX0THRESHPEND masked interrupt read" "No interrupt,Interrupt" setclrfld.long 0x0 7. 0x4 7. 0x8 7. " RX7PEND_SETCLR ,RX7PEND masked interrupt read" "No interrupt,Interrupt" textline " " setclrfld.long 0x0 6. 0x4 6. 0x8 6. " RX6PEND_SETCLR ,RX6PEND masked interrupt read" "No interrupt,Interrupt" setclrfld.long 0x0 5. 0x4 5. 0x8 5. " RX5PEND_SETCLR ,RX5PEND masked interrupt read" "No interrupt,Interrupt" setclrfld.long 0x0 4. 0x4 4. 0x8 4. " RX4PEND_SETCLR ,RX4PEND masked interrupt read" "No interrupt,Interrupt" textline " " setclrfld.long 0x0 3. 0x4 3. 0x8 3. " RX3PEND_SETCLR ,RX3PEND masked interrupt read" "No interrupt,Interrupt" setclrfld.long 0x0 2. 0x4 2. 0x8 2. " RX2PEND_SETCLR ,RX2PEND masked interrupt read" "No interrupt,Interrupt" setclrfld.long 0x0 1. 0x4 1. 0x8 1. " RX1PEND_SETCLR ,RX1PEND masked interrupt read" "No interrupt,Interrupt" textline " " setclrfld.long 0x0 0. 0x4 0. 0x8 0. " RX0PEND_SETCLR ,RX0PEND masked interrupt read" "No interrupt,Interrupt" rgroup.long 0xB0++0x3 line.long 0x0 "MACINTSTATRAW,MAC Interrupt Status Register Raw (Unmasked)" bitfld.long 0x0 1. " HOSTPEND ,Host pending interrupt (HOSTPEND); raw interrupt read (before mask)" "No interrupt,Interrupt" bitfld.long 0x0 0. " STATPEND ,Statistics pending interrupt (STATPEND); raw interrupt read (before mask)" "No interrupt,Interrupt" group.long 0xB4++0x3 line.long 0x0 "MACINTSTATMASKED,MAC Interrupt Status Register Masked" setclrfld.long 0x0 1. 0x4 1. 0x8 1. " HOSTPEND_SETCLR ,Host pending interrupt (HOSTPEND); masked interrupt read" "No interrupt,Interrupt" setclrfld.long 0x0 0. 0x4 0. 0x8 0. " STATPEND_SETCLR ,Statistics pending interrupt (STATPEND); masked interrupt read" "No interrupt,Interrupt" group.long 0x100++0x3 line.long 0x0 "RXMBPENABLE,Receive Multicast/Broadcast/Promiscuous Channel Enable Register" bitfld.long 0x0 30. " RXPASSCRC ,Pass receive CRC enable" "Disabled,Enabled" bitfld.long 0x0 29. " RXQOSEN ,Receive quality of service enable" "Disabled,Enabled" bitfld.long 0x0 28. " RXNOCHAIN ,Receive no buffer chaining" "Multiple,Single" textline " " bitfld.long 0x0 24. " RXCMFEN ,Receive copy MAC control frames enable" "Disabled,Enabled" bitfld.long 0x0 23. " RXCSFEN ,Receive copy short frames enable" "Disabled,Enabled" bitfld.long 0x0 22. " RXCEFEN ,Receive copy error frames enable" "Disabled,Enabled" textline " " bitfld.long 0x0 21. " RXCAFEN ,Receive copy all frames enable" "Disabled,Enabled" bitfld.long 0x0 16.--18. " RXPROMCH ,Receive promiscuous channel select" "0,1,2,3,4,5,6,7" bitfld.long 0x0 13. " RXBROADEN ,Receive broadcast enable" "Disabled,Enabled" textline " " bitfld.long 0x0 8.--10. " RXBROADCH ,Receive broadcast channel select" "0,1,2,3,4,5,6,7" bitfld.long 0x0 5. " RXMULTEN ,RX multicast enable" "Disabled,Enabled" bitfld.long 0x0 0.--2. " RXMULTCH ,RX multicast channel select" "0,1,2,3,4,5,6,7" group.long 0x104++0x3 line.long 0x0 "RXUNICASTSET,Receive Unicast Enable Set Register" bitfld.long 0x0 7. " RXCH7EN ,RX channel 7 unicast enable set" "No effect,Set" bitfld.long 0x0 6. " RXCH6EN ,RX channel 6 unicast enable set" "No effect,Set" bitfld.long 0x0 5. " RXCH5EN ,RX channel 5 unicast enable set" "No effect,Set" textline " " bitfld.long 0x0 4. " RXCH4EN ,RX channel 4 unicast enable set" "No effect,Set" bitfld.long 0x0 3. " RXCH3EN ,RX channel 3 unicast enable set" "No effect,Set" bitfld.long 0x0 2. " RXCH2EN ,RX channel 2 unicast enable set" "No effect,Set" textline " " bitfld.long 0x0 1. " RXCH1EN ,RX channel 1 unicast enable set" "No effect,Set" bitfld.long 0x0 0. " RXCH0EN ,RX channel 0 unicast enable set" "No effect,Set" group.long 0x108++0x3 line.long 0x0 "RXUNICASTCLEAR,Receive Unicast Clear Register" bitfld.long 0x0 7. " RXCH7EN ,RX channel 7 unicast enable clear" "No effect,Clear" bitfld.long 0x0 6. " RXCH6EN ,RX channel 6 unicast enable clear" "No effect,Clear" bitfld.long 0x0 5. " RXCH5EN ,RX channel 5 unicast enable clear" "No effect,Clear" textline " " bitfld.long 0x0 4. " RXCH4EN ,RX channel 4 unicast enable clear" "No effect,Clear" bitfld.long 0x0 3. " RXCH3EN ,RX channel 3 unicast enable clear" "No effect,Clear" bitfld.long 0x0 2. " RXCH2EN ,RX channel 2 unicast enable clear" "No effect,Clear" textline " " bitfld.long 0x0 1. " RXCH1EN ,RX channel 1 unicast enable clear" "No effect,Clear" bitfld.long 0x0 0. " RXCH0EN ,RX channel 0 unicast enable clear" "No effect,Clear" group.long 0x10C++0x3 line.long 0x0 "RXMAXLEN,Receive Maximum Length Register" hexmask.long.word 0x0 0.--15. 1. " RXMAXLEN ,RX maximum frame length" group.long 0x110++0x3 line.long 0x0 "RXBUFFEROFFSET,Receive Buffer Offset Register" hexmask.long.word 0x0 0.--15. 1. " RXBUFFEROFFSET ,RX buffer offset value" group.long 0x114++0x3 line.long 0x0 "RXFILTERLOWTHRESH,Receive Filter Low Priority Frame Threshold Register" hexmask.long.byte 0x0 0.--7. 1. " RXFILTERTHRESH ,RX filter low threshold" group.long 0x120++0x3 line.long 0x0 "RX0FLOWTHRESH,Receive Channel 0 Flow Control Threshold Register" hexmask.long.byte 0x0 0.--7. 1. " RX0FLOWTHRESH ,RX flow threshold" group.long 0x124++0x3 line.long 0x0 "RX1FLOWTHRESH,Receive Channel 1 Flow Control Threshold Register" hexmask.long.byte 0x0 0.--7. 1. " RX1FLOWTHRESH ,RX flow threshold" group.long 0x128++0x3 line.long 0x0 "RX2FLOWTHRESH,Receive Channel 2 Flow Control Threshold Register" hexmask.long.byte 0x0 0.--7. 1. " RX2FLOWTHRESH ,RX flow threshold" group.long 0x12C++0x3 line.long 0x0 "RX3FLOWTHRESH,Receive Channel 3 Flow Control Threshold Register" hexmask.long.byte 0x0 0.--7. 1. " RX3FLOWTHRESH ,RX flow threshold" group.long 0x130++0x3 line.long 0x0 "RX4FLOWTHRESH,Receive Channel 4 Flow Control Threshold Register" hexmask.long.byte 0x0 0.--7. 1. " RX4FLOWTHRESH ,RX flow threshold" group.long 0x134++0x3 line.long 0x0 "RX5FLOWTHRESH,Receive Channel 5 Flow Control Threshold Register" hexmask.long.byte 0x0 0.--7. 1. " RX5FLOWTHRESH ,RX flow threshold" group.long 0x138++0x3 line.long 0x0 "RX6FLOWTHRESH,Receive Channel 6 Flow Control Threshold Register" hexmask.long.byte 0x0 0.--7. 1. " RX6FLOWTHRESH ,RX flow threshold" group.long 0x13C++0x3 line.long 0x0 "RX7FLOWTHRESH,Receive Channel 7 Flow Control Threshold Register" hexmask.long.byte 0x0 0.--7. 1. " RX7FLOWTHRESH ,RX flow threshold" group.long 0x140++0x3 line.long 0x0 "RX0FREEBUFFER,Receive Channel 0 Free Buffer Count Register" hexmask.long.word 0x0 0.--15. 1. " RX0FREEBUF ,RX free buffer count; Write to increment" group.long 0x144++0x3 line.long 0x0 "RX1FREEBUFFER,Receive Channel 1 Free Buffer Count Register" hexmask.long.word 0x0 0.--15. 1. " RX1FREEBUF ,RX free buffer count; Write to increment" group.long 0x148++0x3 line.long 0x0 "RX2FREEBUFFER,Receive Channel 2 Free Buffer Count Register" hexmask.long.word 0x0 0.--15. 1. " RX2FREEBUF ,RX free buffer count; Write to increment" group.long 0x14C++0x3 line.long 0x0 "RX3FREEBUFFER,Receive Channel 3 Free Buffer Count Register" hexmask.long.word 0x0 0.--15. 1. " RX3FREEBUF ,RX free buffer count; Write to increment" group.long 0x150++0x3 line.long 0x0 "RX4FREEBUFFER,Receive Channel 4 Free Buffer Count Register" hexmask.long.word 0x0 0.--15. 1. " RX4FREEBUF ,RX free buffer count; Write to increment" group.long 0x154++0x3 line.long 0x0 "RX5FREEBUFFER,Receive Channel 5 Free Buffer Count Register" hexmask.long.word 0x0 0.--15. 1. " RX5FREEBUF ,RX free buffer count; Write to increment" group.long 0x158++0x3 line.long 0x0 "RX6FREEBUFFER,Receive Channel 6 Free Buffer Count Register" hexmask.long.word 0x0 0.--15. 1. " RX6FREEBUF ,RX free buffer count; Write to increment" group.long 0x15C++0x3 line.long 0x0 "RX7FREEBUFFER,Receive Channel 7 Free Buffer Count Register" hexmask.long.word 0x0 0.--15. 1. " RX7FREEBUF ,RX free buffer count; Write to increment" group.long 0x160++0x3 line.long 0x0 "MACCONTROL,MAC Control Register" bitfld.long 0x0 15. " RMIISPEED ,RMII 10/100 Speed Select (IFCTLA)" "10,100" bitfld.long 0x0 14. " RXOFFLENBLOCK ,Receive Offset / Length word write block" "Not blocked/Length word,Blocked/During processing" textline " " bitfld.long 0x0 13. " RXOWNERSHIP ,Receive ownership write bit value" "0,1" bitfld.long 0x0 11. " CMDIDLE ,Command Idle" "Disabled,Enabled" bitfld.long 0x0 10. " TXSHORTGAPEN ,Transmit short gap enable" "Disabled,Enabled" textline " " bitfld.long 0x0 9. " TXPTYPE ,Transmit queue priority type" "Disabled,Enabled" bitfld.long 0x0 6. " TXPACE ,Transmit pacing enable" "Disabled,Enabled" bitfld.long 0x0 5. " GMIIEN ,GMII enable" "Disabled,Enabled" textline " " bitfld.long 0x0 4. " TXFLOWEN ,Transmit flow control enable" "Disabled,Enabled" bitfld.long 0x0 3. " RXBUFFERFLOWEN ,Receive buffer flow control enable" "Disabled,Enabled" bitfld.long 0x0 1. " LOOPBACK ,Loopback mode" "Disabled,Enabled" textline " " bitfld.long 0x0 0. " FULLDUPLEX ,Full duplex mode; gigabit mode forces full duplex mode regardless of whether the fullduplex bit isset or not" "Disabled,Enabled" sif (cpuis("TMS570LS1227*")) rgroup.long 0x164++0x3 else group.long 0x164++0x3 endif line.long 0x0 "MACSTATUS,MAC Status Register" bitfld.long 0x0 31. " IDLE ,CPGMAC idle" "Not idle,Idle" bitfld.long 0x0 20.--23. " TXERRCODE ,TX host error code" "No error,SOP error,Ownership bit not set in SOP buffer,Zero next buffer descriptor pointer without EOP,Zero buffer pointer,Zero buffer length,Packet length error,?..." textline " " bitfld.long 0x0 16.--18. " TXERRCH ,TX host error channel" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 12.--15. " RXERRCODE ,RX host error code" "No error,Reserved,Ownership bit not set in SOP buffer,Reserved,Zero buffer pointer,?..." textline " " bitfld.long 0x0 8.--10. " RXERRCH ,RX host error channel" "0,1,2,3,4,5,6,7" bitfld.long 0x0 2. " RXQOSACT ,RX Quality of Service active" "Disabled,Enabled" textline " " bitfld.long 0x0 1. " RXFLOWACT ,RX flow control active" "Not active,Active" bitfld.long 0x0 0. " TXFLOWACT ,TX flow control active" "Not active,Active" group.long 0x168++0x3 line.long 0x0 "EMCONTROL,Emulation Control Register" bitfld.long 0x0 1. " SOFT ,Emulation soft bit" "Disabled,Enabled" bitfld.long 0x0 0. " FREE ,Emulation free bit" "Disabled,Enabled" group.long 0x16C++0x3 line.long 0x0 "FIFOCONTROL,FIFO Control Register" bitfld.long 0x0 0.--1. " TXCELLTHRESH ,TX FIFO cell threshold" "Reserved,Reserved,Two packet cells,Three packet cells" group.long 0x170++0x3 line.long 0x0 "MACCONFIG,MAC Configuration Register" hexmask.long.byte 0x0 24.--31. 1. " TXCELLDEPTH ,TX cell depth - the number of cells in the transmit FIFO" hexmask.long.byte 0x0 16.--23. 1. " RXCELLDEPTH ,RX cell depth - the number of cells in the receive FIFO" textline " " hexmask.long.byte 0x0 8.--15. 1. " ADDRESSTYPE ,Address type in the design" hexmask.long.byte 0x0 0.--7. 1. " MACCFIG ,MAC configuration value" group.long 0x174++0x3 line.long 0x0 "SOFTRESET,Soft Reset Register" bitfld.long 0x0 0. " SOFTRESET ,Software reset" "No reset,Reset" group.long 0x1D0++0x3 line.long 0x0 "MACSRCADDRLO,MAC Source Address Low" hexmask.long.byte 0x0 8.--15. 1. " MACSRCADDR0 ,MAC source address lower 8 bits MACADDR[7:0]" hexmask.long.byte 0x0 0.--7. 1. " MACSRCADDR1 ,MAC source address bits 15:9 MACADDR[15:8]" group.long 0x1D4++0x3 line.long 0x0 "MACSRCADDRHI,MAC Source Address High" hexmask.long.byte 0x0 24.--31. 1. " MACSRCADDR2 ,MAC source address bits 23:16 (byte 2)" hexmask.long.byte 0x0 16.--23. 1. " MACSRCADDR3 ,MAC source address bits 31:23 (byte 3)" textline " " hexmask.long.byte 0x0 8.--15. 1. " MACSRCADDR4 ,MAC source address bits 39:32 (byte 4)" hexmask.long.byte 0x0 0.--7. 1. " MACSRCADDR5 ,MAC source address bits 47:40 (byte 5)" group.long 0x1D8++0x3 line.long 0x0 "MACHASH1,MAC Hash Address Register 1" group.long 0x1DC++0x3 line.long 0x0 "MACHASH2,MAC Hash Address Register 2" rgroup.long 0x1E0++0x3 line.long 0x0 "BOFFTEST,Back Off Test Register" hexmask.long.word 0x0 16.--25. 1. " RNDNUM ,Backoff random number generator" bitfld.long 0x0 12.--15. " COLLCOUNT ,Collision count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x0 0.--9. 1. " TXBACKOFF ,Backoff count" rgroup.long 0x1E4++0x3 line.long 0x0 "TPACETEST,Transmit Pacing Algorithm Test Register" bitfld.long 0x0 0.--4. " PACEVAL ,Pacing register current value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x1E8++0x3 line.long 0x0 "RXPAUSE,Receive Pause Timer Register" hexmask.long.word 0x0 0.--15. 1. " PAUSETIMER ,RX pause timer value" rgroup.long 0x1EC++0x3 line.long 0x0 "TXPAUSE,Transmit Pause Timer Register" hexmask.long.word 0x0 0.--15. 1. " PAUSETIMER ,TX pause timer value" group.long 0x500++0x3 line.long 0x0 "MACADDRLO,MAC Address Low - From Receive Address Matching Memory Map" bitfld.long 0x0 20. " VALID ," "Not valid,Valid" bitfld.long 0x0 19. " MATCHFILT ," "Filter,Match" textline " " bitfld.long 0x0 16.--18. " CHANNEL ,Channel select" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--15. 1. " MACADDR0 ,MAC addres lower 8 bits (byte 0)" textline " " hexmask.long.byte 0x0 0.--7. 1. " MACADDR1 ,MAC addres bits 15:8 (byte 1)" group.long 0x504++0x3 line.long 0x0 "MACADDRHI,MAC Address High - Receive Address Matching" hexmask.long.byte 0x0 24.--31. 1. " MACADDR2 ,MAC source address bits 23:16 (byte 2)" hexmask.long.byte 0x0 16.--23. 1. " MACADDR3 ,MAC source address bits 31:23 (byte 3)" textline " " hexmask.long.byte 0x0 8.--15. 1. " MACADDR4 ,MAC source address bits 39:32 (byte 4)" hexmask.long.byte 0x0 0.--7. 1. " MACADDR5 ,MAC source address bits 47:40 (byte 5)" group.long 0x508++0x3 line.long 0x0 "MACINDEX,MAC Index Register" bitfld.long 0x0 0.--4. " MACINDEX ,MAC address index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x600++0x3 line.long 0x0 "TX0HDP,Transmit Channel 0 DMA Head Descriptor Pointer Register" group.long 0x604++0x3 line.long 0x0 "TX1HDP,Transmit Channel 1 DMA Head Descriptor Pointer Register" group.long 0x608++0x3 line.long 0x0 "TX2HDP,Transmit Channel 2 DMA Head Descriptor Pointer Register" group.long 0x60C++0x3 line.long 0x0 "TX3HDP,Transmit Channel 3 DMA Head Descriptor Pointer Register" group.long 0x610++0x3 line.long 0x0 "TX4HDP,Transmit Channel 4 DMA Head Descriptor Pointer Register" group.long 0x614++0x3 line.long 0x0 "TX5HDP,Transmit Channel 5 DMA Head Descriptor Pointer Register" group.long 0x618++0x3 line.long 0x0 "TX6HDP,Transmit Channel 6 DMA Head Descriptor Pointer Register" group.long 0x61C++0x3 line.long 0x0 "TX7HDP,Transmit Channel 7 DMA Head Descriptor Pointer Register" group.long 0x620++0x3 line.long 0x0 "RX0HDP,Receive Channel 0 DMA Head Descriptor Pointer Register" group.long 0x624++0x3 line.long 0x0 "RX1HDP,Receive Channel 1 DMA Head Descriptor Pointer Register" group.long 0x628++0x3 line.long 0x0 "RX2HDP,Receive Channel 2 DMA Head Descriptor Pointer Register" group.long 0x62C++0x3 line.long 0x0 "RX3HDP,Receive Channel 3 DMA Head Descriptor Pointer Register" group.long 0x630++0x3 line.long 0x0 "RX4HDP,Receive Channel 4 DMA Head Descriptor Pointer Register" group.long 0x634++0x3 line.long 0x0 "RX5HDP,Receive Channel 5 DMA Head Descriptor Pointer Register" group.long 0x638++0x3 line.long 0x0 "RX6HDP,Receive Channel 6 DMA Head Descriptor Pointer Register" group.long 0x63C++0x3 line.long 0x0 "RX7HDP,Receive Channel 7 DMA Head Descriptor Pointer Register" group.long 0x640++0x3 line.long 0x0 "TX0CP,Transmit Channel 0 Completion Pointer (Interrupt Ack) Register" group.long 0x644++0x3 line.long 0x0 "TX1CP,Transmit Channel 1 Completion Pointer Register" group.long 0x648++0x3 line.long 0x0 "TX2CP,Transmit Channel 2 Completion Pointer Register" group.long 0x64C++0x3 line.long 0x0 "TX3CP,Transmit Channel 3 Completion Pointer Register" group.long 0x650++0x3 line.long 0x0 "TX4CP,Transmit Channel 4 Completion Pointer Register" group.long 0x654++0x3 line.long 0x0 "TX5CP,Transmit Channel 5 Completion Pointer Register" group.long 0x658++0x3 line.long 0x0 "TX6CP,Transmit Channel 6 Completion Pointer Register" group.long 0x65C++0x3 line.long 0x0 "TX7CP,Transmit Channel 7 Completion Pointer Register" group.long 0x660++0x3 line.long 0x0 "RX0CP,Receive Channel 0 Completion Pointer (Interrupt Ack) Register" group.long 0x664++0x3 line.long 0x0 "RX1CP,Receive Channel 1 Completion Pointer (Interrupt Ack) Register" group.long 0x668++0x3 line.long 0x0 "RX2CP,Receive Channel 2 Completion Pointer (Interrupt Ack) Register" group.long 0x66C++0x3 line.long 0x0 "RX3CP,Receive Channel 3 Completion Pointer (Interrupt Ack) Register" group.long 0x670++0x3 line.long 0x0 "RX4CP,Receive Channel 4 Completion Pointer (Interrupt Ack) Register" group.long 0x674++0x3 line.long 0x0 "RX5CP,Receive Channel 5 Completion Pointer (Interrupt Ack) Register" group.long 0x678++0x3 line.long 0x0 "RX6CP,Receive Channel 6 Completion Pointer (Interrupt Ack) Register" group.long 0x67C++0x3 line.long 0x0 "RX7CP,Receive Channel 7 Completion Pointer (Interrupt Ack) Register" group.long 0x200++0x3 line.long 0x0 "RXGOODFRAMES,Good RX Frames" group.long 0x204++0x3 line.long 0x0 "RXBCASTFRAMES,Total number of good broadcast frames received" group.long 0x208++0x3 line.long 0x0 "RXMCASTFRAMES,Total number of good multicast frames received" group.long 0x20C++0x3 line.long 0x0 "RXPAUSEFRAMES,Pause RX Frames Register" group.long 0x210++0x3 line.long 0x0 "RXCRCERRORS,Total number of frames received with CRC errors" group.long 0x214++0x3 line.long 0x0 "RXALIGNCODEERRORS,Total number of frames received with alignment/code errors" group.long 0x218++0x3 line.long 0x0 "RXOVERSIZED,Total number of oversized frames received" group.long 0x21C++0x3 line.long 0x0 "RXJABBER,Total number of jabber frames received" group.long 0x220++0x3 line.long 0x0 "RXUNDERSIZED,Total number of undersized frames received" group.long 0x224++0x3 line.long 0x0 "RXFRAGMENTS,RX Frame Fragments Register" group.long 0x228++0x3 line.long 0x0 "RXFILTERED,Filtered Receive Frames" group.long 0x22C++0x3 line.long 0x0 "RXQOSFILTERED,Received Frames Filtered by QOS" group.long 0x230++0x3 line.long 0x0 "RXOCTETS,Total number of received bytes in good frames" group.long 0x234++0x3 line.long 0x0 "TXGOODFRAMES,Total number of good frames transmitted" group.long 0x238++0x3 line.long 0x0 "TXBCASTFRAMES,Broadcast TX Frames Register" group.long 0x23C++0x3 line.long 0x0 "TXMCASTFRAMES,Multicast TX Frames Register" group.long 0x240++0x3 line.long 0x0 "TXPAUSEFRAMES,Pause TX Frames Register" group.long 0x244++0x3 line.long 0x0 "TXDEFERRED,Deferred TX Frames Register" group.long 0x248++0x3 line.long 0x0 "TXCOLLISION,TX Collision Frames Register" group.long 0x24C++0x3 line.long 0x0 "TXSINGLECOLL,TX Single Collision Frames Register" group.long 0x250++0x3 line.long 0x0 "TXMULTICOLL,TX Multiple Collision Frames Register" group.long 0x254++0x3 line.long 0x0 "TXEXCESSIVECOLL,TX Excessive Collision Frames Register" group.long 0x258++0x3 line.long 0x0 "TXLATECOLL,TX Late Collision Frames Register" group.long 0x25C++0x3 line.long 0x0 "TXUNDERRUN,TX Underrun Error Register" group.long 0x260++0x3 line.long 0x0 "TXCARRIERSENSE,TX Carrier Sense Errors Register" group.long 0x264++0x3 line.long 0x0 "TXOCTETS,TX Octet Frames Register" group.long 0x268++0x3 line.long 0x0 "FRAME64,Transmit and Receive 64 Octet Frames Register" group.long 0x26C++0x3 line.long 0x0 "FRAME65T127,Transmit and Receive 65 to 127 Octet Frames Register" group.long 0x270++0x3 line.long 0x0 "FRAME128T255,Transmit and Receive 128 to 255 Octet Frames Register" group.long 0x274++0x3 line.long 0x0 "FRAME256T511,Transmit and Receive 256 to 511 Octet Frames Register" group.long 0x278++0x3 line.long 0x0 "FRAME512T1023,Transmit and Receive 512 to 1023 Octet Frames Register" group.long 0x27C++0x3 line.long 0x0 "FRAME1024TUP,Transmit and Receive 1024 to 1518 Octet Frames Register" group.long 0x280++0x3 line.long 0x0 "NETOCTETS,Network Octet Frames Register" group.long 0x284++0x3 line.long 0x0 "RXSOFOVERRUNS,Receive FIFO or DMA Start of Frame Overruns Register" group.long 0x288++0x3 line.long 0x0 "RXMOFOVERRUNS,Receive FIFO or DMA Middle of Frame Overruns Register" group.long 0x28C++0x3 line.long 0x0 "RXDMAOVERRUNS,Receive DMA Start of Frame and Middle of Frame Overruns Register" width 11. tree.end tree.end endif sif (cpu()=="RM48L952-PGE"||cpu()=="RM48L952-ZWT"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE"||cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430"||cpu()=="RM48L550-ZWT") tree "USB (USB Host Controller Registers)" base ad:0xFCF78B00 width 21. rgroup.long 0x00++0x3 line.long 0x00 "HCREVISION,OHCI revision number" hexmask.long.byte 0x00 0.--7. 1. " REV ,OHCI specification revision" group.long 0x04++0x13 line.long 0x00 "HCCONTROL,HC operating mode" bitfld.long 0x00 8. " IR ,Interrupt routing" "0,1" bitfld.long 0x00 6.--7. " HCFS ,Host controller functional state" "Reset,Resume,Operational,Suspend" textline " " bitfld.long 0x00 5. " BLE ,Bulk list enable" "Disabled,Enabled" bitfld.long 0x00 4. " CLE ,Control list enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " IE ,Isochronous enable" "Disabled,Enabled" bitfld.long 0x00 2. " PLE ,Periodic list enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " CBSR ,Specifies the ratio between control and bulk EDs processed in a frame" "One,Two,Three,Four" line.long 0x04 "HCCOMMANDSTATUS,HC command and status" bitfld.long 0x04 16.--17. " SOC ,Scheduling overrun count" "0,1,2,3" bitfld.long 0x04 3. " OCR ,Ownership change request" "Not requested,Requested" textline " " bitfld.long 0x04 2. " BLF ,Bulk list filled" "Disabled,Enabled" bitfld.long 0x04 1. " CLF ,Control list filled" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " HCR ,Host controller reset" "No reset,Reset" line.long 0x08 "HCINTERRUPT_SET/CLR,HC interrupt status" setclrfld.long 0x08 6. 0x0C 6. 0x10 6. " RHSC_set/clr ,Root hub status change" "Disabled,Enabled" setclrfld.long 0x08 5. 0x0C 5. 0x10 5. " FNO_set/clr ,Frame number overflow" "Disabled,Enabled" textline " " setclrfld.long 0x08 4. 0x0C 4. 0x10 4. " UE_set/clr ,Unrecoverable error" "Disabled,Enabled" setclrfld.long 0x08 3. 0x0C 3. 0x10 3. " RD_set/clr ,Resume detected" "Disabled,Enabled" textline " " setclrfld.long 0x08 2. 0x0C 2. 0x10 2. " SF_set/clr ,Start of frame" "Disabled,Enabled" setclrfld.long 0x08 1. 0x0C 1. 0x10 1. " WDH_set/clr ,Write done head" "Disabled,Enabled" textline " " setclrfld.long 0x08 0. 0x0C 0. 0x10 0. " SO_set/clr ,Scheduling overrun" "Disabled,Enabled" group.long 0x18++0x17 line.long 0x00 "HCHCCA,Physical address of HCCA" hexmask.long.tbyte 0x00 8.--31. 1. " HCCA ,Physical address of the beginning of the HCCA" line.long 0x04 "HCPERIODCURRENTED,Physical address of current periodic endpoint R/W 32 FCF78B1Ch descriptor" hexmask.long 0x04 4.--31. 0x10 " PCED ,Physical address of current ED on the periodic ED list" line.long 0x08 "HCCONTROLHEADED,Physical address of head of control endpoint R/W 32 FCF78B20h descriptor list" hexmask.long 0x08 4.--31. 0x10 " CHED ,Physical address of current ED on the periodic ED list" line.long 0x0C "HCCONTROLCURRENTED,Physical address of current control endpoint R/W 32 FCF78B24h descriptor" hexmask.long 0x0C 4.--31. 0x10 " CCED ,Physical address of current ED on the periodic ED list" line.long 0x10 "HCBULKHEADED,Physical address of head of bulk endpoint R/W 32 FCF78B28h descriptor list" hexmask.long 0x10 4.--31. 0x10 " BHED ,Physical address of current ED on the periodic ED list" line.long 0x14 "HCBULKCURRENTED,Physical of current bulk endpoint descriptor" hexmask.long 0x14 4.--31. 0x10 " BCED ,Physical address of current ED on the periodic ED list" rgroup.long 0x30++0x3 line.long 0x00 "HCDONEHEAD,Physical address of head of list of retired R 32 FCF78B30h transfer descriptors" hexmask.long 0x00 4.--31. 0x10 " DH ,Physical address of current ED on the periodic ED list" group.long 0x34++0x3 line.long 0x00 "HCFMINTERVAL,HC frame interval" bitfld.long 0x00 31. " FIT ,Frame interval toggle" "Disabled,Enabled" hexmask.long.word 0x00 16.--30. 1. " FSMPS ,Largest data packet" textline " " hexmask.long.word 0x00 0.--13. 1. " FI ,Frame interval" rgroup.long 0x38++0x7 line.long 0x00 "HCFMREMAINING,HC frame remaining" bitfld.long 0x00 31. " FRT ,Frame interval toggle" "Disabled,Enabled" hexmask.long.word 0x00 0.--13. 1. " FR ,Frame remaining" line.long 0x04 "HCFMNUMBER,HC frame number" hexmask.long.word 0x04 0.--13. 1. " FN ,Frame number" group.long 0x40++0x7 line.long 0x00 "HCPERIODICSTART,HC periodic start" hexmask.long.word 0x00 0.--13. 1. " PS ,Periodic start" line.long 0x04 "HCLSTHRESHOLD,HC low speed threshold" hexmask.long.word 0x04 0.--13. 1. " LST ,Low-speed threshold" if (((d.l(ad:0xFCF78B00+0x48))&0x100000)==0x00) group.long 0x48++0x3 line.long 0x00 "HCRHDESCRIPTORA,HC root hub A" hexmask.long.byte 0x00 24.--31. 1. " POTPG ,Power-on to power-good time" bitfld.long 0x00 12. " NOCP ,No overcurrent protection" "No,Yes" textline " " bitfld.long 0x00 11. " OCPM ,Overcurrent protection mode" "All downstream ports,Per-port basis" bitfld.long 0x00 9. " NPS ,No power switching" "No,Yes" textline " " bitfld.long 0x00 8. " PSM ,Power switching mode for ports" "Same time,Individually" hexmask.long.byte 0x00 0.--7. 1. " NDP ,Number of downstream ports" else group.long 0x48++0x3 line.long 0x00 "HCRHDESCRIPTORA,HC root hub A" hexmask.long.byte 0x00 24.--31. 1. " POTPG ,Power-on to power-good time" bitfld.long 0x00 12. " NOCP ,No overcurrent protection" "No,Yes" textline " " bitfld.long 0x00 9. " NPS ,No power switching" "No,Yes" textline " " bitfld.long 0x00 8. " PSM ,Power switching mode for ports" "Same time,Individually" hexmask.long.byte 0x00 0.--7. 1. " NDP ,Number of downstream ports" endif group.long 0x4C++0x7 line.long 0x00 "HCRHDESCRIPTORB,HC root hub B" bitfld.long 0x00 19. " PPCM[3] ,Port power control mask 3" "Masked,Not masked" bitfld.long 0x00 18. " PPCM[2] ,Port power control mask 2" "Masked,Not masked" textline " " bitfld.long 0x00 17. " PPCM[1] ,Port power control mask 1" "Masked,Not masked" bitfld.long 0x00 16. " PPCM[0] ,Port power control mask 0" "Masked,Not masked" textline " " bitfld.long 0x00 3. " DR[3] ,Device 3 removable" "Removable,Non-removable" bitfld.long 0x00 2. " DR[2] ,Device 2 removable" "Removable,Non-removable" textline " " bitfld.long 0x00 1. " DR[1] ,Device 1 removable" "Removable,Non-removable" bitfld.long 0x00 0. " DR[0] ,Device 0 removable" "Removable,Non-removable" line.long 0x04 "HCRHSTATUS,HC root hub status" eventfld.long 0x04 31. " CRWE ,Clear remote wake-up enable" "Not cleared,Cleared" eventfld.long 0x04 17. " OCIC ,Overcurrent indication change" "Not changed,Changed" textline " " bitfld.long 0x04 15. " DRWE ,Device remote wake-up enable" "No effect,Enabled" if (((d.l(ad:0xFCF78B00+0x54))&0x1000000)==0x1000000) group.long 0x54++0x3 line.long 0x00 "HCRHPORTSTATUS0,HC port 0 control and status" eventfld.long 0x00 20. " PRSC ,Port 0 reset status change" "Not changed,Changed" eventfld.long 0x00 19. " OCIC ,Port 0 overcurrent indicator change" "Not changed,Changed" textline " " eventfld.long 0x00 18. " PSSC ,Port 0 suspend status change" "Not changed,Changed" eventfld.long 0x00 17. " PESC ,Port 0 enable status change" "Not changed,Changed" textline " " eventfld.long 0x00 16. " CSC ,Port 0 connect status change" "Not changed,Changed" bitfld.long 0x00 9. " LSDA/CPP ,Port 0 low-speed device attached/clear port power" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " PPS/SPP ,Port 0 port power status/set port power" "Disabled,Enabled" bitfld.long 0x00 4. " PRS/SPR ,Port 0 port reset status/set port reset" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " POCI/CSS ,Port 0 port overcurrent indicator/clear suspend status" "Disabled,Enabled" bitfld.long 0x00 2. " PSS/SPS ,Port 0 port suspend status/set port suspend" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " PES/SPE ,Port 0 port enable status/set port enable" "Disabled,Enabled" bitfld.long 0x00 0. " CCS/CPE ,Port 0 current connection status/clear port enable" "Disabled,Enabled" else group.long 0x54++0x3 line.long 0x00 "HCRHPORTSTATUS0,HC port 0 control and status" eventfld.long 0x00 20. " PRSC ,Port 0 reset status change" "Not changed,Changed" eventfld.long 0x00 19. " OCIC ,Port 0 overcurrent indicator change" "Not changed,Changed" textline " " eventfld.long 0x00 18. " PSSC ,Port 0 suspend status change" "Not changed,Changed" eventfld.long 0x00 17. " PESC ,Port 0 enable status change" "Not changed,Changed" textline " " eventfld.long 0x00 16. " CSC ,Port 0 connect status change" "Not changed,Changed" textline " " bitfld.long 0x00 8. " PPS/SPP ,Port 0 port power status/set port power" "Disabled,Enabled" bitfld.long 0x00 4. " PRS/SPR ,Port 0 port reset status/set port reset" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " POCI/CSS ,Port 0 port overcurrent indicator/clear suspend status" "Disabled,Enabled" bitfld.long 0x00 2. " PSS/SPS ,Port 0 port suspend status/set port suspend" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " PES/SPE ,Port 0 port enable status/set port enable" "Disabled,Enabled" bitfld.long 0x00 0. " CCS/CPE ,Port 0 current connection status/clear port enable" "Disabled,Enabled" endif if (((d.l(ad:0xFCF78B00+0x58))&0x1000000)==0x1000000) group.long 0x58++0x3 line.long 0x00 "HCRHPORTSTATUS1,HC port 1 control and status" eventfld.long 0x00 20. " PRSC ,Port 1 reset status change" "Not changed,Changed" eventfld.long 0x00 19. " OCIC ,Port 1 overcurrent indicator change" "Not changed,Changed" textline " " eventfld.long 0x00 18. " PSSC ,Port 1 suspend status change" "Not changed,Changed" eventfld.long 0x00 17. " PESC ,Port 1 enable status change" "Not changed,Changed" textline " " eventfld.long 0x00 16. " CSC ,Port 1 connect status change" "Not changed,Changed" bitfld.long 0x00 9. " LSDA/CPP ,Port 1 low-speed device attached/clear port power" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " PPS/SPP ,Port 1 port power status/set port power" "Disabled,Enabled" bitfld.long 0x00 4. " PRS/SPR ,Port 1 port reset status/set port reset" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " POCI/CSS ,Port 1 port overcurrent indicator/clear suspend status" "Disabled,Enabled" bitfld.long 0x00 2. " PSS/SPS ,Port 1 port suspend status/set port suspend" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " PES/SPE ,Port 1 port enable status/set port enable" "Disabled,Enabled" bitfld.long 0x00 0. " CCS/CPE ,Port 1 current connection status/clear port enable" "Disabled,Enabled" else group.long 0x58++0x3 line.long 0x00 "HCRHPORTSTATUS1,HC port 1 control and status" eventfld.long 0x00 20. " PRSC ,Port 1 reset status change" "Not changed,Changed" eventfld.long 0x00 19. " OCIC ,Port 1 overcurrent indicator change" "Not changed,Changed" textline " " eventfld.long 0x00 18. " PSSC ,Port 1 suspend status change" "Not changed,Changed" eventfld.long 0x00 17. " PESC ,Port 1 enable status change" "Not changed,Changed" textline " " eventfld.long 0x00 16. " CSC ,Port 1 connect status change" "Not changed,Changed" textline " " bitfld.long 0x00 8. " PPS/SPP ,Port 1 port power status/set port power" "Disabled,Enabled" bitfld.long 0x00 4. " PRS/SPR ,Port 1 port reset status/set port reset" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " POCI/CSS ,Port 1 port overcurrent indicator/clear suspend status" "Disabled,Enabled" bitfld.long 0x00 2. " PSS/SPS ,Port 1 port suspend status/set port suspend" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " PES/SPE ,Port 1 port enable status/set port enable" "Disabled,Enabled" bitfld.long 0x00 0. " CCS/CPE ,Port 1 current connection status/clear port enable" "Disabled,Enabled" endif rgroup.long 0xE0++0x7 line.long 0x00 "HOSTUEADDR,Host UE address" line.long 0x04 "HOSTUESTATUS,Host UE status" bitfld.long 0x04 0. " UEACCESS ,Access type when unrecoverable error occurred" "Read,Write" group.long 0xE8++0x3 line.long 0x00 "HOSTTIMEOUTCTRL,Host time-out control" bitfld.long 0x00 0. " TO_DIS ,Bus time-out disable" "No,Yes" rgroup.long 0xEC++0x3 line.long 0x00 "HOSTREVISION,Host revision" bitfld.long 0x00 4.--7. " MAJORREV ,Major revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " MINORREV ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 11. tree.end tree "USB (USB Device Controller Registers)" base ad:0xFCF78A00 tree "Endpoint configuration" width 10. group.word 0x2++0x1 line.word 0x00 "EP_NUM,Endpoint selection" bitfld.word 0x00 6. " SETUP_SEL ,Setup select" "No access,Access" bitfld.word 0x00 5. " EP_SEL ,Endpoint select" "No access,Access" textline " " bitfld.word 0x00 4. " EP_DIR ,Endpoint direction" "Out,In" bitfld.word 0x00 0.--3. " EP_NUM ,Endpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if ((d.w(ad:0xFCF78A00+0x2)&0x10000000)==0x0) rgroup.word 0x04++0x1 line.word 0x00 "DATA,Data" else wgroup.word 0x04++0x1 line.word 0x00 "DATA,Data" endif wgroup.word 0x6++0x5 line.word 0x00 "CTRL,Control" bitfld.word 0x00 7. " CLR_HALT ,Halt endpoint clear" "No effect,Clear" bitfld.word 0x00 6. " SET_HALT ,Halt endpoint set" "No effect,Halt" textline " " bitfld.word 0x00 2. " SET_FIFO_EN ,FIFO enable" "No effect,Enable" bitfld.word 0x00 1. " CLR_EP ,Endpoint clear" "No effect,Clear" textline " " bitfld.word 0x00 0. " RESET_EP ,Endpoint reset" "No effect,Reset" rgroup.word 0x08++0x3 line.word 0x00 "STAT_FLG,Status" bitfld.word 0x00 15. " NO_RXPACKET ,Isochronous no packet received" "Received,Not received" bitfld.word 0x00 14. " MISS_IN ,Isochronous missed IN token for the previous frame" "Not missed,Missed" textline " " bitfld.word 0x00 13. " DATA_FLUSH ,Isochronous receive data flush" "Not flushed,Flushed" bitfld.word 0x00 12. " ISO_ERR ,Isochronous receive data error" "No error,Error" textline " " bitfld.word 0x00 9. " ISO_FIFO_EMPTY ,ISO FIFO empty" "Not empty,Empty" bitfld.word 0x00 8. " ISO_FIFO_FULL ,ISO FIFO full" "Not full,Full" textline " " bitfld.word 0x00 6. " EP_HALTED ,Endpoint halted" "Not halted,Halted" bitfld.word 0x00 5. " STALL ,Transaction stall" "No stall,stall" textline " " bitfld.word 0x00 4. " NAK ,Transaction non-acknowledge" "No NAK,NAK" bitfld.word 0x00 3. " ACK ,Transaction acknowledge" "No ACK,ACK" textline " " bitfld.word 0x00 2. " FIFO_EN ,FIFO enable" "Disabled,Enabled" bitfld.word 0x00 1. " NON_ISO_FIFO_EMPTY ,Non-ISO FIFO empty" "Not empty,Empty" textline " " bitfld.word 0x00 0. " NON_ISO_FIFO_FULL ,Non-ISO FIFO full" "Not full,Full" line.word 0x02 "RXFSTAT,Receive FIFO status" hexmask.word 0x02 0.--9. 1. " RXF_COUNT ,Receive FIFO byte count" group.word 0x0C++0x1 line.word 0x00 "SYSCON1,System configuration 1" bitfld.word 0x00 8. " CFG_LOCK ,Device configuration lock" "Not locked,Locked" bitfld.word 0x00 7. " DATA_ENDIAN ,Data endian" "Little-endian,Big-endian" textline " " bitfld.word 0x00 6. " DMA_ENDIAN ,DMA data endian" "Little-endian,Big-endian" bitfld.word 0x00 4. " NAK_EN ,NAK enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " AUTODEC_DIS ,Autodecode process disable" "No,Yes" bitfld.word 0x00 2. " SELF_PWR ,Bus\self-powered" "Bus,Self" textline " " bitfld.word 0x00 1. " SOFF_DIS ,Shutoff disable" "No,Yes" bitfld.word 0x00 0. " PULLUP_EN ,External pullup enable" "Disabled,Enabled" wgroup.word 0x0E++0x1 line.word 0x00 "SYSCON2,System configuration 2" bitfld.word 0x00 6. " RMT_WKP ,Remote wake-up" "No effect,Wake-up" bitfld.word 0x00 5. " STALL_CMD ,Stall command" "No effect,Stall" textline " " bitfld.word 0x00 3. " DEV_CFG ,Device configuration set" "No effect,Set" bitfld.word 0x00 2. " CLR_CFG ,Device configuration clear" "No effect,Clear" rgroup.word 0x10++0x3 line.word 0x00 "DEVSTAT,Device Status Register" bitfld.word 0x00 9. " B_HNP_ENABLE ,HNP enable for B-device" "Disabled,Enabled" bitfld.word 0x00 8. " A_HNP_SUPPORT ,B-device connection to HNP capable A-device" "Not occurred,Occurred" textline " " bitfld.word 0x00 7. " A_ALT_HNP_SUPPORT ,B-device connection to not HNP capable A-device" "Not occurred,Occurred" bitfld.word 0x00 6. " R_WK_OK ,Remote wake-up granted" "Not granted,Granted" textline " " bitfld.word 0x00 5. " USB_RESET ,USB reset" "No reset,Reset" bitfld.word 0x00 4. " SUS ,Suspended state" "Not suspended,Suspended" textline " " bitfld.word 0x00 3. " CFG ,Configured state" "Not configured,Configured" bitfld.word 0x00 2. " ADD ,Addressed state" "Not addressed,Addressed" textline " " bitfld.word 0x00 1. " DEF ,Default state" "Not default,Default" bitfld.word 0x00 0. " ATT ,Attached state" "Not attached,Attached" line.word 0x02 "SOF,Start of Frame Register" bitfld.word 0x02 12. " FT_LOCK ,Frame timer lock" "Not locked,Locked" bitfld.word 0x02 11. " TS_OK ,Timestamp is valid" "Invalid,Valid" textline " " hexmask.word 0x02 0.--10. 1. " TS ,Timestamp value" group.word 0x14++0x5 line.word 0x00 "IRQ_EN,Interrupt Enable Register" bitfld.word 0x00 7. " SOF_IE ,Start of frame interrupt enable" "Disabled,Enabled" bitfld.word 0x00 5. " EPn_RX_IE ,Receive endpoint n interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 4. " EPn_TX_IE ,Transmit endpoint n interrupt enable" "Disabled,Enabled" bitfld.word 0x00 3. " DS_CHG_IE ,Device state changed interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x00 0. " EP0_IE ,EP0 transactions interrupt enable" "Disabled,Enabled" line.word 0x02 "DMA_IRQ_EN,DMA Interrupt Enable Register" bitfld.word 0x02 10. " TX2_DONE_IE ,Transmit DMA channel 2 done interrupt enable" "Disabled,Enabled" bitfld.word 0x02 9. " RX2_CNTT_IE ,Receive DMA channel 2 transactions count interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x02 8. " RX2_EOT_IE ,Receive DMA channel 2 end of transfer interrupt enable" "Disabled,Enabled" bitfld.word 0x02 6. " TX1_DONE_IE ,Transmit DMA channel 1 done interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x02 5. " RX1_CNT_IE ,Receive DMA channel 1 transactions count interrupt enable" "Disabled,Enabled" bitfld.word 0x02 4. " RX1_EOT_IE ,Receive DMA channel 1 end of transfer interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x02 2. " TX0_DONE_IE ,Transmit DMA channel 0 done interrupt enable" "Disabled,Enabled" bitfld.word 0x02 1. " RX0_CNT_IE ,Receive DMA channel 0 transactions count interrupt enable" "Disabled,Enabled" textline " " bitfld.word 0x02 0. " RX0_EOT_IE ,Receive DMA channel 0 end of transfer interrupt enable" "Disabled,Enabled" line.word 0x04 "IRQ_SRC,Interrupt Source Register" eventfld.word 0x04 10. " TXn_DONE ,Tx DMA channel n done interrupt flag" "Not occurred,Occurred" eventfld.word 0x04 9. " RXn_CNT ,Rx DMA channel n transactions count interrupt flag" "Not occurred,Occurred" textline " " eventfld.word 0x04 8. " RXn_EOT ,Rx DMA channel n end of transfer interrupt flag" "Not occurred,Occurred" eventfld.word 0x04 7. " SOF ,Start of frame interrupt flag" "Not occurred,Occurred" textline " " eventfld.word 0x04 5. " EPn_RX ,EPn OUT transactions interrupt flag" "Not occurred,Occurred" eventfld.word 0x04 4. " EPn_TX ,EPn IN transactions interrupt flag" "Not occurred,Occurred" textline " " eventfld.word 0x04 3. " DS_CHG ,Device state changed interrupt flag" "Not occurred,Occurred" bitfld.word 0x04 2. " SETUP ,Setup transaction interrupt flag" "Not occurred,Occurred" textline " " eventfld.word 0x04 1. " EP0_RX ,EP0 OUT transactions interrupt flag" "Not occurred,Occurred" eventfld.word 0x04 0. " EP0_TX ,EP0 IN transactions interrupt flag" "Not occurred,Occurred" rgroup.word 0x1A++0x3 line.word 0x00 "EPN_STAT,DMA receive interrupt source" bitfld.word 0x00 8.--11. " EPn_RX_IT_SRC ,Receive endpoint interrupt source" "No interrupt,EP1,EP2,EP3,EP4,EP5,EP6,EP7,EP8,EP9,EP10,EP11,EP12,EP13,EP14,EP15" bitfld.word 0x00 0.--3. " EPn_TX_IT_SRC ,Transmit endpoint interrupt source" "No interrupt,EP1,EP2,EP3,EP4,EP5,EP6,EP7,EP8,EP9,EP10,EP11,EP12,EP13,EP14,EP15" line.word 0x02 "DMAN_STAT,DMA transmit interrupt source" bitfld.word 0x02 8.--11. " DMAn_RX_IT_SRC ,Receive endpoint interrupt source" "No interrupt,EP1,EP2,EP3,EP4,EP5,EP6,EP7,EP8,EP9,EP10,EP11,EP12,EP13,EP14,EP15" bitfld.word 0x02 0.--3. " DMAn_TX_IT_SRC ,Transmit endpoint interrupt source" "No interrupt,EP1,EP2,EP3,EP4,EP5,EP6,EP7,EP8,EP9,EP10,EP11,EP12,EP13,EP14,EP15" tree.end tree "DMA configuration" width 10. group.word 0x20++0x3 line.word 0x00 "RXDMA_CFG,DMA Receive Channels Configuration Register" bitfld.word 0x00 12. " RX_REQ ,RX DMA request active level/pulse select" "Level,Pulse" bitfld.word 0x00 8.--11. " RXDMA2_EP ,Receive endpoint number for DMA channel 2" "Deactivated,EP1,EP2,EP3,EP4,EP5,EP6,EP7,EP8,EP9,EP10,EP11,EP12,EP13,EP14,EP15" textline " " bitfld.word 0x00 4.--7. " RXDMA1_EP ,Receive endpoint number for DMA channel 1" "Deactivated,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " RXDMA0_EP ,Receive endpoint number for DMA channel 0" "Deactivated,EP1,EP2,EP3,EP4,EP5,EP6,EP7,EP8,EP9,EP10,EP11,EP12,EP13,EP14,EP15" line.word 0x02 "TXDMA_CFG,DMA Transmit Channels Configuration Register" bitfld.word 0x02 12. " TX_REQ ,TX DMA request active level/pulse select" "Level,Pulse" bitfld.word 0x02 8.--11. " TXDMA2_EP ,Transmit endpoint number for DMA channel 2" "Deactivated,EP1,EP2,EP3,EP4,EP5,EP6,EP7,EP8,EP9,EP10,EP11,EP12,EP13,EP14,EP15" textline " " bitfld.word 0x02 4.--7. " TXDMA1_EP ,Transmit endpoint number for DMA channel 1" "Deactivated,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x02 0.--3. " TXDMA0_EP ,Transmit endpoint number for DMA channel 0" "Deactivated,EP1,EP2,EP3,EP4,EP5,EP6,EP7,EP8,EP9,EP10,EP11,EP12,EP13,EP14,EP15" hgroup.word 0x24++0x1 hide.word 0x00 "DATA_DMA,DMA FIFO data" group.word (0x26)++0x1 line.word 0x00 "TXDMA0,Transmit DMA Control Register 0" bitfld.word 0x00 15. " TXn_EOT ,DMA transfer size format" "Buffers,Bytes" bitfld.word 0x00 14. " TXn_START ,Transmit DMA channel n start" "Not started,Started" textline " " hexmask.word 0x00 0.--9. 1. " TXn_TSC ,Transmit DMA channel n transfer size counter" group.word (0x28)++0x1 line.word 0x00 "TXDMA1,Transmit DMA Control Register 1" bitfld.word 0x00 15. " TXn_EOT ,DMA transfer size format" "Buffers,Bytes" bitfld.word 0x00 14. " TXn_START ,Transmit DMA channel n start" "Not started,Started" textline " " hexmask.word 0x00 0.--9. 1. " TXn_TSC ,Transmit DMA channel n transfer size counter" group.word (0x2A)++0x1 line.word 0x00 "TXDMA2,Transmit DMA Control Register 2" bitfld.word 0x00 15. " TXn_EOT ,DMA transfer size format" "Buffers,Bytes" bitfld.word 0x00 14. " TXn_START ,Transmit DMA channel n start" "Not started,Started" textline " " hexmask.word 0x00 0.--9. 1. " TXn_TSC ,Transmit DMA channel n transfer size counter" group.word (0x30)++0x1 line.word 0x00 "RXDMA0,Receive DMA Control Register 0" bitfld.word 0x00 15. " RXn_STOP ,Receive DMA channel n transfer stop" "Not stopped,Stopped" hexmask.word.byte 0x00 0.--7. 1. " RXn_TC ,Receive DMA channel n transactions count" group.word (0x32)++0x1 line.word 0x00 "RXDMA1,Receive DMA Control Register 1" bitfld.word 0x00 15. " RXn_STOP ,Receive DMA channel n transfer stop" "Not stopped,Stopped" hexmask.word.byte 0x00 0.--7. 1. " RXn_TC ,Receive DMA channel n transactions count" group.word (0x34)++0x1 line.word 0x00 "RXDMA2,Receive DMA Control Register 2" bitfld.word 0x00 15. " RXn_STOP ,Receive DMA channel n transfer stop" "Not stopped,Stopped" hexmask.word.byte 0x00 0.--7. 1. " RXn_TC ,Receive DMA channel n transactions count" tree.end tree "Endpoint configuration" width 10. group.word 0x40++0x1 line.word 0x00 "EP0,Endpoint 0 Configuration Register" bitfld.word 0x00 12.--13. " EP0_SIZE ,Endpoint 0 FIFO size" "8-bytes,16-bytes,32-bytes,64-bytes" hexmask.word 0x00 0.--10. 1. " EP0_PTR ,Endpoint 0 pointer" if ((d.w(ad:0xFCF78A00+0x42)&0x080000)==0x080000) group.word (0x42)++0x1 line.word 0x00 "EP1_RX,Receive Endpoint 1 Configuration Register" bitfld.word 0x00 15. " EP1_RX_VALID ,Receive endpoint 1 valid" "Invalid,Valid" bitfld.word 0x00 12.--14. " EP1_RX_SIZE ,Receive endpoint 1 size " "8-bytes,16-bytes,32-bytes,64-bytes,128-bytes,256-bytes,512-bytes,1023-bytes" textline " " bitfld.word 0x00 11. " EP1_RX_ISO ,Receive ISO endpoint 1 field" "Bulk/interrupt,Isochronous" hexmask.word 0x00 0.--10. 1. " EP1_RX_PTR ,Address of the receive endpoint 1 pointer" else group.word (0x42)++0x1 line.word 0x00 "EP1_RX,Receive Endpoint 1 Configuration Register" bitfld.word 0x00 15. " EP1_RX_VALID ,Receive endpoint 1 valid" "Invalid,Valid" bitfld.word 0x00 14. " EP1_RX_SIZE/DB ,Double buffer use for non-ISO receive endpoint 1" "Not used,Used" textline " " bitfld.word 0x00 12.--13. " EP1_RX_SIZE ,Receive endpoint 1 size " "8-bytes,16-bytes,32-bytes,64-bytes" bitfld.word 0x00 11. " EP1_RX_ISO ,Receive ISO endpoint 1 field" "Bulk/interrupt,Isochronous" textline " " hexmask.word 0x00 0.--10. 1. " EP1_RX_PTR ,Address of the receive endpoint 1 pointer" endif if ((d.w(ad:0xFCF78A00+0x44)&0x080000)==0x080000) group.word (0x44)++0x1 line.word 0x00 "EP2_RX,Receive Endpoint 2 Configuration Register" bitfld.word 0x00 15. " EP2_RX_VALID ,Receive endpoint 2 valid" "Invalid,Valid" bitfld.word 0x00 12.--14. " EP2_RX_SIZE ,Receive endpoint 2 size " "8-bytes,16-bytes,32-bytes,64-bytes,128-bytes,256-bytes,512-bytes,1023-bytes" textline " " bitfld.word 0x00 11. " EP2_RX_ISO ,Receive ISO endpoint 2 field" "Bulk/interrupt,Isochronous" hexmask.word 0x00 0.--10. 1. " EP2_RX_PTR ,Address of the receive endpoint 2 pointer" else group.word (0x44)++0x1 line.word 0x00 "EP2_RX,Receive Endpoint 2 Configuration Register" bitfld.word 0x00 15. " EP2_RX_VALID ,Receive endpoint 2 valid" "Invalid,Valid" bitfld.word 0x00 14. " EP2_RX_SIZE/DB ,Double buffer use for non-ISO receive endpoint 2" "Not used,Used" textline " " bitfld.word 0x00 12.--13. " EP2_RX_SIZE ,Receive endpoint 2 size " "8-bytes,16-bytes,32-bytes,64-bytes" bitfld.word 0x00 11. " EP2_RX_ISO ,Receive ISO endpoint 2 field" "Bulk/interrupt,Isochronous" textline " " hexmask.word 0x00 0.--10. 1. " EP2_RX_PTR ,Address of the receive endpoint 2 pointer" endif if ((d.w(ad:0xFCF78A00+0x46)&0x080000)==0x080000) group.word (0x46)++0x1 line.word 0x00 "EP3_RX,Receive Endpoint 3 Configuration Register" bitfld.word 0x00 15. " EP3_RX_VALID ,Receive endpoint 3 valid" "Invalid,Valid" bitfld.word 0x00 12.--14. " EP3_RX_SIZE ,Receive endpoint 3 size " "8-bytes,16-bytes,32-bytes,64-bytes,128-bytes,256-bytes,512-bytes,1023-bytes" textline " " bitfld.word 0x00 11. " EP3_RX_ISO ,Receive ISO endpoint 3 field" "Bulk/interrupt,Isochronous" hexmask.word 0x00 0.--10. 1. " EP3_RX_PTR ,Address of the receive endpoint 3 pointer" else group.word (0x46)++0x1 line.word 0x00 "EP3_RX,Receive Endpoint 3 Configuration Register" bitfld.word 0x00 15. " EP3_RX_VALID ,Receive endpoint 3 valid" "Invalid,Valid" bitfld.word 0x00 14. " EP3_RX_SIZE/DB ,Double buffer use for non-ISO receive endpoint 3" "Not used,Used" textline " " bitfld.word 0x00 12.--13. " EP3_RX_SIZE ,Receive endpoint 3 size " "8-bytes,16-bytes,32-bytes,64-bytes" bitfld.word 0x00 11. " EP3_RX_ISO ,Receive ISO endpoint 3 field" "Bulk/interrupt,Isochronous" textline " " hexmask.word 0x00 0.--10. 1. " EP3_RX_PTR ,Address of the receive endpoint 3 pointer" endif if ((d.w(ad:0xFCF78A00+0x48)&0x080000)==0x080000) group.word (0x48)++0x1 line.word 0x00 "EP4_RX,Receive Endpoint 4 Configuration Register" bitfld.word 0x00 15. " EP4_RX_VALID ,Receive endpoint 4 valid" "Invalid,Valid" bitfld.word 0x00 12.--14. " EP4_RX_SIZE ,Receive endpoint 4 size " "8-bytes,16-bytes,32-bytes,64-bytes,128-bytes,256-bytes,512-bytes,1023-bytes" textline " " bitfld.word 0x00 11. " EP4_RX_ISO ,Receive ISO endpoint 4 field" "Bulk/interrupt,Isochronous" hexmask.word 0x00 0.--10. 1. " EP4_RX_PTR ,Address of the receive endpoint 4 pointer" else group.word (0x48)++0x1 line.word 0x00 "EP4_RX,Receive Endpoint 4 Configuration Register" bitfld.word 0x00 15. " EP4_RX_VALID ,Receive endpoint 4 valid" "Invalid,Valid" bitfld.word 0x00 14. " EP4_RX_SIZE/DB ,Double buffer use for non-ISO receive endpoint 4" "Not used,Used" textline " " bitfld.word 0x00 12.--13. " EP4_RX_SIZE ,Receive endpoint 4 size " "8-bytes,16-bytes,32-bytes,64-bytes" bitfld.word 0x00 11. " EP4_RX_ISO ,Receive ISO endpoint 4 field" "Bulk/interrupt,Isochronous" textline " " hexmask.word 0x00 0.--10. 1. " EP4_RX_PTR ,Address of the receive endpoint 4 pointer" endif if ((d.w(ad:0xFCF78A00+0x4A)&0x080000)==0x080000) group.word (0x4A)++0x1 line.word 0x00 "EP5_RX,Receive Endpoint 5 Configuration Register" bitfld.word 0x00 15. " EP5_RX_VALID ,Receive endpoint 5 valid" "Invalid,Valid" bitfld.word 0x00 12.--14. " EP5_RX_SIZE ,Receive endpoint 5 size " "8-bytes,16-bytes,32-bytes,64-bytes,128-bytes,256-bytes,512-bytes,1023-bytes" textline " " bitfld.word 0x00 11. " EP5_RX_ISO ,Receive ISO endpoint 5 field" "Bulk/interrupt,Isochronous" hexmask.word 0x00 0.--10. 1. " EP5_RX_PTR ,Address of the receive endpoint 5 pointer" else group.word (0x4A)++0x1 line.word 0x00 "EP5_RX,Receive Endpoint 5 Configuration Register" bitfld.word 0x00 15. " EP5_RX_VALID ,Receive endpoint 5 valid" "Invalid,Valid" bitfld.word 0x00 14. " EP5_RX_SIZE/DB ,Double buffer use for non-ISO receive endpoint 5" "Not used,Used" textline " " bitfld.word 0x00 12.--13. " EP5_RX_SIZE ,Receive endpoint 5 size " "8-bytes,16-bytes,32-bytes,64-bytes" bitfld.word 0x00 11. " EP5_RX_ISO ,Receive ISO endpoint 5 field" "Bulk/interrupt,Isochronous" textline " " hexmask.word 0x00 0.--10. 1. " EP5_RX_PTR ,Address of the receive endpoint 5 pointer" endif if ((d.w(ad:0xFCF78A00+0x4C)&0x080000)==0x080000) group.word (0x4C)++0x1 line.word 0x00 "EP6_RX,Receive Endpoint 6 Configuration Register" bitfld.word 0x00 15. " EP6_RX_VALID ,Receive endpoint 6 valid" "Invalid,Valid" bitfld.word 0x00 12.--14. " EP6_RX_SIZE ,Receive endpoint 6 size " "8-bytes,16-bytes,32-bytes,64-bytes,128-bytes,256-bytes,512-bytes,1023-bytes" textline " " bitfld.word 0x00 11. " EP6_RX_ISO ,Receive ISO endpoint 6 field" "Bulk/interrupt,Isochronous" hexmask.word 0x00 0.--10. 1. " EP6_RX_PTR ,Address of the receive endpoint 6 pointer" else group.word (0x4C)++0x1 line.word 0x00 "EP6_RX,Receive Endpoint 6 Configuration Register" bitfld.word 0x00 15. " EP6_RX_VALID ,Receive endpoint 6 valid" "Invalid,Valid" bitfld.word 0x00 14. " EP6_RX_SIZE/DB ,Double buffer use for non-ISO receive endpoint 6" "Not used,Used" textline " " bitfld.word 0x00 12.--13. " EP6_RX_SIZE ,Receive endpoint 6 size " "8-bytes,16-bytes,32-bytes,64-bytes" bitfld.word 0x00 11. " EP6_RX_ISO ,Receive ISO endpoint 6 field" "Bulk/interrupt,Isochronous" textline " " hexmask.word 0x00 0.--10. 1. " EP6_RX_PTR ,Address of the receive endpoint 6 pointer" endif if ((d.w(ad:0xFCF78A00+0x4E)&0x080000)==0x080000) group.word (0x4E)++0x1 line.word 0x00 "EP7_RX,Receive Endpoint 7 Configuration Register" bitfld.word 0x00 15. " EP7_RX_VALID ,Receive endpoint 7 valid" "Invalid,Valid" bitfld.word 0x00 12.--14. " EP7_RX_SIZE ,Receive endpoint 7 size " "8-bytes,16-bytes,32-bytes,64-bytes,128-bytes,256-bytes,512-bytes,1023-bytes" textline " " bitfld.word 0x00 11. " EP7_RX_ISO ,Receive ISO endpoint 7 field" "Bulk/interrupt,Isochronous" hexmask.word 0x00 0.--10. 1. " EP7_RX_PTR ,Address of the receive endpoint 7 pointer" else group.word (0x4E)++0x1 line.word 0x00 "EP7_RX,Receive Endpoint 7 Configuration Register" bitfld.word 0x00 15. " EP7_RX_VALID ,Receive endpoint 7 valid" "Invalid,Valid" bitfld.word 0x00 14. " EP7_RX_SIZE/DB ,Double buffer use for non-ISO receive endpoint 7" "Not used,Used" textline " " bitfld.word 0x00 12.--13. " EP7_RX_SIZE ,Receive endpoint 7 size " "8-bytes,16-bytes,32-bytes,64-bytes" bitfld.word 0x00 11. " EP7_RX_ISO ,Receive ISO endpoint 7 field" "Bulk/interrupt,Isochronous" textline " " hexmask.word 0x00 0.--10. 1. " EP7_RX_PTR ,Address of the receive endpoint 7 pointer" endif if ((d.w(ad:0xFCF78A00+0x50)&0x080000)==0x080000) group.word (0x50)++0x1 line.word 0x00 "EP8_RX,Receive Endpoint 8 Configuration Register" bitfld.word 0x00 15. " EP8_RX_VALID ,Receive endpoint 8 valid" "Invalid,Valid" bitfld.word 0x00 12.--14. " EP8_RX_SIZE ,Receive endpoint 8 size " "8-bytes,16-bytes,32-bytes,64-bytes,128-bytes,256-bytes,512-bytes,1023-bytes" textline " " bitfld.word 0x00 11. " EP8_RX_ISO ,Receive ISO endpoint 8 field" "Bulk/interrupt,Isochronous" hexmask.word 0x00 0.--10. 1. " EP8_RX_PTR ,Address of the receive endpoint 8 pointer" else group.word (0x50)++0x1 line.word 0x00 "EP8_RX,Receive Endpoint 8 Configuration Register" bitfld.word 0x00 15. " EP8_RX_VALID ,Receive endpoint 8 valid" "Invalid,Valid" bitfld.word 0x00 14. " EP8_RX_SIZE/DB ,Double buffer use for non-ISO receive endpoint 8" "Not used,Used" textline " " bitfld.word 0x00 12.--13. " EP8_RX_SIZE ,Receive endpoint 8 size " "8-bytes,16-bytes,32-bytes,64-bytes" bitfld.word 0x00 11. " EP8_RX_ISO ,Receive ISO endpoint 8 field" "Bulk/interrupt,Isochronous" textline " " hexmask.word 0x00 0.--10. 1. " EP8_RX_PTR ,Address of the receive endpoint 8 pointer" endif if ((d.w(ad:0xFCF78A00+0x52)&0x080000)==0x080000) group.word (0x52)++0x1 line.word 0x00 "EP9_RX,Receive Endpoint 9 Configuration Register" bitfld.word 0x00 15. " EP9_RX_VALID ,Receive endpoint 9 valid" "Invalid,Valid" bitfld.word 0x00 12.--14. " EP9_RX_SIZE ,Receive endpoint 9 size " "8-bytes,16-bytes,32-bytes,64-bytes,128-bytes,256-bytes,512-bytes,1023-bytes" textline " " bitfld.word 0x00 11. " EP9_RX_ISO ,Receive ISO endpoint 9 field" "Bulk/interrupt,Isochronous" hexmask.word 0x00 0.--10. 1. " EP9_RX_PTR ,Address of the receive endpoint 9 pointer" else group.word (0x52)++0x1 line.word 0x00 "EP9_RX,Receive Endpoint 9 Configuration Register" bitfld.word 0x00 15. " EP9_RX_VALID ,Receive endpoint 9 valid" "Invalid,Valid" bitfld.word 0x00 14. " EP9_RX_SIZE/DB ,Double buffer use for non-ISO receive endpoint 9" "Not used,Used" textline " " bitfld.word 0x00 12.--13. " EP9_RX_SIZE ,Receive endpoint 9 size " "8-bytes,16-bytes,32-bytes,64-bytes" bitfld.word 0x00 11. " EP9_RX_ISO ,Receive ISO endpoint 9 field" "Bulk/interrupt,Isochronous" textline " " hexmask.word 0x00 0.--10. 1. " EP9_RX_PTR ,Address of the receive endpoint 9 pointer" endif if ((d.w(ad:0xFCF78A00+0x54)&0x080000)==0x080000) group.word (0x54)++0x1 line.word 0x00 "EP10_RX,Receive Endpoint 10 Configuration Register" bitfld.word 0x00 15. " EP10_RX_VALID ,Receive endpoint 10 valid" "Invalid,Valid" bitfld.word 0x00 12.--14. " EP10_RX_SIZE ,Receive endpoint 10 size " "8-bytes,16-bytes,32-bytes,64-bytes,128-bytes,256-bytes,512-bytes,1023-bytes" textline " " bitfld.word 0x00 11. " EP10_RX_ISO ,Receive ISO endpoint 10 field" "Bulk/interrupt,Isochronous" hexmask.word 0x00 0.--10. 1. " EP10_RX_PTR ,Address of the receive endpoint 10 pointer" else group.word (0x54)++0x1 line.word 0x00 "EP10_RX,Receive Endpoint 10 Configuration Register" bitfld.word 0x00 15. " EP10_RX_VALID ,Receive endpoint 10 valid" "Invalid,Valid" bitfld.word 0x00 14. " EP10_RX_SIZE/DB ,Double buffer use for non-ISO receive endpoint 10" "Not used,Used" textline " " bitfld.word 0x00 12.--13. " EP10_RX_SIZE ,Receive endpoint 10 size " "8-bytes,16-bytes,32-bytes,64-bytes" bitfld.word 0x00 11. " EP10_RX_ISO ,Receive ISO endpoint 10 field" "Bulk/interrupt,Isochronous" textline " " hexmask.word 0x00 0.--10. 1. " EP10_RX_PTR ,Address of the receive endpoint 10 pointer" endif if ((d.w(ad:0xFCF78A00+0x56)&0x080000)==0x080000) group.word (0x56)++0x1 line.word 0x00 "EP11_RX,Receive Endpoint 11 Configuration Register" bitfld.word 0x00 15. " EP11_RX_VALID ,Receive endpoint 11 valid" "Invalid,Valid" bitfld.word 0x00 12.--14. " EP11_RX_SIZE ,Receive endpoint 11 size " "8-bytes,16-bytes,32-bytes,64-bytes,128-bytes,256-bytes,512-bytes,1023-bytes" textline " " bitfld.word 0x00 11. " EP11_RX_ISO ,Receive ISO endpoint 11 field" "Bulk/interrupt,Isochronous" hexmask.word 0x00 0.--10. 1. " EP11_RX_PTR ,Address of the receive endpoint 11 pointer" else group.word (0x56)++0x1 line.word 0x00 "EP11_RX,Receive Endpoint 11 Configuration Register" bitfld.word 0x00 15. " EP11_RX_VALID ,Receive endpoint 11 valid" "Invalid,Valid" bitfld.word 0x00 14. " EP11_RX_SIZE/DB ,Double buffer use for non-ISO receive endpoint 11" "Not used,Used" textline " " bitfld.word 0x00 12.--13. " EP11_RX_SIZE ,Receive endpoint 11 size " "8-bytes,16-bytes,32-bytes,64-bytes" bitfld.word 0x00 11. " EP11_RX_ISO ,Receive ISO endpoint 11 field" "Bulk/interrupt,Isochronous" textline " " hexmask.word 0x00 0.--10. 1. " EP11_RX_PTR ,Address of the receive endpoint 11 pointer" endif if ((d.w(ad:0xFCF78A00+0x58)&0x080000)==0x080000) group.word (0x58)++0x1 line.word 0x00 "EP12_RX,Receive Endpoint 12 Configuration Register" bitfld.word 0x00 15. " EP12_RX_VALID ,Receive endpoint 12 valid" "Invalid,Valid" bitfld.word 0x00 12.--14. " EP12_RX_SIZE ,Receive endpoint 12 size " "8-bytes,16-bytes,32-bytes,64-bytes,128-bytes,256-bytes,512-bytes,1023-bytes" textline " " bitfld.word 0x00 11. " EP12_RX_ISO ,Receive ISO endpoint 12 field" "Bulk/interrupt,Isochronous" hexmask.word 0x00 0.--10. 1. " EP12_RX_PTR ,Address of the receive endpoint 12 pointer" else group.word (0x58)++0x1 line.word 0x00 "EP12_RX,Receive Endpoint 12 Configuration Register" bitfld.word 0x00 15. " EP12_RX_VALID ,Receive endpoint 12 valid" "Invalid,Valid" bitfld.word 0x00 14. " EP12_RX_SIZE/DB ,Double buffer use for non-ISO receive endpoint 12" "Not used,Used" textline " " bitfld.word 0x00 12.--13. " EP12_RX_SIZE ,Receive endpoint 12 size " "8-bytes,16-bytes,32-bytes,64-bytes" bitfld.word 0x00 11. " EP12_RX_ISO ,Receive ISO endpoint 12 field" "Bulk/interrupt,Isochronous" textline " " hexmask.word 0x00 0.--10. 1. " EP12_RX_PTR ,Address of the receive endpoint 12 pointer" endif if ((d.w(ad:0xFCF78A00+0x5A)&0x080000)==0x080000) group.word (0x5A)++0x1 line.word 0x00 "EP13_RX,Receive Endpoint 13 Configuration Register" bitfld.word 0x00 15. " EP13_RX_VALID ,Receive endpoint 13 valid" "Invalid,Valid" bitfld.word 0x00 12.--14. " EP13_RX_SIZE ,Receive endpoint 13 size " "8-bytes,16-bytes,32-bytes,64-bytes,128-bytes,256-bytes,512-bytes,1023-bytes" textline " " bitfld.word 0x00 11. " EP13_RX_ISO ,Receive ISO endpoint 13 field" "Bulk/interrupt,Isochronous" hexmask.word 0x00 0.--10. 1. " EP13_RX_PTR ,Address of the receive endpoint 13 pointer" else group.word (0x5A)++0x1 line.word 0x00 "EP13_RX,Receive Endpoint 13 Configuration Register" bitfld.word 0x00 15. " EP13_RX_VALID ,Receive endpoint 13 valid" "Invalid,Valid" bitfld.word 0x00 14. " EP13_RX_SIZE/DB ,Double buffer use for non-ISO receive endpoint 13" "Not used,Used" textline " " bitfld.word 0x00 12.--13. " EP13_RX_SIZE ,Receive endpoint 13 size " "8-bytes,16-bytes,32-bytes,64-bytes" bitfld.word 0x00 11. " EP13_RX_ISO ,Receive ISO endpoint 13 field" "Bulk/interrupt,Isochronous" textline " " hexmask.word 0x00 0.--10. 1. " EP13_RX_PTR ,Address of the receive endpoint 13 pointer" endif if ((d.w(ad:0xFCF78A00+0x5C)&0x080000)==0x080000) group.word (0x5C)++0x1 line.word 0x00 "EP14_RX,Receive Endpoint 14 Configuration Register" bitfld.word 0x00 15. " EP14_RX_VALID ,Receive endpoint 14 valid" "Invalid,Valid" bitfld.word 0x00 12.--14. " EP14_RX_SIZE ,Receive endpoint 14 size " "8-bytes,16-bytes,32-bytes,64-bytes,128-bytes,256-bytes,512-bytes,1023-bytes" textline " " bitfld.word 0x00 11. " EP14_RX_ISO ,Receive ISO endpoint 14 field" "Bulk/interrupt,Isochronous" hexmask.word 0x00 0.--10. 1. " EP14_RX_PTR ,Address of the receive endpoint 14 pointer" else group.word (0x5C)++0x1 line.word 0x00 "EP14_RX,Receive Endpoint 14 Configuration Register" bitfld.word 0x00 15. " EP14_RX_VALID ,Receive endpoint 14 valid" "Invalid,Valid" bitfld.word 0x00 14. " EP14_RX_SIZE/DB ,Double buffer use for non-ISO receive endpoint 14" "Not used,Used" textline " " bitfld.word 0x00 12.--13. " EP14_RX_SIZE ,Receive endpoint 14 size " "8-bytes,16-bytes,32-bytes,64-bytes" bitfld.word 0x00 11. " EP14_RX_ISO ,Receive ISO endpoint 14 field" "Bulk/interrupt,Isochronous" textline " " hexmask.word 0x00 0.--10. 1. " EP14_RX_PTR ,Address of the receive endpoint 14 pointer" endif if ((d.w(ad:0xFCF78A00+0x5E)&0x080000)==0x080000) group.word (0x5E)++0x1 line.word 0x00 "EP15_RX,Receive Endpoint 15 Configuration Register" bitfld.word 0x00 15. " EP15_RX_VALID ,Receive endpoint 15 valid" "Invalid,Valid" bitfld.word 0x00 12.--14. " EP15_RX_SIZE ,Receive endpoint 15 size " "8-bytes,16-bytes,32-bytes,64-bytes,128-bytes,256-bytes,512-bytes,1023-bytes" textline " " bitfld.word 0x00 11. " EP15_RX_ISO ,Receive ISO endpoint 15 field" "Bulk/interrupt,Isochronous" hexmask.word 0x00 0.--10. 1. " EP15_RX_PTR ,Address of the receive endpoint 15 pointer" else group.word (0x5E)++0x1 line.word 0x00 "EP15_RX,Receive Endpoint 15 Configuration Register" bitfld.word 0x00 15. " EP15_RX_VALID ,Receive endpoint 15 valid" "Invalid,Valid" bitfld.word 0x00 14. " EP15_RX_SIZE/DB ,Double buffer use for non-ISO receive endpoint 15" "Not used,Used" textline " " bitfld.word 0x00 12.--13. " EP15_RX_SIZE ,Receive endpoint 15 size " "8-bytes,16-bytes,32-bytes,64-bytes" bitfld.word 0x00 11. " EP15_RX_ISO ,Receive ISO endpoint 15 field" "Bulk/interrupt,Isochronous" textline " " hexmask.word 0x00 0.--10. 1. " EP15_RX_PTR ,Address of the receive endpoint 15 pointer" endif if ((d.w(ad:0xFCF78A00+0x62)&0x080000)==0x080000) group.word (0x62)++0x1 line.word 0x00 "EP1_TX,Transmit Endpoint 1 Configuration Register" bitfld.word 0x00 15. " EP1_TX_VALID ,Transmit endpoint 1 valid" "Invalid,Valid" bitfld.word 0x00 12.--14. " EP1_TX_SIZE ,Transmit endpoint 1 size " "8-bytes,16-bytes,32-bytes,64-bytes,128-bytes,256-bytes,512-bytes,1023-bytes" textline " " bitfld.word 0x00 11. " EP1_TX_ISO ,Transmit ISO endpoint 1 field" "Bulk/interrupt,Isochronous" hexmask.word 0x00 0.--10. 1. " EP1_TX_PTR ,Address of the transmit endpoint 1 pointer" else group.word (0x62)++0x1 line.word 0x00 "EP1_TX,Transmit Endpoint 1 Configuration Register" bitfld.word 0x00 15. " EP1_TX_VALID ,Transmit endpoint 1 valid" "Invalid,Valid" bitfld.word 0x00 14. " EP1_TX_SIZE/DB ,Double buffer use for non-ISO transmit endpoint 1" "Not used,Used" textline " " bitfld.word 0x00 12.--13. " EP1_TX_SIZE ,Transmit endpoint 1 size " "8-bytes,16-bytes,32-bytes,64-bytes" bitfld.word 0x00 11. " EP1_TX_ISO ,Transmit ISO endpoint 1 field" "Bulk/interrupt,Isochronous" textline " " hexmask.word 0x00 0.--10. 1. " EP1_TX_PTR ,Address of the transmit endpoint 1 pointer" endif if ((d.w(ad:0xFCF78A00+0x64)&0x080000)==0x080000) group.word (0x64)++0x1 line.word 0x00 "EP2_TX,Transmit Endpoint 2 Configuration Register" bitfld.word 0x00 15. " EP2_TX_VALID ,Transmit endpoint 2 valid" "Invalid,Valid" bitfld.word 0x00 12.--14. " EP2_TX_SIZE ,Transmit endpoint 2 size " "8-bytes,16-bytes,32-bytes,64-bytes,128-bytes,256-bytes,512-bytes,1023-bytes" textline " " bitfld.word 0x00 11. " EP2_TX_ISO ,Transmit ISO endpoint 2 field" "Bulk/interrupt,Isochronous" hexmask.word 0x00 0.--10. 1. " EP2_TX_PTR ,Address of the transmit endpoint 2 pointer" else group.word (0x64)++0x1 line.word 0x00 "EP2_TX,Transmit Endpoint 2 Configuration Register" bitfld.word 0x00 15. " EP2_TX_VALID ,Transmit endpoint 2 valid" "Invalid,Valid" bitfld.word 0x00 14. " EP2_TX_SIZE/DB ,Double buffer use for non-ISO transmit endpoint 2" "Not used,Used" textline " " bitfld.word 0x00 12.--13. " EP2_TX_SIZE ,Transmit endpoint 2 size " "8-bytes,16-bytes,32-bytes,64-bytes" bitfld.word 0x00 11. " EP2_TX_ISO ,Transmit ISO endpoint 2 field" "Bulk/interrupt,Isochronous" textline " " hexmask.word 0x00 0.--10. 1. " EP2_TX_PTR ,Address of the transmit endpoint 2 pointer" endif if ((d.w(ad:0xFCF78A00+0x66)&0x080000)==0x080000) group.word (0x66)++0x1 line.word 0x00 "EP3_TX,Transmit Endpoint 3 Configuration Register" bitfld.word 0x00 15. " EP3_TX_VALID ,Transmit endpoint 3 valid" "Invalid,Valid" bitfld.word 0x00 12.--14. " EP3_TX_SIZE ,Transmit endpoint 3 size " "8-bytes,16-bytes,32-bytes,64-bytes,128-bytes,256-bytes,512-bytes,1023-bytes" textline " " bitfld.word 0x00 11. " EP3_TX_ISO ,Transmit ISO endpoint 3 field" "Bulk/interrupt,Isochronous" hexmask.word 0x00 0.--10. 1. " EP3_TX_PTR ,Address of the transmit endpoint 3 pointer" else group.word (0x66)++0x1 line.word 0x00 "EP3_TX,Transmit Endpoint 3 Configuration Register" bitfld.word 0x00 15. " EP3_TX_VALID ,Transmit endpoint 3 valid" "Invalid,Valid" bitfld.word 0x00 14. " EP3_TX_SIZE/DB ,Double buffer use for non-ISO transmit endpoint 3" "Not used,Used" textline " " bitfld.word 0x00 12.--13. " EP3_TX_SIZE ,Transmit endpoint 3 size " "8-bytes,16-bytes,32-bytes,64-bytes" bitfld.word 0x00 11. " EP3_TX_ISO ,Transmit ISO endpoint 3 field" "Bulk/interrupt,Isochronous" textline " " hexmask.word 0x00 0.--10. 1. " EP3_TX_PTR ,Address of the transmit endpoint 3 pointer" endif if ((d.w(ad:0xFCF78A00+0x68)&0x080000)==0x080000) group.word (0x68)++0x1 line.word 0x00 "EP4_TX,Transmit Endpoint 4 Configuration Register" bitfld.word 0x00 15. " EP4_TX_VALID ,Transmit endpoint 4 valid" "Invalid,Valid" bitfld.word 0x00 12.--14. " EP4_TX_SIZE ,Transmit endpoint 4 size " "8-bytes,16-bytes,32-bytes,64-bytes,128-bytes,256-bytes,512-bytes,1023-bytes" textline " " bitfld.word 0x00 11. " EP4_TX_ISO ,Transmit ISO endpoint 4 field" "Bulk/interrupt,Isochronous" hexmask.word 0x00 0.--10. 1. " EP4_TX_PTR ,Address of the transmit endpoint 4 pointer" else group.word (0x68)++0x1 line.word 0x00 "EP4_TX,Transmit Endpoint 4 Configuration Register" bitfld.word 0x00 15. " EP4_TX_VALID ,Transmit endpoint 4 valid" "Invalid,Valid" bitfld.word 0x00 14. " EP4_TX_SIZE/DB ,Double buffer use for non-ISO transmit endpoint 4" "Not used,Used" textline " " bitfld.word 0x00 12.--13. " EP4_TX_SIZE ,Transmit endpoint 4 size " "8-bytes,16-bytes,32-bytes,64-bytes" bitfld.word 0x00 11. " EP4_TX_ISO ,Transmit ISO endpoint 4 field" "Bulk/interrupt,Isochronous" textline " " hexmask.word 0x00 0.--10. 1. " EP4_TX_PTR ,Address of the transmit endpoint 4 pointer" endif if ((d.w(ad:0xFCF78A00+0x6A)&0x080000)==0x080000) group.word (0x6A)++0x1 line.word 0x00 "EP5_TX,Transmit Endpoint 5 Configuration Register" bitfld.word 0x00 15. " EP5_TX_VALID ,Transmit endpoint 5 valid" "Invalid,Valid" bitfld.word 0x00 12.--14. " EP5_TX_SIZE ,Transmit endpoint 5 size " "8-bytes,16-bytes,32-bytes,64-bytes,128-bytes,256-bytes,512-bytes,1023-bytes" textline " " bitfld.word 0x00 11. " EP5_TX_ISO ,Transmit ISO endpoint 5 field" "Bulk/interrupt,Isochronous" hexmask.word 0x00 0.--10. 1. " EP5_TX_PTR ,Address of the transmit endpoint 5 pointer" else group.word (0x6A)++0x1 line.word 0x00 "EP5_TX,Transmit Endpoint 5 Configuration Register" bitfld.word 0x00 15. " EP5_TX_VALID ,Transmit endpoint 5 valid" "Invalid,Valid" bitfld.word 0x00 14. " EP5_TX_SIZE/DB ,Double buffer use for non-ISO transmit endpoint 5" "Not used,Used" textline " " bitfld.word 0x00 12.--13. " EP5_TX_SIZE ,Transmit endpoint 5 size " "8-bytes,16-bytes,32-bytes,64-bytes" bitfld.word 0x00 11. " EP5_TX_ISO ,Transmit ISO endpoint 5 field" "Bulk/interrupt,Isochronous" textline " " hexmask.word 0x00 0.--10. 1. " EP5_TX_PTR ,Address of the transmit endpoint 5 pointer" endif if ((d.w(ad:0xFCF78A00+0x6C)&0x080000)==0x080000) group.word (0x6C)++0x1 line.word 0x00 "EP6_TX,Transmit Endpoint 6 Configuration Register" bitfld.word 0x00 15. " EP6_TX_VALID ,Transmit endpoint 6 valid" "Invalid,Valid" bitfld.word 0x00 12.--14. " EP6_TX_SIZE ,Transmit endpoint 6 size " "8-bytes,16-bytes,32-bytes,64-bytes,128-bytes,256-bytes,512-bytes,1023-bytes" textline " " bitfld.word 0x00 11. " EP6_TX_ISO ,Transmit ISO endpoint 6 field" "Bulk/interrupt,Isochronous" hexmask.word 0x00 0.--10. 1. " EP6_TX_PTR ,Address of the transmit endpoint 6 pointer" else group.word (0x6C)++0x1 line.word 0x00 "EP6_TX,Transmit Endpoint 6 Configuration Register" bitfld.word 0x00 15. " EP6_TX_VALID ,Transmit endpoint 6 valid" "Invalid,Valid" bitfld.word 0x00 14. " EP6_TX_SIZE/DB ,Double buffer use for non-ISO transmit endpoint 6" "Not used,Used" textline " " bitfld.word 0x00 12.--13. " EP6_TX_SIZE ,Transmit endpoint 6 size " "8-bytes,16-bytes,32-bytes,64-bytes" bitfld.word 0x00 11. " EP6_TX_ISO ,Transmit ISO endpoint 6 field" "Bulk/interrupt,Isochronous" textline " " hexmask.word 0x00 0.--10. 1. " EP6_TX_PTR ,Address of the transmit endpoint 6 pointer" endif if ((d.w(ad:0xFCF78A00+0x6E)&0x080000)==0x080000) group.word (0x6E)++0x1 line.word 0x00 "EP7_TX,Transmit Endpoint 7 Configuration Register" bitfld.word 0x00 15. " EP7_TX_VALID ,Transmit endpoint 7 valid" "Invalid,Valid" bitfld.word 0x00 12.--14. " EP7_TX_SIZE ,Transmit endpoint 7 size " "8-bytes,16-bytes,32-bytes,64-bytes,128-bytes,256-bytes,512-bytes,1023-bytes" textline " " bitfld.word 0x00 11. " EP7_TX_ISO ,Transmit ISO endpoint 7 field" "Bulk/interrupt,Isochronous" hexmask.word 0x00 0.--10. 1. " EP7_TX_PTR ,Address of the transmit endpoint 7 pointer" else group.word (0x6E)++0x1 line.word 0x00 "EP7_TX,Transmit Endpoint 7 Configuration Register" bitfld.word 0x00 15. " EP7_TX_VALID ,Transmit endpoint 7 valid" "Invalid,Valid" bitfld.word 0x00 14. " EP7_TX_SIZE/DB ,Double buffer use for non-ISO transmit endpoint 7" "Not used,Used" textline " " bitfld.word 0x00 12.--13. " EP7_TX_SIZE ,Transmit endpoint 7 size " "8-bytes,16-bytes,32-bytes,64-bytes" bitfld.word 0x00 11. " EP7_TX_ISO ,Transmit ISO endpoint 7 field" "Bulk/interrupt,Isochronous" textline " " hexmask.word 0x00 0.--10. 1. " EP7_TX_PTR ,Address of the transmit endpoint 7 pointer" endif if ((d.w(ad:0xFCF78A00+0x70)&0x080000)==0x080000) group.word (0x70)++0x1 line.word 0x00 "EP8_TX,Transmit Endpoint 8 Configuration Register" bitfld.word 0x00 15. " EP8_TX_VALID ,Transmit endpoint 8 valid" "Invalid,Valid" bitfld.word 0x00 12.--14. " EP8_TX_SIZE ,Transmit endpoint 8 size " "8-bytes,16-bytes,32-bytes,64-bytes,128-bytes,256-bytes,512-bytes,1023-bytes" textline " " bitfld.word 0x00 11. " EP8_TX_ISO ,Transmit ISO endpoint 8 field" "Bulk/interrupt,Isochronous" hexmask.word 0x00 0.--10. 1. " EP8_TX_PTR ,Address of the transmit endpoint 8 pointer" else group.word (0x70)++0x1 line.word 0x00 "EP8_TX,Transmit Endpoint 8 Configuration Register" bitfld.word 0x00 15. " EP8_TX_VALID ,Transmit endpoint 8 valid" "Invalid,Valid" bitfld.word 0x00 14. " EP8_TX_SIZE/DB ,Double buffer use for non-ISO transmit endpoint 8" "Not used,Used" textline " " bitfld.word 0x00 12.--13. " EP8_TX_SIZE ,Transmit endpoint 8 size " "8-bytes,16-bytes,32-bytes,64-bytes" bitfld.word 0x00 11. " EP8_TX_ISO ,Transmit ISO endpoint 8 field" "Bulk/interrupt,Isochronous" textline " " hexmask.word 0x00 0.--10. 1. " EP8_TX_PTR ,Address of the transmit endpoint 8 pointer" endif if ((d.w(ad:0xFCF78A00+0x72)&0x080000)==0x080000) group.word (0x72)++0x1 line.word 0x00 "EP9_TX,Transmit Endpoint 9 Configuration Register" bitfld.word 0x00 15. " EP9_TX_VALID ,Transmit endpoint 9 valid" "Invalid,Valid" bitfld.word 0x00 12.--14. " EP9_TX_SIZE ,Transmit endpoint 9 size " "8-bytes,16-bytes,32-bytes,64-bytes,128-bytes,256-bytes,512-bytes,1023-bytes" textline " " bitfld.word 0x00 11. " EP9_TX_ISO ,Transmit ISO endpoint 9 field" "Bulk/interrupt,Isochronous" hexmask.word 0x00 0.--10. 1. " EP9_TX_PTR ,Address of the transmit endpoint 9 pointer" else group.word (0x72)++0x1 line.word 0x00 "EP9_TX,Transmit Endpoint 9 Configuration Register" bitfld.word 0x00 15. " EP9_TX_VALID ,Transmit endpoint 9 valid" "Invalid,Valid" bitfld.word 0x00 14. " EP9_TX_SIZE/DB ,Double buffer use for non-ISO transmit endpoint 9" "Not used,Used" textline " " bitfld.word 0x00 12.--13. " EP9_TX_SIZE ,Transmit endpoint 9 size " "8-bytes,16-bytes,32-bytes,64-bytes" bitfld.word 0x00 11. " EP9_TX_ISO ,Transmit ISO endpoint 9 field" "Bulk/interrupt,Isochronous" textline " " hexmask.word 0x00 0.--10. 1. " EP9_TX_PTR ,Address of the transmit endpoint 9 pointer" endif if ((d.w(ad:0xFCF78A00+0x74)&0x080000)==0x080000) group.word (0x74)++0x1 line.word 0x00 "EP10_TX,Transmit Endpoint 10 Configuration Register" bitfld.word 0x00 15. " EP10_TX_VALID ,Transmit endpoint 10 valid" "Invalid,Valid" bitfld.word 0x00 12.--14. " EP10_TX_SIZE ,Transmit endpoint 10 size " "8-bytes,16-bytes,32-bytes,64-bytes,128-bytes,256-bytes,512-bytes,1023-bytes" textline " " bitfld.word 0x00 11. " EP10_TX_ISO ,Transmit ISO endpoint 10 field" "Bulk/interrupt,Isochronous" hexmask.word 0x00 0.--10. 1. " EP10_TX_PTR ,Address of the transmit endpoint 10 pointer" else group.word (0x74)++0x1 line.word 0x00 "EP10_TX,Transmit Endpoint 10 Configuration Register" bitfld.word 0x00 15. " EP10_TX_VALID ,Transmit endpoint 10 valid" "Invalid,Valid" bitfld.word 0x00 14. " EP10_TX_SIZE/DB ,Double buffer use for non-ISO transmit endpoint 10" "Not used,Used" textline " " bitfld.word 0x00 12.--13. " EP10_TX_SIZE ,Transmit endpoint 10 size " "8-bytes,16-bytes,32-bytes,64-bytes" bitfld.word 0x00 11. " EP10_TX_ISO ,Transmit ISO endpoint 10 field" "Bulk/interrupt,Isochronous" textline " " hexmask.word 0x00 0.--10. 1. " EP10_TX_PTR ,Address of the transmit endpoint 10 pointer" endif if ((d.w(ad:0xFCF78A00+0x76)&0x080000)==0x080000) group.word (0x76)++0x1 line.word 0x00 "EP11_TX,Transmit Endpoint 11 Configuration Register" bitfld.word 0x00 15. " EP11_TX_VALID ,Transmit endpoint 11 valid" "Invalid,Valid" bitfld.word 0x00 12.--14. " EP11_TX_SIZE ,Transmit endpoint 11 size " "8-bytes,16-bytes,32-bytes,64-bytes,128-bytes,256-bytes,512-bytes,1023-bytes" textline " " bitfld.word 0x00 11. " EP11_TX_ISO ,Transmit ISO endpoint 11 field" "Bulk/interrupt,Isochronous" hexmask.word 0x00 0.--10. 1. " EP11_TX_PTR ,Address of the transmit endpoint 11 pointer" else group.word (0x76)++0x1 line.word 0x00 "EP11_TX,Transmit Endpoint 11 Configuration Register" bitfld.word 0x00 15. " EP11_TX_VALID ,Transmit endpoint 11 valid" "Invalid,Valid" bitfld.word 0x00 14. " EP11_TX_SIZE/DB ,Double buffer use for non-ISO transmit endpoint 11" "Not used,Used" textline " " bitfld.word 0x00 12.--13. " EP11_TX_SIZE ,Transmit endpoint 11 size " "8-bytes,16-bytes,32-bytes,64-bytes" bitfld.word 0x00 11. " EP11_TX_ISO ,Transmit ISO endpoint 11 field" "Bulk/interrupt,Isochronous" textline " " hexmask.word 0x00 0.--10. 1. " EP11_TX_PTR ,Address of the transmit endpoint 11 pointer" endif if ((d.w(ad:0xFCF78A00+0x78)&0x080000)==0x080000) group.word (0x78)++0x1 line.word 0x00 "EP12_TX,Transmit Endpoint 12 Configuration Register" bitfld.word 0x00 15. " EP12_TX_VALID ,Transmit endpoint 12 valid" "Invalid,Valid" bitfld.word 0x00 12.--14. " EP12_TX_SIZE ,Transmit endpoint 12 size " "8-bytes,16-bytes,32-bytes,64-bytes,128-bytes,256-bytes,512-bytes,1023-bytes" textline " " bitfld.word 0x00 11. " EP12_TX_ISO ,Transmit ISO endpoint 12 field" "Bulk/interrupt,Isochronous" hexmask.word 0x00 0.--10. 1. " EP12_TX_PTR ,Address of the transmit endpoint 12 pointer" else group.word (0x78)++0x1 line.word 0x00 "EP12_TX,Transmit Endpoint 12 Configuration Register" bitfld.word 0x00 15. " EP12_TX_VALID ,Transmit endpoint 12 valid" "Invalid,Valid" bitfld.word 0x00 14. " EP12_TX_SIZE/DB ,Double buffer use for non-ISO transmit endpoint 12" "Not used,Used" textline " " bitfld.word 0x00 12.--13. " EP12_TX_SIZE ,Transmit endpoint 12 size " "8-bytes,16-bytes,32-bytes,64-bytes" bitfld.word 0x00 11. " EP12_TX_ISO ,Transmit ISO endpoint 12 field" "Bulk/interrupt,Isochronous" textline " " hexmask.word 0x00 0.--10. 1. " EP12_TX_PTR ,Address of the transmit endpoint 12 pointer" endif if ((d.w(ad:0xFCF78A00+0x7A)&0x080000)==0x080000) group.word (0x7A)++0x1 line.word 0x00 "EP13_TX,Transmit Endpoint 13 Configuration Register" bitfld.word 0x00 15. " EP13_TX_VALID ,Transmit endpoint 13 valid" "Invalid,Valid" bitfld.word 0x00 12.--14. " EP13_TX_SIZE ,Transmit endpoint 13 size " "8-bytes,16-bytes,32-bytes,64-bytes,128-bytes,256-bytes,512-bytes,1023-bytes" textline " " bitfld.word 0x00 11. " EP13_TX_ISO ,Transmit ISO endpoint 13 field" "Bulk/interrupt,Isochronous" hexmask.word 0x00 0.--10. 1. " EP13_TX_PTR ,Address of the transmit endpoint 13 pointer" else group.word (0x7A)++0x1 line.word 0x00 "EP13_TX,Transmit Endpoint 13 Configuration Register" bitfld.word 0x00 15. " EP13_TX_VALID ,Transmit endpoint 13 valid" "Invalid,Valid" bitfld.word 0x00 14. " EP13_TX_SIZE/DB ,Double buffer use for non-ISO transmit endpoint 13" "Not used,Used" textline " " bitfld.word 0x00 12.--13. " EP13_TX_SIZE ,Transmit endpoint 13 size " "8-bytes,16-bytes,32-bytes,64-bytes" bitfld.word 0x00 11. " EP13_TX_ISO ,Transmit ISO endpoint 13 field" "Bulk/interrupt,Isochronous" textline " " hexmask.word 0x00 0.--10. 1. " EP13_TX_PTR ,Address of the transmit endpoint 13 pointer" endif if ((d.w(ad:0xFCF78A00+0x7C)&0x080000)==0x080000) group.word (0x7C)++0x1 line.word 0x00 "EP14_TX,Transmit Endpoint 14 Configuration Register" bitfld.word 0x00 15. " EP14_TX_VALID ,Transmit endpoint 14 valid" "Invalid,Valid" bitfld.word 0x00 12.--14. " EP14_TX_SIZE ,Transmit endpoint 14 size " "8-bytes,16-bytes,32-bytes,64-bytes,128-bytes,256-bytes,512-bytes,1023-bytes" textline " " bitfld.word 0x00 11. " EP14_TX_ISO ,Transmit ISO endpoint 14 field" "Bulk/interrupt,Isochronous" hexmask.word 0x00 0.--10. 1. " EP14_TX_PTR ,Address of the transmit endpoint 14 pointer" else group.word (0x7C)++0x1 line.word 0x00 "EP14_TX,Transmit Endpoint 14 Configuration Register" bitfld.word 0x00 15. " EP14_TX_VALID ,Transmit endpoint 14 valid" "Invalid,Valid" bitfld.word 0x00 14. " EP14_TX_SIZE/DB ,Double buffer use for non-ISO transmit endpoint 14" "Not used,Used" textline " " bitfld.word 0x00 12.--13. " EP14_TX_SIZE ,Transmit endpoint 14 size " "8-bytes,16-bytes,32-bytes,64-bytes" bitfld.word 0x00 11. " EP14_TX_ISO ,Transmit ISO endpoint 14 field" "Bulk/interrupt,Isochronous" textline " " hexmask.word 0x00 0.--10. 1. " EP14_TX_PTR ,Address of the transmit endpoint 14 pointer" endif if ((d.w(ad:0xFCF78A00+0x7E)&0x080000)==0x080000) group.word (0x7E)++0x1 line.word 0x00 "EP15_TX,Transmit Endpoint 15 Configuration Register" bitfld.word 0x00 15. " EP15_TX_VALID ,Transmit endpoint 15 valid" "Invalid,Valid" bitfld.word 0x00 12.--14. " EP15_TX_SIZE ,Transmit endpoint 15 size " "8-bytes,16-bytes,32-bytes,64-bytes,128-bytes,256-bytes,512-bytes,1023-bytes" textline " " bitfld.word 0x00 11. " EP15_TX_ISO ,Transmit ISO endpoint 15 field" "Bulk/interrupt,Isochronous" hexmask.word 0x00 0.--10. 1. " EP15_TX_PTR ,Address of the transmit endpoint 15 pointer" else group.word (0x7E)++0x1 line.word 0x00 "EP15_TX,Transmit Endpoint 15 Configuration Register" bitfld.word 0x00 15. " EP15_TX_VALID ,Transmit endpoint 15 valid" "Invalid,Valid" bitfld.word 0x00 14. " EP15_TX_SIZE/DB ,Double buffer use for non-ISO transmit endpoint 15" "Not used,Used" textline " " bitfld.word 0x00 12.--13. " EP15_TX_SIZE ,Transmit endpoint 15 size " "8-bytes,16-bytes,32-bytes,64-bytes" bitfld.word 0x00 11. " EP15_TX_ISO ,Transmit ISO endpoint 15 field" "Bulk/interrupt,Isochronous" textline " " hexmask.word 0x00 0.--10. 1. " EP15_TX_PTR ,Address of the transmit endpoint 15 pointer" endif tree.end width 11. tree.end endif endif sif (cpu()=="RM46L852-PGE"||cpu()=="RM46L852-ZWT"||cpu()=="RM46L850-PGE"||cpu()=="RM46L850-ZWT"||cpu()=="RM46L840-ZWT"||cpu()=="RM46L840-PGE"||cpu()=="RM46L830-ZWT"||cpu()=="RM46L830-PGE"||cpu()=="RM46L450-ZWT"||cpu()=="RM46L450-PGE"||cpu()=="RM46L440-ZWT"||cpu()=="RM46L440-PGE"||cpu()=="RM46L430-ZWT"||cpu()=="RM46L430-PGE"||cpu()=="RM42L432") tree "eFUSE (eFuse Controller Registers)" base ad:0xFFF8C000 width 12. group.long 0x1C++0x03 line.long 0x00 "EFCBOUND,EFC Boundary Control Register" bitfld.long 0x00 21. " EFC_SELF_TEST_ERROR ,EFC self test error" "No error,Error" bitfld.long 0x00 20. " EFC_SINGLE_BIT_ERROR ,EFC single bit error" "No error,Error" textline " " bitfld.long 0x00 19. " EFC_INSTRUCTION_ERROR ,EFC instruction error" "No error,Error" bitfld.long 0x00 18. " EFC_AUTOLOAD_ERROR ,EFC autoload error" "No error,Error" textline " " bitfld.long 0x00 17. " SELF_TEST_ERROR_OE ,Self test error OE" "eFuse controller,Boundary register" bitfld.long 0x00 16. " SINGLE_BIT_ERROR_OE ,Single bit error OE" "eFuse controller,Boundary register" textline " " bitfld.long 0x00 15. " INSTRUCTION_ERROR_OE ,Instruction error OE" "eFuse controller,Boundary register" bitfld.long 0x00 14. " AUTOLOAD_ERROR_OE ,Autoload error OE" "eFuse controller,Boundary register" textline " " bitfld.long 0x00 13. " EFC_ECC_SELFTEST_ENABLE ,EFC ECC selftest enable" "Disabled,Enabled" bitfld.long 0x00 0.--3. " INPUT_ENABLE ,Input enable" "Not started,Not started,Not started,Not started,Not started,Not started,Not started,Not started,Not started,Not started,Not started,Not started,Not started,Not started,Not started,Started" rgroup.long 0x2C++0x03 line.long 0x00 "EFCPINS,EFC Pins Register" bitfld.long 0x00 15. " EFC_SELFTEST_DONE ,Determine when the EFC ECC selftest is complete" "Not completed,Completed" bitfld.long 0x00 14. " EFC_SELFTEST_ERROR ,Indicates the pass/fail status of the EFC ECC selftest" "Passed,Failed" textline " " bitfld.long 0x00 12. " EFC_SINGLE_BIT_ERROR ,Indicates if a single bit error was corrected by the ECC logic" "No error,Error" bitfld.long 0x00 11. " EFC_INSTRUCTION_ERROR ,Indicates an error occurred during a factory test or program operation" "Not error,Error" textline " " bitfld.long 0x00 10. " EFC_AUTOLOAD_ERROR ,Indicates that some non-correctable error occurred during the autoload sequence after reset" "No error,Error" group.long 0x3C++0x03 line.long 0x00 "EFCERRSTAT,EFC Error Status Register" bitfld.long 0x00 5. " INSTRUC_DONE ,Indicate that the eFuse self test has completed" "Not done,Done" bitfld.long 0x00 0.--4. " ERROR_CODE ,The error status of the last instruction executed by the eFuse Controller" "No error,,,,,Multibit error,,,,,,,,,,Single bit error,,,Signature not match,?..." group.long 0x48++0x07 line.long 0x00 "EFCSTCY,EFC Self Test Cycles Register" line.long 0x04 "EFCSTSIG,EFC Self Test Signature Register" width 0x0B tree.end endif sif (cpu()=="RM48L952-PGE"||cpu()=="RM48L952-ZWT"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L540-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE") tree "DMM (Data Modification Module)" base ad:0xFFFFF700 width 16. group.long 0x00++0x07 line.long 0x00 "GLBCTRL,DMM Global Control Register" bitfld.long 0x00 24. " BUSY ,Busy indicator" "Not received,Received" sif !cpuis("TMS570LS3137-EP") bitfld.long 0x00 18. " CONTCLK ,Continuous RTPCLK output" "Suspended,Continue" else bitfld.long 0x00 18. " CONTCLK ,Continuous DMMCLK input" "Suspended,Continue" endif bitfld.long 0x00 17. " COS ,Continue on suspend" "Suspended,Continue" newline bitfld.long 0x00 16. " RESET ,This bit resets the state machine and the registers to its reset value" "No reset,Reset" bitfld.long 0x00 9.--10. " DDM_WIDTH ,Packet width in Direct Data Mode" "8 bits,16 bits,32 bits,?..." bitfld.long 0x00 8. " TM_DMM ,Packet format" "Trace Mode,Direct Data Mode" newline bitfld.long 0x00 0.--3. " ON/OFF ,DMM module receives data enable" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" line.long 0x04 "INTSET_SET/CLR,DMM Interrupt Set Register" setclrfld.long 0x04 17. 0x04 17. 0x08 17. " PROG_BUFF ,Programmable buffer interrupt" "No interrupt,Interrupt" setclrfld.long 0x04 16. 0x04 16. 0x08 16. " EO_BUFF ,End of buffer interrupt" "No interrupt,Interrupt" newline setclrfld.long 0x04 15. 0x04 15. 0x08 15. " DEST3REG2 ,Destination 3 Region 2 interrupt" "No interrupt,Interrupt" setclrfld.long 0x04 14. 0x04 14. 0x08 14. " DEST3REG1 ,Destination 3 Region 1 interrupt" "No interrupt,Interrupt" newline setclrfld.long 0x04 13. 0x04 13. 0x08 13. " DEST2REG2 ,Destination 2 Region 2 interrupt" "No interrupt,Interrupt" setclrfld.long 0x04 12. 0x04 12. 0x08 12. " DEST2REG1 ,Destination 2 Region 1 interrupt" "No interrupt,Interrupt" newline setclrfld.long 0x04 11. 0x04 11. 0x08 11. " DEST1REG2 ,Destination 1 Region 2 interrupt" "No interrupt,Interrupt" setclrfld.long 0x04 10. 0x04 10. 0x08 10. " DEST1REG1 ,Destination 1 Region 1 interrupt" "No interrupt,Interrupt" newline setclrfld.long 0x04 9. 0x04 9. 0x08 9. " DEST0REG2 ,Destination 0 Region 2 interrupt" "No interrupt,Interrupt" setclrfld.long 0x04 8. 0x04 8. 0x08 8. " DEST0REG1 ,Destination 0 Region 1 interrupt" "No interrupt,Interrupt" newline setclrfld.long 0x04 7. 0x04 7. 0x08 7. " BUSERROR ,BMM bus error response" "No interrupt,Interrupt" setclrfld.long 0x04 6. 0x04 6. 0x08 6. " BUFF_OVF ,Write buffer overflow interrupt" "No interrupt,Interrupt" newline setclrfld.long 0x04 5. 0x04 5. 0x08 5. " SRC_OVF ,Source overflow interrupt" "No interrupt,Interrupt" setclrfld.long 0x04 4. 0x04 4. 0x08 4. " DEST3_ERRENA ,Destination 3 error interrupt" "No interrupt,Interrupt" newline setclrfld.long 0x04 3. 0x04 3. 0x08 3. " DEST2_ERRENA ,Destination 2 error interrupt" "No interrupt,Interrupt" setclrfld.long 0x04 2. 0x04 2. 0x08 2. " DEST1_ERRENA_ ,Destination 1 error interrupt" "No interrupt,Interrupt" newline setclrfld.long 0x04 1. 0x04 1. 0x08 1. " DEST0_ERRENA ,Destination 0 error interrupt" "No interrupt,Interrupt" setclrfld.long 0x04 0. 0x04 0. 0x08 0. " PACKET_ERR_INT ,Packet error interrupt" "No interrupt,Interrupt" group.long 0x0C++0x07 line.long 0x00 "INTLVL,DMM Interrupt Level Register" bitfld.long 0x00 17. " PROG_BUFF ,Programmable buffer interrupt level" "Level 0,Level 1" bitfld.long 0x00 16. " EO_BUFF ,End of buffer interrupt level" "Level 0,Level 1" bitfld.long 0x00 15. " DEST3REG2 ,Destination 3 Region 2 interrupt level" "Level 0,Level 1" newline bitfld.long 0x00 14. " DEST3REG1 ,Destination 3 Region 1 interrupt level" "Level 0,Level 1" bitfld.long 0x00 13. " DEST2REG2 ,Destination 2 Region 2 Interrupt Level" "Level 0,Level 1" bitfld.long 0x00 12. " DEST2REG1 ,Destination 2 Region 1 interrupt level" "Level 0,Level 1" newline bitfld.long 0x00 11. " DEST1REG2 ,Destination 1 Region 2 interrupt level" "Level 0,Level 1" bitfld.long 0x00 10. " DEST1REG1 ,Destination 1 Region 1 interrupt level" "Level 0,Level 1" bitfld.long 0x00 9. " DEST0REG2 ,Destination 0 Region 2 interrupt level" "Level 0,Level 1" newline bitfld.long 0x00 8. " DEST0REG1 ,Destination 0 Region 1 interrupt level" "Level 0,Level 1" bitfld.long 0x00 7. " BUSERROR ,BMM bus error response" "Level 0,Level 1" bitfld.long 0x00 6. " BUFF_OVF ,Write buffer overflow interrupt level" "Level 0,Level 1" newline bitfld.long 0x00 5. " SRC_OVF ,Source overflow interrupt level" "Level 0,Level 1" bitfld.long 0x00 4. " DEST3_ERRENA ,Destination 3 error interrupt level" "Level 0,Level 1" bitfld.long 0x00 3. " DEST2_ERRENA ,Destination 2 error interrupt level" "Level 0,Level 1" newline bitfld.long 0x00 2. " DEST1_ERRENA ,Destination 1 error interrupt level" "Level 0,Level 1" bitfld.long 0x00 1. " DEST0_ERRENA ,Destination 0 error interrupt level" "Level 0,Level 1" bitfld.long 0x00 0. " PACKET_ERR_INT ,Packet error interrupt level" "Level 0,Level 1" line.long 0x04 "INTFLAG,DMM Interrupt Flag Register" eventfld.long 0x04 17. " PROG_BUFF ,Programmable buffer interrupt flag" "No interrupt,Interrupt" eventfld.long 0x04 16. " EO_BUFF ,End of buffer interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x04 15. " DEST3REG2 ,Destination 3 Region 2 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x04 14. " DEST3REG1 ,Destination 3 Region 1 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x04 13. " DEST2REG2 ,Destination 2 Region 2 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x04 12. " DEST2REG1 ,Destination 2 Region 1 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x04 11. " DEST1REG2 ,Destination 1 Region 2 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x04 10. " DEST1REG1 ,Destination 1 Region 1 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x04 9. " DEST0REG2 ,Destination 0 Region 2 interrupt flag" "No interrupt,Interrupt" eventfld.long 0x04 8. " DEST0REG1 ,Destination 0 Region 1 interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x04 7. " BUSERROR ,BMM bus error response" "No interrupt,Interrupt" eventfld.long 0x04 6. " BUFF_OVF ,Write buffer overflow interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x04 5. " SRC_OVF ,Source overflow interrupt flag" "No interrupt,Interrupt" eventfld.long 0x04 4. " DEST3_ERRENA ,Destination 3 error interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x04 3. " DEST2_ERRENA ,Destination 2 error interrupt flag" "No interrupt,Interrupt" eventfld.long 0x04 2. " DEST1_ERRENA ,Destination 1 error interrupt flag" "No interrupt,Interrupt" newline eventfld.long 0x04 1. " DEST0_ERRENA ,Destination 0 error interrupt flag" "No interrupt,Interrupt" eventfld.long 0x04 0. " PACKET_ERR_INT ,Packet error interrupt flag" "No interrupt,Interrupt" hgroup.long 0x14++0x03 hide.long 0x00 "OFF1,DMM Interrupt Offset 1 Register" in hgroup.long 0x18++0x03 hide.long 0x00 "OFF2,DMM Interrupt Offset 2 Register" in group.long 0x1C++0x07 line.long 0x00 "DDMDEST,DDM Direct Data Mode Destination Register" line.long 0x04 "DDMBL,DMM Direct Data Mode Blocksize Register" bitfld.long 0x04 0.--3. " BLOCKSIZE ,These bits define the size of the buffer region" "0 B,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,?..." rgroup.long 0x24++0x03 line.long 0x00 "DDMPT,DMM Direct Data Mode Pointer Register" hexmask.long.word 0x00 0.--14. 1. " POINTER ,Hold the pointer to the next entry to be written in the buffer" group.long 0x28++0x4B line.long 0x00 "INTPT,DDM Direct Data Mode Interrupt Pointer Register" hexmask.long.word 0x00 0.--14. 1. " INTPT ,Interrupt Pointer" line.long 0x04 "DEST0REG1,DDM Destination 0 Region 1" hexmask.long.word 0x04 18.--31. 0x04 " BASEADDR ,Base Address" hexmask.long.tbyte 0x04 0.--17. 1. " BLOCKADDR ,Block Address" line.long 0x08 "DEST0BL1,DDM Destination 0 Blocksize 1" bitfld.long 0x08 0.--3. " BLOCKSIZE ,Block Size" "0 kB,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." line.long 0x0C "DEST0REG2,DDM Destination 0 Region 2" hexmask.long.word 0x0C 18.--31. 0x4 " BASEADDR ,Base Address" hexmask.long.tbyte 0x0C 0.--17. 1. " BLOCKADDR ,Block Address" line.long 0x10 "DEST0BL2,DDM Destination 0 Blocksize 2" bitfld.long 0x10 0.--3. " BLOCKSIZE ,Block Size" "0 kB,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." line.long 0x14 "DEST1REG1,DDM Destination 1 Region 1" hexmask.long.word 0x14 18.--31. 0x4 " BASEADDR ,Base Address" hexmask.long.tbyte 0x14 0.--17. 1. " BLOCKADDR ,Block Address" line.long 0x18 "DEST1BL1,DDM Destination 1 Blocksize 1" bitfld.long 0x18 0.--3. " BLOCKSIZE ,Block Size" "0 kB,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." line.long 0x1C "DEST1REG2,DDM Destination 1 Region 2" hexmask.long.word 0x1C 18.--31. 0x4 " BASEADDR ,Base Address" hexmask.long.tbyte 0x1C 0.--17. 1. " BLOCKADDR ,Block Address" line.long 0x20 "DEST1BL2,DDM Destination 1 Blocksize 2" bitfld.long 0x20 0.--3. " BLOCKSIZE ,Block Size" "0 kB,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." line.long 0x24 "DEST2REG1,DDM Destination 2 Region 1" hexmask.long.word 0x24 18.--31. 0x4 " BASEADDR ,Base Address" hexmask.long.tbyte 0x24 0.--17. 1. " BLOCKADDR ,Block Address" line.long 0x28 "DEST2BL1,DDM Destination 2 Blocksize 1" bitfld.long 0x28 0.--3. " BLOCKSIZE ,Block Size" "0 kB,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." line.long 0x2C "DEST2REG2,DDM Destination 2 Region 2" hexmask.long.word 0x2C 18.--31. 0x4 " BASEADDR ,Base Address" hexmask.long.tbyte 0x2C 0.--17. 1. " BLOCKADDR ,Block Address" line.long 0x30 "DEST2BL2,DDM Destination 2 Blocksize 2" bitfld.long 0x30 0.--3. " BLOCKSIZE ,Block Size" "0 kB,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." line.long 0x34 "DEST3REG1,DDM Destination 3 Region 1" hexmask.long.word 0x34 18.--31. 0x4 " BASEADDR ,Base Address" hexmask.long.tbyte 0x34 0.--17. 1. " BLOCKADDR ,Block Address" line.long 0x38 "DEST3BL1,DDM Destination 3 Blocksize 1" bitfld.long 0x38 0.--3. " BLOCKSIZE ,Block Size" "0 kB,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." line.long 0x3C "DEST3REG2,DDM Destination 3 Region 2" hexmask.long.word 0x3C 18.--31. 0x4 " BASEADDR ,Base Address" hexmask.long.tbyte 0x3C 0.--17. 1. " BLOCKADDR ,Block Address" line.long 0x40 "DEST3BL2,DDM Destination 3 Blocksize 2" bitfld.long 0x40 0.--3. " BLOCKSIZE ,Block Size" "0 kB,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." line.long 0x44 "PC0,DDM Pin Control 0 (FUNC)" bitfld.long 0x44 18. " ENAFUNC ,DMMENA functional mode pin" "GIO mode,Functional mode" bitfld.long 0x44 17. " DATA15FUNC ,DMMDATA[15] functional mode pin" "GIO mode,Functional mode" newline bitfld.long 0x44 16. " DATA14FUNC ,DMMDATA[14] functional mode pin" "GIO mode,Functional mode" bitfld.long 0x44 15. " DATA13FUNC ,DMMDATA[13] functional mode pin" "GIO mode,Functional mode" newline bitfld.long 0x44 14. " DATA12FUNC ,DMMDATA[12] functional mode pin" "GIO mode,Functional mode" bitfld.long 0x44 13. " DATA11FUNC ,DMMDATA[11] functional mode pin" "GIO mode,Functional mode" newline bitfld.long 0x44 12. " DATA10FUNC ,DMMDATA[10] functional mode pin" "GIO mode,Functional mode" bitfld.long 0x44 11. " DATA9FUNC ,DMMDATA[9] functional mode pin" "GIO mode,Functional mode" newline bitfld.long 0x44 10. " DATA8FUNC ,DMMDATA[8] functional mode pin" "GIO mode,Functional mode" bitfld.long 0x44 9. " DATA7FUNC ,DMMDATA[7] functional mode pin" "GIO mode,Functional mode" newline bitfld.long 0x44 8. " DATA6FUNC ,DMMDATA[6] functional mode pin" "GIO mode,Functional mode" bitfld.long 0x44 7. " DATA5FUNC ,DMMDATA[5] functional mode pin" "GIO mode,Functional mode" newline bitfld.long 0x44 6. " DATA4FUNC ,DMMDATA[4] functional mode pin" "GIO mode,Functional mode" bitfld.long 0x44 5. " DATA3FUNC ,DMMDATA[3] functional mode pin" "GIO mode,Functional mode" newline bitfld.long 0x44 4. " DATA2FUNC ,DMMDATA[2] functional mode pin" "GIO mode,Functional mode" bitfld.long 0x44 3. " DATA1FUNC ,DMMDATA[1] functional mode pin" "GIO mode,Functional mode" newline bitfld.long 0x44 2. " DATA0FUNC ,DMMDATA[0] functional mode pin" "GIO mode,Functional mode" bitfld.long 0x44 1. " CLKFUNC ,DMMCLK functional mode pin" "GIO mode,Functional mode" newline bitfld.long 0x44 0. " SYNCFUNC ,DMMSYNC functional mode pin" "GIO mode,Functional mode" line.long 0x48 "PC1,DDM Pin Control 1 (DIR)" bitfld.long 0x48 18. " ENADIR ,DMMENA direction pin (GIO mode)" "Input,Output" bitfld.long 0x48 17. " DATA15DIR ,DMMDATA[15] direction pin (GIO mode)" "Input,Output" bitfld.long 0x48 16. " DATA14DIR ,DMMDATA[14] direction pin (GIO mode)" "Input,Output" newline bitfld.long 0x48 15. " DATA13DIR ,DMMDATA[13] direction pin (GIO mode)" "Input,Output" bitfld.long 0x48 14. " DATA12DIR ,DMMDATA[12] direction pin (GIO mode)" "Input,Output" bitfld.long 0x48 13. " DATA11DIR ,DMMDATA[11] direction pin (GIO mode)" "Input,Output" newline bitfld.long 0x48 12. " DATA10DIR ,DMMDATA[10] direction pin (GIO mode)" "Input,Output" bitfld.long 0x48 11. " DATA9DIR ,DMMDATA[9] direction pin (GIO mode)" "Input,Output" bitfld.long 0x48 10. " DATA8DIR ,DMMDATA[8] direction pin (GIO mode)" "Input,Output" newline bitfld.long 0x48 9. " DATA7DIR ,DMMDATA[7] direction pin (GIO mode)" "Input,Output" bitfld.long 0x48 8. " DATA6DIR ,DMMDATA[6] direction pin (GIO mode)" "Input,Output" bitfld.long 0x48 7. " DATA5DIR ,DMMDATA[5] direction pin (GIO mode)" "Input,Output" newline bitfld.long 0x48 6. " DATA4DIR ,DMMDATA[4] direction pin (GIO mode)" "Input,Output" bitfld.long 0x48 5. " DATA3DIR ,DMMDATA[3] direction pin (GIO mode)" "Input,Output" bitfld.long 0x48 4. " DATA2DIR ,DMMDATA[2] direction pin (GIO mode)" "Input,Output" newline bitfld.long 0x48 3. " DATA1DIR ,DMMDATA[1] direction pin (GIO mode)" "Input,Output" bitfld.long 0x48 2. " DATA0DIR ,DMMDATA[0] direction pin (GIO mode)" "Input,Output" bitfld.long 0x48 1. " CLKDIR ,DMMCLK direction pin (GIO mode)" "Input,Output" newline bitfld.long 0x48 0. " SYNCDIR ,DMMSYNC direction pin (GIO mode)" "Input,Output" rgroup.long 0x74++0x03 line.long 0x00 "PC2,DDM Pin Control 2 (DIN)" bitfld.long 0x00 18. " ENAIN ,DMMENA input" "Low,High" bitfld.long 0x00 17. " DATA15IN ,DMMDATA[15] input" "Low,High" bitfld.long 0x00 16. " DATA14IN ,DMMDATA[14] input" "Low,High" bitfld.long 0x00 15. " DATA13IN ,DMMDATA[13] input" "Low,High" newline bitfld.long 0x00 14. " DATA12IN ,DMMDATA[12] input" "Low,High" bitfld.long 0x00 13. " DATA11IN ,DMMDATA[11] input" "Low,High" bitfld.long 0x00 12. " DATA10IN ,DMMDATA[10] input" "Low,High" bitfld.long 0x00 11. " DATA9IN ,DMMDATA[9] input" "Low,High" newline bitfld.long 0x00 10. " DATA8IN ,DMMDATA[8] input" "Low,High" bitfld.long 0x00 9. " DATA7IN ,DMMDATA[7] input" "Low,High" bitfld.long 0x00 8. " DATA6IN ,DMMDATA[6] input" "Low,High" bitfld.long 0x00 7. " DATA5IN ,DMMDATA[5] input" "Low,High" newline bitfld.long 0x00 6. " DATA4IN ,DMMDATA[4] input" "Low,High" bitfld.long 0x00 5. " DATA3IN ,DMMDATA[3] input" "Low,High" bitfld.long 0x00 4. " DATA2IN ,DMMDATA[2] input" "Low,High" bitfld.long 0x00 3. " DATA1IN ,DMMDATA[1] input" "Low,High" newline bitfld.long 0x00 2. " DATA0IN ,DMMDATA[0] input" "Low,High" bitfld.long 0x00 1. " CLKIN ,DMMCLK input" "Low,High" bitfld.long 0x00 0. " SYNCIN ,DMMSYNC input" "Low,High" group.long 0x78++0x03 line.long 0x00 "PC3,DMM Pin Control 3 (OUT)" setclrfld.long 0x00 18. 0x04 18. 0x08 18. " ENAOUT_set/clr ,DMMENA output state" "Low,High" setclrfld.long 0x00 17. 0x04 17. 0x08 17. " DATA15OUT_set/clr ,DMMDATA[15] output state" "Low,High" newline setclrfld.long 0x00 16. 0x04 16. 0x08 16. " DATA14OUT_set/clr ,DMMDATA[14] output state" "Low,High" setclrfld.long 0x00 15. 0x04 15. 0x08 15. " DATA13OUT_set/clr ,DMMDATA[13] output state" "Low,High" newline setclrfld.long 0x00 14. 0x04 14. 0x08 14. " DATA12OUT_set/clr ,DMMDATA[12] output state" "Low,High" setclrfld.long 0x00 13. 0x04 13. 0x08 13. " DATA11OUT_set/clr ,DMMDATA[11] output state" "Low,High" newline setclrfld.long 0x00 12. 0x04 12. 0x08 12. " DATA10OUT_set/clr ,DMMDATA[10] output state" "Low,High" setclrfld.long 0x00 11. 0x04 11. 0x08 11. " DATA9OUT_set/clr ,DMMDATA[9] output state" "Low,High" newline setclrfld.long 0x00 10. 0x04 10. 0x08 10. " DATA8OUT_set/clr ,DMMDATA[8] output state" "Low,High" setclrfld.long 0x00 9. 0x04 9. 0x08 9. " DATA7OUT_set/clr ,DMMDATA[7] output state" "Low,High" newline setclrfld.long 0x00 8. 0x04 8. 0x08 8. " DATA6OUT_set/clr ,DMMDATA[6] output state" "Low,High" setclrfld.long 0x00 7. 0x04 7. 0x08 7. " DATA5OUT_set/clr ,DMMDATA[5] output state" "Low,High" newline setclrfld.long 0x00 6. 0x04 6. 0x08 6. " DATA4OUT_set/clr ,DMMDATA[4] output state" "Low,High" setclrfld.long 0x00 5. 0x04 5. 0x08 5. " DATA3OUT_set/clr ,DMMDATA[3] output state" "Low,High" newline setclrfld.long 0x00 4. 0x04 4. 0x08 4. " DATA2OUT_set/clr ,DMMDATA[2] output state" "Low,High" setclrfld.long 0x00 3. 0x04 3. 0x08 3. " DATA1OUT_set/clr ,DMMDATA[1] output state" "Low,High" newline setclrfld.long 0x00 2. 0x04 2. 0x08 2. " DATA0OUT_set/clr ,DMMDATA[0] output state" "Low,High" setclrfld.long 0x00 1. 0x04 1. 0x08 1. " CLKOUT_set/clr ,DMMCLK output state" "Low,High" newline setclrfld.long 0x00 0. 0x04 0. 0x08 0. " SYNCOUT_set/clr ,DMMSYNC output state" "Low,High" sif cpu()==("TMS570LS2124-PGE")||cpu()==("TMS570LS2124-ZWT")||cpu()==("TMS570LS2125-PGE")||cpu()==("TMS570LS2125-ZWT")||(cpu()=="TMS570LS2126")||(cpu()=="TMS570LS2127")||cpu()==("TMS570LS2134-PGE")||cpu()==("TMS570LS2134-ZWT")||cpu()==("TMS570LS2135-PGE")||cpu()==("TMS570LS2135-ZWT")||(cpu()=="TMS570LS2136")||(cpu()=="TMS570LS2137")||cpu()==("TMS570LS3134-PGE")||cpu()==("TMS570LS3134-ZWT")||cpu()==("TMS570LS3135-PGE")||cpu()==("TMS570LS3135-ZWT")||(cpu()=="TMS570LS3136")||(cpu()=="TMS570LS3137-PGE")||(cpu()=="TMS570LS3137-ZWT")||(cpu()=="TMS570LS30336") group.long 0x7C++0x03 line.long 0x00 "DSet,Pin Control 4" group.long 0x80++0x03 line.long 0x00 "DClr,Pin Control 5" endif group.long 0x84++0x0B line.long 0x00 "PC6,DDM Pin Control 6 (PDR)" bitfld.long 0x00 18. " ENAPDR ,DMMENA open drain enable" "Disabled,Enabled" bitfld.long 0x00 17. " DATA15PDR ,DMMDATA[15] open drain enable" "Disabled,Enabled" bitfld.long 0x00 16. " DATA14PDR ,DMMDATA[14] open drain enable" "Disabled,Enabled" newline bitfld.long 0x00 15. " DATA13PDR ,DMMDATA[13] open drain enable" "Disabled,Enabled" bitfld.long 0x00 14. " DATA12PDR ,DMMDATA[12] open drain enable" "Disabled,Enabled" bitfld.long 0x00 13. " DATA11PDR ,DMMDATA[11] open drain enable" "Disabled,Enabled" newline bitfld.long 0x00 12. " DATA10PDR ,DMMDATA[10] open drain enable" "Disabled,Enabled" bitfld.long 0x00 11. " DATA9PDR ,DMMDATA[9] open drain enable" "Disabled,Enabled" bitfld.long 0x00 10. " DATA8PDR ,DMMDATA[8] open drain enable" "Disabled,Enabled" newline bitfld.long 0x00 9. " DATA7PDR ,DMMDATA[7] open drain enable" "Disabled,Enabled" bitfld.long 0x00 8. " DATA6PDR ,DMMDATA[6] open drain enable" "Disabled,Enabled" bitfld.long 0x00 7. " DATA5PDR ,DMMDATA[5] open drain enable" "Disabled,Enabled" newline bitfld.long 0x00 6. " DATA4PDR ,DMMDATA[4] open drain enable" "Disabled,Enabled" bitfld.long 0x00 5. " DATA3PDR ,DMMDATA[3] open drain enable" "Disabled,Enabled" bitfld.long 0x00 4. " DATA2PDR ,DMMDATA[2] open drain enable" "Disabled,Enabled" newline bitfld.long 0x00 3. " DATA1PDR ,DMMDATA[1] open drain enable" "Disabled,Enabled" bitfld.long 0x00 2. " DATA0PDR ,DMMDATA[0] open drain enable" "Disabled,Enabled" bitfld.long 0x00 1. " CLKPDR ,DMMCLK open drain enable" "Disabled,Enabled" newline bitfld.long 0x00 0. " SYNCPDR ,DMMSYNC open drain enable" "Disabled,Enabled" line.long 0x04 "PC7,DMM Pin Control 7 (PDIS)" bitfld.long 0x04 18. " ENAPDIS ,DMMENA pull disable" "Enabled,Disabled" bitfld.long 0x04 17. " DATA15PDIS ,DMMDATA[15] pull disable" "Enabled,Disabled" bitfld.long 0x04 16. " DATA14PDIS ,DMMDATA[14] pull disable" "Enabled,Disabled" bitfld.long 0x04 15. " DATA13PDIS ,DMMDATA[13] pull disable" "Enabled,Disabled" newline bitfld.long 0x04 14. " DATA12PDIS ,DMMDATA[12] pull disable" "Enabled,Disabled" bitfld.long 0x04 13. " DATA11PDIS ,DMMDATA[11] pull disable" "Enabled,Disabled" bitfld.long 0x04 12. " DATA10PDIS ,DMMDATA[10] pull disable" "Enabled,Disabled" bitfld.long 0x04 11. " DATA9PDIS ,DMMDATA[9] pull disable" "Enabled,Disabled" newline bitfld.long 0x04 10. " DATA8PDIS ,DMMDATA[8] pull disable" "Enabled,Disabled" bitfld.long 0x04 9. " DATA7PDIS ,DMMDATA[7] pull disable" "Enabled,Disabled" bitfld.long 0x04 8. " DATA6PDIS ,DMMDATA[6] Pull disable" "Enabled,Disabled" bitfld.long 0x04 7. " DATA5PDIS ,DMMDATA[5] pull disable" "Enabled,Disabled" newline bitfld.long 0x04 6. " DATA4PDIS ,DMMDATA[4] pull disable" "Enabled,Disabled" bitfld.long 0x04 5. " DATA3PDIS ,DMMDATA[3] pull disable" "Enabled,Disabled" bitfld.long 0x04 4. " DATA2PDIS ,DMMDATA[2] Pull disable" "Enabled,Disabled" bitfld.long 0x04 3. " DATA1PDIS ,DMMDATA[1] pull disable" "Enabled,Disabled" newline bitfld.long 0x04 2. " DATA0PDIS ,DMMDATA[0] pull disable" "Enabled,Disabled" bitfld.long 0x04 1. " CLKPDIS ,DMMCLK pull disable" "Enabled,Disabled" bitfld.long 0x04 0. " SYNCPDIS ,DMMSYNC pull disable" "Enabled,Disabled" line.long 0x08 "PC8,DMM Pin Control 8 (PSEL)" bitfld.long 0x08 18. " ENAPSEL ,DMMENA pull select" "Pull down,Pull up" bitfld.long 0x08 17. " DATA15PSEL ,DMMDATA[15] pull select" "Pull down,Pull up" bitfld.long 0x08 16. " DATA14PSEL ,DMMDATA[14] pull select" "Pull down,Pull up" newline bitfld.long 0x08 15. " DATA13PSEL ,DMMDATA[13] pull select" "Pull down,Pull up" bitfld.long 0x08 14. " DATA12PSEL ,DMMDATA[12] pull select" "Pull down,Pull up" bitfld.long 0x08 13. " DATA11PSEL ,DMMDATA[11] pull select" "Pull down,Pull up" newline bitfld.long 0x08 12. " DATA10PSEL ,DMMDATA[10] pull select" "Pull down,Pull up" bitfld.long 0x08 11. " DATA9PSEL ,DMMDATA[9] pull select" "Pull down,Pull up" bitfld.long 0x08 10. " DATA8PSEL ,DMMDATA[8] pull select" "Pull down,Pull up" newline bitfld.long 0x08 9. " DATA7PSEL ,DMMDATA[7] pull select" "Pull down,Pull up" bitfld.long 0x08 8. " DATA6PSEL ,DMMDATA[6] pull select" "Pull down,Pull up" bitfld.long 0x08 7. " DATA5PSEL ,DMMDATA[5] pull select" "Pull down,Pull up" newline bitfld.long 0x08 6. " DATA4PSEL ,DMMDATA[4] pull select" "Pull down,Pull up" bitfld.long 0x08 5. " DATA3PSEL ,DMMDATA[3] pull select" "Pull down,Pull up" bitfld.long 0x08 4. " DATA2PSEL ,DMMDATA[2] pull select" "Pull down,Pull up" newline bitfld.long 0x08 3. " DATA1PSEL ,DMMDATA[1] pull select" "Pull down,Pull up" bitfld.long 0x08 2. " DATA0PSEL ,DMMDATA[0] pull select" "Pull down,Pull up" bitfld.long 0x08 1. " CLKPDSEL ,DMMCLK pull select" "Pull down,Pull up" newline bitfld.long 0x08 0. " SYNCPSEL ,DMMSYNC pull select" "Pull down,Pull up" width 0x0B tree.end tree "RTP (RAM Trace Port)" sif COMP.AVAILABLE("RTP") base CONVert.ADDRESSTODUALPORT(COMPonent.BASE("RTP",-1)) width 14. group.long 0x00++0x07 line.long 0x00 "RTPGLBCTRL,RTP Global Control Register" sif (cpu()=="TMS570LC4357"||cpu()=="RM57L843-ZWT"||cpu()=="TMS570PSFC61"||cpuis("TMS570LS20216*")||cpu()=="TMS570LS31XX"||cpu()=="TMS570LS21XX"||cpu()=="TMS570LS10XX"||cpu()=="M48L"||cpu()=="TMS570PSFC66") bitfld.long 0x00 24. " TEST ,FIFO RAM test enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 16.--18. " PRESCALER ,Rtpclk=1/prescaler" "/1,/2,/3,/4,/5,/6,/7,/8" bitfld.long 0x00 12.--13. " DDM_WIDTH[1:0] ,Word size in DDM" "8 bit,16 bit,32 bit,?..." bitfld.long 0x00 11. " DDM_RW ,Direct data mode read/write" "Read,Write" bitfld.long 0x00 10. " TM_DDM ,Trace mode or direct data mode" "Trace mode,Direct data mode" textline " " bitfld.long 0x00 8.--9. " PW[1:0] ,Port width" "2 pins,4 pins,8 pins,16 pins" bitfld.long 0x00 7. " RESET ,Reset of RTP module" "No reset,Reset" bitfld.long 0x00 6. " CONTCLK ,Continuous RTPCLK enable" "Disabled,Enabled" bitfld.long 0x00 5. " HOVF ,Halt on overflow" "Disabled,Enabled" textline " " sif (cpu()=="TMS570LC4357"||cpu()=="RM57L843-ZWT"||cpu()=="TMS570PSFC66") bitfld.long 0x00 4. " INV_RGN ,Invers trace regions" "Inside,Outside" else bitfld.long 0x00 4. " INVERSE ,Invers trace regions" "Inside,Outside" endif bitfld.long 0x00 0.--3. " ON/OFF ,RTP on or off" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Enabled,Disabled,Disabled,Disabled,Disabled,Disabled" line.long 0x04 "RTPTRENA,RTP Trace Enable Register" bitfld.long 0x04 24. " ENA4 ,FIFO4 enable" "Disabled,Enabled" sif (cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS20206-PGE")&&cpu()!=("TMS570LS20216-PGE")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS20206-ZWT")&&cpu()!=("TMS570LS20216-ZWT")&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE") bitfld.long 0x04 16. " ENA3 ,FIFO3 enable" "Disabled,Enabled" endif bitfld.long 0x04 8. " ENA2 ,FIFO2 enable" "Disabled,Enabled" bitfld.long 0x04 0. " ENA1 ,FIFO1 enable" "Disabled,Enabled" sif (cpu()=="TMS570LC4357"||cpu()=="RM57L843-ZWT") group.long 0x08++0x03 line.long 0x00 "RTPGSR,RTP Global Status Register" rbitfld.long 0x00 12. " EMPTYSER ,Serializer empty" "Not empty,Empty" rbitfld.long 0x00 11. " EMPTYPER2 ,Peripheral FIFO empty" "Not empty,Empty" rbitfld.long 0x00 10. " EMPTYPER1 ,Peripheral FIFO empty" "Not empty,Empty" rbitfld.long 0x00 9. " EMPTY2 ,FIFO2 empty" "Not empty,Empty" textline " " rbitfld.long 0x00 8. " EMPTY1 ,FIFO1 empty" "Not empty,Empty" eventfld.long 0x00 3. " OVFPER ,Overflow peripheral FIFO" "No overflow,Overflow" eventfld.long 0x00 1. " OVF2 ,Overflow FIFO2" "No overflow,Overflow" eventfld.long 0x00 0. " OVF1 ,Overflow FIFO1" "No overflow,Overflow" else rgroup.long 0x08++0x03 line.long 0x00 "RTPGSR,RTP Global Status Register" bitfld.long 0x00 12. " EMPTYSER ,Serializer empty" "Not empty,Empty" sif (cpu()=="TMS570PSFC66") sif (cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS20206-PGE")&&cpu()!=("TMS570LS20216-PGE")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS20206-ZWT")&&cpu()!=("TMS570LS20216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS20206-ZWT")&&cpu()!=("TMS570LS20216-ZWT")&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE") bitfld.long 0x00 10. " EMPTY3 ,FIFO 3 Empty" "Not empty,Empty" endif else bitfld.long 0x00 11. " EMPTYPER2 ,Peripheral FIFO empty" "Not empty,Empty" bitfld.long 0x00 10. " EMPTYPER1 ,Peripheral FIFO empty" "Not empty,Empty" endif bitfld.long 0x00 9. " EMPTY2 ,FIFO2 empty" "Not empty,Empty" bitfld.long 0x00 8. " EMPTY1 ,FIFO1 empty" "Not empty,Empty" textline " " bitfld.long 0x00 3. " OVFPER ,Overflow peripheral FIFO" "No overflow,Overflow" sif (cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS20206-PGE")&&cpu()!=("TMS570LS20216-PGE")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS20206-ZWT")&&cpu()!=("TMS570LS20216-ZWT")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS20206-ZWT")&&cpu()!=("TMS570LS20216-ZWT")&&cpu()!=("TMS570LS2126")&&cpu()!=("TMS570LS2127")&&cpu()!=("TMS570LS2136")&&cpu()!=("TMS570LS2137")&&cpu()!=("TMS570LS2125-PGE")&&cpu()!=("TMS570LS2125-ZWT")&&cpu()!=("TMS570LS2135-PGE")&&cpu()!=("TMS570LS2135-ZWT")&&cpu()!=("TMS570LS2124-PGE")&&cpu()!=("TMS570LS2124-ZWT")&&cpu()!=("TMS570LS2134-PGE")&&cpu()!=("TMS570LS2134-ZWT")&&cpu()!=("TMS570LS3134-PGE")&&cpu()!=("TMS570LS3134-ZWT")&&cpu()!=("TMS570LS3135-PGE")&&cpu()!=("TMS570LS3135-ZWT")&&cpu()!=("TMS570LS3136")&&cpu()!=("TMS570LS3137-ZWT")&&cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE") bitfld.long 0x00 2. " OVFPE3 ,Overflow FIFO3" "No overflow,Overflow" endif bitfld.long 0x00 1. " OVFPE2 ,Overflow FIFO2" "No overflow,Overflow" bitfld.long 0x00 0. " OVFPE1 ,Overflow FIFO1" "No overflow,Overflow" endif group.long 0x0C++0x23 line.long 0x00 "RTPRAM1REG1,RTP RAM 1 Trace Region 1 Register" bitfld.long 0x00 29.--30. " CPU_DMA ,CPU and/or DMA access" "Any,CPU,DMA,?..." bitfld.long 0x00 28. " RW ,Read/write" "Read,Write" bitfld.long 0x00 24.--27. " BLOCKSIZE ,Blocksize" "0,256 B,512 B,1k B,2k B,4k B,8k B,16k B,32k B,64k B,128k B,256k B,?..." hexmask.long.tbyte 0x00 0.--17. 1. " STARTADDR ,Start address" line.long 0x04 "RTPRAM1REG2,RTP RAM 1 Trace Region 2 Register" bitfld.long 0x04 29.--30. " CPU_DMA ,CPU and/or DMA access" "Any,CPU,DMA,?..." bitfld.long 0x04 28. " RW ,Read/write" "Read,Write" bitfld.long 0x04 24.--27. " BLOCKSIZE ,Blocksize" "0,256 B,512 B,1k B,2k B,4k B,8k B,16k B,32k B,64k B,128k B,256k B,?..." hexmask.long.tbyte 0x04 0.--17. 1. " STARTADDR ,Start address" line.long 0x08 "RTPRAM2REG1,RTP RAM 2 Trace Region 1 Register" bitfld.long 0x08 29.--30. " CPU_DMA ,CPU and/or DMA access" "Any,CPU,DMA,?..." bitfld.long 0x08 28. " RW ,Read/write" "Read,Write" bitfld.long 0x08 24.--27. " BLOCKSIZE ,Blocksize" "0,256 B,512 B,1k B,2k B,4k B,8k B,16k B,32k B,64k B,128k B,256k B,?..." hexmask.long.tbyte 0x08 0.--17. 1. " STARTADDR ,Start address" line.long 0x0C "RTPRAM2REG2,RTP RAM 2 Trace Region 2 Register" bitfld.long 0x0C 29.--30. " CPU_DMA ,CPU and/or DMA access" "Any,CPU,DMA,?..." bitfld.long 0x0C 28. " RW ,Read/write" "Read,Write" bitfld.long 0x0C 24.--27. " BLOCKSIZE ,Blocksize" "0,256 B,512 B,1k B,2k B,4k B,8k B,16k B,32k B,64k B,128k B,256k B,?..." hexmask.long.tbyte 0x0C 0.--17. 1. " STARTADDR ,Start address" sif (cpu()!=("TMS570LS10106-PGE")&&cpu()!=("TMS570LS10116-PGE")&&cpu()!=("TMS570LS10206-PGE")&&cpu()!=("TMS570LS10216-PGE")&&cpu()!=("TMS570LS20206-PGE")&&cpu()!=("TMS570LS20216-PGE")&&cpu()!=("TMS570LS10106-ZWT")&&cpu()!=("TMS570LS10116-ZWT")&&cpu()!=("TMS570LS10206-ZWT")&&cpu()!=("TMS570LS10216-ZWT")&&cpu()!=("TMS570LS20206-ZWT")&&cpu()!=("TMS570LS20216-ZWT")&&cpu()!="RM48L952-PGE"&&cpu()!="RM48L952-ZWT"&&cpu()!="RM48L950-PGE"&&cpu()!="RM48L950-ZWT"&&cpu()!="RM48L940-ZWT"&&cpu()!="RM48L940-PGE"&&cpu()!="RM48L930-ZWT"&&cpu()!="RM48L930-PGE"&&cpu()!="RM48L750-ZWT"&&cpu()!="RM48L750-PGE"&&cpu()!="RM48L740-ZWT"&&cpu()!="RM48L740-PGE"&&cpu()!="RM48L730-ZWT"&&cpu()!="RM48L730-PGE"&&cpu()!="RM48L550-PGE"&&cpu()!="RM48L540-ZWT"&&cpu()!="RM48L540-PGE"&&cpu()!="RM48L530-ZWT"&&cpu()!="RM48L530-PGE") line.long 0x10 "RTPRAM3REG1,RTP RAM 3 Trace Region 1 Register" bitfld.long 0x10 29.--30. " CPU_DMA ,CPU and/or DMA access" "Any,CPU,DMA,?..." bitfld.long 0x10 28. " RW ,Read/write" "Read,Write" bitfld.long 0x10 24.--27. " BLOCKSIZE ,Blocksize" "0,256 B,512 B,1k B,2k B,4k B,8k B,16k B,32k B,64k B,128k B,256k B,?..." hexmask.long.tbyte 0x10 0.--17. 1. " STARTADDR ,Start address" line.long 0x14 "RTPRAM3REG2,RTP RAM 3 Trace Region 2 Register" bitfld.long 0x14 29.--30. " CPU_DMA ,CPU and/or DMA access" "Any,CPU,DMA,?..." bitfld.long 0x14 28. " RW ,Read/write" "Read,Write" bitfld.long 0x14 24.--27. " BLOCKSIZE ,Blocksize" "0,256 B,512 B,1k B,2k B,4k B,8k B,16k B,32k B,64k B,128k B,256k B,?..." hexmask.long.tbyte 0x14 0.--17. 1. " STARTADDR ,Start address" endif line.long 0x18 "RTPPERREG1,RTP Peripheral Trace Region 1 Register" bitfld.long 0x18 29.--30. " CPU_DMA ,CPU and/or DMA access" "Any,CPU,DMA,?..." bitfld.long 0x18 28. " RW ,Read/write" "Read,Write" sif (cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10206-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS20206-PGE")||cpu()==("TMS570LS20216-PGE")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS20206-ZWT")||cpu()==("TMS570LS20216-ZWT")||cpu()=="RM48L952-PGE"||cpu()=="RM48L952-ZWT"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L540-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE") bitfld.long 0x00 24.--27. " BLOCKSIZE ,Trace Region Length" "0 kB,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." else bitfld.long 0x18 24.--27. " BLOCKSIZE ,Blocksize" "0,256 B,512 B,1k B,2k B,4k B,8k B,16k B,32k B,64k B,128k B,256k B,?..." endif hexmask.long.tbyte 0x18 0.--23. 1. " STARTADDR ,Start address" line.long 0x1C "RTPPERREG2,RTP Peripheral Trace Region 2 Register" bitfld.long 0x1C 29.--30. " CPU_DMA ,CPU and/or DMA access" "Any,CPU,DMA,?..." bitfld.long 0x1C 28. " RW ,Read/write" "Read,Write" sif (cpu()==("TMS570LS10106-PGE")||cpu()==("TMS570LS10116-PGE")||cpu()==("TMS570LS10206-PGE")||cpu()==("TMS570LS10216-PGE")||cpu()==("TMS570LS20206-PGE")||cpu()==("TMS570LS20216-PGE")||cpu()==("TMS570LS10106-ZWT")||cpu()==("TMS570LS10116-ZWT")||cpu()==("TMS570LS10206-ZWT")||cpu()==("TMS570LS10216-ZWT")||cpu()==("TMS570LS20206-ZWT")||cpu()==("TMS570LS20216-ZWT")||cpu()=="RM48L952-PGE"||cpu()=="RM48L952-ZWT"||cpu()=="RM48L950-PGE"||cpu()=="RM48L950-ZWT"||cpu()=="RM48L940-ZWT"||cpu()=="RM48L940-PGE"||cpu()=="RM48L930-ZWT"||cpu()=="RM48L930-PGE"||cpu()=="RM48L750-ZWT"||cpu()=="RM48L750-PGE"||cpu()=="RM48L740-ZWT"||cpu()=="RM48L740-PGE"||cpu()=="RM48L730-ZWT"||cpu()=="RM48L730-PGE"||cpu()=="RM48L550-PGE"||cpu()=="RM48L540-ZWT"||cpu()=="RM48L540-PGE"||cpu()=="RM48L530-ZWT"||cpu()=="RM48L530-PGE") bitfld.long 0x00 24.--27. " BLOCKSIZE ,Trace Region Length" "0 kB,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,?..." else bitfld.long 0x1C 24.--27. " BLOCKSIZE ,Blocksize" "0,256 B,512 B,1k B,2k B,4k B,8k B,16k B,32k B,64k B,128k B,256k B,?..." endif hexmask.long.tbyte 0x1C 0.--23. 1. " STARTADDR ,Start address" line.long 0x20 "RTPDDMW,RTP Direct Data Mode Write Register" group.long 0x34++0x07 line.long 0x00 "RTPPC0,RTP Pin Control 0" bitfld.long 0x00 18. " ENAFUNC ,Functional mode of RTPENA pin" "GIO mode,Functional mode" bitfld.long 0x00 17. " CLKFUNC ,Functional mode of RTPCLK pin" "GIO mode,Functional mode" bitfld.long 0x00 16. " SYNCFUNC ,Functional mode of RTPSYNC pin" "GIO mode,Functional mode" textline " " bitfld.long 0x00 15. " DATAFUNC ,Output state of RTPDATA pin 15" "GIO,Functional" bitfld.long 0x00 14. " DATAFUNC ,Output state of RTPDATA pin 14" "GIO,Functional" bitfld.long 0x00 13. " DATAFUNC ,Output state of RTPDATA pin 13" "GIO,Functional" textline " " bitfld.long 0x00 12. " DATAFUNC ,Output state of RTPDATA pin 12" "GIO,Functional" bitfld.long 0x00 11. " DATAFUNC ,Output state of RTPDATA pin 11" "GIO,Functional" bitfld.long 0x00 10. " DATAFUNC ,Output state of RTPDATA pin 10" "GIO,Functional" textline " " bitfld.long 0x00 9. " DATAFUNC ,Output state of RTPDATA pin 9" "GIO,Functional" bitfld.long 0x00 8. " DATAFUNC ,Output state of RTPDATA pin 8" "GIO,Functional" bitfld.long 0x00 7. " DATAFUNC ,Output state of RTPDATA pin 7" "GIO,Functional" textline " " bitfld.long 0x00 6. " DATAFUNC ,Output state of RTPDATA pin 6" "GIO,Functional" bitfld.long 0x00 5. " DATAFUNC ,Output state of RTPDATA pin 5" "GIO,Functional" bitfld.long 0x00 4. " DATAFUNC ,Output state of RTPDATA pin 4" "GIO,Functional" textline " " bitfld.long 0x00 3. " DATAFUNC ,Output state of RTPDATA pin 3" "GIO,Functional" bitfld.long 0x00 2. " DATAFUNC ,Output state of RTPDATA pin 2" "GIO,Functional" bitfld.long 0x00 1. " DATAFUNC ,Output state of RTPDATA pin 1" "GIO,Functional" textline " " bitfld.long 0x00 0. " DATAFUNC ,Output state of RTPDATA pin 0" "GIO,Functional" line.long 0x04 "RTPPC1,RTP Pin Control 1" bitfld.long 0x04 18. " ENADIR ,Direction of RTPENA pin" "Input,Output" bitfld.long 0x04 17. " CLKDIR ,Direction of RTPCLK pin" "Input,Output" bitfld.long 0x04 16. " SYNCDIR ,Direction of RTPSYNC pin" "Input,Output" textline " " bitfld.long 0x04 15. " DATADIR ,Output state of RTPDATA pin 15" "Input,Output" bitfld.long 0x04 14. " DATADIR ,Output state of RTPDATA pin 14" "Input,Output" bitfld.long 0x04 13. " DATADIR ,Output state of RTPDATA pin 13" "Input,Output" textline " " bitfld.long 0x04 12. " DATADIR ,Output state of RTPDATA pin 12" "Input,Output" bitfld.long 0x04 11. " DATADIR ,Output state of RTPDATA pin 11" "Input,Output" bitfld.long 0x04 10. " DATADIR ,Output state of RTPDATA pin 10" "Input,Output" textline " " bitfld.long 0x04 9. " DATADIR ,Output state of RTPDATA pin 9" "Input,Output" bitfld.long 0x04 8. " DATADIR ,Output state of RTPDATA pin 8" "Input,Output" bitfld.long 0x04 7. " DATADIR ,Output state of RTPDATA pin 7" "Input,Output" textline " " bitfld.long 0x04 6. " DATADIR ,Output state of RTPDATA pin 6" "Input,Output" bitfld.long 0x04 5. " DATADIR ,Output state of RTPDATA pin 5" "Input,Output" bitfld.long 0x04 4. " DATADIR ,Output state of RTPDATA pin 4" "Input,Output" textline " " bitfld.long 0x04 3. " DATADIR ,Output state of RTPDATA pin 3" "Input,Output" bitfld.long 0x04 2. " DATADIR ,Output state of RTPDATA pin 2" "Input,Output" bitfld.long 0x04 1. " DATADIR ,Output state of RTPDATA pin 1" "Input,Output" textline " " bitfld.long 0x04 0. " DATADIR ,Output state of RTPDATA pin 0" "Input,Output" rgroup.long 0x3C++0x03 line.long 0x00 "RTPPC2,RTP Pin Control 2" bitfld.long 0x00 18. " ENAIN ,State of RTPENA pin" "Low,High" bitfld.long 0x00 17. " CLKIN ,State of RTPCLK pin" "Low,High" bitfld.long 0x00 16. " SYNCIN ,State of RTPSYNC pin" "Low,High" textline " " bitfld.long 0x00 15. " DATAIN ,Output state of RTPDATA pin 15" "Low,High" bitfld.long 0x00 14. " DATAIN ,Output state of RTPDATA pin 14" "Low,High" bitfld.long 0x00 13. " DATAIN ,Output state of RTPDATA pin 13" "Low,High" textline " " bitfld.long 0x00 12. " DATAIN ,Output state of RTPDATA pin 12" "Low,High" bitfld.long 0x00 11. " DATAIN ,Output state of RTPDATA pin 11" "Low,High" bitfld.long 0x00 10. " DATAIN ,Output state of RTPDATA pin 10" "Low,High" textline " " bitfld.long 0x00 9. " DATAIN ,Output state of RTPDATA pin 9" "Low,High" bitfld.long 0x00 8. " DATAIN ,Output state of RTPDATA pin 8" "Low,High" bitfld.long 0x00 7. " DATAIN ,Output state of RTPDATA pin 7" "Low,High" textline " " bitfld.long 0x00 6. " DATAIN ,Output state of RTPDATA pin 6" "Low,High" bitfld.long 0x00 5. " DATAIN ,Output state of RTPDATA pin 5" "Low,High" bitfld.long 0x00 4. " DATAIN ,Output state of RTPDATA pin 4" "Low,High" textline " " bitfld.long 0x00 3. " DATAIN ,Output state of RTPDATA pin 3" "Low,High" bitfld.long 0x00 2. " DATAIN ,Output state of RTPDATA pin 2" "Low,High" bitfld.long 0x00 1. " DATAIN ,Output state of RTPDATA pin 1" "Low,High" textline " " bitfld.long 0x00 0. " DATAIN ,Output state of RTPDATA pin 0" "Low,High" group.long 0x40++0x17 line.long 0x00 "RTPPC3,RTP Pin Control 3" bitfld.long 0x00 18. " ENAOUT ,Output state of RTPENA pin" "Low,High" bitfld.long 0x00 17. " CLKOUT ,Output state of RTPCLK pin" "Low,High" sif (cpu()=="TMS570LC4357"||cpu()=="RM57L843-ZWT"||cpu()=="TMS570PSFC66") bitfld.long 0x00 16. " SYNCOUT ,Output state of RTPSYNC pins" "Low,High" else bitfld.long 0x00 16. " DATAOUT ,Output state of RTPDATA pins" "Low,High" endif textline " " bitfld.long 0x00 15. " DATAOUT ,Output state of RTPDATA pin 15" "Push/pull,Open drain" bitfld.long 0x00 14. " DATAOUT ,Output state of RTPDATA pin 14" "Push/pull,Open drain" bitfld.long 0x00 13. " DATAOUT ,Output state of RTPDATA pin 13" "Push/pull,Open drain" textline " " bitfld.long 0x00 12. " DATAOUT ,Output state of RTPDATA pin 12" "Push/pull,Open drain" bitfld.long 0x00 11. " DATAOUT ,Output state of RTPDATA pin 11" "Push/pull,Open drain" bitfld.long 0x00 10. " DATAOUT ,Output state of RTPDATA pin 10" "Push/pull,Open drain" textline " " bitfld.long 0x00 9. " DATAOUT ,Output state of RTPDATA pin 9" "Push/pull,Open drain" bitfld.long 0x00 8. " DATAOUT ,Output state of RTPDATA pin 8" "Push/pull,Open drain" bitfld.long 0x00 7. " DATAOUT ,Output state of RTPDATA pin 7" "Push/pull,Open drain" textline " " bitfld.long 0x00 6. " DATAOUT ,Output state of RTPDATA pin 6" "Push/pull,Open drain" bitfld.long 0x00 5. " DATAOUT ,Output state of RTPDATA pin 5" "Push/pull,Open drain" bitfld.long 0x00 4. " DATAOUT ,Output state of RTPDATA pin 4" "Push/pull,Open drain" textline " " bitfld.long 0x00 3. " DATAOUT ,Output state of RTPDATA pin 3" "Push/pull,Open drain" bitfld.long 0x00 2. " DATAOUT ,Output state of RTPDATA pin 2" "Push/pull,Open drain" bitfld.long 0x00 1. " DATAOUT ,Output state of RTPDATA pin 1" "Push/pull,Open drain" textline " " bitfld.long 0x00 0. " DATAOUT ,Output state of RTPDATA pin 0" "Push/pull,Open drain" line.long 0x04 "RTPPC4,RTP Pin Control 4" bitfld.long 0x04 18. " ENASET ,Set output state of RTPENA pin to logic high" "No change,Set high" bitfld.long 0x04 17. " CLKSET ,Set output state of RTPCLK pin to logic high" "No change,Set high" bitfld.long 0x04 16. " SYNCSET ,Set output state of RTPSYNC pin to logic high" "No change,Set high" textline " " bitfld.long 0x04 15. " DATASET ,Output state of RTPDATA pin 15" "Low,High" bitfld.long 0x04 14. " DATASET ,Output state of RTPDATA pin 14" "Low,High" bitfld.long 0x04 13. " DATASET ,Output state of RTPDATA pin 13" "Low,High" textline " " bitfld.long 0x04 12. " DATASET ,Output state of RTPDATA pin 12" "Low,High" bitfld.long 0x04 11. " DATASET ,Output state of RTPDATA pin 11" "Low,High" bitfld.long 0x04 10. " DATASET ,Output state of RTPDATA pin 10" "Low,High" textline " " bitfld.long 0x04 9. " DATASET ,Output state of RTPDATA pin 9" "Low,High" bitfld.long 0x04 8. " DATASET ,Output state of RTPDATA pin 8" "Low,High" bitfld.long 0x04 7. " DATASET ,Output state of RTPDATA pin 7" "Low,High" textline " " bitfld.long 0x04 6. " DATASET ,Output state of RTPDATA pin 6" "Low,High" bitfld.long 0x04 5. " DATASET ,Output state of RTPDATA pin 5" "Low,High" bitfld.long 0x04 4. " DATASET ,Output state of RTPDATA pin 4" "Low,High" textline " " bitfld.long 0x04 3. " DATASET ,Output state of RTPDATA pin 3" "Low,High" bitfld.long 0x04 2. " DATASET ,Output state of RTPDATA pin 2" "Low,High" bitfld.long 0x04 1. " DATASET ,Output state of RTPDATA pin 1" "Low,High" textline " " bitfld.long 0x04 0. " DATASET ,Output state of RTPDATA pin 0" "Low,High" line.long 0x08 "RTPPC5,RTP Pin Control 5" bitfld.long 0x08 18. " ENACLR ,Set output state of RTPENA pin to logic low" "No change,Set low" bitfld.long 0x08 17. " CLKCLR ,Set output state of RTPCLK pin to logic low" "No change,Set low" bitfld.long 0x08 16. " SYNCCLR ,Set output state of RTPSYNC pin to logic low" "No change,Set low" textline " " bitfld.long 0x08 15. " DATACLR ,Output state of RTPDATA pin 15" "Low,High" bitfld.long 0x08 14. " DATACLR ,Output state of RTPDATA pin 14" "Low,High" bitfld.long 0x08 13. " DATACLR ,Output state of RTPDATA pin 13" "Low,High" textline " " bitfld.long 0x08 12. " DATACLR ,Output state of RTPDATA pin 12" "Low,High" bitfld.long 0x08 11. " DATACLR ,Output state of RTPDATA pin 11" "Low,High" bitfld.long 0x08 10. " DATACLR ,Output state of RTPDATA pin 10" "Low,High" textline " " bitfld.long 0x08 9. " DATACLR ,Output state of RTPDATA pin 9" "Low,High" bitfld.long 0x08 8. " DATACLR ,Output state of RTPDATA pin 8" "Low,High" bitfld.long 0x08 7. " DATACLR ,Output state of RTPDATA pin 7" "Low,High" textline " " bitfld.long 0x08 6. " DATACLR ,Output state of RTPDATA pin 6" "Low,High" bitfld.long 0x08 5. " DATACLR ,Output state of RTPDATA pin 5" "Low,High" bitfld.long 0x08 4. " DATACLR ,Output state of RTPDATA pin 4" "Low,High" textline " " bitfld.long 0x08 3. " DATACLR ,Output state of RTPDATA pin 3" "Low,High" bitfld.long 0x08 2. " DATACLR ,Output state of RTPDATA pin 2" "Low,High" bitfld.long 0x08 1. " DATACLR ,Output state of RTPDATA pin 1" "Low,High" textline " " bitfld.long 0x08 0. " DATACLR ,Output state of RTPDATA pin 0" "Low,High" line.long 0x0C "RTPPC6,RTP Pin Control 6" bitfld.long 0x0C 18. " ENAPDR ,Open drain enable of RTPENA pin" "Normal mode,Open drain" bitfld.long 0x0C 17. " CLKPDR ,Open drain enable of RTPCLK pin" "Normal mode,Open drain" bitfld.long 0x0C 16. " SYNCPDR ,Open drain enable of RTPSYNC pin" "Normal mode,Open drain" textline " " bitfld.long 0x0C 15. " DATAPDR ,Output state of RTPDATA pin 15" "Push/pull,Open drain" bitfld.long 0x0C 14. " DATAPDR ,Output state of RTPDATA pin 14" "Push/pull,Open drain" bitfld.long 0x0C 13. " DATAPDR ,Output state of RTPDATA pin 13" "Push/pull,Open drain" textline " " bitfld.long 0x0C 12. " DATAPDR ,Output state of RTPDATA pin 12" "Push/pull,Open drain" bitfld.long 0x0C 11. " DATAPDR ,Output state of RTPDATA pin 11" "Push/pull,Open drain" bitfld.long 0x0C 10. " DATAPDR ,Output state of RTPDATA pin 10" "Push/pull,Open drain" textline " " bitfld.long 0x0C 9. " DATAPDR ,Output state of RTPDATA pin 9" "Push/pull,Open drain" bitfld.long 0x0C 8. " DATAPDR ,Output state of RTPDATA pin 8" "Push/pull,Open drain" bitfld.long 0x0C 7. " DATAPDR ,Output state of RTPDATA pin 7" "Push/pull,Open drain" textline " " bitfld.long 0x0C 6. " DATAPDR ,Output state of RTPDATA pin 6" "Push/pull,Open drain" bitfld.long 0x0C 5. " DATAPDR ,Output state of RTPDATA pin 5" "Push/pull,Open drain" bitfld.long 0x0C 4. " DATAPDR ,Output state of RTPDATA pin 4" "Push/pull,Open drain" textline " " bitfld.long 0x0C 3. " DATAPDR ,Output state of RTPDATA pin 3" "Push/pull,Open drain" bitfld.long 0x0C 2. " DATAPDR ,Output state of RTPDATA pin 2" "Push/pull,Open drain" bitfld.long 0x0C 1. " DATAPDR ,Output state of RTPDATA pin 1" "Push/pull,Open drain" textline " " bitfld.long 0x0C 0. " DATAPDR ,Output state of RTPDATA pin 0" "Push/pull,Open drain" line.long 0x10 "RTPPC7,RTP Pin Control 7" sif (cpu()=="TMS570LC4357"||cpu()=="RM57L843-ZWT") bitfld.long 0x10 18. " ENADIS ,Pull-up/pull-down functionality of RTPENA pin disabled" "No,Yes" bitfld.long 0x10 17. " CLKDIS ,Pull-up/pull-down functionality of RTPCLK pin disabled" "No,Yes" bitfld.long 0x10 16. " SYNCDIS ,Pull-up/pull-down functionality of RTPSYNC pin disabled" "No,Yes" else bitfld.long 0x10 18. " ENAPDIS ,Pull-up/pull-down functionality of RTPENA pin disabled" "No,Yes" bitfld.long 0x10 17. " CLKPDIS ,Pull-up/pull-down functionality of RTPCLK pin disabled" "No,Yes" bitfld.long 0x10 16. " SYNCPDIS ,Pull-up/pull-down functionality of RTPSYNC pin disabled" "No,Yes" endif textline " " bitfld.long 0x10 15. " DATADIS ,Output state of RTPDATA pin 15" "Enabled,Disabled" bitfld.long 0x10 14. " DATADIS ,Output state of RTPDATA pin 14" "Enabled,Disabled" bitfld.long 0x10 13. " DATADIS ,Output state of RTPDATA pin 13" "Enabled,Disabled" textline " " bitfld.long 0x10 12. " DATADIS ,Output state of RTPDATA pin 12" "Enabled,Disabled" bitfld.long 0x10 11. " DATADIS ,Output state of RTPDATA pin 11" "Enabled,Disabled" bitfld.long 0x10 10. " DATADIS ,Output state of RTPDATA pin 10" "Enabled,Disabled" textline " " bitfld.long 0x10 9. " DATADIS ,Output state of RTPDATA pin 9" "Enabled,Disabled" bitfld.long 0x10 8. " DATADIS ,Output state of RTPDATA pin 8" "Enabled,Disabled" bitfld.long 0x10 7. " DATADIS ,Output state of RTPDATA pin 7" "Enabled,Disabled" textline " " bitfld.long 0x10 6. " DATADIS ,Output state of RTPDATA pin 6" "Enabled,Disabled" bitfld.long 0x10 5. " DATADIS ,Output state of RTPDATA pin 5" "Enabled,Disabled" bitfld.long 0x10 4. " DATADIS ,Output state of RTPDATA pin 4" "Enabled,Disabled" textline " " bitfld.long 0x10 3. " DATADIS ,Output state of RTPDATA pin 3" "Enabled,Disabled" bitfld.long 0x10 2. " DATADIS ,Output state of RTPDATA pin 2" "Enabled,Disabled" bitfld.long 0x10 1. " DATADIS ,Output state of RTPDATA pin 1" "Enabled,Disabled" textline " " bitfld.long 0x10 0. " DATADIS ,Output state of RTPDATA pin 0" "Enabled,Disabled" line.long 0x14 "RTPPC8,RTP Pin Control 8" bitfld.long 0x14 18. " ENAPSEL ,Pull select of RTPENA pin" "Pull-down,Pull-up" bitfld.long 0x14 17. " CLKPSEL ,Pull select of RTPCLK pin" "Pull-down,Pull-up" bitfld.long 0x14 16. " SYNCPSEL ,Pull select of RTPSYNC pin" "Pull-down,Pull-up" textline " " bitfld.long 0x14 15. " DATAPSEL ,Output state of RTPDATA pin 15" "Pull-down,Pull-up" bitfld.long 0x14 14. " DATAPSEL ,Output state of RTPDATA pin 14" "Pull-down,Pull-up" bitfld.long 0x14 13. " DATAPSEL ,Output state of RTPDATA pin 13" "Pull-down,Pull-up" textline " " bitfld.long 0x14 12. " DATAPSEL ,Output state of RTPDATA pin 12" "Pull-down,Pull-up" bitfld.long 0x14 11. " DATAPSEL ,Output state of RTPDATA pin 11" "Pull-down,Pull-up" bitfld.long 0x14 10. " DATAPSEL ,Output state of RTPDATA pin 10" "Pull-down,Pull-up" textline " " bitfld.long 0x14 9. " DATAPSEL ,Output state of RTPDATA pin 9" "Pull-down,Pull-up" bitfld.long 0x14 8. " DATAPSEL ,Output state of RTPDATA pin 8" "Pull-down,Pull-up" bitfld.long 0x14 7. " DATAPSEL ,Output state of RTPDATA pin 7" "Pull-down,Pull-up" textline " " bitfld.long 0x14 6. " DATAPSEL ,Output state of RTPDATA pin 6" "Pull-down,Pull-up" bitfld.long 0x14 5. " DATAPSEL ,Output state of RTPDATA pin 5" "Pull-down,Pull-up" bitfld.long 0x14 4. " DATAPSEL ,Output state of RTPDATA pin 4" "Pull-down,Pull-up" textline " " bitfld.long 0x14 3. " DATAPSEL ,Output state of RTPDATA pin 3" "Pull-down,Pull-up" bitfld.long 0x14 2. " DATAPSEL ,Output state of RTPDATA pin 2" "Pull-down,Pull-up" bitfld.long 0x14 1. " DATAPSEL ,Output state of RTPDATA pin 1" "Pull-down,Pull-up" textline " " bitfld.long 0x14 0. " DATAPSEL ,Output state of RTPDATA pin 0" "Pull-down,Pull-up" sif (cpu()!="TMS570LC4357"&&cpu()!="RM57L843-ZWT") group.long 0x58++0x03 line.long 0x00 "RTPIODFTCTRL,RTP IODFT Control" hexmask.long.byte 0x00 8.--11. 1. " IODFTENA ,IO DFT enable" bitfld.long 0x00 1. " LBENA ,Loop back enable" "Analog,Digital" endif endif width 0x0B tree.end endif textline ""