; -------------------------------------------------------------------------------- ; @Title: RA4W1 On-Chip Peripherals ; @Props: Released ; @Author: KWI, ADR, JDU, NEJ ; @Changelog: 2021-02-11 KWI ; 2022-01-28 ADR ; 2023-03-13 JDU ; 2023-11-15 NEJ ; @Manufacturer: RENESAS - Renesas Technology, Corp. ; @Doc: Generated (TRACE32, build: 164623.), based on: ; R7FA4W1AD.svd (Ver. 1.0) ; @Core: Cortex-M4F ; @Chip: R7FA4W1AD2CNG ; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: perra4w1.per 17054 2023-11-22 13:00:48Z kwisniewski $ AUTOINDENT.ON CENTER TREE ENUMDELIMITER "," base ad:0x0 tree.close "Core Registers (Cortex-M4F)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. group.long 0x08++0x03 line.long 0x00 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes" bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes" bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes" textline " " bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes" bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes" group.long 0x10++0x0B line.long 0x00 "SYST_CSR,SysTick Control and Status Register" rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted" bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core" bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick" textline " " bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled" line.long 0x04 "SYST_RVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0" line.long 0x08 "SYST_CVR,SysTick Current Value Register" rgroup.long 0x1C++0x03 line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing" rgroup.long 0xD00++0x03 line.long 0x00 "CPUID,CPU ID Base Register" hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code" bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..." bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number" bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xD04++0x23 line.long 0x00 "ICSR,Interrupt Control State Register" bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active" bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending" bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed" textline " " bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending" bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed" bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active" textline " " bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending" hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field" bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active" textline " " hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception" line.long 0x04 "VTOR,Vector Table Offset Register" hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address" line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key" rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big" bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]" textline " " bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested" bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear" bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset" line.long 0x0C "SCR,System Control Register" bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" line.long 0x10 "CCR,Configuration Control Register" bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled" bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled" bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled" textline " " bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment" bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled" bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled" textline " " bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled" bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed" bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level" line.long 0x14 "SHPR1,SSystem Handler Priority Register 1" hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7" hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)" hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)" textline " " hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)" line.long 0x18 "SHPR2,System Handler Priority Register 2" hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)" hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10" hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9" textline " " hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8" line.long 0x1C "SHPR3,System Handler Priority Register 3" hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)" hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)" hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13" textline " " hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)" line.long 0x20 "SHCSR,System Handler Control and State Register" bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled" bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled" bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled" textline " " bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending" bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending" bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending" textline " " bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending" bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active" bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active" textline " " bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active" bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active" bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active" textline " " bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active" bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active" group.byte 0xD28++0x1 line.byte 0x00 "MMFSR,MemManage Status Register" bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred" textline " " bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred" bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred" bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred" line.byte 0x01 "BFSR,Bus Fault Status Register" bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid" bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred" bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred" textline " " bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred" bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred" bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred" textline " " bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred" group.word 0xD2A++0x1 line.word 0x00 "USAFAULT,Usage Fault Status Register" bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error" bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error" bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error" textline " " bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error" bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error" bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error" group.long 0xD2C++0x07 line.long 0x00 "HFSR,Hard Fault Status Register" bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred" bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred" bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred" line.long 0x04 "DFSR,Debug Fault Status Register" bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted" bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred" bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred" textline " " bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed" bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested" group.long 0xD34++0x0B line.long 0x00 "MMFAR,MemManage Fault Address Register" line.long 0x04 "BFAR,BusFault Address Register" line.long 0x08 "AFSR,Auxiliary Fault Status Register" group.long 0xD88++0x03 line.long 0x00 "CPACR,Coprocessor Access Control Register" bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access" bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access" textline " " bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access" wgroup.long 0xF00++0x03 line.long 0x00 "STIR,Software Trigger Interrupt Register" hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered" width 10. tree "Feature Registers" rgroup.long 0xD40++0x0B line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..." bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..." line.long 0x04 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..." line.long 0x08 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..." hgroup.long 0xD4C++0x03 hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long 0xD50++0x03 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..." bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..." bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..." textline " " bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored" bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..." hgroup.long 0xD54++0x03 hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" rgroup.long 0xD58++0x03 line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..." rgroup.long 0xD60++0x13 line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0" bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..." bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..." bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..." textline " " bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..." bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..." bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..." line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1" bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..." bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..." bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..." textline " " bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..." line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2" bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..." bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..." bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..." textline " " bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..." bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..." bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..." textline " " bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..." line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3" bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..." bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..." bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..." textline " " bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..." bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..." textline " " bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..." line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4" bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..." bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..." bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..." textline " " bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..." bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..." bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..." tree.end width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0C "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0C "CID3,Component ID3" tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Memory Protection Unit" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 15. rgroup.long 0xD90++0x03 line.long 0x00 "MPU_TYPE,MPU Type Register" bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported" group.long 0xD94++0x03 line.long 0x00 "MPU_CTRL,MPU Control Register" bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled" bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled" bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled" group.long 0xD98++0x03 line.long 0x00 "MPU_RNR,MPU Region Number Register" hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR" tree.close "MPU regions" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0 group.long 0xD9C++0x03 "Region 0" saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 0 (not implemented)" saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1 group.long 0xD9C++0x03 "Region 1" saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 1 (not implemented)" saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2 group.long 0xD9C++0x03 "Region 2" saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 2 (not implemented)" saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3 group.long 0xD9C++0x03 "Region 3" saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 3 (not implemented)" saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4 group.long 0xD9C++0x03 "Region 4" saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 4 (not implemented)" saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5 group.long 0xD9C++0x03 "Region 5" saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 5 (not implemented)" saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6 group.long 0xD9C++0x03 "Region 6" saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 6 (not implemented)" saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7 group.long 0xD9C++0x03 "Region 7" saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 7 (not implemented)" saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8 group.long 0xD9C++0x03 "Region 8" saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x8 line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 8 (not implemented)" saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x8 hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9 group.long 0xD9C++0x03 "Region 9" saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x9 line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 9 (not implemented)" saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x9 hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA group.long 0xD9C++0x03 "Region 10" saveout 0xD98 %l 0xA line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xA line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 10 (not implemented)" saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xA hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB group.long 0xD9C++0x03 "Region 11" saveout 0xD98 %l 0xB line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xB line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 11 (not implemented)" saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xB hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC group.long 0xD9C++0x03 "Region 12" saveout 0xD98 %l 0xC line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xC line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 12 (not implemented)" saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xC hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD group.long 0xD9C++0x03 "Region 13" saveout 0xD98 %l 0xD line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xD line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 13 (not implemented)" saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xD hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE group.long 0xD9C++0x03 "Region 14" saveout 0xD98 %l 0xE line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xE line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 14 (not implemented)" saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xE hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF group.long 0xD9C++0x03 "Region 15" saveout 0xD98 %l 0xF line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0xF line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 15 (not implemented)" saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0xF hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15" textline " " textline " " endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 6. rgroup.long 0x04++0x03 line.long 0x00 "ICTR,Interrupt Controller Type Register" bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..." tree "Interrupt Enable Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x100++0x03 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x100++0x7 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x100++0x0B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x100++0x0F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x100++0x13 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x100++0x17 line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x100++0x1B line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x100++0x1F line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" else hgroup.long 0x100++0x1F hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register" hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register" hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register" hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register" hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register" hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register" hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register" hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register" endif tree.end tree "Interrupt Pending Registers" width 23. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x200++0x03 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x200++0x07 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x200++0x0B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x200++0x0F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x200++0x13 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x200++0x17 line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x200++0x1B line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x200++0x1F line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending" line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending" else hgroup.long 0x200++0x1F hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register" hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register" endif tree.end tree "Interrupt Active Bit Registers" width 9. if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) rgroup.long 0x300++0x03 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) rgroup.long 0x300++0x07 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) rgroup.long 0x300++0x0B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) rgroup.long 0x300++0x0F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) rgroup.long 0x300++0x13 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) rgroup.long 0x300++0x17 line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) rgroup.long 0x300++0x1B line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) rgroup.long 0x300++0x1F line.long 0x00 "ACTIVE1,Active Bit Register 1" bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active" line.long 0x04 "ACTIVE2,Active Bit Register 2" bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active" line.long 0x08 "ACTIVE3,Active Bit Register 3" bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active" line.long 0x0c "ACTIVE4,Active Bit Register 4" bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active" line.long 0x10 "ACTIVE5,Active Bit Register 5" bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active" line.long 0x14 "ACTIVE6,Active Bit Register 6" bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active" line.long 0x18 "ACTIVE7,Active Bit Register 7" bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active" line.long 0x1c "ACTIVE8,Active Bit Register 8" bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active" textline " " bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active" bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active" else hgroup.long 0x300++0x1F hide.long 0x00 "ACTIVE1,Active Bit Register 1" hide.long 0x04 "ACTIVE2,Active Bit Register 2" hide.long 0x08 "ACTIVE3,Active Bit Register 3" hide.long 0x0c "ACTIVE4,Active Bit Register 4" hide.long 0x10 "ACTIVE5,Active Bit Register 5" hide.long 0x14 "ACTIVE6,Active Bit Register 6" hide.long 0x18 "ACTIVE7,Active Bit Register 7" hide.long 0x1c "ACTIVE8,Active Bit Register 8" endif tree.end tree "Interrupt Priority Registers" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00) group.long 0x400++0x1F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01) group.long 0x400++0x3F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02) group.long 0x400++0x5F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03) group.long 0x400++0x7F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04) group.long 0x400++0x9F line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05) group.long 0x400++0xBF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06) group.long 0x400++0xDF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07) group.long 0x400++0xEF line.long 0x0 "IPR0,Interrupt Priority Register" hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority" hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority" hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority" hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority" line.long 0x4 "IPR1,Interrupt Priority Register" hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority" hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority" hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority" hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority" line.long 0x8 "IPR2,Interrupt Priority Register" hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority" hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority" hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority" hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority" line.long 0xC "IPR3,Interrupt Priority Register" hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority" hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority" hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority" hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority" line.long 0x10 "IPR4,Interrupt Priority Register" hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority" hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority" hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority" hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority" line.long 0x14 "IPR5,Interrupt Priority Register" hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority" hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority" hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority" hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority" line.long 0x18 "IPR6,Interrupt Priority Register" hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority" hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority" hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority" hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority" line.long 0x1C "IPR7,Interrupt Priority Register" hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority" hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority" hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority" hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority" line.long 0x20 "IPR8,Interrupt Priority Register" hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority" hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority" hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority" hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority" line.long 0x24 "IPR9,Interrupt Priority Register" hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority" hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority" hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority" hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority" line.long 0x28 "IPR10,Interrupt Priority Register" hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority" hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority" hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority" hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority" line.long 0x2C "IPR11,Interrupt Priority Register" hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority" hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority" hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority" hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority" line.long 0x30 "IPR12,Interrupt Priority Register" hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority" hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority" hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority" hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority" line.long 0x34 "IPR13,Interrupt Priority Register" hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority" hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority" hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority" hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority" line.long 0x38 "IPR14,Interrupt Priority Register" hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority" hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority" hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority" hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority" line.long 0x3C "IPR15,Interrupt Priority Register" hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority" hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority" hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority" hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority" line.long 0x40 "IPR16,Interrupt Priority Register" hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority" hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority" hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority" hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority" line.long 0x44 "IPR17,Interrupt Priority Register" hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority" hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority" hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority" hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority" line.long 0x48 "IPR18,Interrupt Priority Register" hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority" hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority" hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority" hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority" line.long 0x4C "IPR19,Interrupt Priority Register" hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority" hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority" hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority" hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority" line.long 0x50 "IPR20,Interrupt Priority Register" hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority" hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority" hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority" hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority" line.long 0x54 "IPR21,Interrupt Priority Register" hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority" hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority" hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority" hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority" line.long 0x58 "IPR22,Interrupt Priority Register" hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority" hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority" hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority" hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority" line.long 0x5C "IPR23,Interrupt Priority Register" hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority" hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority" hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority" hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority" line.long 0x60 "IPR24,Interrupt Priority Register" hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority" hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority" hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority" hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority" line.long 0x64 "IPR25,Interrupt Priority Register" hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority" hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority" hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority" hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority" line.long 0x68 "IPR26,Interrupt Priority Register" hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority" hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority" hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority" hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority" line.long 0x6C "IPR27,Interrupt Priority Register" hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority" hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority" hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority" hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority" line.long 0x70 "IPR28,Interrupt Priority Register" hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority" hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority" hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority" hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority" line.long 0x74 "IPR29,Interrupt Priority Register" hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority" hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority" hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority" hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority" line.long 0x78 "IPR30,Interrupt Priority Register" hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority" hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority" hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority" hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority" line.long 0x7C "IPR31,Interrupt Priority Register" hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority" hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority" hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority" hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority" line.long 0x80 "IPR32,Interrupt Priority Register" hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority" hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority" hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority" hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority" line.long 0x84 "IPR33,Interrupt Priority Register" hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority" hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority" hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority" hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority" line.long 0x88 "IPR34,Interrupt Priority Register" hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority" hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority" hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority" hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority" line.long 0x8C "IPR35,Interrupt Priority Register" hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority" hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority" hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority" hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority" line.long 0x90 "IPR36,Interrupt Priority Register" hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority" hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority" hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority" hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority" line.long 0x94 "IPR37,Interrupt Priority Register" hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority" hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority" hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority" hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority" line.long 0x98 "IPR38,Interrupt Priority Register" hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority" hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority" hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority" hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority" line.long 0x9C "IPR39,Interrupt Priority Register" hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority" hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority" hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority" hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority" line.long 0xA0 "IPR40,Interrupt Priority Register" hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority" hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority" hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority" hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority" line.long 0xA4 "IPR41,Interrupt Priority Register" hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority" hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority" hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority" hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority" line.long 0xA8 "IPR42,Interrupt Priority Register" hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority" hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority" hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority" hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority" line.long 0xAC "IPR43,Interrupt Priority Register" hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority" hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority" hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority" hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority" line.long 0xB0 "IPR44,Interrupt Priority Register" hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority" hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority" hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority" hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority" line.long 0xB4 "IPR45,Interrupt Priority Register" hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority" hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority" hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority" hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority" line.long 0xB8 "IPR46,Interrupt Priority Register" hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority" hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority" hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority" hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority" line.long 0xBC "IPR47,Interrupt Priority Register" hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority" hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority" hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority" hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority" line.long 0xC0 "IPR48,Interrupt Priority Register" hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority" hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority" hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority" hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority" line.long 0xC4 "IPR49,Interrupt Priority Register" hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority" hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority" hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority" hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority" line.long 0xC8 "IPR50,Interrupt Priority Register" hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority" hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority" hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority" hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority" line.long 0xCC "IPR51,Interrupt Priority Register" hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority" hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority" hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority" hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority" line.long 0xD0 "IPR52,Interrupt Priority Register" hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority" hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority" hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority" hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority" line.long 0xD4 "IPR53,Interrupt Priority Register" hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority" hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority" hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority" hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority" line.long 0xD8 "IPR54,Interrupt Priority Register" hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority" hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority" hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority" hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority" line.long 0xDC "IPR55,Interrupt Priority Register" hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority" hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority" hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority" hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority" line.long 0xE0 "IPR56,Interrupt Priority Register" hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority" hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority" hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority" hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority" line.long 0xE4 "IPR57,Interrupt Priority Register" hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority" hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority" hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority" hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority" line.long 0xE8 "IPR58,Interrupt Priority Register" hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority" hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority" hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority" hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority" line.long 0xEC "IPR59,Interrupt Priority Register" hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority" hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority" hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority" hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority" else hgroup.long 0x400++0xEF hide.long 0x0 "IPR0,Interrupt Priority Register" hide.long 0x4 "IPR1,Interrupt Priority Register" hide.long 0x8 "IPR2,Interrupt Priority Register" hide.long 0xC "IPR3,Interrupt Priority Register" hide.long 0x10 "IPR4,Interrupt Priority Register" hide.long 0x14 "IPR5,Interrupt Priority Register" hide.long 0x18 "IPR6,Interrupt Priority Register" hide.long 0x1C "IPR7,Interrupt Priority Register" hide.long 0x20 "IPR8,Interrupt Priority Register" hide.long 0x24 "IPR9,Interrupt Priority Register" hide.long 0x28 "IPR10,Interrupt Priority Register" hide.long 0x2C "IPR11,Interrupt Priority Register" hide.long 0x30 "IPR12,Interrupt Priority Register" hide.long 0x34 "IPR13,Interrupt Priority Register" hide.long 0x38 "IPR14,Interrupt Priority Register" hide.long 0x3C "IPR15,Interrupt Priority Register" hide.long 0x40 "IPR16,Interrupt Priority Register" hide.long 0x44 "IPR17,Interrupt Priority Register" hide.long 0x48 "IPR18,Interrupt Priority Register" hide.long 0x4C "IPR19,Interrupt Priority Register" hide.long 0x50 "IPR20,Interrupt Priority Register" hide.long 0x54 "IPR21,Interrupt Priority Register" hide.long 0x58 "IPR22,Interrupt Priority Register" hide.long 0x5C "IPR23,Interrupt Priority Register" hide.long 0x60 "IPR24,Interrupt Priority Register" hide.long 0x64 "IPR25,Interrupt Priority Register" hide.long 0x68 "IPR26,Interrupt Priority Register" hide.long 0x6C "IPR27,Interrupt Priority Register" hide.long 0x70 "IPR28,Interrupt Priority Register" hide.long 0x74 "IPR29,Interrupt Priority Register" hide.long 0x78 "IPR30,Interrupt Priority Register" hide.long 0x7C "IPR31,Interrupt Priority Register" hide.long 0x80 "IPR32,Interrupt Priority Register" hide.long 0x84 "IPR33,Interrupt Priority Register" hide.long 0x88 "IPR34,Interrupt Priority Register" hide.long 0x8C "IPR35,Interrupt Priority Register" hide.long 0x90 "IPR36,Interrupt Priority Register" hide.long 0x94 "IPR37,Interrupt Priority Register" hide.long 0x98 "IPR38,Interrupt Priority Register" hide.long 0x9C "IPR39,Interrupt Priority Register" hide.long 0xA0 "IPR40,Interrupt Priority Register" hide.long 0xA4 "IPR41,Interrupt Priority Register" hide.long 0xA8 "IPR42,Interrupt Priority Register" hide.long 0xAC "IPR43,Interrupt Priority Register" hide.long 0xB0 "IPR44,Interrupt Priority Register" hide.long 0xB4 "IPR45,Interrupt Priority Register" hide.long 0xB8 "IPR46,Interrupt Priority Register" hide.long 0xBC "IPR47,Interrupt Priority Register" hide.long 0xC0 "IPR48,Interrupt Priority Register" hide.long 0xC4 "IPR49,Interrupt Priority Register" hide.long 0xC8 "IPR50,Interrupt Priority Register" hide.long 0xCC "IPR51,Interrupt Priority Register" hide.long 0xD0 "IPR52,Interrupt Priority Register" hide.long 0xD4 "IPR53,Interrupt Priority Register" hide.long 0xD8 "IPR54,Interrupt Priority Register" hide.long 0xDC "IPR55,Interrupt Priority Register" hide.long 0xE0 "IPR56,Interrupt Priority Register" hide.long 0xE4 "IPR57,Interrupt Priority Register" hide.long 0xE8 "IPR58,Interrupt Priority Register" hide.long 0xEC "IPR59,Interrupt Priority Register" endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end sif CORENAME()=="CORTEXM4F" tree "Floating-point Unit (FPU)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 8. group.long 0xF34++0x0B line.long 0x00 "FPCCR,Floating-Point Context Control Register" bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled" bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled" bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able" textline " " bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able" bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able" bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able" textline " " bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread" bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged" bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active" line.long 0x04 "FPCAR,Floating-Point Context Address Register" hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame" line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register" bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative" bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation" bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode" textline " " bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero" rgroup.long 0xF40++0x07 line.long 0x00 "MVFR0,Media and FP Feature Register 0" bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..." bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..." bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..." textline " " bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..." bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..." bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..." bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..." line.long 0x04 "MVFR1,Media and FP Feature Register 1" bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..." bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..." textline " " bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..." bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..." width 0xB else newline textline "COREDEBUG component base address not specified" newline endif tree.end endif tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 7. group.long 0xD30++0x03 line.long 0x00 "DFSR,Debug Fault Status Register" eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated" eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered" eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated" newline eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated" eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated" newline hgroup.long 0xDF0++0x03 hide.long 0x00 "DHCSR,Debug Halting Control and Status Register" in newline wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Register Selector Register" bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write" hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register" group.long 0xDF8++0x03 line.long 0x00 "DCRDR,Debug Core Register Data Register" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000) group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" else group.long 0xDFC++0x03 line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled" bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1" newline bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending" bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled" bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled" newline bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled" bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled" bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" newline bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled" bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled" bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled" newline bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled" endif width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Flash Patch and Breakpoint Unit (FPB)" sif COMPonent.AVAILABLE("FPB") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1)) width 10. group.long 0x00++0x07 line.long 0x00 "FP_CTRL,Flash Patch Control Register" bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..." rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127" bitfld.long 0x00 1. " KEY ,Key Field" "Low,High" bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled" textline "" line.long 0x04 "FP_REMAP,Flash Patch Remap Register" bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region" hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field" if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00) group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x8++0x03 line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00) group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0xC++0x03 line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00) group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x10++0x03 line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00) group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x14++0x03 line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00) group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x18++0x03 line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00) group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x1C++0x03 line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00) group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x20++0x03 line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both" hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address" bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled" elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000) if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00) group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" else group.long 0x24++0x03 line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7" hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address" bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled" endif endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0xB else newline textline "FPB component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 15. group.long 0x00++0x1B line.long 0x00 "DWT_CTRL,Control Register" rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported" rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported" textline " " rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported" rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported" bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled" bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled" bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled" bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled" bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled" bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]" bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]" textline " " bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled" line.long 0x04 "DWT_CYCCNT,Cycle Count Register" line.long 0x08 "DWT_CPICNT,CPI Count Register" hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter" line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register" hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter" line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register" hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter" line.long 0x14 "DWT_LSUCNT,LSU Count Register" hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter" line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register" hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter" rgroup.long 0x1C++0x03 line.long 0x00 "DWT_PCSR,Program Counter Sample register" textline " " group.long 0x20++0x07 line.long 0x00 "DWT_COMP0,DWT Comparator Register 0" line.long 0x04 "DWT_MASK0,DWT Mask Registers 0" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80) group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" else group.long 0x28++0x03 line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled" bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x30)++0x07 line.long 0x00 "DWT_COMP1,DWT Comparator Register 1" line.long 0x04 "DWT_MASK1,DWT Mask Registers 1" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00) group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x30+0x08)++0x03 line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x40)++0x07 line.long 0x00 "DWT_COMP2,DWT Comparator Register 2" line.long 0x04 "DWT_MASK2,DWT Mask Registers 2" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00) group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x40+0x08)++0x03 line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif group.long (0x50)++0x07 line.long 0x00 "DWT_COMP3,DWT Comparator Register 3" line.long 0x04 "DWT_MASK3,DWT Mask Registers 3" bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE" elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00) group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE" else group.long (0x50+0x08)++0x03 line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3" bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched" bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved" bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported" bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled" bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE" endif width 6. tree "CoreSight Identification Registers" rgroup.long 0xFE0++0x0F line.long 0x00 "PID0,Peripheral ID0" hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]" line.long 0x04 "PID1,Peripheral ID1" hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]" hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]" line.long 0x08 "PID2,Peripheral ID2" hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision" bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC" hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]" line.long 0x0c "PID3,Peripheral ID3" hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field" hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block" rgroup.long 0xFD0++0x03 line.long 0x00 "PID4,Peripheral Identification Register 4" hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count" hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code" rgroup.long 0xFF0++0x0F line.long 0x00 "CID0,Component ID0 (Preamble)" line.long 0x04 "CID1,Component ID1" hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class" hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble" line.long 0x08 "CID2,Component ID2" line.long 0x0c "CID3,Component ID3" tree.end width 0x0B else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end tree "ACMPLP (Low-Power Analog Comparator)" base ad:0x40085E00 group.byte 0x0++0x2 line.byte 0x0 "COMPMDR,ACMPLP Mode Setting Register" rbitfld.byte 0x0 7. "C1MON,ACMPLP1 Monitor Flag" "0: CMPIN1 < CMPREF1 CMPIN1 < internal reference..,1: CMPIN1 > CMPREF1 or CMPIN1 > internal reference.." bitfld.byte 0x0 6. "C1VRF,ACMPLP1 Reference Voltage Selection" "0: IVREF0 or IVREF1,1: internal reference voltage (Vref)" newline bitfld.byte 0x0 5. "C1WDE,ACMPLP1 Window Function Mode Enable" "0: Disabled,1: Enabled" bitfld.byte 0x0 4. "C1ENB,ACMPLP1 Operation Enable" "0: Disabled,1: Enabled" newline rbitfld.byte 0x0 3. "C0MON,ACMPLP0 Monitor Flag" "0: CMPIN0 < CMPREF0 CMPIN0 < internal reference..,1: CMPIN0 > CMPREF0 or CMPIN0 > internal reference.." bitfld.byte 0x0 2. "C0VRF,ACMPLP0 Reference Voltage Selection" "0: IVREF0,1: internal reference voltage (Vref)" newline bitfld.byte 0x0 1. "C0WDE,ACMPLP0 Window Function Mode Enable" "0: Disabled,1: Enabled" bitfld.byte 0x0 0. "C0ENB,ACMPLP0 Operation Enable" "0: Disabled,1: Enabled" line.byte 0x1 "COMPFIR,ACMPLP Filter Control Register" bitfld.byte 0x1 7. "C1EDG,ACMPLP1 Edge Detection Selection" "0: Interrupt and ELC event request by one-edge..,1: Interrupt and ELC event request by both-edge.." bitfld.byte 0x1 6. "C1EPO,ACMPLP1 Edge Polarity Switching" "0: Interrupt and ELC event request at rising edge,1: Interrupt and ELC event request at falling edge" newline bitfld.byte 0x1 4.--5. "C1FCK,ACMPLP1 Filter Select" "0: No Sampling (bypass),1: Sampling at PCLK,?,?" bitfld.byte 0x1 3. "C0EDG,ACMPLP0 Edge Detection Selection" "0: Interrupt and ELC event request by one-edge..,1: Interrupt and ELC event request by both-edge.." newline bitfld.byte 0x1 2. "C0EPO,ACMPLP0 Edge Polarity Switching" "0: Interrupt and ELC event request at rising edge,1: Interrupt and ELC event request at falling edge" bitfld.byte 0x1 0.--1. "C0FCK,ACMPLP0 Filter Select" "0: No Sampling (bypass),1: Sampling at PCLK,?,?" line.byte 0x2 "COMPOCR,ACMPLP Output Control Register" bitfld.byte 0x2 7. "SPDMD,ACMPLP0/ACMPLP1 Speed Selection" "0: Comparator low-speed mode,1: Comparator high-speed mode" bitfld.byte 0x2 6. "C1OP,ACMPLP1 VCOUT Output Polarity Selection" "0: Non inverted,1: Inverted" newline bitfld.byte 0x2 5. "C1OE,ACMPLP1 VCOUT Pin Output Enable" "0: Disabled,1: Enabled" bitfld.byte 0x2 3.--4. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" newline bitfld.byte 0x2 2. "C0OP,ACMPLP0 VCOUT Output Polarity Selection" "0: Non inverted,1: Inverted" bitfld.byte 0x2 1. "C0OE,ACMPLP0 VCOUT Pin Output Enable" "0: Disabled,1: Enabled" newline bitfld.byte 0x2 0. "Reserved,This bit is read as 0. The write value should be 0." "0,1" group.byte 0x4++0x1 line.byte 0x0 "COMPSEL0,Comparator Input Select Register" bitfld.byte 0x0 7. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 4.--6. "CMPSEL64,ACMPLP1 Input (IVCMP1) Selection" "0: settings prohibited,1: CMPIN1 (P102),?,?,?,?,?,?" newline bitfld.byte 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 0.--2. "CMPSEL20,ACMPLP0 Input(IVCMP0) Selection" "0: settings prohibited,1: CMPIN0 (P100),?,?,?,?,?,?" line.byte 0x1 "COMPSEL1,Comparator Reference Voltage Select Register" bitfld.byte 0x1 7. "C1VRF2,ACMPLP1 Reference Voltage Selection" "0: IVREF0 selected,1: IVREF1 selected." bitfld.byte 0x1 4.--6. "CRVS64,ACMPLP1 Reference Voltage(IVREF1) Selection" "0: settings prohibited.,1: CMPREF1 (P103),?,?,?,?,?,?" newline bitfld.byte 0x1 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x1 0.--2. "CRVS20,ACMPLP0 Reference Voltage(IVREF0) Selection*" "0: settings prohibited.,1: CMPREF0 (P101),?,?,?,?,?,?" tree.end tree "ADC14 (14-bit A/D Converter)" base ad:0x4005C000 group.word 0x0++0x1 line.word 0x0 "ADCSR,A/D Control Register" bitfld.word 0x0 15. "ADST,A/D Conversion Start" "0: Stops A/D conversion process.,1: Starts A/D conversion process." bitfld.word 0x0 13.--14. "ADCS,Scan Mode Select" "0: Single scan mode,1: Group scan mode,?,?" newline bitfld.word 0x0 11.--12. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.word 0x0 10. "ADHSC,A/D Conversion Operation Mode Select" "0: High speed A/D conversion mode,1: Low current A/D conversion mode" newline bitfld.word 0x0 9. "TRGE,Trigger Start Enable" "0: Disables A/D conversion to be started by the..,1: Enables A/D conversion to be started by the.." bitfld.word 0x0 8. "EXTRG,Trigger Select" "0: A/D conversion is started by the synchronous..,1: A/D conversion is started by the asynchronous.." newline bitfld.word 0x0 7. "DBLE,Double Trigger Mode Select" "0: Double trigger mode non-selection,1: Double trigger mode selection" bitfld.word 0x0 6. "GBADIE,Group B Scan End Interrupt Enable" "0: Disables S12GBADI0 interrupt generation upon..,1: Enables S12GBADI0 interrupt generation upon.." newline bitfld.word 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" hexmask.word.byte 0x0 0.--4. 1. "DBLANS,Double Trigger Channel SelectThese bits select one analog input channel for double triggered operation. The setting is only effective while double trigger mode is selected." group.word 0x4++0x7 line.word 0x0 "ADANSA0,A/D Channel Select Register A0" bitfld.word 0x0 15. "ANSA015,AN015 Select" "0: AN015 is not subjected to conversion.,1: AN015 is subjected to conversion." bitfld.word 0x0 14. "ANSA014,AN014 Select" "0: AN014 is not subjected to conversion.,1: AN014 is subjected to conversion." newline bitfld.word 0x0 13. "ANSA013,AN013 Select" "0: AN013 is not subjected to conversion.,1: AN013 is subjected to conversion." bitfld.word 0x0 12. "ANSA012,AN012 Select" "0: AN012 is not subjected to conversion.,1: AN012 is subjected to conversion." newline bitfld.word 0x0 11. "ANSA011,AN011 Select" "0: AN011 is not subjected to conversion.,1: AN011 is subjected to conversion." bitfld.word 0x0 10. "ANSA010,AN010 Select" "0: AN010 is not subjected to conversion.,1: AN010 is subjected to conversion." newline bitfld.word 0x0 9. "ANSA09,AN009 Select" "0: AN009 is not subjected to conversion.,1: AN009 is subjected to conversion." bitfld.word 0x0 8. "ANSA08,AN008 Select" "0: AN008 is not subjected to conversion.,1: AN008 is subjected to conversion." newline bitfld.word 0x0 7. "ANSA07,AN007 Select" "0: AN007 is not subjected to conversion.,1: AN007 is subjected to conversion." bitfld.word 0x0 6. "ANSA06,AN006 Select" "0: AN006 is not subjected to conversion.,1: AN006 is subjected to conversion." newline bitfld.word 0x0 5. "ANSA05,AN005 Select" "0: AN005 is not subjected to conversion.,1: AN005 is subjected to conversion." bitfld.word 0x0 4. "ANSA04,AN004 Select" "0: AN004 is not subjected to conversion.,1: AN004 is subjected to conversion." newline bitfld.word 0x0 3. "ANSA03,AN003 Select" "0: AN003 is not subjected to conversion.,1: AN003 is subjected to conversion." bitfld.word 0x0 2. "ANSA02,AN002 Select" "0: AN002 is not subjected to conversion.,1: AN002 is subjected to conversion." newline bitfld.word 0x0 1. "ANSA01,AN001 Select" "0: AN001 is not subjected to conversion.,1: AN001 is subjected to conversion." bitfld.word 0x0 0. "ANSA00,AN000 Select" "0: AN000 is not subjected to conversion.,1: AN000 is subjected to conversion." line.word 0x2 "ADANSA1,A/D Channel Select Register A1" hexmask.word.byte 0x2 12.--15. 1. "Reserved,These bits are read as 0000. The write value should be 0000." bitfld.word 0x2 11. "ANSA27,AN027 Select" "0: AN027 is not subjected to conversion.,1: AN027 is subjected to conversion." newline bitfld.word 0x2 10. "ANSA26,AN026 Select" "0: AN026 is not subjected to conversion.,1: AN026 is subjected to conversion." bitfld.word 0x2 9. "ANSA25,AN025 Select" "0: AN025 is not subjected to conversion.,1: AN025 is subjected to conversion." newline bitfld.word 0x2 8. "ANSA24,AN024 Select" "0: AN024 is not subjected to conversion.,1: AN024 is subjected to conversion." bitfld.word 0x2 7. "ANSA23,AN023 Select" "0: AN023 is not subjected to conversion.,1: AN023 is subjected to conversion." newline bitfld.word 0x2 6. "ANSA22,AN022 Select" "0: AN022 is not subjected to conversion.,1: AN022 is subjected to conversion." bitfld.word 0x2 5. "ANSA21,AN021 Select" "0: AN021 is not subjected to conversion.,1: AN021 is subjected to conversion." newline bitfld.word 0x2 4. "ANSA20,AN020 Select" "0: AN020 is not subjected to conversion.,1: AN020 is subjected to conversion." bitfld.word 0x2 3. "ANSA19,AN019 Select" "0: AN019 is not subjected to conversion.,1: AN019 is subjected to conversion." newline bitfld.word 0x2 2. "ANSA18,AN018 Select" "0: AN018 is not subjected to conversion.,1: AN018 is subjected to conversion." bitfld.word 0x2 1. "ANSA17,AN017 Select" "0: AN017 is not subjected to conversion.,1: AN017 is subjected to conversion." newline bitfld.word 0x2 0. "ANSA16,AN016 Select" "0: AN016 is not subjected to conversion.,1: AN016 is subjected to conversion." line.word 0x4 "ADADS0,A/D-Converted Value Addition/Average Channel Select Register 0" bitfld.word 0x4 15. "ADS15,A/D-Converted Value Addition/Average Channel AN015 Select" "0: AN015 is not selected.,1: AN015 is selected." bitfld.word 0x4 14. "ADS14,A/D-Converted Value Addition/Average Channel AN014 Select" "0: AN014 is not selected.,1: AN014 is selected." newline bitfld.word 0x4 13. "ADS13,A/D-Converted Value Addition/Average Channel AN013 Select" "0: AN013 is not selected.,1: AN013 is selected." bitfld.word 0x4 12. "ADS12,A/D-Converted Value Addition/Average Channel AN012 Select" "0: AN012 is not selected.,1: AN012 is selected." newline bitfld.word 0x4 11. "ADS11,A/D-Converted Value Addition/Average Channel AN011 Select" "0: AN011 is not selected.,1: AN011 is selected." bitfld.word 0x4 10. "ADS10,A/D-Converted Value Addition/Average Channel AN010 Select" "0: AN010 is not selected.,1: AN010 is selected." newline bitfld.word 0x4 9. "ADS09,A/D-Converted Value Addition/Average Channel AN009 Select" "0: AN009 is not selected.,1: AN009 is selected." bitfld.word 0x4 8. "ADS08,A/D-Converted Value Addition/Average Channel AN008 Select" "0: AN008 is not selected.,1: AN008 is selected." newline bitfld.word 0x4 7. "ADS07,A/D-Converted Value Addition/Average Channel AN007 Select" "0: AN007 is not selected.,1: AN007 is selected." bitfld.word 0x4 6. "ADS06,A/D-Converted Value Addition/Average Channel AN006 Select" "0: AN006 is not selected.,1: AN006 is selected." newline bitfld.word 0x4 5. "ADS05,A/D-Converted Value Addition/Average Channel AN005 Select" "0: AN005 is not selected.,1: AN005 is selected." bitfld.word 0x4 4. "ADS04,A/D-Converted Value Addition/Average Channel AN004 Select" "0: AN004 is not selected.,1: AN004 is selected." newline bitfld.word 0x4 3. "ADS03,A/D-Converted Value Addition/Average Channel AN003 Select" "0: AN003 is not selected.,1: AN003 is selected." bitfld.word 0x4 2. "ADS02,A/D-Converted Value Addition/Average Channel AN002 Select" "0: AN002 is not selected.,1: AN002 is selected." newline bitfld.word 0x4 1. "ADS01,A/D-Converted Value Addition/Average Channel AN001 Select" "0: AN001 is not selected.,1: AN001 is selected." bitfld.word 0x4 0. "ADS00,A/D-Converted Value Addition/Average Channel AN000 Select" "0: AN000 is not selected.,1: AN000 is selected." line.word 0x6 "ADADS1,A/D-Converted Value Addition/Average Channel Select Register 1" hexmask.word.byte 0x6 12.--15. 1. "Reserved,These bits are read as 0000. The write value should be 0000." bitfld.word 0x6 11. "ADS27,A/D-Converted Value Addition/Average Channel AN027 Select" "0: AN027 is not selected.,1: AN027 is selected." newline bitfld.word 0x6 10. "ADS26,A/D-Converted Value Addition/Average Channel AN026 Select" "0: AN026 is not selected.,1: AN026 is selected." bitfld.word 0x6 9. "ADS25,A/D-Converted Value Addition/Average Channel AN025 Select" "0: AN025 is not selected.,1: AN025 is selected." newline bitfld.word 0x6 8. "ADS24,A/D-Converted Value Addition/Average Channel AN024 Select" "0: AN024 is not selected.,1: AN024 is selected." bitfld.word 0x6 7. "ADS23,A/D-Converted Value Addition/Average Channel AN023 Select" "0: AN023 is not selected.,1: AN023 is selected." newline bitfld.word 0x6 6. "ADS22,A/D-Converted Value Addition/Average Channel AN022 Select" "0: AN022 is not selected.,1: AN022 is selected." bitfld.word 0x6 5. "ADS21,A/D-Converted Value Addition/Average Channel AN021 Select" "0: AN021 is not selected.,1: AN021 is selected." newline bitfld.word 0x6 4. "ADS20,A/D-Converted Value Addition/Average Channel AN020 Select" "0: AN020 is not selected.,1: AN020 is selected." bitfld.word 0x6 3. "ADS19,A/D-Converted Value Addition/Average Channel AN019 Select" "0: AN019 is not selected.,1: AN019 is selected." newline bitfld.word 0x6 2. "ADS18,A/D-Converted Value Addition/Average Channel AN018 Select" "0: AN018 is not selected.,1: AN018 is selected." bitfld.word 0x6 1. "ADS17,A/D-Converted Value Addition/Average Channel AN017 Select" "0: AN017 is not selected.,1: AN017 is selected." newline bitfld.word 0x6 0. "ADS16,A/D-Converted Value Addition/Average Channel AN016 Select" "0: AN016 is not selected.,1: AN016 is selected." group.byte 0xC++0x0 line.byte 0x0 "ADADC,A/D-Converted Value Addition/Average Count Select Register" bitfld.byte 0x0 7. "AVEE,Average mode enable bit.Note: The AVEE bit converts twice and only when converting it four times is effective. Please do not set (ADADC.AVEE=1) to conversion (ADADC.ADC 2:0=010b) three times when you select the average mode." "0: Disabled,1: Enabled" hexmask.byte 0x0 3.--6. 1. "Reserved,These bits are read as 0000. The write value should be 0000." newline bitfld.byte 0x0 0.--2. "ADC,Addition frequency selection bit.NOTE: AVEE bit is valid at the only setting of ADC[2:0] bits = 001b or 011b. When average mode is selected by setting the ADADC.AVEE bit to 1 do not set the addition count to three times (ADADC.ADC[2:0] = 010b)" "0: Setting prohibited,1: 2-time conversion (addition once),?,?,?,?,?,?" group.word 0xE++0x9 line.word 0x0 "ADCER,A/D Control Extended Register" bitfld.word 0x0 15. "ADRFMT,A/D Data Register Format Select" "0: Flush-right is selected for the A/D data..,1: Flush-left is selected for the A/D data register.." bitfld.word 0x0 12.--14. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 11. "DIAGM,Self-Diagnosis Enable" "0: Disables self-diagnosis of A/D converter.,1: Enables self-diagnosis of A/D converter." bitfld.word 0x0 10. "DIAGLD,Self-Diagnosis Mode Select" "0: Rotation mode for self-diagnosis voltage,1: Fixed mode for self-diagnosis voltage" newline bitfld.word 0x0 8.--9. "DIAGVAL,Self-Diagnosis Conversion Voltage Select" "0: When the self-diagnosis fixation mode is..,1: The self-diagnosis by using the voltage of 0V.,?,?" bitfld.word 0x0 6.--7. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" newline bitfld.word 0x0 5. "ACE,A/D Data Register Automatic Clearing Enable" "0: Disables automatic clearing.,1: Enables automatic clearing." bitfld.word 0x0 4. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.word 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x0 1.--2. "ADPRC,A/D Conversion Accuracy Specify" "0: Setting prohibited,?,?,?" newline bitfld.word 0x0 0. "Reserved,This bit is read as 0. The write value should be 0." "0,1" line.word 0x2 "ADSTRGR,A/D Conversion Start Trigger Select Register" bitfld.word 0x2 14.--15. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" hexmask.word.byte 0x2 8.--13. 1. "TRSA,A/D Conversion Start Trigger SelectSelect the A/D conversion start trigger in single scan mode and continuous mode. In group scan mode the A/D conversion start trigger for group A is selected." newline bitfld.word 0x2 6.--7. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" hexmask.word.byte 0x2 0.--5. 1. "TRSB,A/D Conversion Start Trigger Select for Group BSelect the A/D conversion start trigger for group B in group scan mode." line.word 0x4 "ADEXICR,A/D Conversion Extended Input Control Register" bitfld.word 0x4 15. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x4 14. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.word 0x4 12. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x4 11. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.word 0x4 10. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x4 9. "OCSA,Internal Reference Voltage A/D Conversion Select" "0: The internal reference voltage is not selected.,1: The internal reference voltage is selected for.." newline bitfld.word 0x4 8. "TSSA,Temperature Sensor Output A/D Conversion Select" "0: The temperature sensor output is not selected.,1: The temperature sensor output is selected." hexmask.word.byte 0x4 2.--7. 1. "Reserved,These bits are read as 000000. The write value should be 000000." newline bitfld.word 0x4 1. "OCSAD,Internal Reference Voltage A/D converted Value Addition/Average Mode Select" "0: Internal reference voltage A/D-converted value..,1: Internal reference voltage A/D-converted value.." bitfld.word 0x4 0. "TSSAD,Temperature Sensor Output A/D converted Value Addition/Average Mode Select" "0: Temperature sensor output A/D-converted value..,1: Temperature sensor output A/D-converted value.." line.word 0x6 "ADANSB0,A/D Channel Select Register B0" bitfld.word 0x6 15. "ANSB15,AN015 Select" "0: AN015 is not subjected to conversion.,1: AN015 is subjected to conversion." bitfld.word 0x6 14. "ANSB14,AN014 Select" "0: AN014 is not subjected to conversion.,1: AN014 is subjected to conversion." newline bitfld.word 0x6 13. "ANSB13,AN013 Select" "0: AN013 is not subjected to conversion.,1: AN013 is subjected to conversion." bitfld.word 0x6 12. "ANSB12,AN012 Select" "0: AN012 is not subjected to conversion.,1: AN012 is subjected to conversion." newline bitfld.word 0x6 11. "ANSB11,AN011 Select" "0: AN011 is not subjected to conversion.,1: AN011 is subjected to conversion." bitfld.word 0x6 10. "ANSB10,AN010 Select" "0: AN010 is not subjected to conversion.,1: AN010 is subjected to conversion." newline bitfld.word 0x6 9. "ANSB09,AN009 Select" "0: AN009 is not subjected to conversion.,1: AN009 is subjected to conversion." bitfld.word 0x6 8. "ANSB08,AN008 Select" "0: AN008 is not subjected to conversion.,1: AN008 is subjected to conversion." newline bitfld.word 0x6 7. "ANSB07,AN007 Select" "0: AN007 is not subjected to conversion.,1: AN007 is subjected to conversion." bitfld.word 0x6 6. "ANSB06,AN006 Select" "0: AN006 is not subjected to conversion.,1: AN006 is subjected to conversion." newline bitfld.word 0x6 5. "ANSB05,AN005 Select" "0: AN005 is not subjected to conversion.,1: AN005 is subjected to conversion." bitfld.word 0x6 4. "ANSB04,AN004 Select" "0: AN004 is not subjected to conversion.,1: AN004 is subjected to conversion." newline bitfld.word 0x6 3. "ANSB03,AN003 Select" "0: AN003 is not subjected to conversion.,1: AN003 is subjected to conversion." bitfld.word 0x6 2. "ANSB02,AN002 Select" "0: AN002 is not subjected to conversion.,1: AN002 is subjected to conversion." newline bitfld.word 0x6 1. "ANSB01,AN001 Select" "0: AN001 is not subjected to conversion.,1: AN001 is subjected to conversion." bitfld.word 0x6 0. "ANSB00,AN000 Select" "0: AN000 is not subjected to conversion.,1: AN000 is subjected to conversion." line.word 0x8 "ADANSB1,A/D Channel Select Register B1" hexmask.word.byte 0x8 12.--15. 1. "Reserved,These bits are read as 0000. The write value should be 0000." bitfld.word 0x8 11. "ANSB27,AN027 Select" "0: AN027 is not subjected to conversion.,1: AN027 is subjected to conversion." newline bitfld.word 0x8 10. "ANSB26,AN026 Select" "0: AN026 is not subjected to conversion.,1: AN026 is subjected to conversion." bitfld.word 0x8 9. "ANSB25,AN025 Select" "0: AN025 is not subjected to conversion.,1: AN025 is subjected to conversion." newline bitfld.word 0x8 8. "ANSB24,AN024 Select" "0: AN024 is not subjected to conversion.,1: AN024 is subjected to conversion." bitfld.word 0x8 7. "ANSB23,AN023 Select" "0: AN023 is not subjected to conversion.,1: AN023 is subjected to conversion." newline bitfld.word 0x8 6. "ANSB22,AN022 Select" "0: AN022 is not subjected to conversion.,1: AN022 is subjected to conversion." bitfld.word 0x8 5. "ANSB21,AN021 Select" "0: AN021 is not subjected to conversion.,1: AN021 is subjected to conversion." newline bitfld.word 0x8 4. "ANSB20,AN020 Select" "0: AN020 is not subjected to conversion.,1: AN020 is subjected to conversion." bitfld.word 0x8 3. "ANSB19,AN019 Select" "0: AN019 is not subjected to conversion.,1: AN019 is subjected to conversion." newline bitfld.word 0x8 2. "ANSB18,AN018 Select" "0: AN018 is not subjected to conversion.,1: AN018 is subjected to conversion." bitfld.word 0x8 1. "ANSB17,AN017 Select" "0: AN017 is not subjected to conversion.,1: AN017 is subjected to conversion." newline bitfld.word 0x8 0. "ANSB16,AN016 Select" "0: AN016 is not subjected to conversion.,1: AN016 is subjected to conversion." rgroup.word 0x18++0x7 line.word 0x0 "ADDBLDR,A/D Data Duplication Register" hexmask.word 0x0 0.--15. 1. "ADDBLDR,This is a 16-bit read-only register for storing the result of A/D conversion in response to the second trigger in double trigger mode." line.word 0x2 "ADTSDR,A/D Temperature Sensor Data Register" hexmask.word 0x2 0.--15. 1. "ADTSDR,This is a 16-bit read-only register for storing the A/D conversion result of temperature sensor output." line.word 0x4 "ADOCDR,A/D Internal Reference Voltage Data Register" hexmask.word 0x4 0.--15. 1. "ADOCDR,This is a 16-bit read-only register for storing the A/D result of internal reference voltage." line.word 0x6 "ADRD,A/D Self-Diagnosis Data Register" bitfld.word 0x6 14.--15. "DIAGST,Self-Diagnosis Status" "0: Self-diagnosis has never been executed since..,1: Self-diagnosis using the voltage of 0 V has been..,?,?" hexmask.word 0x6 0.--13. 1. "AD,A/D-converted value (right-justified)The format for data determine ADCER.ADRFMT and ADCER.ADPRC." repeat 28. (increment 0x0 0x1)(increment 0x0 0x2) rgroup.word ($2+0x20)++0x1 line.word 0x0 "ADDR$1,A/D Data Register %s" hexmask.word 0x0 0.--15. 1. "ADDR,The ADDR register is a 16-bit read-only registers for storing the result of A/D conversion." repeat.end group.byte 0x7A++0x0 line.byte 0x0 "ADDISCR,A/D Disconnection Detection Control Register" bitfld.byte 0x0 5.--7. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" hexmask.byte 0x0 0.--4. 1. "ADNDIS,The charging time" group.word 0x80++0x1 line.word 0x0 "ADGSPCR,A/D Group Scan Priority Control Register" bitfld.word 0x0 15. "GBRP,Group B Single Scan Continuous Start(Enabled only when PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit has been set to 1 single scan is performed continuously for group B regardless of the setting of the GBRSCN bit." "0: Single scan for group B is not continuously..,1: Single scan for group B is continuously activated." hexmask.word.byte 0x0 9.--14. 1. "Reserved,These bits are read as 000000. The write value should be 000000." newline bitfld.word 0x0 8. "Reserved,This bit is read as 0. The write value should be 0." "0,1" hexmask.word.byte 0x0 2.--7. 1. "Reserved,These bits are read as 000000. The write value should be 000000." newline bitfld.word 0x0 1. "GBRSCN,Group B Restart Setting(Enabled only when PGS = 1. Reserved when PGS = 0.)" "0: Scanning for group B is not restarted after..,1: Scanning for group B is restarted after having.." bitfld.word 0x0 0. "PGS,Group A priority control setting bit.Note: When the PGS bit is to be set to 1 the ADCSR.ADCS[1:0] bits must be set to 01b (group scan mode). If the bits are set to any other values proper operation is not guaranteed." "0: Operation is without group A priority control,1: Operation is with group A priority control" rgroup.word 0x84++0x3 line.word 0x0 "ADDBLDRA,A/D Data Duplexing Register A" hexmask.word 0x0 0.--15. 1. "ADDBLDRA,This register is a 16-bit read-only registers for storing the result of A/D conversion in response to the respective triggers during extended operation in double trigger mode." line.word 0x2 "ADDBLDRB,A/D Data Duplexing Register B" hexmask.word 0x2 0.--15. 1. "ADDBLDRB,This register is a 16-bit read-only registers for storing the result of A/D conversion in response to the respective triggers during extended operation in double trigger mode." group.byte 0x8A++0x0 line.byte 0x0 "ADHVREFCNT,A/D High-Potential/Low-Potential Reference Voltage Control Register" bitfld.byte 0x0 7. "ADSLP,Sleep" "0: Normal operation,1: Standby state." bitfld.byte 0x0 5.--6. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" newline bitfld.byte 0x0 2.--4. "LVSEL,Low-Potential Reference Voltage Select" "0: AVSS0 is selected as the low-potential reference..,1: VREFL0 is selected as the low-potential..,?,?,?,?,?,?" bitfld.byte 0x0 2.--3. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" newline bitfld.byte 0x0 0.--1. "CMPAB,High-Potential Reference Voltage Select" "0: AVCC0 is selected as the high-potential..,1: VREFH0 is selected as the high-potential..,?,?" rgroup.byte 0x8C++0x0 line.byte 0x0 "ADWINMON,A/D Compare Function Window A/B Status Monitor Register" bitfld.byte 0x0 6.--7. "Reserved,These bits are read as 00." "0,1,2,3" bitfld.byte 0x0 5. "MONCMPB,Comparison Result Monitor B" "0: Window B comparison conditions are not met.,1: Window B comparison conditions are met." newline bitfld.byte 0x0 4. "MONCMPA,Comparison Result Monitor A" "0: Window A comparison conditions are not met.,1: Window A comparison conditions are met." bitfld.byte 0x0 1.--3. "Reserved,These bits are read as 000." "0,1,2,3,4,5,6,7" newline bitfld.byte 0x0 0. "MONCOMB,Combination result monitorThis bit indicates the combination result.This bit is valid when both window A operation and window B operation are enabled." "0: Window A / window B composite conditions are not..,1: Window A / window B composite conditions are met." group.word 0x90++0x1 line.word 0x0 "ADCMPCR,A/D Compare Function Control Register" bitfld.word 0x0 15. "CMPAIE,Compare A Interrupt Enable" "0: ADC140_CMPAI interrupt is disabled when..,1: ADC140_CMPAI interrupt is enabled when.." bitfld.word 0x0 14. "WCMPE,Window Function Setting" "0: Window function is disabled. Window A and window..,1: Window function is enabled. Window A and window.." newline bitfld.word 0x0 13. "CMPBIE,Compare B Interrupt Enable" "0: ADC140_CMPAI interrupt is disabled when..,1: ADC140_CMPAI interrupt is enabled when.." bitfld.word 0x0 12. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.word 0x0 11. "CMPAE,Compare Window A Operation Enable" "0: Compare window A operation is disabled.,1: Compare window A operation is enabled." bitfld.word 0x0 10. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.word 0x0 9. "CMPBE,Compare Window B Operation Enable" "0: Compare window B operation is disabled.,1: Compare window B operation is enabled." hexmask.word.byte 0x0 2.--8. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." newline bitfld.word 0x0 0.--1. "CMPAB,Window A/B Composite Conditions SettingNOTE: These bits are valid when both window A and window B are enabled (CMPAE = 1 and CMPBE = 1)." "0: ADC140_WCMPM is output when window A comparison..,1: S14ADWMELC0 is output when window A comparison..,?,?" group.byte 0x92++0x1 line.byte 0x0 "ADCMPANSER,A/D Compare Function Window A Extended Input Select Register" hexmask.byte 0x0 2.--7. 1. "Reserved,These bits are read as 000000. The write value should be 000000." bitfld.byte 0x0 1. "CMPOCA,Internal reference voltage Compare selection bit." "0: Excludes the internal reference voltage from the..,1: Includes the internal reference voltage in the.." newline bitfld.byte 0x0 0. "CMPTSA,Temperature sensor output Compare selection bit." "0: Excludes the temperature sensor output from the..,1: Includes the temperature sensor output in the.." line.byte 0x1 "ADCMPLER,A/D Compare Function Window A Extended Input Comparison Condition Setting Register" hexmask.byte 0x1 2.--7. 1. "Reserved,These bits are read as 000000. The write value should be 000000." bitfld.byte 0x1 1. "CMPLOCA,Compare Window A Internal Reference Voltage ComparisonCondition Select" "0: ADCMPDR0 value > A/D converted..,1: ADCMPDR0 value < A/D converted.." newline bitfld.byte 0x1 0. "CMPLTSA,Compare Window A Temperature Sensor Output Comparison Condition Select" "0: ADCMPDR0 register value > A/D-converted..,1: ADCMPDR0 register value < A/D-converted.." group.word 0x94++0xF line.word 0x0 "ADCMPANSR0,A/D Compare Function Window A Channel Select Register 0" bitfld.word 0x0 15. "CMPCHA15,AN015 Select" "0: Excludes AN015 from the compare window A target..,1: Includes AN015 from the compare window A target.." bitfld.word 0x0 14. "CMPCHA14,AN014 Select" "0: Excludes AN014 from the compare window A target..,1: Includes AN014 from the compare window A target.." newline bitfld.word 0x0 13. "CMPCHA13,AN013 Select" "0: Excludes AN013 from the compare window A target..,1: Includes AN013 from the compare window A target.." bitfld.word 0x0 12. "CMPCHA12,AN012 Select" "0: Excludes AN012 from the compare window A target..,1: Includes AN012 from the compare window A target.." newline bitfld.word 0x0 11. "CMPCHA11,AN011 Select" "0: Excludes AN011 from the compare window A target..,1: Includes AN011 from the compare window A target.." bitfld.word 0x0 10. "CMPCHA10,AN010 Select" "0: Excludes AN010 from the compare window A target..,1: Includes AN010 from the compare window A target.." newline bitfld.word 0x0 9. "CMPCHA09,AN009 Select" "0: Excludes AN009 from the compare window A target..,1: Includes AN009 from the compare window A target.." bitfld.word 0x0 8. "CMPCHA08,AN008 Select" "0: Excludes AN008 from the compare window A target..,1: Includes AN008 from the compare window A target.." newline bitfld.word 0x0 7. "CMPCHA07,AN007 Select" "0: Excludes AN007 from the compare window A target..,1: Includes AN007 from the compare window A target.." bitfld.word 0x0 6. "CMPCHA06,AN006 Select" "0: Excludes AN006 from the compare window A target..,1: Includes AN006 from the compare window A target.." newline bitfld.word 0x0 5. "CMPCHA05,AN005 Select" "0: Excludes AN005 from the compare window A target..,1: Includes AN005 from the compare window A target.." bitfld.word 0x0 4. "CMPCHA04,AN004 Select" "0: Excludes AN004 from the compare window A target..,1: Includes AN004 from the compare window A target.." newline bitfld.word 0x0 3. "CMPCHA03,AN003 Select" "0: Excludes AN003 from the compare window A target..,1: Includes AN003 from the compare window A target.." bitfld.word 0x0 2. "CMPCHA02,AN002 Select" "0: Excludes AN002 from the compare window A target..,1: Includes AN002 from the compare window A target.." newline bitfld.word 0x0 1. "CMPCHA01,AN001 Select" "0: Excludes AN001 from the compare window A target..,1: Includes AN001 from the compare window A target.." bitfld.word 0x0 0. "CMPCHA00,AN000 Select" "0: Excludes AN000 from the compare window A target..,1: Includes AN000 from the compare window A target.." line.word 0x2 "ADCMPANSR1,A/D Compare Function Window A Channel Select Register 1" hexmask.word.byte 0x2 12.--15. 1. "Reserved,These bits are read as 0000. The write value should be 0000." bitfld.word 0x2 11. "CMPCHA27,AN027 Select" "0: Excludes AN027 from the compare window A target..,1: Includes AN027 from the compare window A target.." newline bitfld.word 0x2 10. "CMPCHA26,AN026 Select" "0: Excludes AN026 from the compare window A target..,1: Includes AN026 from the compare window A target.." bitfld.word 0x2 9. "CMPCHA25,AN025 Select" "0: Excludes AN025 from the compare window A target..,1: Includes AN025 from the compare window A target.." newline bitfld.word 0x2 8. "CMPCHA24,AN024 Select" "0: Excludes AN024 from the compare window A target..,1: Includes AN024 from the compare window A target.." bitfld.word 0x2 7. "CMPCHA23,AN023 Select" "0: Excludes AN023 from the compare window A target..,1: Includes AN023 from the compare window A target.." newline bitfld.word 0x2 6. "CMPCHA22,AN022 Select" "0: Excludes AN022 from the compare window A target..,1: Includes AN022 from the compare window A target.." bitfld.word 0x2 5. "CMPCHA21,AN021 Select" "0: Excludes AN021 from the compare window A target..,1: Includes AN021 from the compare window A target.." newline bitfld.word 0x2 4. "CMPCHA20,AN020 Select" "0: Excludes AN020 from the compare window A target..,1: Includes AN020 from the compare window A target.." bitfld.word 0x2 3. "CMPCHA19,AN019 Select" "0: Excludes AN019 from the compare window A target..,1: Includes AN019 from the compare window A target.." newline bitfld.word 0x2 2. "CMPCHA18,AN018 Select" "0: Excludes AN018 from the compare window A target..,1: Includes AN018 from the compare window A target.." bitfld.word 0x2 1. "CMPCHA17,AN017 Select" "0: Excludes AN017 from the compare window A target..,1: Includes AN017 from the compare window A target.." newline bitfld.word 0x2 0. "CMPCHA16,AN016 Select" "0: Excludes AN016 from the compare window A target..,1: Includes AN016 from the compare window A target.." line.word 0x4 "ADCMPLR0,A/D Compare Function Window A Comparison Condition Setting Register 0" bitfld.word 0x4 15. "CMPLCHA15,Comparison condition of AN015" "0: ADCMPDR0 value > A/D converted value..,1: ADCMPDR0 value < A/D converted value.." bitfld.word 0x4 14. "CMPLCHA14,Comparison condition of AN014" "0: ADCMPDR0 value > A/D converted value..,1: ADCMPDR0 value < A/D converted value.." newline bitfld.word 0x4 13. "CMPLCHA13,Comparison condition of AN013" "0: ADCMPDR0 value > A/D converted value..,1: ADCMPDR0 value < A/D converted value.." bitfld.word 0x4 12. "CMPLCHA12,Comparison condition of AN012" "0: ADCMPDR0 value > A/D converted value..,1: ADCMPDR0 value < A/D converted value.." newline bitfld.word 0x4 11. "CMPLCHA11,Comparison condition of AN011" "0: ADCMPDR0 value > A/D converted value..,1: ADCMPDR0 value < A/D converted value.." bitfld.word 0x4 10. "CMPLCHA10,Comparison condition of AN010" "0: ADCMPDR0 value > A/D converted value..,1: ADCMPDR0 value < A/D converted value.." newline bitfld.word 0x4 9. "CMPLCHA09,Comparison condition of AN009" "0: ADCMPDR0 value > A/D converted value..,1: ADCMPDR0 value < A/D converted value.." bitfld.word 0x4 8. "CMPLCHA08,Comparison condition of AN008" "0: ADCMPDR0 value > A/D converted value..,1: ADCMPDR0 value < A/D converted value.." newline bitfld.word 0x4 7. "CMPLCHA07,Comparison condition of AN007" "0: ADCMPDR0 value > A/D converted value..,1: ADCMPDR0 value < A/D converted value.." bitfld.word 0x4 6. "CMPLCHA06,Comparison condition of AN006" "0: ADCMPDR0 value > A/D converted value..,1: ADCMPDR0 value < A/D converted value.." newline bitfld.word 0x4 5. "CMPLCHA05,Comparison condition of AN005" "0: ADCMPDR0 value > A/D converted value..,1: ADCMPDR0 value < A/D converted value.." bitfld.word 0x4 4. "CMPLCHA04,Comparison condition of AN004" "0: ADCMPDR0 value > A/D converted value..,1: ADCMPDR0 value < A/D converted value.." newline bitfld.word 0x4 3. "CMPLCHA03,Comparison condition of AN003" "0: ADCMPDR0 value > A/D converted value..,1: ADCMPDR0 value < A/D converted value.." bitfld.word 0x4 2. "CMPLCHA02,Comparison condition of AN002" "0: ADCMPDR0 value > A/D converted value..,1: ADCMPDR0 value < A/D converted value.." newline bitfld.word 0x4 1. "CMPLCHA01,Comparison condition of AN001" "0: ADCMPDR0 value > A/D converted value..,1: ADCMPDR0 value < A/D converted value.." bitfld.word 0x4 0. "CMPLCHA00,Comparison condition of AN000" "0: ADCMPDR0 value > A/D converted value..,1: ADCMPDR0 value < A/D converted value.." line.word 0x6 "ADCMPLR1,A/D Compare Function Window A Comparison Condition Setting Register 1" hexmask.word.byte 0x6 12.--15. 1. "Reserved,These bits are read as 0000. The write value should be 0000." bitfld.word 0x6 11. "CMPLCHA27,Comparison condition of AN027" "0: ADCMPDR0 value > A/D converted value..,1: ADCMPDR0 value < A/D converted value.." newline bitfld.word 0x6 10. "CMPLCHA26,Comparison condition of AN026" "0: ADCMPDR0 value > A/D converted value..,1: ADCMPDR0 value < A/D converted value.." bitfld.word 0x6 9. "CMPLCHA25,Comparison condition of AN025" "0: ADCMPDR0 value > A/D converted value..,1: ADCMPDR0 value < A/D converted value.." newline bitfld.word 0x6 8. "CMPLCHA24,Comparison condition of AN024" "0: ADCMPDR0 value > A/D converted value..,1: ADCMPDR0 value < A/D converted value.." bitfld.word 0x6 7. "CMPLCHA23,Comparison condition of AN023" "0: ADCMPDR0 value > A/D converted value..,1: ADCMPDR0 value < A/D converted value.." newline bitfld.word 0x6 6. "CMPLCHA22,Comparison condition of AN022" "0: ADCMPDR0 value > A/D converted value..,1: ADCMPDR0 value < A/D converted value.." bitfld.word 0x6 5. "CMPLCHA21,Comparison condition of AN021" "0: ADCMPDR0 value > A/D converted value..,1: ADCMPDR0 value < A/D converted value.." newline bitfld.word 0x6 4. "CMPLCHA20,Comparison condition of AN020" "0: ADCMPDR0 value > A/D converted value..,1: ADCMPDR0 value < A/D converted value.." bitfld.word 0x6 3. "CMPLCHA19,Comparison condition of AN019" "0: ADCMPDR0 value > A/D converted value..,1: ADCMPDR0 value < A/D converted value.." newline bitfld.word 0x6 2. "CMPLCHA18,Comparison condition of AN018" "0: ADCMPDR0 value > A/D converted value..,1: ADCMPDR0 value < A/D converted value.." bitfld.word 0x6 1. "CMPLCHA17,Comparison condition of AN017" "0: ADCMPDR0 value > A/D converted value..,1: ADCMPDR0 value < A/D converted value.." newline bitfld.word 0x6 0. "CMPLCHA16,Comparison condition of AN016" "0: ADCMPDR0 value > A/D converted value..,1: ADCMPDR0 value < A/D converted value.." line.word 0x8 "ADCMPDR0,A/D Compare Function Window A Lower-Side Level Setting Register" hexmask.word 0x8 0.--15. 1. "ADCMPDR0,The ADCMPDR0 register sets the reference data when the compare window A function is used. ADCMPDR0 sets the lower-side level of window A." line.word 0xA "ADCMPDR1,A/D Compare Function Window A Upper-Side Level Setting Register" hexmask.word 0xA 0.--15. 1. "ADCMPDR1,The ADCMPDR1 register sets the reference data when the compare window A function is used. ADCMPDR1 sets the upper-side level of window A.." line.word 0xC "ADCMPSR0,A/D Compare Function Window A Channel Status Register 0" bitfld.word 0xC 15. "CMPSTCHA15,Compare window A flag of AN015" "0: Comparison conditions are not met.,1: Comparison conditions are met." bitfld.word 0xC 14. "CMPSTCHA14,Compare window A flag of AN014" "0: Comparison conditions are not met.,1: Comparison conditions are met." newline bitfld.word 0xC 13. "CMPSTCHA13,Compare window A flag of AN013" "0: Comparison conditions are not met.,1: Comparison conditions are met." bitfld.word 0xC 12. "CMPSTCHA12,Compare window A flag of AN012" "0: Comparison conditions are not met.,1: Comparison conditions are met." newline bitfld.word 0xC 11. "CMPSTCHA11,Compare window A flag of AN011" "0: Comparison conditions are not met.,1: Comparison conditions are met." bitfld.word 0xC 10. "CMPSTCHA10,Compare window A flag of AN010" "0: Comparison conditions are not met.,1: Comparison conditions are met." newline bitfld.word 0xC 9. "CMPSTCHA09,Compare window A flag of AN009" "0: Comparison conditions are not met.,1: Comparison conditions are met." bitfld.word 0xC 8. "CMPSTCHA08,Compare window A flag of AN008" "0: Comparison conditions are not met.,1: Comparison conditions are met." newline bitfld.word 0xC 7. "CMPSTCHA07,Compare window A flag of AN007" "0: Comparison conditions are not met.,1: Comparison conditions are met." bitfld.word 0xC 6. "CMPSTCHA06,Compare window A flag of AN006" "0: Comparison conditions are not met.,1: Comparison conditions are met." newline bitfld.word 0xC 5. "CMPSTCHA05,Compare window A flag of AN005" "0: Comparison conditions are not met.,1: Comparison conditions are met." bitfld.word 0xC 4. "CMPSTCHA04,Compare window A flag of AN004" "0: Comparison conditions are not met.,1: Comparison conditions are met." newline bitfld.word 0xC 3. "CMPSTCHA03,Compare window A flag of AN003" "0: Comparison conditions are not met.,1: Comparison conditions are met." bitfld.word 0xC 2. "CMPSTCHA02,Compare window A flag of AN002" "0: Comparison conditions are not met.,1: Comparison conditions are met." newline bitfld.word 0xC 1. "CMPSTCHA01,Compare window A flag of AN001" "0: Comparison conditions are not met.,1: Comparison conditions are met." bitfld.word 0xC 0. "CMPSTCHA00,Compare window A flag of AN000" "0: Comparison conditions are not met.,1: Comparison conditions are met." line.word 0xE "ADCMPSR1,A/D Compare Function Window A Channel Status Register 1" hexmask.word.byte 0xE 12.--15. 1. "Reserved,These bits are read as 0000. The write value should be 0000." bitfld.word 0xE 11. "CMPSTCHA27,Compare window A flag of AN027" "0: Comparison conditions are not met.,1: Comparison conditions are met." newline bitfld.word 0xE 10. "CMPSTCHA26,Compare window A flag of AN026" "0: Comparison conditions are not met.,1: Comparison conditions are met." bitfld.word 0xE 9. "CMPSTCHA25,Compare window A flag of AN025" "0: Comparison conditions are not met.,1: Comparison conditions are met." newline bitfld.word 0xE 8. "CMPSTCHA24,Compare window A flag of AN024" "0: Comparison conditions are not met.,1: Comparison conditions are met." bitfld.word 0xE 7. "CMPSTCHA23,Compare window A flag of AN023" "0: Comparison conditions are not met.,1: Comparison conditions are met." newline bitfld.word 0xE 6. "CMPSTCHA22,Compare window A flag of AN022" "0: Comparison conditions are not met.,1: Comparison conditions are met." bitfld.word 0xE 5. "CMPSTCHA21,Compare window A flag of AN021" "0: Comparison conditions are not met.,1: Comparison conditions are met." newline bitfld.word 0xE 4. "CMPSTCHA20,Compare window A flag of AN020" "0: Comparison conditions are not met.,1: Comparison conditions are met." bitfld.word 0xE 3. "CMPSTCHA19,Compare window A flag of AN019" "0: Comparison conditions are not met.,1: Comparison conditions are met." newline bitfld.word 0xE 2. "CMPSTCHA18,Compare window A flag of AN018" "0: Comparison conditions are not met.,1: Comparison conditions are met." bitfld.word 0xE 1. "CMPSTCHA17,Compare window A flag of AN017" "0: Comparison conditions are not met.,1: Comparison conditions are met." newline bitfld.word 0xE 0. "CMPSTCHA16,Compare window A flag of AN016" "0: Comparison conditions are not met.,1: Comparison conditions are met." group.byte 0xA4++0x0 line.byte 0x0 "ADCMPSER,A/D Compare Function Window A Extended Input Channel Status Register" hexmask.byte 0x0 2.--7. 1. "Reserved,These bits are read as 000000. The write value should be 000000." bitfld.byte 0x0 1. "CMPSTOCA,Compare Window A Internal Reference Voltage Compare Flag When window A operation is enabled (ADCMPCR.CMPAE = 1b) this bit indicates the temperature sensor output comparison result. When window A operation is disabled (ADCMPCR.CMPAE = 0b) .." "0: Comparison conditions are not met.,1: Comparison conditions are met." newline bitfld.byte 0x0 0. "CMPSTTSA,Compare Window A Temperature Sensor Output Compare Flag When window A operation is enabled (ADCMPCR.CMPAE = 1b) this bit indicates the temperature sensor output comparison result. When window A operation is disabled (ADCMPCR.CMPAE = 0b) .." "0: Comparison conditions are not met.,1: Comparison conditions are met." group.byte 0xA6++0x0 line.byte 0x0 "ADCMPBNSR,A/D Compare Function Window B Channel Selection Register" bitfld.byte 0x0 7. "CMPLB,Compare window B Compare condition setting bit." "0: CMPLLB value > A/D converted value..,1: CMPLLB value < A/D converted.." bitfld.byte 0x0 6. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline hexmask.byte 0x0 0.--5. 1. "CMPCHB,Compare window B channel selection bit.The channel that compares it on the condition of compare window B is selected." group.word 0xA8++0x3 line.word 0x0 "ADWINLLB,A/D Compare Function Window B Lower-Side Level Setting Register" hexmask.word 0x0 0.--15. 1. "ADWINLLB,This register is used to compare A window function is used to set the lower level of the window B." line.word 0x2 "ADWINULB,A/D Compare Function Window B Upper-Side Level Setting Register" hexmask.word 0x2 0.--15. 1. "ADWINULB,This register is used to compare A window function is used to set the higher level of the window B." group.byte 0xAC++0x0 line.byte 0x0 "ADCMPBSR,A/D Compare Function Window B Status Register" hexmask.byte 0x0 1.--7. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.byte 0x0 0. "CMPSTB,Compare window B flag.It is a status flag that shows the comparative result of CH (AN000-AN027 temperature sensor and internal reference voltage) made the object of window B relation condition." "0: AN027,1: Comparison conditions are met." group.byte 0xDD++0x2 line.byte 0x0 "ADSSTRL,A/D Sampling State Register L" hexmask.byte 0x0 0.--7. 1. "SST,Sampling Time Setting (AN016-AN027)" line.byte 0x1 "ADSSTRT,A/D Sampling State Register T" hexmask.byte 0x1 0.--7. 1. "SST,Sampling Time Setting (temperature sensor output)" line.byte 0x2 "ADSSTRO,A/D Sampling State Register O" hexmask.byte 0x2 0.--7. 1. "SST,Sampling Time Setting (Internal reference voltage)" repeat 16. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2+0xE0)++0x0 line.byte 0x0 "ADSSTR$1,A/D Sampling State Register %s" hexmask.byte 0x0 0.--7. 1. "SST,Sampling time setting" repeat.end tree.end tree "AGT (Asynchronous General Purpose Timer)" base ad:0x0 tree "AGT0" base ad:0x40084000 group.word 0x0++0x5 line.word 0x0 "AGT,AGT Counter Register" hexmask.word 0x0 0.--15. 1. "AGT,16bit counter and reload registerNOTE : When 1 is written to the TSTOP bit in the AGTCRn register the 16-bit counter is forcibly stopped and set to FFFFH." line.word 0x2 "AGTCMA,AGT Compare Match A Register" hexmask.word 0x2 0.--15. 1. "AGTCMA,AGT Compare Match A data is stored.NOTE : When 1 is written to the TSTOP bit in the AGTCRn register set to FFFFH" line.word 0x4 "AGTCMB,AGT Compare Match B Register" hexmask.word 0x4 0.--15. 1. "AGTCMB,AGT Compare Match B data is stored.NOTE : When 1 is written to the TSTOP bit in the AGTCR register set to FFFFH" group.byte 0x8++0x2 line.byte 0x0 "AGTCR,AGT Control Register" bitfld.byte 0x0 7. "TCMBF,Compare match B flag" "0: No match,1: Match." bitfld.byte 0x0 6. "TCMAF,Compare match A flag" "0: No match,1: Match." newline bitfld.byte 0x0 5. "TUNDF,Underflow flag" "0: No match,1: Match." bitfld.byte 0x0 4. "TEDGF,Active edge judgment flag" "0: No active edge received,1: Active edge received." newline bitfld.byte 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 2. "TSTOP,AGT count forced stop" "0: Writing is invalid,1: The count is forcibly stopped." newline rbitfld.byte 0x0 1. "TCSTF,AGT count status flag" "0: Count stops,1: Count in progress." bitfld.byte 0x0 0. "TSTART,AGT count start" "0: Count stops,1: Count starts." line.byte 0x1 "AGTMR1,AGT Mode Register 1" bitfld.byte 0x1 7. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x1 4.--6. "TCK,Count source" "0: settings are prohibited.,1: PCLKB/8,?,?,?,?,?,?" newline bitfld.byte 0x1 3. "TEDGPL,Edge polarity" "0: Single-edge,1: Both-edge." bitfld.byte 0x1 0.--2. "TMOD,Operating mode" "0: settings are prohibited,1: Pulse output mode,?,?,?,?,?,?" line.byte 0x2 "AGTMR2,AGT Mode Register 2" bitfld.byte 0x2 7. "LPM,Low Power Mode" "0: Normal mode,1: Low Power mode" hexmask.byte 0x2 3.--6. 1. "Reserved,These bits are read as 0000. The write value should be 0000." newline bitfld.byte 0x2 0.--2. "CKS,AGTLCLK/AGTSCLK count source clock frequency division ratio" "0: 1/1,1: 1/2,?,?,?,?,?,?" group.byte 0xC++0x3 line.byte 0x0 "AGTIOC,AGT I/O Control Register" bitfld.byte 0x0 6.--7. "TIOGT,Count control" "0: settings are prohibited.,1: Event is counted during polarity period..,?,?" bitfld.byte 0x0 4.--5. "TIPF,Input filter" "0: No filter,1: Filter sampled at PCLKB,?,?" newline bitfld.byte 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 2. "TOE,AGTOn output enable" "0: AGTOn output disabled,1: AGTOn output enabled." newline bitfld.byte 0x0 1. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 0. "TEDGSEL,I/O polarity switchFunction varies depending on the operating mode." "0,1" line.byte 0x1 "AGTISR,AGT Event Pin Select Register" hexmask.byte 0x1 3.--7. 1. "Reserved,These bits are read as 00000. The write value should be 00000." bitfld.byte 0x1 2. "EEPS,AGTEE polarty selection" "0: An event is counted during the low-level period,1: An event is counted during the high-level period" newline bitfld.byte 0x1 0.--1. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" line.byte 0x2 "AGTCMSR,AGT Compare Match Function Select Register" bitfld.byte 0x2 7. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x2 6. "TOPOLB,AGTOB polarity select" "0: AGTOB Output is started at low,1: AGTOB Output is started at high" newline bitfld.byte 0x2 5. "TOEB,AGTOB output enable" "0: AGTOB output disabled (port),1: AGTOB output enabled" bitfld.byte 0x2 4. "TCMEB,Compare match B register enable" "0: Disable compare match B register,1: Enable compare match B register" newline bitfld.byte 0x2 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x2 2. "TOPOLA,AGTOA polarity select" "0: AGTOA Output is started at low,1: AGTOA Output is started at high" newline bitfld.byte 0x2 1. "TOEA,AGTOA output enable" "0: AGTOA output disabled (port),1: AGTOA output enabled" bitfld.byte 0x2 0. "TCMEA,Compare match A register enable" "0: Disable compare match A register,1: Enable compare match A register" line.byte 0x3 "AGTIOSEL,AGT Pin Select Register" bitfld.byte 0x3 5.--7. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.byte 0x3 4. "TIES,AGTIO input enable" "0: External event input is disabled during Software..,1: External event input is enabled during Software.." newline bitfld.byte 0x3 2.--3. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.byte 0x3 0.--1. "SEL,AGTIO pin select" "0: Select the AGTIOn except for below pins,1: Setting prohibited,?,?" tree.end tree "AGT1" base ad:0x40084100 group.word 0x0++0x5 line.word 0x0 "AGT,AGT Counter Register" hexmask.word 0x0 0.--15. 1. "AGT,16bit counter and reload registerNOTE : When 1 is written to the TSTOP bit in the AGTCRn register the 16-bit counter is forcibly stopped and set to FFFFH." line.word 0x2 "AGTCMA,AGT Compare Match A Register" hexmask.word 0x2 0.--15. 1. "AGTCMA,AGT Compare Match A data is stored.NOTE : When 1 is written to the TSTOP bit in the AGTCRn register set to FFFFH" line.word 0x4 "AGTCMB,AGT Compare Match B Register" hexmask.word 0x4 0.--15. 1. "AGTCMB,AGT Compare Match B data is stored.NOTE : When 1 is written to the TSTOP bit in the AGTCR register set to FFFFH" group.byte 0x8++0x2 line.byte 0x0 "AGTCR,AGT Control Register" bitfld.byte 0x0 7. "TCMBF,Compare match B flag" "0: No match,1: Match." bitfld.byte 0x0 6. "TCMAF,Compare match A flag" "0: No match,1: Match." newline bitfld.byte 0x0 5. "TUNDF,Underflow flag" "0: No match,1: Match." bitfld.byte 0x0 4. "TEDGF,Active edge judgment flag" "0: No active edge received,1: Active edge received." newline bitfld.byte 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 2. "TSTOP,AGT count forced stop" "0: Writing is invalid,1: The count is forcibly stopped." newline rbitfld.byte 0x0 1. "TCSTF,AGT count status flag" "0: Count stops,1: Count in progress." bitfld.byte 0x0 0. "TSTART,AGT count start" "0: Count stops,1: Count starts." line.byte 0x1 "AGTMR1,AGT Mode Register 1" bitfld.byte 0x1 7. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x1 4.--6. "TCK,Count source" "0: settings are prohibited.,1: PCLKB/8,?,?,?,?,?,?" newline bitfld.byte 0x1 3. "TEDGPL,Edge polarity" "0: Single-edge,1: Both-edge." bitfld.byte 0x1 0.--2. "TMOD,Operating mode" "0: settings are prohibited,1: Pulse output mode,?,?,?,?,?,?" line.byte 0x2 "AGTMR2,AGT Mode Register 2" bitfld.byte 0x2 7. "LPM,Low Power Mode" "0: Normal mode,1: Low Power mode" hexmask.byte 0x2 3.--6. 1. "Reserved,These bits are read as 0000. The write value should be 0000." newline bitfld.byte 0x2 0.--2. "CKS,AGTLCLK/AGTSCLK count source clock frequency division ratio" "0: 1/1,1: 1/2,?,?,?,?,?,?" group.byte 0xC++0x3 line.byte 0x0 "AGTIOC,AGT I/O Control Register" bitfld.byte 0x0 6.--7. "TIOGT,Count control" "0: settings are prohibited.,1: Event is counted during polarity period..,?,?" bitfld.byte 0x0 4.--5. "TIPF,Input filter" "0: No filter,1: Filter sampled at PCLKB,?,?" newline bitfld.byte 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 2. "TOE,AGTOn output enable" "0: AGTOn output disabled,1: AGTOn output enabled." newline bitfld.byte 0x0 1. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 0. "TEDGSEL,I/O polarity switchFunction varies depending on the operating mode." "0,1" line.byte 0x1 "AGTISR,AGT Event Pin Select Register" hexmask.byte 0x1 3.--7. 1. "Reserved,These bits are read as 00000. The write value should be 00000." bitfld.byte 0x1 2. "EEPS,AGTEE polarty selection" "0: An event is counted during the low-level period,1: An event is counted during the high-level period" newline bitfld.byte 0x1 0.--1. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" line.byte 0x2 "AGTCMSR,AGT Compare Match Function Select Register" bitfld.byte 0x2 7. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x2 6. "TOPOLB,AGTOB polarity select" "0: AGTOB Output is started at low,1: AGTOB Output is started at high" newline bitfld.byte 0x2 5. "TOEB,AGTOB output enable" "0: AGTOB output disabled (port),1: AGTOB output enabled" bitfld.byte 0x2 4. "TCMEB,Compare match B register enable" "0: Disable compare match B register,1: Enable compare match B register" newline bitfld.byte 0x2 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x2 2. "TOPOLA,AGTOA polarity select" "0: AGTOA Output is started at low,1: AGTOA Output is started at high" newline bitfld.byte 0x2 1. "TOEA,AGTOA output enable" "0: AGTOA output disabled (port),1: AGTOA output enabled" bitfld.byte 0x2 0. "TCMEA,Compare match A register enable" "0: Disable compare match A register,1: Enable compare match A register" line.byte 0x3 "AGTIOSEL,AGT Pin Select Register" bitfld.byte 0x3 5.--7. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.byte 0x3 4. "TIES,AGTIO input enable" "0: External event input is disabled during Software..,1: External event input is enabled during Software.." newline bitfld.byte 0x3 2.--3. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.byte 0x3 0.--1. "SEL,AGTIO pin select" "0: Select the AGTIOn except for below pins,1: Setting prohibited,?,?" tree.end tree.end tree "BUS (BUS Control)" base ad:0x40003000 repeat 4. (increment 0x0 0x1)(increment 0x0 0x10) group.word ($2+0x2)++0x1 line.word 0x0 "CS$1MOD,CS%s Mode Register" bitfld.word 0x0 15. "PRDMOD,Page Read Access Mode Select" "0: Normal access compatible mode,1: External data read continuous assertion mode" hexmask.word.byte 0x0 10.--14. 1. "Reserved,These bits are read as 00000. The write value should be 00000." newline bitfld.word 0x0 9. "PWENB,Page Write Access Enable" "0: Disabled,1: Enabled" bitfld.word 0x0 8. "PRENB,Page Read Access Enable" "0: Disabled,1: Enabled" newline hexmask.word.byte 0x0 4.--7. 1. "Reserved,These bits are read as 0000. The write value should be 0000." bitfld.word 0x0 3. "EWENB,External Wait Enable" "0: Disabled,1: Enabled" newline bitfld.word 0x0 1.--2. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.word 0x0 0. "WRMOD,Write Access Mode Select" "0: Byte strobe mode,1: Single write strobe mode" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x10) group.long ($2+0x4)++0x3 line.long 0x0 "CS$1WCR1,CS%s Wait Control Register 1" bitfld.long 0x0 29.--31. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "CSRWAIT,Normal Read Cycle Wait Select" newline bitfld.long 0x0 21.--23. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "CSWWAIT,Normal Write Cycle Wait Select" newline hexmask.long.byte 0x0 11.--15. 1. "Reserved,These bits are read as 00000. The write value should be 00000." bitfld.long 0x0 8.--10. "CSPRWAIT,Page Read Cycle Wait SelectNOTE: The CSPRWAIT value is valid only when the PRENB bit in CSnMOD is set to 1." "0: Wait with a length of CSPRWAIT clock cycle is..,?,?,?,?,?,?,?" newline hexmask.long.byte 0x0 3.--7. 1. "Reserved,These bits are read as 00000. The write value should be 00000." bitfld.long 0x0 0.--2. "CSPWWAIT,Page Write Cycle Wait SelectNOTE: The CSPWWAIT value is valid only when the PWENB bit in CSnMOD is set to 1." "0: Wait with a length of CSPWWAIT clock cycle is..,?,?,?,?,?,?,?" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x10) group.long ($2+0x8)++0x3 line.long 0x0 "CS$1WCR2,CS%s Wait Control Register 2" bitfld.long 0x0 31. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 28.--30. "CSON,CS Assert Wait Select" "0: Wait with a length of CSON clock cycle is..,?,?,?,?,?,?,?" newline bitfld.long 0x0 27. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 24.--26. "WDON,Write Data Output Wait Select" "0: Wait with a length of WDON clock cycle is..,?,?,?,?,?,?,?" newline bitfld.long 0x0 23. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 20.--22. "WRON,WR Assert Wait Select" "0: Wait with a length of WRON clock cycle is..,?,?,?,?,?,?,?" newline bitfld.long 0x0 19. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 16.--18. "RDON,RD Assert Wait Select" "0: Wait with a length of RDON clock cycle is..,?,?,?,?,?,?,?" newline bitfld.long 0x0 14.--15. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.long 0x0 12.--13. "AWAIT,Address Cycle Wait Select" "0: Wait with a length of AWAIT clock cycle is..,?,?,?" newline bitfld.long 0x0 11. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 8.--10. "WDOFF,Write Data Output Extension Cycle Select" "0: Wait with a length of WDOFF clock cycle is..,?,?,?,?,?,?,?" newline bitfld.long 0x0 7. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 4.--6. "CSWOFF,Write-Access CS Extension Cycle Select" "0: Wait with a length of CSWOFF clock cycle is..,?,?,?,?,?,?,?" newline bitfld.long 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 0.--2. "CSROFF,Read-Access CS Extension Cycle Select" "0: Wait with a length of CSROFF clock cycle is..,?,?,?,?,?,?,?" repeat.end group.word 0x802++0x1 line.word 0x0 "CS0CR,CS0 Control Register" bitfld.word 0x0 13.--15. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.word 0x0 12. "MPXEN,Address/Data Multiplexed I/O Interface Select" "0: Separate bus interface is selected for area 0.,1: Address/data multiplexed I/O interface is.." newline bitfld.word 0x0 9.--11. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.word 0x0 8. "EMODE,Endian Mode" "0: Little Endian,1: Big Endian" newline bitfld.word 0x0 6.--7. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.word 0x0 4.--5. "BSIZE,External Bus Width Select" "0: 16-bit bus space,1: Setting prohibited,?,?" newline bitfld.word 0x0 1.--3. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.word 0x0 0. "EXENB,Operation Enable" "0: Disabled,1: Enabled" repeat 4. (increment 0x0 0x1)(increment 0x0 0x10) group.word ($2+0x80A)++0x1 line.word 0x0 "CS$1REC,CS%s Recovery Cycle Register" hexmask.word.byte 0x0 12.--15. 1. "Reserved,These bits are read as 0000. The write value should be 0000." hexmask.word.byte 0x0 8.--11. 1. "WRCV,Write Recovery" newline hexmask.word.byte 0x0 4.--7. 1. "Reserved,These bits are read as 0000. The write value should be 0000." hexmask.word.byte 0x0 0.--3. 1. "RRCV,Read Recovery" repeat.end repeat 3. (increment 0x0 0x1)(increment 0x0 0x10) group.word ($2+0x812)++0x1 line.word 0x0 "CS$1CR,CS%s Control Register" bitfld.word 0x0 13.--15. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.word 0x0 12. "MPXEN,Address/Data Multiplexed I/O Interface Select" "0: Separate bus interface is selected for area 0.,1: Address/data multiplexed I/O interface is.." newline bitfld.word 0x0 9.--11. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.word 0x0 8. "EMODE,Endian Mode" "0: Little Endian,1: Big Endian" newline bitfld.word 0x0 6.--7. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.word 0x0 4.--5. "BSIZE,External Bus Width Select" "0: 16-bit bus space,1: Setting prohibited,?,?" newline bitfld.word 0x0 1.--3. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.word 0x0 0. "EXENB,Operation Enable" "0: Disabled,1: Enabled" repeat.end group.word 0x880++0x1 line.word 0x0 "CSRECEN,CS Recovery Cycle Insertion Enable Register" bitfld.word 0x0 15. "RECVENM7,Multiplexed Bus Recovery Cycle Insertion Enable 7" "0: Recovery cycle insertion is disabled.,1: Recovery cycle insertion is enabled." bitfld.word 0x0 14. "RECVENM6,Multiplexed Bus Recovery Cycle Insertion Enable 6" "0: Recovery cycle insertion is disabled.,1: Recovery cycle insertion is enabled." newline bitfld.word 0x0 13. "RECVENM5,Multiplexed Bus Recovery Cycle Insertion Enable 5" "0: Recovery cycle insertion is disabled.,1: Recovery cycle insertion is enabled." bitfld.word 0x0 12. "RECVENM4,Multiplexed Bus Recovery Cycle Insertion Enable 4" "0: Recovery cycle insertion is disabled.,1: Recovery cycle insertion is enabled." newline bitfld.word 0x0 11. "RECVENM3,Multiplexed Bus Recovery Cycle Insertion Enable 3" "0: Recovery cycle insertion is disabled.,1: Recovery cycle insertion is enabled." bitfld.word 0x0 10. "RECVENM2,Multiplexed Bus Recovery Cycle Insertion Enable 2" "0: Recovery cycle insertion is disabled.,1: Recovery cycle insertion is enabled." newline bitfld.word 0x0 9. "RECVENM1,Multiplexed Bus Recovery Cycle Insertion Enable 1" "0: Recovery cycle insertion is disabled.,1: Recovery cycle insertion is enabled." bitfld.word 0x0 8. "RECVENM0,Multiplexed Bus Recovery Cycle Insertion Enable 0" "0: Recovery cycle insertion is disabled.,1: Recovery cycle insertion is enabled." newline bitfld.word 0x0 7. "RECVEN7,Separate Bus Recovery Cycle Insertion Enable 7" "0: Disabled.,1: Enabled." bitfld.word 0x0 6. "RECVEN6,Separate Bus Recovery Cycle Insertion Enable 6" "0: Disabled.,1: Enabled." newline bitfld.word 0x0 5. "RECVEN5,Separate Bus Recovery Cycle Insertion Enable 5" "0: Disabled.,1: Enabled." bitfld.word 0x0 4. "RECVEN4,Separate Bus Recovery Cycle Insertion Enable 4" "0: Disabled.,1: Enabled." newline bitfld.word 0x0 3. "RECVEN3,Separate Bus Recovery Cycle Insertion Enable 3" "0: Disabled.,1: Enabled." bitfld.word 0x0 2. "RECVEN2,Separate Bus Recovery Cycle Insertion Enable 2" "0: Disabled.,1: Enabled." newline bitfld.word 0x0 1. "RECVEN1,Separate Bus Recovery Cycle Insertion Enable 1" "0: Disabled.,1: Enabled." bitfld.word 0x0 0. "RECVEN0,Separate Bus Recovery Cycle Insertion Enable 0" "0: Disabled.,1: Enabled." repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x1000)++0x1 line.word 0x0 "BUSMCNT$1,Master Bus Control Register %s" bitfld.word 0x0 15. "IERES,Ignore Error Responses" "0: A bus error is reported,1: A bus error is not reported." hexmask.word 0x0 0.--14. 1. "Reserved,These bits are read as 000000000000000. The write value should be 000000000000000." repeat.end group.word 0x1100++0x1 line.word 0x0 "BUSSCNTFLI,Slave Bus Control Register FLI" hexmask.word 0x0 6.--15. 1. "Reserved,These bits are read as 0000000000. The write value should be 0000000000." bitfld.word 0x0 4.--5. "ARBMET,Arbitration MethodSpecify the priority between groups" "0: Setting prohibited,1: round-robin,?,?" newline hexmask.word.byte 0x0 0.--3. 1. "Reserved,These bits are read as 0000. The write value should be 0000." repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x1108)++0x1 line.word 0x0 "BUSSCNT$1,Slave Bus Control Register %s" hexmask.word 0x0 6.--15. 1. "Reserved,These bits are read as 0000000000. The write value should be 0000000000." bitfld.word 0x0 4.--5. "ARBMET,Arbitration MethodSpecify the priority between groups" "0: Setting prohibited,1: round-robin,?,?" newline hexmask.word.byte 0x0 0.--3. 1. "Reserved,These bits are read as 0000. The write value should be 0000." repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x1114)++0x1 line.word 0x0 "BUSSCNT$1,Slave Bus Control Register %s" hexmask.word 0x0 6.--15. 1. "Reserved,These bits are read as 0000000000. The write value should be 0000000000." bitfld.word 0x0 4.--5. "ARBMET,Arbitration MethodSpecify the priority between groups" "0: Setting prohibited,1: round-robin,?,?" newline hexmask.word.byte 0x0 0.--3. 1. "Reserved,These bits are read as 0000. The write value should be 0000." repeat.end group.word 0x1128++0x1 line.word 0x0 "BUSSCNTP6B,Slave Bus Control Register P6B" hexmask.word 0x0 6.--15. 1. "Reserved,These bits are read as 0000000000. The write value should be 0000000000." bitfld.word 0x0 4.--5. "ARBMET,Arbitration MethodSpecify the priority between groups" "0: Setting prohibited,1: round-robin,?,?" newline hexmask.word.byte 0x0 0.--3. 1. "Reserved,These bits are read as 0000. The write value should be 0000." repeat 3. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x1130)++0x1 line.word 0x0 "BUSSCNT$1,Slave Bus Control Register %s" hexmask.word 0x0 6.--15. 1. "Reserved,These bits are read as 0000000000. The write value should be 0000000000." bitfld.word 0x0 4.--5. "ARBMET,Arbitration MethodSpecify the priority between groups" "0: Setting prohibited,1: round-robin,?,?" newline hexmask.word.byte 0x0 0.--3. 1. "Reserved,These bits are read as 0000. The write value should be 0000." repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x10) rgroup.long ($2+0x1800)++0x3 line.long 0x0 "BUS$1ERRADD,Bus Error Address Register %s" hexmask.long 0x0 0.--31. 1. "BERAD,Bus Error AddressWhen a bus error occurs It stores an error address." repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x10) rgroup.byte ($2+0x1804)++0x0 line.byte 0x0 "BUS$1ERRSTAT,Bus Error Status Register %s" bitfld.byte 0x0 7. "ERRSTAT,Bus Error StatusWhen bus error assert error flag occurs." "0: No bus error occurred,1: Bus error occurred." hexmask.byte 0x0 1.--6. 1. "Reserved,These bits are read as 000000." newline bitfld.byte 0x0 0. "ACCSTST,Error Access StatusThe status at the time of the error" "0: Read access,1: Write Access" repeat.end tree.end tree "CAC (Clock Frequency Accuracy Measurement Circuit)" base ad:0x40044600 group.byte 0x0++0x3 line.byte 0x0 "CACR0,CAC Control Register 0" hexmask.byte 0x0 1.--7. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.byte 0x0 0. "CFME,Clock Frequency Measurement Enable." "0: Disable,1: Enable" line.byte 0x1 "CACR1,CAC Control Register 1" bitfld.byte 0x1 6.--7. "EDGES,Valid Edge Select" "0: Rising edge,1: Falling edge,?,?" bitfld.byte 0x1 4.--5. "TCSS,Measurement Target Clock Frequency Division Ratio Select" "0: No division,1: x 1/4 clock,?,?" newline bitfld.byte 0x1 1.--3. "FMCS,Measurement Target Clock Select" "0: Main clock,1: Sub-clock,?,?,?,?,?,?" bitfld.byte 0x1 0. "CACREFE,CACREF Pin Input Enable" "0: Disable,1: Enable" line.byte 0x2 "CACR2,CAC Control Register 2" bitfld.byte 0x2 6.--7. "DFS,Digital Filter Selection" "0: Digital filtering is disabled.,1: The sampling clock for the digital filter is the..,?,?" bitfld.byte 0x2 4.--5. "RCDS,Measurement Reference Clock Frequency Division Ratio Select" "0: 1/32 clock,1: 1/128 clock,?,?" newline bitfld.byte 0x2 1.--3. "RSCS,Measurement Reference Clock Select" "0: Main clock,1: Sub-clock,?,?,?,?,?,?" bitfld.byte 0x2 0. "RPS,Reference Signal Select" "0: CACREF pin input,1: Internal clock (internally generated signal)" line.byte 0x3 "CAICR,CAC Interrupt Control Register" bitfld.byte 0x3 7. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x3 6. "OVFFCL,OVFF Clear" "0: No effect on operations,1: Clears the OVFF flag" newline bitfld.byte 0x3 5. "MENDFCL,MENDF Clear" "0: No effect on operations,1: Clears the MENDF flag" bitfld.byte 0x3 4. "FERRFCL,FERRF Clear" "0: No effect on operations,1: Clears the FERRF flag" newline bitfld.byte 0x3 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x3 2. "OVFIE,Overflow Interrupt Request Enable" "0: Disable,1: Enable" newline bitfld.byte 0x3 1. "MENDIE,Measurement End Interrupt Request Enable" "0: Disable,1: Enable" bitfld.byte 0x3 0. "FERRIE,Frequency Error Interrupt Request Enable" "0: Disable,1: Enable" rgroup.byte 0x4++0x0 line.byte 0x0 "CASTR,CAC Status Register" bitfld.byte 0x0 2. "OVFF,Counter Overflow Flag" "0: The counter has not overflowed.,1: The counter has overflowed." bitfld.byte 0x0 1. "MENDF,Measurement End Flag" "0: Measurement is in progress.,1: Measurement has ended." newline bitfld.byte 0x0 0. "FERRF,Frequency Error Flag" "0: The clock frequency is within the range..,1: The clock frequency has deviated beyond the.." group.word 0x6++0x3 line.word 0x0 "CAULVR,CAC Upper-Limit Value Setting Register" hexmask.word 0x0 0.--15. 1. "CAULVR,CAULVR is a 16-bit readable/writable register that stores the upper-limit value of the frequency." line.word 0x2 "CALLVR,CAC Lower-Limit Value Setting Register" hexmask.word 0x2 0.--15. 1. "CALLVR,CALLVR is a 16-bit readable/writable register that stores the lower-limit value of the frequency." rgroup.word 0xA++0x1 line.word 0x0 "CACNTBR,CAC Counter Buffer Register" hexmask.word 0x0 0.--15. 1. "CACNTBR,CACNTBR is a 16-bit read-only register that retains the counter value at the time a valid reference signal edge is input" tree.end tree "CAN (Controller Area Network)" base ad:0x40050000 repeat 32. (increment 0x0 0x1)(increment 0x0 0x10) group.long ($2+0x200)++0x3 line.long 0x0 "MB$1_ID,Mailbox Register" bitfld.long 0x0 31. "IDE,ID Extension" "0: Standard ID,1: Extended ID" bitfld.long 0x0 30. "RTR,Remote Transmission Request" "0: Data frame,1: Remote frame" newline bitfld.long 0x0 29. "Reserved,This bit is read as 0. The write value should be 0." "0,1" hexmask.long.word 0x0 18.--28. 1. "SID,Standard ID" newline hexmask.long.tbyte 0x0 0.--17. 1. "EID,Extended ID" repeat.end repeat 32. (increment 0x0 0x1)(increment 0x0 0x10) group.word ($2+0x204)++0x1 line.word 0x0 "MB$1_DL,Mailbox Register" hexmask.word 0x0 4.--15. 1. "Reserved,These bits are read as 000000000000. The write value should be 000000000000." hexmask.word.byte 0x0 0.--3. 1. "DLC,Data Length Code" repeat.end repeat 32. (increment 0x0 0x1)(increment 0x0 0x10) group.byte ($2+0x206)++0x0 line.byte 0x0 "MB$1_D0,Mailbox Register" hexmask.byte 0x0 0.--7. 1. "DATA0,Data Bytes 0.DATA0 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first and transmission or reception starts from bit 7." repeat.end repeat 32. (increment 0x0 0x1)(increment 0x0 0x10) group.byte ($2+0x207)++0x0 line.byte 0x0 "MB$1_D1,Mailbox Register" hexmask.byte 0x0 0.--7. 1. "DATA1,Data Bytes 1DATA1 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first and transmission or reception starts from bit 7." repeat.end repeat 32. (increment 0x0 0x1)(increment 0x0 0x10) group.byte ($2+0x208)++0x0 line.byte 0x0 "MB$1_D2,Mailbox Register" hexmask.byte 0x0 0.--7. 1. "DATA2,Data Bytes 2DATA2 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first and transmission or reception starts from bit 7." repeat.end repeat 32. (increment 0x0 0x1)(increment 0x0 0x10) group.byte ($2+0x209)++0x0 line.byte 0x0 "MB$1_D3,Mailbox Register" hexmask.byte 0x0 0.--7. 1. "DATA3,Data Bytes 3DATA3 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first and transmission or reception starts from bit 7." repeat.end repeat 32. (increment 0x0 0x1)(increment 0x0 0x10) group.byte ($2+0x20A)++0x0 line.byte 0x0 "MB$1_D4,Mailbox Register" hexmask.byte 0x0 0.--7. 1. "DATA4,Data Bytes 4DATA4 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first and transmission or reception starts from bit 7." repeat.end repeat 32. (increment 0x0 0x1)(increment 0x0 0x10) group.byte ($2+0x20B)++0x0 line.byte 0x0 "MB$1_D5,Mailbox Register" hexmask.byte 0x0 0.--7. 1. "DATA5,Data Bytes 5DATA5 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first and transmission or reception starts from bit 7." repeat.end repeat 32. (increment 0x0 0x1)(increment 0x0 0x10) group.byte ($2+0x20C)++0x0 line.byte 0x0 "MB$1_D6,Mailbox Register" hexmask.byte 0x0 0.--7. 1. "DATA6,Data Bytes 6DATA6 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first and transmission or reception starts from bit 7." repeat.end repeat 32. (increment 0x0 0x1)(increment 0x0 0x10) group.byte ($2+0x20D)++0x0 line.byte 0x0 "MB$1_D7,Mailbox Register" hexmask.byte 0x0 0.--7. 1. "DATA7,Data Bytes 7DATA7 store the transmitted or received CAN message data. Transmission or reception starts from DATA0. The bit order on the CAN bus is MSB first and transmission or reception starts from bit 7." repeat.end repeat 32. (increment 0x0 0x1)(increment 0x0 0x10) group.word ($2+0x20E)++0x1 line.word 0x0 "MB$1_TS,Mailbox Register" hexmask.word.byte 0x0 8.--15. 1. "TSH,Time Stamp Lower ByteBits TSH[7:0] store the counter value of the time stamp when received messages are stored in the mailbox." hexmask.word.byte 0x0 0.--7. 1. "TSL,Time Stamp Higher ByteBits TSL[7:0] store the counter value of the time stamp when received messages are stored in the mailbox." repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x400)++0x3 line.long 0x0 "MKR[$1],Mask Register" bitfld.long 0x0 29.--31. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" hexmask.long.word 0x0 18.--28. 1. "SID,Standard ID" newline hexmask.long.tbyte 0x0 0.--17. 1. "EID,Extended ID" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x420)++0x3 line.long 0x0 "FIDCR$1,FIFO Received ID Compare Registers" bitfld.long 0x0 31. "IDE,ID Extension" "0: Standard ID,1: Extended ID" bitfld.long 0x0 30. "RTR,Remote Transmission Request" "0: Data frame,1: Remote frame" newline bitfld.long 0x0 29. "Reserved,This bit is read as 0. The write value should be 0." "0,1" hexmask.long.word 0x0 18.--28. 1. "SID,Standard ID" newline hexmask.long.tbyte 0x0 0.--17. 1. "EID,Extended ID" repeat.end group.long 0x428++0x7 line.long 0x0 "MKIVLR,Mask Invalid Register" bitfld.long 0x0 31. "MB31,mailbox 31 Mask Invalid" "0: Mask valid,1: Mask invalid" bitfld.long 0x0 30. "MB30,mailbox 30 Mask Invalid" "0: Mask valid,1: Mask invalid" newline bitfld.long 0x0 29. "MB29,mailbox 29 Mask Invalid" "0: Mask valid,1: Mask invalid" bitfld.long 0x0 28. "MB28,mailbox 28 Mask Invalid" "0: Mask valid,1: Mask invalid" newline bitfld.long 0x0 27. "MB27,mailbox 27 Mask Invalid" "0: Mask valid,1: Mask invalid" bitfld.long 0x0 26. "MB26,mailbox 26 Mask Invalid" "0: Mask valid,1: Mask invalid" newline bitfld.long 0x0 25. "MB25,mailbox 25 Mask Invalid" "0: Mask valid,1: Mask invalid" bitfld.long 0x0 24. "MB24,mailbox 24 Mask Invalid" "0: Mask valid,1: Mask invalid" newline bitfld.long 0x0 23. "MB23,mailbox 23 Mask Invalid" "0: Mask valid,1: Mask invalid" bitfld.long 0x0 22. "MB22,mailbox 22 Mask Invalid" "0: Mask valid,1: Mask invalid" newline bitfld.long 0x0 21. "MB21,mailbox 21 Mask Invalid" "0: Mask valid,1: Mask invalid" bitfld.long 0x0 20. "MB20,mailbox 20 Mask Invalid" "0: Mask valid,1: Mask invalid" newline bitfld.long 0x0 19. "MB19,mailbox 19 Mask Invalid" "0: Mask valid,1: Mask invalid" bitfld.long 0x0 18. "MB18,mailbox 18 Mask Invalid" "0: Mask valid,1: Mask invalid" newline bitfld.long 0x0 17. "MB17,mailbox 17 Mask Invalid" "0: Mask valid,1: Mask invalid" bitfld.long 0x0 16. "MB16,mailbox 16 Mask Invalid" "0: Mask valid,1: Mask invalid" newline bitfld.long 0x0 15. "MB15,mailbox 15 Mask Invalid" "0: Mask valid,1: Mask invalid" bitfld.long 0x0 14. "MB14,mailbox 14 Mask Invalid" "0: Mask valid,1: Mask invalid" newline bitfld.long 0x0 13. "MB13,mailbox 13 Mask Invalid" "0: Mask valid,1: Mask invalid" bitfld.long 0x0 12. "MB12,mailbox 12 Mask Invalid" "0: Mask valid,1: Mask invalid" newline bitfld.long 0x0 11. "MB11,mailbox 11 Mask Invalid" "0: Mask valid,1: Mask invalid" bitfld.long 0x0 10. "MB10,mailbox 10 Mask Invalid" "0: Mask valid,1: Mask invalid" newline bitfld.long 0x0 9. "MB9,mailbox 9 Mask Invalid" "0: Mask valid,1: Mask invalid" bitfld.long 0x0 8. "MB8,mailbox 8 Mask Invalid" "0: Mask valid,1: Mask invalid" newline bitfld.long 0x0 7. "MB7,mailbox 7 Mask Invalid" "0: Mask valid,1: Mask invalid" bitfld.long 0x0 6. "MB6,mailbox 6 Mask Invalid" "0: Mask valid,1: Mask invalid" newline bitfld.long 0x0 5. "MB5,mailbox 5 Mask Invalid" "0: Mask valid,1: Mask invalid" bitfld.long 0x0 4. "MB4,mailbox 4 Mask Invalid" "0: Mask valid,1: Mask invalid" newline bitfld.long 0x0 3. "MB3,mailbox 3 Mask Invalid" "0: Mask valid,1: Mask invalid" bitfld.long 0x0 2. "MB2,mailbox 2 Mask Invalid" "0: Mask valid,1: Mask invalid" newline bitfld.long 0x0 1. "MB1,mailbox 1 Mask Invalid" "0: Mask valid,1: Mask invalid" bitfld.long 0x0 0. "MB0,mailbox 0 Mask Invalid" "0: Mask valid,1: Mask invalid" line.long 0x4 "MIER,Mailbox Interrupt Enable Register" bitfld.long 0x4 31. "MB31,mailbox 31 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 30. "MB30,mailbox 30 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 29. "MB29,mailbox 29 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 28. "MB28,mailbox 28 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 27. "MB27,mailbox 27 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 26. "MB26,mailbox 26 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 25. "MB25,mailbox 25 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 24. "MB24,mailbox 24 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 23. "MB23,mailbox 23 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 22. "MB22,mailbox 22 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 21. "MB21,mailbox 21 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 20. "MB20,mailbox 20 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 19. "MB19,mailbox 19 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 18. "MB18,mailbox 18 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 17. "MB17,mailbox 17 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 16. "MB16,mailbox 16 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 15. "MB15,mailbox 15 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 14. "MB14,mailbox 14 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 13. "MB13,mailbox 13 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 12. "MB12,mailbox 12 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 11. "MB11,mailbox 11 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 10. "MB10,mailbox 10 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 9. "MB9,mailbox 9 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 8. "MB8,mailbox 8 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 7. "MB7,mailbox 7 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 6. "MB6,mailbox 6 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 5. "MB5,mailbox 5 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 4. "MB4,mailbox 4 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 3. "MB3,mailbox 3 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 2. "MB2,mailbox 2 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x4 1. "MB1,mailbox 1 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x4 0. "MB0,mailbox 0 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" group.long 0x42C++0x3 line.long 0x0 "MIER_FIFO,Mailbox Interrupt Enable Register for FIFO Mailbox Mode" bitfld.long 0x0 29. "MB29,Receive FIFO Interrupt Generation Timing Control" "0: Every time reception is completed,1: When the receive FIFO becomes buffer warning by.." bitfld.long 0x0 28. "MB28,Receive FIFO Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x0 26.--27. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.long 0x0 25. "MB25,Transmit FIFO Interrupt Generation Timing Control" "0: Every time transmission is completed,1: When the transmit FIFO becomes empty due to.." newline bitfld.long 0x0 24. "MB24,Transmit FIFO Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x0 23. "MB23,mailbox 23 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x0 22. "MB22,mailbox 22 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x0 21. "MB21,mailbox 21 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x0 20. "MB20,mailbox 20 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x0 19. "MB19,mailbox 19 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x0 18. "MB18,mailbox 18 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x0 17. "MB17,mailbox 17 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x0 16. "MB16,mailbox 16 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x0 15. "MB15,mailbox 15 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x0 14. "MB14,mailbox 14 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x0 13. "MB13,mailbox 13 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x0 12. "MB12,mailbox 12 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x0 11. "MB11,mailbox 11 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x0 10. "MB10,mailbox 10 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x0 9. "MB9,mailbox 9 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x0 8. "MB8,mailbox 8 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x0 7. "MB7,mailbox 7 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x0 6. "MB6,mailbox 6 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x0 5. "MB5,mailbox 5 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x0 4. "MB4,mailbox 4 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x0 3. "MB3,mailbox 3 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x0 2. "MB2,mailbox 2 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" bitfld.long 0x0 1. "MB1,mailbox 1 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" newline bitfld.long 0x0 0. "MB0,mailbox 0 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled" repeat 32. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2+0x820)++0x0 line.byte 0x0 "MCTL_TX[$1],Message Control Register for Transmit" bitfld.byte 0x0 7. "TRMREQ,Transmit Mailbox Request" "0: Not configured for transmission,1: Configured for transmission" bitfld.byte 0x0 6. "RECREQ,Receive Mailbox Request" "0: Not configured for reception,1: Configured for reception" newline bitfld.byte 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 4. "ONESHOT,One-Shot Enable" "0: One-shot reception or one-shot transmission..,1: One-shot reception or one-shot transmission.." newline bitfld.byte 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 2. "TRMABT,Transmission Abort Complete Flag (Transmit mailbox setting enabled)" "0: Transmission has started transmission abort..,1: Transmission abort is completed" newline rbitfld.byte 0x0 1. "TRMACTIVE,Transmission-in-Progress Status Flag (Transmit mailbox setting enabled)" "0: Transmission is pending or transmission is not..,1: From acceptance of transmission request to.." bitfld.byte 0x0 0. "SENTDATA,Transmission Complete Flag" "0: Transmission is not completed,1: Transmission is completed" repeat.end repeat 32. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2+0x820)++0x0 line.byte 0x0 "MCTL_RX[$1],Message Control Register for Receive" bitfld.byte 0x0 7. "TRMREQ,Transmit Mailbox Request" "0: Not configured for transmission,1: Configured for transmission" bitfld.byte 0x0 6. "RECREQ,Receive Mailbox Request" "0: Not configured for reception,1: Configured for reception" newline bitfld.byte 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 4. "ONESHOT,One-Shot Enable" "0: One-shot reception or one-shot transmission..,1: One-shot reception or one-shot transmission.." newline bitfld.byte 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 2. "MSGLOST,Message Lost Flag(Receive mailbox setting enabled)" "0: Message is not overwritten or overrun,1: Message is overwritten or overrun" newline rbitfld.byte 0x0 1. "INVALDATA,Reception-in-Progress Status Flag (Receive mailbox setting enabled)" "0: Message valid,1: Message being updated" bitfld.byte 0x0 0. "NEWDATA,Reception Complete Flag" "0: No data has been received or 0 is written to the..,1: A new message is being stored or has been stored.." repeat.end group.word 0x840++0x1 line.word 0x0 "CTLR,Control Register" bitfld.word 0x0 14.--15. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.word 0x0 13. "RBOC,Forcible Return From Bus-Off" "0: Nothing occurred,1: Forcible return from bus-off" newline bitfld.word 0x0 11.--12. "BOM,Bus-Off Recovery Mode by a program request" "0: Normal mode (ISO11898-1 compliant),1: Entry to CAN halt mode automatically at bus-off..,?,?" bitfld.word 0x0 10. "SLPM,CAN Sleep Mode" "0: Other than CAN sleep mode,1: CAN sleep mode" newline bitfld.word 0x0 8.--9. "CANM,CAN Operating Mode Select" "0: CAN operation mode,1: CAN reset mode,?,?" bitfld.word 0x0 6.--7. "TSPS,Time Stamp Prescaler Select" "0: Every bit time,1: Every 2-bit time,?,?" newline bitfld.word 0x0 5. "TSRC,Time Stamp Counter Reset Command" "0: Nothing occurred,1: Reset" bitfld.word 0x0 4. "TPM,Transmission Priority Mode Select" "0: ID priority transmit mode,1: Mailbox number priority transmit mode" newline bitfld.word 0x0 3. "MLM,Message Lost Mode Select" "0: Overwrite mode,1: Overrun mode" bitfld.word 0x0 1.--2. "IDFM,ID Format Mode Select" "0: Standard ID mode.All mailboxes (including FIFO..,1: Extended ID mode.All mailboxes (including FIFO..,?,?" newline bitfld.word 0x0 0. "MBM,CAN Mailbox Mode Select" "0: Normal mailbox mode,1: FIFO mailbox mode" rgroup.word 0x842++0x1 line.word 0x0 "STR,Status Register" bitfld.word 0x0 15. "Reserved,This bit is read as 0." "0,1" bitfld.word 0x0 14. "RECST,Receive Status Flag (receiver)" "0: Bus idle or transmission in progress,1: Reception in progress" newline bitfld.word 0x0 13. "TRMST,Transmit Status Flag (transmitter)" "0: Bus idle or reception in progress,1: Transmission in progress or in bus-off state" bitfld.word 0x0 12. "BOST,Bus-Off Status Flag" "0: Not in bus-off state,1: In bus-off state" newline bitfld.word 0x0 11. "EPST,Error-Passive Status Flag" "0: Not in error-passive state,1: In error-passive state" bitfld.word 0x0 10. "SLPST,CAN Sleep Status Flag" "0: Not in CAN sleep mode,1: In CAN sleep mode" newline bitfld.word 0x0 9. "HLTST,CAN Halt Status Flag" "0: Not in CAN halt mode,1: In CAN halt mode" bitfld.word 0x0 8. "RSTST,CAN Reset Status Flag" "0: Not in CAN reset mode,1: In CAN reset mode" newline bitfld.word 0x0 7. "EST,Error Status Flag" "0: No error occurred,1: Error occurred" bitfld.word 0x0 6. "TABST,Transmission Abort Status Flag" "0: No mailbox with TRMABT bit = 1,1: Mailbox(es) with TRMABT bit = 1" newline bitfld.word 0x0 5. "FMLST,FIFO Mailbox Message Lost Status Flag" "0: RFMLF bit = 0,1: RFMLF bit = 1" bitfld.word 0x0 4. "NMLST,Normal Mailbox Message Lost Status Flag" "0: No mailbox with MSGLOST bit = 1,1: Mailbox(es) with MSGLOST bit = 1" newline bitfld.word 0x0 3. "TFST,Transmit FIFO Status Flag" "0: Transmit FIFO is full,1: Transmit FIFO is not full" bitfld.word 0x0 2. "RFST,Receive FIFO Status Flag" "0: No message in receive FIFO (empty),1: Message in receive FIFO" newline bitfld.word 0x0 1. "SDST,SENTDATA Status Flag" "0: No mailbox with SENTDATA bit = 1,1: Mailbox(es) with SENTDATA bit = 1" bitfld.word 0x0 0. "NDST,NEWDATA Status Flag" "0: No mailbox with NEWDATA bit = 1,1: Mailbox(es) with NEWDATA bit = 1" group.long 0x844++0x3 line.long 0x0 "BCR,Bit Configuration Register" hexmask.long.byte 0x0 28.--31. 1. "TSEG1,Time Segment 1 Control" bitfld.long 0x0 26.--27. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" newline hexmask.long.word 0x0 16.--25. 1. "BRP,Prescaler Division Ratio Select . These bits set the frequency of the CAN communication clock (fCANCLK)." bitfld.long 0x0 14.--15. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" newline bitfld.long 0x0 12.--13. "SJW,Resynchronization Jump Width Control" "0: 1 Tq,1: 2 Tq,?,?" bitfld.long 0x0 11. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.long 0x0 8.--10. "TSEG2,Time Segment 2 Control" "0: Setting prohibited,1: 2 Tq,?,?,?,?,?,?" hexmask.long.byte 0x0 1.--7. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." newline bitfld.long 0x0 0. "CCLKS,CAN Clock Source Selection" "0: PCLK (generated by the PLL clock),1: CANMCLK (generated by the main clock)" group.byte 0x848++0x0 line.byte 0x0 "RFCR,Receive FIFO Control Register" rbitfld.byte 0x0 7. "RFEST,Receive FIFO Empty Status Flag" "0: Unread message in receive FIFO,1: No unread message in receive FIFO" rbitfld.byte 0x0 6. "RFWST,Receive FIFO Buffer Warning Status Flag" "0: Receive FIFO is not buffer warning,1: Receive FIFO is buffer warning (3 unread messages)" newline rbitfld.byte 0x0 5. "RFFST,Receive FIFO Full Status Flag" "0: Receive FIFO is not full,1: Receive FIFO is full (4 unread messages)" bitfld.byte 0x0 4. "RFMLF,Receive FIFO Message Lost Flag" "0: No receive FIFO message lost has occurred,1: Receive FIFO message lost has occurred" newline rbitfld.byte 0x0 1.--3. "RFUST,Receive FIFO Unread Message Number Status" "0: Setting prohibited,1: 1 unread message,?,?,?,?,?,?" bitfld.byte 0x0 0. "RFE,Receive FIFO Enable" "0: Receive FIFO disabled,1: Receive FIFO enabled" wgroup.byte 0x849++0x0 line.byte 0x0 "RFPCR,Receive FIFO Pointer Control Register" hexmask.byte 0x0 0.--7. 1. "RFPCR,The CPU-side pointer for the receive FIFO is incremented by writing FFh to RFPCR." group.byte 0x84A++0x0 line.byte 0x0 "TFCR,Transmit FIFO Control Register" rbitfld.byte 0x0 7. "TFEST,Transmit FIFO Empty Status" "0: Unsent message in transmit FIFO,1: No unsent message in transmit FIFO" rbitfld.byte 0x0 6. "TFFST,Transmit FIFO Full Status" "0: Transmit FIFO is not full,1: Transmit FIFO is full (4 unsent messages)" newline bitfld.byte 0x0 4.--5. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" rbitfld.byte 0x0 1.--3. "TFUST,Transmit FIFO Unsent Message Number Status" "0: Setting prohibited,1: 1 unsent message,?,?,?,?,?,?" newline bitfld.byte 0x0 0. "TFE,Transmit FIFO Enable" "0: Transmit FIFO disabled,1: Transmit FIFO enabled" wgroup.byte 0x84B++0x0 line.byte 0x0 "TFPCR,Transmit FIFO Pointer Control Register" hexmask.byte 0x0 0.--7. 1. "TFPCR,The CPU-side pointer for the transmit FIFO is incremented by writing FFh to TFPCR." group.byte 0x84C++0x1 line.byte 0x0 "EIER,Error Interrupt Enable Register" bitfld.byte 0x0 7. "BLIE,Bus Lock Interrupt Enable" "0: Bus lock interrupt disabled,1: Bus lock interrupt enabled" bitfld.byte 0x0 6. "OLIE,Overload Frame Transmit Interrupt Enable" "0: Overload frame transmit interrupt disabled,1: Overload frame transmit interrupt enabled" newline bitfld.byte 0x0 5. "ORIE,Overrun Interrupt Enable" "0: Receive overrun interrupt disabled,1: Receive overrun interrupt enabled" bitfld.byte 0x0 4. "BORIE,Bus-Off Recovery Interrupt Enable" "0: Bus-off recovery interrupt disabled,1: Bus-off recovery interrupt enabled" newline bitfld.byte 0x0 3. "BOEIE,Bus-Off Entry Interrupt Enable" "0: Bus-off entry interrupt disabled,1: Bus-off entry interrupt enabled" bitfld.byte 0x0 2. "EPIE,Error-Passive Interrupt Enable" "0: Error-passive interrupt disabled,1: Error-passive interrupt enabled" newline bitfld.byte 0x0 1. "EWIE,Error-Warning Interrupt Enable" "0: Error-warning interrupt disabled,1: Error-warning interrupt enabled" bitfld.byte 0x0 0. "BEIE,Bus Error Interrupt Enable" "0: Bus error interrupt disabled,1: Bus error interrupt enabled" line.byte 0x1 "EIFR,Error Interrupt Factor Judge Register" bitfld.byte 0x1 7. "BLIF,Bus Lock Detect Flag" "0: No bus lock detected,1: Bus lock detected" bitfld.byte 0x1 6. "OLIF,Overload Frame Transmission Detect Flag" "0: No overload frame transmission detected,1: Overload frame transmission detected" newline bitfld.byte 0x1 5. "ORIF,Receive Overrun Detect Flag" "0: No receive overrun detected,1: Receive overrun detected" bitfld.byte 0x1 4. "BORIF,Bus-Off Recovery Detect Flag" "0: No bus-off recovery detected,1: Bus-off recovery detected" newline bitfld.byte 0x1 3. "BOEIF,Bus-Off Entry Detect Flag" "0: No bus-off entry detected,1: Bus-off entry detected" bitfld.byte 0x1 2. "EPIF,Error-Passive Detect Flag" "0: No error-passive detected,1: Error-passive detected" newline bitfld.byte 0x1 1. "EWIF,Error-Warning Detect Flag" "0: No error-warning detected,1: Error-warning detected" bitfld.byte 0x1 0. "BEIF,Bus Error Detect Flag" "0: No bus error detected,1: Bus error detected" rgroup.byte 0x84E++0x1 line.byte 0x0 "RECR,Receive Error Count Register" hexmask.byte 0x0 0.--7. 1. "RECR,Receive error count functionRECR increments or decrements the counter value according to the error status of the CAN module during reception." line.byte 0x1 "TECR,Transmit Error Count Register" hexmask.byte 0x1 0.--7. 1. "TECR,Transmit error count functionTECR increments or decrements the counter value according to the error status of the CAN module during transmission." group.byte 0x850++0x1 line.byte 0x0 "ECSR,Error Code Store Register" bitfld.byte 0x0 7. "EDPM,Error Display Mode Select" "0: Output of first detected error code,1: Output of accumulated error code" bitfld.byte 0x0 6. "ADEF,ACK Delimiter Error Flag" "0: No ACK delimiter error detected,1: ACK delimiter error detected" newline bitfld.byte 0x0 5. "BE0F,Bit Error (dominant) Flag" "0: No bit error (dominant) detected,1: Bit error (dominant) detected" bitfld.byte 0x0 4. "BE1F,Bit Error (recessive) Flag" "0: No bit error (recessive) detected,1: Bit error (recessive) detected" newline bitfld.byte 0x0 3. "CEF,CRC Error Flag" "0: No CRC error detected,1: CRC error detected" bitfld.byte 0x0 2. "AEF,ACK Error Flag" "0: No ACK error detected,1: ACK error detected" newline bitfld.byte 0x0 1. "FEF,Form Error Flag" "0: No form error detected,1: Form error detected" bitfld.byte 0x0 0. "SEF,Stuff Error Flag" "0: No stuff error detected,1: Stuff error detected" line.byte 0x1 "CSSR,Channel Search Support Register" hexmask.byte 0x1 0.--7. 1. "CSSR,When the value for the channel search is input the channel number is output to MSSR." rgroup.byte 0x852++0x0 line.byte 0x0 "MSSR,Mailbox Search Status Register" bitfld.byte 0x0 7. "SEST,Search Result Status" "0: Search result found,1: No search result" bitfld.byte 0x0 5.--6. "Reserved,These bits are read as 00." "0,1,2,3" newline hexmask.byte 0x0 0.--4. 1. "MBNST,Search Result Mailbox Number Status These bits output the smallest mailbox number that is searched in each mode of MSMR." group.byte 0x853++0x0 line.byte 0x0 "MSMR,Mailbox Search Mode Register" hexmask.byte 0x0 2.--7. 1. "Reserved,These bits are read as 000000. The write value should be 000000." bitfld.byte 0x0 0.--1. "MBSM,Mailbox Search Mode Select" "0: Receive mailbox search mode,1: Transmit mailbox search mode,?,?" rgroup.word 0x854++0x1 line.word 0x0 "TSR,Time Stamp Register" hexmask.word 0x0 0.--15. 1. "TSR,Free-running counter value for the time stamp function" group.word 0x856++0x1 line.word 0x0 "AFSR,Acceptance Filter Support Register" hexmask.word 0x0 0.--15. 1. "AFSR,After the standard ID of a received message is written the value converted for data table search can be read." group.byte 0x858++0x0 line.byte 0x0 "TCR,Test Control Register" hexmask.byte 0x0 3.--7. 1. "Reserved,These bits are read as 00000. The write value should be 00000." bitfld.byte 0x0 1.--2. "TSTM,CAN Test Mode Select" "0: Other than CAN test mode,1: Listen-only mode,?,?" newline bitfld.byte 0x0 0. "TSTE,CAN Test Mode Enable" "0: CAN test mode disabled,1: CAN test mode enabled" tree.end tree "CRC (Cyclic Redundancy Check)" base ad:0x40074000 group.byte 0x0++0x1 line.byte 0x0 "CRCCR0,CRC Control Register0" bitfld.byte 0x0 7. "DORCIR,CRCDOR Register Clear" "0: No effect.,1: Clears the CRCDOR register." bitfld.byte 0x0 6. "LMS,CRC Calculation Switching" "0: Generates CRC for LSB first communication.,1: Generates CRC for MSB first communication." bitfld.byte 0x0 3.--5. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" newline bitfld.byte 0x0 0.--2. "GPS,CRC Generating Polynomial Switching" "0: No calculation is executed.,1: 8-bit CRC-8 (X8 + X2 + X + 1),?,?,?,?,?,?" line.byte 0x1 "CRCCR1,CRC Control Register1" bitfld.byte 0x1 7. "CRCSEN,Snoop enable bit" "0: Disabled,1: Enabled" bitfld.byte 0x1 6. "CRCSWR,Snoop-on-write/read switch bit" "0: Snoop-on-read,1: Snoop-on-write" hexmask.byte 0x1 0.--5. 1. "Reserved,These bits are read as 000000. The write value should be 000000." group.long 0x4++0x3 line.long 0x0 "CRCDIR,CRC Data Input Register" hexmask.long 0x0 0.--31. 1. "CRCDIR,Calculation input Data (Case of CRC-32 CRC-32C )" group.byte 0x4++0x0 line.byte 0x0 "CRCDIR_BY,CRC Data Input Register (byte access)" hexmask.byte 0x0 0.--7. 1. "CRCDIR_BY,Calculation input Data ( Case of CRC-8 CRC-16 or CRC-CCITT )" group.long 0x8++0x3 line.long 0x0 "CRCDOR,CRC Data Output Register" hexmask.long 0x0 0.--31. 1. "CRCDOR,Calculation output Data (Case of CRC-32 CRC-32C )" group.word 0x8++0x1 line.word 0x0 "CRCDOR_HA,CRC Data Output Register (halfword access)" hexmask.word 0x0 0.--15. 1. "CRCDOR_HA,Calculation output Data (Case of CRC-16 or CRC-CCITT )" group.byte 0x8++0x0 line.byte 0x0 "CRCDOR_BY,CRC Data Output Register(byte access)" hexmask.byte 0x0 0.--7. 1. "CRCDOR_BY,Calculation output Data (Case of CRC-8 )" group.word 0xC++0x1 line.word 0x0 "CRCSAR,Snoop Address Register" bitfld.word 0x0 14.--15. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" hexmask.word 0x0 0.--13. 1. "CRCSA,snoop address bitSet the I/O register address to snoop" tree.end tree "CTSU (Capacitive Touch Sensing Unit)" base ad:0x40081000 group.byte 0x0++0x11 line.byte 0x0 "CTSUCR0,CTSU Control Register 0" bitfld.byte 0x0 4. "CTSUINIT,CTSU Control Block Initialization" "0: Writing a 0 has no effect this bit is read as 0.,1: initializes the CTSU control block and registers." bitfld.byte 0x0 3. "CTSUIOC,CTSU Transmit Pin Control" "0: Low-level output from transmit channel..,1: High-level output from transmit channel.." newline bitfld.byte 0x0 2. "CTSUSNZ,CTSU Wait State Power-Saving Enable" "0: Power-saving function during wait state is..,1: Power-saving function during wait state is.." bitfld.byte 0x0 1. "CTSUCAP,CTSU Measurement Operation Start Trigger Select" "0: Software trigger.,1: External trigger." newline bitfld.byte 0x0 0. "CTSUSTRT,CTSU Measurement Operation Start" "0: Measurement operation stops.,1: Measurement operation starts." line.byte 0x1 "CTSUCR1,CTSU Control Register 1" bitfld.byte 0x1 6.--7. "CTSUMD,CTSU Measurement Mode Select" "0: Self-capacitance single scan mode,1: Self-capacitance multi-scan mode,?,?" bitfld.byte 0x1 4.--5. "CTSUCLK,CTSU Operating Clock Select" "0: PCLK,1: PCLK/2 (PCLK divided by 2),?,?" newline bitfld.byte 0x1 3. "CTSUATUNE1,CTSU Power Supply Capacity Adjustment" "0: Normal output,1: High-current output" bitfld.byte 0x1 2. "CTSUATUNE0,CTSU Power Supply Operating Mode Setting" "0: Normal operating mode,1: Low-voltage operating mode" newline bitfld.byte 0x1 1. "CTSUCSW,CTSU LPF Capacitance Charging Control" "0: Turned off capacitance switch,1: Turned on capacitance switch" bitfld.byte 0x1 0. "CTSUPON,CTSU Power Supply Enable" "0: Powered off the CTSU,1: Powered on the CTSU" line.byte 0x2 "CTSUSDPRS,CTSU Synchronous Noise Reduction Setting Register" bitfld.byte 0x2 7. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x2 6. "CTSUSOFF,CTSU High-Pass Noise Reduction Function Off Setting" "0: High-pass noise reduction function turned on,1: High-pass noise reduction function turned off" newline bitfld.byte 0x2 4.--5. "CTSUPRMODE,CTSU Base Period and Pulse Count Setting" "0: 510 pulses,1: 126 pulses,?,?" hexmask.byte 0x2 0.--3. 1. "CTSUPRRATIO,CTSU Measurement Time and Pulse Count AdjustmentRecommended setting: 3 (0011b)" line.byte 0x3 "CTSUSST,CTSU Sensor Stabilization Wait Control Register" hexmask.byte 0x3 0.--7. 1. "CTSUSST,CTSU Sensor Stabilization Wait ControlNOTE: The value of these bits should be fixed to 00010000b." line.byte 0x4 "CTSUMCH0,CTSU Measurement Channel Register 0" bitfld.byte 0x4 6.--7. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" hexmask.byte 0x4 0.--5. 1. "CTSUMCH0,CTSU Measurement Channel 0.Note1: Writing to these bits is only enabled in self-capacitance single-scan mode (CTSUCR1.CTSUMD[1:0] bits = 00b).Note2: If the value of CTSUMCH0 was set to b'111111 in mode other than self-capacitor single scan.." line.byte 0x5 "CTSUMCH1,CTSU Measurement Channel Register 1" bitfld.byte 0x5 6.--7. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" hexmask.byte 0x5 0.--5. 1. "CTSUMCH1,CTSU Measurement Channel 1Note1: If the value of CTSUMCH1 was set to b'111111 the measurement is stopped." line.byte 0x6 "CTSUCHAC0,CTSU Channel Enable Control Register 0" hexmask.byte 0x6 0.--7. 1. "CTSUCHAC0,CTSU Channel Enable Control 0.0: Not measurement target1: Measurement targetNote: CTSUCHAC0[0] corresponds to TS00 and CTSUCHAC0[7] corresponds to TS07. but the write value of CTSUCHAC0[2] should be 0." line.byte 0x7 "CTSUCHAC1,CTSU Channel Enable Control Register 1" hexmask.byte 0x7 0.--7. 1. "CTSUCHAC1,CTSU Channel Enable Control 1.0: Not measurement target1: Measurement targetNote: CTSUCHAC1[0] corresponds to TS08 and CTSUCHAC1[7] corresponds to TS15." line.byte 0x8 "CTSUCHAC2,CTSU Channel Enable Control Register 2" hexmask.byte 0x8 0.--7. 1. "CTSUCHAC2,CTSU Channel Enable Control 2.0: Not measurement target1: Measurement targetNote: CTSUCHAC2[0] corresponds to TS16 and CTSUCHAC2[7] corresponds to TS23." line.byte 0x9 "CTSUCHAC3,CTSU Channel Enable Control Register 3" hexmask.byte 0x9 0.--7. 1. "CTSUCHAC3,CTSU Channel Enable Control 3.0: Not measurement target1: Measurement targetNote: CTSUCHAC3[0] corresponds to TS24 and CTSUCHAC3[7] corresponds to TS31." line.byte 0xA "CTSUCHAC4,CTSU Channel Enable Control Register 4" hexmask.byte 0xA 4.--7. 1. "Reserved,These bits are read as 0000. The write value should be 0000." hexmask.byte 0xA 0.--3. 1. "CTSUCHAC4,CTSU Channel Enable Control 4.0: Not measurement target1: Measurement targetNote: CTSUCHAC4[0] corresponds to TS32 and CTSUCHAC4[3] corresponds to TS35. but the write value of CTSUCHAC0[4] CTSUCHAC4[5] CTSUCHAC4[6] CTSUCHAC4[7] should be 0." line.byte 0xB "CTSUCHTRC0,CTSU Channel Transmit/Receive Control Register 0" hexmask.byte 0xB 0.--7. 1. "CTSUCHTRC0,CTSU Channel Transmit/Receive Control 0" line.byte 0xC "CTSUCHTRC1,CTSU Channel Transmit/Receive Control Register 1" hexmask.byte 0xC 0.--7. 1. "CTSUCHTRC1,CTSU Channel Transmit/Receive Control 1" line.byte 0xD "CTSUCHTRC2,CTSU Channel Transmit/Receive Control Register 3" hexmask.byte 0xD 0.--7. 1. "CTSUCHTRC2,CTSU Channel Transmit/Receive Control 2" line.byte 0xE "CTSUCHTRC3,CTSU Channel Transmit/Receive Control Register 3" hexmask.byte 0xE 0.--7. 1. "CTSUCHTRC3,CTSU Channel Transmit/Receive Control 3" line.byte 0xF "CTSUCHTRC4,CTSU Channel Transmit/Receive Control Register 4" hexmask.byte 0xF 4.--7. 1. "Reserved,These bits are read as 0000. The write value should be 0000." hexmask.byte 0xF 0.--3. 1. "CTSUCHAC4,CTSU Channel Transmit/Receive Control 4" line.byte 0x10 "CTSUDCLKC,CTSU High-Pass Noise Reduction Control Register" bitfld.byte 0x10 6.--7. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.byte 0x10 4.--5. "CTSUSSCNT,CTSU Diffusion Clock Mode ControlNOTE: This bit should be set to 11b." "0,1,2,3" newline bitfld.byte 0x10 2.--3. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.byte 0x10 0.--1. "CTSUSSMOD,CTSU Diffusion Clock Mode SelectNOTE: This bit should be set to 00b." "0,1,2,3" line.byte 0x11 "CTSUST,CTSU Status Register" rbitfld.byte 0x11 7. "CTSUPS,CTSU Mutual Capacitance Status Flag" "0: First measurement,1: Second measurement" bitfld.byte 0x11 6. "CTSUROVF,CTSU Reference Counter Overflow Flag" "0: No overflow,1: An overflow" newline bitfld.byte 0x11 5. "CTSUSOVF,CTSU Sensor Counter Overflow Flag" "0: No overflow,1: An overflow" rbitfld.byte 0x11 4. "CTSUDTSR,CTSU Data Transfer Status Flag" "0: Measurement result has been read,1: Measurement result has not been read" newline bitfld.byte 0x11 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x11 0.--2. "CTSUSTC,CTSU Measurement Status Counter" "0: Status 0,1: Status 1,?,?,?,?,?,?" group.word 0x12++0x5 line.word 0x0 "CTSUSSC,CTSU High-Pass Noise Reduction Spectrum Diffusion Control Register" hexmask.word.byte 0x0 12.--15. 1. "Reserved,These bits are read as 0000. The write value should be 0000." hexmask.word.byte 0x0 8.--11. 1. "CTSUSSDIV,CTSU Spectrum Diffusion Frequency Division Setting" newline hexmask.word.byte 0x0 0.--7. 1. "Reserved,These bits are read as 00000000. The write value should be 00000000." line.word 0x2 "CTSUSO0,CTSU Sensor Offset Register 0" hexmask.word.byte 0x2 10.--15. 1. "CTSUSNUM,CTSU Measurement Count Setting" hexmask.word 0x2 0.--9. 1. "CTSUSO,CTSU Sensor Offset AdjustmentCurrent offset amount is CTSUSO ( 0 to 1023 )" line.word 0x4 "CTSUSO1,CTSU Sensor Offset Register 1" bitfld.word 0x4 15. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x4 13.--14. "CTSUICOG,CTSU ICO Gain Adjustment" "0: 100 percent gain,1: 66 percent gain,?,?" newline hexmask.word.byte 0x4 8.--12. 1. "CTSUSDPA,CTSU Base Clock SettingOperating clock divided by ( CTSUSDPA + 1 ) x 2" hexmask.word.byte 0x4 0.--7. 1. "CTSURICOA,CTSU Reference ICO Current AdjustmentCurrent offset amount is CTSUSO ( 0 to 255 )" rgroup.word 0x18++0x5 line.word 0x0 "CTSUSC,CTSU Sensor Counter" hexmask.word 0x0 0.--15. 1. "CTSUSC,CTSU Sensor CounterThese bits indicate the measurement result of the CTSU. These bits indicate FFFFh when an overflow occurs." line.word 0x2 "CTSURC,CTSU Reference Counter" hexmask.word 0x2 0.--15. 1. "CTSURC,CTSU Reference CounterThese bits indicate the measurement result of the reference ICO.These bits indicate FFFFh when an overflow occurs." line.word 0x4 "CTSUERRS,CTSU Error Status Register" bitfld.word 0x4 15. "CTSUICOMP,TSCAP Voltage Error Monitor" "0: Normal TSCAP voltage,1: Abnormal TSCAP voltage" hexmask.word 0x4 0.--14. 1. "Reserved,These bits are read as 000000000000000." tree.end tree "DAC (D/A Converter)" base ad:0x0 tree "DAC8" base ad:0x4009E000 repeat 2. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2)++0x0 line.byte 0x0 "DACS$1,D/A Conversion Value Setting Register %s" hexmask.byte 0x0 0.--7. 1. "DACS,DACS D/A conversion store data note: When 8-bit D/A Converter output is selected as the reference input for the ACMPLP in the COMPSEL1 register and ACMPLP operation is enabled (COMPMDR.CnENB = 1) changing the DACS[7:0] bits for the channel in use.." repeat.end group.byte 0x3++0x0 line.byte 0x0 "DAM,D/A Converter Mode Register" bitfld.byte 0x0 6.--7. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.byte 0x0 5. "DACE1,D/A Operation Enable 1" "0: D/A conversion disabled for channel 1,1: D/A conversion enabled for channel 1" bitfld.byte 0x0 4. "DACE0,D/A Operation Enable 0" "0: D/A conversion disabled for channel 0,1: D/A conversion enabled for channel 0." hexmask.byte 0x0 0.--3. 1. "Reserved,These bits are read as 0000. The write value should be 0000." tree.end tree "DAC12" base ad:0x4005E000 group.word 0x0++0x1 line.word 0x0 "DADR0,D/A Data Register 0" hexmask.word 0x0 0.--15. 1. "DADR,D/A Data RegisterNOTE: When DADPR.DPSEL = 0 the high-order 4 bits are fixed to 0: right justified format. When DADPR.DPSEL = 1 the low-order 4 bits are fixed to 0: left justified format." group.byte 0x4++0x3 line.byte 0x0 "DACR,D/A Control Register" bitfld.byte 0x0 7. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 6. "DAOE0,D/A Output Enable 0" "0: Analog output of channel 0 (DA0) is disabled.,1: D/A conversion of channel 0 is enabled. Analog.." bitfld.byte 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" hexmask.byte 0x0 0.--4. 1. "Reserved,These bits are read as 11111. The write value should be 11111." line.byte 0x1 "DADPR,DADR0 Format Select Register" bitfld.byte 0x1 7. "DPSEL,DADRm Format Select" "0: Right justified format.,1: Left justified format." hexmask.byte 0x1 0.--6. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." line.byte 0x2 "DAADSCR,D/A-A/D Synchronous Start Control Register" bitfld.byte 0x2 7. "DAADST,D/A-A/D Synchronous Conversion" "0: D/A converter operation does not synchronize..,1: D/A converter operation synchronizes with A/D.." line.byte 0x3 "DAVREFCR,D/A VREF Control Register" hexmask.byte 0x3 3.--7. 1. "Reserved,These bits are read as 00000. The write value should be 00000." bitfld.byte 0x3 0.--2. "REF,D/A Reference Voltage Select" "0: Setting prohibited,1: AVCC0/AVSS0,?,?,?,?,?,?" tree.end tree.end tree "DBG (Debug Function)" base ad:0x4001B000 rgroup.long 0x0++0x3 line.long 0x0 "DBGSTR,Debug Status Register" bitfld.long 0x0 30.--31. "Reserved,These bits are read as 00." "0,1,2,3" bitfld.long 0x0 29. "CDBGPWRUPACK,Debug power-up acknowledge" "0: Debug power-up request is not acknowledged,1: Debug power-up request is acknowledged" newline bitfld.long 0x0 28. "CDBGPWRUPREQ,Debug power-up request" "0: OCD is not requesting debug power-up,1: OCD is requesting debug power-up" hexmask.long 0x0 0.--27. 1. "Reserved,These bits are read as 0000000000000000000000000000." group.long 0x10++0x3 line.long 0x0 "DBGSTOPCR,Debug Stop Control Register" hexmask.long.byte 0x0 26.--31. 1. "Reserved,These bits are read as 000000. The write value should be 000000." bitfld.long 0x0 25. "DBGSTOP_RECCR,Mask bit for RAM ECC error reset/interrupt" "0: Enable RAM ECC error reset/interrupt,1: Mask RAM ECC error reset/interrupt" newline bitfld.long 0x0 24. "DBGSTOP_RPER,Mask bit for RAM parity error reset/interrupt" "0: Enable RAM parity error reset/interrupt,1: Mask RAM parity error reset/interrupt" hexmask.long.byte 0x0 19.--23. 1. "Reserved,These bits are read as 00000. The write value should be 00000." newline bitfld.long 0x0 16.--18. "DBGSTOP_LVD,b18: Mask bit for LVD2 reset/interrupt (0:enable / 1:Mask)b17: Mask bit for LVD1 reset/interrupt (0:enable / 1:Mask)b16: Mask bit for LVD0 reset (0:enable / 1:Mask)" "0: enable / 1:Mask),?,?,?,?,?,?,?" hexmask.long.word 0x0 2.--15. 1. "Reserved,These bits are read as 00000000000000. The write value should be 00000000000000." newline bitfld.long 0x0 1. "DBGSTOP_WDT,Mask bit for WDT reset/interrupt" "0: Mask WDT reset/interrupt,1: Enable WDT reset" bitfld.long 0x0 0. "DBGSTOP_IWDT,Mask bit for IWDT reset/interrupt" "0: Mask IWDT reset/interrupt,1: Enable IWDT reset" group.long 0x20++0x3 line.long 0x0 "TRACECTR,Trace Control Register" bitfld.long 0x0 31. "ENETBFULL,Enable bit for halt request by ETB full" "0: ETB full does not cause CPU halt,1: ETB full cause CPU halt" hexmask.long 0x0 0.--30. 1. "Reserved,These bits are read as 0000000000000000000000000000000. The write value should be 0000000000000000000000000000000." tree.end tree "DMA (Direct Memory Access)" base ad:0x40005200 group.byte 0x0++0x0 line.byte 0x0 "DMAST,DMAC Module Activation Register" hexmask.byte 0x0 1.--7. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.byte 0x0 0. "DMST,DMAC Operation Enable" "0: Disabled.,1: Enabled." tree.end tree "DMAC (Direct Memory Access Controller)" base ad:0x0 tree "DMAC0" base ad:0x40005000 group.long 0x0++0xB line.long 0x0 "DMSAR,DMA Source Address Register" hexmask.long 0x0 0.--31. 1. "DMSAR,Specifies the transfer source start address." line.long 0x4 "DMDAR,DMA Destination Address Register" hexmask.long 0x4 0.--31. 1. "DMDAR,Specifies the transfer destination start address." line.long 0x8 "DMCRA,DMA Transfer Count Register" hexmask.long.byte 0x8 26.--31. 1. "Reserved,These bits are read as 000000. The write value should be 000000." hexmask.long.word 0x8 16.--25. 1. "DMCRAH,Upper bits of transfer count" newline hexmask.long.word 0x8 0.--15. 1. "DMCRAL,Lower bits of transfer count" group.word 0xC++0x1 line.word 0x0 "DMCRB,DMA Block Transfer Count Register" hexmask.word 0x0 0.--15. 1. "DMCRB,Specifies the number of block transfer operations or repeat transfer operations." group.word 0x10++0x1 line.word 0x0 "DMTMD,DMA Transfer Mode Register" bitfld.word 0x0 14.--15. "MD,Transfer Mode Select" "0: Normal transfer,1: Repeat transfer,?,?" bitfld.word 0x0 12.--13. "DTS,Repeat Area Select" "0: The destination is specified as the repeat area..,1: The source is specified as the repeat area or..,?,?" newline bitfld.word 0x0 10.--11. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.word 0x0 8.--9. "SZ,Transfer Data Size Select" "0: 8 bits,1: 16 bits,?,?" newline hexmask.word.byte 0x0 2.--7. 1. "Reserved,These bits are read as 000000. The write value should be 000000." bitfld.word 0x0 0.--1. "DCTG,Transfer Request Source Select" "0: Software,1: Interrupts*1 from peripheral modules or external..,?,?" group.byte 0x13++0x0 line.byte 0x0 "DMINT,DMA Interrupt Setting Register" bitfld.byte 0x0 5.--7. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.byte 0x0 4. "DTIE,Transfer End Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.byte 0x0 3. "ESIE,Transfer Escape End Interrupt Enable" "0: Disabled,1: Enabled" bitfld.byte 0x0 2. "RPTIE,Repeat Size End Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.byte 0x0 1. "SARIE,Source Address Extended Repeat Area Overflow Interrupt Enable" "0: Disabled,1: Enabled" bitfld.byte 0x0 0. "DARIE,Destination Address Extended Repeat Area Overflow Interrupt Enable" "0: Disabled,1: Enabled" group.word 0x14++0x1 line.word 0x0 "DMAMD,DMA Address Mode Register" bitfld.word 0x0 14.--15. "SM,Source Address Update Mode" "0: Fixed address,1: Offset addition,?,?" bitfld.word 0x0 13. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline hexmask.word.byte 0x0 8.--12. 1. "SARA,Source Address Extended Repeat Area Specifies the extended repeat area on the source address. For details on the settings." bitfld.word 0x0 6.--7. "DM,Destination Address Update Mode" "0: Fixed address,1: Offset addition,?,?" newline bitfld.word 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" hexmask.word.byte 0x0 0.--4. 1. "DARA,Destination Address Extended Repeat Area Specifies the extended repeat area on the destination address. For details on the settings." group.long 0x18++0x3 line.long 0x0 "DMOFR,DMA Offset Register" hexmask.long 0x0 0.--31. 1. "DMOFR,Specifies the offset when offset addition is selected as the address update mode for transfer source or destination." group.byte 0x1C++0x2 line.byte 0x0 "DMCNT,DMA Transfer Enable Register" hexmask.byte 0x0 1.--7. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.byte 0x0 0. "DTE,DMA Transfer Enable" "0: Disabled,1: Enabled." line.byte 0x1 "DMREQ,DMA Software Start Register" bitfld.byte 0x1 5.--7. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.byte 0x1 4. "CLRS,DMA Software Start Bit Auto Clear Select" "0: SWREQ bit is cleared after DMA transfer is..,1: SWREQ bit is not cleared after DMA transfer is.." newline bitfld.byte 0x1 1.--3. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.byte 0x1 0. "SWREQ,DMA Software Start" "0: DMA transfer is not requested.,1: DMA transfer is requested." line.byte 0x2 "DMSTS,DMA Status Register" rbitfld.byte 0x2 7. "ACT,DMA Active Flag" "0: DMAC operation suspended,1: DMAC operating." bitfld.byte 0x2 5.--6. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" newline bitfld.byte 0x2 4. "DTIF,Transfer End Interrupt Flag" "0: No interrupt,1: Interrupt occurred." bitfld.byte 0x2 1.--3. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" newline bitfld.byte 0x2 0. "ESIF,Transfer Escape End Interrupt Flag" "0: No interrupt,1: Interrupt occurred." tree.end tree "DMAC1" base ad:0x40005040 group.long 0x0++0xB line.long 0x0 "DMSAR,DMA Source Address Register" hexmask.long 0x0 0.--31. 1. "DMSAR,Specifies the transfer source start address." line.long 0x4 "DMDAR,DMA Destination Address Register" hexmask.long 0x4 0.--31. 1. "DMDAR,Specifies the transfer destination start address." line.long 0x8 "DMCRA,DMA Transfer Count Register" hexmask.long.byte 0x8 26.--31. 1. "Reserved,These bits are read as 000000. The write value should be 000000." hexmask.long.word 0x8 16.--25. 1. "DMCRAH,Upper bits of transfer count" newline hexmask.long.word 0x8 0.--15. 1. "DMCRAL,Lower bits of transfer count" group.word 0xC++0x1 line.word 0x0 "DMCRB,DMA Block Transfer Count Register" hexmask.word 0x0 0.--15. 1. "DMCRB,Specifies the number of block transfer operations or repeat transfer operations." group.word 0x10++0x1 line.word 0x0 "DMTMD,DMA Transfer Mode Register" bitfld.word 0x0 14.--15. "MD,Transfer Mode Select" "0: Normal transfer,1: Repeat transfer,?,?" bitfld.word 0x0 12.--13. "DTS,Repeat Area Select" "0: The destination is specified as the repeat area..,1: The source is specified as the repeat area or..,?,?" newline bitfld.word 0x0 10.--11. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.word 0x0 8.--9. "SZ,Transfer Data Size Select" "0: 8 bits,1: 16 bits,?,?" newline hexmask.word.byte 0x0 2.--7. 1. "Reserved,These bits are read as 000000. The write value should be 000000." bitfld.word 0x0 0.--1. "DCTG,Transfer Request Source Select" "0: Software,1: Interrupts*1 from peripheral modules or external..,?,?" group.byte 0x13++0x0 line.byte 0x0 "DMINT,DMA Interrupt Setting Register" bitfld.byte 0x0 5.--7. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.byte 0x0 4. "DTIE,Transfer End Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.byte 0x0 3. "ESIE,Transfer Escape End Interrupt Enable" "0: Disabled,1: Enabled" bitfld.byte 0x0 2. "RPTIE,Repeat Size End Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.byte 0x0 1. "SARIE,Source Address Extended Repeat Area Overflow Interrupt Enable" "0: Disabled,1: Enabled" bitfld.byte 0x0 0. "DARIE,Destination Address Extended Repeat Area Overflow Interrupt Enable" "0: Disabled,1: Enabled" group.word 0x14++0x1 line.word 0x0 "DMAMD,DMA Address Mode Register" bitfld.word 0x0 14.--15. "SM,Source Address Update Mode" "0: Fixed address,1: Offset addition,?,?" bitfld.word 0x0 13. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline hexmask.word.byte 0x0 8.--12. 1. "SARA,Source Address Extended Repeat Area Specifies the extended repeat area on the source address. For details on the settings." bitfld.word 0x0 6.--7. "DM,Destination Address Update Mode" "0: Fixed address,1: Offset addition,?,?" newline bitfld.word 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" hexmask.word.byte 0x0 0.--4. 1. "DARA,Destination Address Extended Repeat Area Specifies the extended repeat area on the destination address. For details on the settings." group.long 0x18++0x3 line.long 0x0 "DMOFR,DMA Offset Register" hexmask.long 0x0 0.--31. 1. "DMOFR,Specifies the offset when offset addition is selected as the address update mode for transfer source or destination." group.byte 0x1C++0x2 line.byte 0x0 "DMCNT,DMA Transfer Enable Register" hexmask.byte 0x0 1.--7. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.byte 0x0 0. "DTE,DMA Transfer Enable" "0: Disabled,1: Enabled." line.byte 0x1 "DMREQ,DMA Software Start Register" bitfld.byte 0x1 5.--7. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.byte 0x1 4. "CLRS,DMA Software Start Bit Auto Clear Select" "0: SWREQ bit is cleared after DMA transfer is..,1: SWREQ bit is not cleared after DMA transfer is.." newline bitfld.byte 0x1 1.--3. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.byte 0x1 0. "SWREQ,DMA Software Start" "0: DMA transfer is not requested.,1: DMA transfer is requested." line.byte 0x2 "DMSTS,DMA Status Register" rbitfld.byte 0x2 7. "ACT,DMA Active Flag" "0: DMAC operation suspended,1: DMAC operating." bitfld.byte 0x2 5.--6. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" newline bitfld.byte 0x2 4. "DTIF,Transfer End Interrupt Flag" "0: No interrupt,1: Interrupt occurred." bitfld.byte 0x2 1.--3. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" newline bitfld.byte 0x2 0. "ESIF,Transfer Escape End Interrupt Flag" "0: No interrupt,1: Interrupt occurred." tree.end tree "DMAC2" base ad:0x40005080 group.long 0x0++0xB line.long 0x0 "DMSAR,DMA Source Address Register" hexmask.long 0x0 0.--31. 1. "DMSAR,Specifies the transfer source start address." line.long 0x4 "DMDAR,DMA Destination Address Register" hexmask.long 0x4 0.--31. 1. "DMDAR,Specifies the transfer destination start address." line.long 0x8 "DMCRA,DMA Transfer Count Register" hexmask.long.byte 0x8 26.--31. 1. "Reserved,These bits are read as 000000. The write value should be 000000." hexmask.long.word 0x8 16.--25. 1. "DMCRAH,Upper bits of transfer count" newline hexmask.long.word 0x8 0.--15. 1. "DMCRAL,Lower bits of transfer count" group.word 0xC++0x1 line.word 0x0 "DMCRB,DMA Block Transfer Count Register" hexmask.word 0x0 0.--15. 1. "DMCRB,Specifies the number of block transfer operations or repeat transfer operations." group.word 0x10++0x1 line.word 0x0 "DMTMD,DMA Transfer Mode Register" bitfld.word 0x0 14.--15. "MD,Transfer Mode Select" "0: Normal transfer,1: Repeat transfer,?,?" bitfld.word 0x0 12.--13. "DTS,Repeat Area Select" "0: The destination is specified as the repeat area..,1: The source is specified as the repeat area or..,?,?" newline bitfld.word 0x0 10.--11. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.word 0x0 8.--9. "SZ,Transfer Data Size Select" "0: 8 bits,1: 16 bits,?,?" newline hexmask.word.byte 0x0 2.--7. 1. "Reserved,These bits are read as 000000. The write value should be 000000." bitfld.word 0x0 0.--1. "DCTG,Transfer Request Source Select" "0: Software,1: Interrupts*1 from peripheral modules or external..,?,?" group.byte 0x13++0x0 line.byte 0x0 "DMINT,DMA Interrupt Setting Register" bitfld.byte 0x0 5.--7. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.byte 0x0 4. "DTIE,Transfer End Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.byte 0x0 3. "ESIE,Transfer Escape End Interrupt Enable" "0: Disabled,1: Enabled" bitfld.byte 0x0 2. "RPTIE,Repeat Size End Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.byte 0x0 1. "SARIE,Source Address Extended Repeat Area Overflow Interrupt Enable" "0: Disabled,1: Enabled" bitfld.byte 0x0 0. "DARIE,Destination Address Extended Repeat Area Overflow Interrupt Enable" "0: Disabled,1: Enabled" group.word 0x14++0x1 line.word 0x0 "DMAMD,DMA Address Mode Register" bitfld.word 0x0 14.--15. "SM,Source Address Update Mode" "0: Fixed address,1: Offset addition,?,?" bitfld.word 0x0 13. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline hexmask.word.byte 0x0 8.--12. 1. "SARA,Source Address Extended Repeat Area Specifies the extended repeat area on the source address. For details on the settings." bitfld.word 0x0 6.--7. "DM,Destination Address Update Mode" "0: Fixed address,1: Offset addition,?,?" newline bitfld.word 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" hexmask.word.byte 0x0 0.--4. 1. "DARA,Destination Address Extended Repeat Area Specifies the extended repeat area on the destination address. For details on the settings." group.long 0x18++0x3 line.long 0x0 "DMOFR,DMA Offset Register" hexmask.long 0x0 0.--31. 1. "DMOFR,Specifies the offset when offset addition is selected as the address update mode for transfer source or destination." group.byte 0x1C++0x2 line.byte 0x0 "DMCNT,DMA Transfer Enable Register" hexmask.byte 0x0 1.--7. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.byte 0x0 0. "DTE,DMA Transfer Enable" "0: Disabled,1: Enabled." line.byte 0x1 "DMREQ,DMA Software Start Register" bitfld.byte 0x1 5.--7. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.byte 0x1 4. "CLRS,DMA Software Start Bit Auto Clear Select" "0: SWREQ bit is cleared after DMA transfer is..,1: SWREQ bit is not cleared after DMA transfer is.." newline bitfld.byte 0x1 1.--3. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.byte 0x1 0. "SWREQ,DMA Software Start" "0: DMA transfer is not requested.,1: DMA transfer is requested." line.byte 0x2 "DMSTS,DMA Status Register" rbitfld.byte 0x2 7. "ACT,DMA Active Flag" "0: DMAC operation suspended,1: DMAC operating." bitfld.byte 0x2 5.--6. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" newline bitfld.byte 0x2 4. "DTIF,Transfer End Interrupt Flag" "0: No interrupt,1: Interrupt occurred." bitfld.byte 0x2 1.--3. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" newline bitfld.byte 0x2 0. "ESIF,Transfer Escape End Interrupt Flag" "0: No interrupt,1: Interrupt occurred." tree.end tree "DMAC3" base ad:0x400050C0 group.long 0x0++0xB line.long 0x0 "DMSAR,DMA Source Address Register" hexmask.long 0x0 0.--31. 1. "DMSAR,Specifies the transfer source start address." line.long 0x4 "DMDAR,DMA Destination Address Register" hexmask.long 0x4 0.--31. 1. "DMDAR,Specifies the transfer destination start address." line.long 0x8 "DMCRA,DMA Transfer Count Register" hexmask.long.byte 0x8 26.--31. 1. "Reserved,These bits are read as 000000. The write value should be 000000." hexmask.long.word 0x8 16.--25. 1. "DMCRAH,Upper bits of transfer count" newline hexmask.long.word 0x8 0.--15. 1. "DMCRAL,Lower bits of transfer count" group.word 0xC++0x1 line.word 0x0 "DMCRB,DMA Block Transfer Count Register" hexmask.word 0x0 0.--15. 1. "DMCRB,Specifies the number of block transfer operations or repeat transfer operations." group.word 0x10++0x1 line.word 0x0 "DMTMD,DMA Transfer Mode Register" bitfld.word 0x0 14.--15. "MD,Transfer Mode Select" "0: Normal transfer,1: Repeat transfer,?,?" bitfld.word 0x0 12.--13. "DTS,Repeat Area Select" "0: The destination is specified as the repeat area..,1: The source is specified as the repeat area or..,?,?" newline bitfld.word 0x0 10.--11. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.word 0x0 8.--9. "SZ,Transfer Data Size Select" "0: 8 bits,1: 16 bits,?,?" newline hexmask.word.byte 0x0 2.--7. 1. "Reserved,These bits are read as 000000. The write value should be 000000." bitfld.word 0x0 0.--1. "DCTG,Transfer Request Source Select" "0: Software,1: Interrupts*1 from peripheral modules or external..,?,?" group.byte 0x13++0x0 line.byte 0x0 "DMINT,DMA Interrupt Setting Register" bitfld.byte 0x0 5.--7. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.byte 0x0 4. "DTIE,Transfer End Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.byte 0x0 3. "ESIE,Transfer Escape End Interrupt Enable" "0: Disabled,1: Enabled" bitfld.byte 0x0 2. "RPTIE,Repeat Size End Interrupt Enable" "0: Disabled,1: Enabled" newline bitfld.byte 0x0 1. "SARIE,Source Address Extended Repeat Area Overflow Interrupt Enable" "0: Disabled,1: Enabled" bitfld.byte 0x0 0. "DARIE,Destination Address Extended Repeat Area Overflow Interrupt Enable" "0: Disabled,1: Enabled" group.word 0x14++0x1 line.word 0x0 "DMAMD,DMA Address Mode Register" bitfld.word 0x0 14.--15. "SM,Source Address Update Mode" "0: Fixed address,1: Offset addition,?,?" bitfld.word 0x0 13. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline hexmask.word.byte 0x0 8.--12. 1. "SARA,Source Address Extended Repeat Area Specifies the extended repeat area on the source address. For details on the settings." bitfld.word 0x0 6.--7. "DM,Destination Address Update Mode" "0: Fixed address,1: Offset addition,?,?" newline bitfld.word 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" hexmask.word.byte 0x0 0.--4. 1. "DARA,Destination Address Extended Repeat Area Specifies the extended repeat area on the destination address. For details on the settings." group.long 0x18++0x3 line.long 0x0 "DMOFR,DMA Offset Register" hexmask.long 0x0 0.--31. 1. "DMOFR,Specifies the offset when offset addition is selected as the address update mode for transfer source or destination." group.byte 0x1C++0x2 line.byte 0x0 "DMCNT,DMA Transfer Enable Register" hexmask.byte 0x0 1.--7. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.byte 0x0 0. "DTE,DMA Transfer Enable" "0: Disabled,1: Enabled." line.byte 0x1 "DMREQ,DMA Software Start Register" bitfld.byte 0x1 5.--7. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.byte 0x1 4. "CLRS,DMA Software Start Bit Auto Clear Select" "0: SWREQ bit is cleared after DMA transfer is..,1: SWREQ bit is not cleared after DMA transfer is.." newline bitfld.byte 0x1 1.--3. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.byte 0x1 0. "SWREQ,DMA Software Start" "0: DMA transfer is not requested.,1: DMA transfer is requested." line.byte 0x2 "DMSTS,DMA Status Register" rbitfld.byte 0x2 7. "ACT,DMA Active Flag" "0: DMAC operation suspended,1: DMAC operating." bitfld.byte 0x2 5.--6. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" newline bitfld.byte 0x2 4. "DTIF,Transfer End Interrupt Flag" "0: No interrupt,1: Interrupt occurred." bitfld.byte 0x2 1.--3. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" newline bitfld.byte 0x2 0. "ESIF,Transfer Escape End Interrupt Flag" "0: No interrupt,1: Interrupt occurred." tree.end tree.end tree "DOC (Data Operation Circuit)" base ad:0x40054100 group.byte 0x0++0x0 line.byte 0x0 "DOCR,DOC Control Register" bitfld.byte 0x0 7. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 6. "DOPCFCL,DOPCF Clear" "0: Maintains the DOPCF flag state.,1: Clears the DOPCF flag." rbitfld.byte 0x0 5. "DOPCF,Data Operation Circuit FlagIndicates the result of an operation." "0,1" newline bitfld.byte 0x0 3.--4. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.byte 0x0 2. "DCSEL,Detection Condition Select" "0: DOPCF is set when data mismatch is detected.,1: DOPCF is set when data match is detected." bitfld.byte 0x0 0.--1. "OMS,Operating Mode Select" "0: Data comparison mode,1: Data addition mode,?,?" group.word 0x2++0x3 line.word 0x0 "DODIR,DOC Data Input Register" hexmask.word 0x0 0.--15. 1. "DODIR,16-bit read-write register in which 16-bit data for use in the operations are stored." line.word 0x2 "DODSR,DOC Data Setting Register" hexmask.word 0x2 0.--15. 1. "DODSR,This register stores 16-bit data for use as a reference in data comparison mode. This register also stores the results of operations in data addition and data subtraction modes." tree.end tree "DTC (Data Transfer Controller)" base ad:0x40005400 group.byte 0x0++0x0 line.byte 0x0 "DTCCR,DTC Control Register" bitfld.byte 0x0 5.--7. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.byte 0x0 4. "RRS,DTC Transfer Information Read Skip Enable." "0: Do not skip transfer information read,1: Skip transfer information read when vector.." bitfld.byte 0x0 3. "Reserved,This bit is read as 1. The write value should be 1." "0,1" bitfld.byte 0x0 0.--2. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" group.long 0x4++0x3 line.long 0x0 "DTCVBR,DTC Vector Base Register" hexmask.long 0x0 0.--31. 1. "DTCVBR,DTC Vector Base Address.Note: A value cannot be set in the lower-order 10 bits. These bits are fixed to 0." group.byte 0xC++0x0 line.byte 0x0 "DTCST,DTC Module Start Register" hexmask.byte 0x0 1.--7. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.byte 0x0 0. "DTCST,DTC Module Start" "0: DTC module stop,1: DTC module start" rgroup.word 0xE++0x1 line.word 0x0 "DTCSTS,DTC Status Register" bitfld.word 0x0 15. "ACT,DTC Active Flag" "0: DTC transfer operation is not in progress.,1: DTC transfer operation is in progress." hexmask.word.byte 0x0 8.--14. 1. "Reserved,These bits are read as 0000000." hexmask.word.byte 0x0 0.--7. 1. "VECN,DTC-Activating Vector Number MonitoringThese bits indicate the vector number for the activating source when DTC transfer is in progress.The value is only valid if DTC transfer is in progress (the value of the ACT flag is 1)" tree.end tree "ELC (Event Link Controller)" base ad:0x40041000 group.byte 0x0++0x0 line.byte 0x0 "ELCR,Event Link Controller Register" bitfld.byte 0x0 7. "ELCON,All Event Link Enable" "0: ELC function is disabled.,1: ELC function is enabled." hexmask.byte 0x0 0.--6. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." repeat 2. (increment 0x0 0x1)(increment 0x0 0x2) group.byte ($2+0x2)++0x0 line.byte 0x0 "ELSEGR$1,Event Link Software Event Generation Register %s" bitfld.byte 0x0 7. "WI,ELSEGR Register Write Disable" "0: Write to ELSEGR register is enabled.,1: Write to ELSEGR register is disabled." bitfld.byte 0x0 6. "WE,SEG Bit Write Enable" "0: Write to SEG bit is disabled.,1: Write to SEG bit is enabled." hexmask.byte 0x0 1.--5. 1. "Reserved,These bits are read as 00000. The write value should be 00000." bitfld.byte 0x0 0. "SEG,Software Event Generation" "0: Normal operation,1: Software event is generated." repeat.end repeat 10. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x10)++0x1 line.word 0x0 "ELSR$1,Event Link Setting Register %s" hexmask.word.byte 0x0 8.--15. 1. "Reserved,These bits are read as 00000000. The write value should be 00000000." hexmask.word.byte 0x0 0.--7. 1. "ELS,Event Link Select" repeat.end group.word 0x40++0x1 line.word 0x0 "ELSR12,Event Link Setting Register 12" hexmask.word.byte 0x0 8.--15. 1. "Reserved,These bits are read as 00000000. The write value should be 00000000." hexmask.word.byte 0x0 0.--7. 1. "ELS,Event Link Select" repeat 5. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x48)++0x1 line.word 0x0 "ELSR$1,Event Link Setting Register %s" hexmask.word.byte 0x0 8.--15. 1. "Reserved,These bits are read as 00000000. The write value should be 00000000." hexmask.word.byte 0x0 0.--7. 1. "ELS,Event Link Select" repeat.end tree.end tree "FCACHE (Flash Cache)" base ad:0x4001C000 group.word 0x100++0x1 line.word 0x0 "FCACHEE,Flash Cache Enable Register" hexmask.word 0x0 1.--15. 1. "Reserved,These bits are read as 000000000000000. The write value should be 000000000000000." bitfld.word 0x0 0. "FCACHEEN,FCACHE Enable" "0: FCACHE is disabled,1: FCACHE is enabled" group.word 0x104++0x1 line.word 0x0 "FCACHEIV,Flash Cache Invalidate Register" hexmask.word 0x0 1.--15. 1. "Reserved,These bits are read as 000000000000000. The write value should be 000000000000000." bitfld.word 0x0 0. "FCACHEIV,FCACHE Invalidation" "0: (Read)not in progress / (Write) no effect.,1: (Read)in progress /(Write) Starting Cache.." group.byte 0x11C++0x0 line.byte 0x0 "FLWT,Flash Wait Cycle Register" hexmask.byte 0x0 3.--7. 1. "Reserved,These bits are read as 00000. The write value should be 00000." bitfld.byte 0x0 0.--2. "FLWT,These bits represent the ratio of the CPU clock period to the Flash memory access time." "0: Setting prohibited,?,?,?,?,?,?,?" tree.end tree "GPT (General PWM Timer)" base ad:0x0 tree "GPT164" base ad:0x40078400 group.long 0x0++0xB line.long 0x0 "GTWP,General PWM Timer Write-Protection Register" hexmask.long.word 0x0 16.--31. 1. "Reserved,These bits are read as 0000000000000000. The write value should be 0000000000000000." hexmask.long.byte 0x0 8.--15. 1. "PRKEY,GTWP Key Code" newline hexmask.long.byte 0x0 1.--7. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.long 0x0 0. "WP,Register Write Disable" "0: Write to the register is enabled,1: Write to the register is disabled" line.long 0x4 "GTSTR,General PWM Timer Software Start Register" hexmask.long.tbyte 0x4 10.--31. 1. "Reserved,These bits are read as 0000000000000000000000. The write value should be 0000000000000000000000." bitfld.long 0x4 9. "CSTRT9,Channel 9 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT169.GTCNT counter starts (write) / Counter.." newline bitfld.long 0x4 8. "CSTRT8,Channel 8 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT168.GTCNT counter starts (write) / Counter.." bitfld.long 0x4 7. "CSTRT7,Channel 7 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT167.GTCNT counter starts (write) / Counter.." newline bitfld.long 0x4 6. "CSTRT6,Channel 6 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT166.GTCNT counter starts (write) / Counter.." bitfld.long 0x4 5. "CSTRT5,Channel 5 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT165.GTCNT counter starts (write) / Counter.." newline bitfld.long 0x4 4. "CSTRT4,Channel 4 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT164.GTCNT counter starts (write) / Counter.." bitfld.long 0x4 3. "CSTRT3,Channel 3 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT323.GTCNT counter starts (write) / Counter.." newline bitfld.long 0x4 2. "CSTRT2,Channel 2 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT322.GTCNT counter starts (write) / Counter.." bitfld.long 0x4 1. "CSTRT1,Channel 1 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT321.GTCNT counter starts (write) / Counter.." newline bitfld.long 0x4 0. "CSTRT0,Channel 0 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT320.GTCNT counter starts (write) / Counter.." line.long 0x8 "GTSTP,General PWM Timer Software Stop Register" hexmask.long.tbyte 0x8 10.--31. 1. "Reserved,These bits are read as 1111111111111111111111. The write value should be 1111111111111111111111." bitfld.long 0x8 9. "CSTOP9,Channel 9 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT169.GTCNT counter stops (write) / Counter.." newline bitfld.long 0x8 8. "CSTOP8,Channel 8 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT168.GTCNT counter stops (write) / Counter.." bitfld.long 0x8 7. "CSTOP7,Channel 7 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT167.GTCNT counter stops (write) / Counter.." newline bitfld.long 0x8 6. "CSTOP6,Channel 6 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT166.GTCNT counter stops (write) / Counter.." bitfld.long 0x8 5. "CSTOP5,Channel 5 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT165.GTCNT counter stops (write) / Counter.." newline bitfld.long 0x8 4. "CSTOP4,Channel 4 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT164.GTCNT counter stops (write) / Counter.." bitfld.long 0x8 3. "CSTOP3,Channel 3 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT323.GTCNT counter stops (write) / Counter.." newline bitfld.long 0x8 2. "CSTOP2,Channel 2 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT322.GTCNT counter stops (write) / Counter.." bitfld.long 0x8 1. "CSTOP1,Channel 1 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT321.GTCNT counter stops (write) / Counter.." newline bitfld.long 0x8 0. "CSTOP0,Channel 0 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT320.GTCNT counter stops (write) / Counter.." wgroup.long 0xC++0x3 line.long 0x0 "GTCLR,General PWM Timer Software Clear Register" hexmask.long.tbyte 0x0 10.--31. 1. "Reserved,The write value should be 0000000000000000000000." bitfld.long 0x0 9. "CCLR9,Channel 9 GTCNT Count Clear" "0: No effect,1: GPT169.GTCNT counter clears" newline bitfld.long 0x0 8. "CCLR8,Channel 8 GTCNT Count Clear" "0: No effect,1: GPT168.GTCNT counter clears" bitfld.long 0x0 7. "CCLR7,Channel 7 GTCNT Count Clear" "0: No effect,1: GPT167.GTCNT counter clears" newline bitfld.long 0x0 6. "CCLR6,Channel 6 GTCNT Count Clear" "0: No effect,1: GPT166.GTCNT counter clears" bitfld.long 0x0 5. "CCLR5,Channel 5 GTCNT Count Clear" "0: No effect,1: GPT165.GTCNT counter clears" newline bitfld.long 0x0 4. "CCLR4,Channel 4 GTCNT Count Clear" "0: No effect,1: GPT164.GTCNT counter clears" bitfld.long 0x0 3. "CCLR3,Channel 3 GTCNT Count Clear" "0: No effect,1: GPT323.GTCNT counter clears" newline bitfld.long 0x0 2. "CCLR2,Channel 2 GTCNT Count Clear" "0: No effect,1: GPT322.GTCNT counter clears" bitfld.long 0x0 1. "CCLR1,Channel 1 GTCNT Count Clear" "0: No effect,1: GPT321.GTCNT counter clears" newline bitfld.long 0x0 0. "CCLR0,Channel 0 GTCNT Count Clear" "0: No effect,1: GPT320.GTCNT counter clears" group.long 0x10++0x33 line.long 0x0 "GTSSR,General PWM Timer Start Source Select Register" bitfld.long 0x0 31. "CSTRT,Software Source Counter Start Enable" "0: Counter start is disable by the GTSTR register,1: Counter start is enable by the GTSTR register" hexmask.long.byte 0x0 24.--30. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." newline bitfld.long 0x0 23. "SSELCH,ELC_GPTH Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTH input,1: Counter start is enable at the ELC_GPTH input" bitfld.long 0x0 22. "SSELCG,ELC_GPTG Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTG input,1: Counter start is enable at the ELC_GPTG input" newline bitfld.long 0x0 21. "SSELCF,ELC_GPTF Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTF input,1: Counter start is enable at the ELC_GPTF input" bitfld.long 0x0 20. "SSELCE,ELC_GPTE Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTE input,1: Counter start is enable at the ELC_GPTE input" newline bitfld.long 0x0 19. "SSELCD,ELC_GPTD Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTD input,1: Counter start is enable at the ELC_GPTD input" bitfld.long 0x0 18. "SSELCC,ELC_GPTC Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTC input,1: Counter start is enable at the ELC_GPTC input" newline bitfld.long 0x0 17. "SSELCB,ELC_GPTB Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTB input,1: Counter start is enable at the ELC_GPTB input" bitfld.long 0x0 16. "SSELCA,ELC_GPTA Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTA input,1: Counter start is enable at the ELC_GPTA input" newline bitfld.long 0x0 15. "SSCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." bitfld.long 0x0 14. "SSCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." newline bitfld.long 0x0 13. "SSCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." bitfld.long 0x0 12. "SSCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." newline bitfld.long 0x0 11. "SSCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." bitfld.long 0x0 10. "SSCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." newline bitfld.long 0x0 9. "SSCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." bitfld.long 0x0 8. "SSCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." newline hexmask.long.byte 0x0 4.--7. 1. "Reserved,These bits are read as 0000. The write value should be 0000." bitfld.long 0x0 3. "SSGTRGBF,GTETRGB Pin Falling Input Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." newline bitfld.long 0x0 2. "SSGTRGBR,GTETRGB Pin Rising Input Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." bitfld.long 0x0 1. "SSGTRGAF,GTETRGA Pin Falling Input Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." newline bitfld.long 0x0 0. "SSGTRGAR,GTETRGA Pin Rising Input Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." line.long 0x4 "GTPSR,General PWM Timer Stop Source Select Register" bitfld.long 0x4 31. "CSTOP,Software Source Counter Stop Enable" "0: Counter stop is disable by the GTSTP register,1: Counter stop is enable by the GTSTP register" hexmask.long.byte 0x4 24.--30. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." newline bitfld.long 0x4 23. "PSELCH,ELC_GPTH Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTH input,1: Counter stop is enable at the ELC_GPTH input" bitfld.long 0x4 22. "PSELCG,ELC_GPTG Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTG input,1: Counter stop is enable at the ELC_GPTG input" newline bitfld.long 0x4 21. "PSELCF,ELC_GPTF Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTF input,1: Counter stop is enable at the ELC_GPTF input" bitfld.long 0x4 20. "PSELCE,ELC_GPTE Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTE input,1: Counter stop is enable at the ELC_GPTE input" newline bitfld.long 0x4 19. "PSELCD,ELC_GPTD Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTD input,1: Counter stop is enable at the ELC_GPTD input" bitfld.long 0x4 18. "PSELCC,ELC_GPTC Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTC input,1: Counter stop is enable at the ELC_GPTC input" newline bitfld.long 0x4 17. "PSELCB,ELC_GPTB Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTB input,1: Counter stop is enable at the ELC_GPTB input" bitfld.long 0x4 16. "PSELCA,ELC_GPTA Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTA input,1: Counter stop is enable at the ELC_GPTA input" newline bitfld.long 0x4 15. "PSCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." bitfld.long 0x4 14. "PSCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." newline bitfld.long 0x4 13. "PSCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." bitfld.long 0x4 12. "PSCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." newline bitfld.long 0x4 11. "PSCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." bitfld.long 0x4 10. "PSCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." newline bitfld.long 0x4 9. "PSCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." bitfld.long 0x4 8. "PSCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." newline hexmask.long.byte 0x4 4.--7. 1. "Reserved,These bits are read as 0000. The write value should be 0000." bitfld.long 0x4 3. "PSGTRGBF,GTETRGB Pin Falling Input Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." newline bitfld.long 0x4 2. "PSGTRGBR,GTETRGB Pin Rising Input Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." bitfld.long 0x4 1. "PSGTRGAF,GTETRGA Pin Falling Input Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." newline bitfld.long 0x4 0. "PSGTRGAR,GTETRGA Pin Rising Input Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." line.long 0x8 "GTCSR,General PWM Timer Clear Source Select Register" bitfld.long 0x8 31. "CCLR,Software Source Counter Clear Enable" "0: Counter clear is disable by the GTCLR register,1: Counter clear is enable by the GTCLR register" hexmask.long.byte 0x8 24.--30. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." newline bitfld.long 0x8 23. "CSELCH,ELC_GPTH Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTH input,1: Counter clear is enable at the ELC_GPTH input" bitfld.long 0x8 22. "CSELCG,ELC_GPTG Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTG input,1: Counter clear is enable at the ELC_GPTG input" newline bitfld.long 0x8 21. "CSELCF,ELC_GPTF Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTF input,1: Counter clear is enable at the ELC_GPTF input" bitfld.long 0x8 20. "CSELCE,ELC_GPTE Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTE input,1: Counter clear is enable at the ELC_GPTE input" newline bitfld.long 0x8 19. "CSELCD,ELC_GPTD Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTD input,1: Counter clear is enable at the ELC_GPTD input" bitfld.long 0x8 18. "CSELCC,ELC_GPTC Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTC input,1: Counter clear is enable at the ELC_GPTC input" newline bitfld.long 0x8 17. "CSELCB,ELC_GPTB Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTB input,1: Counter clear is enable at the ELC_GPTB input" bitfld.long 0x8 16. "CSELCA,ELC_GPTA Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTA input,1: Counter clear is enable at the ELC_GPTA input" newline bitfld.long 0x8 15. "CSCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." bitfld.long 0x8 14. "CSCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." newline bitfld.long 0x8 13. "CSCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." bitfld.long 0x8 12. "CSCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." newline bitfld.long 0x8 11. "CSCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." bitfld.long 0x8 10. "CSCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." newline bitfld.long 0x8 9. "CSCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." bitfld.long 0x8 8. "CSCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." newline hexmask.long.byte 0x8 4.--7. 1. "Reserved,These bits are read as 0000. The write value should be 0000." bitfld.long 0x8 3. "CSGTRGBF,GTETRGB Pin Falling Input Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." newline bitfld.long 0x8 2. "CSGTRGBR,GTETRGB Pin Rising Input Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." bitfld.long 0x8 1. "CSGTRGAF,GTETRGA Pin Falling Input Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." newline bitfld.long 0x8 0. "CSGTRGAR,GTETRGA Pin Rising Input Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." line.long 0xC "GTUPSR,General PWM Timer Up Count Source Select Register" bitfld.long 0xC 23. "USELCH,ELC_GPTH Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTH input,1: Counter count up is enable at the ELC_GPTH input" bitfld.long 0xC 22. "USELCG,ELC_GPTG Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTG input,1: Counter count up is enable at the ELC_GPTG input" newline bitfld.long 0xC 21. "USELCF,ELC_GPTF Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTF input,1: Counter count up is enable at the ELC_GPTF input" bitfld.long 0xC 20. "USELCE,ELC_GPTE Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTE input,1: Counter count up is enable at the ELC_GPTE input" newline bitfld.long 0xC 19. "USELCD,ELC_GPTD Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTD input,1: Counter count up is enable at the ELC_GPTD input" bitfld.long 0xC 18. "USELCC,ELC_GPTC Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTC input,1: Counter count up is enable at the ELC_GPTC input" newline bitfld.long 0xC 17. "USELCB,ELC_GPTB Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTB input,1: Counter count up is enable at the ELC_GPTB input" bitfld.long 0xC 16. "USELCA,ELC_GPTA Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTA input,1: Counter count up is enable at the ELC_GPTA input" newline bitfld.long 0xC 15. "USCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." bitfld.long 0xC 14. "USCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." newline bitfld.long 0xC 13. "USCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." bitfld.long 0xC 12. "USCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." newline bitfld.long 0xC 11. "USCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." bitfld.long 0xC 10. "USCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." newline bitfld.long 0xC 9. "USCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." bitfld.long 0xC 8. "USCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." newline bitfld.long 0xC 3. "USGTRGBF,GTETRGB Pin Falling Input Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." bitfld.long 0xC 2. "USGTRGBR,GTETRGB Pin Rising Input Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." newline bitfld.long 0xC 1. "USGTRGAF,GTETRGA Pin Falling Input Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." bitfld.long 0xC 0. "USGTRGAR,GTETRGA Pin Rising Input Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." line.long 0x10 "GTDNSR,General PWM Timer Down Count Source Select Register" bitfld.long 0x10 23. "DSELCH,ELC_GPTH Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTH..,1: Counter count down is enable at the ELC_GPTH input" bitfld.long 0x10 22. "DSELCG,ELC_GPTG Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTG..,1: Counter count down is enable at the ELC_GPTG input" newline bitfld.long 0x10 21. "DSELCF,ELC_GPTF Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTF..,1: Counter count down is enable at the ELC_GPTF input" bitfld.long 0x10 20. "DSELCE,ELC_GPTE Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTE..,1: Counter count down is enable at the ELC_GPTE input" newline bitfld.long 0x10 19. "DSELCD,ELC_GPTD Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTD..,1: Counter count down is enable at the ELC_GPTD input" bitfld.long 0x10 18. "DSELCC,ELC_GPTC Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTC..,1: Counter count down is enable at the ELC_GPTC input" newline bitfld.long 0x10 17. "DSELCB,ELC_GPTB Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTB..,1: Counter count down is enable at the ELC_GPTB input" bitfld.long 0x10 16. "DSELCA,ELC_GPTA Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTA..,1: Counter count down is enable at the ELC_GPTA input" newline bitfld.long 0x10 15. "DSCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." bitfld.long 0x10 14. "DSCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." newline bitfld.long 0x10 13. "DSCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." bitfld.long 0x10 12. "DSCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." newline bitfld.long 0x10 11. "DSCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." bitfld.long 0x10 10. "DSCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." newline bitfld.long 0x10 9. "DSCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." bitfld.long 0x10 8. "DSCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." newline bitfld.long 0x10 3. "DSGTRGBF,GTETRGB Pin Falling Input Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." bitfld.long 0x10 2. "DSGTRGBR,GTETRGB Pin Rising Input Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." newline bitfld.long 0x10 1. "DSGTRGAF,GTETRGA Pin Falling Input Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." bitfld.long 0x10 0. "DSGTRGAR,GTETRGA Pin Rising Input Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." line.long 0x14 "GTICASR,General PWM Timer Input Capture Source Select Register A" bitfld.long 0x14 23. "ASELCH,ELC_GPTH Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTH..,1: GTCCRA input capture is enable at the ELC_GPTH.." bitfld.long 0x14 22. "ASELCG,ELC_GPTG Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTG..,1: GTCCRA input capture is enable at the ELC_GPTG.." newline bitfld.long 0x14 21. "ASELCF,ELC_GPTF Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTF..,1: GTCCRA input capture is enable at the ELC_GPTF.." bitfld.long 0x14 20. "ASELCE,ELC_GPTE Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTE..,1: GTCCRA input capture is enable at the ELC_GPTE.." newline bitfld.long 0x14 19. "ASELCD,ELC_GPTD Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTD..,1: GTCCRA input capture is enable at the ELC_GPTD.." bitfld.long 0x14 18. "ASELCC,ELC_GPTC Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTC..,1: GTCCRA input capture is enable at the ELC_GPTC.." newline bitfld.long 0x14 17. "ASELCB,ELC_GPTB Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTB..,1: GTCCRA input capture is enable at the ELC_GPTB.." bitfld.long 0x14 16. "ASELCA,ELC_GPTA Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTA..,1: GTCCRA input capture is enable at the ELC_GPTA.." newline bitfld.long 0x14 15. "ASCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." bitfld.long 0x14 14. "ASCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." newline bitfld.long 0x14 13. "ASCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." bitfld.long 0x14 12. "ASCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." newline bitfld.long 0x14 11. "ASCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." bitfld.long 0x14 10. "ASCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." newline bitfld.long 0x14 9. "ASCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." bitfld.long 0x14 8. "ASCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." newline bitfld.long 0x14 3. "ASGTRGBF,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." bitfld.long 0x14 2. "ASGTRGBR,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." newline bitfld.long 0x14 1. "ASGTRGAF,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." bitfld.long 0x14 0. "ASGTRGAR,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." line.long 0x18 "GTICBSR,General PWM Timer Input Capture Source Select Register B" bitfld.long 0x18 23. "BSELCH,ELC_GPTH Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTH..,1: GTCCRB input capture is enable at the ELC_GPTH.." bitfld.long 0x18 22. "BSELCG,ELC_GPTG Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTG..,1: GTCCRB input capture is enable at the ELC_GPTG.." newline bitfld.long 0x18 21. "BSELCF,ELC_GPTF Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTF..,1: GTCCRB input capture is enable at the ELC_GPTF.." bitfld.long 0x18 20. "BSELCE,ELC_GPTE Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTE..,1: GTCCRB input capture is enable at the ELC_GPTE.." newline bitfld.long 0x18 19. "BSELCD,ELC_GPTD Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTD..,1: GTCCRB input capture is enable at the ELC_GPTD.." bitfld.long 0x18 18. "BSELCC,ELC_GPTC Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTC..,1: GTCCRB input capture is enable at the ELC_GPTC.." newline bitfld.long 0x18 17. "BSELCB,ELC_GPTB Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTB..,1: GTCCRB input capture is enable at the ELC_GPTB.." bitfld.long 0x18 16. "BSELCA,ELC_GPTA Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTA..,1: GTCCRB input capture is enable at the ELC_GPTA.." newline bitfld.long 0x18 15. "BSCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." bitfld.long 0x18 14. "BSCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." newline bitfld.long 0x18 13. "BSCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." bitfld.long 0x18 12. "BSCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." newline bitfld.long 0x18 11. "BSCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." bitfld.long 0x18 10. "BSCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." newline bitfld.long 0x18 9. "BSCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." bitfld.long 0x18 8. "BSCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." newline bitfld.long 0x18 3. "BSGTRGBF,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." bitfld.long 0x18 2. "BSGTRGBR,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." newline bitfld.long 0x18 1. "BSGTRGAF,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." bitfld.long 0x18 0. "BSGTRGAR,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." line.long 0x1C "GTCR,General PWM Timer Control Register" bitfld.long 0x1C 24.--26. "TPCS,Timer Prescaler Select" "0: Setting prohibied,1: PCLK/4,?,?,?,?,?,?" hexmask.long.byte 0x1C 19.--23. 1. "Reserved,These bits are read as 00000. The write value should be 00000." newline bitfld.long 0x1C 16.--18. "MD,Mode Select" "0: Saw-wave PWM mode (single buffer or double..,1: Saw-wave one-shot pulse mode (fixed buffer..,?,?,?,?,?,?" hexmask.long.word 0x1C 1.--15. 1. "Reserved,These bits are read as 000000000000000. The write value should be 000000000000000." newline bitfld.long 0x1C 0. "CST,Count Start" "0: Count operation is stopped,1: Count operation is performed" line.long 0x20 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register" bitfld.long 0x20 27. "OBDTYR,GTIOCB Output Value Selecting after Releasing 0 percent/100 percent Duty Setting" "0: Apply output value set in 0 percent/100 percent..,1: Apply masked compare match output value to.." bitfld.long 0x20 26. "OBDTYF,Forcible GTIOCB Output Duty Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x20 24.--25. "OBDTY,GTIOCB Output Duty Setting" "0: GTIOCB pin duty is depend on compare match,1: GTIOCB pin duty is depend on compare match,?,?" hexmask.long.byte 0x20 20.--23. 1. "Reserved,These bits are read as 0000. The write value should be 0000." newline bitfld.long 0x20 19. "OADTYR,GTIOCA Output Value Selecting after Releasing 0 percent/100 percent Duty Setting" "0: Apply output value set in 0 percent/100 percent..,1: Apply masked compare match output value to.." bitfld.long 0x20 18. "OADTYF,Forcible GTIOCA Output Duty Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x20 16.--17. "OADTY,GTIOCA Output Duty Setting" "0: GTIOCA pin duty is depend on compare match,1: GTIOCA pin duty is depend on compare match,?,?" bitfld.long 0x20 1. "UDF,Forcible Count Direction Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x20 0. "UD,Count Direction Setting" "0: GTCNT counts down.,1: GTCNT counts up." line.long 0x24 "GTIOR,General PWM Timer I/O Control Register" bitfld.long 0x24 30.--31. "NFCSB,Noise Filter B Sampling Clock Select" "0: PCLK/1,1: PCLK/4,?,?" bitfld.long 0x24 29. "NFBEN,Noise Filter B Enable" "0: The noise filter for the GTIOCB pin is disabled.,1: The noise filter for the GTIOCB pin is enabled." newline bitfld.long 0x24 27.--28. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.long 0x24 25.--26. "OBDF,GTIOCB Pin Disable Value Setting" "0: Output disable is prohibited.,1: GTIOCB pin is set to Hi-Z when output disable is..,?,?" newline bitfld.long 0x24 24. "OBE,GTIOCB Pin Output Enable" "0: Output is disabled,1: Output is enabled" bitfld.long 0x24 23. "OBHLD,GTIOCB Pin Output Setting at the Start/Stop Count" "0: The GTIOCB pin output level at start/stop of..,1: The GTIOCB pin output level is retained at.." newline bitfld.long 0x24 22. "OBDFLT,GTIOCB Pin Output Value Setting at the Count Stop" "0: The GTIOCB pin outputs low when counting is..,1: The GTIOCB pin outputs high when counting is.." bitfld.long 0x24 21. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline hexmask.long.byte 0x24 16.--20. 1. "GTIOB,GTIOCB Pin Function Select" bitfld.long 0x24 14.--15. "NFCSA,Noise Filter A Sampling Clock Select" "0: PCLK/1,1: PCLK/4,?,?" newline bitfld.long 0x24 13. "NFAEN,Noise Filter A Enable" "0: The noise filter for the GTIOCA pin is disabled.,1: The noise filter for the GTIOCA pin is enabled." bitfld.long 0x24 11.--12. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" newline bitfld.long 0x24 9.--10. "OADF,GTIOCA Pin Disable Value Setting" "0: Output disable is prohibited.,1: GTIOCA pin is set to Hi-Z when output disable is..,?,?" bitfld.long 0x24 8. "OAE,GTIOCA Pin Output Enable" "0: Output is disabled,1: Output is enabled" newline bitfld.long 0x24 7. "OAHLD,GTIOCA Pin Output Setting at the Start/Stop Count" "0: The GTIOCA pin output level at start/stop of..,1: The GTIOCA pin output level is retained at.." bitfld.long 0x24 6. "OADFLT,GTIOCA Pin Output Value Setting at the Count Stop" "0: The GTIOCA pin outputs low when counting is..,1: The GTIOCA pin outputs high when counting is.." newline bitfld.long 0x24 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" hexmask.long.byte 0x24 0.--4. 1. "GTIOA,GTIOCA Pin Function Select" line.long 0x28 "GTINTAD,General PWM Timer Interrupt Output Setting Register" bitfld.long 0x28 30. "GRPABL,Same Time Output Level Low Disable Request Enable" "0: Same time output level low disable request is..,1: Same time output level low disable request is.." bitfld.long 0x28 29. "GRPABH,Same Time Output Level High Disable Request Enable" "0: Same time output level high disable request is..,1: Same time output level high disable request is.." newline bitfld.long 0x28 26.--28. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.long 0x28 24.--25. "GRP,Output Disable Source Select" "0: Setting prohibited,1: Group B output disable request,?,?" newline hexmask.long.tbyte 0x28 0.--23. 1. "Reserved,These bits are read as 000000000000000000000000. The write value should be 000000000000000000000000." line.long 0x2C "GTST,General PWM Timer Status Register" rbitfld.long 0x2C 30. "OABLF,Same Time Output Level Low Disable Request Enable" "0: GTIOCA pin and GTIOCB pin don't output 0 at the..,1: GTIOCA pin and GTIOCB pin output 0 at the same.." rbitfld.long 0x2C 29. "OABHF,Same Time Output Level High Disable Request Enable" "0: GTIOCA pin and GTIOCB pin don't output 1 at the..,1: GTIOCA pin and GTIOCB pin output 1 at the same.." newline hexmask.long.byte 0x2C 25.--28. 1. "Reserved,These bits are read as 0000. The write value should be 0000." rbitfld.long 0x2C 24. "ODF,Output Disable Flag" "0: No output disable request is generated.,1: An output disable request is generated." newline hexmask.long.byte 0x2C 16.--23. 1. "Reserved,These bits are read as 00000000. The write value should be 00000000." rbitfld.long 0x2C 15. "TUCF,Count Direction Flag" "0: The GTCNT counter counts downward.,1: The GTCNT counter counts upward." newline hexmask.long.byte 0x2C 8.--14. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.long 0x2C 7. "TCFPU,Underflow Flag" "0: No underflow (trough) has occurred.,1: An underflow (trough) has occurred." newline bitfld.long 0x2C 6. "TCPFO,Overflow Flag" "0: No overflow (crest) has occurred.,1: An overflow (crest) has occurred." bitfld.long 0x2C 5. "TCFF,Input Compare Match Flag F" "0: No compare match of GTCCRF is generated.,1: A compare match of GTCCRF is generated." newline bitfld.long 0x2C 4. "TCFE,Input Compare Match Flag E" "0: No compare match of GTCCRE is generated.,1: A compare match of GTCCRE is generated." bitfld.long 0x2C 3. "TCFD,Input Compare Match Flag D" "0: No compare match of GTCCRD is generated.,1: A compare match of GTCCRD is generated." newline bitfld.long 0x2C 2. "TCFC,Input Compare Match Flag C" "0: No compare match of GTCCRC is generated.,1: A compare match of GTCCRC is generated." bitfld.long 0x2C 1. "TCFB,Input Capture/Compare Match Flag B" "0: No input capture/compare match of GTCCRB is..,1: An input capture/compare match of GTCCRB is.." newline bitfld.long 0x2C 0. "TCFA,Input Capture/Compare Match Flag A" "0: No input capture/compare match of GTCCRA is..,1: An input capture/compare match of GTCCRA is.." line.long 0x30 "GTBER,General PWM Timer Buffer Enable Register" bitfld.long 0x30 22. "CCRSWT,GTCCRA and GTCCRB Forcible Buffer OperationThis bit is read as 0." "0: no effect,1: Forcibly performs buffer transfer of GTCCRA and.." bitfld.long 0x30 20.--21. "PR,GTPR Buffer Operation" "0: Setting prohibited,1: Single buffer operation (GTPBR --> GTPR),?,?" newline bitfld.long 0x30 18.--19. "CCRB,GTCCRB Buffer Operation" "0: Buffer operation is not performed,1: Single buffer operation (GTCCRB <--> GTCCRE),?,?" bitfld.long 0x30 16.--17. "CCRA,GTCCRA Buffer Operation" "0: Buffer operation is not performed,1: Single buffer operation (GTCCRA <--> GTCCRC),?,?" newline bitfld.long 0x30 0.--1. "BD,BD[1]: GTPR Buffer Operation DisableBD[0]: GTCCR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled,?,?" group.long 0x48++0x23 line.long 0x0 "GTCNT,General PWM Timer Counter" hexmask.long 0x0 0.--31. 1. "GTCNT,Counter" line.long 0x4 "GTCCRA,General PWM Timer Compare Capture Register A" hexmask.long 0x4 0.--31. 1. "GTCCRA,Compare Capture Register A" line.long 0x8 "GTCCRB,General PWM Timer Compare Capture Register B" hexmask.long 0x8 0.--31. 1. "GTCCRB,Compare Capture Register B" line.long 0xC "GTCCRC,General PWM Timer Compare Capture Register C" hexmask.long 0xC 0.--31. 1. "GTCCRC,Compare Capture Register C" line.long 0x10 "GTCCRE,General PWM Timer Compare Capture Register E" hexmask.long 0x10 0.--31. 1. "GTCCRE,Compare Capture Register E" line.long 0x14 "GTCCRD,General PWM Timer Compare Capture Register D" hexmask.long 0x14 0.--31. 1. "GTCCRD,Compare Capture Register D" line.long 0x18 "GTCCRF,General PWM Timer Compare Capture Register F" hexmask.long 0x18 0.--31. 1. "GTCCRF,Compare Capture Register F" line.long 0x1C "GTPR,General PWM Timer Cycle Setting Register" hexmask.long 0x1C 0.--31. 1. "GTPR,Cycle Setting Register" line.long 0x20 "GTPBR,General PWM Timer Cycle Setting Buffer Register" hexmask.long 0x20 0.--31. 1. "GTPBR,Cycle Setting Buffer Register" group.long 0x88++0x7 line.long 0x0 "GTDTCR,General PWM Timer Dead Time Control Register" hexmask.long.tbyte 0x0 9.--31. 1. "Reserved,These bits are read as 00000000000000000000000. The write value should be 00000000000000000000000." bitfld.long 0x0 8. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.long 0x0 6.--7. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.long 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.long 0x0 4. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 1.--3. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "TDE,Negative-Phase Waveform Setting" "0: GTCCRB is set without using GTDVU and GTDVD.,1: GTDVU and GTDVD are used to set the compare.." line.long 0x4 "GTDVU,General PWM Timer Dead Time Value Register U" hexmask.long 0x4 0.--31. 1. "GTDVU,Dead Time Value Register U" tree.end tree "GPT165" base ad:0x40078500 group.long 0x0++0xB line.long 0x0 "GTWP,General PWM Timer Write-Protection Register" hexmask.long.word 0x0 16.--31. 1. "Reserved,These bits are read as 0000000000000000. The write value should be 0000000000000000." hexmask.long.byte 0x0 8.--15. 1. "PRKEY,GTWP Key Code" newline hexmask.long.byte 0x0 1.--7. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.long 0x0 0. "WP,Register Write Disable" "0: Write to the register is enabled,1: Write to the register is disabled" line.long 0x4 "GTSTR,General PWM Timer Software Start Register" hexmask.long.tbyte 0x4 10.--31. 1. "Reserved,These bits are read as 0000000000000000000000. The write value should be 0000000000000000000000." bitfld.long 0x4 9. "CSTRT9,Channel 9 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT169.GTCNT counter starts (write) / Counter.." newline bitfld.long 0x4 8. "CSTRT8,Channel 8 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT168.GTCNT counter starts (write) / Counter.." bitfld.long 0x4 7. "CSTRT7,Channel 7 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT167.GTCNT counter starts (write) / Counter.." newline bitfld.long 0x4 6. "CSTRT6,Channel 6 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT166.GTCNT counter starts (write) / Counter.." bitfld.long 0x4 5. "CSTRT5,Channel 5 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT165.GTCNT counter starts (write) / Counter.." newline bitfld.long 0x4 4. "CSTRT4,Channel 4 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT164.GTCNT counter starts (write) / Counter.." bitfld.long 0x4 3. "CSTRT3,Channel 3 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT323.GTCNT counter starts (write) / Counter.." newline bitfld.long 0x4 2. "CSTRT2,Channel 2 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT322.GTCNT counter starts (write) / Counter.." bitfld.long 0x4 1. "CSTRT1,Channel 1 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT321.GTCNT counter starts (write) / Counter.." newline bitfld.long 0x4 0. "CSTRT0,Channel 0 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT320.GTCNT counter starts (write) / Counter.." line.long 0x8 "GTSTP,General PWM Timer Software Stop Register" hexmask.long.tbyte 0x8 10.--31. 1. "Reserved,These bits are read as 1111111111111111111111. The write value should be 1111111111111111111111." bitfld.long 0x8 9. "CSTOP9,Channel 9 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT169.GTCNT counter stops (write) / Counter.." newline bitfld.long 0x8 8. "CSTOP8,Channel 8 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT168.GTCNT counter stops (write) / Counter.." bitfld.long 0x8 7. "CSTOP7,Channel 7 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT167.GTCNT counter stops (write) / Counter.." newline bitfld.long 0x8 6. "CSTOP6,Channel 6 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT166.GTCNT counter stops (write) / Counter.." bitfld.long 0x8 5. "CSTOP5,Channel 5 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT165.GTCNT counter stops (write) / Counter.." newline bitfld.long 0x8 4. "CSTOP4,Channel 4 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT164.GTCNT counter stops (write) / Counter.." bitfld.long 0x8 3. "CSTOP3,Channel 3 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT323.GTCNT counter stops (write) / Counter.." newline bitfld.long 0x8 2. "CSTOP2,Channel 2 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT322.GTCNT counter stops (write) / Counter.." bitfld.long 0x8 1. "CSTOP1,Channel 1 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT321.GTCNT counter stops (write) / Counter.." newline bitfld.long 0x8 0. "CSTOP0,Channel 0 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT320.GTCNT counter stops (write) / Counter.." wgroup.long 0xC++0x3 line.long 0x0 "GTCLR,General PWM Timer Software Clear Register" hexmask.long.tbyte 0x0 10.--31. 1. "Reserved,The write value should be 0000000000000000000000." bitfld.long 0x0 9. "CCLR9,Channel 9 GTCNT Count Clear" "0: No effect,1: GPT169.GTCNT counter clears" newline bitfld.long 0x0 8. "CCLR8,Channel 8 GTCNT Count Clear" "0: No effect,1: GPT168.GTCNT counter clears" bitfld.long 0x0 7. "CCLR7,Channel 7 GTCNT Count Clear" "0: No effect,1: GPT167.GTCNT counter clears" newline bitfld.long 0x0 6. "CCLR6,Channel 6 GTCNT Count Clear" "0: No effect,1: GPT166.GTCNT counter clears" bitfld.long 0x0 5. "CCLR5,Channel 5 GTCNT Count Clear" "0: No effect,1: GPT165.GTCNT counter clears" newline bitfld.long 0x0 4. "CCLR4,Channel 4 GTCNT Count Clear" "0: No effect,1: GPT164.GTCNT counter clears" bitfld.long 0x0 3. "CCLR3,Channel 3 GTCNT Count Clear" "0: No effect,1: GPT323.GTCNT counter clears" newline bitfld.long 0x0 2. "CCLR2,Channel 2 GTCNT Count Clear" "0: No effect,1: GPT322.GTCNT counter clears" bitfld.long 0x0 1. "CCLR1,Channel 1 GTCNT Count Clear" "0: No effect,1: GPT321.GTCNT counter clears" newline bitfld.long 0x0 0. "CCLR0,Channel 0 GTCNT Count Clear" "0: No effect,1: GPT320.GTCNT counter clears" group.long 0x10++0x33 line.long 0x0 "GTSSR,General PWM Timer Start Source Select Register" bitfld.long 0x0 31. "CSTRT,Software Source Counter Start Enable" "0: Counter start is disable by the GTSTR register,1: Counter start is enable by the GTSTR register" hexmask.long.byte 0x0 24.--30. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." newline bitfld.long 0x0 23. "SSELCH,ELC_GPTH Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTH input,1: Counter start is enable at the ELC_GPTH input" bitfld.long 0x0 22. "SSELCG,ELC_GPTG Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTG input,1: Counter start is enable at the ELC_GPTG input" newline bitfld.long 0x0 21. "SSELCF,ELC_GPTF Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTF input,1: Counter start is enable at the ELC_GPTF input" bitfld.long 0x0 20. "SSELCE,ELC_GPTE Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTE input,1: Counter start is enable at the ELC_GPTE input" newline bitfld.long 0x0 19. "SSELCD,ELC_GPTD Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTD input,1: Counter start is enable at the ELC_GPTD input" bitfld.long 0x0 18. "SSELCC,ELC_GPTC Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTC input,1: Counter start is enable at the ELC_GPTC input" newline bitfld.long 0x0 17. "SSELCB,ELC_GPTB Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTB input,1: Counter start is enable at the ELC_GPTB input" bitfld.long 0x0 16. "SSELCA,ELC_GPTA Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTA input,1: Counter start is enable at the ELC_GPTA input" newline bitfld.long 0x0 15. "SSCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." bitfld.long 0x0 14. "SSCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." newline bitfld.long 0x0 13. "SSCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." bitfld.long 0x0 12. "SSCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." newline bitfld.long 0x0 11. "SSCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." bitfld.long 0x0 10. "SSCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." newline bitfld.long 0x0 9. "SSCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." bitfld.long 0x0 8. "SSCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." newline hexmask.long.byte 0x0 4.--7. 1. "Reserved,These bits are read as 0000. The write value should be 0000." bitfld.long 0x0 3. "SSGTRGBF,GTETRGB Pin Falling Input Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." newline bitfld.long 0x0 2. "SSGTRGBR,GTETRGB Pin Rising Input Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." bitfld.long 0x0 1. "SSGTRGAF,GTETRGA Pin Falling Input Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." newline bitfld.long 0x0 0. "SSGTRGAR,GTETRGA Pin Rising Input Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." line.long 0x4 "GTPSR,General PWM Timer Stop Source Select Register" bitfld.long 0x4 31. "CSTOP,Software Source Counter Stop Enable" "0: Counter stop is disable by the GTSTP register,1: Counter stop is enable by the GTSTP register" hexmask.long.byte 0x4 24.--30. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." newline bitfld.long 0x4 23. "PSELCH,ELC_GPTH Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTH input,1: Counter stop is enable at the ELC_GPTH input" bitfld.long 0x4 22. "PSELCG,ELC_GPTG Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTG input,1: Counter stop is enable at the ELC_GPTG input" newline bitfld.long 0x4 21. "PSELCF,ELC_GPTF Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTF input,1: Counter stop is enable at the ELC_GPTF input" bitfld.long 0x4 20. "PSELCE,ELC_GPTE Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTE input,1: Counter stop is enable at the ELC_GPTE input" newline bitfld.long 0x4 19. "PSELCD,ELC_GPTD Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTD input,1: Counter stop is enable at the ELC_GPTD input" bitfld.long 0x4 18. "PSELCC,ELC_GPTC Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTC input,1: Counter stop is enable at the ELC_GPTC input" newline bitfld.long 0x4 17. "PSELCB,ELC_GPTB Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTB input,1: Counter stop is enable at the ELC_GPTB input" bitfld.long 0x4 16. "PSELCA,ELC_GPTA Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTA input,1: Counter stop is enable at the ELC_GPTA input" newline bitfld.long 0x4 15. "PSCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." bitfld.long 0x4 14. "PSCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." newline bitfld.long 0x4 13. "PSCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." bitfld.long 0x4 12. "PSCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." newline bitfld.long 0x4 11. "PSCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." bitfld.long 0x4 10. "PSCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." newline bitfld.long 0x4 9. "PSCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." bitfld.long 0x4 8. "PSCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." newline hexmask.long.byte 0x4 4.--7. 1. "Reserved,These bits are read as 0000. The write value should be 0000." bitfld.long 0x4 3. "PSGTRGBF,GTETRGB Pin Falling Input Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." newline bitfld.long 0x4 2. "PSGTRGBR,GTETRGB Pin Rising Input Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." bitfld.long 0x4 1. "PSGTRGAF,GTETRGA Pin Falling Input Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." newline bitfld.long 0x4 0. "PSGTRGAR,GTETRGA Pin Rising Input Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." line.long 0x8 "GTCSR,General PWM Timer Clear Source Select Register" bitfld.long 0x8 31. "CCLR,Software Source Counter Clear Enable" "0: Counter clear is disable by the GTCLR register,1: Counter clear is enable by the GTCLR register" hexmask.long.byte 0x8 24.--30. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." newline bitfld.long 0x8 23. "CSELCH,ELC_GPTH Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTH input,1: Counter clear is enable at the ELC_GPTH input" bitfld.long 0x8 22. "CSELCG,ELC_GPTG Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTG input,1: Counter clear is enable at the ELC_GPTG input" newline bitfld.long 0x8 21. "CSELCF,ELC_GPTF Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTF input,1: Counter clear is enable at the ELC_GPTF input" bitfld.long 0x8 20. "CSELCE,ELC_GPTE Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTE input,1: Counter clear is enable at the ELC_GPTE input" newline bitfld.long 0x8 19. "CSELCD,ELC_GPTD Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTD input,1: Counter clear is enable at the ELC_GPTD input" bitfld.long 0x8 18. "CSELCC,ELC_GPTC Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTC input,1: Counter clear is enable at the ELC_GPTC input" newline bitfld.long 0x8 17. "CSELCB,ELC_GPTB Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTB input,1: Counter clear is enable at the ELC_GPTB input" bitfld.long 0x8 16. "CSELCA,ELC_GPTA Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTA input,1: Counter clear is enable at the ELC_GPTA input" newline bitfld.long 0x8 15. "CSCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." bitfld.long 0x8 14. "CSCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." newline bitfld.long 0x8 13. "CSCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." bitfld.long 0x8 12. "CSCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." newline bitfld.long 0x8 11. "CSCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." bitfld.long 0x8 10. "CSCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." newline bitfld.long 0x8 9. "CSCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." bitfld.long 0x8 8. "CSCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." newline hexmask.long.byte 0x8 4.--7. 1. "Reserved,These bits are read as 0000. The write value should be 0000." bitfld.long 0x8 3. "CSGTRGBF,GTETRGB Pin Falling Input Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." newline bitfld.long 0x8 2. "CSGTRGBR,GTETRGB Pin Rising Input Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." bitfld.long 0x8 1. "CSGTRGAF,GTETRGA Pin Falling Input Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." newline bitfld.long 0x8 0. "CSGTRGAR,GTETRGA Pin Rising Input Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." line.long 0xC "GTUPSR,General PWM Timer Up Count Source Select Register" bitfld.long 0xC 23. "USELCH,ELC_GPTH Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTH input,1: Counter count up is enable at the ELC_GPTH input" bitfld.long 0xC 22. "USELCG,ELC_GPTG Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTG input,1: Counter count up is enable at the ELC_GPTG input" newline bitfld.long 0xC 21. "USELCF,ELC_GPTF Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTF input,1: Counter count up is enable at the ELC_GPTF input" bitfld.long 0xC 20. "USELCE,ELC_GPTE Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTE input,1: Counter count up is enable at the ELC_GPTE input" newline bitfld.long 0xC 19. "USELCD,ELC_GPTD Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTD input,1: Counter count up is enable at the ELC_GPTD input" bitfld.long 0xC 18. "USELCC,ELC_GPTC Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTC input,1: Counter count up is enable at the ELC_GPTC input" newline bitfld.long 0xC 17. "USELCB,ELC_GPTB Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTB input,1: Counter count up is enable at the ELC_GPTB input" bitfld.long 0xC 16. "USELCA,ELC_GPTA Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTA input,1: Counter count up is enable at the ELC_GPTA input" newline bitfld.long 0xC 15. "USCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." bitfld.long 0xC 14. "USCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." newline bitfld.long 0xC 13. "USCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." bitfld.long 0xC 12. "USCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." newline bitfld.long 0xC 11. "USCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." bitfld.long 0xC 10. "USCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." newline bitfld.long 0xC 9. "USCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." bitfld.long 0xC 8. "USCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." newline bitfld.long 0xC 3. "USGTRGBF,GTETRGB Pin Falling Input Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." bitfld.long 0xC 2. "USGTRGBR,GTETRGB Pin Rising Input Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." newline bitfld.long 0xC 1. "USGTRGAF,GTETRGA Pin Falling Input Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." bitfld.long 0xC 0. "USGTRGAR,GTETRGA Pin Rising Input Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." line.long 0x10 "GTDNSR,General PWM Timer Down Count Source Select Register" bitfld.long 0x10 23. "DSELCH,ELC_GPTH Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTH..,1: Counter count down is enable at the ELC_GPTH input" bitfld.long 0x10 22. "DSELCG,ELC_GPTG Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTG..,1: Counter count down is enable at the ELC_GPTG input" newline bitfld.long 0x10 21. "DSELCF,ELC_GPTF Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTF..,1: Counter count down is enable at the ELC_GPTF input" bitfld.long 0x10 20. "DSELCE,ELC_GPTE Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTE..,1: Counter count down is enable at the ELC_GPTE input" newline bitfld.long 0x10 19. "DSELCD,ELC_GPTD Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTD..,1: Counter count down is enable at the ELC_GPTD input" bitfld.long 0x10 18. "DSELCC,ELC_GPTC Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTC..,1: Counter count down is enable at the ELC_GPTC input" newline bitfld.long 0x10 17. "DSELCB,ELC_GPTB Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTB..,1: Counter count down is enable at the ELC_GPTB input" bitfld.long 0x10 16. "DSELCA,ELC_GPTA Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTA..,1: Counter count down is enable at the ELC_GPTA input" newline bitfld.long 0x10 15. "DSCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." bitfld.long 0x10 14. "DSCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." newline bitfld.long 0x10 13. "DSCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." bitfld.long 0x10 12. "DSCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." newline bitfld.long 0x10 11. "DSCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." bitfld.long 0x10 10. "DSCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." newline bitfld.long 0x10 9. "DSCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." bitfld.long 0x10 8. "DSCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." newline bitfld.long 0x10 3. "DSGTRGBF,GTETRGB Pin Falling Input Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." bitfld.long 0x10 2. "DSGTRGBR,GTETRGB Pin Rising Input Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." newline bitfld.long 0x10 1. "DSGTRGAF,GTETRGA Pin Falling Input Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." bitfld.long 0x10 0. "DSGTRGAR,GTETRGA Pin Rising Input Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." line.long 0x14 "GTICASR,General PWM Timer Input Capture Source Select Register A" bitfld.long 0x14 23. "ASELCH,ELC_GPTH Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTH..,1: GTCCRA input capture is enable at the ELC_GPTH.." bitfld.long 0x14 22. "ASELCG,ELC_GPTG Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTG..,1: GTCCRA input capture is enable at the ELC_GPTG.." newline bitfld.long 0x14 21. "ASELCF,ELC_GPTF Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTF..,1: GTCCRA input capture is enable at the ELC_GPTF.." bitfld.long 0x14 20. "ASELCE,ELC_GPTE Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTE..,1: GTCCRA input capture is enable at the ELC_GPTE.." newline bitfld.long 0x14 19. "ASELCD,ELC_GPTD Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTD..,1: GTCCRA input capture is enable at the ELC_GPTD.." bitfld.long 0x14 18. "ASELCC,ELC_GPTC Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTC..,1: GTCCRA input capture is enable at the ELC_GPTC.." newline bitfld.long 0x14 17. "ASELCB,ELC_GPTB Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTB..,1: GTCCRA input capture is enable at the ELC_GPTB.." bitfld.long 0x14 16. "ASELCA,ELC_GPTA Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTA..,1: GTCCRA input capture is enable at the ELC_GPTA.." newline bitfld.long 0x14 15. "ASCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." bitfld.long 0x14 14. "ASCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." newline bitfld.long 0x14 13. "ASCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." bitfld.long 0x14 12. "ASCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." newline bitfld.long 0x14 11. "ASCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." bitfld.long 0x14 10. "ASCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." newline bitfld.long 0x14 9. "ASCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." bitfld.long 0x14 8. "ASCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." newline bitfld.long 0x14 3. "ASGTRGBF,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." bitfld.long 0x14 2. "ASGTRGBR,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." newline bitfld.long 0x14 1. "ASGTRGAF,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." bitfld.long 0x14 0. "ASGTRGAR,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." line.long 0x18 "GTICBSR,General PWM Timer Input Capture Source Select Register B" bitfld.long 0x18 23. "BSELCH,ELC_GPTH Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTH..,1: GTCCRB input capture is enable at the ELC_GPTH.." bitfld.long 0x18 22. "BSELCG,ELC_GPTG Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTG..,1: GTCCRB input capture is enable at the ELC_GPTG.." newline bitfld.long 0x18 21. "BSELCF,ELC_GPTF Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTF..,1: GTCCRB input capture is enable at the ELC_GPTF.." bitfld.long 0x18 20. "BSELCE,ELC_GPTE Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTE..,1: GTCCRB input capture is enable at the ELC_GPTE.." newline bitfld.long 0x18 19. "BSELCD,ELC_GPTD Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTD..,1: GTCCRB input capture is enable at the ELC_GPTD.." bitfld.long 0x18 18. "BSELCC,ELC_GPTC Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTC..,1: GTCCRB input capture is enable at the ELC_GPTC.." newline bitfld.long 0x18 17. "BSELCB,ELC_GPTB Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTB..,1: GTCCRB input capture is enable at the ELC_GPTB.." bitfld.long 0x18 16. "BSELCA,ELC_GPTA Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTA..,1: GTCCRB input capture is enable at the ELC_GPTA.." newline bitfld.long 0x18 15. "BSCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." bitfld.long 0x18 14. "BSCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." newline bitfld.long 0x18 13. "BSCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." bitfld.long 0x18 12. "BSCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." newline bitfld.long 0x18 11. "BSCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." bitfld.long 0x18 10. "BSCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." newline bitfld.long 0x18 9. "BSCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." bitfld.long 0x18 8. "BSCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." newline bitfld.long 0x18 3. "BSGTRGBF,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." bitfld.long 0x18 2. "BSGTRGBR,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." newline bitfld.long 0x18 1. "BSGTRGAF,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." bitfld.long 0x18 0. "BSGTRGAR,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." line.long 0x1C "GTCR,General PWM Timer Control Register" bitfld.long 0x1C 24.--26. "TPCS,Timer Prescaler Select" "0: Setting prohibied,1: PCLK/4,?,?,?,?,?,?" hexmask.long.byte 0x1C 19.--23. 1. "Reserved,These bits are read as 00000. The write value should be 00000." newline bitfld.long 0x1C 16.--18. "MD,Mode Select" "0: Saw-wave PWM mode (single buffer or double..,1: Saw-wave one-shot pulse mode (fixed buffer..,?,?,?,?,?,?" hexmask.long.word 0x1C 1.--15. 1. "Reserved,These bits are read as 000000000000000. The write value should be 000000000000000." newline bitfld.long 0x1C 0. "CST,Count Start" "0: Count operation is stopped,1: Count operation is performed" line.long 0x20 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register" bitfld.long 0x20 27. "OBDTYR,GTIOCB Output Value Selecting after Releasing 0 percent/100 percent Duty Setting" "0: Apply output value set in 0 percent/100 percent..,1: Apply masked compare match output value to.." bitfld.long 0x20 26. "OBDTYF,Forcible GTIOCB Output Duty Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x20 24.--25. "OBDTY,GTIOCB Output Duty Setting" "0: GTIOCB pin duty is depend on compare match,1: GTIOCB pin duty is depend on compare match,?,?" hexmask.long.byte 0x20 20.--23. 1. "Reserved,These bits are read as 0000. The write value should be 0000." newline bitfld.long 0x20 19. "OADTYR,GTIOCA Output Value Selecting after Releasing 0 percent/100 percent Duty Setting" "0: Apply output value set in 0 percent/100 percent..,1: Apply masked compare match output value to.." bitfld.long 0x20 18. "OADTYF,Forcible GTIOCA Output Duty Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x20 16.--17. "OADTY,GTIOCA Output Duty Setting" "0: GTIOCA pin duty is depend on compare match,1: GTIOCA pin duty is depend on compare match,?,?" bitfld.long 0x20 1. "UDF,Forcible Count Direction Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x20 0. "UD,Count Direction Setting" "0: GTCNT counts down.,1: GTCNT counts up." line.long 0x24 "GTIOR,General PWM Timer I/O Control Register" bitfld.long 0x24 30.--31. "NFCSB,Noise Filter B Sampling Clock Select" "0: PCLK/1,1: PCLK/4,?,?" bitfld.long 0x24 29. "NFBEN,Noise Filter B Enable" "0: The noise filter for the GTIOCB pin is disabled.,1: The noise filter for the GTIOCB pin is enabled." newline bitfld.long 0x24 27.--28. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.long 0x24 25.--26. "OBDF,GTIOCB Pin Disable Value Setting" "0: Output disable is prohibited.,1: GTIOCB pin is set to Hi-Z when output disable is..,?,?" newline bitfld.long 0x24 24. "OBE,GTIOCB Pin Output Enable" "0: Output is disabled,1: Output is enabled" bitfld.long 0x24 23. "OBHLD,GTIOCB Pin Output Setting at the Start/Stop Count" "0: The GTIOCB pin output level at start/stop of..,1: The GTIOCB pin output level is retained at.." newline bitfld.long 0x24 22. "OBDFLT,GTIOCB Pin Output Value Setting at the Count Stop" "0: The GTIOCB pin outputs low when counting is..,1: The GTIOCB pin outputs high when counting is.." bitfld.long 0x24 21. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline hexmask.long.byte 0x24 16.--20. 1. "GTIOB,GTIOCB Pin Function Select" bitfld.long 0x24 14.--15. "NFCSA,Noise Filter A Sampling Clock Select" "0: PCLK/1,1: PCLK/4,?,?" newline bitfld.long 0x24 13. "NFAEN,Noise Filter A Enable" "0: The noise filter for the GTIOCA pin is disabled.,1: The noise filter for the GTIOCA pin is enabled." bitfld.long 0x24 11.--12. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" newline bitfld.long 0x24 9.--10. "OADF,GTIOCA Pin Disable Value Setting" "0: Output disable is prohibited.,1: GTIOCA pin is set to Hi-Z when output disable is..,?,?" bitfld.long 0x24 8. "OAE,GTIOCA Pin Output Enable" "0: Output is disabled,1: Output is enabled" newline bitfld.long 0x24 7. "OAHLD,GTIOCA Pin Output Setting at the Start/Stop Count" "0: The GTIOCA pin output level at start/stop of..,1: The GTIOCA pin output level is retained at.." bitfld.long 0x24 6. "OADFLT,GTIOCA Pin Output Value Setting at the Count Stop" "0: The GTIOCA pin outputs low when counting is..,1: The GTIOCA pin outputs high when counting is.." newline bitfld.long 0x24 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" hexmask.long.byte 0x24 0.--4. 1. "GTIOA,GTIOCA Pin Function Select" line.long 0x28 "GTINTAD,General PWM Timer Interrupt Output Setting Register" bitfld.long 0x28 30. "GRPABL,Same Time Output Level Low Disable Request Enable" "0: Same time output level low disable request is..,1: Same time output level low disable request is.." bitfld.long 0x28 29. "GRPABH,Same Time Output Level High Disable Request Enable" "0: Same time output level high disable request is..,1: Same time output level high disable request is.." newline bitfld.long 0x28 26.--28. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.long 0x28 24.--25. "GRP,Output Disable Source Select" "0: Setting prohibited,1: Group B output disable request,?,?" newline hexmask.long.tbyte 0x28 0.--23. 1. "Reserved,These bits are read as 000000000000000000000000. The write value should be 000000000000000000000000." line.long 0x2C "GTST,General PWM Timer Status Register" rbitfld.long 0x2C 30. "OABLF,Same Time Output Level Low Disable Request Enable" "0: GTIOCA pin and GTIOCB pin don't output 0 at the..,1: GTIOCA pin and GTIOCB pin output 0 at the same.." rbitfld.long 0x2C 29. "OABHF,Same Time Output Level High Disable Request Enable" "0: GTIOCA pin and GTIOCB pin don't output 1 at the..,1: GTIOCA pin and GTIOCB pin output 1 at the same.." newline hexmask.long.byte 0x2C 25.--28. 1. "Reserved,These bits are read as 0000. The write value should be 0000." rbitfld.long 0x2C 24. "ODF,Output Disable Flag" "0: No output disable request is generated.,1: An output disable request is generated." newline hexmask.long.byte 0x2C 16.--23. 1. "Reserved,These bits are read as 00000000. The write value should be 00000000." rbitfld.long 0x2C 15. "TUCF,Count Direction Flag" "0: The GTCNT counter counts downward.,1: The GTCNT counter counts upward." newline hexmask.long.byte 0x2C 8.--14. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.long 0x2C 7. "TCFPU,Underflow Flag" "0: No underflow (trough) has occurred.,1: An underflow (trough) has occurred." newline bitfld.long 0x2C 6. "TCPFO,Overflow Flag" "0: No overflow (crest) has occurred.,1: An overflow (crest) has occurred." bitfld.long 0x2C 5. "TCFF,Input Compare Match Flag F" "0: No compare match of GTCCRF is generated.,1: A compare match of GTCCRF is generated." newline bitfld.long 0x2C 4. "TCFE,Input Compare Match Flag E" "0: No compare match of GTCCRE is generated.,1: A compare match of GTCCRE is generated." bitfld.long 0x2C 3. "TCFD,Input Compare Match Flag D" "0: No compare match of GTCCRD is generated.,1: A compare match of GTCCRD is generated." newline bitfld.long 0x2C 2. "TCFC,Input Compare Match Flag C" "0: No compare match of GTCCRC is generated.,1: A compare match of GTCCRC is generated." bitfld.long 0x2C 1. "TCFB,Input Capture/Compare Match Flag B" "0: No input capture/compare match of GTCCRB is..,1: An input capture/compare match of GTCCRB is.." newline bitfld.long 0x2C 0. "TCFA,Input Capture/Compare Match Flag A" "0: No input capture/compare match of GTCCRA is..,1: An input capture/compare match of GTCCRA is.." line.long 0x30 "GTBER,General PWM Timer Buffer Enable Register" bitfld.long 0x30 22. "CCRSWT,GTCCRA and GTCCRB Forcible Buffer OperationThis bit is read as 0." "0: no effect,1: Forcibly performs buffer transfer of GTCCRA and.." bitfld.long 0x30 20.--21. "PR,GTPR Buffer Operation" "0: Setting prohibited,1: Single buffer operation (GTPBR --> GTPR),?,?" newline bitfld.long 0x30 18.--19. "CCRB,GTCCRB Buffer Operation" "0: Buffer operation is not performed,1: Single buffer operation (GTCCRB <--> GTCCRE),?,?" bitfld.long 0x30 16.--17. "CCRA,GTCCRA Buffer Operation" "0: Buffer operation is not performed,1: Single buffer operation (GTCCRA <--> GTCCRC),?,?" newline bitfld.long 0x30 0.--1. "BD,BD[1]: GTPR Buffer Operation DisableBD[0]: GTCCR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled,?,?" group.long 0x48++0x23 line.long 0x0 "GTCNT,General PWM Timer Counter" hexmask.long 0x0 0.--31. 1. "GTCNT,Counter" line.long 0x4 "GTCCRA,General PWM Timer Compare Capture Register A" hexmask.long 0x4 0.--31. 1. "GTCCRA,Compare Capture Register A" line.long 0x8 "GTCCRB,General PWM Timer Compare Capture Register B" hexmask.long 0x8 0.--31. 1. "GTCCRB,Compare Capture Register B" line.long 0xC "GTCCRC,General PWM Timer Compare Capture Register C" hexmask.long 0xC 0.--31. 1. "GTCCRC,Compare Capture Register C" line.long 0x10 "GTCCRE,General PWM Timer Compare Capture Register E" hexmask.long 0x10 0.--31. 1. "GTCCRE,Compare Capture Register E" line.long 0x14 "GTCCRD,General PWM Timer Compare Capture Register D" hexmask.long 0x14 0.--31. 1. "GTCCRD,Compare Capture Register D" line.long 0x18 "GTCCRF,General PWM Timer Compare Capture Register F" hexmask.long 0x18 0.--31. 1. "GTCCRF,Compare Capture Register F" line.long 0x1C "GTPR,General PWM Timer Cycle Setting Register" hexmask.long 0x1C 0.--31. 1. "GTPR,Cycle Setting Register" line.long 0x20 "GTPBR,General PWM Timer Cycle Setting Buffer Register" hexmask.long 0x20 0.--31. 1. "GTPBR,Cycle Setting Buffer Register" group.long 0x88++0x7 line.long 0x0 "GTDTCR,General PWM Timer Dead Time Control Register" hexmask.long.tbyte 0x0 9.--31. 1. "Reserved,These bits are read as 00000000000000000000000. The write value should be 00000000000000000000000." bitfld.long 0x0 8. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.long 0x0 6.--7. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.long 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.long 0x0 4. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 1.--3. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "TDE,Negative-Phase Waveform Setting" "0: GTCCRB is set without using GTDVU and GTDVD.,1: GTDVU and GTDVD are used to set the compare.." line.long 0x4 "GTDVU,General PWM Timer Dead Time Value Register U" hexmask.long 0x4 0.--31. 1. "GTDVU,Dead Time Value Register U" tree.end tree "GPT166" base ad:0x40078600 group.long 0x0++0xB line.long 0x0 "GTWP,General PWM Timer Write-Protection Register" hexmask.long.word 0x0 16.--31. 1. "Reserved,These bits are read as 0000000000000000. The write value should be 0000000000000000." hexmask.long.byte 0x0 8.--15. 1. "PRKEY,GTWP Key Code" newline hexmask.long.byte 0x0 1.--7. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.long 0x0 0. "WP,Register Write Disable" "0: Write to the register is enabled,1: Write to the register is disabled" line.long 0x4 "GTSTR,General PWM Timer Software Start Register" hexmask.long.tbyte 0x4 10.--31. 1. "Reserved,These bits are read as 0000000000000000000000. The write value should be 0000000000000000000000." bitfld.long 0x4 9. "CSTRT9,Channel 9 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT169.GTCNT counter starts (write) / Counter.." newline bitfld.long 0x4 8. "CSTRT8,Channel 8 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT168.GTCNT counter starts (write) / Counter.." bitfld.long 0x4 7. "CSTRT7,Channel 7 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT167.GTCNT counter starts (write) / Counter.." newline bitfld.long 0x4 6. "CSTRT6,Channel 6 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT166.GTCNT counter starts (write) / Counter.." bitfld.long 0x4 5. "CSTRT5,Channel 5 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT165.GTCNT counter starts (write) / Counter.." newline bitfld.long 0x4 4. "CSTRT4,Channel 4 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT164.GTCNT counter starts (write) / Counter.." bitfld.long 0x4 3. "CSTRT3,Channel 3 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT323.GTCNT counter starts (write) / Counter.." newline bitfld.long 0x4 2. "CSTRT2,Channel 2 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT322.GTCNT counter starts (write) / Counter.." bitfld.long 0x4 1. "CSTRT1,Channel 1 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT321.GTCNT counter starts (write) / Counter.." newline bitfld.long 0x4 0. "CSTRT0,Channel 0 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT320.GTCNT counter starts (write) / Counter.." line.long 0x8 "GTSTP,General PWM Timer Software Stop Register" hexmask.long.tbyte 0x8 10.--31. 1. "Reserved,These bits are read as 1111111111111111111111. The write value should be 1111111111111111111111." bitfld.long 0x8 9. "CSTOP9,Channel 9 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT169.GTCNT counter stops (write) / Counter.." newline bitfld.long 0x8 8. "CSTOP8,Channel 8 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT168.GTCNT counter stops (write) / Counter.." bitfld.long 0x8 7. "CSTOP7,Channel 7 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT167.GTCNT counter stops (write) / Counter.." newline bitfld.long 0x8 6. "CSTOP6,Channel 6 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT166.GTCNT counter stops (write) / Counter.." bitfld.long 0x8 5. "CSTOP5,Channel 5 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT165.GTCNT counter stops (write) / Counter.." newline bitfld.long 0x8 4. "CSTOP4,Channel 4 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT164.GTCNT counter stops (write) / Counter.." bitfld.long 0x8 3. "CSTOP3,Channel 3 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT323.GTCNT counter stops (write) / Counter.." newline bitfld.long 0x8 2. "CSTOP2,Channel 2 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT322.GTCNT counter stops (write) / Counter.." bitfld.long 0x8 1. "CSTOP1,Channel 1 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT321.GTCNT counter stops (write) / Counter.." newline bitfld.long 0x8 0. "CSTOP0,Channel 0 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT320.GTCNT counter stops (write) / Counter.." wgroup.long 0xC++0x3 line.long 0x0 "GTCLR,General PWM Timer Software Clear Register" hexmask.long.tbyte 0x0 10.--31. 1. "Reserved,The write value should be 0000000000000000000000." bitfld.long 0x0 9. "CCLR9,Channel 9 GTCNT Count Clear" "0: No effect,1: GPT169.GTCNT counter clears" newline bitfld.long 0x0 8. "CCLR8,Channel 8 GTCNT Count Clear" "0: No effect,1: GPT168.GTCNT counter clears" bitfld.long 0x0 7. "CCLR7,Channel 7 GTCNT Count Clear" "0: No effect,1: GPT167.GTCNT counter clears" newline bitfld.long 0x0 6. "CCLR6,Channel 6 GTCNT Count Clear" "0: No effect,1: GPT166.GTCNT counter clears" bitfld.long 0x0 5. "CCLR5,Channel 5 GTCNT Count Clear" "0: No effect,1: GPT165.GTCNT counter clears" newline bitfld.long 0x0 4. "CCLR4,Channel 4 GTCNT Count Clear" "0: No effect,1: GPT164.GTCNT counter clears" bitfld.long 0x0 3. "CCLR3,Channel 3 GTCNT Count Clear" "0: No effect,1: GPT323.GTCNT counter clears" newline bitfld.long 0x0 2. "CCLR2,Channel 2 GTCNT Count Clear" "0: No effect,1: GPT322.GTCNT counter clears" bitfld.long 0x0 1. "CCLR1,Channel 1 GTCNT Count Clear" "0: No effect,1: GPT321.GTCNT counter clears" newline bitfld.long 0x0 0. "CCLR0,Channel 0 GTCNT Count Clear" "0: No effect,1: GPT320.GTCNT counter clears" group.long 0x10++0x33 line.long 0x0 "GTSSR,General PWM Timer Start Source Select Register" bitfld.long 0x0 31. "CSTRT,Software Source Counter Start Enable" "0: Counter start is disable by the GTSTR register,1: Counter start is enable by the GTSTR register" hexmask.long.byte 0x0 24.--30. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." newline bitfld.long 0x0 23. "SSELCH,ELC_GPTH Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTH input,1: Counter start is enable at the ELC_GPTH input" bitfld.long 0x0 22. "SSELCG,ELC_GPTG Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTG input,1: Counter start is enable at the ELC_GPTG input" newline bitfld.long 0x0 21. "SSELCF,ELC_GPTF Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTF input,1: Counter start is enable at the ELC_GPTF input" bitfld.long 0x0 20. "SSELCE,ELC_GPTE Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTE input,1: Counter start is enable at the ELC_GPTE input" newline bitfld.long 0x0 19. "SSELCD,ELC_GPTD Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTD input,1: Counter start is enable at the ELC_GPTD input" bitfld.long 0x0 18. "SSELCC,ELC_GPTC Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTC input,1: Counter start is enable at the ELC_GPTC input" newline bitfld.long 0x0 17. "SSELCB,ELC_GPTB Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTB input,1: Counter start is enable at the ELC_GPTB input" bitfld.long 0x0 16. "SSELCA,ELC_GPTA Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTA input,1: Counter start is enable at the ELC_GPTA input" newline bitfld.long 0x0 15. "SSCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." bitfld.long 0x0 14. "SSCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." newline bitfld.long 0x0 13. "SSCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." bitfld.long 0x0 12. "SSCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." newline bitfld.long 0x0 11. "SSCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." bitfld.long 0x0 10. "SSCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." newline bitfld.long 0x0 9. "SSCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." bitfld.long 0x0 8. "SSCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." newline hexmask.long.byte 0x0 4.--7. 1. "Reserved,These bits are read as 0000. The write value should be 0000." bitfld.long 0x0 3. "SSGTRGBF,GTETRGB Pin Falling Input Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." newline bitfld.long 0x0 2. "SSGTRGBR,GTETRGB Pin Rising Input Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." bitfld.long 0x0 1. "SSGTRGAF,GTETRGA Pin Falling Input Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." newline bitfld.long 0x0 0. "SSGTRGAR,GTETRGA Pin Rising Input Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." line.long 0x4 "GTPSR,General PWM Timer Stop Source Select Register" bitfld.long 0x4 31. "CSTOP,Software Source Counter Stop Enable" "0: Counter stop is disable by the GTSTP register,1: Counter stop is enable by the GTSTP register" hexmask.long.byte 0x4 24.--30. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." newline bitfld.long 0x4 23. "PSELCH,ELC_GPTH Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTH input,1: Counter stop is enable at the ELC_GPTH input" bitfld.long 0x4 22. "PSELCG,ELC_GPTG Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTG input,1: Counter stop is enable at the ELC_GPTG input" newline bitfld.long 0x4 21. "PSELCF,ELC_GPTF Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTF input,1: Counter stop is enable at the ELC_GPTF input" bitfld.long 0x4 20. "PSELCE,ELC_GPTE Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTE input,1: Counter stop is enable at the ELC_GPTE input" newline bitfld.long 0x4 19. "PSELCD,ELC_GPTD Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTD input,1: Counter stop is enable at the ELC_GPTD input" bitfld.long 0x4 18. "PSELCC,ELC_GPTC Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTC input,1: Counter stop is enable at the ELC_GPTC input" newline bitfld.long 0x4 17. "PSELCB,ELC_GPTB Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTB input,1: Counter stop is enable at the ELC_GPTB input" bitfld.long 0x4 16. "PSELCA,ELC_GPTA Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTA input,1: Counter stop is enable at the ELC_GPTA input" newline bitfld.long 0x4 15. "PSCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." bitfld.long 0x4 14. "PSCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." newline bitfld.long 0x4 13. "PSCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." bitfld.long 0x4 12. "PSCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." newline bitfld.long 0x4 11. "PSCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." bitfld.long 0x4 10. "PSCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." newline bitfld.long 0x4 9. "PSCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." bitfld.long 0x4 8. "PSCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." newline hexmask.long.byte 0x4 4.--7. 1. "Reserved,These bits are read as 0000. The write value should be 0000." bitfld.long 0x4 3. "PSGTRGBF,GTETRGB Pin Falling Input Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." newline bitfld.long 0x4 2. "PSGTRGBR,GTETRGB Pin Rising Input Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." bitfld.long 0x4 1. "PSGTRGAF,GTETRGA Pin Falling Input Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." newline bitfld.long 0x4 0. "PSGTRGAR,GTETRGA Pin Rising Input Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." line.long 0x8 "GTCSR,General PWM Timer Clear Source Select Register" bitfld.long 0x8 31. "CCLR,Software Source Counter Clear Enable" "0: Counter clear is disable by the GTCLR register,1: Counter clear is enable by the GTCLR register" hexmask.long.byte 0x8 24.--30. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." newline bitfld.long 0x8 23. "CSELCH,ELC_GPTH Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTH input,1: Counter clear is enable at the ELC_GPTH input" bitfld.long 0x8 22. "CSELCG,ELC_GPTG Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTG input,1: Counter clear is enable at the ELC_GPTG input" newline bitfld.long 0x8 21. "CSELCF,ELC_GPTF Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTF input,1: Counter clear is enable at the ELC_GPTF input" bitfld.long 0x8 20. "CSELCE,ELC_GPTE Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTE input,1: Counter clear is enable at the ELC_GPTE input" newline bitfld.long 0x8 19. "CSELCD,ELC_GPTD Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTD input,1: Counter clear is enable at the ELC_GPTD input" bitfld.long 0x8 18. "CSELCC,ELC_GPTC Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTC input,1: Counter clear is enable at the ELC_GPTC input" newline bitfld.long 0x8 17. "CSELCB,ELC_GPTB Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTB input,1: Counter clear is enable at the ELC_GPTB input" bitfld.long 0x8 16. "CSELCA,ELC_GPTA Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTA input,1: Counter clear is enable at the ELC_GPTA input" newline bitfld.long 0x8 15. "CSCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." bitfld.long 0x8 14. "CSCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." newline bitfld.long 0x8 13. "CSCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." bitfld.long 0x8 12. "CSCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." newline bitfld.long 0x8 11. "CSCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." bitfld.long 0x8 10. "CSCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." newline bitfld.long 0x8 9. "CSCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." bitfld.long 0x8 8. "CSCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." newline hexmask.long.byte 0x8 4.--7. 1. "Reserved,These bits are read as 0000. The write value should be 0000." bitfld.long 0x8 3. "CSGTRGBF,GTETRGB Pin Falling Input Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." newline bitfld.long 0x8 2. "CSGTRGBR,GTETRGB Pin Rising Input Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." bitfld.long 0x8 1. "CSGTRGAF,GTETRGA Pin Falling Input Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." newline bitfld.long 0x8 0. "CSGTRGAR,GTETRGA Pin Rising Input Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." line.long 0xC "GTUPSR,General PWM Timer Up Count Source Select Register" bitfld.long 0xC 23. "USELCH,ELC_GPTH Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTH input,1: Counter count up is enable at the ELC_GPTH input" bitfld.long 0xC 22. "USELCG,ELC_GPTG Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTG input,1: Counter count up is enable at the ELC_GPTG input" newline bitfld.long 0xC 21. "USELCF,ELC_GPTF Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTF input,1: Counter count up is enable at the ELC_GPTF input" bitfld.long 0xC 20. "USELCE,ELC_GPTE Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTE input,1: Counter count up is enable at the ELC_GPTE input" newline bitfld.long 0xC 19. "USELCD,ELC_GPTD Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTD input,1: Counter count up is enable at the ELC_GPTD input" bitfld.long 0xC 18. "USELCC,ELC_GPTC Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTC input,1: Counter count up is enable at the ELC_GPTC input" newline bitfld.long 0xC 17. "USELCB,ELC_GPTB Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTB input,1: Counter count up is enable at the ELC_GPTB input" bitfld.long 0xC 16. "USELCA,ELC_GPTA Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTA input,1: Counter count up is enable at the ELC_GPTA input" newline bitfld.long 0xC 15. "USCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." bitfld.long 0xC 14. "USCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." newline bitfld.long 0xC 13. "USCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." bitfld.long 0xC 12. "USCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." newline bitfld.long 0xC 11. "USCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." bitfld.long 0xC 10. "USCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." newline bitfld.long 0xC 9. "USCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." bitfld.long 0xC 8. "USCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." newline bitfld.long 0xC 3. "USGTRGBF,GTETRGB Pin Falling Input Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." bitfld.long 0xC 2. "USGTRGBR,GTETRGB Pin Rising Input Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." newline bitfld.long 0xC 1. "USGTRGAF,GTETRGA Pin Falling Input Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." bitfld.long 0xC 0. "USGTRGAR,GTETRGA Pin Rising Input Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." line.long 0x10 "GTDNSR,General PWM Timer Down Count Source Select Register" bitfld.long 0x10 23. "DSELCH,ELC_GPTH Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTH..,1: Counter count down is enable at the ELC_GPTH input" bitfld.long 0x10 22. "DSELCG,ELC_GPTG Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTG..,1: Counter count down is enable at the ELC_GPTG input" newline bitfld.long 0x10 21. "DSELCF,ELC_GPTF Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTF..,1: Counter count down is enable at the ELC_GPTF input" bitfld.long 0x10 20. "DSELCE,ELC_GPTE Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTE..,1: Counter count down is enable at the ELC_GPTE input" newline bitfld.long 0x10 19. "DSELCD,ELC_GPTD Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTD..,1: Counter count down is enable at the ELC_GPTD input" bitfld.long 0x10 18. "DSELCC,ELC_GPTC Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTC..,1: Counter count down is enable at the ELC_GPTC input" newline bitfld.long 0x10 17. "DSELCB,ELC_GPTB Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTB..,1: Counter count down is enable at the ELC_GPTB input" bitfld.long 0x10 16. "DSELCA,ELC_GPTA Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTA..,1: Counter count down is enable at the ELC_GPTA input" newline bitfld.long 0x10 15. "DSCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." bitfld.long 0x10 14. "DSCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." newline bitfld.long 0x10 13. "DSCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." bitfld.long 0x10 12. "DSCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." newline bitfld.long 0x10 11. "DSCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." bitfld.long 0x10 10. "DSCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." newline bitfld.long 0x10 9. "DSCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." bitfld.long 0x10 8. "DSCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." newline bitfld.long 0x10 3. "DSGTRGBF,GTETRGB Pin Falling Input Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." bitfld.long 0x10 2. "DSGTRGBR,GTETRGB Pin Rising Input Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." newline bitfld.long 0x10 1. "DSGTRGAF,GTETRGA Pin Falling Input Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." bitfld.long 0x10 0. "DSGTRGAR,GTETRGA Pin Rising Input Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." line.long 0x14 "GTICASR,General PWM Timer Input Capture Source Select Register A" bitfld.long 0x14 23. "ASELCH,ELC_GPTH Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTH..,1: GTCCRA input capture is enable at the ELC_GPTH.." bitfld.long 0x14 22. "ASELCG,ELC_GPTG Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTG..,1: GTCCRA input capture is enable at the ELC_GPTG.." newline bitfld.long 0x14 21. "ASELCF,ELC_GPTF Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTF..,1: GTCCRA input capture is enable at the ELC_GPTF.." bitfld.long 0x14 20. "ASELCE,ELC_GPTE Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTE..,1: GTCCRA input capture is enable at the ELC_GPTE.." newline bitfld.long 0x14 19. "ASELCD,ELC_GPTD Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTD..,1: GTCCRA input capture is enable at the ELC_GPTD.." bitfld.long 0x14 18. "ASELCC,ELC_GPTC Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTC..,1: GTCCRA input capture is enable at the ELC_GPTC.." newline bitfld.long 0x14 17. "ASELCB,ELC_GPTB Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTB..,1: GTCCRA input capture is enable at the ELC_GPTB.." bitfld.long 0x14 16. "ASELCA,ELC_GPTA Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTA..,1: GTCCRA input capture is enable at the ELC_GPTA.." newline bitfld.long 0x14 15. "ASCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." bitfld.long 0x14 14. "ASCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." newline bitfld.long 0x14 13. "ASCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." bitfld.long 0x14 12. "ASCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." newline bitfld.long 0x14 11. "ASCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." bitfld.long 0x14 10. "ASCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." newline bitfld.long 0x14 9. "ASCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." bitfld.long 0x14 8. "ASCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." newline bitfld.long 0x14 3. "ASGTRGBF,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." bitfld.long 0x14 2. "ASGTRGBR,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." newline bitfld.long 0x14 1. "ASGTRGAF,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." bitfld.long 0x14 0. "ASGTRGAR,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." line.long 0x18 "GTICBSR,General PWM Timer Input Capture Source Select Register B" bitfld.long 0x18 23. "BSELCH,ELC_GPTH Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTH..,1: GTCCRB input capture is enable at the ELC_GPTH.." bitfld.long 0x18 22. "BSELCG,ELC_GPTG Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTG..,1: GTCCRB input capture is enable at the ELC_GPTG.." newline bitfld.long 0x18 21. "BSELCF,ELC_GPTF Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTF..,1: GTCCRB input capture is enable at the ELC_GPTF.." bitfld.long 0x18 20. "BSELCE,ELC_GPTE Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTE..,1: GTCCRB input capture is enable at the ELC_GPTE.." newline bitfld.long 0x18 19. "BSELCD,ELC_GPTD Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTD..,1: GTCCRB input capture is enable at the ELC_GPTD.." bitfld.long 0x18 18. "BSELCC,ELC_GPTC Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTC..,1: GTCCRB input capture is enable at the ELC_GPTC.." newline bitfld.long 0x18 17. "BSELCB,ELC_GPTB Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTB..,1: GTCCRB input capture is enable at the ELC_GPTB.." bitfld.long 0x18 16. "BSELCA,ELC_GPTA Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTA..,1: GTCCRB input capture is enable at the ELC_GPTA.." newline bitfld.long 0x18 15. "BSCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." bitfld.long 0x18 14. "BSCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." newline bitfld.long 0x18 13. "BSCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." bitfld.long 0x18 12. "BSCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." newline bitfld.long 0x18 11. "BSCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." bitfld.long 0x18 10. "BSCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." newline bitfld.long 0x18 9. "BSCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." bitfld.long 0x18 8. "BSCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." newline bitfld.long 0x18 3. "BSGTRGBF,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." bitfld.long 0x18 2. "BSGTRGBR,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." newline bitfld.long 0x18 1. "BSGTRGAF,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." bitfld.long 0x18 0. "BSGTRGAR,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." line.long 0x1C "GTCR,General PWM Timer Control Register" bitfld.long 0x1C 24.--26. "TPCS,Timer Prescaler Select" "0: Setting prohibied,1: PCLK/4,?,?,?,?,?,?" hexmask.long.byte 0x1C 19.--23. 1. "Reserved,These bits are read as 00000. The write value should be 00000." newline bitfld.long 0x1C 16.--18. "MD,Mode Select" "0: Saw-wave PWM mode (single buffer or double..,1: Saw-wave one-shot pulse mode (fixed buffer..,?,?,?,?,?,?" hexmask.long.word 0x1C 1.--15. 1. "Reserved,These bits are read as 000000000000000. The write value should be 000000000000000." newline bitfld.long 0x1C 0. "CST,Count Start" "0: Count operation is stopped,1: Count operation is performed" line.long 0x20 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register" bitfld.long 0x20 27. "OBDTYR,GTIOCB Output Value Selecting after Releasing 0 percent/100 percent Duty Setting" "0: Apply output value set in 0 percent/100 percent..,1: Apply masked compare match output value to.." bitfld.long 0x20 26. "OBDTYF,Forcible GTIOCB Output Duty Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x20 24.--25. "OBDTY,GTIOCB Output Duty Setting" "0: GTIOCB pin duty is depend on compare match,1: GTIOCB pin duty is depend on compare match,?,?" hexmask.long.byte 0x20 20.--23. 1. "Reserved,These bits are read as 0000. The write value should be 0000." newline bitfld.long 0x20 19. "OADTYR,GTIOCA Output Value Selecting after Releasing 0 percent/100 percent Duty Setting" "0: Apply output value set in 0 percent/100 percent..,1: Apply masked compare match output value to.." bitfld.long 0x20 18. "OADTYF,Forcible GTIOCA Output Duty Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x20 16.--17. "OADTY,GTIOCA Output Duty Setting" "0: GTIOCA pin duty is depend on compare match,1: GTIOCA pin duty is depend on compare match,?,?" bitfld.long 0x20 1. "UDF,Forcible Count Direction Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x20 0. "UD,Count Direction Setting" "0: GTCNT counts down.,1: GTCNT counts up." line.long 0x24 "GTIOR,General PWM Timer I/O Control Register" bitfld.long 0x24 30.--31. "NFCSB,Noise Filter B Sampling Clock Select" "0: PCLK/1,1: PCLK/4,?,?" bitfld.long 0x24 29. "NFBEN,Noise Filter B Enable" "0: The noise filter for the GTIOCB pin is disabled.,1: The noise filter for the GTIOCB pin is enabled." newline bitfld.long 0x24 27.--28. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.long 0x24 25.--26. "OBDF,GTIOCB Pin Disable Value Setting" "0: Output disable is prohibited.,1: GTIOCB pin is set to Hi-Z when output disable is..,?,?" newline bitfld.long 0x24 24. "OBE,GTIOCB Pin Output Enable" "0: Output is disabled,1: Output is enabled" bitfld.long 0x24 23. "OBHLD,GTIOCB Pin Output Setting at the Start/Stop Count" "0: The GTIOCB pin output level at start/stop of..,1: The GTIOCB pin output level is retained at.." newline bitfld.long 0x24 22. "OBDFLT,GTIOCB Pin Output Value Setting at the Count Stop" "0: The GTIOCB pin outputs low when counting is..,1: The GTIOCB pin outputs high when counting is.." bitfld.long 0x24 21. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline hexmask.long.byte 0x24 16.--20. 1. "GTIOB,GTIOCB Pin Function Select" bitfld.long 0x24 14.--15. "NFCSA,Noise Filter A Sampling Clock Select" "0: PCLK/1,1: PCLK/4,?,?" newline bitfld.long 0x24 13. "NFAEN,Noise Filter A Enable" "0: The noise filter for the GTIOCA pin is disabled.,1: The noise filter for the GTIOCA pin is enabled." bitfld.long 0x24 11.--12. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" newline bitfld.long 0x24 9.--10. "OADF,GTIOCA Pin Disable Value Setting" "0: Output disable is prohibited.,1: GTIOCA pin is set to Hi-Z when output disable is..,?,?" bitfld.long 0x24 8. "OAE,GTIOCA Pin Output Enable" "0: Output is disabled,1: Output is enabled" newline bitfld.long 0x24 7. "OAHLD,GTIOCA Pin Output Setting at the Start/Stop Count" "0: The GTIOCA pin output level at start/stop of..,1: The GTIOCA pin output level is retained at.." bitfld.long 0x24 6. "OADFLT,GTIOCA Pin Output Value Setting at the Count Stop" "0: The GTIOCA pin outputs low when counting is..,1: The GTIOCA pin outputs high when counting is.." newline bitfld.long 0x24 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" hexmask.long.byte 0x24 0.--4. 1. "GTIOA,GTIOCA Pin Function Select" line.long 0x28 "GTINTAD,General PWM Timer Interrupt Output Setting Register" bitfld.long 0x28 30. "GRPABL,Same Time Output Level Low Disable Request Enable" "0: Same time output level low disable request is..,1: Same time output level low disable request is.." bitfld.long 0x28 29. "GRPABH,Same Time Output Level High Disable Request Enable" "0: Same time output level high disable request is..,1: Same time output level high disable request is.." newline bitfld.long 0x28 26.--28. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.long 0x28 24.--25. "GRP,Output Disable Source Select" "0: Setting prohibited,1: Group B output disable request,?,?" newline hexmask.long.tbyte 0x28 0.--23. 1. "Reserved,These bits are read as 000000000000000000000000. The write value should be 000000000000000000000000." line.long 0x2C "GTST,General PWM Timer Status Register" rbitfld.long 0x2C 30. "OABLF,Same Time Output Level Low Disable Request Enable" "0: GTIOCA pin and GTIOCB pin don't output 0 at the..,1: GTIOCA pin and GTIOCB pin output 0 at the same.." rbitfld.long 0x2C 29. "OABHF,Same Time Output Level High Disable Request Enable" "0: GTIOCA pin and GTIOCB pin don't output 1 at the..,1: GTIOCA pin and GTIOCB pin output 1 at the same.." newline hexmask.long.byte 0x2C 25.--28. 1. "Reserved,These bits are read as 0000. The write value should be 0000." rbitfld.long 0x2C 24. "ODF,Output Disable Flag" "0: No output disable request is generated.,1: An output disable request is generated." newline hexmask.long.byte 0x2C 16.--23. 1. "Reserved,These bits are read as 00000000. The write value should be 00000000." rbitfld.long 0x2C 15. "TUCF,Count Direction Flag" "0: The GTCNT counter counts downward.,1: The GTCNT counter counts upward." newline hexmask.long.byte 0x2C 8.--14. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.long 0x2C 7. "TCFPU,Underflow Flag" "0: No underflow (trough) has occurred.,1: An underflow (trough) has occurred." newline bitfld.long 0x2C 6. "TCPFO,Overflow Flag" "0: No overflow (crest) has occurred.,1: An overflow (crest) has occurred." bitfld.long 0x2C 5. "TCFF,Input Compare Match Flag F" "0: No compare match of GTCCRF is generated.,1: A compare match of GTCCRF is generated." newline bitfld.long 0x2C 4. "TCFE,Input Compare Match Flag E" "0: No compare match of GTCCRE is generated.,1: A compare match of GTCCRE is generated." bitfld.long 0x2C 3. "TCFD,Input Compare Match Flag D" "0: No compare match of GTCCRD is generated.,1: A compare match of GTCCRD is generated." newline bitfld.long 0x2C 2. "TCFC,Input Compare Match Flag C" "0: No compare match of GTCCRC is generated.,1: A compare match of GTCCRC is generated." bitfld.long 0x2C 1. "TCFB,Input Capture/Compare Match Flag B" "0: No input capture/compare match of GTCCRB is..,1: An input capture/compare match of GTCCRB is.." newline bitfld.long 0x2C 0. "TCFA,Input Capture/Compare Match Flag A" "0: No input capture/compare match of GTCCRA is..,1: An input capture/compare match of GTCCRA is.." line.long 0x30 "GTBER,General PWM Timer Buffer Enable Register" bitfld.long 0x30 22. "CCRSWT,GTCCRA and GTCCRB Forcible Buffer OperationThis bit is read as 0." "0: no effect,1: Forcibly performs buffer transfer of GTCCRA and.." bitfld.long 0x30 20.--21. "PR,GTPR Buffer Operation" "0: Setting prohibited,1: Single buffer operation (GTPBR --> GTPR),?,?" newline bitfld.long 0x30 18.--19. "CCRB,GTCCRB Buffer Operation" "0: Buffer operation is not performed,1: Single buffer operation (GTCCRB <--> GTCCRE),?,?" bitfld.long 0x30 16.--17. "CCRA,GTCCRA Buffer Operation" "0: Buffer operation is not performed,1: Single buffer operation (GTCCRA <--> GTCCRC),?,?" newline bitfld.long 0x30 0.--1. "BD,BD[1]: GTPR Buffer Operation DisableBD[0]: GTCCR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled,?,?" group.long 0x48++0x23 line.long 0x0 "GTCNT,General PWM Timer Counter" hexmask.long 0x0 0.--31. 1. "GTCNT,Counter" line.long 0x4 "GTCCRA,General PWM Timer Compare Capture Register A" hexmask.long 0x4 0.--31. 1. "GTCCRA,Compare Capture Register A" line.long 0x8 "GTCCRB,General PWM Timer Compare Capture Register B" hexmask.long 0x8 0.--31. 1. "GTCCRB,Compare Capture Register B" line.long 0xC "GTCCRC,General PWM Timer Compare Capture Register C" hexmask.long 0xC 0.--31. 1. "GTCCRC,Compare Capture Register C" line.long 0x10 "GTCCRE,General PWM Timer Compare Capture Register E" hexmask.long 0x10 0.--31. 1. "GTCCRE,Compare Capture Register E" line.long 0x14 "GTCCRD,General PWM Timer Compare Capture Register D" hexmask.long 0x14 0.--31. 1. "GTCCRD,Compare Capture Register D" line.long 0x18 "GTCCRF,General PWM Timer Compare Capture Register F" hexmask.long 0x18 0.--31. 1. "GTCCRF,Compare Capture Register F" line.long 0x1C "GTPR,General PWM Timer Cycle Setting Register" hexmask.long 0x1C 0.--31. 1. "GTPR,Cycle Setting Register" line.long 0x20 "GTPBR,General PWM Timer Cycle Setting Buffer Register" hexmask.long 0x20 0.--31. 1. "GTPBR,Cycle Setting Buffer Register" group.long 0x88++0x7 line.long 0x0 "GTDTCR,General PWM Timer Dead Time Control Register" hexmask.long.tbyte 0x0 9.--31. 1. "Reserved,These bits are read as 00000000000000000000000. The write value should be 00000000000000000000000." bitfld.long 0x0 8. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.long 0x0 6.--7. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.long 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.long 0x0 4. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 1.--3. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "TDE,Negative-Phase Waveform Setting" "0: GTCCRB is set without using GTDVU and GTDVD.,1: GTDVU and GTDVD are used to set the compare.." line.long 0x4 "GTDVU,General PWM Timer Dead Time Value Register U" hexmask.long 0x4 0.--31. 1. "GTDVU,Dead Time Value Register U" tree.end tree "GPT167" base ad:0x40078700 group.long 0x0++0xB line.long 0x0 "GTWP,General PWM Timer Write-Protection Register" hexmask.long.word 0x0 16.--31. 1. "Reserved,These bits are read as 0000000000000000. The write value should be 0000000000000000." hexmask.long.byte 0x0 8.--15. 1. "PRKEY,GTWP Key Code" newline hexmask.long.byte 0x0 1.--7. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.long 0x0 0. "WP,Register Write Disable" "0: Write to the register is enabled,1: Write to the register is disabled" line.long 0x4 "GTSTR,General PWM Timer Software Start Register" hexmask.long.tbyte 0x4 10.--31. 1. "Reserved,These bits are read as 0000000000000000000000. The write value should be 0000000000000000000000." bitfld.long 0x4 9. "CSTRT9,Channel 9 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT169.GTCNT counter starts (write) / Counter.." newline bitfld.long 0x4 8. "CSTRT8,Channel 8 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT168.GTCNT counter starts (write) / Counter.." bitfld.long 0x4 7. "CSTRT7,Channel 7 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT167.GTCNT counter starts (write) / Counter.." newline bitfld.long 0x4 6. "CSTRT6,Channel 6 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT166.GTCNT counter starts (write) / Counter.." bitfld.long 0x4 5. "CSTRT5,Channel 5 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT165.GTCNT counter starts (write) / Counter.." newline bitfld.long 0x4 4. "CSTRT4,Channel 4 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT164.GTCNT counter starts (write) / Counter.." bitfld.long 0x4 3. "CSTRT3,Channel 3 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT323.GTCNT counter starts (write) / Counter.." newline bitfld.long 0x4 2. "CSTRT2,Channel 2 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT322.GTCNT counter starts (write) / Counter.." bitfld.long 0x4 1. "CSTRT1,Channel 1 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT321.GTCNT counter starts (write) / Counter.." newline bitfld.long 0x4 0. "CSTRT0,Channel 0 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT320.GTCNT counter starts (write) / Counter.." line.long 0x8 "GTSTP,General PWM Timer Software Stop Register" hexmask.long.tbyte 0x8 10.--31. 1. "Reserved,These bits are read as 1111111111111111111111. The write value should be 1111111111111111111111." bitfld.long 0x8 9. "CSTOP9,Channel 9 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT169.GTCNT counter stops (write) / Counter.." newline bitfld.long 0x8 8. "CSTOP8,Channel 8 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT168.GTCNT counter stops (write) / Counter.." bitfld.long 0x8 7. "CSTOP7,Channel 7 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT167.GTCNT counter stops (write) / Counter.." newline bitfld.long 0x8 6. "CSTOP6,Channel 6 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT166.GTCNT counter stops (write) / Counter.." bitfld.long 0x8 5. "CSTOP5,Channel 5 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT165.GTCNT counter stops (write) / Counter.." newline bitfld.long 0x8 4. "CSTOP4,Channel 4 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT164.GTCNT counter stops (write) / Counter.." bitfld.long 0x8 3. "CSTOP3,Channel 3 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT323.GTCNT counter stops (write) / Counter.." newline bitfld.long 0x8 2. "CSTOP2,Channel 2 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT322.GTCNT counter stops (write) / Counter.." bitfld.long 0x8 1. "CSTOP1,Channel 1 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT321.GTCNT counter stops (write) / Counter.." newline bitfld.long 0x8 0. "CSTOP0,Channel 0 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT320.GTCNT counter stops (write) / Counter.." wgroup.long 0xC++0x3 line.long 0x0 "GTCLR,General PWM Timer Software Clear Register" hexmask.long.tbyte 0x0 10.--31. 1. "Reserved,The write value should be 0000000000000000000000." bitfld.long 0x0 9. "CCLR9,Channel 9 GTCNT Count Clear" "0: No effect,1: GPT169.GTCNT counter clears" newline bitfld.long 0x0 8. "CCLR8,Channel 8 GTCNT Count Clear" "0: No effect,1: GPT168.GTCNT counter clears" bitfld.long 0x0 7. "CCLR7,Channel 7 GTCNT Count Clear" "0: No effect,1: GPT167.GTCNT counter clears" newline bitfld.long 0x0 6. "CCLR6,Channel 6 GTCNT Count Clear" "0: No effect,1: GPT166.GTCNT counter clears" bitfld.long 0x0 5. "CCLR5,Channel 5 GTCNT Count Clear" "0: No effect,1: GPT165.GTCNT counter clears" newline bitfld.long 0x0 4. "CCLR4,Channel 4 GTCNT Count Clear" "0: No effect,1: GPT164.GTCNT counter clears" bitfld.long 0x0 3. "CCLR3,Channel 3 GTCNT Count Clear" "0: No effect,1: GPT323.GTCNT counter clears" newline bitfld.long 0x0 2. "CCLR2,Channel 2 GTCNT Count Clear" "0: No effect,1: GPT322.GTCNT counter clears" bitfld.long 0x0 1. "CCLR1,Channel 1 GTCNT Count Clear" "0: No effect,1: GPT321.GTCNT counter clears" newline bitfld.long 0x0 0. "CCLR0,Channel 0 GTCNT Count Clear" "0: No effect,1: GPT320.GTCNT counter clears" group.long 0x10++0x33 line.long 0x0 "GTSSR,General PWM Timer Start Source Select Register" bitfld.long 0x0 31. "CSTRT,Software Source Counter Start Enable" "0: Counter start is disable by the GTSTR register,1: Counter start is enable by the GTSTR register" hexmask.long.byte 0x0 24.--30. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." newline bitfld.long 0x0 23. "SSELCH,ELC_GPTH Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTH input,1: Counter start is enable at the ELC_GPTH input" bitfld.long 0x0 22. "SSELCG,ELC_GPTG Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTG input,1: Counter start is enable at the ELC_GPTG input" newline bitfld.long 0x0 21. "SSELCF,ELC_GPTF Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTF input,1: Counter start is enable at the ELC_GPTF input" bitfld.long 0x0 20. "SSELCE,ELC_GPTE Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTE input,1: Counter start is enable at the ELC_GPTE input" newline bitfld.long 0x0 19. "SSELCD,ELC_GPTD Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTD input,1: Counter start is enable at the ELC_GPTD input" bitfld.long 0x0 18. "SSELCC,ELC_GPTC Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTC input,1: Counter start is enable at the ELC_GPTC input" newline bitfld.long 0x0 17. "SSELCB,ELC_GPTB Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTB input,1: Counter start is enable at the ELC_GPTB input" bitfld.long 0x0 16. "SSELCA,ELC_GPTA Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTA input,1: Counter start is enable at the ELC_GPTA input" newline bitfld.long 0x0 15. "SSCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." bitfld.long 0x0 14. "SSCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." newline bitfld.long 0x0 13. "SSCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." bitfld.long 0x0 12. "SSCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." newline bitfld.long 0x0 11. "SSCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." bitfld.long 0x0 10. "SSCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." newline bitfld.long 0x0 9. "SSCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." bitfld.long 0x0 8. "SSCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." newline hexmask.long.byte 0x0 4.--7. 1. "Reserved,These bits are read as 0000. The write value should be 0000." bitfld.long 0x0 3. "SSGTRGBF,GTETRGB Pin Falling Input Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." newline bitfld.long 0x0 2. "SSGTRGBR,GTETRGB Pin Rising Input Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." bitfld.long 0x0 1. "SSGTRGAF,GTETRGA Pin Falling Input Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." newline bitfld.long 0x0 0. "SSGTRGAR,GTETRGA Pin Rising Input Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." line.long 0x4 "GTPSR,General PWM Timer Stop Source Select Register" bitfld.long 0x4 31. "CSTOP,Software Source Counter Stop Enable" "0: Counter stop is disable by the GTSTP register,1: Counter stop is enable by the GTSTP register" hexmask.long.byte 0x4 24.--30. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." newline bitfld.long 0x4 23. "PSELCH,ELC_GPTH Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTH input,1: Counter stop is enable at the ELC_GPTH input" bitfld.long 0x4 22. "PSELCG,ELC_GPTG Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTG input,1: Counter stop is enable at the ELC_GPTG input" newline bitfld.long 0x4 21. "PSELCF,ELC_GPTF Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTF input,1: Counter stop is enable at the ELC_GPTF input" bitfld.long 0x4 20. "PSELCE,ELC_GPTE Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTE input,1: Counter stop is enable at the ELC_GPTE input" newline bitfld.long 0x4 19. "PSELCD,ELC_GPTD Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTD input,1: Counter stop is enable at the ELC_GPTD input" bitfld.long 0x4 18. "PSELCC,ELC_GPTC Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTC input,1: Counter stop is enable at the ELC_GPTC input" newline bitfld.long 0x4 17. "PSELCB,ELC_GPTB Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTB input,1: Counter stop is enable at the ELC_GPTB input" bitfld.long 0x4 16. "PSELCA,ELC_GPTA Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTA input,1: Counter stop is enable at the ELC_GPTA input" newline bitfld.long 0x4 15. "PSCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." bitfld.long 0x4 14. "PSCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." newline bitfld.long 0x4 13. "PSCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." bitfld.long 0x4 12. "PSCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." newline bitfld.long 0x4 11. "PSCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." bitfld.long 0x4 10. "PSCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." newline bitfld.long 0x4 9. "PSCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." bitfld.long 0x4 8. "PSCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." newline hexmask.long.byte 0x4 4.--7. 1. "Reserved,These bits are read as 0000. The write value should be 0000." bitfld.long 0x4 3. "PSGTRGBF,GTETRGB Pin Falling Input Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." newline bitfld.long 0x4 2. "PSGTRGBR,GTETRGB Pin Rising Input Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." bitfld.long 0x4 1. "PSGTRGAF,GTETRGA Pin Falling Input Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." newline bitfld.long 0x4 0. "PSGTRGAR,GTETRGA Pin Rising Input Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." line.long 0x8 "GTCSR,General PWM Timer Clear Source Select Register" bitfld.long 0x8 31. "CCLR,Software Source Counter Clear Enable" "0: Counter clear is disable by the GTCLR register,1: Counter clear is enable by the GTCLR register" hexmask.long.byte 0x8 24.--30. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." newline bitfld.long 0x8 23. "CSELCH,ELC_GPTH Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTH input,1: Counter clear is enable at the ELC_GPTH input" bitfld.long 0x8 22. "CSELCG,ELC_GPTG Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTG input,1: Counter clear is enable at the ELC_GPTG input" newline bitfld.long 0x8 21. "CSELCF,ELC_GPTF Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTF input,1: Counter clear is enable at the ELC_GPTF input" bitfld.long 0x8 20. "CSELCE,ELC_GPTE Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTE input,1: Counter clear is enable at the ELC_GPTE input" newline bitfld.long 0x8 19. "CSELCD,ELC_GPTD Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTD input,1: Counter clear is enable at the ELC_GPTD input" bitfld.long 0x8 18. "CSELCC,ELC_GPTC Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTC input,1: Counter clear is enable at the ELC_GPTC input" newline bitfld.long 0x8 17. "CSELCB,ELC_GPTB Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTB input,1: Counter clear is enable at the ELC_GPTB input" bitfld.long 0x8 16. "CSELCA,ELC_GPTA Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTA input,1: Counter clear is enable at the ELC_GPTA input" newline bitfld.long 0x8 15. "CSCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." bitfld.long 0x8 14. "CSCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." newline bitfld.long 0x8 13. "CSCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." bitfld.long 0x8 12. "CSCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." newline bitfld.long 0x8 11. "CSCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." bitfld.long 0x8 10. "CSCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." newline bitfld.long 0x8 9. "CSCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." bitfld.long 0x8 8. "CSCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." newline hexmask.long.byte 0x8 4.--7. 1. "Reserved,These bits are read as 0000. The write value should be 0000." bitfld.long 0x8 3. "CSGTRGBF,GTETRGB Pin Falling Input Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." newline bitfld.long 0x8 2. "CSGTRGBR,GTETRGB Pin Rising Input Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." bitfld.long 0x8 1. "CSGTRGAF,GTETRGA Pin Falling Input Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." newline bitfld.long 0x8 0. "CSGTRGAR,GTETRGA Pin Rising Input Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." line.long 0xC "GTUPSR,General PWM Timer Up Count Source Select Register" bitfld.long 0xC 23. "USELCH,ELC_GPTH Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTH input,1: Counter count up is enable at the ELC_GPTH input" bitfld.long 0xC 22. "USELCG,ELC_GPTG Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTG input,1: Counter count up is enable at the ELC_GPTG input" newline bitfld.long 0xC 21. "USELCF,ELC_GPTF Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTF input,1: Counter count up is enable at the ELC_GPTF input" bitfld.long 0xC 20. "USELCE,ELC_GPTE Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTE input,1: Counter count up is enable at the ELC_GPTE input" newline bitfld.long 0xC 19. "USELCD,ELC_GPTD Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTD input,1: Counter count up is enable at the ELC_GPTD input" bitfld.long 0xC 18. "USELCC,ELC_GPTC Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTC input,1: Counter count up is enable at the ELC_GPTC input" newline bitfld.long 0xC 17. "USELCB,ELC_GPTB Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTB input,1: Counter count up is enable at the ELC_GPTB input" bitfld.long 0xC 16. "USELCA,ELC_GPTA Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTA input,1: Counter count up is enable at the ELC_GPTA input" newline bitfld.long 0xC 15. "USCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." bitfld.long 0xC 14. "USCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." newline bitfld.long 0xC 13. "USCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." bitfld.long 0xC 12. "USCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." newline bitfld.long 0xC 11. "USCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." bitfld.long 0xC 10. "USCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." newline bitfld.long 0xC 9. "USCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." bitfld.long 0xC 8. "USCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." newline bitfld.long 0xC 3. "USGTRGBF,GTETRGB Pin Falling Input Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." bitfld.long 0xC 2. "USGTRGBR,GTETRGB Pin Rising Input Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." newline bitfld.long 0xC 1. "USGTRGAF,GTETRGA Pin Falling Input Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." bitfld.long 0xC 0. "USGTRGAR,GTETRGA Pin Rising Input Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." line.long 0x10 "GTDNSR,General PWM Timer Down Count Source Select Register" bitfld.long 0x10 23. "DSELCH,ELC_GPTH Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTH..,1: Counter count down is enable at the ELC_GPTH input" bitfld.long 0x10 22. "DSELCG,ELC_GPTG Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTG..,1: Counter count down is enable at the ELC_GPTG input" newline bitfld.long 0x10 21. "DSELCF,ELC_GPTF Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTF..,1: Counter count down is enable at the ELC_GPTF input" bitfld.long 0x10 20. "DSELCE,ELC_GPTE Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTE..,1: Counter count down is enable at the ELC_GPTE input" newline bitfld.long 0x10 19. "DSELCD,ELC_GPTD Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTD..,1: Counter count down is enable at the ELC_GPTD input" bitfld.long 0x10 18. "DSELCC,ELC_GPTC Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTC..,1: Counter count down is enable at the ELC_GPTC input" newline bitfld.long 0x10 17. "DSELCB,ELC_GPTB Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTB..,1: Counter count down is enable at the ELC_GPTB input" bitfld.long 0x10 16. "DSELCA,ELC_GPTA Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTA..,1: Counter count down is enable at the ELC_GPTA input" newline bitfld.long 0x10 15. "DSCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." bitfld.long 0x10 14. "DSCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." newline bitfld.long 0x10 13. "DSCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." bitfld.long 0x10 12. "DSCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." newline bitfld.long 0x10 11. "DSCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." bitfld.long 0x10 10. "DSCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." newline bitfld.long 0x10 9. "DSCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." bitfld.long 0x10 8. "DSCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." newline bitfld.long 0x10 3. "DSGTRGBF,GTETRGB Pin Falling Input Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." bitfld.long 0x10 2. "DSGTRGBR,GTETRGB Pin Rising Input Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." newline bitfld.long 0x10 1. "DSGTRGAF,GTETRGA Pin Falling Input Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." bitfld.long 0x10 0. "DSGTRGAR,GTETRGA Pin Rising Input Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." line.long 0x14 "GTICASR,General PWM Timer Input Capture Source Select Register A" bitfld.long 0x14 23. "ASELCH,ELC_GPTH Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTH..,1: GTCCRA input capture is enable at the ELC_GPTH.." bitfld.long 0x14 22. "ASELCG,ELC_GPTG Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTG..,1: GTCCRA input capture is enable at the ELC_GPTG.." newline bitfld.long 0x14 21. "ASELCF,ELC_GPTF Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTF..,1: GTCCRA input capture is enable at the ELC_GPTF.." bitfld.long 0x14 20. "ASELCE,ELC_GPTE Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTE..,1: GTCCRA input capture is enable at the ELC_GPTE.." newline bitfld.long 0x14 19. "ASELCD,ELC_GPTD Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTD..,1: GTCCRA input capture is enable at the ELC_GPTD.." bitfld.long 0x14 18. "ASELCC,ELC_GPTC Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTC..,1: GTCCRA input capture is enable at the ELC_GPTC.." newline bitfld.long 0x14 17. "ASELCB,ELC_GPTB Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTB..,1: GTCCRA input capture is enable at the ELC_GPTB.." bitfld.long 0x14 16. "ASELCA,ELC_GPTA Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTA..,1: GTCCRA input capture is enable at the ELC_GPTA.." newline bitfld.long 0x14 15. "ASCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." bitfld.long 0x14 14. "ASCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." newline bitfld.long 0x14 13. "ASCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." bitfld.long 0x14 12. "ASCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." newline bitfld.long 0x14 11. "ASCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." bitfld.long 0x14 10. "ASCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." newline bitfld.long 0x14 9. "ASCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." bitfld.long 0x14 8. "ASCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." newline bitfld.long 0x14 3. "ASGTRGBF,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." bitfld.long 0x14 2. "ASGTRGBR,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." newline bitfld.long 0x14 1. "ASGTRGAF,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." bitfld.long 0x14 0. "ASGTRGAR,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." line.long 0x18 "GTICBSR,General PWM Timer Input Capture Source Select Register B" bitfld.long 0x18 23. "BSELCH,ELC_GPTH Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTH..,1: GTCCRB input capture is enable at the ELC_GPTH.." bitfld.long 0x18 22. "BSELCG,ELC_GPTG Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTG..,1: GTCCRB input capture is enable at the ELC_GPTG.." newline bitfld.long 0x18 21. "BSELCF,ELC_GPTF Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTF..,1: GTCCRB input capture is enable at the ELC_GPTF.." bitfld.long 0x18 20. "BSELCE,ELC_GPTE Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTE..,1: GTCCRB input capture is enable at the ELC_GPTE.." newline bitfld.long 0x18 19. "BSELCD,ELC_GPTD Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTD..,1: GTCCRB input capture is enable at the ELC_GPTD.." bitfld.long 0x18 18. "BSELCC,ELC_GPTC Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTC..,1: GTCCRB input capture is enable at the ELC_GPTC.." newline bitfld.long 0x18 17. "BSELCB,ELC_GPTB Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTB..,1: GTCCRB input capture is enable at the ELC_GPTB.." bitfld.long 0x18 16. "BSELCA,ELC_GPTA Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTA..,1: GTCCRB input capture is enable at the ELC_GPTA.." newline bitfld.long 0x18 15. "BSCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." bitfld.long 0x18 14. "BSCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." newline bitfld.long 0x18 13. "BSCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." bitfld.long 0x18 12. "BSCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." newline bitfld.long 0x18 11. "BSCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." bitfld.long 0x18 10. "BSCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." newline bitfld.long 0x18 9. "BSCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." bitfld.long 0x18 8. "BSCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." newline bitfld.long 0x18 3. "BSGTRGBF,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." bitfld.long 0x18 2. "BSGTRGBR,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." newline bitfld.long 0x18 1. "BSGTRGAF,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." bitfld.long 0x18 0. "BSGTRGAR,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." line.long 0x1C "GTCR,General PWM Timer Control Register" bitfld.long 0x1C 24.--26. "TPCS,Timer Prescaler Select" "0: Setting prohibied,1: PCLK/4,?,?,?,?,?,?" hexmask.long.byte 0x1C 19.--23. 1. "Reserved,These bits are read as 00000. The write value should be 00000." newline bitfld.long 0x1C 16.--18. "MD,Mode Select" "0: Saw-wave PWM mode (single buffer or double..,1: Saw-wave one-shot pulse mode (fixed buffer..,?,?,?,?,?,?" hexmask.long.word 0x1C 1.--15. 1. "Reserved,These bits are read as 000000000000000. The write value should be 000000000000000." newline bitfld.long 0x1C 0. "CST,Count Start" "0: Count operation is stopped,1: Count operation is performed" line.long 0x20 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register" bitfld.long 0x20 27. "OBDTYR,GTIOCB Output Value Selecting after Releasing 0 percent/100 percent Duty Setting" "0: Apply output value set in 0 percent/100 percent..,1: Apply masked compare match output value to.." bitfld.long 0x20 26. "OBDTYF,Forcible GTIOCB Output Duty Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x20 24.--25. "OBDTY,GTIOCB Output Duty Setting" "0: GTIOCB pin duty is depend on compare match,1: GTIOCB pin duty is depend on compare match,?,?" hexmask.long.byte 0x20 20.--23. 1. "Reserved,These bits are read as 0000. The write value should be 0000." newline bitfld.long 0x20 19. "OADTYR,GTIOCA Output Value Selecting after Releasing 0 percent/100 percent Duty Setting" "0: Apply output value set in 0 percent/100 percent..,1: Apply masked compare match output value to.." bitfld.long 0x20 18. "OADTYF,Forcible GTIOCA Output Duty Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x20 16.--17. "OADTY,GTIOCA Output Duty Setting" "0: GTIOCA pin duty is depend on compare match,1: GTIOCA pin duty is depend on compare match,?,?" bitfld.long 0x20 1. "UDF,Forcible Count Direction Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x20 0. "UD,Count Direction Setting" "0: GTCNT counts down.,1: GTCNT counts up." line.long 0x24 "GTIOR,General PWM Timer I/O Control Register" bitfld.long 0x24 30.--31. "NFCSB,Noise Filter B Sampling Clock Select" "0: PCLK/1,1: PCLK/4,?,?" bitfld.long 0x24 29. "NFBEN,Noise Filter B Enable" "0: The noise filter for the GTIOCB pin is disabled.,1: The noise filter for the GTIOCB pin is enabled." newline bitfld.long 0x24 27.--28. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.long 0x24 25.--26. "OBDF,GTIOCB Pin Disable Value Setting" "0: Output disable is prohibited.,1: GTIOCB pin is set to Hi-Z when output disable is..,?,?" newline bitfld.long 0x24 24. "OBE,GTIOCB Pin Output Enable" "0: Output is disabled,1: Output is enabled" bitfld.long 0x24 23. "OBHLD,GTIOCB Pin Output Setting at the Start/Stop Count" "0: The GTIOCB pin output level at start/stop of..,1: The GTIOCB pin output level is retained at.." newline bitfld.long 0x24 22. "OBDFLT,GTIOCB Pin Output Value Setting at the Count Stop" "0: The GTIOCB pin outputs low when counting is..,1: The GTIOCB pin outputs high when counting is.." bitfld.long 0x24 21. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline hexmask.long.byte 0x24 16.--20. 1. "GTIOB,GTIOCB Pin Function Select" bitfld.long 0x24 14.--15. "NFCSA,Noise Filter A Sampling Clock Select" "0: PCLK/1,1: PCLK/4,?,?" newline bitfld.long 0x24 13. "NFAEN,Noise Filter A Enable" "0: The noise filter for the GTIOCA pin is disabled.,1: The noise filter for the GTIOCA pin is enabled." bitfld.long 0x24 11.--12. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" newline bitfld.long 0x24 9.--10. "OADF,GTIOCA Pin Disable Value Setting" "0: Output disable is prohibited.,1: GTIOCA pin is set to Hi-Z when output disable is..,?,?" bitfld.long 0x24 8. "OAE,GTIOCA Pin Output Enable" "0: Output is disabled,1: Output is enabled" newline bitfld.long 0x24 7. "OAHLD,GTIOCA Pin Output Setting at the Start/Stop Count" "0: The GTIOCA pin output level at start/stop of..,1: The GTIOCA pin output level is retained at.." bitfld.long 0x24 6. "OADFLT,GTIOCA Pin Output Value Setting at the Count Stop" "0: The GTIOCA pin outputs low when counting is..,1: The GTIOCA pin outputs high when counting is.." newline bitfld.long 0x24 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" hexmask.long.byte 0x24 0.--4. 1. "GTIOA,GTIOCA Pin Function Select" line.long 0x28 "GTINTAD,General PWM Timer Interrupt Output Setting Register" bitfld.long 0x28 30. "GRPABL,Same Time Output Level Low Disable Request Enable" "0: Same time output level low disable request is..,1: Same time output level low disable request is.." bitfld.long 0x28 29. "GRPABH,Same Time Output Level High Disable Request Enable" "0: Same time output level high disable request is..,1: Same time output level high disable request is.." newline bitfld.long 0x28 26.--28. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.long 0x28 24.--25. "GRP,Output Disable Source Select" "0: Setting prohibited,1: Group B output disable request,?,?" newline hexmask.long.tbyte 0x28 0.--23. 1. "Reserved,These bits are read as 000000000000000000000000. The write value should be 000000000000000000000000." line.long 0x2C "GTST,General PWM Timer Status Register" rbitfld.long 0x2C 30. "OABLF,Same Time Output Level Low Disable Request Enable" "0: GTIOCA pin and GTIOCB pin don't output 0 at the..,1: GTIOCA pin and GTIOCB pin output 0 at the same.." rbitfld.long 0x2C 29. "OABHF,Same Time Output Level High Disable Request Enable" "0: GTIOCA pin and GTIOCB pin don't output 1 at the..,1: GTIOCA pin and GTIOCB pin output 1 at the same.." newline hexmask.long.byte 0x2C 25.--28. 1. "Reserved,These bits are read as 0000. The write value should be 0000." rbitfld.long 0x2C 24. "ODF,Output Disable Flag" "0: No output disable request is generated.,1: An output disable request is generated." newline hexmask.long.byte 0x2C 16.--23. 1. "Reserved,These bits are read as 00000000. The write value should be 00000000." rbitfld.long 0x2C 15. "TUCF,Count Direction Flag" "0: The GTCNT counter counts downward.,1: The GTCNT counter counts upward." newline hexmask.long.byte 0x2C 8.--14. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.long 0x2C 7. "TCFPU,Underflow Flag" "0: No underflow (trough) has occurred.,1: An underflow (trough) has occurred." newline bitfld.long 0x2C 6. "TCPFO,Overflow Flag" "0: No overflow (crest) has occurred.,1: An overflow (crest) has occurred." bitfld.long 0x2C 5. "TCFF,Input Compare Match Flag F" "0: No compare match of GTCCRF is generated.,1: A compare match of GTCCRF is generated." newline bitfld.long 0x2C 4. "TCFE,Input Compare Match Flag E" "0: No compare match of GTCCRE is generated.,1: A compare match of GTCCRE is generated." bitfld.long 0x2C 3. "TCFD,Input Compare Match Flag D" "0: No compare match of GTCCRD is generated.,1: A compare match of GTCCRD is generated." newline bitfld.long 0x2C 2. "TCFC,Input Compare Match Flag C" "0: No compare match of GTCCRC is generated.,1: A compare match of GTCCRC is generated." bitfld.long 0x2C 1. "TCFB,Input Capture/Compare Match Flag B" "0: No input capture/compare match of GTCCRB is..,1: An input capture/compare match of GTCCRB is.." newline bitfld.long 0x2C 0. "TCFA,Input Capture/Compare Match Flag A" "0: No input capture/compare match of GTCCRA is..,1: An input capture/compare match of GTCCRA is.." line.long 0x30 "GTBER,General PWM Timer Buffer Enable Register" bitfld.long 0x30 22. "CCRSWT,GTCCRA and GTCCRB Forcible Buffer OperationThis bit is read as 0." "0: no effect,1: Forcibly performs buffer transfer of GTCCRA and.." bitfld.long 0x30 20.--21. "PR,GTPR Buffer Operation" "0: Setting prohibited,1: Single buffer operation (GTPBR --> GTPR),?,?" newline bitfld.long 0x30 18.--19. "CCRB,GTCCRB Buffer Operation" "0: Buffer operation is not performed,1: Single buffer operation (GTCCRB <--> GTCCRE),?,?" bitfld.long 0x30 16.--17. "CCRA,GTCCRA Buffer Operation" "0: Buffer operation is not performed,1: Single buffer operation (GTCCRA <--> GTCCRC),?,?" newline bitfld.long 0x30 0.--1. "BD,BD[1]: GTPR Buffer Operation DisableBD[0]: GTCCR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled,?,?" group.long 0x48++0x23 line.long 0x0 "GTCNT,General PWM Timer Counter" hexmask.long 0x0 0.--31. 1. "GTCNT,Counter" line.long 0x4 "GTCCRA,General PWM Timer Compare Capture Register A" hexmask.long 0x4 0.--31. 1. "GTCCRA,Compare Capture Register A" line.long 0x8 "GTCCRB,General PWM Timer Compare Capture Register B" hexmask.long 0x8 0.--31. 1. "GTCCRB,Compare Capture Register B" line.long 0xC "GTCCRC,General PWM Timer Compare Capture Register C" hexmask.long 0xC 0.--31. 1. "GTCCRC,Compare Capture Register C" line.long 0x10 "GTCCRE,General PWM Timer Compare Capture Register E" hexmask.long 0x10 0.--31. 1. "GTCCRE,Compare Capture Register E" line.long 0x14 "GTCCRD,General PWM Timer Compare Capture Register D" hexmask.long 0x14 0.--31. 1. "GTCCRD,Compare Capture Register D" line.long 0x18 "GTCCRF,General PWM Timer Compare Capture Register F" hexmask.long 0x18 0.--31. 1. "GTCCRF,Compare Capture Register F" line.long 0x1C "GTPR,General PWM Timer Cycle Setting Register" hexmask.long 0x1C 0.--31. 1. "GTPR,Cycle Setting Register" line.long 0x20 "GTPBR,General PWM Timer Cycle Setting Buffer Register" hexmask.long 0x20 0.--31. 1. "GTPBR,Cycle Setting Buffer Register" group.long 0x88++0x7 line.long 0x0 "GTDTCR,General PWM Timer Dead Time Control Register" hexmask.long.tbyte 0x0 9.--31. 1. "Reserved,These bits are read as 00000000000000000000000. The write value should be 00000000000000000000000." bitfld.long 0x0 8. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.long 0x0 6.--7. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.long 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.long 0x0 4. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 1.--3. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "TDE,Negative-Phase Waveform Setting" "0: GTCCRB is set without using GTDVU and GTDVD.,1: GTDVU and GTDVD are used to set the compare.." line.long 0x4 "GTDVU,General PWM Timer Dead Time Value Register U" hexmask.long 0x4 0.--31. 1. "GTDVU,Dead Time Value Register U" tree.end tree "GPT168" base ad:0x40078800 group.long 0x0++0xB line.long 0x0 "GTWP,General PWM Timer Write-Protection Register" hexmask.long.word 0x0 16.--31. 1. "Reserved,These bits are read as 0000000000000000. The write value should be 0000000000000000." hexmask.long.byte 0x0 8.--15. 1. "PRKEY,GTWP Key Code" newline hexmask.long.byte 0x0 1.--7. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.long 0x0 0. "WP,Register Write Disable" "0: Write to the register is enabled,1: Write to the register is disabled" line.long 0x4 "GTSTR,General PWM Timer Software Start Register" hexmask.long.tbyte 0x4 10.--31. 1. "Reserved,These bits are read as 0000000000000000000000. The write value should be 0000000000000000000000." bitfld.long 0x4 9. "CSTRT9,Channel 9 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT169.GTCNT counter starts (write) / Counter.." newline bitfld.long 0x4 8. "CSTRT8,Channel 8 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT168.GTCNT counter starts (write) / Counter.." bitfld.long 0x4 7. "CSTRT7,Channel 7 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT167.GTCNT counter starts (write) / Counter.." newline bitfld.long 0x4 6. "CSTRT6,Channel 6 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT166.GTCNT counter starts (write) / Counter.." bitfld.long 0x4 5. "CSTRT5,Channel 5 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT165.GTCNT counter starts (write) / Counter.." newline bitfld.long 0x4 4. "CSTRT4,Channel 4 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT164.GTCNT counter starts (write) / Counter.." bitfld.long 0x4 3. "CSTRT3,Channel 3 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT323.GTCNT counter starts (write) / Counter.." newline bitfld.long 0x4 2. "CSTRT2,Channel 2 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT322.GTCNT counter starts (write) / Counter.." bitfld.long 0x4 1. "CSTRT1,Channel 1 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT321.GTCNT counter starts (write) / Counter.." newline bitfld.long 0x4 0. "CSTRT0,Channel 0 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT320.GTCNT counter starts (write) / Counter.." line.long 0x8 "GTSTP,General PWM Timer Software Stop Register" hexmask.long.tbyte 0x8 10.--31. 1. "Reserved,These bits are read as 1111111111111111111111. The write value should be 1111111111111111111111." bitfld.long 0x8 9. "CSTOP9,Channel 9 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT169.GTCNT counter stops (write) / Counter.." newline bitfld.long 0x8 8. "CSTOP8,Channel 8 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT168.GTCNT counter stops (write) / Counter.." bitfld.long 0x8 7. "CSTOP7,Channel 7 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT167.GTCNT counter stops (write) / Counter.." newline bitfld.long 0x8 6. "CSTOP6,Channel 6 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT166.GTCNT counter stops (write) / Counter.." bitfld.long 0x8 5. "CSTOP5,Channel 5 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT165.GTCNT counter stops (write) / Counter.." newline bitfld.long 0x8 4. "CSTOP4,Channel 4 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT164.GTCNT counter stops (write) / Counter.." bitfld.long 0x8 3. "CSTOP3,Channel 3 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT323.GTCNT counter stops (write) / Counter.." newline bitfld.long 0x8 2. "CSTOP2,Channel 2 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT322.GTCNT counter stops (write) / Counter.." bitfld.long 0x8 1. "CSTOP1,Channel 1 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT321.GTCNT counter stops (write) / Counter.." newline bitfld.long 0x8 0. "CSTOP0,Channel 0 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT320.GTCNT counter stops (write) / Counter.." wgroup.long 0xC++0x3 line.long 0x0 "GTCLR,General PWM Timer Software Clear Register" hexmask.long.tbyte 0x0 10.--31. 1. "Reserved,The write value should be 0000000000000000000000." bitfld.long 0x0 9. "CCLR9,Channel 9 GTCNT Count Clear" "0: No effect,1: GPT169.GTCNT counter clears" newline bitfld.long 0x0 8. "CCLR8,Channel 8 GTCNT Count Clear" "0: No effect,1: GPT168.GTCNT counter clears" bitfld.long 0x0 7. "CCLR7,Channel 7 GTCNT Count Clear" "0: No effect,1: GPT167.GTCNT counter clears" newline bitfld.long 0x0 6. "CCLR6,Channel 6 GTCNT Count Clear" "0: No effect,1: GPT166.GTCNT counter clears" bitfld.long 0x0 5. "CCLR5,Channel 5 GTCNT Count Clear" "0: No effect,1: GPT165.GTCNT counter clears" newline bitfld.long 0x0 4. "CCLR4,Channel 4 GTCNT Count Clear" "0: No effect,1: GPT164.GTCNT counter clears" bitfld.long 0x0 3. "CCLR3,Channel 3 GTCNT Count Clear" "0: No effect,1: GPT323.GTCNT counter clears" newline bitfld.long 0x0 2. "CCLR2,Channel 2 GTCNT Count Clear" "0: No effect,1: GPT322.GTCNT counter clears" bitfld.long 0x0 1. "CCLR1,Channel 1 GTCNT Count Clear" "0: No effect,1: GPT321.GTCNT counter clears" newline bitfld.long 0x0 0. "CCLR0,Channel 0 GTCNT Count Clear" "0: No effect,1: GPT320.GTCNT counter clears" group.long 0x10++0x33 line.long 0x0 "GTSSR,General PWM Timer Start Source Select Register" bitfld.long 0x0 31. "CSTRT,Software Source Counter Start Enable" "0: Counter start is disable by the GTSTR register,1: Counter start is enable by the GTSTR register" hexmask.long.byte 0x0 24.--30. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." newline bitfld.long 0x0 23. "SSELCH,ELC_GPTH Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTH input,1: Counter start is enable at the ELC_GPTH input" bitfld.long 0x0 22. "SSELCG,ELC_GPTG Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTG input,1: Counter start is enable at the ELC_GPTG input" newline bitfld.long 0x0 21. "SSELCF,ELC_GPTF Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTF input,1: Counter start is enable at the ELC_GPTF input" bitfld.long 0x0 20. "SSELCE,ELC_GPTE Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTE input,1: Counter start is enable at the ELC_GPTE input" newline bitfld.long 0x0 19. "SSELCD,ELC_GPTD Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTD input,1: Counter start is enable at the ELC_GPTD input" bitfld.long 0x0 18. "SSELCC,ELC_GPTC Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTC input,1: Counter start is enable at the ELC_GPTC input" newline bitfld.long 0x0 17. "SSELCB,ELC_GPTB Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTB input,1: Counter start is enable at the ELC_GPTB input" bitfld.long 0x0 16. "SSELCA,ELC_GPTA Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTA input,1: Counter start is enable at the ELC_GPTA input" newline bitfld.long 0x0 15. "SSCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." bitfld.long 0x0 14. "SSCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." newline bitfld.long 0x0 13. "SSCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." bitfld.long 0x0 12. "SSCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." newline bitfld.long 0x0 11. "SSCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." bitfld.long 0x0 10. "SSCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." newline bitfld.long 0x0 9. "SSCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." bitfld.long 0x0 8. "SSCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." newline hexmask.long.byte 0x0 4.--7. 1. "Reserved,These bits are read as 0000. The write value should be 0000." bitfld.long 0x0 3. "SSGTRGBF,GTETRGB Pin Falling Input Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." newline bitfld.long 0x0 2. "SSGTRGBR,GTETRGB Pin Rising Input Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." bitfld.long 0x0 1. "SSGTRGAF,GTETRGA Pin Falling Input Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." newline bitfld.long 0x0 0. "SSGTRGAR,GTETRGA Pin Rising Input Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." line.long 0x4 "GTPSR,General PWM Timer Stop Source Select Register" bitfld.long 0x4 31. "CSTOP,Software Source Counter Stop Enable" "0: Counter stop is disable by the GTSTP register,1: Counter stop is enable by the GTSTP register" hexmask.long.byte 0x4 24.--30. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." newline bitfld.long 0x4 23. "PSELCH,ELC_GPTH Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTH input,1: Counter stop is enable at the ELC_GPTH input" bitfld.long 0x4 22. "PSELCG,ELC_GPTG Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTG input,1: Counter stop is enable at the ELC_GPTG input" newline bitfld.long 0x4 21. "PSELCF,ELC_GPTF Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTF input,1: Counter stop is enable at the ELC_GPTF input" bitfld.long 0x4 20. "PSELCE,ELC_GPTE Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTE input,1: Counter stop is enable at the ELC_GPTE input" newline bitfld.long 0x4 19. "PSELCD,ELC_GPTD Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTD input,1: Counter stop is enable at the ELC_GPTD input" bitfld.long 0x4 18. "PSELCC,ELC_GPTC Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTC input,1: Counter stop is enable at the ELC_GPTC input" newline bitfld.long 0x4 17. "PSELCB,ELC_GPTB Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTB input,1: Counter stop is enable at the ELC_GPTB input" bitfld.long 0x4 16. "PSELCA,ELC_GPTA Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTA input,1: Counter stop is enable at the ELC_GPTA input" newline bitfld.long 0x4 15. "PSCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." bitfld.long 0x4 14. "PSCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." newline bitfld.long 0x4 13. "PSCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." bitfld.long 0x4 12. "PSCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." newline bitfld.long 0x4 11. "PSCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." bitfld.long 0x4 10. "PSCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." newline bitfld.long 0x4 9. "PSCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." bitfld.long 0x4 8. "PSCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." newline hexmask.long.byte 0x4 4.--7. 1. "Reserved,These bits are read as 0000. The write value should be 0000." bitfld.long 0x4 3. "PSGTRGBF,GTETRGB Pin Falling Input Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." newline bitfld.long 0x4 2. "PSGTRGBR,GTETRGB Pin Rising Input Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." bitfld.long 0x4 1. "PSGTRGAF,GTETRGA Pin Falling Input Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." newline bitfld.long 0x4 0. "PSGTRGAR,GTETRGA Pin Rising Input Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." line.long 0x8 "GTCSR,General PWM Timer Clear Source Select Register" bitfld.long 0x8 31. "CCLR,Software Source Counter Clear Enable" "0: Counter clear is disable by the GTCLR register,1: Counter clear is enable by the GTCLR register" hexmask.long.byte 0x8 24.--30. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." newline bitfld.long 0x8 23. "CSELCH,ELC_GPTH Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTH input,1: Counter clear is enable at the ELC_GPTH input" bitfld.long 0x8 22. "CSELCG,ELC_GPTG Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTG input,1: Counter clear is enable at the ELC_GPTG input" newline bitfld.long 0x8 21. "CSELCF,ELC_GPTF Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTF input,1: Counter clear is enable at the ELC_GPTF input" bitfld.long 0x8 20. "CSELCE,ELC_GPTE Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTE input,1: Counter clear is enable at the ELC_GPTE input" newline bitfld.long 0x8 19. "CSELCD,ELC_GPTD Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTD input,1: Counter clear is enable at the ELC_GPTD input" bitfld.long 0x8 18. "CSELCC,ELC_GPTC Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTC input,1: Counter clear is enable at the ELC_GPTC input" newline bitfld.long 0x8 17. "CSELCB,ELC_GPTB Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTB input,1: Counter clear is enable at the ELC_GPTB input" bitfld.long 0x8 16. "CSELCA,ELC_GPTA Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTA input,1: Counter clear is enable at the ELC_GPTA input" newline bitfld.long 0x8 15. "CSCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." bitfld.long 0x8 14. "CSCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." newline bitfld.long 0x8 13. "CSCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." bitfld.long 0x8 12. "CSCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." newline bitfld.long 0x8 11. "CSCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." bitfld.long 0x8 10. "CSCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." newline bitfld.long 0x8 9. "CSCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." bitfld.long 0x8 8. "CSCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." newline hexmask.long.byte 0x8 4.--7. 1. "Reserved,These bits are read as 0000. The write value should be 0000." bitfld.long 0x8 3. "CSGTRGBF,GTETRGB Pin Falling Input Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." newline bitfld.long 0x8 2. "CSGTRGBR,GTETRGB Pin Rising Input Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." bitfld.long 0x8 1. "CSGTRGAF,GTETRGA Pin Falling Input Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." newline bitfld.long 0x8 0. "CSGTRGAR,GTETRGA Pin Rising Input Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." line.long 0xC "GTUPSR,General PWM Timer Up Count Source Select Register" bitfld.long 0xC 23. "USELCH,ELC_GPTH Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTH input,1: Counter count up is enable at the ELC_GPTH input" bitfld.long 0xC 22. "USELCG,ELC_GPTG Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTG input,1: Counter count up is enable at the ELC_GPTG input" newline bitfld.long 0xC 21. "USELCF,ELC_GPTF Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTF input,1: Counter count up is enable at the ELC_GPTF input" bitfld.long 0xC 20. "USELCE,ELC_GPTE Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTE input,1: Counter count up is enable at the ELC_GPTE input" newline bitfld.long 0xC 19. "USELCD,ELC_GPTD Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTD input,1: Counter count up is enable at the ELC_GPTD input" bitfld.long 0xC 18. "USELCC,ELC_GPTC Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTC input,1: Counter count up is enable at the ELC_GPTC input" newline bitfld.long 0xC 17. "USELCB,ELC_GPTB Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTB input,1: Counter count up is enable at the ELC_GPTB input" bitfld.long 0xC 16. "USELCA,ELC_GPTA Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTA input,1: Counter count up is enable at the ELC_GPTA input" newline bitfld.long 0xC 15. "USCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." bitfld.long 0xC 14. "USCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." newline bitfld.long 0xC 13. "USCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." bitfld.long 0xC 12. "USCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." newline bitfld.long 0xC 11. "USCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." bitfld.long 0xC 10. "USCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." newline bitfld.long 0xC 9. "USCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." bitfld.long 0xC 8. "USCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." newline bitfld.long 0xC 3. "USGTRGBF,GTETRGB Pin Falling Input Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." bitfld.long 0xC 2. "USGTRGBR,GTETRGB Pin Rising Input Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." newline bitfld.long 0xC 1. "USGTRGAF,GTETRGA Pin Falling Input Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." bitfld.long 0xC 0. "USGTRGAR,GTETRGA Pin Rising Input Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." line.long 0x10 "GTDNSR,General PWM Timer Down Count Source Select Register" bitfld.long 0x10 23. "DSELCH,ELC_GPTH Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTH..,1: Counter count down is enable at the ELC_GPTH input" bitfld.long 0x10 22. "DSELCG,ELC_GPTG Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTG..,1: Counter count down is enable at the ELC_GPTG input" newline bitfld.long 0x10 21. "DSELCF,ELC_GPTF Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTF..,1: Counter count down is enable at the ELC_GPTF input" bitfld.long 0x10 20. "DSELCE,ELC_GPTE Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTE..,1: Counter count down is enable at the ELC_GPTE input" newline bitfld.long 0x10 19. "DSELCD,ELC_GPTD Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTD..,1: Counter count down is enable at the ELC_GPTD input" bitfld.long 0x10 18. "DSELCC,ELC_GPTC Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTC..,1: Counter count down is enable at the ELC_GPTC input" newline bitfld.long 0x10 17. "DSELCB,ELC_GPTB Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTB..,1: Counter count down is enable at the ELC_GPTB input" bitfld.long 0x10 16. "DSELCA,ELC_GPTA Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTA..,1: Counter count down is enable at the ELC_GPTA input" newline bitfld.long 0x10 15. "DSCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." bitfld.long 0x10 14. "DSCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." newline bitfld.long 0x10 13. "DSCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." bitfld.long 0x10 12. "DSCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." newline bitfld.long 0x10 11. "DSCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." bitfld.long 0x10 10. "DSCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." newline bitfld.long 0x10 9. "DSCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." bitfld.long 0x10 8. "DSCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." newline bitfld.long 0x10 3. "DSGTRGBF,GTETRGB Pin Falling Input Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." bitfld.long 0x10 2. "DSGTRGBR,GTETRGB Pin Rising Input Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." newline bitfld.long 0x10 1. "DSGTRGAF,GTETRGA Pin Falling Input Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." bitfld.long 0x10 0. "DSGTRGAR,GTETRGA Pin Rising Input Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." line.long 0x14 "GTICASR,General PWM Timer Input Capture Source Select Register A" bitfld.long 0x14 23. "ASELCH,ELC_GPTH Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTH..,1: GTCCRA input capture is enable at the ELC_GPTH.." bitfld.long 0x14 22. "ASELCG,ELC_GPTG Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTG..,1: GTCCRA input capture is enable at the ELC_GPTG.." newline bitfld.long 0x14 21. "ASELCF,ELC_GPTF Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTF..,1: GTCCRA input capture is enable at the ELC_GPTF.." bitfld.long 0x14 20. "ASELCE,ELC_GPTE Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTE..,1: GTCCRA input capture is enable at the ELC_GPTE.." newline bitfld.long 0x14 19. "ASELCD,ELC_GPTD Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTD..,1: GTCCRA input capture is enable at the ELC_GPTD.." bitfld.long 0x14 18. "ASELCC,ELC_GPTC Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTC..,1: GTCCRA input capture is enable at the ELC_GPTC.." newline bitfld.long 0x14 17. "ASELCB,ELC_GPTB Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTB..,1: GTCCRA input capture is enable at the ELC_GPTB.." bitfld.long 0x14 16. "ASELCA,ELC_GPTA Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTA..,1: GTCCRA input capture is enable at the ELC_GPTA.." newline bitfld.long 0x14 15. "ASCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." bitfld.long 0x14 14. "ASCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." newline bitfld.long 0x14 13. "ASCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." bitfld.long 0x14 12. "ASCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." newline bitfld.long 0x14 11. "ASCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." bitfld.long 0x14 10. "ASCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." newline bitfld.long 0x14 9. "ASCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." bitfld.long 0x14 8. "ASCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." newline bitfld.long 0x14 3. "ASGTRGBF,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." bitfld.long 0x14 2. "ASGTRGBR,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." newline bitfld.long 0x14 1. "ASGTRGAF,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." bitfld.long 0x14 0. "ASGTRGAR,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." line.long 0x18 "GTICBSR,General PWM Timer Input Capture Source Select Register B" bitfld.long 0x18 23. "BSELCH,ELC_GPTH Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTH..,1: GTCCRB input capture is enable at the ELC_GPTH.." bitfld.long 0x18 22. "BSELCG,ELC_GPTG Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTG..,1: GTCCRB input capture is enable at the ELC_GPTG.." newline bitfld.long 0x18 21. "BSELCF,ELC_GPTF Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTF..,1: GTCCRB input capture is enable at the ELC_GPTF.." bitfld.long 0x18 20. "BSELCE,ELC_GPTE Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTE..,1: GTCCRB input capture is enable at the ELC_GPTE.." newline bitfld.long 0x18 19. "BSELCD,ELC_GPTD Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTD..,1: GTCCRB input capture is enable at the ELC_GPTD.." bitfld.long 0x18 18. "BSELCC,ELC_GPTC Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTC..,1: GTCCRB input capture is enable at the ELC_GPTC.." newline bitfld.long 0x18 17. "BSELCB,ELC_GPTB Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTB..,1: GTCCRB input capture is enable at the ELC_GPTB.." bitfld.long 0x18 16. "BSELCA,ELC_GPTA Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTA..,1: GTCCRB input capture is enable at the ELC_GPTA.." newline bitfld.long 0x18 15. "BSCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." bitfld.long 0x18 14. "BSCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." newline bitfld.long 0x18 13. "BSCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." bitfld.long 0x18 12. "BSCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." newline bitfld.long 0x18 11. "BSCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." bitfld.long 0x18 10. "BSCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." newline bitfld.long 0x18 9. "BSCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." bitfld.long 0x18 8. "BSCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." newline bitfld.long 0x18 3. "BSGTRGBF,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." bitfld.long 0x18 2. "BSGTRGBR,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." newline bitfld.long 0x18 1. "BSGTRGAF,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." bitfld.long 0x18 0. "BSGTRGAR,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." line.long 0x1C "GTCR,General PWM Timer Control Register" bitfld.long 0x1C 24.--26. "TPCS,Timer Prescaler Select" "0: Setting prohibied,1: PCLK/4,?,?,?,?,?,?" hexmask.long.byte 0x1C 19.--23. 1. "Reserved,These bits are read as 00000. The write value should be 00000." newline bitfld.long 0x1C 16.--18. "MD,Mode Select" "0: Saw-wave PWM mode (single buffer or double..,1: Saw-wave one-shot pulse mode (fixed buffer..,?,?,?,?,?,?" hexmask.long.word 0x1C 1.--15. 1. "Reserved,These bits are read as 000000000000000. The write value should be 000000000000000." newline bitfld.long 0x1C 0. "CST,Count Start" "0: Count operation is stopped,1: Count operation is performed" line.long 0x20 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register" bitfld.long 0x20 27. "OBDTYR,GTIOCB Output Value Selecting after Releasing 0 percent/100 percent Duty Setting" "0: Apply output value set in 0 percent/100 percent..,1: Apply masked compare match output value to.." bitfld.long 0x20 26. "OBDTYF,Forcible GTIOCB Output Duty Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x20 24.--25. "OBDTY,GTIOCB Output Duty Setting" "0: GTIOCB pin duty is depend on compare match,1: GTIOCB pin duty is depend on compare match,?,?" hexmask.long.byte 0x20 20.--23. 1. "Reserved,These bits are read as 0000. The write value should be 0000." newline bitfld.long 0x20 19. "OADTYR,GTIOCA Output Value Selecting after Releasing 0 percent/100 percent Duty Setting" "0: Apply output value set in 0 percent/100 percent..,1: Apply masked compare match output value to.." bitfld.long 0x20 18. "OADTYF,Forcible GTIOCA Output Duty Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x20 16.--17. "OADTY,GTIOCA Output Duty Setting" "0: GTIOCA pin duty is depend on compare match,1: GTIOCA pin duty is depend on compare match,?,?" bitfld.long 0x20 1. "UDF,Forcible Count Direction Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x20 0. "UD,Count Direction Setting" "0: GTCNT counts down.,1: GTCNT counts up." line.long 0x24 "GTIOR,General PWM Timer I/O Control Register" bitfld.long 0x24 30.--31. "NFCSB,Noise Filter B Sampling Clock Select" "0: PCLK/1,1: PCLK/4,?,?" bitfld.long 0x24 29. "NFBEN,Noise Filter B Enable" "0: The noise filter for the GTIOCB pin is disabled.,1: The noise filter for the GTIOCB pin is enabled." newline bitfld.long 0x24 27.--28. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.long 0x24 25.--26. "OBDF,GTIOCB Pin Disable Value Setting" "0: Output disable is prohibited.,1: GTIOCB pin is set to Hi-Z when output disable is..,?,?" newline bitfld.long 0x24 24. "OBE,GTIOCB Pin Output Enable" "0: Output is disabled,1: Output is enabled" bitfld.long 0x24 23. "OBHLD,GTIOCB Pin Output Setting at the Start/Stop Count" "0: The GTIOCB pin output level at start/stop of..,1: The GTIOCB pin output level is retained at.." newline bitfld.long 0x24 22. "OBDFLT,GTIOCB Pin Output Value Setting at the Count Stop" "0: The GTIOCB pin outputs low when counting is..,1: The GTIOCB pin outputs high when counting is.." bitfld.long 0x24 21. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline hexmask.long.byte 0x24 16.--20. 1. "GTIOB,GTIOCB Pin Function Select" bitfld.long 0x24 14.--15. "NFCSA,Noise Filter A Sampling Clock Select" "0: PCLK/1,1: PCLK/4,?,?" newline bitfld.long 0x24 13. "NFAEN,Noise Filter A Enable" "0: The noise filter for the GTIOCA pin is disabled.,1: The noise filter for the GTIOCA pin is enabled." bitfld.long 0x24 11.--12. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" newline bitfld.long 0x24 9.--10. "OADF,GTIOCA Pin Disable Value Setting" "0: Output disable is prohibited.,1: GTIOCA pin is set to Hi-Z when output disable is..,?,?" bitfld.long 0x24 8. "OAE,GTIOCA Pin Output Enable" "0: Output is disabled,1: Output is enabled" newline bitfld.long 0x24 7. "OAHLD,GTIOCA Pin Output Setting at the Start/Stop Count" "0: The GTIOCA pin output level at start/stop of..,1: The GTIOCA pin output level is retained at.." bitfld.long 0x24 6. "OADFLT,GTIOCA Pin Output Value Setting at the Count Stop" "0: The GTIOCA pin outputs low when counting is..,1: The GTIOCA pin outputs high when counting is.." newline bitfld.long 0x24 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" hexmask.long.byte 0x24 0.--4. 1. "GTIOA,GTIOCA Pin Function Select" line.long 0x28 "GTINTAD,General PWM Timer Interrupt Output Setting Register" bitfld.long 0x28 30. "GRPABL,Same Time Output Level Low Disable Request Enable" "0: Same time output level low disable request is..,1: Same time output level low disable request is.." bitfld.long 0x28 29. "GRPABH,Same Time Output Level High Disable Request Enable" "0: Same time output level high disable request is..,1: Same time output level high disable request is.." newline bitfld.long 0x28 26.--28. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.long 0x28 24.--25. "GRP,Output Disable Source Select" "0: Setting prohibited,1: Group B output disable request,?,?" newline hexmask.long.tbyte 0x28 0.--23. 1. "Reserved,These bits are read as 000000000000000000000000. The write value should be 000000000000000000000000." line.long 0x2C "GTST,General PWM Timer Status Register" rbitfld.long 0x2C 30. "OABLF,Same Time Output Level Low Disable Request Enable" "0: GTIOCA pin and GTIOCB pin don't output 0 at the..,1: GTIOCA pin and GTIOCB pin output 0 at the same.." rbitfld.long 0x2C 29. "OABHF,Same Time Output Level High Disable Request Enable" "0: GTIOCA pin and GTIOCB pin don't output 1 at the..,1: GTIOCA pin and GTIOCB pin output 1 at the same.." newline hexmask.long.byte 0x2C 25.--28. 1. "Reserved,These bits are read as 0000. The write value should be 0000." rbitfld.long 0x2C 24. "ODF,Output Disable Flag" "0: No output disable request is generated.,1: An output disable request is generated." newline hexmask.long.byte 0x2C 16.--23. 1. "Reserved,These bits are read as 00000000. The write value should be 00000000." rbitfld.long 0x2C 15. "TUCF,Count Direction Flag" "0: The GTCNT counter counts downward.,1: The GTCNT counter counts upward." newline hexmask.long.byte 0x2C 8.--14. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.long 0x2C 7. "TCFPU,Underflow Flag" "0: No underflow (trough) has occurred.,1: An underflow (trough) has occurred." newline bitfld.long 0x2C 6. "TCPFO,Overflow Flag" "0: No overflow (crest) has occurred.,1: An overflow (crest) has occurred." bitfld.long 0x2C 5. "TCFF,Input Compare Match Flag F" "0: No compare match of GTCCRF is generated.,1: A compare match of GTCCRF is generated." newline bitfld.long 0x2C 4. "TCFE,Input Compare Match Flag E" "0: No compare match of GTCCRE is generated.,1: A compare match of GTCCRE is generated." bitfld.long 0x2C 3. "TCFD,Input Compare Match Flag D" "0: No compare match of GTCCRD is generated.,1: A compare match of GTCCRD is generated." newline bitfld.long 0x2C 2. "TCFC,Input Compare Match Flag C" "0: No compare match of GTCCRC is generated.,1: A compare match of GTCCRC is generated." bitfld.long 0x2C 1. "TCFB,Input Capture/Compare Match Flag B" "0: No input capture/compare match of GTCCRB is..,1: An input capture/compare match of GTCCRB is.." newline bitfld.long 0x2C 0. "TCFA,Input Capture/Compare Match Flag A" "0: No input capture/compare match of GTCCRA is..,1: An input capture/compare match of GTCCRA is.." line.long 0x30 "GTBER,General PWM Timer Buffer Enable Register" bitfld.long 0x30 22. "CCRSWT,GTCCRA and GTCCRB Forcible Buffer OperationThis bit is read as 0." "0: no effect,1: Forcibly performs buffer transfer of GTCCRA and.." bitfld.long 0x30 20.--21. "PR,GTPR Buffer Operation" "0: Setting prohibited,1: Single buffer operation (GTPBR --> GTPR),?,?" newline bitfld.long 0x30 18.--19. "CCRB,GTCCRB Buffer Operation" "0: Buffer operation is not performed,1: Single buffer operation (GTCCRB <--> GTCCRE),?,?" bitfld.long 0x30 16.--17. "CCRA,GTCCRA Buffer Operation" "0: Buffer operation is not performed,1: Single buffer operation (GTCCRA <--> GTCCRC),?,?" newline bitfld.long 0x30 0.--1. "BD,BD[1]: GTPR Buffer Operation DisableBD[0]: GTCCR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled,?,?" group.long 0x48++0x23 line.long 0x0 "GTCNT,General PWM Timer Counter" hexmask.long 0x0 0.--31. 1. "GTCNT,Counter" line.long 0x4 "GTCCRA,General PWM Timer Compare Capture Register A" hexmask.long 0x4 0.--31. 1. "GTCCRA,Compare Capture Register A" line.long 0x8 "GTCCRB,General PWM Timer Compare Capture Register B" hexmask.long 0x8 0.--31. 1. "GTCCRB,Compare Capture Register B" line.long 0xC "GTCCRC,General PWM Timer Compare Capture Register C" hexmask.long 0xC 0.--31. 1. "GTCCRC,Compare Capture Register C" line.long 0x10 "GTCCRE,General PWM Timer Compare Capture Register E" hexmask.long 0x10 0.--31. 1. "GTCCRE,Compare Capture Register E" line.long 0x14 "GTCCRD,General PWM Timer Compare Capture Register D" hexmask.long 0x14 0.--31. 1. "GTCCRD,Compare Capture Register D" line.long 0x18 "GTCCRF,General PWM Timer Compare Capture Register F" hexmask.long 0x18 0.--31. 1. "GTCCRF,Compare Capture Register F" line.long 0x1C "GTPR,General PWM Timer Cycle Setting Register" hexmask.long 0x1C 0.--31. 1. "GTPR,Cycle Setting Register" line.long 0x20 "GTPBR,General PWM Timer Cycle Setting Buffer Register" hexmask.long 0x20 0.--31. 1. "GTPBR,Cycle Setting Buffer Register" group.long 0x88++0x7 line.long 0x0 "GTDTCR,General PWM Timer Dead Time Control Register" hexmask.long.tbyte 0x0 9.--31. 1. "Reserved,These bits are read as 00000000000000000000000. The write value should be 00000000000000000000000." bitfld.long 0x0 8. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.long 0x0 6.--7. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.long 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.long 0x0 4. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 1.--3. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "TDE,Negative-Phase Waveform Setting" "0: GTCCRB is set without using GTDVU and GTDVD.,1: GTDVU and GTDVD are used to set the compare.." line.long 0x4 "GTDVU,General PWM Timer Dead Time Value Register U" hexmask.long 0x4 0.--31. 1. "GTDVU,Dead Time Value Register U" tree.end tree "GPT169" base ad:0x40078900 group.long 0x0++0xB line.long 0x0 "GTWP,General PWM Timer Write-Protection Register" hexmask.long.word 0x0 16.--31. 1. "Reserved,These bits are read as 0000000000000000. The write value should be 0000000000000000." hexmask.long.byte 0x0 8.--15. 1. "PRKEY,GTWP Key Code" newline hexmask.long.byte 0x0 1.--7. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.long 0x0 0. "WP,Register Write Disable" "0: Write to the register is enabled,1: Write to the register is disabled" line.long 0x4 "GTSTR,General PWM Timer Software Start Register" hexmask.long.tbyte 0x4 10.--31. 1. "Reserved,These bits are read as 0000000000000000000000. The write value should be 0000000000000000000000." bitfld.long 0x4 9. "CSTRT9,Channel 9 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT169.GTCNT counter starts (write) / Counter.." newline bitfld.long 0x4 8. "CSTRT8,Channel 8 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT168.GTCNT counter starts (write) / Counter.." bitfld.long 0x4 7. "CSTRT7,Channel 7 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT167.GTCNT counter starts (write) / Counter.." newline bitfld.long 0x4 6. "CSTRT6,Channel 6 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT166.GTCNT counter starts (write) / Counter.." bitfld.long 0x4 5. "CSTRT5,Channel 5 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT165.GTCNT counter starts (write) / Counter.." newline bitfld.long 0x4 4. "CSTRT4,Channel 4 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT164.GTCNT counter starts (write) / Counter.." bitfld.long 0x4 3. "CSTRT3,Channel 3 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT323.GTCNT counter starts (write) / Counter.." newline bitfld.long 0x4 2. "CSTRT2,Channel 2 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT322.GTCNT counter starts (write) / Counter.." bitfld.long 0x4 1. "CSTRT1,Channel 1 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT321.GTCNT counter starts (write) / Counter.." newline bitfld.long 0x4 0. "CSTRT0,Channel 0 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT320.GTCNT counter starts (write) / Counter.." line.long 0x8 "GTSTP,General PWM Timer Software Stop Register" hexmask.long.tbyte 0x8 10.--31. 1. "Reserved,These bits are read as 1111111111111111111111. The write value should be 1111111111111111111111." bitfld.long 0x8 9. "CSTOP9,Channel 9 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT169.GTCNT counter stops (write) / Counter.." newline bitfld.long 0x8 8. "CSTOP8,Channel 8 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT168.GTCNT counter stops (write) / Counter.." bitfld.long 0x8 7. "CSTOP7,Channel 7 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT167.GTCNT counter stops (write) / Counter.." newline bitfld.long 0x8 6. "CSTOP6,Channel 6 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT166.GTCNT counter stops (write) / Counter.." bitfld.long 0x8 5. "CSTOP5,Channel 5 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT165.GTCNT counter stops (write) / Counter.." newline bitfld.long 0x8 4. "CSTOP4,Channel 4 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT164.GTCNT counter stops (write) / Counter.." bitfld.long 0x8 3. "CSTOP3,Channel 3 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT323.GTCNT counter stops (write) / Counter.." newline bitfld.long 0x8 2. "CSTOP2,Channel 2 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT322.GTCNT counter stops (write) / Counter.." bitfld.long 0x8 1. "CSTOP1,Channel 1 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT321.GTCNT counter stops (write) / Counter.." newline bitfld.long 0x8 0. "CSTOP0,Channel 0 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT320.GTCNT counter stops (write) / Counter.." wgroup.long 0xC++0x3 line.long 0x0 "GTCLR,General PWM Timer Software Clear Register" hexmask.long.tbyte 0x0 10.--31. 1. "Reserved,The write value should be 0000000000000000000000." bitfld.long 0x0 9. "CCLR9,Channel 9 GTCNT Count Clear" "0: No effect,1: GPT169.GTCNT counter clears" newline bitfld.long 0x0 8. "CCLR8,Channel 8 GTCNT Count Clear" "0: No effect,1: GPT168.GTCNT counter clears" bitfld.long 0x0 7. "CCLR7,Channel 7 GTCNT Count Clear" "0: No effect,1: GPT167.GTCNT counter clears" newline bitfld.long 0x0 6. "CCLR6,Channel 6 GTCNT Count Clear" "0: No effect,1: GPT166.GTCNT counter clears" bitfld.long 0x0 5. "CCLR5,Channel 5 GTCNT Count Clear" "0: No effect,1: GPT165.GTCNT counter clears" newline bitfld.long 0x0 4. "CCLR4,Channel 4 GTCNT Count Clear" "0: No effect,1: GPT164.GTCNT counter clears" bitfld.long 0x0 3. "CCLR3,Channel 3 GTCNT Count Clear" "0: No effect,1: GPT323.GTCNT counter clears" newline bitfld.long 0x0 2. "CCLR2,Channel 2 GTCNT Count Clear" "0: No effect,1: GPT322.GTCNT counter clears" bitfld.long 0x0 1. "CCLR1,Channel 1 GTCNT Count Clear" "0: No effect,1: GPT321.GTCNT counter clears" newline bitfld.long 0x0 0. "CCLR0,Channel 0 GTCNT Count Clear" "0: No effect,1: GPT320.GTCNT counter clears" group.long 0x10++0x33 line.long 0x0 "GTSSR,General PWM Timer Start Source Select Register" bitfld.long 0x0 31. "CSTRT,Software Source Counter Start Enable" "0: Counter start is disable by the GTSTR register,1: Counter start is enable by the GTSTR register" hexmask.long.byte 0x0 24.--30. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." newline bitfld.long 0x0 23. "SSELCH,ELC_GPTH Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTH input,1: Counter start is enable at the ELC_GPTH input" bitfld.long 0x0 22. "SSELCG,ELC_GPTG Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTG input,1: Counter start is enable at the ELC_GPTG input" newline bitfld.long 0x0 21. "SSELCF,ELC_GPTF Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTF input,1: Counter start is enable at the ELC_GPTF input" bitfld.long 0x0 20. "SSELCE,ELC_GPTE Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTE input,1: Counter start is enable at the ELC_GPTE input" newline bitfld.long 0x0 19. "SSELCD,ELC_GPTD Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTD input,1: Counter start is enable at the ELC_GPTD input" bitfld.long 0x0 18. "SSELCC,ELC_GPTC Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTC input,1: Counter start is enable at the ELC_GPTC input" newline bitfld.long 0x0 17. "SSELCB,ELC_GPTB Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTB input,1: Counter start is enable at the ELC_GPTB input" bitfld.long 0x0 16. "SSELCA,ELC_GPTA Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTA input,1: Counter start is enable at the ELC_GPTA input" newline bitfld.long 0x0 15. "SSCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." bitfld.long 0x0 14. "SSCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." newline bitfld.long 0x0 13. "SSCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." bitfld.long 0x0 12. "SSCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." newline bitfld.long 0x0 11. "SSCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." bitfld.long 0x0 10. "SSCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." newline bitfld.long 0x0 9. "SSCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." bitfld.long 0x0 8. "SSCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." newline hexmask.long.byte 0x0 4.--7. 1. "Reserved,These bits are read as 0000. The write value should be 0000." bitfld.long 0x0 3. "SSGTRGBF,GTETRGB Pin Falling Input Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." newline bitfld.long 0x0 2. "SSGTRGBR,GTETRGB Pin Rising Input Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." bitfld.long 0x0 1. "SSGTRGAF,GTETRGA Pin Falling Input Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." newline bitfld.long 0x0 0. "SSGTRGAR,GTETRGA Pin Rising Input Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." line.long 0x4 "GTPSR,General PWM Timer Stop Source Select Register" bitfld.long 0x4 31. "CSTOP,Software Source Counter Stop Enable" "0: Counter stop is disable by the GTSTP register,1: Counter stop is enable by the GTSTP register" hexmask.long.byte 0x4 24.--30. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." newline bitfld.long 0x4 23. "PSELCH,ELC_GPTH Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTH input,1: Counter stop is enable at the ELC_GPTH input" bitfld.long 0x4 22. "PSELCG,ELC_GPTG Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTG input,1: Counter stop is enable at the ELC_GPTG input" newline bitfld.long 0x4 21. "PSELCF,ELC_GPTF Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTF input,1: Counter stop is enable at the ELC_GPTF input" bitfld.long 0x4 20. "PSELCE,ELC_GPTE Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTE input,1: Counter stop is enable at the ELC_GPTE input" newline bitfld.long 0x4 19. "PSELCD,ELC_GPTD Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTD input,1: Counter stop is enable at the ELC_GPTD input" bitfld.long 0x4 18. "PSELCC,ELC_GPTC Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTC input,1: Counter stop is enable at the ELC_GPTC input" newline bitfld.long 0x4 17. "PSELCB,ELC_GPTB Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTB input,1: Counter stop is enable at the ELC_GPTB input" bitfld.long 0x4 16. "PSELCA,ELC_GPTA Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTA input,1: Counter stop is enable at the ELC_GPTA input" newline bitfld.long 0x4 15. "PSCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." bitfld.long 0x4 14. "PSCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." newline bitfld.long 0x4 13. "PSCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." bitfld.long 0x4 12. "PSCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." newline bitfld.long 0x4 11. "PSCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." bitfld.long 0x4 10. "PSCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." newline bitfld.long 0x4 9. "PSCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." bitfld.long 0x4 8. "PSCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." newline hexmask.long.byte 0x4 4.--7. 1. "Reserved,These bits are read as 0000. The write value should be 0000." bitfld.long 0x4 3. "PSGTRGBF,GTETRGB Pin Falling Input Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." newline bitfld.long 0x4 2. "PSGTRGBR,GTETRGB Pin Rising Input Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." bitfld.long 0x4 1. "PSGTRGAF,GTETRGA Pin Falling Input Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." newline bitfld.long 0x4 0. "PSGTRGAR,GTETRGA Pin Rising Input Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." line.long 0x8 "GTCSR,General PWM Timer Clear Source Select Register" bitfld.long 0x8 31. "CCLR,Software Source Counter Clear Enable" "0: Counter clear is disable by the GTCLR register,1: Counter clear is enable by the GTCLR register" hexmask.long.byte 0x8 24.--30. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." newline bitfld.long 0x8 23. "CSELCH,ELC_GPTH Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTH input,1: Counter clear is enable at the ELC_GPTH input" bitfld.long 0x8 22. "CSELCG,ELC_GPTG Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTG input,1: Counter clear is enable at the ELC_GPTG input" newline bitfld.long 0x8 21. "CSELCF,ELC_GPTF Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTF input,1: Counter clear is enable at the ELC_GPTF input" bitfld.long 0x8 20. "CSELCE,ELC_GPTE Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTE input,1: Counter clear is enable at the ELC_GPTE input" newline bitfld.long 0x8 19. "CSELCD,ELC_GPTD Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTD input,1: Counter clear is enable at the ELC_GPTD input" bitfld.long 0x8 18. "CSELCC,ELC_GPTC Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTC input,1: Counter clear is enable at the ELC_GPTC input" newline bitfld.long 0x8 17. "CSELCB,ELC_GPTB Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTB input,1: Counter clear is enable at the ELC_GPTB input" bitfld.long 0x8 16. "CSELCA,ELC_GPTA Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTA input,1: Counter clear is enable at the ELC_GPTA input" newline bitfld.long 0x8 15. "CSCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." bitfld.long 0x8 14. "CSCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." newline bitfld.long 0x8 13. "CSCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." bitfld.long 0x8 12. "CSCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." newline bitfld.long 0x8 11. "CSCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." bitfld.long 0x8 10. "CSCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." newline bitfld.long 0x8 9. "CSCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." bitfld.long 0x8 8. "CSCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." newline hexmask.long.byte 0x8 4.--7. 1. "Reserved,These bits are read as 0000. The write value should be 0000." bitfld.long 0x8 3. "CSGTRGBF,GTETRGB Pin Falling Input Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." newline bitfld.long 0x8 2. "CSGTRGBR,GTETRGB Pin Rising Input Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." bitfld.long 0x8 1. "CSGTRGAF,GTETRGA Pin Falling Input Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." newline bitfld.long 0x8 0. "CSGTRGAR,GTETRGA Pin Rising Input Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." line.long 0xC "GTUPSR,General PWM Timer Up Count Source Select Register" bitfld.long 0xC 23. "USELCH,ELC_GPTH Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTH input,1: Counter count up is enable at the ELC_GPTH input" bitfld.long 0xC 22. "USELCG,ELC_GPTG Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTG input,1: Counter count up is enable at the ELC_GPTG input" newline bitfld.long 0xC 21. "USELCF,ELC_GPTF Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTF input,1: Counter count up is enable at the ELC_GPTF input" bitfld.long 0xC 20. "USELCE,ELC_GPTE Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTE input,1: Counter count up is enable at the ELC_GPTE input" newline bitfld.long 0xC 19. "USELCD,ELC_GPTD Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTD input,1: Counter count up is enable at the ELC_GPTD input" bitfld.long 0xC 18. "USELCC,ELC_GPTC Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTC input,1: Counter count up is enable at the ELC_GPTC input" newline bitfld.long 0xC 17. "USELCB,ELC_GPTB Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTB input,1: Counter count up is enable at the ELC_GPTB input" bitfld.long 0xC 16. "USELCA,ELC_GPTA Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTA input,1: Counter count up is enable at the ELC_GPTA input" newline bitfld.long 0xC 15. "USCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." bitfld.long 0xC 14. "USCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." newline bitfld.long 0xC 13. "USCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." bitfld.long 0xC 12. "USCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." newline bitfld.long 0xC 11. "USCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." bitfld.long 0xC 10. "USCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." newline bitfld.long 0xC 9. "USCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." bitfld.long 0xC 8. "USCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." newline bitfld.long 0xC 3. "USGTRGBF,GTETRGB Pin Falling Input Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." bitfld.long 0xC 2. "USGTRGBR,GTETRGB Pin Rising Input Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." newline bitfld.long 0xC 1. "USGTRGAF,GTETRGA Pin Falling Input Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." bitfld.long 0xC 0. "USGTRGAR,GTETRGA Pin Rising Input Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." line.long 0x10 "GTDNSR,General PWM Timer Down Count Source Select Register" bitfld.long 0x10 23. "DSELCH,ELC_GPTH Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTH..,1: Counter count down is enable at the ELC_GPTH input" bitfld.long 0x10 22. "DSELCG,ELC_GPTG Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTG..,1: Counter count down is enable at the ELC_GPTG input" newline bitfld.long 0x10 21. "DSELCF,ELC_GPTF Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTF..,1: Counter count down is enable at the ELC_GPTF input" bitfld.long 0x10 20. "DSELCE,ELC_GPTE Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTE..,1: Counter count down is enable at the ELC_GPTE input" newline bitfld.long 0x10 19. "DSELCD,ELC_GPTD Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTD..,1: Counter count down is enable at the ELC_GPTD input" bitfld.long 0x10 18. "DSELCC,ELC_GPTC Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTC..,1: Counter count down is enable at the ELC_GPTC input" newline bitfld.long 0x10 17. "DSELCB,ELC_GPTB Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTB..,1: Counter count down is enable at the ELC_GPTB input" bitfld.long 0x10 16. "DSELCA,ELC_GPTA Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTA..,1: Counter count down is enable at the ELC_GPTA input" newline bitfld.long 0x10 15. "DSCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." bitfld.long 0x10 14. "DSCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." newline bitfld.long 0x10 13. "DSCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." bitfld.long 0x10 12. "DSCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." newline bitfld.long 0x10 11. "DSCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." bitfld.long 0x10 10. "DSCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." newline bitfld.long 0x10 9. "DSCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." bitfld.long 0x10 8. "DSCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." newline bitfld.long 0x10 3. "DSGTRGBF,GTETRGB Pin Falling Input Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." bitfld.long 0x10 2. "DSGTRGBR,GTETRGB Pin Rising Input Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." newline bitfld.long 0x10 1. "DSGTRGAF,GTETRGA Pin Falling Input Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." bitfld.long 0x10 0. "DSGTRGAR,GTETRGA Pin Rising Input Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." line.long 0x14 "GTICASR,General PWM Timer Input Capture Source Select Register A" bitfld.long 0x14 23. "ASELCH,ELC_GPTH Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTH..,1: GTCCRA input capture is enable at the ELC_GPTH.." bitfld.long 0x14 22. "ASELCG,ELC_GPTG Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTG..,1: GTCCRA input capture is enable at the ELC_GPTG.." newline bitfld.long 0x14 21. "ASELCF,ELC_GPTF Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTF..,1: GTCCRA input capture is enable at the ELC_GPTF.." bitfld.long 0x14 20. "ASELCE,ELC_GPTE Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTE..,1: GTCCRA input capture is enable at the ELC_GPTE.." newline bitfld.long 0x14 19. "ASELCD,ELC_GPTD Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTD..,1: GTCCRA input capture is enable at the ELC_GPTD.." bitfld.long 0x14 18. "ASELCC,ELC_GPTC Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTC..,1: GTCCRA input capture is enable at the ELC_GPTC.." newline bitfld.long 0x14 17. "ASELCB,ELC_GPTB Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTB..,1: GTCCRA input capture is enable at the ELC_GPTB.." bitfld.long 0x14 16. "ASELCA,ELC_GPTA Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTA..,1: GTCCRA input capture is enable at the ELC_GPTA.." newline bitfld.long 0x14 15. "ASCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." bitfld.long 0x14 14. "ASCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." newline bitfld.long 0x14 13. "ASCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." bitfld.long 0x14 12. "ASCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." newline bitfld.long 0x14 11. "ASCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." bitfld.long 0x14 10. "ASCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." newline bitfld.long 0x14 9. "ASCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." bitfld.long 0x14 8. "ASCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." newline bitfld.long 0x14 3. "ASGTRGBF,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." bitfld.long 0x14 2. "ASGTRGBR,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." newline bitfld.long 0x14 1. "ASGTRGAF,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." bitfld.long 0x14 0. "ASGTRGAR,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." line.long 0x18 "GTICBSR,General PWM Timer Input Capture Source Select Register B" bitfld.long 0x18 23. "BSELCH,ELC_GPTH Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTH..,1: GTCCRB input capture is enable at the ELC_GPTH.." bitfld.long 0x18 22. "BSELCG,ELC_GPTG Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTG..,1: GTCCRB input capture is enable at the ELC_GPTG.." newline bitfld.long 0x18 21. "BSELCF,ELC_GPTF Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTF..,1: GTCCRB input capture is enable at the ELC_GPTF.." bitfld.long 0x18 20. "BSELCE,ELC_GPTE Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTE..,1: GTCCRB input capture is enable at the ELC_GPTE.." newline bitfld.long 0x18 19. "BSELCD,ELC_GPTD Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTD..,1: GTCCRB input capture is enable at the ELC_GPTD.." bitfld.long 0x18 18. "BSELCC,ELC_GPTC Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTC..,1: GTCCRB input capture is enable at the ELC_GPTC.." newline bitfld.long 0x18 17. "BSELCB,ELC_GPTB Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTB..,1: GTCCRB input capture is enable at the ELC_GPTB.." bitfld.long 0x18 16. "BSELCA,ELC_GPTA Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTA..,1: GTCCRB input capture is enable at the ELC_GPTA.." newline bitfld.long 0x18 15. "BSCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." bitfld.long 0x18 14. "BSCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." newline bitfld.long 0x18 13. "BSCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." bitfld.long 0x18 12. "BSCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." newline bitfld.long 0x18 11. "BSCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." bitfld.long 0x18 10. "BSCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." newline bitfld.long 0x18 9. "BSCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." bitfld.long 0x18 8. "BSCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." newline bitfld.long 0x18 3. "BSGTRGBF,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." bitfld.long 0x18 2. "BSGTRGBR,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." newline bitfld.long 0x18 1. "BSGTRGAF,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." bitfld.long 0x18 0. "BSGTRGAR,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." line.long 0x1C "GTCR,General PWM Timer Control Register" bitfld.long 0x1C 24.--26. "TPCS,Timer Prescaler Select" "0: Setting prohibied,1: PCLK/4,?,?,?,?,?,?" hexmask.long.byte 0x1C 19.--23. 1. "Reserved,These bits are read as 00000. The write value should be 00000." newline bitfld.long 0x1C 16.--18. "MD,Mode Select" "0: Saw-wave PWM mode (single buffer or double..,1: Saw-wave one-shot pulse mode (fixed buffer..,?,?,?,?,?,?" hexmask.long.word 0x1C 1.--15. 1. "Reserved,These bits are read as 000000000000000. The write value should be 000000000000000." newline bitfld.long 0x1C 0. "CST,Count Start" "0: Count operation is stopped,1: Count operation is performed" line.long 0x20 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register" bitfld.long 0x20 27. "OBDTYR,GTIOCB Output Value Selecting after Releasing 0 percent/100 percent Duty Setting" "0: Apply output value set in 0 percent/100 percent..,1: Apply masked compare match output value to.." bitfld.long 0x20 26. "OBDTYF,Forcible GTIOCB Output Duty Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x20 24.--25. "OBDTY,GTIOCB Output Duty Setting" "0: GTIOCB pin duty is depend on compare match,1: GTIOCB pin duty is depend on compare match,?,?" hexmask.long.byte 0x20 20.--23. 1. "Reserved,These bits are read as 0000. The write value should be 0000." newline bitfld.long 0x20 19. "OADTYR,GTIOCA Output Value Selecting after Releasing 0 percent/100 percent Duty Setting" "0: Apply output value set in 0 percent/100 percent..,1: Apply masked compare match output value to.." bitfld.long 0x20 18. "OADTYF,Forcible GTIOCA Output Duty Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x20 16.--17. "OADTY,GTIOCA Output Duty Setting" "0: GTIOCA pin duty is depend on compare match,1: GTIOCA pin duty is depend on compare match,?,?" bitfld.long 0x20 1. "UDF,Forcible Count Direction Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x20 0. "UD,Count Direction Setting" "0: GTCNT counts down.,1: GTCNT counts up." line.long 0x24 "GTIOR,General PWM Timer I/O Control Register" bitfld.long 0x24 30.--31. "NFCSB,Noise Filter B Sampling Clock Select" "0: PCLK/1,1: PCLK/4,?,?" bitfld.long 0x24 29. "NFBEN,Noise Filter B Enable" "0: The noise filter for the GTIOCB pin is disabled.,1: The noise filter for the GTIOCB pin is enabled." newline bitfld.long 0x24 27.--28. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.long 0x24 25.--26. "OBDF,GTIOCB Pin Disable Value Setting" "0: Output disable is prohibited.,1: GTIOCB pin is set to Hi-Z when output disable is..,?,?" newline bitfld.long 0x24 24. "OBE,GTIOCB Pin Output Enable" "0: Output is disabled,1: Output is enabled" bitfld.long 0x24 23. "OBHLD,GTIOCB Pin Output Setting at the Start/Stop Count" "0: The GTIOCB pin output level at start/stop of..,1: The GTIOCB pin output level is retained at.." newline bitfld.long 0x24 22. "OBDFLT,GTIOCB Pin Output Value Setting at the Count Stop" "0: The GTIOCB pin outputs low when counting is..,1: The GTIOCB pin outputs high when counting is.." bitfld.long 0x24 21. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline hexmask.long.byte 0x24 16.--20. 1. "GTIOB,GTIOCB Pin Function Select" bitfld.long 0x24 14.--15. "NFCSA,Noise Filter A Sampling Clock Select" "0: PCLK/1,1: PCLK/4,?,?" newline bitfld.long 0x24 13. "NFAEN,Noise Filter A Enable" "0: The noise filter for the GTIOCA pin is disabled.,1: The noise filter for the GTIOCA pin is enabled." bitfld.long 0x24 11.--12. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" newline bitfld.long 0x24 9.--10. "OADF,GTIOCA Pin Disable Value Setting" "0: Output disable is prohibited.,1: GTIOCA pin is set to Hi-Z when output disable is..,?,?" bitfld.long 0x24 8. "OAE,GTIOCA Pin Output Enable" "0: Output is disabled,1: Output is enabled" newline bitfld.long 0x24 7. "OAHLD,GTIOCA Pin Output Setting at the Start/Stop Count" "0: The GTIOCA pin output level at start/stop of..,1: The GTIOCA pin output level is retained at.." bitfld.long 0x24 6. "OADFLT,GTIOCA Pin Output Value Setting at the Count Stop" "0: The GTIOCA pin outputs low when counting is..,1: The GTIOCA pin outputs high when counting is.." newline bitfld.long 0x24 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" hexmask.long.byte 0x24 0.--4. 1. "GTIOA,GTIOCA Pin Function Select" line.long 0x28 "GTINTAD,General PWM Timer Interrupt Output Setting Register" bitfld.long 0x28 30. "GRPABL,Same Time Output Level Low Disable Request Enable" "0: Same time output level low disable request is..,1: Same time output level low disable request is.." bitfld.long 0x28 29. "GRPABH,Same Time Output Level High Disable Request Enable" "0: Same time output level high disable request is..,1: Same time output level high disable request is.." newline bitfld.long 0x28 26.--28. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.long 0x28 24.--25. "GRP,Output Disable Source Select" "0: Setting prohibited,1: Group B output disable request,?,?" newline hexmask.long.tbyte 0x28 0.--23. 1. "Reserved,These bits are read as 000000000000000000000000. The write value should be 000000000000000000000000." line.long 0x2C "GTST,General PWM Timer Status Register" rbitfld.long 0x2C 30. "OABLF,Same Time Output Level Low Disable Request Enable" "0: GTIOCA pin and GTIOCB pin don't output 0 at the..,1: GTIOCA pin and GTIOCB pin output 0 at the same.." rbitfld.long 0x2C 29. "OABHF,Same Time Output Level High Disable Request Enable" "0: GTIOCA pin and GTIOCB pin don't output 1 at the..,1: GTIOCA pin and GTIOCB pin output 1 at the same.." newline hexmask.long.byte 0x2C 25.--28. 1. "Reserved,These bits are read as 0000. The write value should be 0000." rbitfld.long 0x2C 24. "ODF,Output Disable Flag" "0: No output disable request is generated.,1: An output disable request is generated." newline hexmask.long.byte 0x2C 16.--23. 1. "Reserved,These bits are read as 00000000. The write value should be 00000000." rbitfld.long 0x2C 15. "TUCF,Count Direction Flag" "0: The GTCNT counter counts downward.,1: The GTCNT counter counts upward." newline hexmask.long.byte 0x2C 8.--14. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.long 0x2C 7. "TCFPU,Underflow Flag" "0: No underflow (trough) has occurred.,1: An underflow (trough) has occurred." newline bitfld.long 0x2C 6. "TCPFO,Overflow Flag" "0: No overflow (crest) has occurred.,1: An overflow (crest) has occurred." bitfld.long 0x2C 5. "TCFF,Input Compare Match Flag F" "0: No compare match of GTCCRF is generated.,1: A compare match of GTCCRF is generated." newline bitfld.long 0x2C 4. "TCFE,Input Compare Match Flag E" "0: No compare match of GTCCRE is generated.,1: A compare match of GTCCRE is generated." bitfld.long 0x2C 3. "TCFD,Input Compare Match Flag D" "0: No compare match of GTCCRD is generated.,1: A compare match of GTCCRD is generated." newline bitfld.long 0x2C 2. "TCFC,Input Compare Match Flag C" "0: No compare match of GTCCRC is generated.,1: A compare match of GTCCRC is generated." bitfld.long 0x2C 1. "TCFB,Input Capture/Compare Match Flag B" "0: No input capture/compare match of GTCCRB is..,1: An input capture/compare match of GTCCRB is.." newline bitfld.long 0x2C 0. "TCFA,Input Capture/Compare Match Flag A" "0: No input capture/compare match of GTCCRA is..,1: An input capture/compare match of GTCCRA is.." line.long 0x30 "GTBER,General PWM Timer Buffer Enable Register" bitfld.long 0x30 22. "CCRSWT,GTCCRA and GTCCRB Forcible Buffer OperationThis bit is read as 0." "0: no effect,1: Forcibly performs buffer transfer of GTCCRA and.." bitfld.long 0x30 20.--21. "PR,GTPR Buffer Operation" "0: Setting prohibited,1: Single buffer operation (GTPBR --> GTPR),?,?" newline bitfld.long 0x30 18.--19. "CCRB,GTCCRB Buffer Operation" "0: Buffer operation is not performed,1: Single buffer operation (GTCCRB <--> GTCCRE),?,?" bitfld.long 0x30 16.--17. "CCRA,GTCCRA Buffer Operation" "0: Buffer operation is not performed,1: Single buffer operation (GTCCRA <--> GTCCRC),?,?" newline bitfld.long 0x30 0.--1. "BD,BD[1]: GTPR Buffer Operation DisableBD[0]: GTCCR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled,?,?" group.long 0x48++0x23 line.long 0x0 "GTCNT,General PWM Timer Counter" hexmask.long 0x0 0.--31. 1. "GTCNT,Counter" line.long 0x4 "GTCCRA,General PWM Timer Compare Capture Register A" hexmask.long 0x4 0.--31. 1. "GTCCRA,Compare Capture Register A" line.long 0x8 "GTCCRB,General PWM Timer Compare Capture Register B" hexmask.long 0x8 0.--31. 1. "GTCCRB,Compare Capture Register B" line.long 0xC "GTCCRC,General PWM Timer Compare Capture Register C" hexmask.long 0xC 0.--31. 1. "GTCCRC,Compare Capture Register C" line.long 0x10 "GTCCRE,General PWM Timer Compare Capture Register E" hexmask.long 0x10 0.--31. 1. "GTCCRE,Compare Capture Register E" line.long 0x14 "GTCCRD,General PWM Timer Compare Capture Register D" hexmask.long 0x14 0.--31. 1. "GTCCRD,Compare Capture Register D" line.long 0x18 "GTCCRF,General PWM Timer Compare Capture Register F" hexmask.long 0x18 0.--31. 1. "GTCCRF,Compare Capture Register F" line.long 0x1C "GTPR,General PWM Timer Cycle Setting Register" hexmask.long 0x1C 0.--31. 1. "GTPR,Cycle Setting Register" line.long 0x20 "GTPBR,General PWM Timer Cycle Setting Buffer Register" hexmask.long 0x20 0.--31. 1. "GTPBR,Cycle Setting Buffer Register" group.long 0x88++0x7 line.long 0x0 "GTDTCR,General PWM Timer Dead Time Control Register" hexmask.long.tbyte 0x0 9.--31. 1. "Reserved,These bits are read as 00000000000000000000000. The write value should be 00000000000000000000000." bitfld.long 0x0 8. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.long 0x0 6.--7. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.long 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.long 0x0 4. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 1.--3. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "TDE,Negative-Phase Waveform Setting" "0: GTCCRB is set without using GTDVU and GTDVD.,1: GTDVU and GTDVD are used to set the compare.." line.long 0x4 "GTDVU,General PWM Timer Dead Time Value Register U" hexmask.long 0x4 0.--31. 1. "GTDVU,Dead Time Value Register U" tree.end tree "GPT320" base ad:0x40078000 group.long 0x0++0xB line.long 0x0 "GTWP,General PWM Timer Write-Protection Register" hexmask.long.word 0x0 16.--31. 1. "Reserved,These bits are read as 0000000000000000. The write value should be 0000000000000000." hexmask.long.byte 0x0 8.--15. 1. "PRKEY,GTWP Key Code" newline hexmask.long.byte 0x0 1.--7. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.long 0x0 0. "WP,Register Write Disable" "0: Write to the register is enabled,1: Write to the register is disabled" line.long 0x4 "GTSTR,General PWM Timer Software Start Register" hexmask.long.tbyte 0x4 10.--31. 1. "Reserved,These bits are read as 0000000000000000000000. The write value should be 0000000000000000000000." bitfld.long 0x4 9. "CSTRT9,Channel 9 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT169.GTCNT counter starts (write) / Counter.." newline bitfld.long 0x4 8. "CSTRT8,Channel 8 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT168.GTCNT counter starts (write) / Counter.." bitfld.long 0x4 7. "CSTRT7,Channel 7 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT167.GTCNT counter starts (write) / Counter.." newline bitfld.long 0x4 6. "CSTRT6,Channel 6 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT166.GTCNT counter starts (write) / Counter.." bitfld.long 0x4 5. "CSTRT5,Channel 5 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT165.GTCNT counter starts (write) / Counter.." newline bitfld.long 0x4 4. "CSTRT4,Channel 4 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT164.GTCNT counter starts (write) / Counter.." bitfld.long 0x4 3. "CSTRT3,Channel 3 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT323.GTCNT counter starts (write) / Counter.." newline bitfld.long 0x4 2. "CSTRT2,Channel 2 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT322.GTCNT counter starts (write) / Counter.." bitfld.long 0x4 1. "CSTRT1,Channel 1 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT321.GTCNT counter starts (write) / Counter.." newline bitfld.long 0x4 0. "CSTRT0,Channel 0 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT320.GTCNT counter starts (write) / Counter.." line.long 0x8 "GTSTP,General PWM Timer Software Stop Register" hexmask.long.tbyte 0x8 10.--31. 1. "Reserved,These bits are read as 1111111111111111111111. The write value should be 1111111111111111111111." bitfld.long 0x8 9. "CSTOP9,Channel 9 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT169.GTCNT counter stops (write) / Counter.." newline bitfld.long 0x8 8. "CSTOP8,Channel 8 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT168.GTCNT counter stops (write) / Counter.." bitfld.long 0x8 7. "CSTOP7,Channel 7 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT167.GTCNT counter stops (write) / Counter.." newline bitfld.long 0x8 6. "CSTOP6,Channel 6 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT166.GTCNT counter stops (write) / Counter.." bitfld.long 0x8 5. "CSTOP5,Channel 5 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT165.GTCNT counter stops (write) / Counter.." newline bitfld.long 0x8 4. "CSTOP4,Channel 4 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT164.GTCNT counter stops (write) / Counter.." bitfld.long 0x8 3. "CSTOP3,Channel 3 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT323.GTCNT counter stops (write) / Counter.." newline bitfld.long 0x8 2. "CSTOP2,Channel 2 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT322.GTCNT counter stops (write) / Counter.." bitfld.long 0x8 1. "CSTOP1,Channel 1 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT321.GTCNT counter stops (write) / Counter.." newline bitfld.long 0x8 0. "CSTOP0,Channel 0 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT320.GTCNT counter stops (write) / Counter.." wgroup.long 0xC++0x3 line.long 0x0 "GTCLR,General PWM Timer Software Clear Register" hexmask.long.tbyte 0x0 10.--31. 1. "Reserved,The write value should be 0000000000000000000000." bitfld.long 0x0 9. "CCLR9,Channel 9 GTCNT Count Clear" "0: No effect,1: GPT169.GTCNT counter clears" newline bitfld.long 0x0 8. "CCLR8,Channel 8 GTCNT Count Clear" "0: No effect,1: GPT168.GTCNT counter clears" bitfld.long 0x0 7. "CCLR7,Channel 7 GTCNT Count Clear" "0: No effect,1: GPT167.GTCNT counter clears" newline bitfld.long 0x0 6. "CCLR6,Channel 6 GTCNT Count Clear" "0: No effect,1: GPT166.GTCNT counter clears" bitfld.long 0x0 5. "CCLR5,Channel 5 GTCNT Count Clear" "0: No effect,1: GPT165.GTCNT counter clears" newline bitfld.long 0x0 4. "CCLR4,Channel 4 GTCNT Count Clear" "0: No effect,1: GPT164.GTCNT counter clears" bitfld.long 0x0 3. "CCLR3,Channel 3 GTCNT Count Clear" "0: No effect,1: GPT323.GTCNT counter clears" newline bitfld.long 0x0 2. "CCLR2,Channel 2 GTCNT Count Clear" "0: No effect,1: GPT322.GTCNT counter clears" bitfld.long 0x0 1. "CCLR1,Channel 1 GTCNT Count Clear" "0: No effect,1: GPT321.GTCNT counter clears" newline bitfld.long 0x0 0. "CCLR0,Channel 0 GTCNT Count Clear" "0: No effect,1: GPT320.GTCNT counter clears" group.long 0x10++0x33 line.long 0x0 "GTSSR,General PWM Timer Start Source Select Register" bitfld.long 0x0 31. "CSTRT,Software Source Counter Start Enable" "0: Counter start is disable by the GTSTR register,1: Counter start is enable by the GTSTR register" hexmask.long.byte 0x0 24.--30. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." newline bitfld.long 0x0 23. "SSELCH,ELCH Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTH input,1: Counter start is enable at the ELC_GPTH input" bitfld.long 0x0 22. "SSELCG,ELC_GPTG Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTG input,1: Counter start is enable at the ELC_GPTG input" newline bitfld.long 0x0 21. "SSELCF,ELC_GPTF Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTF input,1: Counter start is enable at the ELC_GPTF input" bitfld.long 0x0 20. "SSELCE,ELC_GPTE Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTE input,1: Counter start is enable at the ELC_GPTE input" newline bitfld.long 0x0 19. "SSELCD,ELC_GPTD Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTD input,1: Counter start is enable at the ELC_GPTD input" bitfld.long 0x0 18. "SSELCC,ELC_GPTC Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTC input,1: Counter start is enable at the ELC_GPTC input" newline bitfld.long 0x0 17. "SSELCB,ELC_GPTB Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTB input,1: Counter start is enable at the ELC_GPTB input" bitfld.long 0x0 16. "SSELCA,ELC_GPTA Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTA input,1: Counter start is enable at the ELC_GPTA input" newline bitfld.long 0x0 15. "SSCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." bitfld.long 0x0 14. "SSCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." newline bitfld.long 0x0 13. "SSCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." bitfld.long 0x0 12. "SSCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." newline bitfld.long 0x0 11. "SSCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." bitfld.long 0x0 10. "SSCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." newline bitfld.long 0x0 9. "SSCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." bitfld.long 0x0 8. "SSCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." newline hexmask.long.byte 0x0 4.--7. 1. "Reserved,These bits are read as 0000. The write value should be 0000." bitfld.long 0x0 3. "SSGTRGBF,GTETRGB Pin Falling Input Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." newline bitfld.long 0x0 2. "SSGTRGBR,GTETRGB Pin Rising Input Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." bitfld.long 0x0 1. "SSGTRGAF,GTETRGA Pin Falling Input Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." newline bitfld.long 0x0 0. "SSGTRGAR,GTETRGA Pin Rising Input Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." line.long 0x4 "GTPSR,General PWM Timer Stop Source Select Register" bitfld.long 0x4 31. "CSTOP,Software Source Counter Stop Enable" "0: Counter stop is disable by the GTSTP register,1: Counter stop is enable by the GTSTP register" hexmask.long.byte 0x4 24.--30. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." newline bitfld.long 0x4 23. "PSELCH,ELCH Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTH input,1: Counter stop is enable at the ELC_GPTH input" bitfld.long 0x4 22. "PSELCG,ELC_GPTG Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTG input,1: Counter stop is enable at the ELC_GPTG input" newline bitfld.long 0x4 21. "PSELCF,ELC_GPTF Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTF input,1: Counter stop is enable at the ELC_GPTF input" bitfld.long 0x4 20. "PSELCE,ELC_GPTE Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTE input,1: Counter stop is enable at the ELC_GPTE input" newline bitfld.long 0x4 19. "PSELCD,ELC_GPTD Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTD input,1: Counter stop is enable at the ELC_GPTD input" bitfld.long 0x4 18. "PSELCC,ELC_GPTC Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTC input,1: Counter stop is enable at the ELC_GPTC input" newline bitfld.long 0x4 17. "PSELCB,ELC_GPTB Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTB input,1: Counter stop is enable at the ELC_GPTB input" bitfld.long 0x4 16. "PSELCA,ELC_GPTA Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTA input,1: Counter stop is enable at the ELC_GPTA input" newline bitfld.long 0x4 15. "PSCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." bitfld.long 0x4 14. "PSCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." newline bitfld.long 0x4 13. "PSCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." bitfld.long 0x4 12. "PSCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." newline bitfld.long 0x4 11. "PSCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." bitfld.long 0x4 10. "PSCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." newline bitfld.long 0x4 9. "PSCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." bitfld.long 0x4 8. "PSCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." newline hexmask.long.byte 0x4 4.--7. 1. "Reserved,These bits are read as 0000. The write value should be 0000." bitfld.long 0x4 3. "PSGTRGBF,GTETRGB Pin Falling Input Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." newline bitfld.long 0x4 2. "PSGTRGBR,GTETRGB Pin Rising Input Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." bitfld.long 0x4 1. "PSGTRGAF,GTETRGA Pin Falling Input Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." newline bitfld.long 0x4 0. "PSGTRGAR,GTETRGA Pin Rising Input Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." line.long 0x8 "GTCSR,General PWM Timer Clear Source Select Register" bitfld.long 0x8 31. "CCLR,Software Source Counter Clear Enable" "0: Counter clear is disable by the GTCLR register,1: Counter clear is enable by the GTCLR register" hexmask.long.byte 0x8 24.--30. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." newline bitfld.long 0x8 23. "CSELCH,ELCH Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTH input,1: Counter clear is enable at the ELC_GPTH input" bitfld.long 0x8 22. "CSELCG,ELC_GPTG Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTG input,1: Counter clear is enable at the ELC_GPTG input" newline bitfld.long 0x8 21. "CSELCF,ELC_GPTF Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTF input,1: Counter clear is enable at the ELC_GPTF input" bitfld.long 0x8 20. "CSELCE,ELC_GPTE Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTE input,1: Counter clear is enable at the ELC_GPTE input" newline bitfld.long 0x8 19. "CSELCD,ELC_GPTD Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTD input,1: Counter clear is enable at the ELC_GPTD input" bitfld.long 0x8 18. "CSELCC,ELC_GPTC Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTC input,1: Counter clear is enable at the ELC_GPTC input" newline bitfld.long 0x8 17. "CSELCB,ELC_GPTB Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTB input,1: Counter clear is enable at the ELC_GPTB input" bitfld.long 0x8 16. "CSELCA,ELC_GPTA Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTA input,1: Counter clear is enable at the ELC_GPTA input" newline bitfld.long 0x8 15. "CSCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." bitfld.long 0x8 14. "CSCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." newline bitfld.long 0x8 13. "CSCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." bitfld.long 0x8 12. "CSCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." newline bitfld.long 0x8 11. "CSCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." bitfld.long 0x8 10. "CSCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." newline bitfld.long 0x8 9. "CSCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." bitfld.long 0x8 8. "CSCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." newline hexmask.long.byte 0x8 4.--7. 1. "Reserved,These bits are read as 0000. The write value should be 0000." bitfld.long 0x8 3. "CSGTRGBF,GTETRGB Pin Falling Input Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." newline bitfld.long 0x8 2. "CSGTRGBR,GTETRGB Pin Rising Input Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." bitfld.long 0x8 1. "CSGTRGAF,GTETRGA Pin Falling Input Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." newline bitfld.long 0x8 0. "CSGTRGAR,GTETRGA Pin Rising Input Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." line.long 0xC "GTUPSR,General PWM Timer Up Count Source Select Register" bitfld.long 0xC 23. "USELCH,ELCH Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTH input,1: Counter count up is enable at the ELC_GPTH input" bitfld.long 0xC 22. "USELCG,ELC_GPTG Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTG input,1: Counter count up is enable at the ELC_GPTG input" newline bitfld.long 0xC 21. "USELCF,ELC_GPTF Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTF input,1: Counter count up is enable at the ELC_GPTF input" bitfld.long 0xC 20. "USELCE,ELC_GPTE Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTE input,1: Counter count up is enable at the ELC_GPTE input" newline bitfld.long 0xC 19. "USELCD,ELC_GPTD Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTD input,1: Counter count up is enable at the ELC_GPTD input" bitfld.long 0xC 18. "USELCC,ELC_GPTC Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTC input,1: Counter count up is enable at the ELC_GPTC input" newline bitfld.long 0xC 17. "USELCB,ELC_GPTB Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTB input,1: Counter count up is enable at the ELC_GPTB input" bitfld.long 0xC 16. "USELCA,ELC_GPTA Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTA input,1: Counter count up is enable at the ELC_GPTA input" newline bitfld.long 0xC 15. "USCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." bitfld.long 0xC 14. "USCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." newline bitfld.long 0xC 13. "USCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." bitfld.long 0xC 12. "USCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." newline bitfld.long 0xC 11. "USCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." bitfld.long 0xC 10. "USCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." newline bitfld.long 0xC 9. "USCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." bitfld.long 0xC 8. "USCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." newline bitfld.long 0xC 3. "USGTRGBF,GTETRGB Pin Falling Input Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." bitfld.long 0xC 2. "USGTRGBR,GTETRGB Pin Rising Input Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." newline bitfld.long 0xC 1. "USGTRGAF,GTETRGA Pin Falling Input Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." bitfld.long 0xC 0. "USGTRGAR,GTETRGA Pin Rising Input Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." line.long 0x10 "GTDNSR,General PWM Timer Down Count Source Select Register" bitfld.long 0x10 23. "DSELCH,ELCH Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTH..,1: Counter count down is enable at the ELC_GPTH input" bitfld.long 0x10 22. "DSELCG,ELC_GPTG Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTG..,1: Counter count down is enable at the ELC_GPTG input" newline bitfld.long 0x10 21. "DSELCF,ELC_GPTF Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTF..,1: Counter count down is enable at the ELC_GPTF input" bitfld.long 0x10 20. "DSELCE,ELC_GPTE Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTE..,1: Counter count down is enable at the ELC_GPTE input" newline bitfld.long 0x10 19. "DSELCD,ELC_GPTD Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTD..,1: Counter count down is enable at the ELC_GPTD input" bitfld.long 0x10 18. "DSELCC,ELC_GPTC Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTC..,1: Counter count down is enable at the ELC_GPTC input" newline bitfld.long 0x10 17. "DSELCB,ELC_GPTB Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTB..,1: Counter count down is enable at the ELC_GPTB input" bitfld.long 0x10 16. "DSELCA,ELC_GPTA Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTA..,1: Counter count down is enable at the ELC_GPTA input" newline bitfld.long 0x10 15. "DSCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." bitfld.long 0x10 14. "DSCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." newline bitfld.long 0x10 13. "DSCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." bitfld.long 0x10 12. "DSCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." newline bitfld.long 0x10 11. "DSCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." bitfld.long 0x10 10. "DSCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." newline bitfld.long 0x10 9. "DSCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." bitfld.long 0x10 8. "DSCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." newline bitfld.long 0x10 3. "DSGTRGBF,GTETRGB Pin Falling Input Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." bitfld.long 0x10 2. "DSGTRGBR,GTETRGB Pin Rising Input Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." newline bitfld.long 0x10 1. "DSGTRGAF,GTETRGA Pin Falling Input Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." bitfld.long 0x10 0. "DSGTRGAR,GTETRGA Pin Rising Input Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." line.long 0x14 "GTICASR,General PWM Timer Input Capture Source Select Register A" bitfld.long 0x14 23. "ASELCH,ELCH Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTH..,1: GTCCRA input capture is enable at the ELC_GPTH.." bitfld.long 0x14 22. "ASELCG,ELC_GPTG Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTG..,1: GTCCRA input capture is enable at the ELC_GPTG.." newline bitfld.long 0x14 21. "ASELCF,ELC_GPTF Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTF..,1: GTCCRA input capture is enable at the ELC_GPTF.." bitfld.long 0x14 20. "ASELCE,ELC_GPTE Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTE..,1: GTCCRA input capture is enable at the ELC_GPTE.." newline bitfld.long 0x14 19. "ASELCD,ELC_GPTD Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTD..,1: GTCCRA input capture is enable at the ELC_GPTD.." bitfld.long 0x14 18. "ASELCC,ELC_GPTC Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTC..,1: GTCCRA input capture is enable at the ELC_GPTC.." newline bitfld.long 0x14 17. "ASELCB,ELC_GPTB Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTB..,1: GTCCRA input capture is enable at the ELC_GPTB.." bitfld.long 0x14 16. "ASELCA,ELC_GPTA Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTA..,1: GTCCRA input capture is enable at the ELC_GPTA.." newline bitfld.long 0x14 15. "ASCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." bitfld.long 0x14 14. "ASCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." newline bitfld.long 0x14 13. "ASCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." bitfld.long 0x14 12. "ASCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." newline bitfld.long 0x14 11. "ASCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." bitfld.long 0x14 10. "ASCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." newline bitfld.long 0x14 9. "ASCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." bitfld.long 0x14 8. "ASCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." newline bitfld.long 0x14 3. "ASGTRGBF,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." bitfld.long 0x14 2. "ASGTRGBR,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." newline bitfld.long 0x14 1. "ASGTRGAF,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." bitfld.long 0x14 0. "ASGTRGAR,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." line.long 0x18 "GTICBSR,General PWM Timer Input Capture Source Select Register B" bitfld.long 0x18 23. "BSELCH,ELCH Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTH..,1: GTCCRB input capture is enable at the ELC_GPTH.." bitfld.long 0x18 22. "BSELCG,ELC_GPTG Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTG..,1: GTCCRB input capture is enable at the ELC_GPTG.." newline bitfld.long 0x18 21. "BSELCF,ELC_GPTF Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTF..,1: GTCCRB input capture is enable at the ELC_GPTF.." bitfld.long 0x18 20. "BSELCE,ELC_GPTE Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTE..,1: GTCCRB input capture is enable at the ELC_GPTE.." newline bitfld.long 0x18 19. "BSELCD,ELC_GPTD Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTD..,1: GTCCRB input capture is enable at the ELC_GPTD.." bitfld.long 0x18 18. "BSELCC,ELC_GPTC Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTC..,1: GTCCRB input capture is enable at the ELC_GPTC.." newline bitfld.long 0x18 17. "BSELCB,ELC_GPTB Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTB..,1: GTCCRB input capture is enable at the ELC_GPTB.." bitfld.long 0x18 16. "BSELCA,ELC_GPTA Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTA..,1: GTCCRB input capture is enable at the ELC_GPTA.." newline bitfld.long 0x18 15. "BSCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." bitfld.long 0x18 14. "BSCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." newline bitfld.long 0x18 13. "BSCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." bitfld.long 0x18 12. "BSCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." newline bitfld.long 0x18 11. "BSCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." bitfld.long 0x18 10. "BSCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." newline bitfld.long 0x18 9. "BSCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." bitfld.long 0x18 8. "BSCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." newline bitfld.long 0x18 3. "BSGTRGBF,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." bitfld.long 0x18 2. "BSGTRGBR,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." newline bitfld.long 0x18 1. "BSGTRGAF,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." bitfld.long 0x18 0. "BSGTRGAR,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." line.long 0x1C "GTCR,General PWM Timer Control Register" bitfld.long 0x1C 24.--26. "TPCS,Timer Prescaler Select" "0: Setting prohibied,1: PCLK/4,?,?,?,?,?,?" hexmask.long.byte 0x1C 19.--23. 1. "Reserved,These bits are read as 00000. The write value should be 00000." newline bitfld.long 0x1C 16.--18. "MD,Mode Select" "0: Saw-wave PWM mode (single buffer or double..,1: Saw-wave one-shot pulse mode (fixed buffer..,?,?,?,?,?,?" hexmask.long.word 0x1C 1.--15. 1. "Reserved,These bits are read as 000000000000000. The write value should be 000000000000000." newline bitfld.long 0x1C 0. "CST,Count Start" "0: Count operation is stopped,1: Count operation is performed" line.long 0x20 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register" bitfld.long 0x20 27. "OBDTYR,GTIOCB Output Value Selecting after Releasing 0 percent/100 percent Duty Setting" "0: Apply output value set in 0 percent/100 percent..,1: Apply masked compare match output value to.." bitfld.long 0x20 26. "OBDTYF,Forcible GTIOCB Output Duty Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x20 24.--25. "OBDTY,GTIOCB Output Duty Setting" "0: GTIOCB pin duty is depend on compare match,1: GTIOCB pin duty is depend on compare match,?,?" hexmask.long.byte 0x20 20.--23. 1. "Reserved,These bits are read as 0000. The write value should be 0000." newline bitfld.long 0x20 19. "OADTYR,GTIOCA Output Value Selecting after Releasing 0 percent/100 percent Duty Setting" "0: Apply output value set in 0 percent/100 percent..,1: Apply masked compare match output value to.." bitfld.long 0x20 18. "OADTYF,Forcible GTIOCA Output Duty Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x20 16.--17. "OADTY,GTIOCA Output Duty Setting" "0: GTIOCA pin duty is depend on compare match,1: GTIOCA pin duty is depend on compare match,?,?" bitfld.long 0x20 1. "UDF,Forcible Count Direction Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x20 0. "UD,Count Direction Setting" "0: GTCNT counts down.,1: GTCNT counts up." line.long 0x24 "GTIOR,General PWM Timer I/O Control Register" bitfld.long 0x24 30.--31. "NFCSB,Noise Filter B Sampling Clock Select" "0: PCLK/1,1: PCLK/4,?,?" bitfld.long 0x24 29. "NFBEN,Noise Filter B Enable" "0: The noise filter for the GTIOCB pin is disabled.,1: The noise filter for the GTIOCB pin is enabled." newline bitfld.long 0x24 27.--28. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.long 0x24 25.--26. "OBDF,GTIOCB Pin Disable Value Setting" "0: Output disable is prohibited.,1: GTIOCB pin is set to Hi-Z when output disable is..,?,?" newline bitfld.long 0x24 24. "OBE,GTIOCB Pin Output Enable" "0: Output is disabled,1: Output is enabled" bitfld.long 0x24 23. "OBHLD,GTIOCB Pin Output Setting at the Start/Stop Count" "0: The GTIOCB pin output level at start/stop of..,1: The GTIOCB pin output level is retained at.." newline bitfld.long 0x24 22. "OBDFLT,GTIOCB Pin Output Value Setting at the Count Stop" "0: The GTIOCB pin outputs low when counting is..,1: The GTIOCB pin outputs high when counting is.." bitfld.long 0x24 21. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline hexmask.long.byte 0x24 16.--20. 1. "GTIOB,GTIOCB Pin Function Select" bitfld.long 0x24 14.--15. "NFCSA,Noise Filter A Sampling Clock Select" "0: PCLK/1,1: PCLK/4,?,?" newline bitfld.long 0x24 13. "NFAEN,Noise Filter A Enable" "0: The noise filter for the GTIOCA pin is disabled.,1: The noise filter for the GTIOCA pin is enabled." bitfld.long 0x24 11.--12. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" newline bitfld.long 0x24 9.--10. "OADF,GTIOCA Pin Disable Value Setting" "0: Output disable is prohibited.,1: GTIOCA pin is set to Hi-Z when output disable is..,?,?" bitfld.long 0x24 8. "OAE,GTIOCA Pin Output Enable" "0: Output is disabled,1: Output is enabled" newline bitfld.long 0x24 7. "OAHLD,GTIOCA Pin Output Setting at the Start/Stop Count" "0: The GTIOCA pin output level at start/stop of..,1: The GTIOCA pin output level is retained at.." bitfld.long 0x24 6. "OADFLT,GTIOCA Pin Output Value Setting at the Count Stop" "0: The GTIOCA pin outputs low when counting is..,1: The GTIOCA pin outputs high when counting is.." newline bitfld.long 0x24 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" hexmask.long.byte 0x24 0.--4. 1. "GTIOA,GTIOCA Pin Function Select" line.long 0x28 "GTINTAD,General PWM Timer Interrupt Output Setting Register" bitfld.long 0x28 30. "GRPABL,Same Time Output Level Low Disable Request Enable" "0: Same time output level low disable request is..,1: Same time output level low disable request is.." bitfld.long 0x28 29. "GRPABH,Same Time Output Level High Disable Request Enable" "0: Same time output level high disable request is..,1: Same time output level high disable request is.." newline bitfld.long 0x28 26.--28. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.long 0x28 24.--25. "GRP,Output Disable Source Select" "0: Setting prohibited,1: Group B output disable request,?,?" newline hexmask.long.tbyte 0x28 0.--23. 1. "Reserved,These bits are read as 000000000000000000000000. The write value should be 000000000000000000000000." line.long 0x2C "GTST,General PWM Timer Status Register" rbitfld.long 0x2C 30. "OABLF,Same Time Output Level Low Disable Request Enable" "0: GTIOCA pin and GTIOCB pin don't output 0 at the..,1: GTIOCA pin and GTIOCB pin output 0 at the same.." rbitfld.long 0x2C 29. "OABHF,Same Time Output Level High Disable Request Enable" "0: GTIOCA pin and GTIOCB pin don't output 1 at the..,1: GTIOCA pin and GTIOCB pin output 1 at the same.." newline hexmask.long.byte 0x2C 25.--28. 1. "Reserved,These bits are read as 0000. The write value should be 0000." rbitfld.long 0x2C 24. "ODF,Output Disable Flag" "0: No output disable request is generated.,1: An output disable request is generated." newline hexmask.long.byte 0x2C 16.--23. 1. "Reserved,These bits are read as 00000000. The write value should be 00000000." rbitfld.long 0x2C 15. "TUCF,Count Direction Flag" "0: The GTCNT counter counts downward.,1: The GTCNT counter counts upward." newline hexmask.long.byte 0x2C 8.--14. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.long 0x2C 7. "TCFPU,Underflow Flag" "0: No underflow (trough) has occurred.,1: An underflow (trough) has occurred." newline bitfld.long 0x2C 6. "TCPFO,Overflow Flag" "0: No overflow (crest) has occurred.,1: An overflow (crest) has occurred." bitfld.long 0x2C 5. "TCFF,Input Compare Match Flag F" "0: No compare match of GTCCRF is generated.,1: A compare match of GTCCRF is generated." newline bitfld.long 0x2C 4. "TCFE,Input Compare Match Flag E" "0: No compare match of GTCCRE is generated.,1: A compare match of GTCCRE is generated." bitfld.long 0x2C 3. "TCFD,Input Compare Match Flag D" "0: No compare match of GTCCRD is generated.,1: A compare match of GTCCRD is generated." newline bitfld.long 0x2C 2. "TCFC,Input Compare Match Flag C" "0: No compare match of GTCCRC is generated.,1: A compare match of GTCCRC is generated." bitfld.long 0x2C 1. "TCFB,Input Capture/Compare Match Flag B" "0: No input capture/compare match of GTCCRB is..,1: An input capture/compare match of GTCCRB is.." newline bitfld.long 0x2C 0. "TCFA,Input Capture/Compare Match Flag A" "0: No input capture/compare match of GTCCRA is..,1: An input capture/compare match of GTCCRA is.." line.long 0x30 "GTBER,General PWM Timer Buffer Enable Register" bitfld.long 0x30 22. "CCRSWT,GTCCRA and GTCCRB Forcible Buffer OperationThis bit is read as 0." "0: no effect,1: Forcibly performs buffer transfer of GTCCRA and.." bitfld.long 0x30 20.--21. "PR,GTPR Buffer Operation" "0: Setting prohibited,1: Single buffer operation (GTPBR --> GTPR),?,?" newline bitfld.long 0x30 18.--19. "CCRB,GTCCRB Buffer Operation" "0: Buffer operation is not performed,1: Single buffer operation (GTCCRB <--> GTCCRE),?,?" bitfld.long 0x30 16.--17. "CCRA,GTCCRA Buffer Operation" "0: Buffer operation is not performed,1: Single buffer operation (GTCCRA <--> GTCCRC),?,?" newline bitfld.long 0x30 0.--1. "BD,BD[1]: GTPR Buffer Operation DisableBD[0]: GTCCR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled,?,?" group.long 0x48++0x23 line.long 0x0 "GTCNT,General PWM Timer Counter" hexmask.long 0x0 0.--31. 1. "GTCNT,Counter" line.long 0x4 "GTCCRA,General PWM Timer Compare Capture Register A" hexmask.long 0x4 0.--31. 1. "GTCCRA,Compare Capture Register A" line.long 0x8 "GTCCRB,General PWM Timer Compare Capture Register B" hexmask.long 0x8 0.--31. 1. "GTCCRB,Compare Capture Register B" line.long 0xC "GTCCRC,General PWM Timer Compare Capture Register C" hexmask.long 0xC 0.--31. 1. "GTCCRC,Compare Capture Register C" line.long 0x10 "GTCCRE,General PWM Timer Compare Capture Register E" hexmask.long 0x10 0.--31. 1. "GTCCRE,Compare Capture Register E" line.long 0x14 "GTCCRD,General PWM Timer Compare Capture Register D" hexmask.long 0x14 0.--31. 1. "GTCCRD,Compare Capture Register D" line.long 0x18 "GTCCRF,General PWM Timer Compare Capture Register F" hexmask.long 0x18 0.--31. 1. "GTCCRF,Compare Capture Register F" line.long 0x1C "GTPR,General PWM Timer Cycle Setting Register" hexmask.long 0x1C 0.--31. 1. "GTPR,Cycle Setting Register" line.long 0x20 "GTPBR,General PWM Timer Cycle Setting Buffer Register" hexmask.long 0x20 0.--31. 1. "GTPBR,Cycle Setting Buffer Register" group.long 0x88++0x7 line.long 0x0 "GTDTCR,General PWM Timer Dead Time Control Register" hexmask.long.tbyte 0x0 9.--31. 1. "Reserved,These bits are read as 00000000000000000000000. The write value should be 00000000000000000000000." bitfld.long 0x0 8. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.long 0x0 6.--7. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.long 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.long 0x0 4. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 1.--3. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "TDE,Negative-Phase Waveform Setting" "0: GTCCRB is set without using GTDVU and GTDVD.,1: GTDVU and GTDVD are used to set the compare.." line.long 0x4 "GTDVU,General PWM Timer Dead Time Value Register U" hexmask.long 0x4 0.--31. 1. "GTDVU,Dead Time Value Register U" tree.end tree "GPT321" base ad:0x40078100 group.long 0x0++0xB line.long 0x0 "GTWP,General PWM Timer Write-Protection Register" hexmask.long.word 0x0 16.--31. 1. "Reserved,These bits are read as 0000000000000000. The write value should be 0000000000000000." hexmask.long.byte 0x0 8.--15. 1. "PRKEY,GTWP Key Code" newline hexmask.long.byte 0x0 1.--7. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.long 0x0 0. "WP,Register Write Disable" "0: Write to the register is enabled,1: Write to the register is disabled" line.long 0x4 "GTSTR,General PWM Timer Software Start Register" hexmask.long.tbyte 0x4 10.--31. 1. "Reserved,These bits are read as 0000000000000000000000. The write value should be 0000000000000000000000." bitfld.long 0x4 9. "CSTRT9,Channel 9 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT169.GTCNT counter starts (write) / Counter.." newline bitfld.long 0x4 8. "CSTRT8,Channel 8 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT168.GTCNT counter starts (write) / Counter.." bitfld.long 0x4 7. "CSTRT7,Channel 7 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT167.GTCNT counter starts (write) / Counter.." newline bitfld.long 0x4 6. "CSTRT6,Channel 6 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT166.GTCNT counter starts (write) / Counter.." bitfld.long 0x4 5. "CSTRT5,Channel 5 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT165.GTCNT counter starts (write) / Counter.." newline bitfld.long 0x4 4. "CSTRT4,Channel 4 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT164.GTCNT counter starts (write) / Counter.." bitfld.long 0x4 3. "CSTRT3,Channel 3 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT323.GTCNT counter starts (write) / Counter.." newline bitfld.long 0x4 2. "CSTRT2,Channel 2 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT322.GTCNT counter starts (write) / Counter.." bitfld.long 0x4 1. "CSTRT1,Channel 1 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT321.GTCNT counter starts (write) / Counter.." newline bitfld.long 0x4 0. "CSTRT0,Channel 0 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT320.GTCNT counter starts (write) / Counter.." line.long 0x8 "GTSTP,General PWM Timer Software Stop Register" hexmask.long.tbyte 0x8 10.--31. 1. "Reserved,These bits are read as 1111111111111111111111. The write value should be 1111111111111111111111." bitfld.long 0x8 9. "CSTOP9,Channel 9 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT169.GTCNT counter stops (write) / Counter.." newline bitfld.long 0x8 8. "CSTOP8,Channel 8 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT168.GTCNT counter stops (write) / Counter.." bitfld.long 0x8 7. "CSTOP7,Channel 7 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT167.GTCNT counter stops (write) / Counter.." newline bitfld.long 0x8 6. "CSTOP6,Channel 6 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT166.GTCNT counter stops (write) / Counter.." bitfld.long 0x8 5. "CSTOP5,Channel 5 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT165.GTCNT counter stops (write) / Counter.." newline bitfld.long 0x8 4. "CSTOP4,Channel 4 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT164.GTCNT counter stops (write) / Counter.." bitfld.long 0x8 3. "CSTOP3,Channel 3 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT323.GTCNT counter stops (write) / Counter.." newline bitfld.long 0x8 2. "CSTOP2,Channel 2 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT322.GTCNT counter stops (write) / Counter.." bitfld.long 0x8 1. "CSTOP1,Channel 1 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT321.GTCNT counter stops (write) / Counter.." newline bitfld.long 0x8 0. "CSTOP0,Channel 0 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT320.GTCNT counter stops (write) / Counter.." wgroup.long 0xC++0x3 line.long 0x0 "GTCLR,General PWM Timer Software Clear Register" hexmask.long.tbyte 0x0 10.--31. 1. "Reserved,The write value should be 0000000000000000000000." bitfld.long 0x0 9. "CCLR9,Channel 9 GTCNT Count Clear" "0: No effect,1: GPT169.GTCNT counter clears" newline bitfld.long 0x0 8. "CCLR8,Channel 8 GTCNT Count Clear" "0: No effect,1: GPT168.GTCNT counter clears" bitfld.long 0x0 7. "CCLR7,Channel 7 GTCNT Count Clear" "0: No effect,1: GPT167.GTCNT counter clears" newline bitfld.long 0x0 6. "CCLR6,Channel 6 GTCNT Count Clear" "0: No effect,1: GPT166.GTCNT counter clears" bitfld.long 0x0 5. "CCLR5,Channel 5 GTCNT Count Clear" "0: No effect,1: GPT165.GTCNT counter clears" newline bitfld.long 0x0 4. "CCLR4,Channel 4 GTCNT Count Clear" "0: No effect,1: GPT164.GTCNT counter clears" bitfld.long 0x0 3. "CCLR3,Channel 3 GTCNT Count Clear" "0: No effect,1: GPT323.GTCNT counter clears" newline bitfld.long 0x0 2. "CCLR2,Channel 2 GTCNT Count Clear" "0: No effect,1: GPT322.GTCNT counter clears" bitfld.long 0x0 1. "CCLR1,Channel 1 GTCNT Count Clear" "0: No effect,1: GPT321.GTCNT counter clears" newline bitfld.long 0x0 0. "CCLR0,Channel 0 GTCNT Count Clear" "0: No effect,1: GPT320.GTCNT counter clears" group.long 0x10++0x33 line.long 0x0 "GTSSR,General PWM Timer Start Source Select Register" bitfld.long 0x0 31. "CSTRT,Software Source Counter Start Enable" "0: Counter start is disable by the GTSTR register,1: Counter start is enable by the GTSTR register" hexmask.long.byte 0x0 24.--30. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." newline bitfld.long 0x0 23. "SSELCH,ELCH Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTH input,1: Counter start is enable at the ELC_GPTH input" bitfld.long 0x0 22. "SSELCG,ELC_GPTG Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTG input,1: Counter start is enable at the ELC_GPTG input" newline bitfld.long 0x0 21. "SSELCF,ELC_GPTF Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTF input,1: Counter start is enable at the ELC_GPTF input" bitfld.long 0x0 20. "SSELCE,ELC_GPTE Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTE input,1: Counter start is enable at the ELC_GPTE input" newline bitfld.long 0x0 19. "SSELCD,ELC_GPTD Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTD input,1: Counter start is enable at the ELC_GPTD input" bitfld.long 0x0 18. "SSELCC,ELC_GPTC Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTC input,1: Counter start is enable at the ELC_GPTC input" newline bitfld.long 0x0 17. "SSELCB,ELC_GPTB Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTB input,1: Counter start is enable at the ELC_GPTB input" bitfld.long 0x0 16. "SSELCA,ELC_GPTA Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTA input,1: Counter start is enable at the ELC_GPTA input" newline bitfld.long 0x0 15. "SSCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." bitfld.long 0x0 14. "SSCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." newline bitfld.long 0x0 13. "SSCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." bitfld.long 0x0 12. "SSCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." newline bitfld.long 0x0 11. "SSCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." bitfld.long 0x0 10. "SSCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." newline bitfld.long 0x0 9. "SSCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." bitfld.long 0x0 8. "SSCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." newline hexmask.long.byte 0x0 4.--7. 1. "Reserved,These bits are read as 0000. The write value should be 0000." bitfld.long 0x0 3. "SSGTRGBF,GTETRGB Pin Falling Input Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." newline bitfld.long 0x0 2. "SSGTRGBR,GTETRGB Pin Rising Input Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." bitfld.long 0x0 1. "SSGTRGAF,GTETRGA Pin Falling Input Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." newline bitfld.long 0x0 0. "SSGTRGAR,GTETRGA Pin Rising Input Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." line.long 0x4 "GTPSR,General PWM Timer Stop Source Select Register" bitfld.long 0x4 31. "CSTOP,Software Source Counter Stop Enable" "0: Counter stop is disable by the GTSTP register,1: Counter stop is enable by the GTSTP register" hexmask.long.byte 0x4 24.--30. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." newline bitfld.long 0x4 23. "PSELCH,ELCH Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTH input,1: Counter stop is enable at the ELC_GPTH input" bitfld.long 0x4 22. "PSELCG,ELC_GPTG Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTG input,1: Counter stop is enable at the ELC_GPTG input" newline bitfld.long 0x4 21. "PSELCF,ELC_GPTF Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTF input,1: Counter stop is enable at the ELC_GPTF input" bitfld.long 0x4 20. "PSELCE,ELC_GPTE Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTE input,1: Counter stop is enable at the ELC_GPTE input" newline bitfld.long 0x4 19. "PSELCD,ELC_GPTD Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTD input,1: Counter stop is enable at the ELC_GPTD input" bitfld.long 0x4 18. "PSELCC,ELC_GPTC Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTC input,1: Counter stop is enable at the ELC_GPTC input" newline bitfld.long 0x4 17. "PSELCB,ELC_GPTB Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTB input,1: Counter stop is enable at the ELC_GPTB input" bitfld.long 0x4 16. "PSELCA,ELC_GPTA Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTA input,1: Counter stop is enable at the ELC_GPTA input" newline bitfld.long 0x4 15. "PSCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." bitfld.long 0x4 14. "PSCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." newline bitfld.long 0x4 13. "PSCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." bitfld.long 0x4 12. "PSCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." newline bitfld.long 0x4 11. "PSCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." bitfld.long 0x4 10. "PSCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." newline bitfld.long 0x4 9. "PSCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." bitfld.long 0x4 8. "PSCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." newline hexmask.long.byte 0x4 4.--7. 1. "Reserved,These bits are read as 0000. The write value should be 0000." bitfld.long 0x4 3. "PSGTRGBF,GTETRGB Pin Falling Input Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." newline bitfld.long 0x4 2. "PSGTRGBR,GTETRGB Pin Rising Input Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." bitfld.long 0x4 1. "PSGTRGAF,GTETRGA Pin Falling Input Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." newline bitfld.long 0x4 0. "PSGTRGAR,GTETRGA Pin Rising Input Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." line.long 0x8 "GTCSR,General PWM Timer Clear Source Select Register" bitfld.long 0x8 31. "CCLR,Software Source Counter Clear Enable" "0: Counter clear is disable by the GTCLR register,1: Counter clear is enable by the GTCLR register" hexmask.long.byte 0x8 24.--30. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." newline bitfld.long 0x8 23. "CSELCH,ELCH Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTH input,1: Counter clear is enable at the ELC_GPTH input" bitfld.long 0x8 22. "CSELCG,ELC_GPTG Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTG input,1: Counter clear is enable at the ELC_GPTG input" newline bitfld.long 0x8 21. "CSELCF,ELC_GPTF Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTF input,1: Counter clear is enable at the ELC_GPTF input" bitfld.long 0x8 20. "CSELCE,ELC_GPTE Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTE input,1: Counter clear is enable at the ELC_GPTE input" newline bitfld.long 0x8 19. "CSELCD,ELC_GPTD Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTD input,1: Counter clear is enable at the ELC_GPTD input" bitfld.long 0x8 18. "CSELCC,ELC_GPTC Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTC input,1: Counter clear is enable at the ELC_GPTC input" newline bitfld.long 0x8 17. "CSELCB,ELC_GPTB Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTB input,1: Counter clear is enable at the ELC_GPTB input" bitfld.long 0x8 16. "CSELCA,ELC_GPTA Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTA input,1: Counter clear is enable at the ELC_GPTA input" newline bitfld.long 0x8 15. "CSCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." bitfld.long 0x8 14. "CSCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." newline bitfld.long 0x8 13. "CSCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." bitfld.long 0x8 12. "CSCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." newline bitfld.long 0x8 11. "CSCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." bitfld.long 0x8 10. "CSCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." newline bitfld.long 0x8 9. "CSCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." bitfld.long 0x8 8. "CSCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." newline hexmask.long.byte 0x8 4.--7. 1. "Reserved,These bits are read as 0000. The write value should be 0000." bitfld.long 0x8 3. "CSGTRGBF,GTETRGB Pin Falling Input Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." newline bitfld.long 0x8 2. "CSGTRGBR,GTETRGB Pin Rising Input Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." bitfld.long 0x8 1. "CSGTRGAF,GTETRGA Pin Falling Input Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." newline bitfld.long 0x8 0. "CSGTRGAR,GTETRGA Pin Rising Input Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." line.long 0xC "GTUPSR,General PWM Timer Up Count Source Select Register" bitfld.long 0xC 23. "USELCH,ELCH Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTH input,1: Counter count up is enable at the ELC_GPTH input" bitfld.long 0xC 22. "USELCG,ELC_GPTG Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTG input,1: Counter count up is enable at the ELC_GPTG input" newline bitfld.long 0xC 21. "USELCF,ELC_GPTF Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTF input,1: Counter count up is enable at the ELC_GPTF input" bitfld.long 0xC 20. "USELCE,ELC_GPTE Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTE input,1: Counter count up is enable at the ELC_GPTE input" newline bitfld.long 0xC 19. "USELCD,ELC_GPTD Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTD input,1: Counter count up is enable at the ELC_GPTD input" bitfld.long 0xC 18. "USELCC,ELC_GPTC Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTC input,1: Counter count up is enable at the ELC_GPTC input" newline bitfld.long 0xC 17. "USELCB,ELC_GPTB Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTB input,1: Counter count up is enable at the ELC_GPTB input" bitfld.long 0xC 16. "USELCA,ELC_GPTA Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTA input,1: Counter count up is enable at the ELC_GPTA input" newline bitfld.long 0xC 15. "USCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." bitfld.long 0xC 14. "USCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." newline bitfld.long 0xC 13. "USCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." bitfld.long 0xC 12. "USCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." newline bitfld.long 0xC 11. "USCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." bitfld.long 0xC 10. "USCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." newline bitfld.long 0xC 9. "USCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." bitfld.long 0xC 8. "USCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." newline bitfld.long 0xC 3. "USGTRGBF,GTETRGB Pin Falling Input Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." bitfld.long 0xC 2. "USGTRGBR,GTETRGB Pin Rising Input Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." newline bitfld.long 0xC 1. "USGTRGAF,GTETRGA Pin Falling Input Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." bitfld.long 0xC 0. "USGTRGAR,GTETRGA Pin Rising Input Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." line.long 0x10 "GTDNSR,General PWM Timer Down Count Source Select Register" bitfld.long 0x10 23. "DSELCH,ELCH Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTH..,1: Counter count down is enable at the ELC_GPTH input" bitfld.long 0x10 22. "DSELCG,ELC_GPTG Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTG..,1: Counter count down is enable at the ELC_GPTG input" newline bitfld.long 0x10 21. "DSELCF,ELC_GPTF Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTF..,1: Counter count down is enable at the ELC_GPTF input" bitfld.long 0x10 20. "DSELCE,ELC_GPTE Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTE..,1: Counter count down is enable at the ELC_GPTE input" newline bitfld.long 0x10 19. "DSELCD,ELC_GPTD Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTD..,1: Counter count down is enable at the ELC_GPTD input" bitfld.long 0x10 18. "DSELCC,ELC_GPTC Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTC..,1: Counter count down is enable at the ELC_GPTC input" newline bitfld.long 0x10 17. "DSELCB,ELC_GPTB Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTB..,1: Counter count down is enable at the ELC_GPTB input" bitfld.long 0x10 16. "DSELCA,ELC_GPTA Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTA..,1: Counter count down is enable at the ELC_GPTA input" newline bitfld.long 0x10 15. "DSCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." bitfld.long 0x10 14. "DSCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." newline bitfld.long 0x10 13. "DSCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." bitfld.long 0x10 12. "DSCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." newline bitfld.long 0x10 11. "DSCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." bitfld.long 0x10 10. "DSCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." newline bitfld.long 0x10 9. "DSCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." bitfld.long 0x10 8. "DSCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." newline bitfld.long 0x10 3. "DSGTRGBF,GTETRGB Pin Falling Input Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." bitfld.long 0x10 2. "DSGTRGBR,GTETRGB Pin Rising Input Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." newline bitfld.long 0x10 1. "DSGTRGAF,GTETRGA Pin Falling Input Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." bitfld.long 0x10 0. "DSGTRGAR,GTETRGA Pin Rising Input Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." line.long 0x14 "GTICASR,General PWM Timer Input Capture Source Select Register A" bitfld.long 0x14 23. "ASELCH,ELCH Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTH..,1: GTCCRA input capture is enable at the ELC_GPTH.." bitfld.long 0x14 22. "ASELCG,ELC_GPTG Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTG..,1: GTCCRA input capture is enable at the ELC_GPTG.." newline bitfld.long 0x14 21. "ASELCF,ELC_GPTF Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTF..,1: GTCCRA input capture is enable at the ELC_GPTF.." bitfld.long 0x14 20. "ASELCE,ELC_GPTE Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTE..,1: GTCCRA input capture is enable at the ELC_GPTE.." newline bitfld.long 0x14 19. "ASELCD,ELC_GPTD Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTD..,1: GTCCRA input capture is enable at the ELC_GPTD.." bitfld.long 0x14 18. "ASELCC,ELC_GPTC Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTC..,1: GTCCRA input capture is enable at the ELC_GPTC.." newline bitfld.long 0x14 17. "ASELCB,ELC_GPTB Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTB..,1: GTCCRA input capture is enable at the ELC_GPTB.." bitfld.long 0x14 16. "ASELCA,ELC_GPTA Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTA..,1: GTCCRA input capture is enable at the ELC_GPTA.." newline bitfld.long 0x14 15. "ASCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." bitfld.long 0x14 14. "ASCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." newline bitfld.long 0x14 13. "ASCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." bitfld.long 0x14 12. "ASCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." newline bitfld.long 0x14 11. "ASCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." bitfld.long 0x14 10. "ASCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." newline bitfld.long 0x14 9. "ASCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." bitfld.long 0x14 8. "ASCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." newline bitfld.long 0x14 3. "ASGTRGBF,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." bitfld.long 0x14 2. "ASGTRGBR,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." newline bitfld.long 0x14 1. "ASGTRGAF,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." bitfld.long 0x14 0. "ASGTRGAR,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." line.long 0x18 "GTICBSR,General PWM Timer Input Capture Source Select Register B" bitfld.long 0x18 23. "BSELCH,ELCH Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTH..,1: GTCCRB input capture is enable at the ELC_GPTH.." bitfld.long 0x18 22. "BSELCG,ELC_GPTG Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTG..,1: GTCCRB input capture is enable at the ELC_GPTG.." newline bitfld.long 0x18 21. "BSELCF,ELC_GPTF Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTF..,1: GTCCRB input capture is enable at the ELC_GPTF.." bitfld.long 0x18 20. "BSELCE,ELC_GPTE Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTE..,1: GTCCRB input capture is enable at the ELC_GPTE.." newline bitfld.long 0x18 19. "BSELCD,ELC_GPTD Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTD..,1: GTCCRB input capture is enable at the ELC_GPTD.." bitfld.long 0x18 18. "BSELCC,ELC_GPTC Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTC..,1: GTCCRB input capture is enable at the ELC_GPTC.." newline bitfld.long 0x18 17. "BSELCB,ELC_GPTB Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTB..,1: GTCCRB input capture is enable at the ELC_GPTB.." bitfld.long 0x18 16. "BSELCA,ELC_GPTA Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTA..,1: GTCCRB input capture is enable at the ELC_GPTA.." newline bitfld.long 0x18 15. "BSCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." bitfld.long 0x18 14. "BSCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." newline bitfld.long 0x18 13. "BSCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." bitfld.long 0x18 12. "BSCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." newline bitfld.long 0x18 11. "BSCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." bitfld.long 0x18 10. "BSCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." newline bitfld.long 0x18 9. "BSCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." bitfld.long 0x18 8. "BSCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." newline bitfld.long 0x18 3. "BSGTRGBF,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." bitfld.long 0x18 2. "BSGTRGBR,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." newline bitfld.long 0x18 1. "BSGTRGAF,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." bitfld.long 0x18 0. "BSGTRGAR,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." line.long 0x1C "GTCR,General PWM Timer Control Register" bitfld.long 0x1C 24.--26. "TPCS,Timer Prescaler Select" "0: Setting prohibied,1: PCLK/4,?,?,?,?,?,?" hexmask.long.byte 0x1C 19.--23. 1. "Reserved,These bits are read as 00000. The write value should be 00000." newline bitfld.long 0x1C 16.--18. "MD,Mode Select" "0: Saw-wave PWM mode (single buffer or double..,1: Saw-wave one-shot pulse mode (fixed buffer..,?,?,?,?,?,?" hexmask.long.word 0x1C 1.--15. 1. "Reserved,These bits are read as 000000000000000. The write value should be 000000000000000." newline bitfld.long 0x1C 0. "CST,Count Start" "0: Count operation is stopped,1: Count operation is performed" line.long 0x20 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register" bitfld.long 0x20 27. "OBDTYR,GTIOCB Output Value Selecting after Releasing 0 percent/100 percent Duty Setting" "0: Apply output value set in 0 percent/100 percent..,1: Apply masked compare match output value to.." bitfld.long 0x20 26. "OBDTYF,Forcible GTIOCB Output Duty Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x20 24.--25. "OBDTY,GTIOCB Output Duty Setting" "0: GTIOCB pin duty is depend on compare match,1: GTIOCB pin duty is depend on compare match,?,?" hexmask.long.byte 0x20 20.--23. 1. "Reserved,These bits are read as 0000. The write value should be 0000." newline bitfld.long 0x20 19. "OADTYR,GTIOCA Output Value Selecting after Releasing 0 percent/100 percent Duty Setting" "0: Apply output value set in 0 percent/100 percent..,1: Apply masked compare match output value to.." bitfld.long 0x20 18. "OADTYF,Forcible GTIOCA Output Duty Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x20 16.--17. "OADTY,GTIOCA Output Duty Setting" "0: GTIOCA pin duty is depend on compare match,1: GTIOCA pin duty is depend on compare match,?,?" bitfld.long 0x20 1. "UDF,Forcible Count Direction Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x20 0. "UD,Count Direction Setting" "0: GTCNT counts down.,1: GTCNT counts up." line.long 0x24 "GTIOR,General PWM Timer I/O Control Register" bitfld.long 0x24 30.--31. "NFCSB,Noise Filter B Sampling Clock Select" "0: PCLK/1,1: PCLK/4,?,?" bitfld.long 0x24 29. "NFBEN,Noise Filter B Enable" "0: The noise filter for the GTIOCB pin is disabled.,1: The noise filter for the GTIOCB pin is enabled." newline bitfld.long 0x24 27.--28. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.long 0x24 25.--26. "OBDF,GTIOCB Pin Disable Value Setting" "0: Output disable is prohibited.,1: GTIOCB pin is set to Hi-Z when output disable is..,?,?" newline bitfld.long 0x24 24. "OBE,GTIOCB Pin Output Enable" "0: Output is disabled,1: Output is enabled" bitfld.long 0x24 23. "OBHLD,GTIOCB Pin Output Setting at the Start/Stop Count" "0: The GTIOCB pin output level at start/stop of..,1: The GTIOCB pin output level is retained at.." newline bitfld.long 0x24 22. "OBDFLT,GTIOCB Pin Output Value Setting at the Count Stop" "0: The GTIOCB pin outputs low when counting is..,1: The GTIOCB pin outputs high when counting is.." bitfld.long 0x24 21. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline hexmask.long.byte 0x24 16.--20. 1. "GTIOB,GTIOCB Pin Function Select" bitfld.long 0x24 14.--15. "NFCSA,Noise Filter A Sampling Clock Select" "0: PCLK/1,1: PCLK/4,?,?" newline bitfld.long 0x24 13. "NFAEN,Noise Filter A Enable" "0: The noise filter for the GTIOCA pin is disabled.,1: The noise filter for the GTIOCA pin is enabled." bitfld.long 0x24 11.--12. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" newline bitfld.long 0x24 9.--10. "OADF,GTIOCA Pin Disable Value Setting" "0: Output disable is prohibited.,1: GTIOCA pin is set to Hi-Z when output disable is..,?,?" bitfld.long 0x24 8. "OAE,GTIOCA Pin Output Enable" "0: Output is disabled,1: Output is enabled" newline bitfld.long 0x24 7. "OAHLD,GTIOCA Pin Output Setting at the Start/Stop Count" "0: The GTIOCA pin output level at start/stop of..,1: The GTIOCA pin output level is retained at.." bitfld.long 0x24 6. "OADFLT,GTIOCA Pin Output Value Setting at the Count Stop" "0: The GTIOCA pin outputs low when counting is..,1: The GTIOCA pin outputs high when counting is.." newline bitfld.long 0x24 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" hexmask.long.byte 0x24 0.--4. 1. "GTIOA,GTIOCA Pin Function Select" line.long 0x28 "GTINTAD,General PWM Timer Interrupt Output Setting Register" bitfld.long 0x28 30. "GRPABL,Same Time Output Level Low Disable Request Enable" "0: Same time output level low disable request is..,1: Same time output level low disable request is.." bitfld.long 0x28 29. "GRPABH,Same Time Output Level High Disable Request Enable" "0: Same time output level high disable request is..,1: Same time output level high disable request is.." newline bitfld.long 0x28 26.--28. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.long 0x28 24.--25. "GRP,Output Disable Source Select" "0: Setting prohibited,1: Group B output disable request,?,?" newline hexmask.long.tbyte 0x28 0.--23. 1. "Reserved,These bits are read as 000000000000000000000000. The write value should be 000000000000000000000000." line.long 0x2C "GTST,General PWM Timer Status Register" rbitfld.long 0x2C 30. "OABLF,Same Time Output Level Low Disable Request Enable" "0: GTIOCA pin and GTIOCB pin don't output 0 at the..,1: GTIOCA pin and GTIOCB pin output 0 at the same.." rbitfld.long 0x2C 29. "OABHF,Same Time Output Level High Disable Request Enable" "0: GTIOCA pin and GTIOCB pin don't output 1 at the..,1: GTIOCA pin and GTIOCB pin output 1 at the same.." newline hexmask.long.byte 0x2C 25.--28. 1. "Reserved,These bits are read as 0000. The write value should be 0000." rbitfld.long 0x2C 24. "ODF,Output Disable Flag" "0: No output disable request is generated.,1: An output disable request is generated." newline hexmask.long.byte 0x2C 16.--23. 1. "Reserved,These bits are read as 00000000. The write value should be 00000000." rbitfld.long 0x2C 15. "TUCF,Count Direction Flag" "0: The GTCNT counter counts downward.,1: The GTCNT counter counts upward." newline hexmask.long.byte 0x2C 8.--14. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.long 0x2C 7. "TCFPU,Underflow Flag" "0: No underflow (trough) has occurred.,1: An underflow (trough) has occurred." newline bitfld.long 0x2C 6. "TCPFO,Overflow Flag" "0: No overflow (crest) has occurred.,1: An overflow (crest) has occurred." bitfld.long 0x2C 5. "TCFF,Input Compare Match Flag F" "0: No compare match of GTCCRF is generated.,1: A compare match of GTCCRF is generated." newline bitfld.long 0x2C 4. "TCFE,Input Compare Match Flag E" "0: No compare match of GTCCRE is generated.,1: A compare match of GTCCRE is generated." bitfld.long 0x2C 3. "TCFD,Input Compare Match Flag D" "0: No compare match of GTCCRD is generated.,1: A compare match of GTCCRD is generated." newline bitfld.long 0x2C 2. "TCFC,Input Compare Match Flag C" "0: No compare match of GTCCRC is generated.,1: A compare match of GTCCRC is generated." bitfld.long 0x2C 1. "TCFB,Input Capture/Compare Match Flag B" "0: No input capture/compare match of GTCCRB is..,1: An input capture/compare match of GTCCRB is.." newline bitfld.long 0x2C 0. "TCFA,Input Capture/Compare Match Flag A" "0: No input capture/compare match of GTCCRA is..,1: An input capture/compare match of GTCCRA is.." line.long 0x30 "GTBER,General PWM Timer Buffer Enable Register" bitfld.long 0x30 22. "CCRSWT,GTCCRA and GTCCRB Forcible Buffer OperationThis bit is read as 0." "0: no effect,1: Forcibly performs buffer transfer of GTCCRA and.." bitfld.long 0x30 20.--21. "PR,GTPR Buffer Operation" "0: Setting prohibited,1: Single buffer operation (GTPBR --> GTPR),?,?" newline bitfld.long 0x30 18.--19. "CCRB,GTCCRB Buffer Operation" "0: Buffer operation is not performed,1: Single buffer operation (GTCCRB <--> GTCCRE),?,?" bitfld.long 0x30 16.--17. "CCRA,GTCCRA Buffer Operation" "0: Buffer operation is not performed,1: Single buffer operation (GTCCRA <--> GTCCRC),?,?" newline bitfld.long 0x30 0.--1. "BD,BD[1]: GTPR Buffer Operation DisableBD[0]: GTCCR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled,?,?" group.long 0x48++0x23 line.long 0x0 "GTCNT,General PWM Timer Counter" hexmask.long 0x0 0.--31. 1. "GTCNT,Counter" line.long 0x4 "GTCCRA,General PWM Timer Compare Capture Register A" hexmask.long 0x4 0.--31. 1. "GTCCRA,Compare Capture Register A" line.long 0x8 "GTCCRB,General PWM Timer Compare Capture Register B" hexmask.long 0x8 0.--31. 1. "GTCCRB,Compare Capture Register B" line.long 0xC "GTCCRC,General PWM Timer Compare Capture Register C" hexmask.long 0xC 0.--31. 1. "GTCCRC,Compare Capture Register C" line.long 0x10 "GTCCRE,General PWM Timer Compare Capture Register E" hexmask.long 0x10 0.--31. 1. "GTCCRE,Compare Capture Register E" line.long 0x14 "GTCCRD,General PWM Timer Compare Capture Register D" hexmask.long 0x14 0.--31. 1. "GTCCRD,Compare Capture Register D" line.long 0x18 "GTCCRF,General PWM Timer Compare Capture Register F" hexmask.long 0x18 0.--31. 1. "GTCCRF,Compare Capture Register F" line.long 0x1C "GTPR,General PWM Timer Cycle Setting Register" hexmask.long 0x1C 0.--31. 1. "GTPR,Cycle Setting Register" line.long 0x20 "GTPBR,General PWM Timer Cycle Setting Buffer Register" hexmask.long 0x20 0.--31. 1. "GTPBR,Cycle Setting Buffer Register" group.long 0x88++0x7 line.long 0x0 "GTDTCR,General PWM Timer Dead Time Control Register" hexmask.long.tbyte 0x0 9.--31. 1. "Reserved,These bits are read as 00000000000000000000000. The write value should be 00000000000000000000000." bitfld.long 0x0 8. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.long 0x0 6.--7. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.long 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.long 0x0 4. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 1.--3. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "TDE,Negative-Phase Waveform Setting" "0: GTCCRB is set without using GTDVU and GTDVD.,1: GTDVU and GTDVD are used to set the compare.." line.long 0x4 "GTDVU,General PWM Timer Dead Time Value Register U" hexmask.long 0x4 0.--31. 1. "GTDVU,Dead Time Value Register U" tree.end tree "GPT322" base ad:0x40078200 group.long 0x0++0xB line.long 0x0 "GTWP,General PWM Timer Write-Protection Register" hexmask.long.word 0x0 16.--31. 1. "Reserved,These bits are read as 0000000000000000. The write value should be 0000000000000000." hexmask.long.byte 0x0 8.--15. 1. "PRKEY,GTWP Key Code" newline hexmask.long.byte 0x0 1.--7. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.long 0x0 0. "WP,Register Write Disable" "0: Write to the register is enabled,1: Write to the register is disabled" line.long 0x4 "GTSTR,General PWM Timer Software Start Register" hexmask.long.tbyte 0x4 10.--31. 1. "Reserved,These bits are read as 0000000000000000000000. The write value should be 0000000000000000000000." bitfld.long 0x4 9. "CSTRT9,Channel 9 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT169.GTCNT counter starts (write) / Counter.." newline bitfld.long 0x4 8. "CSTRT8,Channel 8 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT168.GTCNT counter starts (write) / Counter.." bitfld.long 0x4 7. "CSTRT7,Channel 7 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT167.GTCNT counter starts (write) / Counter.." newline bitfld.long 0x4 6. "CSTRT6,Channel 6 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT166.GTCNT counter starts (write) / Counter.." bitfld.long 0x4 5. "CSTRT5,Channel 5 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT165.GTCNT counter starts (write) / Counter.." newline bitfld.long 0x4 4. "CSTRT4,Channel 4 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT164.GTCNT counter starts (write) / Counter.." bitfld.long 0x4 3. "CSTRT3,Channel 3 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT323.GTCNT counter starts (write) / Counter.." newline bitfld.long 0x4 2. "CSTRT2,Channel 2 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT322.GTCNT counter starts (write) / Counter.." bitfld.long 0x4 1. "CSTRT1,Channel 1 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT321.GTCNT counter starts (write) / Counter.." newline bitfld.long 0x4 0. "CSTRT0,Channel 0 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT320.GTCNT counter starts (write) / Counter.." line.long 0x8 "GTSTP,General PWM Timer Software Stop Register" hexmask.long.tbyte 0x8 10.--31. 1. "Reserved,These bits are read as 1111111111111111111111. The write value should be 1111111111111111111111." bitfld.long 0x8 9. "CSTOP9,Channel 9 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT169.GTCNT counter stops (write) / Counter.." newline bitfld.long 0x8 8. "CSTOP8,Channel 8 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT168.GTCNT counter stops (write) / Counter.." bitfld.long 0x8 7. "CSTOP7,Channel 7 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT167.GTCNT counter stops (write) / Counter.." newline bitfld.long 0x8 6. "CSTOP6,Channel 6 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT166.GTCNT counter stops (write) / Counter.." bitfld.long 0x8 5. "CSTOP5,Channel 5 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT165.GTCNT counter stops (write) / Counter.." newline bitfld.long 0x8 4. "CSTOP4,Channel 4 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT164.GTCNT counter stops (write) / Counter.." bitfld.long 0x8 3. "CSTOP3,Channel 3 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT323.GTCNT counter stops (write) / Counter.." newline bitfld.long 0x8 2. "CSTOP2,Channel 2 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT322.GTCNT counter stops (write) / Counter.." bitfld.long 0x8 1. "CSTOP1,Channel 1 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT321.GTCNT counter stops (write) / Counter.." newline bitfld.long 0x8 0. "CSTOP0,Channel 0 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT320.GTCNT counter stops (write) / Counter.." wgroup.long 0xC++0x3 line.long 0x0 "GTCLR,General PWM Timer Software Clear Register" hexmask.long.tbyte 0x0 10.--31. 1. "Reserved,The write value should be 0000000000000000000000." bitfld.long 0x0 9. "CCLR9,Channel 9 GTCNT Count Clear" "0: No effect,1: GPT169.GTCNT counter clears" newline bitfld.long 0x0 8. "CCLR8,Channel 8 GTCNT Count Clear" "0: No effect,1: GPT168.GTCNT counter clears" bitfld.long 0x0 7. "CCLR7,Channel 7 GTCNT Count Clear" "0: No effect,1: GPT167.GTCNT counter clears" newline bitfld.long 0x0 6. "CCLR6,Channel 6 GTCNT Count Clear" "0: No effect,1: GPT166.GTCNT counter clears" bitfld.long 0x0 5. "CCLR5,Channel 5 GTCNT Count Clear" "0: No effect,1: GPT165.GTCNT counter clears" newline bitfld.long 0x0 4. "CCLR4,Channel 4 GTCNT Count Clear" "0: No effect,1: GPT164.GTCNT counter clears" bitfld.long 0x0 3. "CCLR3,Channel 3 GTCNT Count Clear" "0: No effect,1: GPT323.GTCNT counter clears" newline bitfld.long 0x0 2. "CCLR2,Channel 2 GTCNT Count Clear" "0: No effect,1: GPT322.GTCNT counter clears" bitfld.long 0x0 1. "CCLR1,Channel 1 GTCNT Count Clear" "0: No effect,1: GPT321.GTCNT counter clears" newline bitfld.long 0x0 0. "CCLR0,Channel 0 GTCNT Count Clear" "0: No effect,1: GPT320.GTCNT counter clears" group.long 0x10++0x33 line.long 0x0 "GTSSR,General PWM Timer Start Source Select Register" bitfld.long 0x0 31. "CSTRT,Software Source Counter Start Enable" "0: Counter start is disable by the GTSTR register,1: Counter start is enable by the GTSTR register" hexmask.long.byte 0x0 24.--30. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." newline bitfld.long 0x0 23. "SSELCH,ELCH Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTH input,1: Counter start is enable at the ELC_GPTH input" bitfld.long 0x0 22. "SSELCG,ELC_GPTG Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTG input,1: Counter start is enable at the ELC_GPTG input" newline bitfld.long 0x0 21. "SSELCF,ELC_GPTF Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTF input,1: Counter start is enable at the ELC_GPTF input" bitfld.long 0x0 20. "SSELCE,ELC_GPTE Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTE input,1: Counter start is enable at the ELC_GPTE input" newline bitfld.long 0x0 19. "SSELCD,ELC_GPTD Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTD input,1: Counter start is enable at the ELC_GPTD input" bitfld.long 0x0 18. "SSELCC,ELC_GPTC Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTC input,1: Counter start is enable at the ELC_GPTC input" newline bitfld.long 0x0 17. "SSELCB,ELC_GPTB Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTB input,1: Counter start is enable at the ELC_GPTB input" bitfld.long 0x0 16. "SSELCA,ELC_GPTA Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTA input,1: Counter start is enable at the ELC_GPTA input" newline bitfld.long 0x0 15. "SSCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." bitfld.long 0x0 14. "SSCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." newline bitfld.long 0x0 13. "SSCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." bitfld.long 0x0 12. "SSCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." newline bitfld.long 0x0 11. "SSCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." bitfld.long 0x0 10. "SSCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." newline bitfld.long 0x0 9. "SSCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." bitfld.long 0x0 8. "SSCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." newline hexmask.long.byte 0x0 4.--7. 1. "Reserved,These bits are read as 0000. The write value should be 0000." bitfld.long 0x0 3. "SSGTRGBF,GTETRGB Pin Falling Input Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." newline bitfld.long 0x0 2. "SSGTRGBR,GTETRGB Pin Rising Input Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." bitfld.long 0x0 1. "SSGTRGAF,GTETRGA Pin Falling Input Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." newline bitfld.long 0x0 0. "SSGTRGAR,GTETRGA Pin Rising Input Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." line.long 0x4 "GTPSR,General PWM Timer Stop Source Select Register" bitfld.long 0x4 31. "CSTOP,Software Source Counter Stop Enable" "0: Counter stop is disable by the GTSTP register,1: Counter stop is enable by the GTSTP register" hexmask.long.byte 0x4 24.--30. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." newline bitfld.long 0x4 23. "PSELCH,ELCH Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTH input,1: Counter stop is enable at the ELC_GPTH input" bitfld.long 0x4 22. "PSELCG,ELC_GPTG Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTG input,1: Counter stop is enable at the ELC_GPTG input" newline bitfld.long 0x4 21. "PSELCF,ELC_GPTF Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTF input,1: Counter stop is enable at the ELC_GPTF input" bitfld.long 0x4 20. "PSELCE,ELC_GPTE Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTE input,1: Counter stop is enable at the ELC_GPTE input" newline bitfld.long 0x4 19. "PSELCD,ELC_GPTD Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTD input,1: Counter stop is enable at the ELC_GPTD input" bitfld.long 0x4 18. "PSELCC,ELC_GPTC Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTC input,1: Counter stop is enable at the ELC_GPTC input" newline bitfld.long 0x4 17. "PSELCB,ELC_GPTB Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTB input,1: Counter stop is enable at the ELC_GPTB input" bitfld.long 0x4 16. "PSELCA,ELC_GPTA Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTA input,1: Counter stop is enable at the ELC_GPTA input" newline bitfld.long 0x4 15. "PSCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." bitfld.long 0x4 14. "PSCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." newline bitfld.long 0x4 13. "PSCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." bitfld.long 0x4 12. "PSCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." newline bitfld.long 0x4 11. "PSCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." bitfld.long 0x4 10. "PSCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." newline bitfld.long 0x4 9. "PSCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." bitfld.long 0x4 8. "PSCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." newline hexmask.long.byte 0x4 4.--7. 1. "Reserved,These bits are read as 0000. The write value should be 0000." bitfld.long 0x4 3. "PSGTRGBF,GTETRGB Pin Falling Input Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." newline bitfld.long 0x4 2. "PSGTRGBR,GTETRGB Pin Rising Input Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." bitfld.long 0x4 1. "PSGTRGAF,GTETRGA Pin Falling Input Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." newline bitfld.long 0x4 0. "PSGTRGAR,GTETRGA Pin Rising Input Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." line.long 0x8 "GTCSR,General PWM Timer Clear Source Select Register" bitfld.long 0x8 31. "CCLR,Software Source Counter Clear Enable" "0: Counter clear is disable by the GTCLR register,1: Counter clear is enable by the GTCLR register" hexmask.long.byte 0x8 24.--30. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." newline bitfld.long 0x8 23. "CSELCH,ELCH Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTH input,1: Counter clear is enable at the ELC_GPTH input" bitfld.long 0x8 22. "CSELCG,ELC_GPTG Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTG input,1: Counter clear is enable at the ELC_GPTG input" newline bitfld.long 0x8 21. "CSELCF,ELC_GPTF Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTF input,1: Counter clear is enable at the ELC_GPTF input" bitfld.long 0x8 20. "CSELCE,ELC_GPTE Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTE input,1: Counter clear is enable at the ELC_GPTE input" newline bitfld.long 0x8 19. "CSELCD,ELC_GPTD Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTD input,1: Counter clear is enable at the ELC_GPTD input" bitfld.long 0x8 18. "CSELCC,ELC_GPTC Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTC input,1: Counter clear is enable at the ELC_GPTC input" newline bitfld.long 0x8 17. "CSELCB,ELC_GPTB Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTB input,1: Counter clear is enable at the ELC_GPTB input" bitfld.long 0x8 16. "CSELCA,ELC_GPTA Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTA input,1: Counter clear is enable at the ELC_GPTA input" newline bitfld.long 0x8 15. "CSCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." bitfld.long 0x8 14. "CSCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." newline bitfld.long 0x8 13. "CSCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." bitfld.long 0x8 12. "CSCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." newline bitfld.long 0x8 11. "CSCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." bitfld.long 0x8 10. "CSCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." newline bitfld.long 0x8 9. "CSCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." bitfld.long 0x8 8. "CSCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." newline hexmask.long.byte 0x8 4.--7. 1. "Reserved,These bits are read as 0000. The write value should be 0000." bitfld.long 0x8 3. "CSGTRGBF,GTETRGB Pin Falling Input Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." newline bitfld.long 0x8 2. "CSGTRGBR,GTETRGB Pin Rising Input Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." bitfld.long 0x8 1. "CSGTRGAF,GTETRGA Pin Falling Input Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." newline bitfld.long 0x8 0. "CSGTRGAR,GTETRGA Pin Rising Input Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." line.long 0xC "GTUPSR,General PWM Timer Up Count Source Select Register" bitfld.long 0xC 23. "USELCH,ELCH Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTH input,1: Counter count up is enable at the ELC_GPTH input" bitfld.long 0xC 22. "USELCG,ELC_GPTG Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTG input,1: Counter count up is enable at the ELC_GPTG input" newline bitfld.long 0xC 21. "USELCF,ELC_GPTF Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTF input,1: Counter count up is enable at the ELC_GPTF input" bitfld.long 0xC 20. "USELCE,ELC_GPTE Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTE input,1: Counter count up is enable at the ELC_GPTE input" newline bitfld.long 0xC 19. "USELCD,ELC_GPTD Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTD input,1: Counter count up is enable at the ELC_GPTD input" bitfld.long 0xC 18. "USELCC,ELC_GPTC Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTC input,1: Counter count up is enable at the ELC_GPTC input" newline bitfld.long 0xC 17. "USELCB,ELC_GPTB Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTB input,1: Counter count up is enable at the ELC_GPTB input" bitfld.long 0xC 16. "USELCA,ELC_GPTA Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTA input,1: Counter count up is enable at the ELC_GPTA input" newline bitfld.long 0xC 15. "USCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." bitfld.long 0xC 14. "USCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." newline bitfld.long 0xC 13. "USCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." bitfld.long 0xC 12. "USCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." newline bitfld.long 0xC 11. "USCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." bitfld.long 0xC 10. "USCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." newline bitfld.long 0xC 9. "USCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." bitfld.long 0xC 8. "USCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." newline bitfld.long 0xC 3. "USGTRGBF,GTETRGB Pin Falling Input Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." bitfld.long 0xC 2. "USGTRGBR,GTETRGB Pin Rising Input Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." newline bitfld.long 0xC 1. "USGTRGAF,GTETRGA Pin Falling Input Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." bitfld.long 0xC 0. "USGTRGAR,GTETRGA Pin Rising Input Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." line.long 0x10 "GTDNSR,General PWM Timer Down Count Source Select Register" bitfld.long 0x10 23. "DSELCH,ELCH Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTH..,1: Counter count down is enable at the ELC_GPTH input" bitfld.long 0x10 22. "DSELCG,ELC_GPTG Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTG..,1: Counter count down is enable at the ELC_GPTG input" newline bitfld.long 0x10 21. "DSELCF,ELC_GPTF Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTF..,1: Counter count down is enable at the ELC_GPTF input" bitfld.long 0x10 20. "DSELCE,ELC_GPTE Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTE..,1: Counter count down is enable at the ELC_GPTE input" newline bitfld.long 0x10 19. "DSELCD,ELC_GPTD Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTD..,1: Counter count down is enable at the ELC_GPTD input" bitfld.long 0x10 18. "DSELCC,ELC_GPTC Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTC..,1: Counter count down is enable at the ELC_GPTC input" newline bitfld.long 0x10 17. "DSELCB,ELC_GPTB Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTB..,1: Counter count down is enable at the ELC_GPTB input" bitfld.long 0x10 16. "DSELCA,ELC_GPTA Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTA..,1: Counter count down is enable at the ELC_GPTA input" newline bitfld.long 0x10 15. "DSCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." bitfld.long 0x10 14. "DSCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." newline bitfld.long 0x10 13. "DSCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." bitfld.long 0x10 12. "DSCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." newline bitfld.long 0x10 11. "DSCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." bitfld.long 0x10 10. "DSCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." newline bitfld.long 0x10 9. "DSCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." bitfld.long 0x10 8. "DSCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." newline bitfld.long 0x10 3. "DSGTRGBF,GTETRGB Pin Falling Input Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." bitfld.long 0x10 2. "DSGTRGBR,GTETRGB Pin Rising Input Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." newline bitfld.long 0x10 1. "DSGTRGAF,GTETRGA Pin Falling Input Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." bitfld.long 0x10 0. "DSGTRGAR,GTETRGA Pin Rising Input Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." line.long 0x14 "GTICASR,General PWM Timer Input Capture Source Select Register A" bitfld.long 0x14 23. "ASELCH,ELCH Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTH..,1: GTCCRA input capture is enable at the ELC_GPTH.." bitfld.long 0x14 22. "ASELCG,ELC_GPTG Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTG..,1: GTCCRA input capture is enable at the ELC_GPTG.." newline bitfld.long 0x14 21. "ASELCF,ELC_GPTF Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTF..,1: GTCCRA input capture is enable at the ELC_GPTF.." bitfld.long 0x14 20. "ASELCE,ELC_GPTE Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTE..,1: GTCCRA input capture is enable at the ELC_GPTE.." newline bitfld.long 0x14 19. "ASELCD,ELC_GPTD Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTD..,1: GTCCRA input capture is enable at the ELC_GPTD.." bitfld.long 0x14 18. "ASELCC,ELC_GPTC Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTC..,1: GTCCRA input capture is enable at the ELC_GPTC.." newline bitfld.long 0x14 17. "ASELCB,ELC_GPTB Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTB..,1: GTCCRA input capture is enable at the ELC_GPTB.." bitfld.long 0x14 16. "ASELCA,ELC_GPTA Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTA..,1: GTCCRA input capture is enable at the ELC_GPTA.." newline bitfld.long 0x14 15. "ASCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." bitfld.long 0x14 14. "ASCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." newline bitfld.long 0x14 13. "ASCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." bitfld.long 0x14 12. "ASCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." newline bitfld.long 0x14 11. "ASCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." bitfld.long 0x14 10. "ASCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." newline bitfld.long 0x14 9. "ASCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." bitfld.long 0x14 8. "ASCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." newline bitfld.long 0x14 3. "ASGTRGBF,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." bitfld.long 0x14 2. "ASGTRGBR,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." newline bitfld.long 0x14 1. "ASGTRGAF,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." bitfld.long 0x14 0. "ASGTRGAR,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." line.long 0x18 "GTICBSR,General PWM Timer Input Capture Source Select Register B" bitfld.long 0x18 23. "BSELCH,ELCH Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTH..,1: GTCCRB input capture is enable at the ELC_GPTH.." bitfld.long 0x18 22. "BSELCG,ELC_GPTG Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTG..,1: GTCCRB input capture is enable at the ELC_GPTG.." newline bitfld.long 0x18 21. "BSELCF,ELC_GPTF Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTF..,1: GTCCRB input capture is enable at the ELC_GPTF.." bitfld.long 0x18 20. "BSELCE,ELC_GPTE Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTE..,1: GTCCRB input capture is enable at the ELC_GPTE.." newline bitfld.long 0x18 19. "BSELCD,ELC_GPTD Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTD..,1: GTCCRB input capture is enable at the ELC_GPTD.." bitfld.long 0x18 18. "BSELCC,ELC_GPTC Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTC..,1: GTCCRB input capture is enable at the ELC_GPTC.." newline bitfld.long 0x18 17. "BSELCB,ELC_GPTB Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTB..,1: GTCCRB input capture is enable at the ELC_GPTB.." bitfld.long 0x18 16. "BSELCA,ELC_GPTA Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTA..,1: GTCCRB input capture is enable at the ELC_GPTA.." newline bitfld.long 0x18 15. "BSCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." bitfld.long 0x18 14. "BSCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." newline bitfld.long 0x18 13. "BSCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." bitfld.long 0x18 12. "BSCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." newline bitfld.long 0x18 11. "BSCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." bitfld.long 0x18 10. "BSCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." newline bitfld.long 0x18 9. "BSCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." bitfld.long 0x18 8. "BSCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." newline bitfld.long 0x18 3. "BSGTRGBF,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." bitfld.long 0x18 2. "BSGTRGBR,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." newline bitfld.long 0x18 1. "BSGTRGAF,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." bitfld.long 0x18 0. "BSGTRGAR,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." line.long 0x1C "GTCR,General PWM Timer Control Register" bitfld.long 0x1C 24.--26. "TPCS,Timer Prescaler Select" "0: Setting prohibied,1: PCLK/4,?,?,?,?,?,?" hexmask.long.byte 0x1C 19.--23. 1. "Reserved,These bits are read as 00000. The write value should be 00000." newline bitfld.long 0x1C 16.--18. "MD,Mode Select" "0: Saw-wave PWM mode (single buffer or double..,1: Saw-wave one-shot pulse mode (fixed buffer..,?,?,?,?,?,?" hexmask.long.word 0x1C 1.--15. 1. "Reserved,These bits are read as 000000000000000. The write value should be 000000000000000." newline bitfld.long 0x1C 0. "CST,Count Start" "0: Count operation is stopped,1: Count operation is performed" line.long 0x20 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register" bitfld.long 0x20 27. "OBDTYR,GTIOCB Output Value Selecting after Releasing 0 percent/100 percent Duty Setting" "0: Apply output value set in 0 percent/100 percent..,1: Apply masked compare match output value to.." bitfld.long 0x20 26. "OBDTYF,Forcible GTIOCB Output Duty Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x20 24.--25. "OBDTY,GTIOCB Output Duty Setting" "0: GTIOCB pin duty is depend on compare match,1: GTIOCB pin duty is depend on compare match,?,?" hexmask.long.byte 0x20 20.--23. 1. "Reserved,These bits are read as 0000. The write value should be 0000." newline bitfld.long 0x20 19. "OADTYR,GTIOCA Output Value Selecting after Releasing 0 percent/100 percent Duty Setting" "0: Apply output value set in 0 percent/100 percent..,1: Apply masked compare match output value to.." bitfld.long 0x20 18. "OADTYF,Forcible GTIOCA Output Duty Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x20 16.--17. "OADTY,GTIOCA Output Duty Setting" "0: GTIOCA pin duty is depend on compare match,1: GTIOCA pin duty is depend on compare match,?,?" bitfld.long 0x20 1. "UDF,Forcible Count Direction Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x20 0. "UD,Count Direction Setting" "0: GTCNT counts down.,1: GTCNT counts up." line.long 0x24 "GTIOR,General PWM Timer I/O Control Register" bitfld.long 0x24 30.--31. "NFCSB,Noise Filter B Sampling Clock Select" "0: PCLK/1,1: PCLK/4,?,?" bitfld.long 0x24 29. "NFBEN,Noise Filter B Enable" "0: The noise filter for the GTIOCB pin is disabled.,1: The noise filter for the GTIOCB pin is enabled." newline bitfld.long 0x24 27.--28. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.long 0x24 25.--26. "OBDF,GTIOCB Pin Disable Value Setting" "0: Output disable is prohibited.,1: GTIOCB pin is set to Hi-Z when output disable is..,?,?" newline bitfld.long 0x24 24. "OBE,GTIOCB Pin Output Enable" "0: Output is disabled,1: Output is enabled" bitfld.long 0x24 23. "OBHLD,GTIOCB Pin Output Setting at the Start/Stop Count" "0: The GTIOCB pin output level at start/stop of..,1: The GTIOCB pin output level is retained at.." newline bitfld.long 0x24 22. "OBDFLT,GTIOCB Pin Output Value Setting at the Count Stop" "0: The GTIOCB pin outputs low when counting is..,1: The GTIOCB pin outputs high when counting is.." bitfld.long 0x24 21. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline hexmask.long.byte 0x24 16.--20. 1. "GTIOB,GTIOCB Pin Function Select" bitfld.long 0x24 14.--15. "NFCSA,Noise Filter A Sampling Clock Select" "0: PCLK/1,1: PCLK/4,?,?" newline bitfld.long 0x24 13. "NFAEN,Noise Filter A Enable" "0: The noise filter for the GTIOCA pin is disabled.,1: The noise filter for the GTIOCA pin is enabled." bitfld.long 0x24 11.--12. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" newline bitfld.long 0x24 9.--10. "OADF,GTIOCA Pin Disable Value Setting" "0: Output disable is prohibited.,1: GTIOCA pin is set to Hi-Z when output disable is..,?,?" bitfld.long 0x24 8. "OAE,GTIOCA Pin Output Enable" "0: Output is disabled,1: Output is enabled" newline bitfld.long 0x24 7. "OAHLD,GTIOCA Pin Output Setting at the Start/Stop Count" "0: The GTIOCA pin output level at start/stop of..,1: The GTIOCA pin output level is retained at.." bitfld.long 0x24 6. "OADFLT,GTIOCA Pin Output Value Setting at the Count Stop" "0: The GTIOCA pin outputs low when counting is..,1: The GTIOCA pin outputs high when counting is.." newline bitfld.long 0x24 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" hexmask.long.byte 0x24 0.--4. 1. "GTIOA,GTIOCA Pin Function Select" line.long 0x28 "GTINTAD,General PWM Timer Interrupt Output Setting Register" bitfld.long 0x28 30. "GRPABL,Same Time Output Level Low Disable Request Enable" "0: Same time output level low disable request is..,1: Same time output level low disable request is.." bitfld.long 0x28 29. "GRPABH,Same Time Output Level High Disable Request Enable" "0: Same time output level high disable request is..,1: Same time output level high disable request is.." newline bitfld.long 0x28 26.--28. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.long 0x28 24.--25. "GRP,Output Disable Source Select" "0: Setting prohibited,1: Group B output disable request,?,?" newline hexmask.long.tbyte 0x28 0.--23. 1. "Reserved,These bits are read as 000000000000000000000000. The write value should be 000000000000000000000000." line.long 0x2C "GTST,General PWM Timer Status Register" rbitfld.long 0x2C 30. "OABLF,Same Time Output Level Low Disable Request Enable" "0: GTIOCA pin and GTIOCB pin don't output 0 at the..,1: GTIOCA pin and GTIOCB pin output 0 at the same.." rbitfld.long 0x2C 29. "OABHF,Same Time Output Level High Disable Request Enable" "0: GTIOCA pin and GTIOCB pin don't output 1 at the..,1: GTIOCA pin and GTIOCB pin output 1 at the same.." newline hexmask.long.byte 0x2C 25.--28. 1. "Reserved,These bits are read as 0000. The write value should be 0000." rbitfld.long 0x2C 24. "ODF,Output Disable Flag" "0: No output disable request is generated.,1: An output disable request is generated." newline hexmask.long.byte 0x2C 16.--23. 1. "Reserved,These bits are read as 00000000. The write value should be 00000000." rbitfld.long 0x2C 15. "TUCF,Count Direction Flag" "0: The GTCNT counter counts downward.,1: The GTCNT counter counts upward." newline hexmask.long.byte 0x2C 8.--14. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.long 0x2C 7. "TCFPU,Underflow Flag" "0: No underflow (trough) has occurred.,1: An underflow (trough) has occurred." newline bitfld.long 0x2C 6. "TCPFO,Overflow Flag" "0: No overflow (crest) has occurred.,1: An overflow (crest) has occurred." bitfld.long 0x2C 5. "TCFF,Input Compare Match Flag F" "0: No compare match of GTCCRF is generated.,1: A compare match of GTCCRF is generated." newline bitfld.long 0x2C 4. "TCFE,Input Compare Match Flag E" "0: No compare match of GTCCRE is generated.,1: A compare match of GTCCRE is generated." bitfld.long 0x2C 3. "TCFD,Input Compare Match Flag D" "0: No compare match of GTCCRD is generated.,1: A compare match of GTCCRD is generated." newline bitfld.long 0x2C 2. "TCFC,Input Compare Match Flag C" "0: No compare match of GTCCRC is generated.,1: A compare match of GTCCRC is generated." bitfld.long 0x2C 1. "TCFB,Input Capture/Compare Match Flag B" "0: No input capture/compare match of GTCCRB is..,1: An input capture/compare match of GTCCRB is.." newline bitfld.long 0x2C 0. "TCFA,Input Capture/Compare Match Flag A" "0: No input capture/compare match of GTCCRA is..,1: An input capture/compare match of GTCCRA is.." line.long 0x30 "GTBER,General PWM Timer Buffer Enable Register" bitfld.long 0x30 22. "CCRSWT,GTCCRA and GTCCRB Forcible Buffer OperationThis bit is read as 0." "0: no effect,1: Forcibly performs buffer transfer of GTCCRA and.." bitfld.long 0x30 20.--21. "PR,GTPR Buffer Operation" "0: Setting prohibited,1: Single buffer operation (GTPBR --> GTPR),?,?" newline bitfld.long 0x30 18.--19. "CCRB,GTCCRB Buffer Operation" "0: Buffer operation is not performed,1: Single buffer operation (GTCCRB <--> GTCCRE),?,?" bitfld.long 0x30 16.--17. "CCRA,GTCCRA Buffer Operation" "0: Buffer operation is not performed,1: Single buffer operation (GTCCRA <--> GTCCRC),?,?" newline bitfld.long 0x30 0.--1. "BD,BD[1]: GTPR Buffer Operation DisableBD[0]: GTCCR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled,?,?" group.long 0x48++0x23 line.long 0x0 "GTCNT,General PWM Timer Counter" hexmask.long 0x0 0.--31. 1. "GTCNT,Counter" line.long 0x4 "GTCCRA,General PWM Timer Compare Capture Register A" hexmask.long 0x4 0.--31. 1. "GTCCRA,Compare Capture Register A" line.long 0x8 "GTCCRB,General PWM Timer Compare Capture Register B" hexmask.long 0x8 0.--31. 1. "GTCCRB,Compare Capture Register B" line.long 0xC "GTCCRC,General PWM Timer Compare Capture Register C" hexmask.long 0xC 0.--31. 1. "GTCCRC,Compare Capture Register C" line.long 0x10 "GTCCRE,General PWM Timer Compare Capture Register E" hexmask.long 0x10 0.--31. 1. "GTCCRE,Compare Capture Register E" line.long 0x14 "GTCCRD,General PWM Timer Compare Capture Register D" hexmask.long 0x14 0.--31. 1. "GTCCRD,Compare Capture Register D" line.long 0x18 "GTCCRF,General PWM Timer Compare Capture Register F" hexmask.long 0x18 0.--31. 1. "GTCCRF,Compare Capture Register F" line.long 0x1C "GTPR,General PWM Timer Cycle Setting Register" hexmask.long 0x1C 0.--31. 1. "GTPR,Cycle Setting Register" line.long 0x20 "GTPBR,General PWM Timer Cycle Setting Buffer Register" hexmask.long 0x20 0.--31. 1. "GTPBR,Cycle Setting Buffer Register" group.long 0x88++0x7 line.long 0x0 "GTDTCR,General PWM Timer Dead Time Control Register" hexmask.long.tbyte 0x0 9.--31. 1. "Reserved,These bits are read as 00000000000000000000000. The write value should be 00000000000000000000000." bitfld.long 0x0 8. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.long 0x0 6.--7. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.long 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.long 0x0 4. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 1.--3. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "TDE,Negative-Phase Waveform Setting" "0: GTCCRB is set without using GTDVU and GTDVD.,1: GTDVU and GTDVD are used to set the compare.." line.long 0x4 "GTDVU,General PWM Timer Dead Time Value Register U" hexmask.long 0x4 0.--31. 1. "GTDVU,Dead Time Value Register U" tree.end tree "GPT323" base ad:0x40078300 group.long 0x0++0xB line.long 0x0 "GTWP,General PWM Timer Write-Protection Register" hexmask.long.word 0x0 16.--31. 1. "Reserved,These bits are read as 0000000000000000. The write value should be 0000000000000000." hexmask.long.byte 0x0 8.--15. 1. "PRKEY,GTWP Key Code" newline hexmask.long.byte 0x0 1.--7. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.long 0x0 0. "WP,Register Write Disable" "0: Write to the register is enabled,1: Write to the register is disabled" line.long 0x4 "GTSTR,General PWM Timer Software Start Register" hexmask.long.tbyte 0x4 10.--31. 1. "Reserved,These bits are read as 0000000000000000000000. The write value should be 0000000000000000000000." bitfld.long 0x4 9. "CSTRT9,Channel 9 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT169.GTCNT counter starts (write) / Counter.." newline bitfld.long 0x4 8. "CSTRT8,Channel 8 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT168.GTCNT counter starts (write) / Counter.." bitfld.long 0x4 7. "CSTRT7,Channel 7 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT167.GTCNT counter starts (write) / Counter.." newline bitfld.long 0x4 6. "CSTRT6,Channel 6 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT166.GTCNT counter starts (write) / Counter.." bitfld.long 0x4 5. "CSTRT5,Channel 5 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT165.GTCNT counter starts (write) / Counter.." newline bitfld.long 0x4 4. "CSTRT4,Channel 4 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT164.GTCNT counter starts (write) / Counter.." bitfld.long 0x4 3. "CSTRT3,Channel 3 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT323.GTCNT counter starts (write) / Counter.." newline bitfld.long 0x4 2. "CSTRT2,Channel 2 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT322.GTCNT counter starts (write) / Counter.." bitfld.long 0x4 1. "CSTRT1,Channel 1 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT321.GTCNT counter starts (write) / Counter.." newline bitfld.long 0x4 0. "CSTRT0,Channel 0 GTCNT Count StartRead data shows each channel's counter status (GTCR.CST bit). 0 means counter stop. 1 means counter running." "0: No effect (write) / counter stop (read),1: GPT320.GTCNT counter starts (write) / Counter.." line.long 0x8 "GTSTP,General PWM Timer Software Stop Register" hexmask.long.tbyte 0x8 10.--31. 1. "Reserved,These bits are read as 1111111111111111111111. The write value should be 1111111111111111111111." bitfld.long 0x8 9. "CSTOP9,Channel 9 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT169.GTCNT counter stops (write) / Counter.." newline bitfld.long 0x8 8. "CSTOP8,Channel 8 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT168.GTCNT counter stops (write) / Counter.." bitfld.long 0x8 7. "CSTOP7,Channel 7 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT167.GTCNT counter stops (write) / Counter.." newline bitfld.long 0x8 6. "CSTOP6,Channel 6 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT166.GTCNT counter stops (write) / Counter.." bitfld.long 0x8 5. "CSTOP5,Channel 5 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT165.GTCNT counter stops (write) / Counter.." newline bitfld.long 0x8 4. "CSTOP4,Channel 4 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT164.GTCNT counter stops (write) / Counter.." bitfld.long 0x8 3. "CSTOP3,Channel 3 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT323.GTCNT counter stops (write) / Counter.." newline bitfld.long 0x8 2. "CSTOP2,Channel 2 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT322.GTCNT counter stops (write) / Counter.." bitfld.long 0x8 1. "CSTOP1,Channel 1 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT321.GTCNT counter stops (write) / Counter.." newline bitfld.long 0x8 0. "CSTOP0,Channel 0 GTCNT Count StopRead data shows each channel's counter status (GTCR.CST bit). 0 means counter runnning. 1 means counter stop." "0: No effect (write) / counter running (read),1: GPT320.GTCNT counter stops (write) / Counter.." wgroup.long 0xC++0x3 line.long 0x0 "GTCLR,General PWM Timer Software Clear Register" hexmask.long.tbyte 0x0 10.--31. 1. "Reserved,The write value should be 0000000000000000000000." bitfld.long 0x0 9. "CCLR9,Channel 9 GTCNT Count Clear" "0: No effect,1: GPT169.GTCNT counter clears" newline bitfld.long 0x0 8. "CCLR8,Channel 8 GTCNT Count Clear" "0: No effect,1: GPT168.GTCNT counter clears" bitfld.long 0x0 7. "CCLR7,Channel 7 GTCNT Count Clear" "0: No effect,1: GPT167.GTCNT counter clears" newline bitfld.long 0x0 6. "CCLR6,Channel 6 GTCNT Count Clear" "0: No effect,1: GPT166.GTCNT counter clears" bitfld.long 0x0 5. "CCLR5,Channel 5 GTCNT Count Clear" "0: No effect,1: GPT165.GTCNT counter clears" newline bitfld.long 0x0 4. "CCLR4,Channel 4 GTCNT Count Clear" "0: No effect,1: GPT164.GTCNT counter clears" bitfld.long 0x0 3. "CCLR3,Channel 3 GTCNT Count Clear" "0: No effect,1: GPT323.GTCNT counter clears" newline bitfld.long 0x0 2. "CCLR2,Channel 2 GTCNT Count Clear" "0: No effect,1: GPT322.GTCNT counter clears" bitfld.long 0x0 1. "CCLR1,Channel 1 GTCNT Count Clear" "0: No effect,1: GPT321.GTCNT counter clears" newline bitfld.long 0x0 0. "CCLR0,Channel 0 GTCNT Count Clear" "0: No effect,1: GPT320.GTCNT counter clears" group.long 0x10++0x33 line.long 0x0 "GTSSR,General PWM Timer Start Source Select Register" bitfld.long 0x0 31. "CSTRT,Software Source Counter Start Enable" "0: Counter start is disable by the GTSTR register,1: Counter start is enable by the GTSTR register" hexmask.long.byte 0x0 24.--30. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." newline bitfld.long 0x0 23. "SSELCH,ELCH Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTH input,1: Counter start is enable at the ELC_GPTH input" bitfld.long 0x0 22. "SSELCG,ELC_GPTG Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTG input,1: Counter start is enable at the ELC_GPTG input" newline bitfld.long 0x0 21. "SSELCF,ELC_GPTF Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTF input,1: Counter start is enable at the ELC_GPTF input" bitfld.long 0x0 20. "SSELCE,ELC_GPTE Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTE input,1: Counter start is enable at the ELC_GPTE input" newline bitfld.long 0x0 19. "SSELCD,ELC_GPTD Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTD input,1: Counter start is enable at the ELC_GPTD input" bitfld.long 0x0 18. "SSELCC,ELC_GPTC Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTC input,1: Counter start is enable at the ELC_GPTC input" newline bitfld.long 0x0 17. "SSELCB,ELC_GPTB Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTB input,1: Counter start is enable at the ELC_GPTB input" bitfld.long 0x0 16. "SSELCA,ELC_GPTA Event Source Counter Start Enable" "0: Counter start is disable at the ELC_GPTA input,1: Counter start is enable at the ELC_GPTA input" newline bitfld.long 0x0 15. "SSCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." bitfld.long 0x0 14. "SSCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." newline bitfld.long 0x0 13. "SSCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." bitfld.long 0x0 12. "SSCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." newline bitfld.long 0x0 11. "SSCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." bitfld.long 0x0 10. "SSCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." newline bitfld.long 0x0 9. "SSCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." bitfld.long 0x0 8. "SSCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." newline hexmask.long.byte 0x0 4.--7. 1. "Reserved,These bits are read as 0000. The write value should be 0000." bitfld.long 0x0 3. "SSGTRGBF,GTETRGB Pin Falling Input Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." newline bitfld.long 0x0 2. "SSGTRGBR,GTETRGB Pin Rising Input Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." bitfld.long 0x0 1. "SSGTRGAF,GTETRGA Pin Falling Input Source Counter Start Enable" "0: Counter start is disable at the falling edge of..,1: Counter start is enable at the falling edge of.." newline bitfld.long 0x0 0. "SSGTRGAR,GTETRGA Pin Rising Input Source Counter Start Enable" "0: Counter start is disable at the rising edge of..,1: Counter start is enable at the rising edge of.." line.long 0x4 "GTPSR,General PWM Timer Stop Source Select Register" bitfld.long 0x4 31. "CSTOP,Software Source Counter Stop Enable" "0: Counter stop is disable by the GTSTP register,1: Counter stop is enable by the GTSTP register" hexmask.long.byte 0x4 24.--30. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." newline bitfld.long 0x4 23. "PSELCH,ELCH Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTH input,1: Counter stop is enable at the ELC_GPTH input" bitfld.long 0x4 22. "PSELCG,ELC_GPTG Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTG input,1: Counter stop is enable at the ELC_GPTG input" newline bitfld.long 0x4 21. "PSELCF,ELC_GPTF Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTF input,1: Counter stop is enable at the ELC_GPTF input" bitfld.long 0x4 20. "PSELCE,ELC_GPTE Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTE input,1: Counter stop is enable at the ELC_GPTE input" newline bitfld.long 0x4 19. "PSELCD,ELC_GPTD Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTD input,1: Counter stop is enable at the ELC_GPTD input" bitfld.long 0x4 18. "PSELCC,ELC_GPTC Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTC input,1: Counter stop is enable at the ELC_GPTC input" newline bitfld.long 0x4 17. "PSELCB,ELC_GPTB Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTB input,1: Counter stop is enable at the ELC_GPTB input" bitfld.long 0x4 16. "PSELCA,ELC_GPTA Event Source Counter Stop Enable" "0: Counter stop is disable at the ELC_GPTA input,1: Counter stop is enable at the ELC_GPTA input" newline bitfld.long 0x4 15. "PSCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." bitfld.long 0x4 14. "PSCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." newline bitfld.long 0x4 13. "PSCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." bitfld.long 0x4 12. "PSCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." newline bitfld.long 0x4 11. "PSCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." bitfld.long 0x4 10. "PSCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." newline bitfld.long 0x4 9. "PSCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." bitfld.long 0x4 8. "PSCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." newline hexmask.long.byte 0x4 4.--7. 1. "Reserved,These bits are read as 0000. The write value should be 0000." bitfld.long 0x4 3. "PSGTRGBF,GTETRGB Pin Falling Input Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." newline bitfld.long 0x4 2. "PSGTRGBR,GTETRGB Pin Rising Input Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." bitfld.long 0x4 1. "PSGTRGAF,GTETRGA Pin Falling Input Source Counter Stop Enable" "0: Counter stop is disable at the falling edge of..,1: Counter stop is enable at the falling edge of.." newline bitfld.long 0x4 0. "PSGTRGAR,GTETRGA Pin Rising Input Source Counter Stop Enable" "0: Counter stop is disable at the rising edge of..,1: Counter stop is enable at the rising edge of.." line.long 0x8 "GTCSR,General PWM Timer Clear Source Select Register" bitfld.long 0x8 31. "CCLR,Software Source Counter Clear Enable" "0: Counter clear is disable by the GTCLR register,1: Counter clear is enable by the GTCLR register" hexmask.long.byte 0x8 24.--30. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." newline bitfld.long 0x8 23. "CSELCH,ELCH Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTH input,1: Counter clear is enable at the ELC_GPTH input" bitfld.long 0x8 22. "CSELCG,ELC_GPTG Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTG input,1: Counter clear is enable at the ELC_GPTG input" newline bitfld.long 0x8 21. "CSELCF,ELC_GPTF Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTF input,1: Counter clear is enable at the ELC_GPTF input" bitfld.long 0x8 20. "CSELCE,ELC_GPTE Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTE input,1: Counter clear is enable at the ELC_GPTE input" newline bitfld.long 0x8 19. "CSELCD,ELC_GPTD Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTD input,1: Counter clear is enable at the ELC_GPTD input" bitfld.long 0x8 18. "CSELCC,ELC_GPTC Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTC input,1: Counter clear is enable at the ELC_GPTC input" newline bitfld.long 0x8 17. "CSELCB,ELC_GPTB Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTB input,1: Counter clear is enable at the ELC_GPTB input" bitfld.long 0x8 16. "CSELCA,ELC_GPTA Event Source Counter Clear Enable" "0: Counter clear is disable at the ELC_GPTA input,1: Counter clear is enable at the ELC_GPTA input" newline bitfld.long 0x8 15. "CSCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." bitfld.long 0x8 14. "CSCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." newline bitfld.long 0x8 13. "CSCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." bitfld.long 0x8 12. "CSCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." newline bitfld.long 0x8 11. "CSCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." bitfld.long 0x8 10. "CSCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." newline bitfld.long 0x8 9. "CSCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." bitfld.long 0x8 8. "CSCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." newline hexmask.long.byte 0x8 4.--7. 1. "Reserved,These bits are read as 0000. The write value should be 0000." bitfld.long 0x8 3. "CSGTRGBF,GTETRGB Pin Falling Input Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." newline bitfld.long 0x8 2. "CSGTRGBR,GTETRGB Pin Rising Input Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." bitfld.long 0x8 1. "CSGTRGAF,GTETRGA Pin Falling Input Source Counter Clear Enable" "0: Counter clear is disable at the falling edge of..,1: Counter clear is enable at the falling edge of.." newline bitfld.long 0x8 0. "CSGTRGAR,GTETRGA Pin Rising Input Source Counter Clear Enable" "0: Counter clear is disable at the rising edge of..,1: Counter clear is enable at the rising edge of.." line.long 0xC "GTUPSR,General PWM Timer Up Count Source Select Register" bitfld.long 0xC 23. "USELCH,ELCH Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTH input,1: Counter count up is enable at the ELC_GPTH input" bitfld.long 0xC 22. "USELCG,ELC_GPTG Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTG input,1: Counter count up is enable at the ELC_GPTG input" newline bitfld.long 0xC 21. "USELCF,ELC_GPTF Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTF input,1: Counter count up is enable at the ELC_GPTF input" bitfld.long 0xC 20. "USELCE,ELC_GPTE Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTE input,1: Counter count up is enable at the ELC_GPTE input" newline bitfld.long 0xC 19. "USELCD,ELC_GPTD Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTD input,1: Counter count up is enable at the ELC_GPTD input" bitfld.long 0xC 18. "USELCC,ELC_GPTC Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTC input,1: Counter count up is enable at the ELC_GPTC input" newline bitfld.long 0xC 17. "USELCB,ELC_GPTB Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTB input,1: Counter count up is enable at the ELC_GPTB input" bitfld.long 0xC 16. "USELCA,ELC_GPTA Event Source Counter Count Up Enable" "0: Counter count up is disable at the ELC_GPTA input,1: Counter count up is enable at the ELC_GPTA input" newline bitfld.long 0xC 15. "USCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." bitfld.long 0xC 14. "USCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." newline bitfld.long 0xC 13. "USCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." bitfld.long 0xC 12. "USCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." newline bitfld.long 0xC 11. "USCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." bitfld.long 0xC 10. "USCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." newline bitfld.long 0xC 9. "USCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." bitfld.long 0xC 8. "USCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." newline bitfld.long 0xC 3. "USGTRGBF,GTETRGB Pin Falling Input Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." bitfld.long 0xC 2. "USGTRGBR,GTETRGB Pin Rising Input Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." newline bitfld.long 0xC 1. "USGTRGAF,GTETRGA Pin Falling Input Source Counter Count Up Enable" "0: Counter count up is disable at the falling edge..,1: Counter count up is enable at the falling edge.." bitfld.long 0xC 0. "USGTRGAR,GTETRGA Pin Rising Input Source Counter Count Up Enable" "0: Counter count up is disable at the rising edge..,1: Counter count up is enable at the rising edge of.." line.long 0x10 "GTDNSR,General PWM Timer Down Count Source Select Register" bitfld.long 0x10 23. "DSELCH,ELCH Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTH..,1: Counter count down is enable at the ELC_GPTH input" bitfld.long 0x10 22. "DSELCG,ELC_GPTG Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTG..,1: Counter count down is enable at the ELC_GPTG input" newline bitfld.long 0x10 21. "DSELCF,ELC_GPTF Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTF..,1: Counter count down is enable at the ELC_GPTF input" bitfld.long 0x10 20. "DSELCE,ELC_GPTE Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTE..,1: Counter count down is enable at the ELC_GPTE input" newline bitfld.long 0x10 19. "DSELCD,ELC_GPTD Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTD..,1: Counter count down is enable at the ELC_GPTD input" bitfld.long 0x10 18. "DSELCC,ELC_GPTC Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTC..,1: Counter count down is enable at the ELC_GPTC input" newline bitfld.long 0x10 17. "DSELCB,ELC_GPTB Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTB..,1: Counter count down is enable at the ELC_GPTB input" bitfld.long 0x10 16. "DSELCA,ELC_GPTA Event Source Counter Count Down Enable" "0: Counter count down is disable at the ELC_GPTA..,1: Counter count down is enable at the ELC_GPTA input" newline bitfld.long 0x10 15. "DSCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." bitfld.long 0x10 14. "DSCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." newline bitfld.long 0x10 13. "DSCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." bitfld.long 0x10 12. "DSCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." newline bitfld.long 0x10 11. "DSCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." bitfld.long 0x10 10. "DSCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." newline bitfld.long 0x10 9. "DSCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." bitfld.long 0x10 8. "DSCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." newline bitfld.long 0x10 3. "DSGTRGBF,GTETRGB Pin Falling Input Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." bitfld.long 0x10 2. "DSGTRGBR,GTETRGB Pin Rising Input Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." newline bitfld.long 0x10 1. "DSGTRGAF,GTETRGA Pin Falling Input Source Counter Count Down Enable" "0: Counter count down is disable at the falling..,1: Counter count down is enable at the falling edge.." bitfld.long 0x10 0. "DSGTRGAR,GTETRGA Pin Rising Input Source Counter Count Down Enable" "0: Counter count down is disable at the rising edge..,1: Counter count down is enable at the rising edge.." line.long 0x14 "GTICASR,General PWM Timer Input Capture Source Select Register A" bitfld.long 0x14 23. "ASELCH,ELCH Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTH..,1: GTCCRA input capture is enable at the ELC_GPTH.." bitfld.long 0x14 22. "ASELCG,ELC_GPTG Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTG..,1: GTCCRA input capture is enable at the ELC_GPTG.." newline bitfld.long 0x14 21. "ASELCF,ELC_GPTF Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTF..,1: GTCCRA input capture is enable at the ELC_GPTF.." bitfld.long 0x14 20. "ASELCE,ELC_GPTE Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTE..,1: GTCCRA input capture is enable at the ELC_GPTE.." newline bitfld.long 0x14 19. "ASELCD,ELC_GPTD Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTD..,1: GTCCRA input capture is enable at the ELC_GPTD.." bitfld.long 0x14 18. "ASELCC,ELC_GPTC Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTC..,1: GTCCRA input capture is enable at the ELC_GPTC.." newline bitfld.long 0x14 17. "ASELCB,ELC_GPTB Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTB..,1: GTCCRA input capture is enable at the ELC_GPTB.." bitfld.long 0x14 16. "ASELCA,ELC_GPTA Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the ELC_GPTA..,1: GTCCRA input capture is enable at the ELC_GPTA.." newline bitfld.long 0x14 15. "ASCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." bitfld.long 0x14 14. "ASCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." newline bitfld.long 0x14 13. "ASCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." bitfld.long 0x14 12. "ASCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." newline bitfld.long 0x14 11. "ASCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." bitfld.long 0x14 10. "ASCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." newline bitfld.long 0x14 9. "ASCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." bitfld.long 0x14 8. "ASCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." newline bitfld.long 0x14 3. "ASGTRGBF,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." bitfld.long 0x14 2. "ASGTRGBR,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." newline bitfld.long 0x14 1. "ASGTRGAF,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the falling..,1: GTCCRA input capture is enable at the falling.." bitfld.long 0x14 0. "ASGTRGAR,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture is disable at the rising..,1: GTCCRA input capture is enable at the rising.." line.long 0x18 "GTICBSR,General PWM Timer Input Capture Source Select Register B" bitfld.long 0x18 23. "BSELCH,ELCH Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTH..,1: GTCCRB input capture is enable at the ELC_GPTH.." bitfld.long 0x18 22. "BSELCG,ELC_GPTG Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTG..,1: GTCCRB input capture is enable at the ELC_GPTG.." newline bitfld.long 0x18 21. "BSELCF,ELC_GPTF Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTF..,1: GTCCRB input capture is enable at the ELC_GPTF.." bitfld.long 0x18 20. "BSELCE,ELC_GPTE Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTE..,1: GTCCRB input capture is enable at the ELC_GPTE.." newline bitfld.long 0x18 19. "BSELCD,ELC_GPTD Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTD..,1: GTCCRB input capture is enable at the ELC_GPTD.." bitfld.long 0x18 18. "BSELCC,ELC_GPTC Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTC..,1: GTCCRB input capture is enable at the ELC_GPTC.." newline bitfld.long 0x18 17. "BSELCB,ELC_GPTB Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTB..,1: GTCCRB input capture is enable at the ELC_GPTB.." bitfld.long 0x18 16. "BSELCA,ELC_GPTA Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the ELC_GPTA..,1: GTCCRB input capture is enable at the ELC_GPTA.." newline bitfld.long 0x18 15. "BSCBFAH,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." bitfld.long 0x18 14. "BSCBFAL,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." newline bitfld.long 0x18 13. "BSCBRAH,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." bitfld.long 0x18 12. "BSCBRAL,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." newline bitfld.long 0x18 11. "BSCAFBH,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." bitfld.long 0x18 10. "BSCAFBL,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." newline bitfld.long 0x18 9. "BSCARBH,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." bitfld.long 0x18 8. "BSCARBL,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." newline bitfld.long 0x18 3. "BSGTRGBF,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." bitfld.long 0x18 2. "BSGTRGBR,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." newline bitfld.long 0x18 1. "BSGTRGAF,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the falling..,1: GTCCRB input capture is enable at the falling.." bitfld.long 0x18 0. "BSGTRGAR,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture is disable at the rising..,1: GTCCRB input capture is enable at the rising.." line.long 0x1C "GTCR,General PWM Timer Control Register" bitfld.long 0x1C 24.--26. "TPCS,Timer Prescaler Select" "0: Setting prohibied,1: PCLK/4,?,?,?,?,?,?" hexmask.long.byte 0x1C 19.--23. 1. "Reserved,These bits are read as 00000. The write value should be 00000." newline bitfld.long 0x1C 16.--18. "MD,Mode Select" "0: Saw-wave PWM mode (single buffer or double..,1: Saw-wave one-shot pulse mode (fixed buffer..,?,?,?,?,?,?" hexmask.long.word 0x1C 1.--15. 1. "Reserved,These bits are read as 000000000000000. The write value should be 000000000000000." newline bitfld.long 0x1C 0. "CST,Count Start" "0: Count operation is stopped,1: Count operation is performed" line.long 0x20 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register" bitfld.long 0x20 27. "OBDTYR,GTIOCB Output Value Selecting after Releasing 0 percent/100 percent Duty Setting" "0: Apply output value set in 0 percent/100 percent..,1: Apply masked compare match output value to.." bitfld.long 0x20 26. "OBDTYF,Forcible GTIOCB Output Duty Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x20 24.--25. "OBDTY,GTIOCB Output Duty Setting" "0: GTIOCB pin duty is depend on compare match,1: GTIOCB pin duty is depend on compare match,?,?" hexmask.long.byte 0x20 20.--23. 1. "Reserved,These bits are read as 0000. The write value should be 0000." newline bitfld.long 0x20 19. "OADTYR,GTIOCA Output Value Selecting after Releasing 0 percent/100 percent Duty Setting" "0: Apply output value set in 0 percent/100 percent..,1: Apply masked compare match output value to.." bitfld.long 0x20 18. "OADTYF,Forcible GTIOCA Output Duty Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x20 16.--17. "OADTY,GTIOCA Output Duty Setting" "0: GTIOCA pin duty is depend on compare match,1: GTIOCA pin duty is depend on compare match,?,?" bitfld.long 0x20 1. "UDF,Forcible Count Direction Setting" "0: Not forcibly set,1: Forcibly set" newline bitfld.long 0x20 0. "UD,Count Direction Setting" "0: GTCNT counts down.,1: GTCNT counts up." line.long 0x24 "GTIOR,General PWM Timer I/O Control Register" bitfld.long 0x24 30.--31. "NFCSB,Noise Filter B Sampling Clock Select" "0: PCLK/1,1: PCLK/4,?,?" bitfld.long 0x24 29. "NFBEN,Noise Filter B Enable" "0: The noise filter for the GTIOCB pin is disabled.,1: The noise filter for the GTIOCB pin is enabled." newline bitfld.long 0x24 27.--28. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.long 0x24 25.--26. "OBDF,GTIOCB Pin Disable Value Setting" "0: Output disable is prohibited.,1: GTIOCB pin is set to Hi-Z when output disable is..,?,?" newline bitfld.long 0x24 24. "OBE,GTIOCB Pin Output Enable" "0: Output is disabled,1: Output is enabled" bitfld.long 0x24 23. "OBHLD,GTIOCB Pin Output Setting at the Start/Stop Count" "0: The GTIOCB pin output level at start/stop of..,1: The GTIOCB pin output level is retained at.." newline bitfld.long 0x24 22. "OBDFLT,GTIOCB Pin Output Value Setting at the Count Stop" "0: The GTIOCB pin outputs low when counting is..,1: The GTIOCB pin outputs high when counting is.." bitfld.long 0x24 21. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline hexmask.long.byte 0x24 16.--20. 1. "GTIOB,GTIOCB Pin Function Select" bitfld.long 0x24 14.--15. "NFCSA,Noise Filter A Sampling Clock Select" "0: PCLK/1,1: PCLK/4,?,?" newline bitfld.long 0x24 13. "NFAEN,Noise Filter A Enable" "0: The noise filter for the GTIOCA pin is disabled.,1: The noise filter for the GTIOCA pin is enabled." bitfld.long 0x24 11.--12. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" newline bitfld.long 0x24 9.--10. "OADF,GTIOCA Pin Disable Value Setting" "0: Output disable is prohibited.,1: GTIOCA pin is set to Hi-Z when output disable is..,?,?" bitfld.long 0x24 8. "OAE,GTIOCA Pin Output Enable" "0: Output is disabled,1: Output is enabled" newline bitfld.long 0x24 7. "OAHLD,GTIOCA Pin Output Setting at the Start/Stop Count" "0: The GTIOCA pin output level at start/stop of..,1: The GTIOCA pin output level is retained at.." bitfld.long 0x24 6. "OADFLT,GTIOCA Pin Output Value Setting at the Count Stop" "0: The GTIOCA pin outputs low when counting is..,1: The GTIOCA pin outputs high when counting is.." newline bitfld.long 0x24 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" hexmask.long.byte 0x24 0.--4. 1. "GTIOA,GTIOCA Pin Function Select" line.long 0x28 "GTINTAD,General PWM Timer Interrupt Output Setting Register" bitfld.long 0x28 30. "GRPABL,Same Time Output Level Low Disable Request Enable" "0: Same time output level low disable request is..,1: Same time output level low disable request is.." bitfld.long 0x28 29. "GRPABH,Same Time Output Level High Disable Request Enable" "0: Same time output level high disable request is..,1: Same time output level high disable request is.." newline bitfld.long 0x28 26.--28. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.long 0x28 24.--25. "GRP,Output Disable Source Select" "0: Setting prohibited,1: Group B output disable request,?,?" newline hexmask.long.tbyte 0x28 0.--23. 1. "Reserved,These bits are read as 000000000000000000000000. The write value should be 000000000000000000000000." line.long 0x2C "GTST,General PWM Timer Status Register" rbitfld.long 0x2C 30. "OABLF,Same Time Output Level Low Disable Request Enable" "0: GTIOCA pin and GTIOCB pin don't output 0 at the..,1: GTIOCA pin and GTIOCB pin output 0 at the same.." rbitfld.long 0x2C 29. "OABHF,Same Time Output Level High Disable Request Enable" "0: GTIOCA pin and GTIOCB pin don't output 1 at the..,1: GTIOCA pin and GTIOCB pin output 1 at the same.." newline hexmask.long.byte 0x2C 25.--28. 1. "Reserved,These bits are read as 0000. The write value should be 0000." rbitfld.long 0x2C 24. "ODF,Output Disable Flag" "0: No output disable request is generated.,1: An output disable request is generated." newline hexmask.long.byte 0x2C 16.--23. 1. "Reserved,These bits are read as 00000000. The write value should be 00000000." rbitfld.long 0x2C 15. "TUCF,Count Direction Flag" "0: The GTCNT counter counts downward.,1: The GTCNT counter counts upward." newline hexmask.long.byte 0x2C 8.--14. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.long 0x2C 7. "TCFPU,Underflow Flag" "0: No underflow (trough) has occurred.,1: An underflow (trough) has occurred." newline bitfld.long 0x2C 6. "TCPFO,Overflow Flag" "0: No overflow (crest) has occurred.,1: An overflow (crest) has occurred." bitfld.long 0x2C 5. "TCFF,Input Compare Match Flag F" "0: No compare match of GTCCRF is generated.,1: A compare match of GTCCRF is generated." newline bitfld.long 0x2C 4. "TCFE,Input Compare Match Flag E" "0: No compare match of GTCCRE is generated.,1: A compare match of GTCCRE is generated." bitfld.long 0x2C 3. "TCFD,Input Compare Match Flag D" "0: No compare match of GTCCRD is generated.,1: A compare match of GTCCRD is generated." newline bitfld.long 0x2C 2. "TCFC,Input Compare Match Flag C" "0: No compare match of GTCCRC is generated.,1: A compare match of GTCCRC is generated." bitfld.long 0x2C 1. "TCFB,Input Capture/Compare Match Flag B" "0: No input capture/compare match of GTCCRB is..,1: An input capture/compare match of GTCCRB is.." newline bitfld.long 0x2C 0. "TCFA,Input Capture/Compare Match Flag A" "0: No input capture/compare match of GTCCRA is..,1: An input capture/compare match of GTCCRA is.." line.long 0x30 "GTBER,General PWM Timer Buffer Enable Register" bitfld.long 0x30 22. "CCRSWT,GTCCRA and GTCCRB Forcible Buffer OperationThis bit is read as 0." "0: no effect,1: Forcibly performs buffer transfer of GTCCRA and.." bitfld.long 0x30 20.--21. "PR,GTPR Buffer Operation" "0: Setting prohibited,1: Single buffer operation (GTPBR --> GTPR),?,?" newline bitfld.long 0x30 18.--19. "CCRB,GTCCRB Buffer Operation" "0: Buffer operation is not performed,1: Single buffer operation (GTCCRB <--> GTCCRE),?,?" bitfld.long 0x30 16.--17. "CCRA,GTCCRA Buffer Operation" "0: Buffer operation is not performed,1: Single buffer operation (GTCCRA <--> GTCCRC),?,?" newline bitfld.long 0x30 0.--1. "BD,BD[1]: GTPR Buffer Operation DisableBD[0]: GTCCR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled,?,?" group.long 0x48++0x23 line.long 0x0 "GTCNT,General PWM Timer Counter" hexmask.long 0x0 0.--31. 1. "GTCNT,Counter" line.long 0x4 "GTCCRA,General PWM Timer Compare Capture Register A" hexmask.long 0x4 0.--31. 1. "GTCCRA,Compare Capture Register A" line.long 0x8 "GTCCRB,General PWM Timer Compare Capture Register B" hexmask.long 0x8 0.--31. 1. "GTCCRB,Compare Capture Register B" line.long 0xC "GTCCRC,General PWM Timer Compare Capture Register C" hexmask.long 0xC 0.--31. 1. "GTCCRC,Compare Capture Register C" line.long 0x10 "GTCCRE,General PWM Timer Compare Capture Register E" hexmask.long 0x10 0.--31. 1. "GTCCRE,Compare Capture Register E" line.long 0x14 "GTCCRD,General PWM Timer Compare Capture Register D" hexmask.long 0x14 0.--31. 1. "GTCCRD,Compare Capture Register D" line.long 0x18 "GTCCRF,General PWM Timer Compare Capture Register F" hexmask.long 0x18 0.--31. 1. "GTCCRF,Compare Capture Register F" line.long 0x1C "GTPR,General PWM Timer Cycle Setting Register" hexmask.long 0x1C 0.--31. 1. "GTPR,Cycle Setting Register" line.long 0x20 "GTPBR,General PWM Timer Cycle Setting Buffer Register" hexmask.long 0x20 0.--31. 1. "GTPBR,Cycle Setting Buffer Register" group.long 0x88++0x7 line.long 0x0 "GTDTCR,General PWM Timer Dead Time Control Register" hexmask.long.tbyte 0x0 9.--31. 1. "Reserved,These bits are read as 00000000000000000000000. The write value should be 00000000000000000000000." bitfld.long 0x0 8. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.long 0x0 6.--7. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.long 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.long 0x0 4. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 1.--3. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "TDE,Negative-Phase Waveform Setting" "0: GTCCRB is set without using GTDVU and GTDVD.,1: GTDVU and GTDVD are used to set the compare.." line.long 0x4 "GTDVU,General PWM Timer Dead Time Value Register U" hexmask.long 0x4 0.--31. 1. "GTDVU,Dead Time Value Register U" tree.end tree "GPT_OPS" base ad:0x40078FF0 group.long 0x0++0x3 line.long 0x0 "OPSCR,Output Phase Switching Control Register" bitfld.long 0x0 30.--31. "NFCS,External Input Noise Filter Clock selectionNoise filter sampling clock setting of the external input." "0: PCLK/1,1: PCLK/4,?,?" bitfld.long 0x0 29. "NFEN,External Input Noise Filter Enable" "0: Do not use a noise filter to the external input.,1: Use a noise filter to the external input." newline bitfld.long 0x0 27.--28. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.long 0x0 26. "GODF,Group output disable function" "0: This bit function is ignored.,1: Group disable will clear OPSCR.EN Bit." newline bitfld.long 0x0 24.--25. "GRP,Output disabled source selection" "0: Setting prohibited,1: Select Group B output disable source,?,?" bitfld.long 0x0 22.--23. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" newline bitfld.long 0x0 21. "ALIGN,Input phase alignment" "0: Input phase is aligned to PCLK.,1: Input phase is aligned PWM." bitfld.long 0x0 20. "RV,Output phase rotation direction reversal" "0: U/V/W-Phase output,1: Output to reverse the V / W-phase" newline bitfld.long 0x0 19. "INV,Invert-Phase Output Control" "0: Positive Logic (Active High)output,1: Negative Logic (Active Low)output" bitfld.long 0x0 18. "N,Negative-Phase Output (N) Control" "0: Level signal output,1: PWM signal output (PWM of GPT0)" newline bitfld.long 0x0 17. "P,Positive-Phase Output (P) Control" "0: Level signal output,1: PWM signal output (PWM of GPT0)" bitfld.long 0x0 16. "FB,External Feedback Signal EnableThis bit selects the input phase from the software settings and external input." "0: Select the external input.,1: Select the soft setting(OPSCR.UF VF WF)." newline hexmask.long.byte 0x0 9.--15. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.long 0x0 8. "EN,Enable-Phase Output Control" "0: Not Output(Hi-Z external terminals).,1: Output" newline bitfld.long 0x0 7. "Reserved,This bit is read as 0. The write value should be 0." "0,1" rbitfld.long 0x0 6. "W,Input W-Phase MonitorThis bit monitors the state of the input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Software settings (UF/VF/WF)" "0: External input monitoring by PCLKOPSCR,1: Software settings" newline rbitfld.long 0x0 5. "V,Input V-Phase MonitorThis bit monitors the state of the input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Software settings (UF/VF/WF)" "0: External input monitoring by PCLKOPSCR,1: Software settings" rbitfld.long 0x0 4. "U,Input U-Phase MonitorThis bit monitors the state of the input phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Software settings (UF/VF/WF)" "0: External input monitoring by PCLKOPSCR,1: Software settings" newline bitfld.long 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 2. "WF,Input Phase Soft Setting UFThis bit sets the input phase by the software settings.This bit setting is valid when the OPSCR.FB bit = 1." "0,1" newline bitfld.long 0x0 1. "VF,Input Phase Soft Setting VFThis bit sets the input phase by the software settings.This bit setting is valid when the OPSCR.FB bit = 1." "0,1" bitfld.long 0x0 0. "UF,Input Phase Soft Setting WFThis bit sets the input phase by the software settings.This bit setting is valid when the OPSCR.FB bit = 1." "0,1" tree.end tree.end tree "ICU (Interrupt Controller Unit)" base ad:0x40006000 repeat 16. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2)++0x0 line.byte 0x0 "IRQCR$1,IRQ Control Register %s" bitfld.byte 0x0 7. "FLTEN,IRQ Digital Filter Enable" "0: Digital filter disabled.,1: Digital filter enabled." bitfld.byte 0x0 6. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.byte 0x0 4.--5. "FCLKSEL,IRQ Digital Filter Sampling Clock Select" "0: PCLKB,1: PCLKB/8,?,?" bitfld.byte 0x0 2.--3. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" newline bitfld.byte 0x0 0.--1. "IRQMD,IRQ Detection Sense Select" "0: Falling edge,1: Rising edge,?,?" repeat.end rgroup.word 0x140++0x1 line.word 0x0 "NMISR,Non-Maskable Interrupt Status Register" bitfld.word 0x0 13.--15. "Reserved,These bits are read as 000." "0,1,2,3,4,5,6,7" bitfld.word 0x0 12. "SPEST,CPU Stack pointer monitor Interrupt Status Flag" "0: Interrupt not requested,1: Interrupt requested." newline bitfld.word 0x0 11. "BUSMST,MPU Bus Master Error Interrupt Status Flag" "0: Interrupt not requested,1: Interrupt requested." bitfld.word 0x0 10. "BUSSST,MPU Bus Slave Error Interrupt Status Flag" "0: Interrupt not requested,1: Interrupt requested." newline bitfld.word 0x0 9. "RECCST,RAM ECC Error Interrupt Status Flag" "0: Interrupt not requested,1: Interrupt requested." bitfld.word 0x0 8. "RPEST,RAM Parity Error Interrupt Status Flag" "0: Interrupt not requested,1: Interrupt requested." newline bitfld.word 0x0 7. "NMIST,NMI Status Flag" "0: Interrupt not requested,1: Interrupt requested." bitfld.word 0x0 6. "OSTST,Oscillation Stop Detection Interrupt Status Flag" "0: Interrupt not requested for main oscillation stop,1: Interrupt requested for main oscillation stop." newline bitfld.word 0x0 5. "Reserved,This bit is read as 0." "0,1" bitfld.word 0x0 4. "VBATTST,VBATT monitor Interrupt Status Flag" "0: Interrupt not requested,1: Interrupt requested." newline bitfld.word 0x0 3. "LVD2ST,Voltage-Monitoring 2 Interrupt Status Flag" "0: Interrupt not requested,1: Interrupt requested." bitfld.word 0x0 2. "LVD1ST,Voltage-Monitoring 1 Interrupt Status Flag" "0: Interrupt not requested,1: Interrupt requested." newline bitfld.word 0x0 1. "WDTST,WDT Underflow/Refresh Error Status Flag" "0: Interrupt not requested,1: Interrupt requested." bitfld.word 0x0 0. "IWDTST,IWDT Underflow/Refresh Error Status Flag" "0: Interrupt not requested,1: Interrupt requested." group.word 0x120++0x1 line.word 0x0 "NMIER,Non-Maskable Interrupt Enable Register" bitfld.word 0x0 13.--15. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.word 0x0 12. "SPEEN,CPU Stack pointer monitor Interrupt Enable" "0: Disabled,1: Enabled." newline bitfld.word 0x0 11. "BUSMEN,MPU Bus Master Error Interrupt Enable" "0: Disabled,1: Enabled." bitfld.word 0x0 10. "BUSSEN,MPU Bus Slave Error Interrupt Enable" "0: Disabled,1: Enabled." newline bitfld.word 0x0 9. "RECCEN,RAM ECC Error Interrupt Enable" "0: Disabled,1: Enabled." bitfld.word 0x0 8. "RPEEN,RAM Parity Error Interrupt Enable" "0: Disabled,1: Enabled." newline bitfld.word 0x0 7. "NMIEN,NMI Pin Interrupt Enable" "0: Disabled,1: Enabled." bitfld.word 0x0 6. "OSTEN,Oscillation Stop Detection Interrupt Enable" "0: Disabled,1: Enabled." newline bitfld.word 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x0 4. "VBATTEN,VBATT monitor Interrupt Enable" "0: Disabled,1: Enabled." newline bitfld.word 0x0 3. "LVD2EN,Voltage-Monitoring 2 Interrupt Enable" "0: Disabled,1: Enabled." bitfld.word 0x0 2. "LVD1EN,Voltage-Monitoring 1 Interrupt Enable" "0: Disabled,1: Enabled." newline bitfld.word 0x0 1. "WDTEN,WDT Underflow/Refresh Error Interrupt Enable" "0: Disabled,1: Enabled." bitfld.word 0x0 0. "IWDTEN,IWDT Underflow/Refresh Error Interrupt Enable" "0: Disabled,1: Enabled." group.word 0x130++0x1 line.word 0x0 "NMICLR,Non-Maskable Interrupt Status Clear Register" bitfld.word 0x0 13.--15. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.word 0x0 12. "SPECLR,CPU Stack Pointer Monitor Interrupt Clear" "0: No effect.,1: Clear the NMISR.SPEST flag." newline bitfld.word 0x0 11. "BUSMCLR,Bus Master Error Clear" "0: No effect.,1: Clear the NMISR.BUSMST flag." bitfld.word 0x0 10. "BUSSCLR,Bus Slave Error Clear" "0: No effect.,1: Clear the NMISR.BUSSST flag." newline bitfld.word 0x0 9. "RECCCLR,SRAM ECC Error Clear" "0: No effect.,1: Clear the NMISR.RECCST flag." bitfld.word 0x0 8. "RPECLR,SRAM Parity Error Clear" "0: No effect.,1: Clear the NMISR.RPEST flag." newline bitfld.word 0x0 7. "NMICLR,NMI Clear" "0: No effect.,1: Clear the NMISR.NMIST flag." bitfld.word 0x0 6. "OSTCLR,OST Clear" "0: No effect.,1: Clear the NMISR.OSTST flag." newline bitfld.word 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x0 4. "VBATTCLR,VBATT Clear" "0: No effect.,1: Clear the NMISR.VBATTST flag." newline bitfld.word 0x0 3. "LVD2CLR,LVD2 Clear" "0: No effect.,1: Clear the NMISR.LVD2ST flag." bitfld.word 0x0 2. "LVD1CLR,LVD1 Clear" "0: No effect.,1: Clear the NMISR.LVD1ST flag." newline bitfld.word 0x0 1. "WDTCLR,WDT Clear" "0: No effect.,1: Clear the NMISR.WDTST flag." bitfld.word 0x0 0. "IWDTCLR,IWDT Clear" "0: No effect.,1: Clear the NMISR.IWDTST flag." group.byte 0x100++0x0 line.byte 0x0 "NMICR,NMI Pin Interrupt Control Register" bitfld.byte 0x0 7. "NFLTEN,NMI Digital Filter Enable" "0: Digital filter is disabled.,1: Digital filter is enabled." bitfld.byte 0x0 6. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.byte 0x0 4.--5. "NFCLKSEL,NMI Digital Filter Sampling Clock Select" "0: PCLKB,1: PCLKB/8,?,?" bitfld.byte 0x0 1.--3. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" newline bitfld.byte 0x0 0. "NMIMD,NMI Detection Set" "0: Falling edge,1: Rising edge" repeat 32. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x300)++0x3 line.long 0x0 "IELSR$1,ICU Event Link Setting Register %s" hexmask.long.byte 0x0 25.--31. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.long 0x0 24. "DTCE,DTC Activation Enable" "0: DTC activation is disabled,1: DTC activation is enabled" newline hexmask.long.byte 0x0 17.--23. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.long 0x0 16. "IR,Interrupt Status Flag" "0: No interrupt request is generated,1: An interrupt request is generated ( 1 write to.." newline hexmask.long.byte 0x0 8.--15. 1. "Reserved,These bits are read as 00000000. The write value should be 00000000." hexmask.long.byte 0x0 0.--7. 1. "IELS,ICU Event selection to NVICSet the number for the event signal to be linked ." repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x280)++0x1 line.word 0x0 "DELSR$1,DMAC Event Link Setting Register %s" hexmask.word.byte 0x0 8.--15. 1. "Reserved,These bits are read as 00000000. The write value should be 00000000." hexmask.word.byte 0x0 0.--7. 1. "DELS,Event selection to DMAC Start request" repeat.end group.word 0x200++0x1 line.word 0x0 "SELSR0,Snooze Event Link Setting Register" hexmask.word.byte 0x0 8.--15. 1. "Reserved,These bits are read as 00000000. The write value should be 00000000." hexmask.word.byte 0x0 0.--7. 1. "SELS,SYS Event Link Select" group.long 0x1A0++0x3 line.long 0x0 "WUPEN,Wake Up Interrupt Enable Register" bitfld.long 0x0 31. "IIC0WUPEN,IIC0 address match interrupt S/W standby returns enable" "0: S/W standby returns by IIC0 address match..,1: S/W standby returns by IIC0 address match.." bitfld.long 0x0 30. "AGT1CBWUPEN,AGT1 compare match B interrupt S/W standby returns enable" "0: S/W standby returns by AGT1 compare match B..,1: S/W standby returns by AGT1 compare match B.." newline bitfld.long 0x0 29. "AGT1CAWUPEN,AGT1 compare match A interrupt S/W standby returns enable" "0: S/W standby returns by AGT1 compare match A..,1: S/W standby returns by AGT1 compare match A.." bitfld.long 0x0 28. "AGT1UDWUPEN,AGT1 underflow interrupt S/W standby returns enable" "0: S/W standby returns by AGT1 underflow interrupt..,1: S/W standby returns by AGT1 underflow interrupt.." newline bitfld.long 0x0 27. "USBFSWUPEN,USBFS interrupt S/W standby returns enable" "0: S/W standby returns by USBFS interrupt is disabled,1: S/W standby returns by USBFS interrupt is enabled" bitfld.long 0x0 26. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.long 0x0 25. "RTCPRDWUPEN,RCT period interrupt S/W standby returns enable" "0: S/W standby returns by RTC period interrupt is..,1: S/W standby returns by RTC period interrupt is.." bitfld.long 0x0 24. "RTCALMWUPEN,RTC alarm interrupt S/W standby returns enable" "0: S/W standby returns by RTC alarm interrupt is..,1: S/W standby returns by RTC alarm interrupt is.." newline bitfld.long 0x0 23. "ACMPLP0WUPEN,ACMPLP0 interrupt S/W standby returns enable" "0: S/W standby returns by ACMPLP0 interrupt is..,1: S/W standby returns by ACMPLP0 interrupt is.." bitfld.long 0x0 21.--22. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" newline bitfld.long 0x0 20. "VBATTWUPEN,VBATT monitor interrupt S/W standby returns enable" "0: S/W standby returns by VBATT monitor interrupt..,1: S/W standby returns by VBATT monitor interrupt.." bitfld.long 0x0 19. "LVD2WUPEN,LVD2 interrupt S/W standby returns enable" "0: S/W standby returns by LVD2 interrupt is disabled,1: S/W standby returns by LVD2 interrupt is enabled" newline bitfld.long 0x0 18. "LVD1WUPEN,LVD1 interrupt S/W standby returns enable" "0: S/W standby returns by LVD1 interrupt is disabled,1: S/W standby returns by LVD1 interrupt is enabled" bitfld.long 0x0 17. "KEYWUPEN,Key interrupt S/W standby returns enable" "0: S/W standby returns by KEY interrupt is disabled,1: S/W standby returns by KEY interrupt is enabled" newline bitfld.long 0x0 16. "IWDTWUPEN,IWDT interrupt S/W standby returns enable" "0: S/W standby returns by IWDT interrupt is disabled,1: S/W standby returns by IWDT interrupt is enabled" bitfld.long 0x0 15. "IRQWUPEN15,IRQ15 interrupt S/W standby returns enable" "0: S/W standby returns by IRQ15 interrupt is disabled,1: S/W standby returns by IRQ15 interrupt is enabled" newline bitfld.long 0x0 14. "IRQWUPEN14,IRQ14 interrupt S/W standby returns enable" "0: S/W standby returns by IRQ14 interrupt is disabled,1: S/W standby returns by IRQ14 interrupt is enabled" bitfld.long 0x0 13. "IRQWUPEN13,IRQ13 interrupt S/W standby returns enable" "0: S/W standby returns by IRQ13 interrupt is disabled,1: S/W standby returns by IRQ13 interrupt is enabled" newline bitfld.long 0x0 12. "IRQWUPEN12,IRQ12 interrupt S/W standby returns enable" "0: S/W standby returns by IRQ12 interrupt is disabled,1: S/W standby returns by IRQ12 interrupt is enabled" bitfld.long 0x0 11. "IRQWUPEN11,IRQ11 interrupt S/W standby returns enable" "0: S/W standby returns by IRQ11 interrupt is disabled,1: S/W standby returns by IRQ11 interrupt is enabled" newline bitfld.long 0x0 10. "IRQWUPEN10,IRQ10 interrupt S/W standby returns enable" "0: S/W standby returns by IRQ10 interrupt is disabled,1: S/W standby returns by IRQ10 interrupt is enabled" bitfld.long 0x0 9. "IRQWUPEN9,IRQ9 interrupt S/W standby returns enable" "0: S/W standby returns by IRQ9 interrupt is disabled,1: S/W standby returns by IRQ9 interrupt is enabled" newline bitfld.long 0x0 8. "IRQWUPEN8,IRQ8 interrupt S/W standby returns enable" "0: S/W standby returns by IRQ8 interrupt is disabled,1: S/W standby returns by IRQ8 interrupt is enabled" bitfld.long 0x0 7. "IRQWUPEN7,IRQ7 interrupt S/W standby returns enable" "0: S/W standby returns by IRQ7 interrupt is disabled,1: S/W standby returns by IRQ7 interrupt is enabled" newline bitfld.long 0x0 6. "IRQWUPEN6,IRQ6 interrupt S/W standby returns enable" "0: S/W standby returns by IRQ6 interrupt is disabled,1: S/W standby returns by IRQ6 interrupt is enabled" bitfld.long 0x0 5. "IRQWUPEN5,IRQ5 interrupt S/W standby returns enable" "0: S/W standby returns by IRQ5 interrupt is disabled,1: S/W standby returns by IRQ5 interrupt is enabled" newline bitfld.long 0x0 4. "IRQWUPEN4,IRQ4 interrupt S/W standby returns enable" "0: S/W standby returns by IRQ4 interrupt is disabled,1: S/W standby returns by IRQ4 interrupt is enabled" bitfld.long 0x0 3. "IRQWUPEN3,IRQ3 interrupt S/W standby returns enable" "0: S/W standby returns by IRQ3 interrupt is disabled,1: S/W standby returns by IRQ3 interrupt is enabled" newline bitfld.long 0x0 2. "IRQWUPEN2,IRQ2 interrupt S/W standby returns enable" "0: S/W standby returns by IRQ2 interrupt is disabled,1: S/W standby returns by IRQ2 interrupt is enabled" bitfld.long 0x0 1. "IRQWUPEN1,IRQ1 interrupt S/W standby returns enable" "0: S/W standby returns by IRQ1 interrupt is disabled,1: S/W standby returns by IRQ1 interrupt is enabled" newline bitfld.long 0x0 0. "IRQWUPEN0,IRQ0 interrupt S/W standby returns enable" "0: S/W standby returns by IRQ0 interrupt is disabled,1: S/W standby returns by IRQ0 interrupt is enabled" tree.end tree "IIC (Inter-Integrated Circuit)" base ad:0x0 tree "IIC0" base ad:0x40053000 group.byte 0x0++0x9 line.byte 0x0 "ICCR1,I2C Bus Control Register 1" bitfld.byte 0x0 7. "ICE,I2C Bus Interface Enable" "0: Disable (SCLn and SDAn pins in inactive state),1: Enable (SCLn and SDAn pins in active state)" bitfld.byte 0x0 6. "IICRST,I2C Bus Interface Internal ResetNote:If an internal reset is initiated using the IICRST bit for a bus hang-up occurred during communication with the master device in slave mode the states may become different between the slave device and the.." "0: Releases the RIIC reset or internal reset.,1: Initiates the RIIC reset or internal reset." newline bitfld.byte 0x0 5. "CLO,Extra SCL Clock Cycle Output" "0: Does not output an extra SCL clock cycle.,1: Outputs an extra SCL clock cycle." bitfld.byte 0x0 4. "SOWP,SCLO/SDAO Write Protect" "0: Bits SCLO and SDAO can be written,1: Bits SCLO and SDAO are protected." newline bitfld.byte 0x0 3. "SCLO,SCL Output Control/Monitor" "0: (Read)The RIIC has driven the SCLn pin low. /..,1: (Read)The RIIC has released the SCLn pin. /.." bitfld.byte 0x0 2. "SDAO,SDA Output Control/Monitor" "0: (Read)The RIIC has driven the SDAn pin low. /..,1: (Read)The RIIC has released the SDAn pin./.." newline rbitfld.byte 0x0 1. "SCLI,SCL Line Monitor" "0: SCLn line is low.,1: SCLn line is high." rbitfld.byte 0x0 0. "SDAI,SDA Line Monitor" "0: SDAn line is low.,1: SDAn line is high." line.byte 0x1 "ICCR2,I2C Bus Control Register 2" rbitfld.byte 0x1 7. "BBSY,Bus Busy Detection Flag" "0: The I2C bus is released (bus free state).,1: The I2C bus is occupied (bus busy state)." bitfld.byte 0x1 6. "MST,Master/Slave Mode" "0: Slave mode,1: Master mode" newline bitfld.byte 0x1 5. "TRS,Transmit/Receive Mode" "0: Receive mode,1: Transmit mode" bitfld.byte 0x1 4. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.byte 0x1 3. "SP,Stop Condition Issuance RequestNote: Writing to the SP bit is not possible while the setting of the BBSY flag is 0 (bus free state).Note: Do not set the SP bit to 1 while a restart condition is being issued." "0: Does not request to issue a stop condition.,1: Requests to issue a stop condition." bitfld.byte 0x1 2. "RS,Restart Condition Issuance RequestNote: Do not set the RS bit to 1 while issuing a stop condition." "0: Does not request to issue a restart condition.,1: Requests to issue a restart condition." newline bitfld.byte 0x1 1. "ST,Start Condition Issuance RequestSet the ST bit to 1 (start condition issuance request) when the BBSY flag is set to 0 (bus free state)." "0: Does not request to issue a start condition.,1: Requests to issue a start condition." bitfld.byte 0x1 0. "Reserved,This bit is read as 0. The write value should be 0." "0,1" line.byte 0x2 "ICMR1,I2C Bus Mode Register 1" bitfld.byte 0x2 7. "MTWP,MST/TRS Write Protect" "0: Disables writing to the MST and TRS bits in ICCR2.,1: Enables writing to the MST and TRS bits in ICCR2." bitfld.byte 0x2 4.--6. "CKS,Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB / 2^CKS )" "0: PCLKB/1 clock,1: PCLKB/2 clock,?,?,?,?,?,?" newline bitfld.byte 0x2 3. "BCWP,BC Write Protect(This bit is read as 1.)" "0: Enables a value to be written in the BC[2:0] bits.,1: Disables a value to be written in the BC[2:0].." bitfld.byte 0x2 0.--2. "BC,Bit Counter" "0: 9 bits,1: 2 bits,?,?,?,?,?,?" line.byte 0x3 "ICMR2,I2C Bus Mode Register 2" bitfld.byte 0x3 7. "DLCS,SDA Output Delay Clock Source Select" "0: The internal reference clock (fIIC) is selected..,1: The internal reference clock divided by 2.." bitfld.byte 0x3 4.--6. "SDDL,SDA Output Delay Counter" "0: No output delay,1: 1 fIIC cycle (ICMR2.DLCS=0) / 1 or 2 fIIC cycles..,?,?,?,?,?,?" newline bitfld.byte 0x3 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x3 2. "TMOH,Timeout H Count Control" "0: Count is disabled while the SCLn line is at a..,1: Count is enabled while the SCLn line is at a.." newline bitfld.byte 0x3 1. "TMOL,Timeout L Count Control" "0: Count is disabled while the SCLn line is at a..,1: Count is enabled while the SCLn line is at a low.." bitfld.byte 0x3 0. "TMOS,Timeout Detection Time Select" "0: Long mode is selected.,1: Short mode is selected." line.byte 0x4 "ICMR3,I2C Bus Mode Register 3" bitfld.byte 0x4 7. "SMBS,SMBus/I2C Bus Selection" "0: The I2C bus is selected.,1: The SMBus is selected." bitfld.byte 0x4 6. "WAIT,WAITNote: When the value of the WAIT bit is to be read be sure to read the ICDRR beforehand." "0: No WAIT (The period between ninth clock cycle..,1: WAIT (The period between ninth clock cycle and.." newline bitfld.byte 0x4 5. "RDRFS,RDRF Flag Set Timing Selection" "0: The RDRF flag is set at the rising edge of the..,1: The RDRF flag is set at the rising edge of the.." bitfld.byte 0x4 4. "ACKWP,ACKBT Write Protect" "0: Modification of the ACKBT bit is disabled.,1: Modification of the ACKBT bit is enabled." newline bitfld.byte 0x4 3. "ACKBT,Transmit Acknowledge" "0: A 0 is sent as the acknowledge bit (ACK..,1: A 1 is sent as the acknowledge bit (NACK.." rbitfld.byte 0x4 2. "ACKBR,Receive Acknowledge" "0: A 0 is received as the acknowledge bit (ACK..,1: A 1 is received as the acknowledge bit (NACK.." newline bitfld.byte 0x4 0.--1. "NF,Noise Filter Stage Selection" "0: Noise of up to one fIIC cycle is filtered out..,1: Noise of up to two fIIC cycles is filtered out..,?,?" line.byte 0x5 "ICFER,I2C Bus Function Enable Register" bitfld.byte 0x5 7. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x5 6. "SCLE,SCL Synchronous Circuit Enable" "0: No SCL synchronous circuit is used.,1: An SCL synchronous circuit is used." newline bitfld.byte 0x5 5. "NFE,Digital Noise Filter Circuit Enable" "0: No digital noise filter circuit is used.,1: A digital noise filter circuit is used." bitfld.byte 0x5 4. "NACKE,NACK Reception Transfer Suspension Enable" "0: Transfer operation is not suspended during NACK..,1: Transfer operation is suspended during NACK.." newline bitfld.byte 0x5 3. "SALE,Slave Arbitration-Lost Detection Enable" "0: Slave arbitration-lost detection is disabled.,1: Slave arbitration-lost detection is enabled." bitfld.byte 0x5 2. "NALE,NACK Transmission Arbitration-Lost Detection Enable" "0: NACK transmission arbitration-lost detection is..,1: NACK transmission arbitration-lost detection is.." newline bitfld.byte 0x5 1. "MALE,Master Arbitration-Lost Detection Enable" "0: Master arbitration-lost detection is disabled.,1: Master arbitration-lost detection is enabled." bitfld.byte 0x5 0. "TMOE,Timeout Function Enable" "0: The timeout function is disabled.,1: The timeout function is enabled." line.byte 0x6 "ICSER,I2C Bus Status Enable Register" bitfld.byte 0x6 7. "HOAE,Host Address Enable" "0: Host address detection is disabled.,1: Host address detection is enabled." bitfld.byte 0x6 6. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.byte 0x6 5. "DIDE,Device-ID Address Detection Enable" "0: Device-ID address detection is disabled.,1: Device-ID address detection is enabled." bitfld.byte 0x6 4. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.byte 0x6 3. "GCAE,General Call Address Enable" "0: General call address detection is disabled.,1: General call address detection is enabled." bitfld.byte 0x6 2. "SAR2E,Slave Address Register 2 Enable" "0: Slave address in SARL2 and SARU2 is disabled.,1: Slave address in SARL2 and SARU2 is enabled" newline bitfld.byte 0x6 1. "SAR1E,Slave Address Register 1 Enable" "0: Slave address in SARL1 and SARU1 is disabled.,1: Slave address in SARL1 and SARU1 is enabled." bitfld.byte 0x6 0. "SAR0E,Slave Address Register 0 Enable" "0: Slave address in SARL0 and SARU0 is disabled.,1: Slave address in SARL0 and SARU0 is enabled." line.byte 0x7 "ICIER,I2C Bus Interrupt Enable Register" bitfld.byte 0x7 7. "TIE,Transmit Data Empty Interrupt Request Enable" "0: Transmit data empty interrupt request (IIC_TXI)..,1: Transmit data empty interrupt request (IIC_TXI).." bitfld.byte 0x7 6. "TEIE,Transmit End Interrupt Request Enable" "0: Transmit end interrupt request (IIC_TEI) is..,1: Transmit end interrupt request (IIC_TEI) is.." newline bitfld.byte 0x7 5. "RIE,Receive Data Full Interrupt Request Enable" "0: Receive data full interrupt request (IIC_RXI) is..,1: Receive data full interrupt request (IIC_RXI) is.." bitfld.byte 0x7 4. "NAKIE,NACK Reception Interrupt Request Enable" "0: NACK reception interrupt request (NAKI) is..,1: NACK reception interrupt request (NAKI) is.." newline bitfld.byte 0x7 3. "SPIE,Stop Condition Detection Interrupt Request Enable" "0: Stop condition detection interrupt request (SPI)..,1: Stop condition detection interrupt request (SPI).." bitfld.byte 0x7 2. "STIE,Start Condition Detection Interrupt Request Enable" "0: Start condition detection interrupt request..,1: Start condition detection interrupt request.." newline bitfld.byte 0x7 1. "ALIE,Arbitration-Lost Interrupt Request Enable" "0: Arbitration-lost interrupt request (ALI) is..,1: Arbitration-lost interrupt request (ALI) is.." bitfld.byte 0x7 0. "TMOIE,Timeout Interrupt Request Enable" "0: Timeout interrupt request (TMOI) is disabled.,1: Timeout interrupt request (TMOI) is enabled." line.byte 0x8 "ICSR1,I2C Bus Status Register 1" bitfld.byte 0x8 7. "HOA,Host Address Detection Flag" "0: Host address is not detected.,1: Host address is detected." bitfld.byte 0x8 6. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.byte 0x8 5. "DID,Device-ID Address Detection Flag" "0: Device-ID command is not detected.,1: Device-ID command is detected." bitfld.byte 0x8 4. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.byte 0x8 3. "GCA,General Call Address Detection Flag" "0: General call address is not detected.,1: General call address is detected." bitfld.byte 0x8 2. "AAS2,Slave Address 2 Detection Flag" "0: Slave address 2 is not detected.,1: Slave address 2 is detected" newline bitfld.byte 0x8 1. "AAS1,Slave Address 1 Detection Flag" "0: Slave address 1 is not detected.,1: Slave address 1 is detected." bitfld.byte 0x8 0. "AAS0,Slave Address 0 Detection Flag" "0: Slave address 0 is not detected.,1: Slave address 0 is detected." line.byte 0x9 "ICSR2,I2C Bus Status Register 2" rbitfld.byte 0x9 7. "TDRE,Transmit Data Empty Flag" "0: ICDRT contains transmit data.,1: ICDRT contains no transmit data." bitfld.byte 0x9 6. "TEND,Transmit End Flag" "0: Data is being transmitted.,1: Data has been transmitted." newline bitfld.byte 0x9 5. "RDRF,Receive Data Full Flag" "0: ICDRR contains no receive data.,1: ICDRR contains receive data." bitfld.byte 0x9 4. "NACKF,NACK Detection Flag" "0: NACK is not detected.,1: NACK is detected." newline bitfld.byte 0x9 3. "STOP,Stop Condition Detection Flag" "0: Stop condition is not detected.,1: Stop condition is detected." bitfld.byte 0x9 2. "START,Start Condition Detection Flag" "0: Start condition is not detected.,1: Start condition is detected." newline bitfld.byte 0x9 1. "AL,Arbitration-Lost Flag" "0: Arbitration is not lost.,1: Arbitration is lost." bitfld.byte 0x9 0. "TMOF,Timeout Detection Flag" "0: Timeout is not detected.,1: Timeout is detected." repeat 3. (increment 0x0 0x1)(increment 0x0 0x2) group.byte ($2+0xA)++0x0 line.byte 0x0 "SARL$1,Slave Address Register L%s" hexmask.byte 0x0 0.--7. 1. "SVA,A slave address is set.7-Bit Address = SVA[7:1] 10-Bit Address = { SVA9 SVA8 SVA[7:0] }" repeat.end repeat 3. (increment 0x0 0x1)(increment 0x0 0x2) group.byte ($2+0xB)++0x0 line.byte 0x0 "SARU$1,Slave Address Register U%s" hexmask.byte 0x0 3.--7. 1. "Reserved,These bits are read as 00000. The write value should be 00000." bitfld.byte 0x0 2. "SVA9,10-Bit Address(bit9)" "0,1" newline bitfld.byte 0x0 1. "SVA8,10-Bit Address(bit8)" "0,1" bitfld.byte 0x0 0. "FS,7-Bit/10-Bit Address Format Selection" "0: The 7-bit address format is selected.,1: The 10-bit address format is selected." repeat.end group.byte 0x10++0x2 line.byte 0x0 "ICBRL,I2C Bus Bit Rate Low-Level Register" bitfld.byte 0x0 5.--7. "Reserved,These bits are read as 111. The write value should be 111." "0,1,2,3,4,5,6,7" hexmask.byte 0x0 0.--4. 1. "BRL,Bit Rate Low-Level Period(Low-level period of SCL clock)" line.byte 0x1 "ICBRH,I2C Bus Bit Rate High-Level Register" bitfld.byte 0x1 5.--7. "Reserved,These bits are read as 111. The write value should be 111." "0,1,2,3,4,5,6,7" hexmask.byte 0x1 0.--4. 1. "BRH,Bit Rate High-Level Period(High-level period of SCL clock)" line.byte 0x2 "ICDRT,I2C Bus Transmit Data Register" hexmask.byte 0x2 0.--7. 1. "ICDRT,8-bit read-write register that stores transmit data." rgroup.byte 0x13++0x0 line.byte 0x0 "ICDRR,I2C Bus Receive Data Register" hexmask.byte 0x0 0.--7. 1. "ICDRR,8-bit register that stores the received data" group.byte 0x16++0x1 line.byte 0x0 "ICWUR,I2C Bus Wake Up Unit Register" bitfld.byte 0x0 7. "WUE,Wakeup Function Enable" "0: Wakeup function disabled,1: Wakeup function enabled." bitfld.byte 0x0 6. "WUIE,Wakeup Interrupt Request Enable" "0: Wakeup Interrupt Request (IIC0_WUI) disabled,1: Wakeup Interrupt Request (IIC0_WUI) enabled." newline bitfld.byte 0x0 5. "WUF,Wakeup Event Occurrence Flag" "0: Slave address does not match during wakeup..,1: Slave address matches during wakeup function." bitfld.byte 0x0 4. "WUACK,ACK bit for Wakeup Mode" "0: State of synchronous operation,1: State of asynchronous operation" newline bitfld.byte 0x0 1.--3. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.byte 0x0 0. "WUAFA,Wakeup Analog Filter Additional Selection" "0: Do not add the wakeup analog filter,1: Add the wakeup analog filter." line.byte 0x1 "ICWUR2,I2C Bus Wake up Unit Register 2" hexmask.byte 0x1 3.--7. 1. "Reserved,These bits are read as 11111. The write value should be 11111." rbitfld.byte 0x1 2. "WUSYF,Wake-up Function Synchronous Operation Status Flag" "0: IIC asynchronous circuit enable condition,1: IIC synchronous circuit enable condition." newline rbitfld.byte 0x1 1. "WUASYF,Wake-up Function Asynchronous Operation Status Flag" "0: IIC synchronous circuit enable condition,1: IIC asynchronous circuit enable condition." rbitfld.byte 0x1 0. "WUSEN,Wake-up Function Synchronous Enable" "0: IIC asynchronous circuit enable,1: IIC synchronous circuit enable" tree.end tree "IIC1" base ad:0x40053100 group.byte 0x0++0x9 line.byte 0x0 "ICCR1,I2C Bus Control Register 1" bitfld.byte 0x0 7. "ICE,I2C Bus Interface Enable" "0: Disable (SCLn and SDAn pins in inactive state),1: Enable (SCLn and SDAn pins in active state)" bitfld.byte 0x0 6. "IICRST,I2C Bus Interface Internal ResetNote:If an internal reset is initiated using the IICRST bit for a bus hang-up occurred during communication with the master device in slave mode the states may become different between the slave device and the.." "0: Releases the RIIC reset or internal reset.,1: Initiates the RIIC reset or internal reset." newline bitfld.byte 0x0 5. "CLO,Extra SCL Clock Cycle Output" "0: Does not output an extra SCL clock cycle.,1: Outputs an extra SCL clock cycle." bitfld.byte 0x0 4. "SOWP,SCLO/SDAO Write Protect" "0: Bits SCLO and SDAO can be written,1: Bits SCLO and SDAO are protected." newline bitfld.byte 0x0 3. "SCLO,SCL Output Control/Monitor" "0: (Read)The RIIC has driven the SCLn pin low. /..,1: (Read)The RIIC has released the SCLn pin. /.." bitfld.byte 0x0 2. "SDAO,SDA Output Control/Monitor" "0: (Read)The RIIC has driven the SDAn pin low. /..,1: (Read)The RIIC has released the SDAn pin./.." newline rbitfld.byte 0x0 1. "SCLI,SCL Line Monitor" "0: SCLn line is low.,1: SCLn line is high." rbitfld.byte 0x0 0. "SDAI,SDA Line Monitor" "0: SDAn line is low.,1: SDAn line is high." line.byte 0x1 "ICCR2,I2C Bus Control Register 2" rbitfld.byte 0x1 7. "BBSY,Bus Busy Detection Flag" "0: The I2C bus is released (bus free state).,1: The I2C bus is occupied (bus busy state)." bitfld.byte 0x1 6. "MST,Master/Slave Mode" "0: Slave mode,1: Master mode" newline bitfld.byte 0x1 5. "TRS,Transmit/Receive Mode" "0: Receive mode,1: Transmit mode" bitfld.byte 0x1 4. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.byte 0x1 3. "SP,Stop Condition Issuance RequestNote: Writing to the SP bit is not possible while the setting of the BBSY flag is 0 (bus free state).Note: Do not set the SP bit to 1 while a restart condition is being issued." "0: Does not request to issue a stop condition.,1: Requests to issue a stop condition." bitfld.byte 0x1 2. "RS,Restart Condition Issuance RequestNote: Do not set the RS bit to 1 while issuing a stop condition." "0: Does not request to issue a restart condition.,1: Requests to issue a restart condition." newline bitfld.byte 0x1 1. "ST,Start Condition Issuance RequestSet the ST bit to 1 (start condition issuance request) when the BBSY flag is set to 0 (bus free state)." "0: Does not request to issue a start condition.,1: Requests to issue a start condition." bitfld.byte 0x1 0. "Reserved,This bit is read as 0. The write value should be 0." "0,1" line.byte 0x2 "ICMR1,I2C Bus Mode Register 1" bitfld.byte 0x2 7. "MTWP,MST/TRS Write Protect" "0: Disables writing to the MST and TRS bits in ICCR2.,1: Enables writing to the MST and TRS bits in ICCR2." bitfld.byte 0x2 4.--6. "CKS,Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB / 2^CKS )" "0: PCLKB/1 clock,1: PCLKB/2 clock,?,?,?,?,?,?" newline bitfld.byte 0x2 3. "BCWP,BC Write Protect(This bit is read as 1.)" "0: Enables a value to be written in the BC[2:0] bits.,1: Disables a value to be written in the BC[2:0].." bitfld.byte 0x2 0.--2. "BC,Bit Counter" "0: 9 bits,1: 2 bits,?,?,?,?,?,?" line.byte 0x3 "ICMR2,I2C Bus Mode Register 2" bitfld.byte 0x3 7. "DLCS,SDA Output Delay Clock Source Select" "0: The internal reference clock (fIIC) is selected..,1: The internal reference clock divided by 2.." bitfld.byte 0x3 4.--6. "SDDL,SDA Output Delay Counter" "0: No output delay,1: 1 fIIC cycle (ICMR2.DLCS=0) / 1 or 2 fIIC cycles..,?,?,?,?,?,?" newline bitfld.byte 0x3 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x3 2. "TMOH,Timeout H Count Control" "0: Count is disabled while the SCLn line is at a..,1: Count is enabled while the SCLn line is at a.." newline bitfld.byte 0x3 1. "TMOL,Timeout L Count Control" "0: Count is disabled while the SCLn line is at a..,1: Count is enabled while the SCLn line is at a low.." bitfld.byte 0x3 0. "TMOS,Timeout Detection Time Select" "0: Long mode is selected.,1: Short mode is selected." line.byte 0x4 "ICMR3,I2C Bus Mode Register 3" bitfld.byte 0x4 7. "SMBS,SMBus/I2C Bus Selection" "0: The I2C bus is selected.,1: The SMBus is selected." bitfld.byte 0x4 6. "WAIT,WAITNote: When the value of the WAIT bit is to be read be sure to read the ICDRR beforehand." "0: No WAIT (The period between ninth clock cycle..,1: WAIT (The period between ninth clock cycle and.." newline bitfld.byte 0x4 5. "RDRFS,RDRF Flag Set Timing Selection" "0: The RDRF flag is set at the rising edge of the..,1: The RDRF flag is set at the rising edge of the.." bitfld.byte 0x4 4. "ACKWP,ACKBT Write Protect" "0: Modification of the ACKBT bit is disabled.,1: Modification of the ACKBT bit is enabled." newline bitfld.byte 0x4 3. "ACKBT,Transmit Acknowledge" "0: A 0 is sent as the acknowledge bit (ACK..,1: A 1 is sent as the acknowledge bit (NACK.." rbitfld.byte 0x4 2. "ACKBR,Receive Acknowledge" "0: A 0 is received as the acknowledge bit (ACK..,1: A 1 is received as the acknowledge bit (NACK.." newline bitfld.byte 0x4 0.--1. "NF,Noise Filter Stage Selection" "0: Noise of up to one fIIC cycle is filtered out..,1: Noise of up to two fIIC cycles is filtered out..,?,?" line.byte 0x5 "ICFER,I2C Bus Function Enable Register" bitfld.byte 0x5 7. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x5 6. "SCLE,SCL Synchronous Circuit Enable" "0: No SCL synchronous circuit is used.,1: An SCL synchronous circuit is used." newline bitfld.byte 0x5 5. "NFE,Digital Noise Filter Circuit Enable" "0: No digital noise filter circuit is used.,1: A digital noise filter circuit is used." bitfld.byte 0x5 4. "NACKE,NACK Reception Transfer Suspension Enable" "0: Transfer operation is not suspended during NACK..,1: Transfer operation is suspended during NACK.." newline bitfld.byte 0x5 3. "SALE,Slave Arbitration-Lost Detection Enable" "0: Slave arbitration-lost detection is disabled.,1: Slave arbitration-lost detection is enabled." bitfld.byte 0x5 2. "NALE,NACK Transmission Arbitration-Lost Detection Enable" "0: NACK transmission arbitration-lost detection is..,1: NACK transmission arbitration-lost detection is.." newline bitfld.byte 0x5 1. "MALE,Master Arbitration-Lost Detection Enable" "0: Master arbitration-lost detection is disabled.,1: Master arbitration-lost detection is enabled." bitfld.byte 0x5 0. "TMOE,Timeout Function Enable" "0: The timeout function is disabled.,1: The timeout function is enabled." line.byte 0x6 "ICSER,I2C Bus Status Enable Register" bitfld.byte 0x6 7. "HOAE,Host Address Enable" "0: Host address detection is disabled.,1: Host address detection is enabled." bitfld.byte 0x6 6. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.byte 0x6 5. "DIDE,Device-ID Address Detection Enable" "0: Device-ID address detection is disabled.,1: Device-ID address detection is enabled." bitfld.byte 0x6 4. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.byte 0x6 3. "GCAE,General Call Address Enable" "0: General call address detection is disabled.,1: General call address detection is enabled." bitfld.byte 0x6 2. "SAR2E,Slave Address Register 2 Enable" "0: Slave address in SARL2 and SARU2 is disabled.,1: Slave address in SARL2 and SARU2 is enabled" newline bitfld.byte 0x6 1. "SAR1E,Slave Address Register 1 Enable" "0: Slave address in SARL1 and SARU1 is disabled.,1: Slave address in SARL1 and SARU1 is enabled." bitfld.byte 0x6 0. "SAR0E,Slave Address Register 0 Enable" "0: Slave address in SARL0 and SARU0 is disabled.,1: Slave address in SARL0 and SARU0 is enabled." line.byte 0x7 "ICIER,I2C Bus Interrupt Enable Register" bitfld.byte 0x7 7. "TIE,Transmit Data Empty Interrupt Request Enable" "0: Transmit data empty interrupt request (IIC_TXI)..,1: Transmit data empty interrupt request (IIC_TXI).." bitfld.byte 0x7 6. "TEIE,Transmit End Interrupt Request Enable" "0: Transmit end interrupt request (IIC_TEI) is..,1: Transmit end interrupt request (IIC_TEI) is.." newline bitfld.byte 0x7 5. "RIE,Receive Data Full Interrupt Request Enable" "0: Receive data full interrupt request (IIC_RXI) is..,1: Receive data full interrupt request (IIC_RXI) is.." bitfld.byte 0x7 4. "NAKIE,NACK Reception Interrupt Request Enable" "0: NACK reception interrupt request (NAKI) is..,1: NACK reception interrupt request (NAKI) is.." newline bitfld.byte 0x7 3. "SPIE,Stop Condition Detection Interrupt Request Enable" "0: Stop condition detection interrupt request (SPI)..,1: Stop condition detection interrupt request (SPI).." bitfld.byte 0x7 2. "STIE,Start Condition Detection Interrupt Request Enable" "0: Start condition detection interrupt request..,1: Start condition detection interrupt request.." newline bitfld.byte 0x7 1. "ALIE,Arbitration-Lost Interrupt Request Enable" "0: Arbitration-lost interrupt request (ALI) is..,1: Arbitration-lost interrupt request (ALI) is.." bitfld.byte 0x7 0. "TMOIE,Timeout Interrupt Request Enable" "0: Timeout interrupt request (TMOI) is disabled.,1: Timeout interrupt request (TMOI) is enabled." line.byte 0x8 "ICSR1,I2C Bus Status Register 1" bitfld.byte 0x8 7. "HOA,Host Address Detection Flag" "0: Host address is not detected.,1: Host address is detected." bitfld.byte 0x8 6. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.byte 0x8 5. "DID,Device-ID Address Detection Flag" "0: Device-ID command is not detected.,1: Device-ID command is detected." bitfld.byte 0x8 4. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.byte 0x8 3. "GCA,General Call Address Detection Flag" "0: General call address is not detected.,1: General call address is detected." bitfld.byte 0x8 2. "AAS2,Slave Address 2 Detection Flag" "0: Slave address 2 is not detected.,1: Slave address 2 is detected" newline bitfld.byte 0x8 1. "AAS1,Slave Address 1 Detection Flag" "0: Slave address 1 is not detected.,1: Slave address 1 is detected." bitfld.byte 0x8 0. "AAS0,Slave Address 0 Detection Flag" "0: Slave address 0 is not detected.,1: Slave address 0 is detected." line.byte 0x9 "ICSR2,I2C Bus Status Register 2" rbitfld.byte 0x9 7. "TDRE,Transmit Data Empty Flag" "0: ICDRT contains transmit data.,1: ICDRT contains no transmit data." bitfld.byte 0x9 6. "TEND,Transmit End Flag" "0: Data is being transmitted.,1: Data has been transmitted." newline bitfld.byte 0x9 5. "RDRF,Receive Data Full Flag" "0: ICDRR contains no receive data.,1: ICDRR contains receive data." bitfld.byte 0x9 4. "NACKF,NACK Detection Flag" "0: NACK is not detected.,1: NACK is detected." newline bitfld.byte 0x9 3. "STOP,Stop Condition Detection Flag" "0: Stop condition is not detected.,1: Stop condition is detected." bitfld.byte 0x9 2. "START,Start Condition Detection Flag" "0: Start condition is not detected.,1: Start condition is detected." newline bitfld.byte 0x9 1. "AL,Arbitration-Lost Flag" "0: Arbitration is not lost.,1: Arbitration is lost." bitfld.byte 0x9 0. "TMOF,Timeout Detection Flag" "0: Timeout is not detected.,1: Timeout is detected." repeat 3. (increment 0x0 0x1)(increment 0x0 0x2) group.byte ($2+0xA)++0x0 line.byte 0x0 "SARL$1,Slave Address Register L%s" hexmask.byte 0x0 0.--7. 1. "SVA,A slave address is set.7-Bit Address = SVA[7:1] 10-Bit Address = { SVA9 SVA8 SVA[7:0] }" repeat.end repeat 3. (increment 0x0 0x1)(increment 0x0 0x2) group.byte ($2+0xB)++0x0 line.byte 0x0 "SARU$1,Slave Address Register U%s" hexmask.byte 0x0 3.--7. 1. "Reserved,These bits are read as 00000. The write value should be 00000." bitfld.byte 0x0 2. "SVA9,10-Bit Address(bit9)" "0,1" newline bitfld.byte 0x0 1. "SVA8,10-Bit Address(bit8)" "0,1" bitfld.byte 0x0 0. "FS,7-Bit/10-Bit Address Format Selection" "0: The 7-bit address format is selected.,1: The 10-bit address format is selected." repeat.end group.byte 0x10++0x2 line.byte 0x0 "ICBRL,I2C Bus Bit Rate Low-Level Register" bitfld.byte 0x0 5.--7. "Reserved,These bits are read as 111. The write value should be 111." "0,1,2,3,4,5,6,7" hexmask.byte 0x0 0.--4. 1. "BRL,Bit Rate Low-Level Period(Low-level period of SCL clock)" line.byte 0x1 "ICBRH,I2C Bus Bit Rate High-Level Register" bitfld.byte 0x1 5.--7. "Reserved,These bits are read as 111. The write value should be 111." "0,1,2,3,4,5,6,7" hexmask.byte 0x1 0.--4. 1. "BRH,Bit Rate High-Level Period(High-level period of SCL clock)" line.byte 0x2 "ICDRT,I2C Bus Transmit Data Register" hexmask.byte 0x2 0.--7. 1. "ICDRT,8-bit read-write register that stores transmit data." rgroup.byte 0x13++0x0 line.byte 0x0 "ICDRR,I2C Bus Receive Data Register" hexmask.byte 0x0 0.--7. 1. "ICDRR,8-bit register that stores the received data" tree.end tree "IIC2" base ad:0x40053200 group.byte 0x0++0x9 line.byte 0x0 "ICCR1,I2C Bus Control Register 1" bitfld.byte 0x0 7. "ICE,I2C Bus Interface Enable" "0: Disable (SCLn and SDAn pins in inactive state),1: Enable (SCLn and SDAn pins in active state)" bitfld.byte 0x0 6. "IICRST,I2C Bus Interface Internal ResetNote:If an internal reset is initiated using the IICRST bit for a bus hang-up occurred during communication with the master device in slave mode the states may become different between the slave device and the.." "0: Releases the RIIC reset or internal reset.,1: Initiates the RIIC reset or internal reset." newline bitfld.byte 0x0 5. "CLO,Extra SCL Clock Cycle Output" "0: Does not output an extra SCL clock cycle.,1: Outputs an extra SCL clock cycle." bitfld.byte 0x0 4. "SOWP,SCLO/SDAO Write Protect" "0: Bits SCLO and SDAO can be written,1: Bits SCLO and SDAO are protected." newline bitfld.byte 0x0 3. "SCLO,SCL Output Control/Monitor" "0: (Read)The RIIC has driven the SCLn pin low. /..,1: (Read)The RIIC has released the SCLn pin. /.." bitfld.byte 0x0 2. "SDAO,SDA Output Control/Monitor" "0: (Read)The RIIC has driven the SDAn pin low. /..,1: (Read)The RIIC has released the SDAn pin./.." newline rbitfld.byte 0x0 1. "SCLI,SCL Line Monitor" "0: SCLn line is low.,1: SCLn line is high." rbitfld.byte 0x0 0. "SDAI,SDA Line Monitor" "0: SDAn line is low.,1: SDAn line is high." line.byte 0x1 "ICCR2,I2C Bus Control Register 2" rbitfld.byte 0x1 7. "BBSY,Bus Busy Detection Flag" "0: The I2C bus is released (bus free state).,1: The I2C bus is occupied (bus busy state)." bitfld.byte 0x1 6. "MST,Master/Slave Mode" "0: Slave mode,1: Master mode" newline bitfld.byte 0x1 5. "TRS,Transmit/Receive Mode" "0: Receive mode,1: Transmit mode" bitfld.byte 0x1 4. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.byte 0x1 3. "SP,Stop Condition Issuance RequestNote: Writing to the SP bit is not possible while the setting of the BBSY flag is 0 (bus free state).Note: Do not set the SP bit to 1 while a restart condition is being issued." "0: Does not request to issue a stop condition.,1: Requests to issue a stop condition." bitfld.byte 0x1 2. "RS,Restart Condition Issuance RequestNote: Do not set the RS bit to 1 while issuing a stop condition." "0: Does not request to issue a restart condition.,1: Requests to issue a restart condition." newline bitfld.byte 0x1 1. "ST,Start Condition Issuance RequestSet the ST bit to 1 (start condition issuance request) when the BBSY flag is set to 0 (bus free state)." "0: Does not request to issue a start condition.,1: Requests to issue a start condition." bitfld.byte 0x1 0. "Reserved,This bit is read as 0. The write value should be 0." "0,1" line.byte 0x2 "ICMR1,I2C Bus Mode Register 1" bitfld.byte 0x2 7. "MTWP,MST/TRS Write Protect" "0: Disables writing to the MST and TRS bits in ICCR2.,1: Enables writing to the MST and TRS bits in ICCR2." bitfld.byte 0x2 4.--6. "CKS,Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB / 2^CKS )" "0: PCLKB/1 clock,1: PCLKB/2 clock,?,?,?,?,?,?" newline bitfld.byte 0x2 3. "BCWP,BC Write Protect(This bit is read as 1.)" "0: Enables a value to be written in the BC[2:0] bits.,1: Disables a value to be written in the BC[2:0].." bitfld.byte 0x2 0.--2. "BC,Bit Counter" "0: 9 bits,1: 2 bits,?,?,?,?,?,?" line.byte 0x3 "ICMR2,I2C Bus Mode Register 2" bitfld.byte 0x3 7. "DLCS,SDA Output Delay Clock Source Select" "0: The internal reference clock (fIIC) is selected..,1: The internal reference clock divided by 2.." bitfld.byte 0x3 4.--6. "SDDL,SDA Output Delay Counter" "0: No output delay,1: 1 fIIC cycle (ICMR2.DLCS=0) / 1 or 2 fIIC cycles..,?,?,?,?,?,?" newline bitfld.byte 0x3 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x3 2. "TMOH,Timeout H Count Control" "0: Count is disabled while the SCLn line is at a..,1: Count is enabled while the SCLn line is at a.." newline bitfld.byte 0x3 1. "TMOL,Timeout L Count Control" "0: Count is disabled while the SCLn line is at a..,1: Count is enabled while the SCLn line is at a low.." bitfld.byte 0x3 0. "TMOS,Timeout Detection Time Select" "0: Long mode is selected.,1: Short mode is selected." line.byte 0x4 "ICMR3,I2C Bus Mode Register 3" bitfld.byte 0x4 7. "SMBS,SMBus/I2C Bus Selection" "0: The I2C bus is selected.,1: The SMBus is selected." bitfld.byte 0x4 6. "WAIT,WAITNote: When the value of the WAIT bit is to be read be sure to read the ICDRR beforehand." "0: No WAIT (The period between ninth clock cycle..,1: WAIT (The period between ninth clock cycle and.." newline bitfld.byte 0x4 5. "RDRFS,RDRF Flag Set Timing Selection" "0: The RDRF flag is set at the rising edge of the..,1: The RDRF flag is set at the rising edge of the.." bitfld.byte 0x4 4. "ACKWP,ACKBT Write Protect" "0: Modification of the ACKBT bit is disabled.,1: Modification of the ACKBT bit is enabled." newline bitfld.byte 0x4 3. "ACKBT,Transmit Acknowledge" "0: A 0 is sent as the acknowledge bit (ACK..,1: A 1 is sent as the acknowledge bit (NACK.." rbitfld.byte 0x4 2. "ACKBR,Receive Acknowledge" "0: A 0 is received as the acknowledge bit (ACK..,1: A 1 is received as the acknowledge bit (NACK.." newline bitfld.byte 0x4 0.--1. "NF,Noise Filter Stage Selection" "0: Noise of up to one fIIC cycle is filtered out..,1: Noise of up to two fIIC cycles is filtered out..,?,?" line.byte 0x5 "ICFER,I2C Bus Function Enable Register" bitfld.byte 0x5 7. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x5 6. "SCLE,SCL Synchronous Circuit Enable" "0: No SCL synchronous circuit is used.,1: An SCL synchronous circuit is used." newline bitfld.byte 0x5 5. "NFE,Digital Noise Filter Circuit Enable" "0: No digital noise filter circuit is used.,1: A digital noise filter circuit is used." bitfld.byte 0x5 4. "NACKE,NACK Reception Transfer Suspension Enable" "0: Transfer operation is not suspended during NACK..,1: Transfer operation is suspended during NACK.." newline bitfld.byte 0x5 3. "SALE,Slave Arbitration-Lost Detection Enable" "0: Slave arbitration-lost detection is disabled.,1: Slave arbitration-lost detection is enabled." bitfld.byte 0x5 2. "NALE,NACK Transmission Arbitration-Lost Detection Enable" "0: NACK transmission arbitration-lost detection is..,1: NACK transmission arbitration-lost detection is.." newline bitfld.byte 0x5 1. "MALE,Master Arbitration-Lost Detection Enable" "0: Master arbitration-lost detection is disabled.,1: Master arbitration-lost detection is enabled." bitfld.byte 0x5 0. "TMOE,Timeout Function Enable" "0: The timeout function is disabled.,1: The timeout function is enabled." line.byte 0x6 "ICSER,I2C Bus Status Enable Register" bitfld.byte 0x6 7. "HOAE,Host Address Enable" "0: Host address detection is disabled.,1: Host address detection is enabled." bitfld.byte 0x6 6. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.byte 0x6 5. "DIDE,Device-ID Address Detection Enable" "0: Device-ID address detection is disabled.,1: Device-ID address detection is enabled." bitfld.byte 0x6 4. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.byte 0x6 3. "GCAE,General Call Address Enable" "0: General call address detection is disabled.,1: General call address detection is enabled." bitfld.byte 0x6 2. "SAR2E,Slave Address Register 2 Enable" "0: Slave address in SARL2 and SARU2 is disabled.,1: Slave address in SARL2 and SARU2 is enabled" newline bitfld.byte 0x6 1. "SAR1E,Slave Address Register 1 Enable" "0: Slave address in SARL1 and SARU1 is disabled.,1: Slave address in SARL1 and SARU1 is enabled." bitfld.byte 0x6 0. "SAR0E,Slave Address Register 0 Enable" "0: Slave address in SARL0 and SARU0 is disabled.,1: Slave address in SARL0 and SARU0 is enabled." line.byte 0x7 "ICIER,I2C Bus Interrupt Enable Register" bitfld.byte 0x7 7. "TIE,Transmit Data Empty Interrupt Request Enable" "0: Transmit data empty interrupt request (IIC_TXI)..,1: Transmit data empty interrupt request (IIC_TXI).." bitfld.byte 0x7 6. "TEIE,Transmit End Interrupt Request Enable" "0: Transmit end interrupt request (IIC_TEI) is..,1: Transmit end interrupt request (IIC_TEI) is.." newline bitfld.byte 0x7 5. "RIE,Receive Data Full Interrupt Request Enable" "0: Receive data full interrupt request (IIC_RXI) is..,1: Receive data full interrupt request (IIC_RXI) is.." bitfld.byte 0x7 4. "NAKIE,NACK Reception Interrupt Request Enable" "0: NACK reception interrupt request (NAKI) is..,1: NACK reception interrupt request (NAKI) is.." newline bitfld.byte 0x7 3. "SPIE,Stop Condition Detection Interrupt Request Enable" "0: Stop condition detection interrupt request (SPI)..,1: Stop condition detection interrupt request (SPI).." bitfld.byte 0x7 2. "STIE,Start Condition Detection Interrupt Request Enable" "0: Start condition detection interrupt request..,1: Start condition detection interrupt request.." newline bitfld.byte 0x7 1. "ALIE,Arbitration-Lost Interrupt Request Enable" "0: Arbitration-lost interrupt request (ALI) is..,1: Arbitration-lost interrupt request (ALI) is.." bitfld.byte 0x7 0. "TMOIE,Timeout Interrupt Request Enable" "0: Timeout interrupt request (TMOI) is disabled.,1: Timeout interrupt request (TMOI) is enabled." line.byte 0x8 "ICSR1,I2C Bus Status Register 1" bitfld.byte 0x8 7. "HOA,Host Address Detection Flag" "0: Host address is not detected.,1: Host address is detected." bitfld.byte 0x8 6. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.byte 0x8 5. "DID,Device-ID Address Detection Flag" "0: Device-ID command is not detected.,1: Device-ID command is detected." bitfld.byte 0x8 4. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.byte 0x8 3. "GCA,General Call Address Detection Flag" "0: General call address is not detected.,1: General call address is detected." bitfld.byte 0x8 2. "AAS2,Slave Address 2 Detection Flag" "0: Slave address 2 is not detected.,1: Slave address 2 is detected" newline bitfld.byte 0x8 1. "AAS1,Slave Address 1 Detection Flag" "0: Slave address 1 is not detected.,1: Slave address 1 is detected." bitfld.byte 0x8 0. "AAS0,Slave Address 0 Detection Flag" "0: Slave address 0 is not detected.,1: Slave address 0 is detected." line.byte 0x9 "ICSR2,I2C Bus Status Register 2" rbitfld.byte 0x9 7. "TDRE,Transmit Data Empty Flag" "0: ICDRT contains transmit data.,1: ICDRT contains no transmit data." bitfld.byte 0x9 6. "TEND,Transmit End Flag" "0: Data is being transmitted.,1: Data has been transmitted." newline bitfld.byte 0x9 5. "RDRF,Receive Data Full Flag" "0: ICDRR contains no receive data.,1: ICDRR contains receive data." bitfld.byte 0x9 4. "NACKF,NACK Detection Flag" "0: NACK is not detected.,1: NACK is detected." newline bitfld.byte 0x9 3. "STOP,Stop Condition Detection Flag" "0: Stop condition is not detected.,1: Stop condition is detected." bitfld.byte 0x9 2. "START,Start Condition Detection Flag" "0: Start condition is not detected.,1: Start condition is detected." newline bitfld.byte 0x9 1. "AL,Arbitration-Lost Flag" "0: Arbitration is not lost.,1: Arbitration is lost." bitfld.byte 0x9 0. "TMOF,Timeout Detection Flag" "0: Timeout is not detected.,1: Timeout is detected." repeat 3. (increment 0x0 0x1)(increment 0x0 0x2) group.byte ($2+0xA)++0x0 line.byte 0x0 "SARL$1,Slave Address Register L%s" hexmask.byte 0x0 0.--7. 1. "SVA,A slave address is set.7-Bit Address = SVA[7:1] 10-Bit Address = { SVA9 SVA8 SVA[7:0] }" repeat.end repeat 3. (increment 0x0 0x1)(increment 0x0 0x2) group.byte ($2+0xB)++0x0 line.byte 0x0 "SARU$1,Slave Address Register U%s" hexmask.byte 0x0 3.--7. 1. "Reserved,These bits are read as 00000. The write value should be 00000." bitfld.byte 0x0 2. "SVA9,10-Bit Address(bit9)" "0,1" newline bitfld.byte 0x0 1. "SVA8,10-Bit Address(bit8)" "0,1" bitfld.byte 0x0 0. "FS,7-Bit/10-Bit Address Format Selection" "0: The 7-bit address format is selected.,1: The 10-bit address format is selected." repeat.end group.byte 0x10++0x2 line.byte 0x0 "ICBRL,I2C Bus Bit Rate Low-Level Register" bitfld.byte 0x0 5.--7. "Reserved,These bits are read as 111. The write value should be 111." "0,1,2,3,4,5,6,7" hexmask.byte 0x0 0.--4. 1. "BRL,Bit Rate Low-Level Period(Low-level period of SCL clock)" line.byte 0x1 "ICBRH,I2C Bus Bit Rate High-Level Register" bitfld.byte 0x1 5.--7. "Reserved,These bits are read as 111. The write value should be 111." "0,1,2,3,4,5,6,7" hexmask.byte 0x1 0.--4. 1. "BRH,Bit Rate High-Level Period(High-level period of SCL clock)" line.byte 0x2 "ICDRT,I2C Bus Transmit Data Register" hexmask.byte 0x2 0.--7. 1. "ICDRT,8-bit read-write register that stores transmit data." rgroup.byte 0x13++0x0 line.byte 0x0 "ICDRR,I2C Bus Receive Data Register" hexmask.byte 0x0 0.--7. 1. "ICDRR,8-bit register that stores the received data" tree.end tree.end tree "IWDT (Independent Watchdog Timer)" base ad:0x40044400 group.byte 0x0++0x0 line.byte 0x0 "IWDTRR,IWDT Refresh Register" hexmask.byte 0x0 0.--7. 1. "IWDTRR,The counter is refreshed by writing 0x00 and then writing 0xFF to this register." group.word 0x4++0x1 line.word 0x0 "IWDTSR,IWDT Status Register" bitfld.word 0x0 15. "REFEF,Refresh Error Flag" "0: Refresh error not occurred,1: Refresh error occurred" bitfld.word 0x0 14. "UNDFF,Underflow Flag" "0: Underflow not occurred,1: Underflow occurred" hexmask.word 0x0 0.--13. 1. "CNTVAL,Counter ValueValue counted by the counter" tree.end tree "KINT (Key Interrupt Function)" base ad:0x40080000 group.byte 0x0++0x0 line.byte 0x0 "KRCTL,KEY Return Control Register" bitfld.byte 0x0 7. "KRMD,Usage of Key Interrupt Flags(KR0 to KR7)" "0: Do not use key interrupt flags,1: Use key interrupt flags." hexmask.byte 0x0 1.--6. 1. "Reserved,These bits are read as 000000. The write value should be 000000." bitfld.byte 0x0 0. "KREG,Detection Edge Selection (KRF0 to KRF7)" "0: Falling edge,1: Rising edge" group.byte 0x4++0x0 line.byte 0x0 "KRF,KEY Return Flag Register" bitfld.byte 0x0 7. "KRF7,Key interrupt flag 7" "0: No interrupt detected,1: Interrupt detected." bitfld.byte 0x0 6. "KRF6,Key interrupt flag 6" "0: No interrupt detected,1: Interrupt detected." bitfld.byte 0x0 5. "KRF5,Key interrupt flag 5" "0: No interrupt detected,1: Interrupt detected." newline bitfld.byte 0x0 4. "KRF4,Key interrupt flag 4" "0: No interrupt detected,1: Interrupt detected." bitfld.byte 0x0 3. "KRF3,Key interrupt flag 3" "0: No interrupt detected,1: Interrupt detected." bitfld.byte 0x0 2. "KRF2,Key interrupt flag 2" "0: No interrupt detected,1: Interrupt detected." newline bitfld.byte 0x0 1. "KRF1,Key interrupt flag 1" "0: No interrupt detected,1: Interrupt detected." bitfld.byte 0x0 0. "KRF0,Key interrupt flag 0" "0: No interrupt detected,1: Interrupt detected." group.byte 0x8++0x0 line.byte 0x0 "KRM,KEY Return Mode Register" bitfld.byte 0x0 7. "KRM7,Key interrupt mode control 7" "0: Does not detect key interrupt signal,1: Detect key interrupt signal." bitfld.byte 0x0 6. "KRM6,Key interrupt mode control 6" "0: Does not detect key interrupt signal,1: Detect key interrupt signal." bitfld.byte 0x0 5. "KRM5,Key interrupt mode control 5" "0: Does not detect key interrupt signal,1: Detect key interrupt signal." newline bitfld.byte 0x0 4. "KRM4,Key interrupt mode control 4" "0: Does not detect key interrupt signal,1: Detect key interrupt signal." bitfld.byte 0x0 3. "KRM3,Key interrupt mode control 3" "0: Does not detect key interrupt signal,1: Detect key interrupt signal." bitfld.byte 0x0 2. "KRM2,Key interrupt mode control 2" "0: Does not detect key interrupt signal,1: Detect key interrupt signal." newline bitfld.byte 0x0 1. "KRM1,Key interrupt mode control 1" "0: Does not detect key interrupt signal,1: Detect key interrupt signal." bitfld.byte 0x0 0. "KRM0,Key interrupt mode control 0" "0: Does not detect key interrupt signal,1: Detect key interrupt signal." tree.end tree "MMF (Memory Mirror Function)" base ad:0x40001000 group.long 0x0++0x7 line.long 0x0 "MMSFR,MemMirror Special Function Register" hexmask.long.byte 0x0 24.--31. 1. "KEY,MMSFR Key Code" bitfld.long 0x0 23. "Reserved,This bit is read as 0. The write value should be 0." "0,1" hexmask.long.word 0x0 7.--22. 1. "MEMMIRADDR,Specifies the memory mirror address.NOTE: A value cannot be set in the low-order 7 bits. These bits are fixed to 0." hexmask.long.byte 0x0 0.--6. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." line.long 0x4 "MMEN,MemMirror Enable Register" hexmask.long.byte 0x4 24.--31. 1. "KEY,MMEN Key Code" hexmask.long.tbyte 0x4 1.--23. 1. "Reserved,These bits are read as 00000000000000000000000. The write value should be 00000000000000000000000." bitfld.long 0x4 0. "EN,Memory Mirror Function Enable" "0: Memory Mirror Function is disabled.,1: Memory Mirror Function is enabled." tree.end tree "MMPU (Bus Master MPU)" base ad:0x40000000 group.word 0x0++0x1 line.word 0x0 "MMPUCTLA,Bus Master MPU Control Register A" hexmask.word.byte 0x0 8.--15. 1. "KEY,Key CodeThese bits are used to enable or disable writing of the OAD and ENABLE bit." hexmask.word.byte 0x0 2.--7. 1. "Reserved,These bits are read as 000000. The write value should be 000000." bitfld.word 0x0 1. "OAD,Operation after detection" "0: Non-maskable interrupt.,1: Internal reset." newline bitfld.word 0x0 0. "ENABLE,Master Group enable" "0: Master Group A disabled,1: Master Group A enabled." repeat 16. (increment 0x0 0x1)(increment 0x0 0x10) group.word ($2+0x200)++0x1 line.word 0x0 "MMPUACA$1,Group A Region %s Access Control Register" hexmask.word 0x0 3.--15. 1. "Reserved,These bits are read as 0000000000000. The write value should be 0000000000000." bitfld.word 0x0 2. "WP,Write protection" "0: Write permission,1: Write protection" bitfld.word 0x0 1. "RP,Read protection" "0: Read permission,1: Read protection" newline bitfld.word 0x0 0. "ENABLE,Region enable" "0: Group m Region n unit is disabled,1: Group m Region n unit is enabled" repeat.end repeat 16. (increment 0x0 0x1)(increment 0x0 0x10) group.long ($2+0x204)++0x3 line.long 0x0 "MMPUSA$1,Group A Region %s Start Address Register" hexmask.long 0x0 0.--31. 1. "MMPUSA,Address where the region starts for use in region determination.NOTE: The low-order 2 bits are fixed to 0." repeat.end repeat 16. (increment 0x0 0x1)(increment 0x0 0x10) group.long ($2+0x208)++0x3 line.long 0x0 "MMPUEA$1,Group A Region %s End Address Register" hexmask.long 0x0 0.--31. 1. "MMPUEA,Region end address registerAddress where the region end for use in region determination.NOTE: The low-order 2 bits are fixed to 1." repeat.end group.word 0x102++0x1 line.word 0x0 "MMPUPTA,Group A Protection of Register" hexmask.word.byte 0x0 8.--15. 1. "KEY,Write Keyword The data written to these bits are not stored." hexmask.word.byte 0x0 1.--7. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.word 0x0 0. "PROTECT,Protection of register(MMPUSAn MMPUEAn and MMPUACAn)" "0: All Bus Master MPU Group A register writing is..,1: All Bus Master MPU Group A register writing is.." tree.end tree "MSTP (Module Stop Control)" base ad:0x40047000 group.long 0x0++0xB line.long 0x0 "MSTPCRB,Module Stop Control Register B" bitfld.long 0x0 31. "MSTPB31,Serial Communication Interface 0 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x0 30. "MSTPB30,Serial Communication Interface 1 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x0 29. "MSTPB29,Serial Communication Interface 2 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" newline bitfld.long 0x0 28. "MSTPB28,Serial Communication Interface 3 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x0 27. "MSTPB27,Serial Communication Interface 4 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" hexmask.long.byte 0x0 23.--26. 1. "Reserved,These bits are read as 1111. The write value should be 1111." newline bitfld.long 0x0 22. "MSTPB22,Serial Communication Interface 9 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x0 20.--21. "Reserved,These bits are read as 11. The write value should be 11." "0,1,2,3" bitfld.long 0x0 19. "MSTPB19,Serial Peripheral Interface 0 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" newline bitfld.long 0x0 18. "MSTPB18,Serial Peripheral Interface 1 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" hexmask.long.byte 0x0 12.--17. 1. "Reserved,These bits are read as 111111. The write value should be 111111." bitfld.long 0x0 11. "MSTPB11,Universal Serial Bus 2.0 FS Interface Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" newline bitfld.long 0x0 10. "Reserved,This bit is read as 1. The write value should be 1." "0,1" bitfld.long 0x0 9. "MSTPB9,I2C Bus Interface 0 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x0 8. "MSTPB8,I2C Bus Interface 1 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" newline bitfld.long 0x0 7. "MSTPB7,I2C Bus Interface 2 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x0 6. "MSTPB6,Queued Serial Peripheral Interface Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x0 3.--5. "Reserved,These bits are read as 111. The write value should be 111." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2. "MSTPB2,Controller Area Network Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x0 0.--1. "Reserved,These bits are read as 11. The write value should be 11." "0,1,2,3" line.long 0x4 "MSTPCRC,Module Stop Control Register C" bitfld.long 0x4 31. "MSTPC31,TSIP Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" hexmask.long.word 0x4 15.--30. 1. "Reserved,These bits are read as 1111111111111111. The write value should be 1111111111111111." bitfld.long 0x4 14. "MSTPC14,Event Link Controller Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" newline bitfld.long 0x4 13. "MSTPC13,Data Operation Circuit Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x4 12. "MSTPC12,Secure Digital Host Interface/Multi Media Card Interface ModuleStop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x4 9.--11. "Reserved,These bits are read as 111. The write value should be 111." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8. "MSTPC8,Synchronous Serial Interface 0 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x4 5.--7. "Reserved,These bits are read as 111. The write value should be 111." "0,1,2,3,4,5,6,7" bitfld.long 0x4 4. "MSTPC4,Segment LCD Controller Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" newline bitfld.long 0x4 3. "MSTPC3,Capacitive Touch Sensing Unit Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x4 2. "Reserved,This bit is read as 1. The write value should be 1." "0,1" bitfld.long 0x4 1. "MSTPC1,Cyclic Redundancy Check Calculator Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" newline bitfld.long 0x4 0. "MSTPC0,Clock Frequency Accuracy Measurement Circuit Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" line.long 0x8 "MSTPCRD,Module Stop Control Register D" bitfld.long 0x8 31. "MSTPD31,Operational Amplifier Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x8 30. "Reserved,This bit is read as 1. The write value should be 1." "0,1" bitfld.long 0x8 29. "MSTPD29,Low-Power Analog Comparator Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" newline hexmask.long.byte 0x8 21.--28. 1. "Reserved,These bits are read as 11111111. The write value should be 11111111." bitfld.long 0x8 20. "MSTPD20,12-Bit D/A Converter Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x8 19. "MSTPD19,8-bit D/A Converter Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" newline bitfld.long 0x8 17.--18. "Reserved,These bits are read as 11. The write value should be 11." "0,1,2,3" bitfld.long 0x8 16. "MSTPD16,14-Bit A/D Converter Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x8 15. "Reserved,This bit is read as 1. The write value should be 1." "0,1" newline bitfld.long 0x8 14. "MSTPD14,Port Output Enable for GPT Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" hexmask.long.byte 0x8 7.--13. 1. "Reserved,These bits are read as 1111111. The write value should be 1111111." bitfld.long 0x8 6. "MSTPD6,General PWM Timer 169 to 164 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" newline bitfld.long 0x8 5. "MSTPD5,General PWM Timer 323 to 320 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x8 4. "Reserved,This bit is read as 1. The write value should be 1." "0,1" bitfld.long 0x8 3. "MSTPD3,Asynchronous General Purpose Timer 0 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" newline bitfld.long 0x8 2. "MSTPD2,Asynchronous General Purpose Timer 1 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" bitfld.long 0x8 0.--1. "Reserved,These bits are read as 11. The write value should be 11." "0,1,2,3" tree.end tree "OPAMP (Operational Amplifier)" base ad:0x40086000 group.byte 0x8++0x3 line.byte 0x0 "AMPMC,Operational amplifier mode control register" bitfld.byte 0x0 7. "AMPSP,Operation mode selection" "0: Low-power mode (low-speed).,1: High-speed mode." bitfld.byte 0x0 4.--6. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" newline bitfld.byte 0x0 3. "AMPPC3,Operational amplifier precharge control status" "0: Precharging is stopped.,1: Precharging is enabled." bitfld.byte 0x0 2. "AMPPC2,Operational amplifier precharge control status" "0: Precharging is stopped.,1: Precharging is enabled." newline bitfld.byte 0x0 1. "AMPPC1,Operational amplifier precharge control status" "0: Precharging is stopped.,1: Precharging is enabled." bitfld.byte 0x0 0. "AMPPC0,Operational amplifier precharge control status" "0: Precharging is stopped.,1: Precharging is enabled." line.byte 0x1 "AMPTRM,Operational amplifier trigger mode control register" bitfld.byte 0x1 7. "AMPTRM31,Operational amplifier function activation/stop trigger control" "0: Software trigger mode(AMPTRM30=0)/An activation..,1: Setting prohibited(AMPTRM30=0)/An activation and.." bitfld.byte 0x1 6. "AMPTRM30,Operational amplifier function activation/stop trigger control" "0: Software trigger mode(AMPTRM31=0)/Setting..,1: An activation trigger mode(AMPTRM31=0)/An.." newline bitfld.byte 0x1 5. "AMPTRM21,Operational amplifier function activation/stop trigger control" "0: Software trigger mode(AMPTRM20=0)/An activation..,1: Setting prohibited(AMPTRM20=0)/An activation and.." bitfld.byte 0x1 4. "AMPTRM20,Operational amplifier function activation/stop trigger control" "0: Software trigger mode(AMPTRM21=0)/Setting..,1: An activation trigger mode(AMPTRM21=0)/An.." newline bitfld.byte 0x1 3. "AMPTRM11,Operational amplifier function activation/stop trigger control" "0: Software trigger mode(AMPTRM10=0)/An activation..,1: Setting prohibited(AMPTRM10=0)/An activation and.." bitfld.byte 0x1 2. "AMPTRM10,Operational amplifier function activation/stop trigger control" "0: Software trigger mode(AMPTRM11=0)/Setting..,1: An activation trigger mode(AMPTRM11=0)/An.." newline bitfld.byte 0x1 1. "AMPTRM01,Operational amplifier function activation/stop trigger control" "0: Software trigger mode(AMPTRM00=0)/An activation..,1: Setting prohibited(AMPTRM00=0)/An activation and.." bitfld.byte 0x1 0. "AMPTRM00,Operational amplifier function activation/stop trigger control" "0: Software trigger mode(AMPTRM01=0)/Setting..,1: An activation trigger mode(AMPTRM01=0)/An.." line.byte 0x2 "AMPTRS,Operational Amplifier Activation Trigger Select Register" bitfld.byte 0x2 0.--1. "AMPTRS,ELC trigger selection Do not change the value of the AMPTRS register after setting the AMPTRM register." "0: Operational amplifier 0: Operational amplifier..,1: Operational amplifier 0: Operational amplifier..,?,?" line.byte 0x3 "AMPC,Operational amplifier control register" bitfld.byte 0x3 7. "IREFE,Operation control of operational amplifier reference current circuit" "0: Operational amplifier reference current circuit..,1: Operation of operational amplifier reference.." bitfld.byte 0x3 4.--6. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" newline bitfld.byte 0x3 3. "AMPE3,Operation control of operational amplifier(UNIT3)" "0: Operation amplifier is stopped.,1: Software trigger mode: Operation of operational.." bitfld.byte 0x3 2. "AMPE2,Operation control of operational amplifier(UNIT2)" "0: Operation amplifier is stopped.,1: Software trigger mode: Operation of operational.." newline bitfld.byte 0x3 1. "AMPE1,Operation control of operational amplifier(UNIT1)" "0: Operation amplifier is stopped.,1: Software trigger mode: Operation of operational.." bitfld.byte 0x3 0. "AMPE0,Operation control of operational amplifier(UNIT0)" "0: Operation amplifier is stopped.,1: Software trigger mode: Operation of operational.." rgroup.byte 0xC++0x0 line.byte 0x0 "AMPMON,Operational amplifier monitor register" hexmask.byte 0x0 4.--7. 1. "Reserved,These bits are read as 0000." bitfld.byte 0x0 3. "AMPMON3,Operational amplifier status(UNIT3)" "0: Operational amplifier 3 is stopped.,1: Operational amplifier 3 is operating." newline bitfld.byte 0x0 2. "AMPMON2,Operational amplifier status(UNIT2)" "0: Operational amplifier 2 is stopped.,1: Operational amplifier 2 is operating." bitfld.byte 0x0 1. "AMPMON1,Operational amplifier status(UNIT1)" "0: Operational amplifier 1 is stopped.,1: Operational amplifier 1 is operating." newline bitfld.byte 0x0 0. "AMPMON0,Operational amplifier status(UNIT0)" "0: Operational amplifier 0 is stopped.,1: Operational amplifier 0 is operating." tree.end tree "PFS (Pmn Pin Function Control)" base ad:0x40040800 group.long 0x0++0x3 line.long 0x0 "P000PFS,P000 Pin Function Control Register" bitfld.long 0x0 29.--31. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Port Function SelectThese bits select the peripheral function. For individual pin functions see the MPC table" newline hexmask.long.byte 0x0 17.--23. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Uses the pin as a general I/O pin.,1: Uses the pin as an I/O port for peripheral.." newline bitfld.long 0x0 15. "ASEL,Analog Input enable" "0: Used other than as analog pin,1: Used as analog pin" bitfld.long 0x0 14. "ISEL,IRQ input enable" "0: Not used as IRQn input pin,1: Used as IRQn input pin" newline bitfld.long 0x0 13. "EOF,Event on Failing" "0: No effected,1: Detect failing edge" bitfld.long 0x0 12. "EOR,Event on Rising" "0: No effected,1: Detect rising edge" newline bitfld.long 0x0 11. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 10. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive." newline bitfld.long 0x0 7.--9. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "NCODR,N-Channel Open Drain Control" "0: CMOS output,1: NMOS open-drain output" newline bitfld.long 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disables an input pull-up.,1: Enables an input pull-up." newline bitfld.long 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (Functions as an input pin.),1: Output (Functions as an output pin.)" newline rbitfld.long 0x0 1. "PIDR,Port Input Data" "0: Low input,1: High input" bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" group.word 0x2++0x1 line.word 0x0 "P000PFS_HA,P000 Pin Function Control Register" bitfld.word 0x0 15. "ASEL,Analog Input enable" "0: Used other than as analog pin,1: Used as analog pin" bitfld.word 0x0 14. "ISEL,IRQ input enable" "0: Not used as IRQn input pin,1: Used as IRQn input pin" newline bitfld.word 0x0 13. "EOF,Event on Failing" "0: No effected,1: Detect failing edge" bitfld.word 0x0 12. "EOR,Event on Rising" "0: No effected,1: Detect rising edge" newline bitfld.word 0x0 11. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x0 10. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive." newline bitfld.word 0x0 7.--9. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.word 0x0 6. "NCODR,N-Channel Open Drain Control" "0: CMOS output,1: NMOS open-drain output" newline bitfld.word 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x0 4. "PCR,Pull-up Control" "0: Disables an input pull-up.,1: Enables an input pull-up." newline bitfld.word 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x0 2. "PDR,Port Direction" "0: Input (Functions as an input pin.),1: Output (Functions as an output pin.)" newline rbitfld.word 0x0 1. "PIDR,Port Input Data" "0: Low input,1: High input" bitfld.word 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" group.byte 0x3++0x0 line.byte 0x0 "P000PFS_BY,P000 Pin Function Control Register" bitfld.byte 0x0 7. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 6. "NCODR,N-Channel Open Drain Control" "0: CMOS output,1: NMOS open-drain output" newline bitfld.byte 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 4. "PCR,Pull-up Control" "0: Disables an input pull-up.,1: Enables an input pull-up." newline bitfld.byte 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 2. "PDR,Port Direction" "0: Input (Functions as an input pin.),1: Output (Functions as an output pin.)" newline rbitfld.byte 0x0 1. "PIDR,Port Input Data" "0: Low input,1: High input" bitfld.byte 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat 9. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x4)++0x3 line.long 0x0 "P00$1PFS,P00%s Pin Function Control Register" bitfld.long 0x0 29.--31. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Port Function SelectThese bits select the peripheral function. For individual pin functions see the MPC table" newline hexmask.long.byte 0x0 17.--23. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Uses the pin as a general I/O pin.,1: Uses the pin as an I/O port for peripheral.." newline bitfld.long 0x0 15. "ASEL,Analog Input enable" "0: Used other than as analog pin,1: Used as analog pin" bitfld.long 0x0 14. "ISEL,IRQ input enable" "0: Not used as IRQn input pin,1: Used as IRQn input pin" newline bitfld.long 0x0 13. "EOF,Event on Failing" "0: No effected,1: Detect failing edge" bitfld.long 0x0 12. "EOR,Event on Rising" "0: No effected,1: Detect rising edge" newline bitfld.long 0x0 11. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 10. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive." newline bitfld.long 0x0 7.--9. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "NCODR,N-Channel Open Drain Control" "0: CMOS output,1: NMOS open-drain output" newline bitfld.long 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disables an input pull-up.,1: Enables an input pull-up." newline bitfld.long 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (Functions as an input pin.),1: Output (Functions as an output pin.)" newline rbitfld.long 0x0 1. "PIDR,Port Input Data" "0: Low input,1: High input" bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 9. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x6)++0x1 line.word 0x0 "P00$1PFS_HA,P00%s Pin Function Control Register" bitfld.word 0x0 15. "ASEL,Analog Input enable" "0: Used other than as analog pin,1: Used as analog pin" bitfld.word 0x0 14. "ISEL,IRQ input enable" "0: Not used as IRQn input pin,1: Used as IRQn input pin" newline bitfld.word 0x0 13. "EOF,Event on Failing" "0: No effected,1: Detect failing edge" bitfld.word 0x0 12. "EOR,Event on Rising" "0: No effected,1: Detect rising edge" newline bitfld.word 0x0 11. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x0 10. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive." newline bitfld.word 0x0 7.--9. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.word 0x0 6. "NCODR,N-Channel Open Drain Control" "0: CMOS output,1: NMOS open-drain output" newline bitfld.word 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x0 4. "PCR,Pull-up Control" "0: Disables an input pull-up.,1: Enables an input pull-up." newline bitfld.word 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x0 2. "PDR,Port Direction" "0: Input (Functions as an input pin.),1: Output (Functions as an output pin.)" newline rbitfld.word 0x0 1. "PIDR,Port Input Data" "0: Low input,1: High input" bitfld.word 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 9. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0x7)++0x0 line.byte 0x0 "P00$1PFS_BY,P00%s Pin Function Control Register" bitfld.byte 0x0 7. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 6. "NCODR,N-Channel Open Drain Control" "0: CMOS output,1: NMOS open-drain output" newline bitfld.byte 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 4. "PCR,Pull-up Control" "0: Disables an input pull-up.,1: Enables an input pull-up." newline bitfld.byte 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 2. "PDR,Port Direction" "0: Input (Functions as an input pin.),1: Output (Functions as an output pin.)" newline rbitfld.byte 0x0 1. "PIDR,Port Input Data" "0: Low input,1: High input" bitfld.byte 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x28)++0x3 line.long 0x0 "P0$1PFS,P0%s Pin Function Control Register" bitfld.long 0x0 29.--31. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Port Function SelectThese bits select the peripheral function. For individual pin functions see the MPC table" newline hexmask.long.byte 0x0 17.--23. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Uses the pin as a general I/O pin.,1: Uses the pin as an I/O port for peripheral.." newline bitfld.long 0x0 15. "ASEL,Analog Input enable" "0: Used other than as analog pin,1: Used as analog pin" bitfld.long 0x0 14. "ISEL,IRQ input enable" "0: Not used as IRQn input pin,1: Used as IRQn input pin" newline bitfld.long 0x0 13. "EOF,Event on Failing" "0: No effected,1: Detect failing edge" bitfld.long 0x0 12. "EOR,Event on Rising" "0: No effected,1: Detect rising edge" newline bitfld.long 0x0 11. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 10. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive." newline bitfld.long 0x0 7.--9. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "NCODR,N-Channel Open Drain Control" "0: CMOS output,1: NMOS open-drain output" newline bitfld.long 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disables an input pull-up.,1: Enables an input pull-up." newline bitfld.long 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (Functions as an input pin.),1: Output (Functions as an output pin.)" newline rbitfld.long 0x0 1. "PIDR,Port Input Data" "0: Low input,1: High input" bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x2A)++0x1 line.word 0x0 "P0$1PFS_HA,P0%s Pin Function Control Register" bitfld.word 0x0 15. "ASEL,Analog Input enable" "0: Used other than as analog pin,1: Used as analog pin" bitfld.word 0x0 14. "ISEL,IRQ input enable" "0: Not used as IRQn input pin,1: Used as IRQn input pin" newline bitfld.word 0x0 13. "EOF,Event on Failing" "0: No effected,1: Detect failing edge" bitfld.word 0x0 12. "EOR,Event on Rising" "0: No effected,1: Detect rising edge" newline bitfld.word 0x0 11. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x0 10. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive." newline bitfld.word 0x0 7.--9. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.word 0x0 6. "NCODR,N-Channel Open Drain Control" "0: CMOS output,1: NMOS open-drain output" newline bitfld.word 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x0 4. "PCR,Pull-up Control" "0: Disables an input pull-up.,1: Enables an input pull-up." newline bitfld.word 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x0 2. "PDR,Port Direction" "0: Input (Functions as an input pin.),1: Output (Functions as an output pin.)" newline rbitfld.word 0x0 1. "PIDR,Port Input Data" "0: Low input,1: High input" bitfld.word 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0x2B)++0x0 line.byte 0x0 "P0$1PFS_BY,P0%s Pin Function Control Register" bitfld.byte 0x0 7. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 6. "NCODR,N-Channel Open Drain Control" "0: CMOS output,1: NMOS open-drain output" newline bitfld.byte 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 4. "PCR,Pull-up Control" "0: Disables an input pull-up.,1: Enables an input pull-up." newline bitfld.byte 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 2. "PDR,Port Direction" "0: Input (Functions as an input pin.),1: Output (Functions as an output pin.)" newline rbitfld.byte 0x0 1. "PIDR,Port Input Data" "0: Low input,1: High input" bitfld.byte 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x40)++0x3 line.long 0x0 "P10$1PFS,P10%s Pin Function Control Register" bitfld.long 0x0 29.--31. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Port Function SelectThese bits select the peripheral function. For individual pin functions see the MPC table" newline hexmask.long.byte 0x0 17.--23. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Uses the pin as a general I/O pin.,1: Uses the pin as an I/O port for peripheral.." newline bitfld.long 0x0 15. "ASEL,Analog Input enable" "0: Used other than as analog pin,1: Used as analog pin" bitfld.long 0x0 14. "ISEL,IRQ input enable" "0: Not used as IRQn input pin,1: Used as IRQn input pin" newline bitfld.long 0x0 13. "EOF,Event on Failing" "0: No effected,1: Detect failing edge" bitfld.long 0x0 12. "EOR,Event on Rising" "0: No effected,1: Detect rising edge" newline bitfld.long 0x0 11. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 10. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive." newline bitfld.long 0x0 7.--9. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "NCODR,N-Channel Open Drain Control" "0: CMOS output,1: NMOS open-drain output" newline bitfld.long 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disables an input pull-up.,1: Enables an input pull-up." newline bitfld.long 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (Functions as an input pin.),1: Output (Functions as an output pin.)" newline rbitfld.long 0x0 1. "PIDR,Port Input Data" "0: Low input,1: High input" bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x42)++0x1 line.word 0x0 "P10$1PFS_HA,P10%s Pin Function Control Register" bitfld.word 0x0 15. "ASEL,Analog Input enable" "0: Used other than as analog pin,1: Used as analog pin" bitfld.word 0x0 14. "ISEL,IRQ input enable" "0: Not used as IRQn input pin,1: Used as IRQn input pin" newline bitfld.word 0x0 13. "EOF,Event on Failing" "0: No effected,1: Detect failing edge" bitfld.word 0x0 12. "EOR,Event on Rising" "0: No effected,1: Detect rising edge" newline bitfld.word 0x0 11. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x0 10. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive." newline bitfld.word 0x0 7.--9. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.word 0x0 6. "NCODR,N-Channel Open Drain Control" "0: CMOS output,1: NMOS open-drain output" newline bitfld.word 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x0 4. "PCR,Pull-up Control" "0: Disables an input pull-up.,1: Enables an input pull-up." newline bitfld.word 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x0 2. "PDR,Port Direction" "0: Input (Functions as an input pin.),1: Output (Functions as an output pin.)" newline rbitfld.word 0x0 1. "PIDR,Port Input Data" "0: Low input,1: High input" bitfld.word 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 8. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0x43)++0x0 line.byte 0x0 "P10$1PFS_BY,P10%s Pin Function Control Register" bitfld.byte 0x0 7. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 6. "NCODR,N-Channel Open Drain Control" "0: CMOS output,1: NMOS open-drain output" newline bitfld.byte 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 4. "PCR,Pull-up Control" "0: Disables an input pull-up.,1: Enables an input pull-up." newline bitfld.byte 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 2. "PDR,Port Direction" "0: Input (Functions as an input pin.),1: Output (Functions as an output pin.)" newline rbitfld.byte 0x0 1. "PIDR,Port Input Data" "0: Low input,1: High input" bitfld.byte 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end group.long 0x60++0x3 line.long 0x0 "P108PFS,P108 Pin Function Control Register" bitfld.long 0x0 29.--31. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Port Function Select These bits select the peripheral function. For individual pin functions see the setting table." newline hexmask.long.byte 0x0 17.--23. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Uses the pin as a general I/O pin.,1: Uses the pin as an I/O port for peripheral.." newline bitfld.long 0x0 15. "ASEL,Analog Input enable" "0: Used other than as analog pin,1: Used as analog pin" bitfld.long 0x0 14. "ISEL,IRQ input enable" "0: Not used as IRQn input pin,1: Used as IRQn input pin" newline bitfld.long 0x0 13. "EOF,Event on Failing" "0: No effected,1: Detect failing edge" bitfld.long 0x0 12. "EOR,Event on Rising" "0: No effected,1: Detect rising edge" newline bitfld.long 0x0 11. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 10. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive." newline bitfld.long 0x0 7.--9. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "NCODR,N-Channel Open Drain Control" "0: CMOS output,1: NMOS open-drain output" newline bitfld.long 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disables an input pull-up.,1: Enables an input pull-up." newline bitfld.long 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (Functions as an input pin.),1: Output (Functions as an output pin.)" newline rbitfld.long 0x0 1. "PIDR,Port Input Data" "0: Low input,1: High input" bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" group.word 0x62++0x1 line.word 0x0 "P108PFS_HA,P108 Pin Function Control Register" bitfld.word 0x0 15. "ASEL,Analog Input enable" "0: Used other than as analog pin,1: Used as analog pin" bitfld.word 0x0 14. "ISEL,IRQ input enable" "0: Not used as IRQn input pin,1: Used as IRQn input pin" newline bitfld.word 0x0 13. "EOF,Event on Failing" "0: No effected,1: Detect failing edge" bitfld.word 0x0 12. "EOR,Event on Rising" "0: No effected,1: Detect rising edge" newline bitfld.word 0x0 11. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x0 10. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive." newline bitfld.word 0x0 7.--9. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.word 0x0 6. "NCODR,N-Channel Open Drain Control" "0: CMOS output,1: NMOS open-drain output" newline bitfld.word 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x0 4. "PCR,Pull-up Control" "0: Disables an input pull-up.,1: Enables an input pull-up." newline bitfld.word 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x0 2. "PDR,Port Direction" "0: Input (Functions as an input pin.),1: Output (Functions as an output pin.)" newline rbitfld.word 0x0 1. "PIDR,Port Input Data" "0: Low input,1: High input" bitfld.word 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" group.byte 0x63++0x0 line.byte 0x0 "P108PFS_BY,P108 Pin Function Control Register" bitfld.byte 0x0 7. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 6. "NCODR,N-Channel Open Drain Control" "0: CMOS output,1: NMOS open-drain output" newline bitfld.byte 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 4. "PCR,Pull-up Control" "0: Disables an input pull-up.,1: Enables an input pull-up." newline bitfld.byte 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 2. "PDR,Port Direction" "0: Input (Functions as an input pin.),1: Output (Functions as an output pin.)" newline rbitfld.byte 0x0 1. "PIDR,Port Input Data" "0: Low input,1: High input" bitfld.byte 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" group.long 0x64++0x3 line.long 0x0 "P109PFS,P109 Pin Function Control Register" bitfld.long 0x0 29.--31. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Port Function Select These bits select the peripheral function. For individual pin functions see the setting table." newline hexmask.long.byte 0x0 17.--23. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Uses the pin as a general I/O pin.,1: Uses the pin as an I/O port for peripheral.." newline bitfld.long 0x0 15. "ASEL,Analog Input enable" "0: Used other than as analog pin,1: Used as analog pin" bitfld.long 0x0 14. "ISEL,IRQ input enable" "0: Not used as IRQn input pin,1: Used as IRQn input pin" newline bitfld.long 0x0 13. "EOF,Event on Failing" "0: No effected,1: Detect failing edge" bitfld.long 0x0 12. "EOR,Event on Rising" "0: No effected,1: Detect rising edge" newline bitfld.long 0x0 11. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 10. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive." newline bitfld.long 0x0 7.--9. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "NCODR,N-Channel Open Drain Control" "0: CMOS output,1: NMOS open-drain output" newline bitfld.long 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disables an input pull-up.,1: Enables an input pull-up." newline bitfld.long 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (Functions as an input pin.),1: Output (Functions as an output pin.)" newline rbitfld.long 0x0 1. "PIDR,Port Input Data" "0: Low input,1: High input" bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" group.word 0x66++0x1 line.word 0x0 "P109PFS_HA,P109 Pin Function Control Register" bitfld.word 0x0 15. "ASEL,Analog Input enable" "0: Used other than as analog pin,1: Used as analog pin" bitfld.word 0x0 14. "ISEL,IRQ input enable" "0: Not used as IRQn input pin,1: Used as IRQn input pin" newline bitfld.word 0x0 13. "EOF,Event on Failing" "0: No effected,1: Detect failing edge" bitfld.word 0x0 12. "EOR,Event on Rising" "0: No effected,1: Detect rising edge" newline bitfld.word 0x0 11. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x0 10. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive." newline bitfld.word 0x0 7.--9. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.word 0x0 6. "NCODR,N-Channel Open Drain Control" "0: CMOS output,1: NMOS open-drain output" newline bitfld.word 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x0 4. "PCR,Pull-up Control" "0: Disables an input pull-up.,1: Enables an input pull-up." newline bitfld.word 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x0 2. "PDR,Port Direction" "0: Input (Functions as an input pin.),1: Output (Functions as an output pin.)" newline rbitfld.word 0x0 1. "PIDR,Port Input Data" "0: Low input,1: High input" bitfld.word 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" group.byte 0x67++0x0 line.byte 0x0 "P109PFS_BY,P109 Pin Function Control Register" bitfld.byte 0x0 7. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 6. "NCODR,N-Channel Open Drain Control" "0: CMOS output,1: NMOS open-drain output" newline bitfld.byte 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 4. "PCR,Pull-up Control" "0: Disables an input pull-up.,1: Enables an input pull-up." newline bitfld.byte 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 2. "PDR,Port Direction" "0: Input (Functions as an input pin.),1: Output (Functions as an output pin.)" newline rbitfld.byte 0x0 1. "PIDR,Port Input Data" "0: Low input,1: High input" bitfld.byte 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" group.long 0x68++0x3 line.long 0x0 "P110PFS,P110 Pin Function Control Register" bitfld.long 0x0 29.--31. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Port Function Select These bits select the peripheral function. For individual pin functions see the setting table." newline hexmask.long.byte 0x0 17.--23. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Uses the pin as a general I/O pin.,1: Uses the pin as an I/O port for peripheral.." newline bitfld.long 0x0 15. "ASEL,Analog Input enable" "0: Used other than as analog pin,1: Used as analog pin" bitfld.long 0x0 14. "ISEL,IRQ input enable" "0: Not used as IRQn input pin,1: Used as IRQn input pin" newline bitfld.long 0x0 13. "EOF,Event on Failing" "0: No effected,1: Detect failing edge" bitfld.long 0x0 12. "EOR,Event on Rising" "0: No effected,1: Detect rising edge" newline bitfld.long 0x0 11. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 10. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive." newline bitfld.long 0x0 7.--9. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "NCODR,N-Channel Open Drain Control" "0: CMOS output,1: NMOS open-drain output" newline bitfld.long 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disables an input pull-up.,1: Enables an input pull-up." newline bitfld.long 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (Functions as an input pin.),1: Output (Functions as an output pin.)" newline rbitfld.long 0x0 1. "PIDR,Port Input Data" "0: Low input,1: High input" bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" group.word 0x6A++0x1 line.word 0x0 "P110PFS_HA,P110 Pin Function Control Register" bitfld.word 0x0 15. "ASEL,Analog Input enable" "0: Used other than as analog pin,1: Used as analog pin" bitfld.word 0x0 14. "ISEL,IRQ input enable" "0: Not used as IRQn input pin,1: Used as IRQn input pin" newline bitfld.word 0x0 13. "EOF,Event on Failing" "0: No effected,1: Detect failing edge" bitfld.word 0x0 12. "EOR,Event on Rising" "0: No effected,1: Detect rising edge" newline bitfld.word 0x0 11. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x0 10. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive." newline bitfld.word 0x0 7.--9. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.word 0x0 6. "NCODR,N-Channel Open Drain Control" "0: CMOS output,1: NMOS open-drain output" newline bitfld.word 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x0 4. "PCR,Pull-up Control" "0: Disables an input pull-up.,1: Enables an input pull-up." newline bitfld.word 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x0 2. "PDR,Port Direction" "0: Input (Functions as an input pin.),1: Output (Functions as an output pin.)" newline rbitfld.word 0x0 1. "PIDR,Port Input Data" "0: Low input,1: High input" bitfld.word 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" group.byte 0x6B++0x0 line.byte 0x0 "P110PFS_BY,P110 Pin Function Control Register" bitfld.byte 0x0 7. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 6. "NCODR,N-Channel Open Drain Control" "0: CMOS output,1: NMOS open-drain output" newline bitfld.byte 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 4. "PCR,Pull-up Control" "0: Disables an input pull-up.,1: Enables an input pull-up." newline bitfld.byte 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 2. "PDR,Port Direction" "0: Input (Functions as an input pin.),1: Output (Functions as an output pin.)" newline rbitfld.byte 0x0 1. "PIDR,Port Input Data" "0: Low input,1: High input" bitfld.byte 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat 5. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x6C)++0x3 line.long 0x0 "P1$1PFS,P1%s Pin Function Control Register" bitfld.long 0x0 29.--31. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Port Function SelectThese bits select the peripheral function. For individual pin functions see the MPC table" newline hexmask.long.byte 0x0 17.--23. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Uses the pin as a general I/O pin.,1: Uses the pin as an I/O port for peripheral.." newline bitfld.long 0x0 15. "ASEL,Analog Input enable" "0: Used other than as analog pin,1: Used as analog pin" bitfld.long 0x0 14. "ISEL,IRQ input enable" "0: Not used as IRQn input pin,1: Used as IRQn input pin" newline bitfld.long 0x0 13. "EOF,Event on Failing" "0: No effected,1: Detect failing edge" bitfld.long 0x0 12. "EOR,Event on Rising" "0: No effected,1: Detect rising edge" newline bitfld.long 0x0 11. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 10. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive." newline bitfld.long 0x0 7.--9. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "NCODR,N-Channel Open Drain Control" "0: CMOS output,1: NMOS open-drain output" newline bitfld.long 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disables an input pull-up.,1: Enables an input pull-up." newline bitfld.long 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (Functions as an input pin.),1: Output (Functions as an output pin.)" newline rbitfld.long 0x0 1. "PIDR,Port Input Data" "0: Low input,1: High input" bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 5. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x6E)++0x1 line.word 0x0 "P1$1PFS_HA,P1%s Pin Function Control Register" bitfld.word 0x0 15. "ASEL,Analog Input enable" "0: Used other than as analog pin,1: Used as analog pin" bitfld.word 0x0 14. "ISEL,IRQ input enable" "0: Not used as IRQn input pin,1: Used as IRQn input pin" newline bitfld.word 0x0 13. "EOF,Event on Failing" "0: No effected,1: Detect failing edge" bitfld.word 0x0 12. "EOR,Event on Rising" "0: No effected,1: Detect rising edge" newline bitfld.word 0x0 11. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x0 10. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive." newline bitfld.word 0x0 7.--9. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.word 0x0 6. "NCODR,N-Channel Open Drain Control" "0: CMOS output,1: NMOS open-drain output" newline bitfld.word 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x0 4. "PCR,Pull-up Control" "0: Disables an input pull-up.,1: Enables an input pull-up." newline bitfld.word 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x0 2. "PDR,Port Direction" "0: Input (Functions as an input pin.),1: Output (Functions as an output pin.)" newline rbitfld.word 0x0 1. "PIDR,Port Input Data" "0: Low input,1: High input" bitfld.word 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 5. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0x6F)++0x0 line.byte 0x0 "P1$1PFS_BY,P1%s Pin Function Control Register" bitfld.byte 0x0 7. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 6. "NCODR,N-Channel Open Drain Control" "0: CMOS output,1: NMOS open-drain output" newline bitfld.byte 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 4. "PCR,Pull-up Control" "0: Disables an input pull-up.,1: Enables an input pull-up." newline bitfld.byte 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 2. "PDR,Port Direction" "0: Input (Functions as an input pin.),1: Output (Functions as an output pin.)" newline rbitfld.byte 0x0 1. "PIDR,Port Input Data" "0: Low input,1: High input" bitfld.byte 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end group.long 0x80++0x3 line.long 0x0 "P200PFS,P200 Pin Function Control Register" bitfld.long 0x0 29.--31. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Port Function SelectThese bits select the peripheral function. For individual pin functions see the MPC table" newline hexmask.long.byte 0x0 17.--23. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Uses the pin as a general I/O pin.,1: Uses the pin as an I/O port for peripheral.." newline bitfld.long 0x0 15. "ASEL,Analog Input enable" "0: Used other than as analog pin,1: Used as analog pin" bitfld.long 0x0 14. "ISEL,IRQ input enable" "0: Not used as IRQn input pin,1: Used as IRQn input pin" newline bitfld.long 0x0 13. "EOF,Event on Failing" "0: No effected,1: Detect failing edge" bitfld.long 0x0 12. "EOR,Event on Rising" "0: No effected,1: Detect rising edge" newline bitfld.long 0x0 11. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 10. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive." newline bitfld.long 0x0 7.--9. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "NCODR,N-Channel Open Drain Control" "0: CMOS output,1: NMOS open-drain output" newline bitfld.long 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disables an input pull-up.,1: Enables an input pull-up." newline bitfld.long 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (Functions as an input pin.),1: Output (Functions as an output pin.)" newline rbitfld.long 0x0 1. "PIDR,Port Input Data" "0: Low input,1: High input" bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" group.word 0x82++0x1 line.word 0x0 "P200PFS_HA,P200 Pin Function Control Register" bitfld.word 0x0 15. "ASEL,Analog Input enable" "0: Used other than as analog pin,1: Used as analog pin" bitfld.word 0x0 14. "ISEL,IRQ input enable" "0: Not used as IRQn input pin,1: Used as IRQn input pin" newline bitfld.word 0x0 13. "EOF,Event on Failing" "0: No effected,1: Detect failing edge" bitfld.word 0x0 12. "EOR,Event on Rising" "0: No effected,1: Detect rising edge" newline bitfld.word 0x0 11. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x0 10. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive." newline bitfld.word 0x0 7.--9. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.word 0x0 6. "NCODR,N-Channel Open Drain Control" "0: CMOS output,1: NMOS open-drain output" newline bitfld.word 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x0 4. "PCR,Pull-up Control" "0: Disables an input pull-up.,1: Enables an input pull-up." newline bitfld.word 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x0 2. "PDR,Port Direction" "0: Input (Functions as an input pin.),1: Output (Functions as an output pin.)" newline rbitfld.word 0x0 1. "PIDR,Port Input Data" "0: Low input,1: High input" bitfld.word 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" group.byte 0x83++0x0 line.byte 0x0 "P200PFS_BY,P200 Pin Function Control Register" bitfld.byte 0x0 7. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 6. "NCODR,N-Channel Open Drain Control" "0: CMOS output,1: NMOS open-drain output" newline bitfld.byte 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 4. "PCR,Pull-up Control" "0: Disables an input pull-up.,1: Enables an input pull-up." newline bitfld.byte 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 2. "PDR,Port Direction" "0: Input (Functions as an input pin.),1: Output (Functions as an output pin.)" newline rbitfld.byte 0x0 1. "PIDR,Port Input Data" "0: Low input,1: High input" bitfld.byte 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" group.long 0x84++0x3 line.long 0x0 "P201PFS,P201 Pin Function Control Register" bitfld.long 0x0 29.--31. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Port Function Select These bits select the peripheral function. For individual pin functions see the setting table." newline hexmask.long.byte 0x0 17.--23. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Uses the pin as a general I/O pin.,1: Uses the pin as an I/O port for peripheral.." newline bitfld.long 0x0 15. "ASEL,Analog Input enable" "0: Used other than as analog pin,1: Used as analog pin" bitfld.long 0x0 14. "ISEL,IRQ input enable" "0: Not used as IRQn input pin,1: Used as IRQn input pin" newline bitfld.long 0x0 13. "EOF,Event on Falling" "0: Do not care,1: Detect falling edge" bitfld.long 0x0 12. "EOR,Event on Rising" "0: Do not care,1: Detect rising edge" newline bitfld.long 0x0 11. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 10. "DSCR,Drive Strength Control Register" "0: Low drive,1: High drive" newline bitfld.long 0x0 7.--9. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "NCODR,N-Channel Open Drain Control" "0: CMOS output,1: NMOS open-drain output" newline bitfld.long 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disables an input pull-up.,1: Enables an input pull-up." newline bitfld.long 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (Functions as an input pin.),1: Output (Functions as an output pin.)" newline rbitfld.long 0x0 1. "PIDR,Port Input Data" "0: Low input,1: High input" bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" group.word 0x86++0x1 line.word 0x0 "P201PFS_HA,P201 Pin Function Control Register" bitfld.word 0x0 15. "ASEL,Analog Input enable" "0: Used other than as analog pin,1: Used as analog pin" bitfld.word 0x0 14. "ISEL,IRQ input enable" "0: Not used as IRQn input pin,1: Used as IRQn input pin" newline bitfld.word 0x0 13. "EOF,Event on Falling" "0: Do not care,1: Detect falling edge" bitfld.word 0x0 12. "EOR,Event on Rising" "0: Do not care,1: Detect rising edge" newline bitfld.word 0x0 11. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x0 10. "DSCR,Drive Strength Control Register" "0: Low drive,1: High drive" newline bitfld.word 0x0 7.--9. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.word 0x0 6. "NCODR,N-Channel Open Drain Control" "0: CMOS output,1: NMOS open-drain output" newline bitfld.word 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x0 4. "PCR,Pull-up Control" "0: Disables an input pull-up.,1: Enables an input pull-up." newline bitfld.word 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x0 2. "PDR,Port Direction" "0: Input (Functions as an input pin.),1: Output (Functions as an output pin.)" newline rbitfld.word 0x0 1. "PIDR,Port Input Data" "0: Low input,1: High input" bitfld.word 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" group.byte 0x87++0x0 line.byte 0x0 "P201PFS_BY,P201 Pin Function Control Register" bitfld.byte 0x0 7. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 6. "NCODR,N-Channel Open Drain Control" "0: CMOS output,1: NMOS open-drain output" newline bitfld.byte 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 4. "PCR,Pull-up Control" "0: Disables an input pull-up.,1: Enables an input pull-up." newline bitfld.byte 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 2. "PDR,Port Direction" "0: Input (Functions as an input pin.),1: Output (Functions as an output pin.)" newline rbitfld.byte 0x0 1. "PIDR,Port Input Data" "0: Low input,1: High input" bitfld.byte 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat 5. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0x88)++0x3 line.long 0x0 "P20$1PFS,P20%s Pin Function Control Register" bitfld.long 0x0 29.--31. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Port Function SelectThese bits select the peripheral function. For individual pin functions see the MPC table" newline hexmask.long.byte 0x0 17.--23. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Uses the pin as a general I/O pin.,1: Uses the pin as an I/O port for peripheral.." newline bitfld.long 0x0 15. "ASEL,Analog Input enable" "0: Used other than as analog pin,1: Used as analog pin" bitfld.long 0x0 14. "ISEL,IRQ input enable" "0: Not used as IRQn input pin,1: Used as IRQn input pin" newline bitfld.long 0x0 13. "EOF,Event on Failing" "0: No effected,1: Detect failing edge" bitfld.long 0x0 12. "EOR,Event on Rising" "0: No effected,1: Detect rising edge" newline bitfld.long 0x0 11. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 10. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive." newline bitfld.long 0x0 7.--9. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "NCODR,N-Channel Open Drain Control" "0: CMOS output,1: NMOS open-drain output" newline bitfld.long 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disables an input pull-up.,1: Enables an input pull-up." newline bitfld.long 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (Functions as an input pin.),1: Output (Functions as an output pin.)" newline rbitfld.long 0x0 1. "PIDR,Port Input Data" "0: Low input,1: High input" bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 5. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x8A)++0x1 line.word 0x0 "P20$1PFS_HA,P20%s Pin Function Control Register" bitfld.word 0x0 15. "ASEL,Analog Input enable" "0: Used other than as analog pin,1: Used as analog pin" bitfld.word 0x0 14. "ISEL,IRQ input enable" "0: Not used as IRQn input pin,1: Used as IRQn input pin" newline bitfld.word 0x0 13. "EOF,Event on Failing" "0: No effected,1: Detect failing edge" bitfld.word 0x0 12. "EOR,Event on Rising" "0: No effected,1: Detect rising edge" newline bitfld.word 0x0 11. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x0 10. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive." newline bitfld.word 0x0 7.--9. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.word 0x0 6. "NCODR,N-Channel Open Drain Control" "0: CMOS output,1: NMOS open-drain output" newline bitfld.word 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x0 4. "PCR,Pull-up Control" "0: Disables an input pull-up.,1: Enables an input pull-up." newline bitfld.word 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x0 2. "PDR,Port Direction" "0: Input (Functions as an input pin.),1: Output (Functions as an output pin.)" newline rbitfld.word 0x0 1. "PIDR,Port Input Data" "0: Low input,1: High input" bitfld.word 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 5. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0x8B)++0x0 line.byte 0x0 "P20$1PFS_BY,P20%s Pin Function Control Register" bitfld.byte 0x0 7. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 6. "NCODR,N-Channel Open Drain Control" "0: CMOS output,1: NMOS open-drain output" newline bitfld.byte 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 4. "PCR,Pull-up Control" "0: Disables an input pull-up.,1: Enables an input pull-up." newline bitfld.byte 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 2. "PDR,Port Direction" "0: Input (Functions as an input pin.),1: Output (Functions as an output pin.)" newline rbitfld.byte 0x0 1. "PIDR,Port Input Data" "0: Low input,1: High input" bitfld.byte 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.long ($2+0xB0)++0x3 line.long 0x0 "P2$1PFS,P2%s Pin Function Control Register" bitfld.long 0x0 29.--31. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Port Function SelectThese bits select the peripheral function. For individual pin functions see the MPC table" newline hexmask.long.byte 0x0 17.--23. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Uses the pin as a general I/O pin.,1: Uses the pin as an I/O port for peripheral.." newline bitfld.long 0x0 15. "ASEL,Analog Input enable" "0: Used other than as analog pin,1: Used as analog pin" bitfld.long 0x0 14. "ISEL,IRQ input enable" "0: Not used as IRQn input pin,1: Used as IRQn input pin" newline bitfld.long 0x0 13. "EOF,Event on Failing" "0: No effected,1: Detect failing edge" bitfld.long 0x0 12. "EOR,Event on Rising" "0: No effected,1: Detect rising edge" newline bitfld.long 0x0 11. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 10. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive." newline bitfld.long 0x0 7.--9. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "NCODR,N-Channel Open Drain Control" "0: CMOS output,1: NMOS open-drain output" newline bitfld.long 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disables an input pull-up.,1: Enables an input pull-up." newline bitfld.long 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (Functions as an input pin.),1: Output (Functions as an output pin.)" newline rbitfld.long 0x0 1. "PIDR,Port Input Data" "0: Low input,1: High input" bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0xB2)++0x1 line.word 0x0 "P2$1PFS_HA,P2%s Pin Function Control Register" bitfld.word 0x0 15. "ASEL,Analog Input enable" "0: Used other than as analog pin,1: Used as analog pin" bitfld.word 0x0 14. "ISEL,IRQ input enable" "0: Not used as IRQn input pin,1: Used as IRQn input pin" newline bitfld.word 0x0 13. "EOF,Event on Failing" "0: No effected,1: Detect failing edge" bitfld.word 0x0 12. "EOR,Event on Rising" "0: No effected,1: Detect rising edge" newline bitfld.word 0x0 11. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x0 10. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive." newline bitfld.word 0x0 7.--9. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.word 0x0 6. "NCODR,N-Channel Open Drain Control" "0: CMOS output,1: NMOS open-drain output" newline bitfld.word 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x0 4. "PCR,Pull-up Control" "0: Disables an input pull-up.,1: Enables an input pull-up." newline bitfld.word 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x0 2. "PDR,Port Direction" "0: Input (Functions as an input pin.),1: Output (Functions as an output pin.)" newline rbitfld.word 0x0 1. "PIDR,Port Input Data" "0: Low input,1: High input" bitfld.word 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x4) group.byte ($2+0xB3)++0x0 line.byte 0x0 "P2$1PFS_BY,P2%s Pin Function Control Register" bitfld.byte 0x0 7. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 6. "NCODR,N-Channel Open Drain Control" "0: CMOS output,1: NMOS open-drain output" newline bitfld.byte 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 4. "PCR,Pull-up Control" "0: Disables an input pull-up.,1: Enables an input pull-up." newline bitfld.byte 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 2. "PDR,Port Direction" "0: Input (Functions as an input pin.),1: Output (Functions as an output pin.)" newline rbitfld.byte 0x0 1. "PIDR,Port Input Data" "0: Low input,1: High input" bitfld.byte 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" repeat.end group.long 0xC0++0x3 line.long 0x0 "P300PFS,P300 Pin Function Control Register" bitfld.long 0x0 29.--31. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "PSEL,Port Function Select These bits select the peripheral function. For individual pin functions see the setting table." newline hexmask.long.byte 0x0 17.--23. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Uses the pin as a general I/O pin.,1: Uses the pin as an I/O port for peripheral.." newline bitfld.long 0x0 15. "ASEL,Analog Input enable" "0: Used other than as analog pin,1: Used as analog pin" bitfld.long 0x0 14. "ISEL,IRQ input enable" "0: Not used as IRQn input pin,1: Used as IRQn input pin" newline bitfld.long 0x0 13. "EOF,Event on Failing" "0: No effected,1: Detect failing edge" bitfld.long 0x0 12. "EOR,Event on Rising" "0: No effected,1: Detect rising edge" newline bitfld.long 0x0 11. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 10. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive." newline bitfld.long 0x0 7.--9. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.long 0x0 6. "NCODR,N-Channel Open Drain Control" "0: CMOS output,1: NMOS open-drain output" newline bitfld.long 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disables an input pull-up.,1: Enables an input pull-up." newline bitfld.long 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (Functions as an input pin.),1: Output (Functions as an output pin.)" newline rbitfld.long 0x0 1. "PIDR,Port Input Data" "0: Low input,1: High input" bitfld.long 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" group.word 0xC2++0x1 line.word 0x0 "P300PFS_HA,P300 Pin Function Control Register" bitfld.word 0x0 15. "ASEL,Analog Input enable" "0: Used other than as analog pin,1: Used as analog pin" bitfld.word 0x0 14. "ISEL,IRQ input enable" "0: Not used as IRQn input pin,1: Used as IRQn input pin" newline bitfld.word 0x0 13. "EOF,Event on Failing" "0: No effected,1: Detect failing edge" bitfld.word 0x0 12. "EOR,Event on Rising" "0: No effected,1: Detect rising edge" newline bitfld.word 0x0 11. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x0 10. "DSCR,Port Drive Capability" "0: Low drive,1: Middle drive." newline bitfld.word 0x0 7.--9. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.word 0x0 6. "NCODR,N-Channel Open Drain Control" "0: CMOS output,1: NMOS open-drain output" newline bitfld.word 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x0 4. "PCR,Pull-up Control" "0: Disables an input pull-up.,1: Enables an input pull-up." newline bitfld.word 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x0 2. "PDR,Port Direction" "0: Input (Functions as an input pin.),1: Output (Functions as an output pin.)" newline rbitfld.word 0x0 1. "PIDR,Port Input Data" "0: Low input,1: High input" bitfld.word 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" group.byte 0xC3++0x0 line.byte 0x0 "P300PFS_BY,P300 Pin Function Control Register" bitfld.byte 0x0 7. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 6. "NCODR,N-Channel Open Drain Control" "0: CMOS output,1: NMOS open-drain output" newline bitfld.byte 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 4. "PCR,Pull-up Control" "0: Disables an input pull-up.,1: Enables an input pull-up." newline bitfld.byte 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 2. "PDR,Port Direction" "0: Input (Functions as an input pin.),1: Output (Functions as an output pin.)" newline rbitfld.byte 0x0 1. "PIDR,Port Input Data" "0: Low input,1: High input" bitfld.byte 0x0 0. "PODR,Port Output Data" "0: Low output,1: High output" tree.end tree "PMISC (Miscellaneous Port Control)" base ad:0x40040D00 group.byte 0x3++0x0 line.byte 0x0 "PWPR,Write-Protect Register" bitfld.byte 0x0 7. "B0WI,PFSWE Bit Write Disable" "0: Writing to the PFSWE bit is enabled,1: Writing to the PFSWE bit is disabled" bitfld.byte 0x0 6. "PFSWE,PFS Register Write Enable" "0: Writing to the PFS register is disabled,1: Writing to the PFS register is enabled" hexmask.byte 0x0 0.--5. 1. "Reserved,These bits are read as 000000. The write value should be 000000." tree.end tree "POEG (Port Output Enable Module for GPT)" base ad:0x40042000 repeat 2. (increment 0x0 0x1)(increment 0x0 0x100) group.long ($2)++0x3 line.long 0x0 "POEGG$1,POEG Group %s Setting Register" bitfld.long 0x0 30.--31. "NFCS,Noise Filter Clock Select" "0: Sampling GTETRG pin input level for three times..,1: Sampling GTETRG pin input level for three times..,?,?" bitfld.long 0x0 29. "NFEN,Noise Filter Enable" "0: Filtering noise disabled,1: Filtering noise enabled" newline bitfld.long 0x0 28. "INV,GTETRG Input Reverse" "0: GTETRG Input,1: GTETRG Input Reversed." hexmask.long.word 0x0 17.--27. 1. "Reserved,These bits are read as 00000000000. The write value should be 00000000000." newline rbitfld.long 0x0 16. "ST,GTETRG Input Status Flag" "0: GTETRG input after filtering is 0.,1: GTETRG input after filtering is 1." bitfld.long 0x0 6. "OSTPE,Oscillation Stop Detection EnableNote: Can be modified only once after a reset." "0: A output-disable request from the oscillation..,1: A output-disable request from the oscillation.." newline bitfld.long 0x0 5. "IOCE,Output-disable Request Enable from GPTNote: Can be modified only once after a reset." "0: Output-disable request from the GPT disable..,1: Output-disable request from the GPT disable.." bitfld.long 0x0 4. "PIDE,Port Input Detection EnableNote: Can be modified only once after a reset." "0: Output-disable request from the GTETRG pins..,1: Output-disable request from the GTETRG pins.." newline bitfld.long 0x0 3. "SSF,Software Stop Flag" "0: No output-disable request from software has..,1: Output-disable request from software occurred." bitfld.long 0x0 2. "OSTPF,Oscillation Stop Detection Flag" "0: No output-disable request from oscillation stop..,1: Output-disable request from oscillation stop.." newline bitfld.long 0x0 1. "IOCF,Output-disable Request Detection Flag from GPT" "0: No output-disable request from the GPT disable..,1: Output-disable request from the GPT disable.." bitfld.long 0x0 0. "PIDF,Port Input Detection Flag" "0: No output-disable request from the GTETRGn pin..,1: Output-disable request from the GTETRGn pin.." repeat.end tree.end tree "PORT (Port Control)" base ad:0x0 tree "PORT0" base ad:0x40040000 group.long 0x0++0x3 line.long 0x0 "PCNTR1,Port Control Register 1" hexmask.long.word 0x0 16.--31. 1. "PODR,Pmn Output Data" hexmask.long.word 0x0 0.--15. 1. "PDR,Pmn Direction" group.word 0x0++0x3 line.word 0x0 "PODR,Output data register" hexmask.word 0x0 0.--15. 1. "PODR,Pmn Output Data" line.word 0x2 "PDR,Data direction register" hexmask.word 0x2 0.--15. 1. "PDR,Pmn Direction" rgroup.long 0x4++0x3 line.long 0x0 "PCNTR2,Port Control Register 2" hexmask.long.word 0x0 16.--31. 1. "EIDR,Pmn Event Input Data" hexmask.long.word 0x0 0.--15. 1. "PIDR,Pmn Input Data" rgroup.word 0x6++0x1 line.word 0x0 "PIDR,Input data register" hexmask.word 0x0 0.--15. 1. "PIDR,Pmn Input Data" wgroup.long 0x8++0x3 line.long 0x0 "PCNTR3,Port Control Register 3" hexmask.long.word 0x0 16.--31. 1. "PORR,Pmn Output Reset" hexmask.long.word 0x0 0.--15. 1. "POSR,Pmn Output Set" wgroup.word 0x8++0x3 line.word 0x0 "PORR,Output reset register" hexmask.word 0x0 0.--15. 1. "PORR,Pmn Output Reset" line.word 0x2 "POSR,Output set register" hexmask.word 0x2 0.--15. 1. "POSR,Pmn Output Set" tree.end tree "PORT1" base ad:0x40040020 group.long 0x0++0x3 line.long 0x0 "PCNTR1,Port Control Register 1" hexmask.long.word 0x0 16.--31. 1. "PODR,Pmn Output Data" hexmask.long.word 0x0 0.--15. 1. "PDR,Pmn Direction" group.word 0x0++0x3 line.word 0x0 "PODR,Output data register" hexmask.word 0x0 0.--15. 1. "PODR,Pmn Output Data" line.word 0x2 "PDR,Data direction register" hexmask.word 0x2 0.--15. 1. "PDR,Pmn Direction" rgroup.long 0x4++0x3 line.long 0x0 "PCNTR2,Port Control Register 2" hexmask.long.word 0x0 16.--31. 1. "EIDR,Pmn Event Input Data" hexmask.long.word 0x0 0.--15. 1. "PIDR,Pmn Input Data" rgroup.word 0x4++0x3 line.word 0x0 "EIDR,Event input data register" hexmask.word 0x0 0.--15. 1. "EIDR,Pmn Event Input Data" line.word 0x2 "PIDR,Input data register" hexmask.word 0x2 0.--15. 1. "PIDR,Pmn Input Data" wgroup.long 0x8++0x3 line.long 0x0 "PCNTR3,Port Control Register 3" hexmask.long.word 0x0 16.--31. 1. "PORR,Pmn Output Reset" hexmask.long.word 0x0 0.--15. 1. "POSR,Pmn Output Set" wgroup.word 0x8++0x3 line.word 0x0 "PORR,Output set register" hexmask.word 0x0 0.--15. 1. "PORR,Pmn Output Reset" line.word 0x2 "POSR,Output reset register" hexmask.word 0x2 0.--15. 1. "POSR,Pmn Output Set" group.long 0xC++0x3 line.long 0x0 "PCNTR4,Port Control Register 4" hexmask.long.word 0x0 16.--31. 1. "EORR,Pmn Event Output Reset" hexmask.long.word 0x0 0.--15. 1. "EOSR,Pmn Event Output Set" group.word 0xC++0x3 line.word 0x0 "EORR,Event output set register" hexmask.word 0x0 0.--15. 1. "EORR,Pmn Event Output Reset" line.word 0x2 "EOSR,Event output reset register" hexmask.word 0x2 0.--15. 1. "EOSR,Pmn Event Output Set" tree.end tree "PORT2" base ad:0x40040040 group.long 0x0++0x3 line.long 0x0 "PCNTR1,Port Control Register 1" hexmask.long.word 0x0 16.--31. 1. "PODR,Pmn Output Data" hexmask.long.word 0x0 0.--15. 1. "PDR,Pmn Direction" group.word 0x0++0x3 line.word 0x0 "PODR,Output data register" hexmask.word 0x0 0.--15. 1. "PODR,Pmn Output Data" line.word 0x2 "PDR,Data direction register" hexmask.word 0x2 0.--15. 1. "PDR,Pmn Direction" rgroup.long 0x4++0x3 line.long 0x0 "PCNTR2,Port Control Register 2" hexmask.long.word 0x0 16.--31. 1. "EIDR,Pmn Event Input Data" hexmask.long.word 0x0 0.--15. 1. "PIDR,Pmn Input Data" rgroup.word 0x4++0x3 line.word 0x0 "EIDR,Event input data register" hexmask.word 0x0 0.--15. 1. "EIDR,Pmn Event Input Data" line.word 0x2 "PIDR,Input data register" hexmask.word 0x2 0.--15. 1. "PIDR,Pmn Input Data" wgroup.long 0x8++0x3 line.long 0x0 "PCNTR3,Port Control Register 3" hexmask.long.word 0x0 16.--31. 1. "PORR,Pmn Output Reset" hexmask.long.word 0x0 0.--15. 1. "POSR,Pmn Output Set" wgroup.word 0x8++0x3 line.word 0x0 "PORR,Output set register" hexmask.word 0x0 0.--15. 1. "PORR,Pmn Output Reset" line.word 0x2 "POSR,Output reset register" hexmask.word 0x2 0.--15. 1. "POSR,Pmn Output Set" group.long 0xC++0x3 line.long 0x0 "PCNTR4,Port Control Register 4" hexmask.long.word 0x0 16.--31. 1. "EORR,Pmn Event Output Reset" hexmask.long.word 0x0 0.--15. 1. "EOSR,Pmn Event Output Set" group.word 0xC++0x3 line.word 0x0 "EORR,Event output set register" hexmask.word 0x0 0.--15. 1. "EORR,Pmn Event Output Reset" line.word 0x2 "EOSR,Event output reset register" hexmask.word 0x2 0.--15. 1. "EOSR,Pmn Event Output Set" tree.end tree "PORT3" base ad:0x40040060 group.long 0x0++0x3 line.long 0x0 "PCNTR1,Port Control Register 1" hexmask.long.word 0x0 16.--31. 1. "PODR,Pmn Output Data" hexmask.long.word 0x0 0.--15. 1. "PDR,Pmn Direction" group.word 0x0++0x3 line.word 0x0 "PODR,Output data register" hexmask.word 0x0 0.--15. 1. "PODR,Pmn Output Data" line.word 0x2 "PDR,Data direction register" hexmask.word 0x2 0.--15. 1. "PDR,Pmn Direction" rgroup.long 0x4++0x3 line.long 0x0 "PCNTR2,Port Control Register 2" hexmask.long.word 0x0 16.--31. 1. "EIDR,Pmn Event Input Data" hexmask.long.word 0x0 0.--15. 1. "PIDR,Pmn Input Data" rgroup.word 0x4++0x3 line.word 0x0 "EIDR,Event input data register" hexmask.word 0x0 0.--15. 1. "EIDR,Pmn Event Input Data" line.word 0x2 "PIDR,Input data register" hexmask.word 0x2 0.--15. 1. "PIDR,Pmn Input Data" wgroup.long 0x8++0x3 line.long 0x0 "PCNTR3,Port Control Register 3" hexmask.long.word 0x0 16.--31. 1. "PORR,Pmn Output Reset" hexmask.long.word 0x0 0.--15. 1. "POSR,Pmn Output Set" wgroup.word 0x8++0x3 line.word 0x0 "PORR,Output set register" hexmask.word 0x0 0.--15. 1. "PORR,Pmn Output Reset" line.word 0x2 "POSR,Output reset register" hexmask.word 0x2 0.--15. 1. "POSR,Pmn Output Set" group.long 0xC++0x3 line.long 0x0 "PCNTR4,Port Control Register 4" hexmask.long.word 0x0 16.--31. 1. "EORR,Pmn Event Output Reset" hexmask.long.word 0x0 0.--15. 1. "EOSR,Pmn Event Output Set" group.word 0xC++0x3 line.word 0x0 "EORR,Event output set register" hexmask.word 0x0 0.--15. 1. "EORR,Pmn Event Output Reset" line.word 0x2 "EOSR,Event output reset register" hexmask.word 0x2 0.--15. 1. "EOSR,Pmn Event Output Set" tree.end tree "PORT4" base ad:0x40040080 group.long 0x0++0x3 line.long 0x0 "PCNTR1,Port Control Register 1" hexmask.long.word 0x0 16.--31. 1. "PODR,Pmn Output Data" hexmask.long.word 0x0 0.--15. 1. "PDR,Pmn Direction" group.word 0x0++0x3 line.word 0x0 "PODR,Output data register" hexmask.word 0x0 0.--15. 1. "PODR,Pmn Output Data" line.word 0x2 "PDR,Data direction register" hexmask.word 0x2 0.--15. 1. "PDR,Pmn Direction" rgroup.long 0x4++0x3 line.long 0x0 "PCNTR2,Port Control Register 2" hexmask.long.word 0x0 16.--31. 1. "EIDR,Pmn Event Input Data" hexmask.long.word 0x0 0.--15. 1. "PIDR,Pmn Input Data" rgroup.word 0x4++0x3 line.word 0x0 "EIDR,Event input data register" hexmask.word 0x0 0.--15. 1. "EIDR,Pmn Event Input Data" line.word 0x2 "PIDR,Input data register" hexmask.word 0x2 0.--15. 1. "PIDR,Pmn Input Data" wgroup.long 0x8++0x3 line.long 0x0 "PCNTR3,Port Control Register 3" hexmask.long.word 0x0 16.--31. 1. "PORR,Pmn Output Reset" hexmask.long.word 0x0 0.--15. 1. "POSR,Pmn Output Set" wgroup.word 0x8++0x3 line.word 0x0 "PORR,Output set register" hexmask.word 0x0 0.--15. 1. "PORR,Pmn Output Reset" line.word 0x2 "POSR,Output reset register" hexmask.word 0x2 0.--15. 1. "POSR,Pmn Output Set" group.long 0xC++0x3 line.long 0x0 "PCNTR4,Port Control Register 4" hexmask.long.word 0x0 16.--31. 1. "EORR,Pmn Event Output Reset" hexmask.long.word 0x0 0.--15. 1. "EOSR,Pmn Event Output Set" group.word 0xC++0x3 line.word 0x0 "EORR,Event output set register" hexmask.word 0x0 0.--15. 1. "EORR,Pmn Event Output Reset" line.word 0x2 "EOSR,Event output reset register" hexmask.word 0x2 0.--15. 1. "EOSR,Pmn Event Output Set" tree.end tree "PORT5" base ad:0x400400A0 group.long 0x0++0x3 line.long 0x0 "PCNTR1,Port Control Register 1" hexmask.long.word 0x0 16.--31. 1. "PODR,Pmn Output Data" hexmask.long.word 0x0 0.--15. 1. "PDR,Pmn Direction" group.word 0x0++0x3 line.word 0x0 "PODR,Output data register" hexmask.word 0x0 0.--15. 1. "PODR,Pmn Output Data" line.word 0x2 "PDR,Data direction register" hexmask.word 0x2 0.--15. 1. "PDR,Pmn Direction" rgroup.long 0x4++0x3 line.long 0x0 "PCNTR2,Port Control Register 2" hexmask.long.word 0x0 16.--31. 1. "EIDR,Pmn Event Input Data" hexmask.long.word 0x0 0.--15. 1. "PIDR,Pmn Input Data" rgroup.word 0x6++0x1 line.word 0x0 "PIDR,Input data register" hexmask.word 0x0 0.--15. 1. "PIDR,Pmn Input Data" wgroup.long 0x8++0x3 line.long 0x0 "PCNTR3,Port Control Register 3" hexmask.long.word 0x0 16.--31. 1. "PORR,Pmn Output Reset" hexmask.long.word 0x0 0.--15. 1. "POSR,Pmn Output Set" wgroup.word 0x8++0x3 line.word 0x0 "PORR,Output reset register" hexmask.word 0x0 0.--15. 1. "PORR,Pmn Output Reset" line.word 0x2 "POSR,Output set register" hexmask.word 0x2 0.--15. 1. "POSR,Pmn Output Set" tree.end tree "PORT6" base ad:0x400400C0 group.long 0x0++0x3 line.long 0x0 "PCNTR1,Port Control Register 1" hexmask.long.word 0x0 16.--31. 1. "PODR,Pmn Output Data" hexmask.long.word 0x0 0.--15. 1. "PDR,Pmn Direction" group.word 0x0++0x3 line.word 0x0 "PODR,Output data register" hexmask.word 0x0 0.--15. 1. "PODR,Pmn Output Data" line.word 0x2 "PDR,Data direction register" hexmask.word 0x2 0.--15. 1. "PDR,Pmn Direction" rgroup.long 0x4++0x3 line.long 0x0 "PCNTR2,Port Control Register 2" hexmask.long.word 0x0 16.--31. 1. "EIDR,Pmn Event Input Data" hexmask.long.word 0x0 0.--15. 1. "PIDR,Pmn Input Data" rgroup.word 0x6++0x1 line.word 0x0 "PIDR,Input data register" hexmask.word 0x0 0.--15. 1. "PIDR,Pmn Input Data" wgroup.long 0x8++0x3 line.long 0x0 "PCNTR3,Port Control Register 3" hexmask.long.word 0x0 16.--31. 1. "PORR,Pmn Output Reset" hexmask.long.word 0x0 0.--15. 1. "POSR,Pmn Output Set" wgroup.word 0x8++0x3 line.word 0x0 "PORR,Output reset register" hexmask.word 0x0 0.--15. 1. "PORR,Pmn Output Reset" line.word 0x2 "POSR,Output set register" hexmask.word 0x2 0.--15. 1. "POSR,Pmn Output Set" tree.end tree "PORT7" base ad:0x400400E0 group.long 0x0++0x3 line.long 0x0 "PCNTR1,Port Control Register 1" hexmask.long.word 0x0 16.--31. 1. "PODR,Pmn Output Data" hexmask.long.word 0x0 0.--15. 1. "PDR,Pmn Direction" group.word 0x0++0x3 line.word 0x0 "PODR,Output data register" hexmask.word 0x0 0.--15. 1. "PODR,Pmn Output Data" line.word 0x2 "PDR,Data direction register" hexmask.word 0x2 0.--15. 1. "PDR,Pmn Direction" rgroup.long 0x4++0x3 line.long 0x0 "PCNTR2,Port Control Register 2" hexmask.long.word 0x0 16.--31. 1. "EIDR,Pmn Event Input Data" hexmask.long.word 0x0 0.--15. 1. "PIDR,Pmn Input Data" rgroup.word 0x6++0x1 line.word 0x0 "PIDR,Input data register" hexmask.word 0x0 0.--15. 1. "PIDR,Pmn Input Data" wgroup.long 0x8++0x3 line.long 0x0 "PCNTR3,Port Control Register 3" hexmask.long.word 0x0 16.--31. 1. "PORR,Pmn Output Reset" hexmask.long.word 0x0 0.--15. 1. "POSR,Pmn Output Set" wgroup.word 0x8++0x3 line.word 0x0 "PORR,Output reset register" hexmask.word 0x0 0.--15. 1. "PORR,Pmn Output Reset" line.word 0x2 "POSR,Output set register" hexmask.word 0x2 0.--15. 1. "POSR,Pmn Output Set" tree.end tree "PORT8" base ad:0x40040100 group.long 0x0++0x3 line.long 0x0 "PCNTR1,Port Control Register 1" hexmask.long.word 0x0 16.--31. 1. "PODR,Pmn Output Data" hexmask.long.word 0x0 0.--15. 1. "PDR,Pmn Direction" group.word 0x0++0x3 line.word 0x0 "PODR,Output data register" hexmask.word 0x0 0.--15. 1. "PODR,Pmn Output Data" line.word 0x2 "PDR,Data direction register" hexmask.word 0x2 0.--15. 1. "PDR,Pmn Direction" rgroup.long 0x4++0x3 line.long 0x0 "PCNTR2,Port Control Register 2" hexmask.long.word 0x0 16.--31. 1. "EIDR,Pmn Event Input Data" hexmask.long.word 0x0 0.--15. 1. "PIDR,Pmn Input Data" rgroup.word 0x6++0x1 line.word 0x0 "PIDR,Input data register" hexmask.word 0x0 0.--15. 1. "PIDR,Pmn Input Data" wgroup.long 0x8++0x3 line.long 0x0 "PCNTR3,Port Control Register 3" hexmask.long.word 0x0 16.--31. 1. "PORR,Pmn Output Reset" hexmask.long.word 0x0 0.--15. 1. "POSR,Pmn Output Set" wgroup.word 0x8++0x3 line.word 0x0 "PORR,Output reset register" hexmask.word 0x0 0.--15. 1. "PORR,Pmn Output Reset" line.word 0x2 "POSR,Output set register" hexmask.word 0x2 0.--15. 1. "POSR,Pmn Output Set" tree.end tree "PORT9" base ad:0x40040120 group.long 0x0++0x3 line.long 0x0 "PCNTR1,Port Control Register 1" hexmask.long.word 0x0 16.--31. 1. "PODR,Pmn Output Data" hexmask.long.word 0x0 0.--15. 1. "PDR,Pmn Direction" group.word 0x0++0x3 line.word 0x0 "PODR,Output data register" hexmask.word 0x0 0.--15. 1. "PODR,Pmn Output Data" line.word 0x2 "PDR,Data direction register" hexmask.word 0x2 0.--15. 1. "PDR,Pmn Direction" rgroup.long 0x4++0x3 line.long 0x0 "PCNTR2,Port Control Register 2" hexmask.long.word 0x0 16.--31. 1. "EIDR,Pmn Event Input Data" hexmask.long.word 0x0 0.--15. 1. "PIDR,Pmn Input Data" rgroup.word 0x6++0x1 line.word 0x0 "PIDR,Input data register" hexmask.word 0x0 0.--15. 1. "PIDR,Pmn Input Data" wgroup.long 0x8++0x3 line.long 0x0 "PCNTR3,Port Control Register 3" hexmask.long.word 0x0 16.--31. 1. "PORR,Pmn Output Reset" hexmask.long.word 0x0 0.--15. 1. "POSR,Pmn Output Set" wgroup.word 0x8++0x3 line.word 0x0 "PORR,Output reset register" hexmask.word 0x0 0.--15. 1. "PORR,Pmn Output Reset" line.word 0x2 "POSR,Output set register" hexmask.word 0x2 0.--15. 1. "POSR,Pmn Output Set" tree.end tree.end tree "RTC (Realtime Clock)" base ad:0x40044000 rgroup.byte 0x0++0x0 line.byte 0x0 "R64CNT,64-Hz Counter" bitfld.byte 0x0 6. "F1HZ,1Hz" "0,1" bitfld.byte 0x0 5. "F2HZ,2Hz" "0,1" newline bitfld.byte 0x0 4. "F4HZ,4Hz" "0,1" bitfld.byte 0x0 3. "F8HZ,8Hz" "0,1" newline bitfld.byte 0x0 2. "F16HZ,16Hz" "0,1" bitfld.byte 0x0 1. "F32HZ,32Hz" "0,1" newline bitfld.byte 0x0 0. "F64HZ,64Hz" "0,1" group.byte 0x2++0x0 line.byte 0x0 "RSECCNT,Second Counter" bitfld.byte 0x0 4.--6. "SEC10,10-Second Count Counts from 0 to 5 for 60-second counting." "0,1,2,3,4,5,6,7" hexmask.byte 0x0 0.--3. 1. "SEC1,1-Second Count Counts from 0 to 9 every second. When a carry is generated 1 is added to the tens place." group.byte 0x2++0x0 line.byte 0x0 "BCNT0,Binary Counter 0" hexmask.byte 0x0 0.--7. 1. "BCNT0,The BCNT0 counter is a readable/writable 32-bit binary counter b7 to b0." group.byte 0x4++0x0 line.byte 0x0 "RMINCNT,Minute Counter" bitfld.byte 0x0 4.--6. "MIN10,10-Minute Count Counts from 0 to 5 for 60-minute counting." "0,1,2,3,4,5,6,7" hexmask.byte 0x0 0.--3. 1. "MIN1,1-Minute Count Counts from 0 to 9 every minute. When a carry is generated 1 is added to the tens place." group.byte 0x4++0x0 line.byte 0x0 "BCNT1,Binary Counter 1" hexmask.byte 0x0 0.--7. 1. "BCNT1,The BCNT1 counter is a readable/writable 32-bit binary counter b15 to b8." group.byte 0x6++0x0 line.byte 0x0 "RHRCNT,Hour Counter" bitfld.byte 0x0 6. "PM,Time Counter Setting for a.m./p.m." "0: a.m.,1: p.m." bitfld.byte 0x0 4.--5. "HR10,10-Hour Count Counts from 0 to 2 once per carry from the ones place." "0,1,2,3" newline hexmask.byte 0x0 0.--3. 1. "HR1,1-Hour Count Counts from 0 to 9 once per hour. When a carry is generated 1 is added to the tens place." group.byte 0x6++0x0 line.byte 0x0 "BCNT2,Binary Counter 2" hexmask.byte 0x0 0.--7. 1. "BCNT2,The BCNT2 counter is a readable/writable 32-bit binary counter b23 to b16." group.byte 0x8++0x0 line.byte 0x0 "RWKCNT,Day-of-Week Counter" bitfld.byte 0x0 0.--2. "DAYW,Day-of-Week Counting" "0: Sunday,1: Monday,?,?,?,?,?,?" group.byte 0x8++0x0 line.byte 0x0 "BCNT3,Binary Counter 3" hexmask.byte 0x0 0.--7. 1. "BCNT3,The BCNT3 counter is a readable/writable 32-bit binary counter b31 to b24." group.byte 0xA++0x0 line.byte 0x0 "RDAYCNT,Day Counter" bitfld.byte 0x0 4.--5. "DATE10,10-Day Count Counts from 0 to 3 once per carry from the ones place." "0,1,2,3" hexmask.byte 0x0 0.--3. 1. "DATE1,1-Day Count Counts from 0 to 9 once per day. When a carry is generated 1 is added to the tens place." group.byte 0xC++0x0 line.byte 0x0 "RMONCNT,Month Counter" bitfld.byte 0x0 5.--7. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.byte 0x0 4. "MON10,10-Month Count Counts from 0 to 1 once per carry from the ones place." "0,1" newline hexmask.byte 0x0 0.--3. 1. "MON1,1-Month Count Counts from 0 to 9 once per month. When a carry is generated 1 is added to the tens place." group.word 0xE++0x1 line.word 0x0 "RYRCNT,Year Counter" hexmask.word.byte 0x0 8.--15. 1. "Reserved,These bits are read as 00000000. The write value should be 00000000." hexmask.word.byte 0x0 4.--7. 1. "YR10,10-Year Count Counts from 0 to 9 once per carry from ones place. When a carry is generated in the tens place 1 is added to the hundreds place." newline hexmask.word.byte 0x0 0.--3. 1. "YR1,1-Year Count Counts from 0 to 9 once per year. When a carry is generated 1 is added to the tens place." group.byte 0x10++0x0 line.byte 0x0 "RSECAR,Second Alarm Register" bitfld.byte 0x0 7. "ENB,Compare enable" "0: The register value is not compared with the..,1: The register value is compared with the RSECCNT.." bitfld.byte 0x0 4.--6. "SEC10,10-Seconds Value for the tens place of seconds" "0,1,2,3,4,5,6,7" newline hexmask.byte 0x0 0.--3. 1. "SEC1,1-Second Value for the ones place of seconds" group.byte 0x10++0x0 line.byte 0x0 "BCNT0AR,Binary Counter 0 Alarm Register" hexmask.byte 0x0 0.--7. 1. "BCNT0AR,he BCNT0AR counter is a readable/writable alarm register corresponding to 32-bit binary counter b7 to b0." group.byte 0x12++0x0 line.byte 0x0 "RMINAR,Minute Alarm Register" bitfld.byte 0x0 7. "ENB,Compare enable" "0: The register value is not compared with the..,1: The register value is compared with the RMINCNT.." bitfld.byte 0x0 4.--6. "MIN10,10-Minute Count Value for the tens place of minutes" "0,1,2,3,4,5,6,7" newline hexmask.byte 0x0 0.--3. 1. "MIN1,1-Minute Count Value for the ones place of minutes" group.byte 0x12++0x0 line.byte 0x0 "BCNT1AR,Binary Counter 1 Alarm Register" hexmask.byte 0x0 0.--7. 1. "BCNT1AR,he BCNT1AR counter is a readable/writable alarm register corresponding to 32-bit binary counter b15 to b8." group.byte 0x14++0x0 line.byte 0x0 "RHRAR,Hour Alarm Register" bitfld.byte 0x0 7. "ENB,Compare enable" "0: The register value is not compared with the..,1: The register value is compared with the RHRCNT.." bitfld.byte 0x0 6. "PM,Time Counter Setting for a.m./p.m." "0: a.m.,1: p.m." newline bitfld.byte 0x0 4.--5. "HR10,10-Hour Count Value for the tens place of hours" "0,1,2,3" hexmask.byte 0x0 0.--3. 1. "HR1,1-Hour Count Value for the ones place of hours" group.byte 0x14++0x0 line.byte 0x0 "BCNT2AR,Binary Counter 2 Alarm Register" hexmask.byte 0x0 0.--7. 1. "BCNT2AR,The BCNT2AR counter is a readable/writable 32-bit binary counter b23 to b16." group.byte 0x16++0x0 line.byte 0x0 "RWKAR,Day-of-Week Alarm Register" bitfld.byte 0x0 7. "ENB,Compare enable" "0: The register value is not compared with the..,1: The register value is compared with the RWKCNT.." hexmask.byte 0x0 3.--6. 1. "Reserved,These bits are read as 0000. The write value should be 0000." newline bitfld.byte 0x0 0.--2. "DAYW,Day-of-Week Counting" "0: Sunday,1: Monday,?,?,?,?,?,?" group.byte 0x16++0x0 line.byte 0x0 "BCNT3AR,Binary Counter 3 Alarm Register" hexmask.byte 0x0 0.--7. 1. "BCNT3AR,The BCNT3AR counter is a readable/writable 32-bit binary counter b31 to b24." group.byte 0x18++0x0 line.byte 0x0 "RDAYAR,Date Alarm Register" bitfld.byte 0x0 7. "ENB,Compare enable" "0: The register value is not compared with the..,1: The register value is compared with the RDAYCNT.." bitfld.byte 0x0 6. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.byte 0x0 4.--5. "DATE10,10 Days Value for the tens place of days" "0,1,2,3" hexmask.byte 0x0 0.--3. 1. "DATE1,1 Day Value for the ones place of days" group.byte 0x18++0x0 line.byte 0x0 "BCNT0AER,Binary Counter 0 Alarm Enable Register" hexmask.byte 0x0 0.--7. 1. "ENB,The BCNT0AER register is a readable/writable register for setting the alarm enable corresponding to 32-bit binary counter b7 to b0." group.byte 0x1A++0x0 line.byte 0x0 "RMONAR,Month Alarm Register" bitfld.byte 0x0 7. "ENB,Compare enable" "0: The register value is not compared with the..,1: The register value is compared with the RMONCNT.." bitfld.byte 0x0 5.--6. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" newline bitfld.byte 0x0 4. "MON10,10 Months Value for the tens place of months" "0,1" hexmask.byte 0x0 0.--3. 1. "MON1,1 Month Value for the ones place of months" group.byte 0x1A++0x0 line.byte 0x0 "BCNT1AER,Binary Counter 1 Alarm Enable Register" hexmask.byte 0x0 0.--7. 1. "ENB,The BCNT1AER register is a readable/writable register for setting the alarm enable corresponding to 32-bit binary counter b15 to b8." group.word 0x1C++0x1 line.word 0x0 "RYRAR,Year Alarm Register" hexmask.word.byte 0x0 8.--15. 1. "Reserved,These bits are read as 00000000. The write value should be 00000000." hexmask.word.byte 0x0 4.--7. 1. "YR10,10 Years Value for the tens place of years" newline hexmask.word.byte 0x0 0.--3. 1. "YR1,1 Year Value for the ones place of years" group.word 0x1C++0x1 line.word 0x0 "BCNT2AER,Binary Counter 2 Alarm Enable Register" hexmask.word.byte 0x0 8.--15. 1. "Reserved,These bits are read as 00000000. The write value should be 00000000." hexmask.word.byte 0x0 0.--7. 1. "ENB,The BCNT2AER register is a readable/writable register for setting the alarm enable corresponding to 32-bit binary counter b23 to b16." group.byte 0x1E++0x0 line.byte 0x0 "RYRAREN,Year Alarm Enable Register" bitfld.byte 0x0 7. "ENB,Compare enable" "0: The register value is not compared with the..,1: The register value is compared with the RYRCNT.." hexmask.byte 0x0 0.--6. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." group.byte 0x1E++0x0 line.byte 0x0 "BCNT3AER,Binary Counter 3 Alarm Enable Register" hexmask.byte 0x0 0.--7. 1. "ENB,The BCNT3AER register is a readable/writable register for setting the alarm enable corresponding to 32-bit binary counter b31 to b24." group.byte 0x22++0x0 line.byte 0x0 "RCR1,RTC Control Register 1" hexmask.byte 0x0 4.--7. 1. "PES,Periodic Interrupt Select" bitfld.byte 0x0 3. "RTCOS,RTCOUT Output Select" "0: RTCOUT outputs 1 Hz.,1: RTCOUT outputs 64 Hz." newline bitfld.byte 0x0 2. "PIE,Periodic Interrupt Enable" "0: A periodic interrupt request is disabled.,1: A periodic interrupt request is enabled." bitfld.byte 0x0 1. "CIE,Carry Interrupt Enable" "0: A carry interrupt request is disabled.,1: A carry interrupt request is enabled." newline bitfld.byte 0x0 0. "AIE,Alarm Interrupt Enable" "0: An alarm interrupt request is disabled.,1: An alarm interrupt request is enabled." group.byte 0x24++0x0 line.byte 0x0 "RCR2,RTC Control Register 2" bitfld.byte 0x0 7. "CNTMD,Count Mode Select" "0: The calendar count mode.,1: The binary count mode." bitfld.byte 0x0 6. "HR24,Hours Mode" "0: The RTC operates in 12-hour mode.,1: The RTC operates in 24-hour mode." newline bitfld.byte 0x0 5. "AADJP,Automatic Adjustment Period Select (When the LOCO clock is selected the setting of this bit is disabled.)" "0: The RADJ.ADJ[5:0] setting value is adjusted from..,1: The RADJ.ADJ[5:0] setting value is adjusted from.." bitfld.byte 0x0 4. "AADJE,Automatic Adjustment Enable (When the LOCO clock is selected the setting of this bit is disabled.)" "0: Automatic adjustment is disabled.,1: Automatic adjustment is enabled." newline bitfld.byte 0x0 3. "RTCOE,RTCOUT Output Enable" "0: RTCOUT output disabled.,1: RTCOUT output enabled." bitfld.byte 0x0 2. "ADJ30,30-Second Adjustment" "0: Writing is invalid.(write) / In normal time..,1: 30-second adjustment is executed.(write) /.." newline bitfld.byte 0x0 1. "RESET,RTC Software Reset" "0: Writing is invalid.(write) / In normal time..,1: The prescaler and the target registers for RTC.." bitfld.byte 0x0 0. "START,Start" "0: Prescaler and time counter are stopped.,1: Prescaler and time counter operate normally." group.byte 0x28++0x0 line.byte 0x0 "RCR4,RTC Control Register 4" hexmask.byte 0x0 1.--7. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.byte 0x0 0. "RCKSEL,Count Source Select" "0: Sub-clock oscillator is selected.,1: LOCO clock oscillator is selected." group.word 0x2A++0x3 line.word 0x0 "RFRH,Frequency Register H" hexmask.word 0x0 1.--15. 1. "Reserved,These bits are read as 000000000000000. The write value should be 000000000000000." bitfld.word 0x0 0. "RFC16,Frequency Comparison Value (b16) To generate the operating clock from the LOCOclock this bit sets the comparison value of the 128-Hz clock cycle." "0,1" line.word 0x2 "RFRL,Frequency Register L" hexmask.word 0x2 0.--15. 1. "RFC,Frequency Comparison Value(b15-b0) To generate the operating clock from the main clock this bit sets the comparison value of the 128-Hz clock cycle." group.byte 0x2E++0x0 line.byte 0x0 "RADJ,Time Error Adjustment Register" bitfld.byte 0x0 6.--7. "PMADJ,Plus-Minus" "0: Adjustment is not performed.,1: Adjustment is performed by the addition to the..,?,?" hexmask.byte 0x0 0.--5. 1. "ADJ,Adjustment Value These bits specify the adjustment value from the prescaler." repeat 3. (increment 0x0 0x1)(increment 0x0 0x2) group.byte ($2+0x40)++0x0 line.byte 0x0 "RTCCR$1,Time Capture Control Register %s" bitfld.byte 0x0 7. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 6. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.byte 0x0 4.--5. "TCNF,Time Capture Noise Filter Control" "0: The noise filter is off.,1: Setting prohibited,?,?" bitfld.byte 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline rbitfld.byte 0x0 2. "TCST,Time Capture Status" "0: No event is detected.,1: An event is detected." bitfld.byte 0x0 0.--1. "TCCT,Time Capture Control" "0: No event is detected.,1: Rising edge is detected.,?,?" repeat.end repeat 3. (increment 0x0 0x1)(increment 0x0 0x10) rgroup.byte ($2+0x52)++0x0 line.byte 0x0 "RSECCP$1,Second Capture Register %s" bitfld.byte 0x0 7. "Reserved,This bit is read as 0." "0,1" bitfld.byte 0x0 4.--6. "SEC10,10-Second Capture Capture value for the tens place of seconds" "0,1,2,3,4,5,6,7" newline hexmask.byte 0x0 0.--3. 1. "SEC1,1-Second Capture Capture value for the ones place of seconds" repeat.end repeat 3. (increment 0x0 0x1)(increment 0x0 0x10) rgroup.byte ($2+0x52)++0x0 line.byte 0x0 "BCNT0CP$1,BCNT0 Capture Register %s" hexmask.byte 0x0 0.--7. 1. "BCNT0CP,BCNT0CP is a read-only register that captures the BCNT0 value when a time capture event is detected." repeat.end repeat 3. (increment 0x0 0x1)(increment 0x0 0x10) rgroup.byte ($2+0x54)++0x0 line.byte 0x0 "RMINCP$1,Minute Capture Register %s" bitfld.byte 0x0 7. "Reserved,This bit is read as 0." "0,1" bitfld.byte 0x0 4.--6. "MIN10,10-Minute Capture Capture value for the tens place of minutes" "0,1,2,3,4,5,6,7" newline hexmask.byte 0x0 0.--3. 1. "MIN1,1-Minute Capture Capture value for the ones place of minutes" repeat.end repeat 3. (increment 0x0 0x1)(increment 0x0 0x10) rgroup.byte ($2+0x54)++0x0 line.byte 0x0 "BCNT1CP$1,BCNT1 Capture Register %s" hexmask.byte 0x0 0.--7. 1. "BCNT1CP,BCNT1CP is a read-only register that captures the BCNT1 value when a time capture event is detected." repeat.end repeat 3. (increment 0x0 0x1)(increment 0x0 0x10) rgroup.byte ($2+0x56)++0x0 line.byte 0x0 "RHRCP$1,Hour Capture Register %s" bitfld.byte 0x0 7. "Reserved,This bit is read as 0." "0,1" bitfld.byte 0x0 6. "PM,A.m./p.m. select for time counter setting." "0: a.m.,1: p.m." newline bitfld.byte 0x0 4.--5. "HR10,10-Minute Capture Capture value for the tens place of minutes" "0,1,2,3" hexmask.byte 0x0 0.--3. 1. "HR1,1-Minute Capture Capture value for the ones place of minutes" repeat.end repeat 3. (increment 0x0 0x1)(increment 0x0 0x10) rgroup.byte ($2+0x56)++0x0 line.byte 0x0 "BCNT2CP$1,BCNT2 Capture Register %s" hexmask.byte 0x0 0.--7. 1. "BCNT2CP,BCNT2CP is a read-only register that captures the BCNT2 value when a time capture event is detected." repeat.end repeat 3. (increment 0x0 0x1)(increment 0x0 0x10) rgroup.byte ($2+0x5A)++0x0 line.byte 0x0 "RDAYCP$1,Date Capture Register %s" bitfld.byte 0x0 6.--7. "Reserved,These bits are read as 00." "0,1,2,3" bitfld.byte 0x0 4.--5. "DATE10,10-Day Capture Capture value for the tens place of minutes" "0,1,2,3" newline hexmask.byte 0x0 0.--3. 1. "DATE1,1-Day Capture Capture value for the ones place of minutes" repeat.end repeat 3. (increment 0x0 0x1)(increment 0x0 0x10) rgroup.byte ($2+0x5A)++0x0 line.byte 0x0 "BCNT3CP$1,BCNT3 Capture Register %s" hexmask.byte 0x0 0.--7. 1. "BCNT3CP,BCNT3CP is a read-only register that captures the BCNT3 value when a time capture event is detected." repeat.end repeat 3. (increment 0x0 0x1)(increment 0x0 0x10) rgroup.byte ($2+0x5C)++0x0 line.byte 0x0 "RMONCP$1,Month Capture Register %s" bitfld.byte 0x0 4. "MON10,10-Month Capture Capture value for the tens place of months" "0,1" hexmask.byte 0x0 0.--3. 1. "MON1,1-Month Capture Capture value for the ones place of months" repeat.end tree.end tree "SCI (Serial Communications Interface)" base ad:0x0 tree "SCI0" base ad:0x40070000 group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register (SCMR.SMIF = 0)" bitfld.byte 0x0 7. "CM,Communication Mode" "0: Asynchronous mode or simple I2C mode,1: Clock synchronous mode" bitfld.byte 0x0 6. "CHR,Character Length(Valid only in asynchronous mode)" "0: Transmit/receive in 9-bit data..,1: Transmit/receive in 9-bit data.." newline bitfld.byte 0x0 5. "PE,Parity Enable(Valid only in asynchronous mode)" "0: Parity bit addition is not performed..,1: The parity bit is added (transmitting) / The.." bitfld.byte 0x0 4. "PM,Parity Mode (Valid only when the PE bit is 1)" "0: Selects even parity,1: Selects odd parity" newline bitfld.byte 0x0 3. "STOP,Stop Bit Length(Valid only in asynchronous mode)" "0: 1 stop bit,1: 2 stop bits" bitfld.byte 0x0 2. "MP,Multi-Processor Mode(Valid only in asynchronous mode)" "0: Multi-processor communications function is..,1: Multi-processor communications function is enabled" newline bitfld.byte 0x0 0.--1. "CKS,Clock Select" "0: PCLK clock,1: PCLK/4 clock,?,?" group.byte 0x0++0x2 line.byte 0x0 "SMR_SMCI,Serial mode register (SCMR.SMIF = 1)" bitfld.byte 0x0 7. "GM,GSM Mode" "0: Normal mode operation,1: GSM mode operation" bitfld.byte 0x0 6. "BLK,Block Transfer Mode" "0: Normal mode operation,1: Block transfer mode operation" newline bitfld.byte 0x0 5. "PE,Parity Enable(Valid only in asynchronous mode)" "0: Setting Prohibited,1: Set this bit to 1 in smart card interface mode." bitfld.byte 0x0 4. "PM,Parity Mode (Valid only when the PE bit is 1)" "0: Selects even parity,1: Selects odd parity" newline bitfld.byte 0x0 2.--3. "BCP,Base Clock Pulse(Valid only in asynchronous mode)" "0: 93 clock cycles(S=93) (SCMR.BCP2=0) / 32 clock..,1: 128 clock cycles(S=128) (SCMR.BCP2=0) / 64 clock..,?,?" bitfld.byte 0x0 0.--1. "CKS,Clock Select" "0: PCLK clock,1: PCLK/4 clock,?,?" line.byte 0x1 "BRR,Bit Rate Register" hexmask.byte 0x1 0.--7. 1. "BRR,BRR is an 8-bit register that adjusts the bit rate." line.byte 0x2 "SCR,Serial Control Register (SCMR.SMIF = 0)" bitfld.byte 0x2 7. "TIE,Transmit Interrupt Enable" "0: SCI_TXI interrupt request is disabled,1: SCI_TXI interrupt request is enabled" bitfld.byte 0x2 6. "RIE,Receive Interrupt Enable" "0: SCI_RXI and SCI_ERI interrupt requests are..,1: SCI_RXI and SCI_ERI interrupt requests are enabled" newline bitfld.byte 0x2 5. "TE,Transmit Enable" "0: Serial transmission is disabled,1: Serial transmission is enabled" bitfld.byte 0x2 4. "RE,Receive Enable" "0: Serial reception is disabled,1: Serial reception is enabled" newline bitfld.byte 0x2 3. "MPIE,Multi-Processor Interrupt Enable(Valid in asynchronous mode when SMR.MP = 1)" "0: Normal reception,1: When the data with the multi-processor bit set.." bitfld.byte 0x2 2. "TEIE,Transmit End Interrupt Enable" "0: SCI_TEI interrupt request is disabled,1: SCI_TEI interrupt request is enabled" newline bitfld.byte 0x2 0.--1. "CKE,Clock Enable" "0: The clock with a frequency 16 times the bit rate..,1: The clock with the same frequency as the bit..,?,?" group.byte 0x2++0x2 line.byte 0x0 "SCR_SMCI,Serial Control Register (SCMR.SMIF =1)" bitfld.byte 0x0 7. "TIE,Transmit Interrupt Enable" "0: A SCI_TXI interrupt request is disabled,1: A SCI_TXI interrupt request is enabled" bitfld.byte 0x0 6. "RIE,Receive Interrupt Enable" "0: SCI_RXI and SCI_ERI interrupt requests are..,1: SCI_RXI and SCI_ERI interrupt requests are enabled" newline bitfld.byte 0x0 5. "TE,Transmit Enable" "0: Serial transmission is disabled,1: Serial transmission is enabled" bitfld.byte 0x0 4. "RE,Receive Enable" "0: Serial reception is disabled,1: Serial reception is enabled" newline bitfld.byte 0x0 3. "MPIE,Multi-Processor Interrupt Enable" "0,1" bitfld.byte 0x0 2. "TEIE,Transmit End Interrupt Enable" "0,1" newline bitfld.byte 0x0 0.--1. "CKE,Clock Enable" "0: Output disabled(SMR_SMCI.GM=0) / Output fixed..,1: Clock Output,?,?" line.byte 0x1 "TDR,Transmit Data Register" hexmask.byte 0x1 0.--7. 1. "TDR,TDR is an 8-bit register that stores transmit data." line.byte 0x2 "SSR,Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0)" bitfld.byte 0x2 7. "TDRE,Transmit Data Empty Flag" "0: Transmit data is in TDR register,1: No transmit data is in TDR register" bitfld.byte 0x2 6. "RDRF,Receive Data Full Flag" "0: No received data is in RDR register,1: Received data is in RDR register" newline bitfld.byte 0x2 5. "ORER,Overrun Error Flag" "0: No overrun error occurred,1: An overrun error has occurred" bitfld.byte 0x2 4. "FER,Framing Error Flag" "0: No framing error occurred,1: A framing error has occurred" newline bitfld.byte 0x2 3. "PER,Parity Error Flag" "0: No parity error occurred,1: A parity error has occurred" rbitfld.byte 0x2 2. "TEND,Transmit End Flag" "0: A character is being transmitted.,1: Character transfer has been completed." newline rbitfld.byte 0x2 1. "MPB,Multi-Processor" "0: Data transmission cycles,1: ID transmission cycles" bitfld.byte 0x2 0. "MPBT,Multi-Processor Bit Transfer" "0: Data transmission cycles,1: ID transmission cycles" group.byte 0x4++0x0 line.byte 0x0 "SSR_FIFO,Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1)" bitfld.byte 0x0 7. "TDFE,Transmit FIFO data empty flag" "0: The quantity of transmit data written in FTDR..,1: The quantity of transmit data written in FTDR is.." bitfld.byte 0x0 6. "RDF,Receive FIFO data full flag" "0: The quantity of receive data written in FRDR..,1: The quantity of receive data written in FRDR is.." newline bitfld.byte 0x0 5. "ORER,Overrun Error Flag" "0: No overrun error occurred,1: An overrun error has occurred" bitfld.byte 0x0 4. "FER,Framing Error Flag" "0: No framing error occurred.,1: A framing error has occurred." newline bitfld.byte 0x0 3. "PER,Parity Error Flag" "0: No parity error occurred.,1: A parity error has occurred." bitfld.byte 0x0 2. "TEND,Transmit End Flag" "0: A character is being transmitted or standing by..,1: Character transfer has been completed." newline bitfld.byte 0x0 1. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 0. "DR,Receive Data Ready flag(Valid only in asynchronous mode(including multi-processor) and FIFO selected)" "0: Receiving is in progress or no received data has..,1: Next receive data has not been received for a.." group.byte 0x4++0x0 line.byte 0x0 "SSR_SMCI,Serial Status Register(SCMR.SMIF = 1)" bitfld.byte 0x0 7. "TDRE,Transmit Data Empty Flag" "0: Transmit data is in TDR register,1: No transmit data is in TDR register" bitfld.byte 0x0 6. "RDRF,Receive Data Full Flag" "0: No received data is in RDR register,1: Received data is in RDR register" newline bitfld.byte 0x0 5. "ORER,Overrun Error Flag" "0: No overrun error occurred,1: An overrun error has occurred" bitfld.byte 0x0 4. "ERS,Error Signal Status Flag" "0: Low error signal not responded,1: Low error signal responded" newline bitfld.byte 0x0 3. "PER,Parity Error Flag" "0: No parity error occurred,1: A parity error has occurred" rbitfld.byte 0x0 2. "TEND,Transmit End Flag" "0: A character is being transmitted.,1: Character transfer has been completed." newline rbitfld.byte 0x0 1. "MPB,Multi-ProcessorThis bit should be 0 in smart card interface mode." "0,1" bitfld.byte 0x0 0. "MPBT,Multi-Processor Bit TransferThis bit should be 0 in smart card interface mode." "0,1" rgroup.byte 0x5++0x0 line.byte 0x0 "RDR,Receive Data Register" hexmask.byte 0x0 0.--7. 1. "RDR,RDR is an 8-bit register that stores receive data." group.byte 0x6++0x5 line.byte 0x0 "SCMR,Smart Card Mode Register" bitfld.byte 0x0 7. "BCP2,Base Clock Pulse 2Selects the number of base clock cycles in combination with the SMR.BCP[1:0] bits" "0: S=93(SMR.BCP[1:0]=00) 128(SMR.BCP[1:0]=01)..,1: S=32(SMR.BCP[1:0]=00) 64(SMR.BCP[1:0]=01).." bitfld.byte 0x0 5.--6. "Reserved,These bits are read as 11. The write value should be 11." "0,1,2,3" newline bitfld.byte 0x0 4. "CHR1,Character Length 1(Only valid in asynchronous mode)" "0: Transmit/receive in 9-bit data length,1: Transmit/receive in 8-bit data length(SMR.CHR=0).." bitfld.byte 0x0 3. "SDIR,Transmitted/Received Data Transfer DirectionNOTE: The setting is invalid and a fixed data length of 8 bits is used in modes other than asynchronous mode.Set this bit to 1 if operation is to be in simple I2C mode." "0: Transfer with LSB first,1: Transfer with MSB first" newline bitfld.byte 0x0 2. "SINV,Transmitted/Received Data InvertSet this bit to 0 if operation is to be in simple I2C mode." "0: TDR contents are transmitted as they are.,1: TDR contents are inverted before being.." bitfld.byte 0x0 1. "Reserved,This bit is read as 1. The write value should be 1." "0,1" newline bitfld.byte 0x0 0. "SMIF,Smart Card Interface Mode Select" "0: Non-smart card interface mode(Asynchronous mode..,1: Smart card interface mode" line.byte 0x1 "SEMR,Serial Extended Mode Register" bitfld.byte 0x1 7. "RXDESEL,Asynchronous Start Bit Edge Detection Select(Valid only in asynchronous mode)" "0: The low level on the RXDn pin is detected as the..,1: A falling edge on the RXDn pin is detected as.." bitfld.byte 0x1 6. "BGDM,Baud Rate Generator Double-Speed Mode Select(Only valid the CKE[1] bit in SCR is 0 in asynchronous mode)." "0: Baud rate generator outputs the clock with..,1: Baud rate generator outputs the clock with.." newline bitfld.byte 0x1 5. "NFEN,Digital Noise Filter Function Enable(The NFEN bit should be 0 without simple I2C mode and asynchronous mode.)In asynchronous mode for RXDn input only. In simple I2C mode for RXDn/TxDn input." "0: Noise cancellation function for the RXDn/SSCLn..,1: Noise cancellation function for the RXDn/SSCLn.." bitfld.byte 0x1 4. "ABCS,Asynchronous Mode Base Clock Select(Valid only in asynchronous mode)" "0: Selects 16 base clock cycles for 1-bit period.,1: Selects 8 base clock cycles for 1-bit period." newline bitfld.byte 0x1 3. "ABCSE,Asynchronous Mode Extended Base Clock Select 1(Valid only in asynchronous mode and SCR.CKE[1]=0)" "0: Clock cycles for 1-bit period is decided with..,1: Baud rate is 6 base clock cycles for 1-bit.." bitfld.byte 0x1 2. "BRME,Bit Rate Modulation Enable" "0: Bit rate modulation function is disabled.,1: Bit rate modulation function is enabled." newline bitfld.byte 0x1 0.--1. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" line.byte 0x2 "SNFR,Noise Filter Setting Register" hexmask.byte 0x2 3.--7. 1. "Reserved,These bits are read as 00000. The write value should be 00000." bitfld.byte 0x2 0.--2. "NFCS,Noise Filter Clock Select" "0: Settings prohibited.,1: The clock signal divided by 1 is used with the..,?,?,?,?,?,?" line.byte 0x3 "SIMR1,I2C Mode Register 1" hexmask.byte 0x3 3.--7. 1. "IICDL,SDA Delay Output SelectCycles below are of the clock signal from the on-chip baud rate generator." bitfld.byte 0x3 1.--2. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" newline bitfld.byte 0x3 0. "IICM,Simple I2C Mode Select" "0: Asynchronous mode Multi-processor mode Clock..,1: Simple I2C mode(SCMR.SMIF=0) / Setting.." line.byte 0x4 "SIMR2,I2C Mode Register 2" bitfld.byte 0x4 6.--7. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.byte 0x4 5. "IICACKT,ACK Transmission Data" "0: ACK transmission,1: NACK transmission and reception of ACK/NACK" newline bitfld.byte 0x4 2.--4. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.byte 0x4 1. "IICCSC,Clock Synchronization" "0: No synchronization with the clock signal,1: Synchronization with the clock signal" newline bitfld.byte 0x4 0. "IICINTM,I2C Interrupt Mode Select" "0: Use ACK/NACK interrupts.,1: Use reception and transmission interrupts" line.byte 0x5 "SIMR3,I2C Mode Register 3" bitfld.byte 0x5 6.--7. "IICSCLS,SCL Output Select" "0: Serial clock output,1: Generate a start restart or stop condition.,?,?" bitfld.byte 0x5 4.--5. "IICSDAS,SDA Output Select" "0: Serial data output,1: Generate a start restart or stop condition.,?,?" newline bitfld.byte 0x5 3. "IICSTIF,Issuing of Start Restart or Stop Condition Completed Flag(When 0 is written to IICSTIF it is cleared to 0.)" "0: There are no requests for generating conditions..,1: A start restart or stop condition is completely.." bitfld.byte 0x5 2. "IICSTPREQ,Stop Condition Generation" "0: A stop condition is not generated.,1: A stop condition is generated." newline bitfld.byte 0x5 1. "IICRSTAREQ,Restart Condition Generation" "0: A restart condition is not generated.,1: A restart condition is generated." bitfld.byte 0x5 0. "IICSTAREQ,Start Condition Generation" "0: A start condition is not generated.,1: A start condition is generated." rgroup.byte 0xC++0x0 line.byte 0x0 "SISR,I2C Status Register" bitfld.byte 0x0 6.--7. "Reserved,These bits are read as 00." "0,1,2,3" bitfld.byte 0x0 5. "Reserved,This bit is read as 0." "0,1" newline bitfld.byte 0x0 4. "Reserved,This bit is read as 0." "0,1" bitfld.byte 0x0 3. "Reserved,This bit is read as 0." "0,1" newline bitfld.byte 0x0 2. "Reserved,This bit is read as 0." "0,1" bitfld.byte 0x0 1. "Reserved,This bit is read as 0." "0,1" newline bitfld.byte 0x0 0. "IICACKR,ACK Reception Data Flag" "0: ACK received,1: NACK received" group.byte 0xD++0x0 line.byte 0x0 "SPMR,SPI Mode Register" bitfld.byte 0x0 7. "CKPH,Clock Phase Select" "0: Clock is not delayed.,1: Clock is delayed." bitfld.byte 0x0 6. "CKPOL,Clock Polarity Select" "0: Clock polarity is not inverted.,1: Clock polarity is inverted" newline bitfld.byte 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 4. "MFF,Mode Fault Flag" "0: No mode fault error,1: Mode fault error" newline bitfld.byte 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 2. "MSS,Master Slave Select" "0: Transmission is through the TXDn pin and..,1: Reception is through the TXDn pin and.." newline bitfld.byte 0x0 1. "CTSE,CTS Enable" "0: CTS function is disabled (RTS output function is..,1: CTS function is enabled." bitfld.byte 0x0 0. "SSE,SSn Pin Function Enable" "0: SSn pin function is disabled.,1: SSn pin function is enabled." wgroup.word 0xE++0x1 line.word 0x0 "TDRHL,Transmit 9-bit Data Register" hexmask.word 0x0 0.--15. 1. "TDRHL,TDRHL is a 16-bit register that stores transmit data." wgroup.word 0xE++0x1 line.word 0x0 "FTDRHL,Transmit FIFO Data Register HL" hexmask.word.byte 0x0 10.--15. 1. "Reserved,The write value should be 111111." bitfld.word 0x0 9. "MPBT,Multi-processor transfer bit flag(Valid only in asynchronous mode and SMR.MP=1 and FIFO selected)" "0: Data transmission cycles,1: ID transmission cycles" newline hexmask.word 0x0 0.--8. 1. "TDAT,Serial transmit data (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode and FIFO selected)" wgroup.byte 0xE++0x1 line.byte 0x0 "FTDRH,Transmit FIFO Data Register H" hexmask.byte 0x0 2.--7. 1. "Reserved,The write value should be 111111." bitfld.byte 0x0 1. "MPBT,Multi-processor transfer bit flag(Valid only in asynchronous mode and SMR.MP=1 and FIFO selected)" "0: Data transmission cycles,1: ID transmission cycles" newline bitfld.byte 0x0 0. "TDATH,Serial transmit data (b8) (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode and FIFO selected)" "0,1" line.byte 0x1 "FTDRL,Transmit FIFO Data Register L" hexmask.byte 0x1 0.--7. 1. "TDATL,Serial transmit data(b7-b0) (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode and FIFO selected)" rgroup.word 0x10++0x1 line.word 0x0 "RDRHL,Receive 9-bit Data Register" hexmask.word 0x0 0.--15. 1. "RDRHL,RDRHL is an 16-bit register that stores receive data." rgroup.word 0x10++0x1 line.word 0x0 "FRDRHL,Receive FIFO Data Register HL" bitfld.word 0x0 15. "Reserved,This bit is read as 0." "0,1" bitfld.word 0x0 14. "RDF,Receive FIFO data full flag(It is same as SSR.RDF)" "0: The quantity of receive data written in FRDRH..,1: The quantity of receive data written in FRDRH.." newline bitfld.word 0x0 13. "ORER,Overrun error flag(It is same as SSR.ORER)" "0: No overrun error occurred.,1: An overrun error has occurred." bitfld.word 0x0 12. "FER,Framing error flag" "0: No framing error occurred at the first data of..,1: A framing error has occurred at the first data.." newline bitfld.word 0x0 11. "PER,Parity error flag" "0: No parity error occurred at the first data of..,1: A parity error has occurred at the first data of.." bitfld.word 0x0 10. "DR,Receive data ready flag(It is same as SSR.DR)" "0: Receiving is in progress or no received data has..,1: Next receive data has not been received for a.." newline bitfld.word 0x0 9. "MPB,Multi-processor bit flag(Valid only in asynchronous mode with SMR.MP=1 and FIFO selected) It can read multi-processor bit corresponded to serial receive data(RDATA[8:0])" "0: Data transmission cycles,1: ID transmission cycles" hexmask.word 0x0 0.--8. 1. "RDAT,Serial receive data(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode and FIFO selected)" rgroup.byte 0x10++0x1 line.byte 0x0 "FRDRH,Receive FIFO Data Register H" bitfld.byte 0x0 7. "Reserved,This bit is read as 0." "0,1" bitfld.byte 0x0 6. "RDF,Receive FIFO data full flag(It is same as SSR.RDF)" "0: The quantity of receive data written in FRDRH..,1: The quantity of receive data written in FRDRH.." newline bitfld.byte 0x0 5. "ORER,Overrun error flag(It is same as SSR.ORER)" "0: No overrun error occurred,1: An overrun error has occurred" bitfld.byte 0x0 4. "FER,Framing error flag" "0: No framing error occurred at the first data of..,1: A framing error has occurred at the first data.." newline bitfld.byte 0x0 3. "PER,Parity error flag" "0: No parity error occurred at the first data of..,1: A parity error has occurred at the first data of.." bitfld.byte 0x0 2. "DR,Receive data ready flag(It is same as SSR.DR)" "0: Receiving is in progress or no received data has..,1: Next receive data has not been received for a.." newline bitfld.byte 0x0 1. "MPB,Multi-processor bit flag(Valid only in asynchronous mode with SMR.MP=1 and FIFO selected) It can read multi-processor bit corresponded to serial receive data(RDATA[8:0])" "0: Data transmission cycles,1: ID transmission cycles" bitfld.byte 0x0 0. "RDATH,Serial receive data(b8)(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode and FIFO selected)" "0,1" line.byte 0x1 "FRDRL,Receive FIFO Data Register L" hexmask.byte 0x1 0.--7. 1. "RDATL,Serial receive data(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode and FIFO selected)NOTE: When reading both of FRDRH register and FRDRL register please read by an order of the FRDRH register and the FRDRL.." group.byte 0x12++0x1 line.byte 0x0 "MDDR,Modulation Duty Register" hexmask.byte 0x0 0.--7. 1. "MDDR,MDDR corrects the bit rate adjusted by the BRR register." line.byte 0x1 "DCCR,Data Compare Match Control Register" bitfld.byte 0x1 7. "DCME,Data Compare Match Enable(Valid only in asynchronous mode(including multi-processor)" "0: Address match function is disabled.,1: Address match function is enabled" bitfld.byte 0x1 6. "IDSEL,ID frame select(Valid only in asynchronous mode(including multi-processor)" "0: Always compare data regardless of the value of..,1: Compare data when the MPB bit is 1 (ID frame).." newline bitfld.byte 0x1 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x1 4. "DFER,Data Compare Match Framing Error Flag" "0: No framing error occurred,1: A framing error has occurred" newline bitfld.byte 0x1 3. "DPER,Data Compare Match Parity Error Flag" "0: No parity error occurred,1: A parity error has occurred" bitfld.byte 0x1 1.--2. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" newline bitfld.byte 0x1 0. "DCMF,Data Compare Match Flag" "0: No matched,1: Matched" group.word 0x14++0x1 line.word 0x0 "FCR,FIFO Control Register" hexmask.word.byte 0x0 12.--15. 1. "RSTRG,RTS Output Active Trigger Number Select(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode)" hexmask.word.byte 0x0 8.--11. 1. "RTRG,Receive FIFO data trigger number(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode)" newline hexmask.word.byte 0x0 4.--7. 1. "TTRG,Transmit FIFO data trigger number(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode)" bitfld.word 0x0 3. "DRES,Receive data ready error select bit(When detecting a reception data ready the interrupt request is selected.)" "0: reception data full interrupt (RXI),1: receive error interrupt (ERI)" newline bitfld.word 0x0 2. "TFRST,Transmit FIFO Data Register Reset(Valid only in FCR.FM=1)" "0: The number of data stored in FTDRH and FTDRL..,1: The number of data stored in FTDRH and FTDRL.." bitfld.word 0x0 1. "RFRST,Receive FIFO Data Register Reset(Valid only in FCR.FM=1)" "0: The number of data stored in FRDRH and FRDRL..,1: The number of data stored in FRDRH and FRDRL.." newline bitfld.word 0x0 0. "FM,FIFO Mode Select(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode)" "0: Non-FIFO mode(Selects o TDR/RDR for communication),1: FIFO mode (Selects to FTDRH and FTDRL/FRDRH and.." rgroup.word 0x16++0x3 line.word 0x0 "FDR,FIFO Data Count Register" bitfld.word 0x0 13.--15. "Reserved,These bits are read as 000." "0,1,2,3,4,5,6,7" hexmask.word.byte 0x0 8.--12. 1. "T,Transmit FIFO Data CountIndicate the quantity of non-transmit data stored in FTDRH and FTDRL(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode while FCR.FM=1)" newline bitfld.word 0x0 5.--7. "Reserved,These bits are read as 000." "0,1,2,3,4,5,6,7" hexmask.word.byte 0x0 0.--4. 1. "R,Receive FIFO Data CountIndicate the quantity of receive data stored in FRDRH and FRDRL(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode while FCR.FM=1)" line.word 0x2 "LSR,Line Status Register" bitfld.word 0x2 13.--15. "Reserved,These bits are read as 000." "0,1,2,3,4,5,6,7" hexmask.word.byte 0x2 8.--12. 1. "PNUM,Parity Error CountIndicates the quantity of data with a parity error among the receive data stored in the receive FIFO data register (FRDRH and FRDRL)." newline bitfld.word 0x2 7. "Reserved,This bit is read as 0." "0,1" hexmask.word.byte 0x2 2.--6. 1. "FNUM,Framing Error CountIndicates the quantity of data with a framing error among the receive data stored in the receive FIFO data register (FRDRH and FRDRL)." newline bitfld.word 0x2 1. "Reserved,This bit is read as 0." "0,1" bitfld.word 0x2 0. "ORER,Overrun Error Flag (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode and FIFO selected)" "0: No overrun error occurred,1: An overrun error has occurred" group.word 0x1A++0x1 line.word 0x0 "CDR,Compare Match Data Register" hexmask.word.byte 0x0 9.--15. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." hexmask.word 0x0 0.--8. 1. "CMPD,Compare Match DataCompare data pattern for address match wake-up function" group.byte 0x1C++0x0 line.byte 0x0 "SPTR,Serial Port Register" hexmask.byte 0x0 3.--7. 1. "Reserved,These bits are read as 00000. The write value should be 00000." bitfld.byte 0x0 2. "SPB2IO,Serial port break I/O bit(It's selected whether the value of SPB2DT is output to TxD terminal.)" "0: The value of SPB2DT bit is not output in TXD pin.,1: The value of SPB2DT bit is output in TXD pin." newline bitfld.byte 0x0 1. "SPB2DT,Serial port break data select bit(The output level of TxD terminal is selected when SCR.TE = 0.)" "0: Low level is output on TXD pin,1: High level is output on TXD pin" rbitfld.byte 0x0 0. "RXDMON,Serial input data monitor bit(The state of the RXD terminal is shown.)" "0: RXD pin is low.,1: RXD pin is high." tree.end tree "SCI1" base ad:0x40070020 group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register (SCMR.SMIF = 0)" bitfld.byte 0x0 7. "CM,Communication Mode" "0: Asynchronous mode or simple I2C mode,1: Clock synchronous mode" bitfld.byte 0x0 6. "CHR,Character Length(Valid only in asynchronous mode)" "0: Transmit/receive in 9-bit data..,1: Transmit/receive in 9-bit data.." newline bitfld.byte 0x0 5. "PE,Parity Enable(Valid only in asynchronous mode)" "0: Parity bit addition is not performed..,1: The parity bit is added (transmitting) / The.." bitfld.byte 0x0 4. "PM,Parity Mode (Valid only when the PE bit is 1)" "0: Selects even parity,1: Selects odd parity" newline bitfld.byte 0x0 3. "STOP,Stop Bit Length(Valid only in asynchronous mode)" "0: 1 stop bit,1: 2 stop bits" bitfld.byte 0x0 2. "MP,Multi-Processor Mode(Valid only in asynchronous mode)" "0: Multi-processor communications function is..,1: Multi-processor communications function is enabled" newline bitfld.byte 0x0 0.--1. "CKS,Clock Select" "0: PCLK clock,1: PCLK/4 clock,?,?" group.byte 0x0++0x2 line.byte 0x0 "SMR_SMCI,Serial mode register (SCMR.SMIF = 1)" bitfld.byte 0x0 7. "GM,GSM Mode" "0: Normal mode operation,1: GSM mode operation" bitfld.byte 0x0 6. "BLK,Block Transfer Mode" "0: Normal mode operation,1: Block transfer mode operation" newline bitfld.byte 0x0 5. "PE,Parity Enable(Valid only in asynchronous mode)" "0: Setting Prohibited,1: Set this bit to 1 in smart card interface mode." bitfld.byte 0x0 4. "PM,Parity Mode (Valid only when the PE bit is 1)" "0: Selects even parity,1: Selects odd parity" newline bitfld.byte 0x0 2.--3. "BCP,Base Clock Pulse(Valid only in asynchronous mode)" "0: 93 clock cycles(S=93) (SCMR.BCP2=0) / 32 clock..,1: 128 clock cycles(S=128) (SCMR.BCP2=0) / 64 clock..,?,?" bitfld.byte 0x0 0.--1. "CKS,Clock Select" "0: PCLK clock,1: PCLK/4 clock,?,?" line.byte 0x1 "BRR,Bit Rate Register" hexmask.byte 0x1 0.--7. 1. "BRR,BRR is an 8-bit register that adjusts the bit rate." line.byte 0x2 "SCR,Serial Control Register (SCMR.SMIF = 0)" bitfld.byte 0x2 7. "TIE,Transmit Interrupt Enable" "0: SCI_TXI interrupt request is disabled,1: SCI_TXI interrupt request is enabled" bitfld.byte 0x2 6. "RIE,Receive Interrupt Enable" "0: SCI_RXI and SCI_ERI interrupt requests are..,1: SCI_RXI and SCI_ERI interrupt requests are enabled" newline bitfld.byte 0x2 5. "TE,Transmit Enable" "0: Serial transmission is disabled,1: Serial transmission is enabled" bitfld.byte 0x2 4. "RE,Receive Enable" "0: Serial reception is disabled,1: Serial reception is enabled" newline bitfld.byte 0x2 3. "MPIE,Multi-Processor Interrupt Enable(Valid in asynchronous mode when SMR.MP = 1)" "0: Normal reception,1: When the data with the multi-processor bit set.." bitfld.byte 0x2 2. "TEIE,Transmit End Interrupt Enable" "0: SCI_TEI interrupt request is disabled,1: SCI_TEI interrupt request is enabled" newline bitfld.byte 0x2 0.--1. "CKE,Clock Enable" "0: The clock with a frequency 16 times the bit rate..,1: The clock with the same frequency as the bit..,?,?" group.byte 0x2++0x2 line.byte 0x0 "SCR_SMCI,Serial Control Register (SCMR.SMIF =1)" bitfld.byte 0x0 7. "TIE,Transmit Interrupt Enable" "0: A SCI_TXI interrupt request is disabled,1: A SCI_TXI interrupt request is enabled" bitfld.byte 0x0 6. "RIE,Receive Interrupt Enable" "0: SCI_RXI and SCI_ERI interrupt requests are..,1: SCI_RXI and SCI_ERI interrupt requests are enabled" newline bitfld.byte 0x0 5. "TE,Transmit Enable" "0: Serial transmission is disabled,1: Serial transmission is enabled" bitfld.byte 0x0 4. "RE,Receive Enable" "0: Serial reception is disabled,1: Serial reception is enabled" newline bitfld.byte 0x0 3. "MPIE,Multi-Processor Interrupt Enable" "0,1" bitfld.byte 0x0 2. "TEIE,Transmit End Interrupt Enable" "0,1" newline bitfld.byte 0x0 0.--1. "CKE,Clock Enable" "0: Output disabled(SMR_SMCI.GM=0) / Output fixed..,1: Clock Output,?,?" line.byte 0x1 "TDR,Transmit Data Register" hexmask.byte 0x1 0.--7. 1. "TDR,TDR is an 8-bit register that stores transmit data." line.byte 0x2 "SSR,Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0)" bitfld.byte 0x2 7. "TDRE,Transmit Data Empty Flag" "0: Transmit data is in TDR register,1: No transmit data is in TDR register" bitfld.byte 0x2 6. "RDRF,Receive Data Full Flag" "0: No received data is in RDR register,1: Received data is in RDR register" newline bitfld.byte 0x2 5. "ORER,Overrun Error Flag" "0: No overrun error occurred,1: An overrun error has occurred" bitfld.byte 0x2 4. "FER,Framing Error Flag" "0: No framing error occurred,1: A framing error has occurred" newline bitfld.byte 0x2 3. "PER,Parity Error Flag" "0: No parity error occurred,1: A parity error has occurred" rbitfld.byte 0x2 2. "TEND,Transmit End Flag" "0: A character is being transmitted.,1: Character transfer has been completed." newline rbitfld.byte 0x2 1. "MPB,Multi-Processor" "0: Data transmission cycles,1: ID transmission cycles" bitfld.byte 0x2 0. "MPBT,Multi-Processor Bit Transfer" "0: Data transmission cycles,1: ID transmission cycles" group.byte 0x4++0x0 line.byte 0x0 "SSR_FIFO,Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1)" bitfld.byte 0x0 7. "TDFE,Transmit FIFO data empty flag" "0: The quantity of transmit data written in FTDR..,1: The quantity of transmit data written in FTDR is.." bitfld.byte 0x0 6. "RDF,Receive FIFO data full flag" "0: The quantity of receive data written in FRDR..,1: The quantity of receive data written in FRDR is.." newline bitfld.byte 0x0 5. "ORER,Overrun Error Flag" "0: No overrun error occurred,1: An overrun error has occurred" bitfld.byte 0x0 4. "FER,Framing Error Flag" "0: No framing error occurred.,1: A framing error has occurred." newline bitfld.byte 0x0 3. "PER,Parity Error Flag" "0: No parity error occurred.,1: A parity error has occurred." bitfld.byte 0x0 2. "TEND,Transmit End Flag" "0: A character is being transmitted or standing by..,1: Character transfer has been completed." newline bitfld.byte 0x0 1. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 0. "DR,Receive Data Ready flag(Valid only in asynchronous mode(including multi-processor) and FIFO selected)" "0: Receiving is in progress or no received data has..,1: Next receive data has not been received for a.." group.byte 0x4++0x0 line.byte 0x0 "SSR_SMCI,Serial Status Register(SCMR.SMIF = 1)" bitfld.byte 0x0 7. "TDRE,Transmit Data Empty Flag" "0: Transmit data is in TDR register,1: No transmit data is in TDR register" bitfld.byte 0x0 6. "RDRF,Receive Data Full Flag" "0: No received data is in RDR register,1: Received data is in RDR register" newline bitfld.byte 0x0 5. "ORER,Overrun Error Flag" "0: No overrun error occurred,1: An overrun error has occurred" bitfld.byte 0x0 4. "ERS,Error Signal Status Flag" "0: Low error signal not responded,1: Low error signal responded" newline bitfld.byte 0x0 3. "PER,Parity Error Flag" "0: No parity error occurred,1: A parity error has occurred" rbitfld.byte 0x0 2. "TEND,Transmit End Flag" "0: A character is being transmitted.,1: Character transfer has been completed." newline rbitfld.byte 0x0 1. "MPB,Multi-ProcessorThis bit should be 0 in smart card interface mode." "0,1" bitfld.byte 0x0 0. "MPBT,Multi-Processor Bit TransferThis bit should be 0 in smart card interface mode." "0,1" rgroup.byte 0x5++0x0 line.byte 0x0 "RDR,Receive Data Register" hexmask.byte 0x0 0.--7. 1. "RDR,RDR is an 8-bit register that stores receive data." group.byte 0x6++0x5 line.byte 0x0 "SCMR,Smart Card Mode Register" bitfld.byte 0x0 7. "BCP2,Base Clock Pulse 2Selects the number of base clock cycles in combination with the SMR.BCP[1:0] bits" "0: S=93(SMR.BCP[1:0]=00) 128(SMR.BCP[1:0]=01)..,1: S=32(SMR.BCP[1:0]=00) 64(SMR.BCP[1:0]=01).." bitfld.byte 0x0 5.--6. "Reserved,These bits are read as 11. The write value should be 11." "0,1,2,3" newline bitfld.byte 0x0 4. "CHR1,Character Length 1(Only valid in asynchronous mode)" "0: Transmit/receive in 9-bit data length,1: Transmit/receive in 8-bit data length(SMR.CHR=0).." bitfld.byte 0x0 3. "SDIR,Transmitted/Received Data Transfer DirectionNOTE: The setting is invalid and a fixed data length of 8 bits is used in modes other than asynchronous mode.Set this bit to 1 if operation is to be in simple I2C mode." "0: Transfer with LSB first,1: Transfer with MSB first" newline bitfld.byte 0x0 2. "SINV,Transmitted/Received Data InvertSet this bit to 0 if operation is to be in simple I2C mode." "0: TDR contents are transmitted as they are.,1: TDR contents are inverted before being.." bitfld.byte 0x0 1. "Reserved,This bit is read as 1. The write value should be 1." "0,1" newline bitfld.byte 0x0 0. "SMIF,Smart Card Interface Mode Select" "0: Non-smart card interface mode(Asynchronous mode..,1: Smart card interface mode" line.byte 0x1 "SEMR,Serial Extended Mode Register" bitfld.byte 0x1 7. "RXDESEL,Asynchronous Start Bit Edge Detection Select(Valid only in asynchronous mode)" "0: The low level on the RXDn pin is detected as the..,1: A falling edge on the RXDn pin is detected as.." bitfld.byte 0x1 6. "BGDM,Baud Rate Generator Double-Speed Mode Select(Only valid the CKE[1] bit in SCR is 0 in asynchronous mode)." "0: Baud rate generator outputs the clock with..,1: Baud rate generator outputs the clock with.." newline bitfld.byte 0x1 5. "NFEN,Digital Noise Filter Function Enable(The NFEN bit should be 0 without simple I2C mode and asynchronous mode.)In asynchronous mode for RXDn input only. In simple I2C mode for RXDn/TxDn input." "0: Noise cancellation function for the RXDn/SSCLn..,1: Noise cancellation function for the RXDn/SSCLn.." bitfld.byte 0x1 4. "ABCS,Asynchronous Mode Base Clock Select(Valid only in asynchronous mode)" "0: Selects 16 base clock cycles for 1-bit period.,1: Selects 8 base clock cycles for 1-bit period." newline bitfld.byte 0x1 3. "ABCSE,Asynchronous Mode Extended Base Clock Select 1(Valid only in asynchronous mode and SCR.CKE[1]=0)" "0: Clock cycles for 1-bit period is decided with..,1: Baud rate is 6 base clock cycles for 1-bit.." bitfld.byte 0x1 2. "BRME,Bit Rate Modulation Enable" "0: Bit rate modulation function is disabled.,1: Bit rate modulation function is enabled." newline bitfld.byte 0x1 0.--1. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" line.byte 0x2 "SNFR,Noise Filter Setting Register" hexmask.byte 0x2 3.--7. 1. "Reserved,These bits are read as 00000. The write value should be 00000." bitfld.byte 0x2 0.--2. "NFCS,Noise Filter Clock Select" "0: Settings prohibited.,1: The clock signal divided by 1 is used with the..,?,?,?,?,?,?" line.byte 0x3 "SIMR1,I2C Mode Register 1" hexmask.byte 0x3 3.--7. 1. "IICDL,SDA Delay Output SelectCycles below are of the clock signal from the on-chip baud rate generator." bitfld.byte 0x3 1.--2. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" newline bitfld.byte 0x3 0. "IICM,Simple I2C Mode Select" "0: Asynchronous mode Multi-processor mode Clock..,1: Simple I2C mode(SCMR.SMIF=0) / Setting.." line.byte 0x4 "SIMR2,I2C Mode Register 2" bitfld.byte 0x4 6.--7. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.byte 0x4 5. "IICACKT,ACK Transmission Data" "0: ACK transmission,1: NACK transmission and reception of ACK/NACK" newline bitfld.byte 0x4 2.--4. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.byte 0x4 1. "IICCSC,Clock Synchronization" "0: No synchronization with the clock signal,1: Synchronization with the clock signal" newline bitfld.byte 0x4 0. "IICINTM,I2C Interrupt Mode Select" "0: Use ACK/NACK interrupts.,1: Use reception and transmission interrupts" line.byte 0x5 "SIMR3,I2C Mode Register 3" bitfld.byte 0x5 6.--7. "IICSCLS,SCL Output Select" "0: Serial clock output,1: Generate a start restart or stop condition.,?,?" bitfld.byte 0x5 4.--5. "IICSDAS,SDA Output Select" "0: Serial data output,1: Generate a start restart or stop condition.,?,?" newline bitfld.byte 0x5 3. "IICSTIF,Issuing of Start Restart or Stop Condition Completed Flag(When 0 is written to IICSTIF it is cleared to 0.)" "0: There are no requests for generating conditions..,1: A start restart or stop condition is completely.." bitfld.byte 0x5 2. "IICSTPREQ,Stop Condition Generation" "0: A stop condition is not generated.,1: A stop condition is generated." newline bitfld.byte 0x5 1. "IICRSTAREQ,Restart Condition Generation" "0: A restart condition is not generated.,1: A restart condition is generated." bitfld.byte 0x5 0. "IICSTAREQ,Start Condition Generation" "0: A start condition is not generated.,1: A start condition is generated." rgroup.byte 0xC++0x0 line.byte 0x0 "SISR,I2C Status Register" bitfld.byte 0x0 6.--7. "Reserved,These bits are read as 00." "0,1,2,3" bitfld.byte 0x0 5. "Reserved,This bit is read as 0." "0,1" newline bitfld.byte 0x0 4. "Reserved,This bit is read as 0." "0,1" bitfld.byte 0x0 3. "Reserved,This bit is read as 0." "0,1" newline bitfld.byte 0x0 2. "Reserved,This bit is read as 0." "0,1" bitfld.byte 0x0 1. "Reserved,This bit is read as 0." "0,1" newline bitfld.byte 0x0 0. "IICACKR,ACK Reception Data Flag" "0: ACK received,1: NACK received" group.byte 0xD++0x0 line.byte 0x0 "SPMR,SPI Mode Register" bitfld.byte 0x0 7. "CKPH,Clock Phase Select" "0: Clock is not delayed.,1: Clock is delayed." bitfld.byte 0x0 6. "CKPOL,Clock Polarity Select" "0: Clock polarity is not inverted.,1: Clock polarity is inverted" newline bitfld.byte 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 4. "MFF,Mode Fault Flag" "0: No mode fault error,1: Mode fault error" newline bitfld.byte 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 2. "MSS,Master Slave Select" "0: Transmission is through the TXDn pin and..,1: Reception is through the TXDn pin and.." newline bitfld.byte 0x0 1. "CTSE,CTS Enable" "0: CTS function is disabled (RTS output function is..,1: CTS function is enabled." bitfld.byte 0x0 0. "SSE,SSn Pin Function Enable" "0: SSn pin function is disabled.,1: SSn pin function is enabled." wgroup.word 0xE++0x1 line.word 0x0 "TDRHL,Transmit 9-bit Data Register" hexmask.word 0x0 0.--15. 1. "TDRHL,TDRHL is a 16-bit register that stores transmit data." wgroup.word 0xE++0x1 line.word 0x0 "FTDRHL,Transmit FIFO Data Register HL" hexmask.word.byte 0x0 10.--15. 1. "Reserved,The write value should be 111111." bitfld.word 0x0 9. "MPBT,Multi-processor transfer bit flag(Valid only in asynchronous mode and SMR.MP=1 and FIFO selected)" "0: Data transmission cycles,1: ID transmission cycles" newline hexmask.word 0x0 0.--8. 1. "TDAT,Serial transmit data (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode and FIFO selected)" wgroup.byte 0xE++0x1 line.byte 0x0 "FTDRH,Transmit FIFO Data Register H" hexmask.byte 0x0 2.--7. 1. "Reserved,The write value should be 111111." bitfld.byte 0x0 1. "MPBT,Multi-processor transfer bit flag(Valid only in asynchronous mode and SMR.MP=1 and FIFO selected)" "0: Data transmission cycles,1: ID transmission cycles" newline bitfld.byte 0x0 0. "TDATH,Serial transmit data (b8) (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode and FIFO selected)" "0,1" line.byte 0x1 "FTDRL,Transmit FIFO Data Register L" hexmask.byte 0x1 0.--7. 1. "TDATL,Serial transmit data(b7-b0) (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode and FIFO selected)" rgroup.word 0x10++0x1 line.word 0x0 "RDRHL,Receive 9-bit Data Register" hexmask.word 0x0 0.--15. 1. "RDRHL,RDRHL is an 16-bit register that stores receive data." rgroup.word 0x10++0x1 line.word 0x0 "FRDRHL,Receive FIFO Data Register HL" bitfld.word 0x0 15. "Reserved,This bit is read as 0." "0,1" bitfld.word 0x0 14. "RDF,Receive FIFO data full flag(It is same as SSR.RDF)" "0: The quantity of receive data written in FRDRH..,1: The quantity of receive data written in FRDRH.." newline bitfld.word 0x0 13. "ORER,Overrun error flag(It is same as SSR.ORER)" "0: No overrun error occurred.,1: An overrun error has occurred." bitfld.word 0x0 12. "FER,Framing error flag" "0: No framing error occurred at the first data of..,1: A framing error has occurred at the first data.." newline bitfld.word 0x0 11. "PER,Parity error flag" "0: No parity error occurred at the first data of..,1: A parity error has occurred at the first data of.." bitfld.word 0x0 10. "DR,Receive data ready flag(It is same as SSR.DR)" "0: Receiving is in progress or no received data has..,1: Next receive data has not been received for a.." newline bitfld.word 0x0 9. "MPB,Multi-processor bit flag(Valid only in asynchronous mode with SMR.MP=1 and FIFO selected) It can read multi-processor bit corresponded to serial receive data(RDATA[8:0])" "0: Data transmission cycles,1: ID transmission cycles" hexmask.word 0x0 0.--8. 1. "RDAT,Serial receive data(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode and FIFO selected)" rgroup.byte 0x10++0x1 line.byte 0x0 "FRDRH,Receive FIFO Data Register H" bitfld.byte 0x0 7. "Reserved,This bit is read as 0." "0,1" bitfld.byte 0x0 6. "RDF,Receive FIFO data full flag(It is same as SSR.RDF)" "0: The quantity of receive data written in FRDRH..,1: The quantity of receive data written in FRDRH.." newline bitfld.byte 0x0 5. "ORER,Overrun error flag(It is same as SSR.ORER)" "0: No overrun error occurred,1: An overrun error has occurred" bitfld.byte 0x0 4. "FER,Framing error flag" "0: No framing error occurred at the first data of..,1: A framing error has occurred at the first data.." newline bitfld.byte 0x0 3. "PER,Parity error flag" "0: No parity error occurred at the first data of..,1: A parity error has occurred at the first data of.." bitfld.byte 0x0 2. "DR,Receive data ready flag(It is same as SSR.DR)" "0: Receiving is in progress or no received data has..,1: Next receive data has not been received for a.." newline bitfld.byte 0x0 1. "MPB,Multi-processor bit flag(Valid only in asynchronous mode with SMR.MP=1 and FIFO selected) It can read multi-processor bit corresponded to serial receive data(RDATA[8:0])" "0: Data transmission cycles,1: ID transmission cycles" bitfld.byte 0x0 0. "RDATH,Serial receive data(b8)(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode and FIFO selected)" "0,1" line.byte 0x1 "FRDRL,Receive FIFO Data Register L" hexmask.byte 0x1 0.--7. 1. "RDATL,Serial receive data(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode and FIFO selected)NOTE: When reading both of FRDRH register and FRDRL register please read by an order of the FRDRH register and the FRDRL.." group.byte 0x12++0x1 line.byte 0x0 "MDDR,Modulation Duty Register" hexmask.byte 0x0 0.--7. 1. "MDDR,MDDR corrects the bit rate adjusted by the BRR register." line.byte 0x1 "DCCR,Data Compare Match Control Register" bitfld.byte 0x1 7. "DCME,Data Compare Match Enable(Valid only in asynchronous mode(including multi-processor)" "0: Address match function is disabled.,1: Address match function is enabled" bitfld.byte 0x1 6. "IDSEL,ID frame select(Valid only in asynchronous mode(including multi-processor)" "0: Always compare data regardless of the value of..,1: Compare data when the MPB bit is 1 (ID frame).." newline bitfld.byte 0x1 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x1 4. "DFER,Data Compare Match Framing Error Flag" "0: No framing error occurred,1: A framing error has occurred" newline bitfld.byte 0x1 3. "DPER,Data Compare Match Parity Error Flag" "0: No parity error occurred,1: A parity error has occurred" bitfld.byte 0x1 1.--2. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" newline bitfld.byte 0x1 0. "DCMF,Data Compare Match Flag" "0: No matched,1: Matched" group.word 0x14++0x1 line.word 0x0 "FCR,FIFO Control Register" hexmask.word.byte 0x0 12.--15. 1. "RSTRG,RTS Output Active Trigger Number Select(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode)" hexmask.word.byte 0x0 8.--11. 1. "RTRG,Receive FIFO data trigger number(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode)" newline hexmask.word.byte 0x0 4.--7. 1. "TTRG,Transmit FIFO data trigger number(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode)" bitfld.word 0x0 3. "DRES,Receive data ready error select bit(When detecting a reception data ready the interrupt request is selected.)" "0: reception data full interrupt (RXI),1: receive error interrupt (ERI)" newline bitfld.word 0x0 2. "TFRST,Transmit FIFO Data Register Reset(Valid only in FCR.FM=1)" "0: The number of data stored in FTDRH and FTDRL..,1: The number of data stored in FTDRH and FTDRL.." bitfld.word 0x0 1. "RFRST,Receive FIFO Data Register Reset(Valid only in FCR.FM=1)" "0: The number of data stored in FRDRH and FRDRL..,1: The number of data stored in FRDRH and FRDRL.." newline bitfld.word 0x0 0. "FM,FIFO Mode Select(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode)" "0: Non-FIFO mode(Selects o TDR/RDR for communication),1: FIFO mode (Selects to FTDRH and FTDRL/FRDRH and.." rgroup.word 0x16++0x3 line.word 0x0 "FDR,FIFO Data Count Register" bitfld.word 0x0 13.--15. "Reserved,These bits are read as 000." "0,1,2,3,4,5,6,7" hexmask.word.byte 0x0 8.--12. 1. "T,Transmit FIFO Data CountIndicate the quantity of non-transmit data stored in FTDRH and FTDRL(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode while FCR.FM=1)" newline bitfld.word 0x0 5.--7. "Reserved,These bits are read as 000." "0,1,2,3,4,5,6,7" hexmask.word.byte 0x0 0.--4. 1. "R,Receive FIFO Data CountIndicate the quantity of receive data stored in FRDRH and FRDRL(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode while FCR.FM=1)" line.word 0x2 "LSR,Line Status Register" bitfld.word 0x2 13.--15. "Reserved,These bits are read as 000." "0,1,2,3,4,5,6,7" hexmask.word.byte 0x2 8.--12. 1. "PNUM,Parity Error CountIndicates the quantity of data with a parity error among the receive data stored in the receive FIFO data register (FRDRH and FRDRL)." newline bitfld.word 0x2 7. "Reserved,This bit is read as 0." "0,1" hexmask.word.byte 0x2 2.--6. 1. "FNUM,Framing Error CountIndicates the quantity of data with a framing error among the receive data stored in the receive FIFO data register (FRDRH and FRDRL)." newline bitfld.word 0x2 1. "Reserved,This bit is read as 0." "0,1" bitfld.word 0x2 0. "ORER,Overrun Error Flag (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode and FIFO selected)" "0: No overrun error occurred,1: An overrun error has occurred" group.word 0x1A++0x1 line.word 0x0 "CDR,Compare Match Data Register" hexmask.word.byte 0x0 9.--15. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." hexmask.word 0x0 0.--8. 1. "CMPD,Compare Match DataCompare data pattern for address match wake-up function" group.byte 0x1C++0x0 line.byte 0x0 "SPTR,Serial Port Register" hexmask.byte 0x0 3.--7. 1. "Reserved,These bits are read as 00000. The write value should be 00000." bitfld.byte 0x0 2. "SPB2IO,Serial port break I/O bit(It's selected whether the value of SPB2DT is output to TxD terminal.)" "0: The value of SPB2DT bit is not output in TXD pin.,1: The value of SPB2DT bit is output in TXD pin." newline bitfld.byte 0x0 1. "SPB2DT,Serial port break data select bit(The output level of TxD terminal is selected when SCR.TE = 0.)" "0: Low level is output on TXD pin,1: High level is output on TXD pin" rbitfld.byte 0x0 0. "RXDMON,Serial input data monitor bit(The state of the RXD terminal is shown.)" "0: RXD pin is low.,1: RXD pin is high." tree.end tree "SCI2" base ad:0x40070040 group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register (SCMR.SMIF = 0)" bitfld.byte 0x0 7. "CM,Communication Mode" "0: Asynchronous mode or simple I2C mode,1: Clock synchronous mode" bitfld.byte 0x0 6. "CHR,Character Length(Valid only in asynchronous mode)" "0: Transmit/receive in 9-bit data..,1: Transmit/receive in 9-bit data.." newline bitfld.byte 0x0 5. "PE,Parity Enable(Valid only in asynchronous mode)" "0: Parity bit addition is not performed..,1: The parity bit is added (transmitting) / The.." bitfld.byte 0x0 4. "PM,Parity Mode (Valid only when the PE bit is 1)" "0: Selects even parity,1: Selects odd parity" newline bitfld.byte 0x0 3. "STOP,Stop Bit Length(Valid only in asynchronous mode)" "0: 1 stop bit,1: 2 stop bits" bitfld.byte 0x0 2. "MP,Multi-Processor Mode(Valid only in asynchronous mode)" "0: Multi-processor communications function is..,1: Multi-processor communications function is enabled" newline bitfld.byte 0x0 0.--1. "CKS,Clock Select" "0: PCLK clock,1: PCLK/4 clock,?,?" group.byte 0x0++0x2 line.byte 0x0 "SMR_SMCI,Serial mode register (SCMR.SMIF = 1)" bitfld.byte 0x0 7. "GM,GSM Mode" "0: Normal mode operation,1: GSM mode operation" bitfld.byte 0x0 6. "BLK,Block Transfer Mode" "0: Normal mode operation,1: Block transfer mode operation" newline bitfld.byte 0x0 5. "PE,Parity Enable(Valid only in asynchronous mode)" "0: Setting Prohibited,1: Set this bit to 1 in smart card interface mode." bitfld.byte 0x0 4. "PM,Parity Mode (Valid only when the PE bit is 1)" "0: Selects even parity,1: Selects odd parity" newline bitfld.byte 0x0 2.--3. "BCP,Base Clock Pulse(Valid only in asynchronous mode)" "0: 93 clock cycles(S=93) (SCMR.BCP2=0) / 32 clock..,1: 128 clock cycles(S=128) (SCMR.BCP2=0) / 64 clock..,?,?" bitfld.byte 0x0 0.--1. "CKS,Clock Select" "0: PCLK clock,1: PCLK/4 clock,?,?" line.byte 0x1 "BRR,Bit Rate Register" hexmask.byte 0x1 0.--7. 1. "BRR,BRR is an 8-bit register that adjusts the bit rate." line.byte 0x2 "SCR,Serial Control Register (SCMR.SMIF = 0)" bitfld.byte 0x2 7. "TIE,Transmit Interrupt Enable" "0: SCI_TXI interrupt request is disabled,1: SCI_TXI interrupt request is enabled" bitfld.byte 0x2 6. "RIE,Receive Interrupt Enable" "0: SCI_RXI and SCI_ERI interrupt requests are..,1: SCI_RXI and SCI_ERI interrupt requests are enabled" newline bitfld.byte 0x2 5. "TE,Transmit Enable" "0: Serial transmission is disabled,1: Serial transmission is enabled" bitfld.byte 0x2 4. "RE,Receive Enable" "0: Serial reception is disabled,1: Serial reception is enabled" newline bitfld.byte 0x2 3. "MPIE,Multi-Processor Interrupt Enable(Valid in asynchronous mode when SMR.MP = 1)" "0: Normal reception,1: When the data with the multi-processor bit set.." bitfld.byte 0x2 2. "TEIE,Transmit End Interrupt Enable" "0: SCI_TEI interrupt request is disabled,1: SCI_TEI interrupt request is enabled" newline bitfld.byte 0x2 0.--1. "CKE,Clock Enable" "0: The clock with a frequency 16 times the bit rate..,1: The clock with the same frequency as the bit..,?,?" group.byte 0x2++0x2 line.byte 0x0 "SCR_SMCI,Serial Control Register (SCMR.SMIF =1)" bitfld.byte 0x0 7. "TIE,Transmit Interrupt Enable" "0: A SCI_TXI interrupt request is disabled,1: A SCI_TXI interrupt request is enabled" bitfld.byte 0x0 6. "RIE,Receive Interrupt Enable" "0: SCI_RXI and SCI_ERI interrupt requests are..,1: SCI_RXI and SCI_ERI interrupt requests are enabled" newline bitfld.byte 0x0 5. "TE,Transmit Enable" "0: Serial transmission is disabled,1: Serial transmission is enabled" bitfld.byte 0x0 4. "RE,Receive Enable" "0: Serial reception is disabled,1: Serial reception is enabled" newline bitfld.byte 0x0 3. "MPIE,Multi-Processor Interrupt Enable" "0,1" bitfld.byte 0x0 2. "TEIE,Transmit End Interrupt Enable" "0,1" newline bitfld.byte 0x0 0.--1. "CKE,Clock Enable" "0: Output disabled(SMR_SMCI.GM=0) / Output fixed..,1: Clock Output,?,?" line.byte 0x1 "TDR,Transmit Data Register" hexmask.byte 0x1 0.--7. 1. "TDR,TDR is an 8-bit register that stores transmit data." line.byte 0x2 "SSR,Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0)" bitfld.byte 0x2 7. "TDRE,Transmit Data Empty Flag" "0: Transmit data is in TDR register,1: No transmit data is in TDR register" bitfld.byte 0x2 6. "RDRF,Receive Data Full Flag" "0: No received data is in RDR register,1: Received data is in RDR register" newline bitfld.byte 0x2 5. "ORER,Overrun Error Flag" "0: No overrun error occurred,1: An overrun error has occurred" bitfld.byte 0x2 4. "FER,Framing Error Flag" "0: No framing error occurred,1: A framing error has occurred" newline bitfld.byte 0x2 3. "PER,Parity Error Flag" "0: No parity error occurred,1: A parity error has occurred" rbitfld.byte 0x2 2. "TEND,Transmit End Flag" "0: A character is being transmitted.,1: Character transfer has been completed." newline rbitfld.byte 0x2 1. "MPB,Multi-Processor" "0: Data transmission cycles,1: ID transmission cycles" bitfld.byte 0x2 0. "MPBT,Multi-Processor Bit Transfer" "0: Data transmission cycles,1: ID transmission cycles" group.byte 0x4++0x0 line.byte 0x0 "SSR_SMCI,Serial Status Register(SCMR.SMIF = 1)" bitfld.byte 0x0 7. "TDRE,Transmit Data Empty Flag" "0: Transmit data is in TDR register,1: No transmit data is in TDR register" bitfld.byte 0x0 6. "RDRF,Receive Data Full Flag" "0: No received data is in RDR register,1: Received data is in RDR register" newline bitfld.byte 0x0 5. "ORER,Overrun Error Flag" "0: No overrun error occurred,1: An overrun error has occurred" bitfld.byte 0x0 4. "ERS,Error Signal Status Flag" "0: Low error signal not responded,1: Low error signal responded" newline bitfld.byte 0x0 3. "PER,Parity Error Flag" "0: No parity error occurred,1: A parity error has occurred" rbitfld.byte 0x0 2. "TEND,Transmit End Flag" "0: A character is being transmitted.,1: Character transfer has been completed." newline rbitfld.byte 0x0 1. "MPB,Multi-ProcessorThis bit should be 0 in smart card interface mode." "0,1" bitfld.byte 0x0 0. "MPBT,Multi-Processor Bit TransferThis bit should be 0 in smart card interface mode." "0,1" rgroup.byte 0x5++0x0 line.byte 0x0 "RDR,Receive Data Register" hexmask.byte 0x0 0.--7. 1. "RDR,RDR is an 8-bit register that stores receive data." group.byte 0x6++0x5 line.byte 0x0 "SCMR,Smart Card Mode Register" bitfld.byte 0x0 7. "BCP2,Base Clock Pulse 2Selects the number of base clock cycles in combination with the SMR.BCP[1:0] bits" "0: S=93(SMR.BCP[1:0]=00) 128(SMR.BCP[1:0]=01)..,1: S=32(SMR.BCP[1:0]=00) 64(SMR.BCP[1:0]=01).." bitfld.byte 0x0 5.--6. "Reserved,These bits are read as 11. The write value should be 11." "0,1,2,3" newline bitfld.byte 0x0 4. "CHR1,Character Length 1(Only valid in asynchronous mode)" "0: Transmit/receive in 9-bit data length,1: Transmit/receive in 8-bit data length(SMR.CHR=0).." bitfld.byte 0x0 3. "SDIR,Transmitted/Received Data Transfer DirectionNOTE: The setting is invalid and a fixed data length of 8 bits is used in modes other than asynchronous mode.Set this bit to 1 if operation is to be in simple I2C mode." "0: Transfer with LSB first,1: Transfer with MSB first" newline bitfld.byte 0x0 2. "SINV,Transmitted/Received Data InvertSet this bit to 0 if operation is to be in simple I2C mode." "0: TDR contents are transmitted as they are.,1: TDR contents are inverted before being.." bitfld.byte 0x0 1. "Reserved,This bit is read as 1. The write value should be 1." "0,1" newline bitfld.byte 0x0 0. "SMIF,Smart Card Interface Mode Select" "0: Non-smart card interface mode(Asynchronous mode..,1: Smart card interface mode" line.byte 0x1 "SEMR,Serial Extended Mode Register" bitfld.byte 0x1 7. "RXDESEL,Asynchronous Start Bit Edge Detection Select(Valid only in asynchronous mode)" "0: The low level on the RXDn pin is detected as the..,1: A falling edge on the RXDn pin is detected as.." bitfld.byte 0x1 6. "BGDM,Baud Rate Generator Double-Speed Mode Select(Only valid the CKE[1] bit in SCR is 0 in asynchronous mode)." "0: Baud rate generator outputs the clock with..,1: Baud rate generator outputs the clock with.." newline bitfld.byte 0x1 5. "NFEN,Digital Noise Filter Function Enable(The NFEN bit should be 0 without simple I2C mode and asynchronous mode.)In asynchronous mode for RXDn input only. In simple I2C mode for RXDn/TxDn input." "0: Noise cancellation function for the RXDn/SSCLn..,1: Noise cancellation function for the RXDn/SSCLn.." bitfld.byte 0x1 4. "ABCS,Asynchronous Mode Base Clock Select(Valid only in asynchronous mode)" "0: Selects 16 base clock cycles for 1-bit period.,1: Selects 8 base clock cycles for 1-bit period." newline bitfld.byte 0x1 3. "ABCSE,Asynchronous Mode Extended Base Clock Select 1(Valid only in asynchronous mode and SCR.CKE[1]=0)" "0: Clock cycles for 1-bit period is decided with..,1: Baud rate is 6 base clock cycles for 1-bit.." bitfld.byte 0x1 2. "BRME,Bit Rate Modulation Enable" "0: Bit rate modulation function is disabled.,1: Bit rate modulation function is enabled." newline bitfld.byte 0x1 0.--1. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" line.byte 0x2 "SNFR,Noise Filter Setting Register" hexmask.byte 0x2 3.--7. 1. "Reserved,These bits are read as 00000. The write value should be 00000." bitfld.byte 0x2 0.--2. "NFCS,Noise Filter Clock Select" "0: Settings prohibited.,1: The clock signal divided by 1 is used with the..,?,?,?,?,?,?" line.byte 0x3 "SIMR1,I2C Mode Register 1" hexmask.byte 0x3 3.--7. 1. "IICDL,SDA Delay Output SelectCycles below are of the clock signal from the on-chip baud rate generator." bitfld.byte 0x3 1.--2. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" newline bitfld.byte 0x3 0. "IICM,Simple I2C Mode Select" "0: Asynchronous mode Multi-processor mode Clock..,1: Simple I2C mode(SCMR.SMIF=0) / Setting.." line.byte 0x4 "SIMR2,I2C Mode Register 2" bitfld.byte 0x4 6.--7. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.byte 0x4 5. "IICACKT,ACK Transmission Data" "0: ACK transmission,1: NACK transmission and reception of ACK/NACK" newline bitfld.byte 0x4 2.--4. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.byte 0x4 1. "IICCSC,Clock Synchronization" "0: No synchronization with the clock signal,1: Synchronization with the clock signal" newline bitfld.byte 0x4 0. "IICINTM,I2C Interrupt Mode Select" "0: Use ACK/NACK interrupts.,1: Use reception and transmission interrupts" line.byte 0x5 "SIMR3,I2C Mode Register 3" bitfld.byte 0x5 6.--7. "IICSCLS,SCL Output Select" "0: Serial clock output,1: Generate a start restart or stop condition.,?,?" bitfld.byte 0x5 4.--5. "IICSDAS,SDA Output Select" "0: Serial data output,1: Generate a start restart or stop condition.,?,?" newline bitfld.byte 0x5 3. "IICSTIF,Issuing of Start Restart or Stop Condition Completed Flag(When 0 is written to IICSTIF it is cleared to 0.)" "0: There are no requests for generating conditions..,1: A start restart or stop condition is completely.." bitfld.byte 0x5 2. "IICSTPREQ,Stop Condition Generation" "0: A stop condition is not generated.,1: A stop condition is generated." newline bitfld.byte 0x5 1. "IICRSTAREQ,Restart Condition Generation" "0: A restart condition is not generated.,1: A restart condition is generated." bitfld.byte 0x5 0. "IICSTAREQ,Start Condition Generation" "0: A start condition is not generated.,1: A start condition is generated." rgroup.byte 0xC++0x0 line.byte 0x0 "SISR,I2C Status Register" bitfld.byte 0x0 6.--7. "Reserved,These bits are read as 00." "0,1,2,3" bitfld.byte 0x0 5. "Reserved,This bit is read as 0." "0,1" newline bitfld.byte 0x0 4. "Reserved,This bit is read as 0." "0,1" bitfld.byte 0x0 3. "Reserved,This bit is read as 0." "0,1" newline bitfld.byte 0x0 2. "Reserved,This bit is read as 0." "0,1" bitfld.byte 0x0 1. "Reserved,This bit is read as 0." "0,1" newline bitfld.byte 0x0 0. "IICACKR,ACK Reception Data Flag" "0: ACK received,1: NACK received" group.byte 0xD++0x0 line.byte 0x0 "SPMR,SPI Mode Register" bitfld.byte 0x0 7. "CKPH,Clock Phase Select" "0: Clock is not delayed.,1: Clock is delayed." bitfld.byte 0x0 6. "CKPOL,Clock Polarity Select" "0: Clock polarity is not inverted.,1: Clock polarity is inverted" newline bitfld.byte 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 4. "MFF,Mode Fault Flag" "0: No mode fault error,1: Mode fault error" newline bitfld.byte 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 2. "MSS,Master Slave Select" "0: Transmission is through the TXDn pin and..,1: Reception is through the TXDn pin and.." newline bitfld.byte 0x0 1. "CTSE,CTS Enable" "0: CTS function is disabled (RTS output function is..,1: CTS function is enabled." bitfld.byte 0x0 0. "SSE,SSn Pin Function Enable" "0: SSn pin function is disabled.,1: SSn pin function is enabled." wgroup.word 0xE++0x1 line.word 0x0 "TDRHL,Transmit 9-bit Data Register" hexmask.word 0x0 0.--15. 1. "TDRHL,TDRHL is a 16-bit register that stores transmit data." rgroup.word 0x10++0x1 line.word 0x0 "RDRHL,Receive 9-bit Data Register" hexmask.word 0x0 0.--15. 1. "RDRHL,RDRHL is an 16-bit register that stores receive data." group.byte 0x12++0x1 line.byte 0x0 "MDDR,Modulation Duty Register" hexmask.byte 0x0 0.--7. 1. "MDDR,MDDR corrects the bit rate adjusted by the BRR register." line.byte 0x1 "DCCR,Data Compare Match Control Register" bitfld.byte 0x1 7. "DCME,Data Compare Match Enable(Valid only in asynchronous mode(including multi-processor)" "0: Address match function is disabled.,1: Address match function is enabled" bitfld.byte 0x1 6. "IDSEL,ID frame select(Valid only in asynchronous mode(including multi-processor)" "0: Always compare data regardless of the value of..,1: Compare data when the MPB bit is 1 (ID frame).." newline bitfld.byte 0x1 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x1 4. "DFER,Data Compare Match Framing Error Flag" "0: No framing error occurred,1: A framing error has occurred" newline bitfld.byte 0x1 3. "DPER,Data Compare Match Parity Error Flag" "0: No parity error occurred,1: A parity error has occurred" bitfld.byte 0x1 1.--2. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" newline bitfld.byte 0x1 0. "DCMF,Data Compare Match Flag" "0: No matched,1: Matched" group.word 0x1A++0x1 line.word 0x0 "CDR,Compare Match Data Register" hexmask.word.byte 0x0 9.--15. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." hexmask.word 0x0 0.--8. 1. "CMPD,Compare Match DataCompare data pattern for address match wake-up function" group.byte 0x1C++0x0 line.byte 0x0 "SPTR,Serial Port Register" hexmask.byte 0x0 3.--7. 1. "Reserved,These bits are read as 00000. The write value should be 00000." bitfld.byte 0x0 2. "SPB2IO,Serial port break I/O bit(It's selected whether the value of SPB2DT is output to TxD terminal.)" "0: The value of SPB2DT bit is not output in TXD pin.,1: The value of SPB2DT bit is output in TXD pin." newline bitfld.byte 0x0 1. "SPB2DT,Serial port break data select bit(The output level of TxD terminal is selected when SCR.TE = 0.)" "0: Low level is output on TXD pin,1: High level is output on TXD pin" rbitfld.byte 0x0 0. "RXDMON,Serial input data monitor bit(The state of the RXD terminal is shown.)" "0: RXD pin is low.,1: RXD pin is high." tree.end tree "SCI3" base ad:0x40070060 group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register (SCMR.SMIF = 0)" bitfld.byte 0x0 7. "CM,Communication Mode" "0: Asynchronous mode or simple I2C mode,1: Clock synchronous mode" bitfld.byte 0x0 6. "CHR,Character Length(Valid only in asynchronous mode)" "0: Transmit/receive in 9-bit data..,1: Transmit/receive in 9-bit data.." newline bitfld.byte 0x0 5. "PE,Parity Enable(Valid only in asynchronous mode)" "0: Parity bit addition is not performed..,1: The parity bit is added (transmitting) / The.." bitfld.byte 0x0 4. "PM,Parity Mode (Valid only when the PE bit is 1)" "0: Selects even parity,1: Selects odd parity" newline bitfld.byte 0x0 3. "STOP,Stop Bit Length(Valid only in asynchronous mode)" "0: 1 stop bit,1: 2 stop bits" bitfld.byte 0x0 2. "MP,Multi-Processor Mode(Valid only in asynchronous mode)" "0: Multi-processor communications function is..,1: Multi-processor communications function is enabled" newline bitfld.byte 0x0 0.--1. "CKS,Clock Select" "0: PCLK clock,1: PCLK/4 clock,?,?" group.byte 0x0++0x2 line.byte 0x0 "SMR_SMCI,Serial mode register (SCMR.SMIF = 1)" bitfld.byte 0x0 7. "GM,GSM Mode" "0: Normal mode operation,1: GSM mode operation" bitfld.byte 0x0 6. "BLK,Block Transfer Mode" "0: Normal mode operation,1: Block transfer mode operation" newline bitfld.byte 0x0 5. "PE,Parity Enable(Valid only in asynchronous mode)" "0: Setting Prohibited,1: Set this bit to 1 in smart card interface mode." bitfld.byte 0x0 4. "PM,Parity Mode (Valid only when the PE bit is 1)" "0: Selects even parity,1: Selects odd parity" newline bitfld.byte 0x0 2.--3. "BCP,Base Clock Pulse(Valid only in asynchronous mode)" "0: 93 clock cycles(S=93) (SCMR.BCP2=0) / 32 clock..,1: 128 clock cycles(S=128) (SCMR.BCP2=0) / 64 clock..,?,?" bitfld.byte 0x0 0.--1. "CKS,Clock Select" "0: PCLK clock,1: PCLK/4 clock,?,?" line.byte 0x1 "BRR,Bit Rate Register" hexmask.byte 0x1 0.--7. 1. "BRR,BRR is an 8-bit register that adjusts the bit rate." line.byte 0x2 "SCR,Serial Control Register (SCMR.SMIF = 0)" bitfld.byte 0x2 7. "TIE,Transmit Interrupt Enable" "0: SCI_TXI interrupt request is disabled,1: SCI_TXI interrupt request is enabled" bitfld.byte 0x2 6. "RIE,Receive Interrupt Enable" "0: SCI_RXI and SCI_ERI interrupt requests are..,1: SCI_RXI and SCI_ERI interrupt requests are enabled" newline bitfld.byte 0x2 5. "TE,Transmit Enable" "0: Serial transmission is disabled,1: Serial transmission is enabled" bitfld.byte 0x2 4. "RE,Receive Enable" "0: Serial reception is disabled,1: Serial reception is enabled" newline bitfld.byte 0x2 3. "MPIE,Multi-Processor Interrupt Enable(Valid in asynchronous mode when SMR.MP = 1)" "0: Normal reception,1: When the data with the multi-processor bit set.." bitfld.byte 0x2 2. "TEIE,Transmit End Interrupt Enable" "0: SCI_TEI interrupt request is disabled,1: SCI_TEI interrupt request is enabled" newline bitfld.byte 0x2 0.--1. "CKE,Clock Enable" "0: The clock with a frequency 16 times the bit rate..,1: The clock with the same frequency as the bit..,?,?" group.byte 0x2++0x2 line.byte 0x0 "SCR_SMCI,Serial Control Register (SCMR.SMIF =1)" bitfld.byte 0x0 7. "TIE,Transmit Interrupt Enable" "0: A SCI_TXI interrupt request is disabled,1: A SCI_TXI interrupt request is enabled" bitfld.byte 0x0 6. "RIE,Receive Interrupt Enable" "0: SCI_RXI and SCI_ERI interrupt requests are..,1: SCI_RXI and SCI_ERI interrupt requests are enabled" newline bitfld.byte 0x0 5. "TE,Transmit Enable" "0: Serial transmission is disabled,1: Serial transmission is enabled" bitfld.byte 0x0 4. "RE,Receive Enable" "0: Serial reception is disabled,1: Serial reception is enabled" newline bitfld.byte 0x0 3. "MPIE,Multi-Processor Interrupt Enable" "0,1" bitfld.byte 0x0 2. "TEIE,Transmit End Interrupt Enable" "0,1" newline bitfld.byte 0x0 0.--1. "CKE,Clock Enable" "0: Output disabled(SMR_SMCI.GM=0) / Output fixed..,1: Clock Output,?,?" line.byte 0x1 "TDR,Transmit Data Register" hexmask.byte 0x1 0.--7. 1. "TDR,TDR is an 8-bit register that stores transmit data." line.byte 0x2 "SSR,Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0)" bitfld.byte 0x2 7. "TDRE,Transmit Data Empty Flag" "0: Transmit data is in TDR register,1: No transmit data is in TDR register" bitfld.byte 0x2 6. "RDRF,Receive Data Full Flag" "0: No received data is in RDR register,1: Received data is in RDR register" newline bitfld.byte 0x2 5. "ORER,Overrun Error Flag" "0: No overrun error occurred,1: An overrun error has occurred" bitfld.byte 0x2 4. "FER,Framing Error Flag" "0: No framing error occurred,1: A framing error has occurred" newline bitfld.byte 0x2 3. "PER,Parity Error Flag" "0: No parity error occurred,1: A parity error has occurred" rbitfld.byte 0x2 2. "TEND,Transmit End Flag" "0: A character is being transmitted.,1: Character transfer has been completed." newline rbitfld.byte 0x2 1. "MPB,Multi-Processor" "0: Data transmission cycles,1: ID transmission cycles" bitfld.byte 0x2 0. "MPBT,Multi-Processor Bit Transfer" "0: Data transmission cycles,1: ID transmission cycles" group.byte 0x4++0x0 line.byte 0x0 "SSR_SMCI,Serial Status Register(SCMR.SMIF = 1)" bitfld.byte 0x0 7. "TDRE,Transmit Data Empty Flag" "0: Transmit data is in TDR register,1: No transmit data is in TDR register" bitfld.byte 0x0 6. "RDRF,Receive Data Full Flag" "0: No received data is in RDR register,1: Received data is in RDR register" newline bitfld.byte 0x0 5. "ORER,Overrun Error Flag" "0: No overrun error occurred,1: An overrun error has occurred" bitfld.byte 0x0 4. "ERS,Error Signal Status Flag" "0: Low error signal not responded,1: Low error signal responded" newline bitfld.byte 0x0 3. "PER,Parity Error Flag" "0: No parity error occurred,1: A parity error has occurred" rbitfld.byte 0x0 2. "TEND,Transmit End Flag" "0: A character is being transmitted.,1: Character transfer has been completed." newline rbitfld.byte 0x0 1. "MPB,Multi-ProcessorThis bit should be 0 in smart card interface mode." "0,1" bitfld.byte 0x0 0. "MPBT,Multi-Processor Bit TransferThis bit should be 0 in smart card interface mode." "0,1" rgroup.byte 0x5++0x0 line.byte 0x0 "RDR,Receive Data Register" hexmask.byte 0x0 0.--7. 1. "RDR,RDR is an 8-bit register that stores receive data." group.byte 0x6++0x5 line.byte 0x0 "SCMR,Smart Card Mode Register" bitfld.byte 0x0 7. "BCP2,Base Clock Pulse 2Selects the number of base clock cycles in combination with the SMR.BCP[1:0] bits" "0: S=93(SMR.BCP[1:0]=00) 128(SMR.BCP[1:0]=01)..,1: S=32(SMR.BCP[1:0]=00) 64(SMR.BCP[1:0]=01).." bitfld.byte 0x0 5.--6. "Reserved,These bits are read as 11. The write value should be 11." "0,1,2,3" newline bitfld.byte 0x0 4. "CHR1,Character Length 1(Only valid in asynchronous mode)" "0: Transmit/receive in 9-bit data length,1: Transmit/receive in 8-bit data length(SMR.CHR=0).." bitfld.byte 0x0 3. "SDIR,Transmitted/Received Data Transfer DirectionNOTE: The setting is invalid and a fixed data length of 8 bits is used in modes other than asynchronous mode.Set this bit to 1 if operation is to be in simple I2C mode." "0: Transfer with LSB first,1: Transfer with MSB first" newline bitfld.byte 0x0 2. "SINV,Transmitted/Received Data InvertSet this bit to 0 if operation is to be in simple I2C mode." "0: TDR contents are transmitted as they are.,1: TDR contents are inverted before being.." bitfld.byte 0x0 1. "Reserved,This bit is read as 1. The write value should be 1." "0,1" newline bitfld.byte 0x0 0. "SMIF,Smart Card Interface Mode Select" "0: Non-smart card interface mode(Asynchronous mode..,1: Smart card interface mode" line.byte 0x1 "SEMR,Serial Extended Mode Register" bitfld.byte 0x1 7. "RXDESEL,Asynchronous Start Bit Edge Detection Select(Valid only in asynchronous mode)" "0: The low level on the RXDn pin is detected as the..,1: A falling edge on the RXDn pin is detected as.." bitfld.byte 0x1 6. "BGDM,Baud Rate Generator Double-Speed Mode Select(Only valid the CKE[1] bit in SCR is 0 in asynchronous mode)." "0: Baud rate generator outputs the clock with..,1: Baud rate generator outputs the clock with.." newline bitfld.byte 0x1 5. "NFEN,Digital Noise Filter Function Enable(The NFEN bit should be 0 without simple I2C mode and asynchronous mode.)In asynchronous mode for RXDn input only. In simple I2C mode for RXDn/TxDn input." "0: Noise cancellation function for the RXDn/SSCLn..,1: Noise cancellation function for the RXDn/SSCLn.." bitfld.byte 0x1 4. "ABCS,Asynchronous Mode Base Clock Select(Valid only in asynchronous mode)" "0: Selects 16 base clock cycles for 1-bit period.,1: Selects 8 base clock cycles for 1-bit period." newline bitfld.byte 0x1 3. "ABCSE,Asynchronous Mode Extended Base Clock Select 1(Valid only in asynchronous mode and SCR.CKE[1]=0)" "0: Clock cycles for 1-bit period is decided with..,1: Baud rate is 6 base clock cycles for 1-bit.." bitfld.byte 0x1 2. "BRME,Bit Rate Modulation Enable" "0: Bit rate modulation function is disabled.,1: Bit rate modulation function is enabled." newline bitfld.byte 0x1 0.--1. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" line.byte 0x2 "SNFR,Noise Filter Setting Register" hexmask.byte 0x2 3.--7. 1. "Reserved,These bits are read as 00000. The write value should be 00000." bitfld.byte 0x2 0.--2. "NFCS,Noise Filter Clock Select" "0: Settings prohibited.,1: The clock signal divided by 1 is used with the..,?,?,?,?,?,?" line.byte 0x3 "SIMR1,I2C Mode Register 1" hexmask.byte 0x3 3.--7. 1. "IICDL,SDA Delay Output SelectCycles below are of the clock signal from the on-chip baud rate generator." bitfld.byte 0x3 1.--2. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" newline bitfld.byte 0x3 0. "IICM,Simple I2C Mode Select" "0: Asynchronous mode Multi-processor mode Clock..,1: Simple I2C mode(SCMR.SMIF=0) / Setting.." line.byte 0x4 "SIMR2,I2C Mode Register 2" bitfld.byte 0x4 6.--7. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.byte 0x4 5. "IICACKT,ACK Transmission Data" "0: ACK transmission,1: NACK transmission and reception of ACK/NACK" newline bitfld.byte 0x4 2.--4. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.byte 0x4 1. "IICCSC,Clock Synchronization" "0: No synchronization with the clock signal,1: Synchronization with the clock signal" newline bitfld.byte 0x4 0. "IICINTM,I2C Interrupt Mode Select" "0: Use ACK/NACK interrupts.,1: Use reception and transmission interrupts" line.byte 0x5 "SIMR3,I2C Mode Register 3" bitfld.byte 0x5 6.--7. "IICSCLS,SCL Output Select" "0: Serial clock output,1: Generate a start restart or stop condition.,?,?" bitfld.byte 0x5 4.--5. "IICSDAS,SDA Output Select" "0: Serial data output,1: Generate a start restart or stop condition.,?,?" newline bitfld.byte 0x5 3. "IICSTIF,Issuing of Start Restart or Stop Condition Completed Flag(When 0 is written to IICSTIF it is cleared to 0.)" "0: There are no requests for generating conditions..,1: A start restart or stop condition is completely.." bitfld.byte 0x5 2. "IICSTPREQ,Stop Condition Generation" "0: A stop condition is not generated.,1: A stop condition is generated." newline bitfld.byte 0x5 1. "IICRSTAREQ,Restart Condition Generation" "0: A restart condition is not generated.,1: A restart condition is generated." bitfld.byte 0x5 0. "IICSTAREQ,Start Condition Generation" "0: A start condition is not generated.,1: A start condition is generated." rgroup.byte 0xC++0x0 line.byte 0x0 "SISR,I2C Status Register" bitfld.byte 0x0 6.--7. "Reserved,These bits are read as 00." "0,1,2,3" bitfld.byte 0x0 5. "Reserved,This bit is read as 0." "0,1" newline bitfld.byte 0x0 4. "Reserved,This bit is read as 0." "0,1" bitfld.byte 0x0 3. "Reserved,This bit is read as 0." "0,1" newline bitfld.byte 0x0 2. "Reserved,This bit is read as 0." "0,1" bitfld.byte 0x0 1. "Reserved,This bit is read as 0." "0,1" newline bitfld.byte 0x0 0. "IICACKR,ACK Reception Data Flag" "0: ACK received,1: NACK received" group.byte 0xD++0x0 line.byte 0x0 "SPMR,SPI Mode Register" bitfld.byte 0x0 7. "CKPH,Clock Phase Select" "0: Clock is not delayed.,1: Clock is delayed." bitfld.byte 0x0 6. "CKPOL,Clock Polarity Select" "0: Clock polarity is not inverted.,1: Clock polarity is inverted" newline bitfld.byte 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 4. "MFF,Mode Fault Flag" "0: No mode fault error,1: Mode fault error" newline bitfld.byte 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 2. "MSS,Master Slave Select" "0: Transmission is through the TXDn pin and..,1: Reception is through the TXDn pin and.." newline bitfld.byte 0x0 1. "CTSE,CTS Enable" "0: CTS function is disabled (RTS output function is..,1: CTS function is enabled." bitfld.byte 0x0 0. "SSE,SSn Pin Function Enable" "0: SSn pin function is disabled.,1: SSn pin function is enabled." wgroup.word 0xE++0x1 line.word 0x0 "TDRHL,Transmit 9-bit Data Register" hexmask.word 0x0 0.--15. 1. "TDRHL,TDRHL is a 16-bit register that stores transmit data." rgroup.word 0x10++0x1 line.word 0x0 "RDRHL,Receive 9-bit Data Register" hexmask.word 0x0 0.--15. 1. "RDRHL,RDRHL is an 16-bit register that stores receive data." group.byte 0x12++0x1 line.byte 0x0 "MDDR,Modulation Duty Register" hexmask.byte 0x0 0.--7. 1. "MDDR,MDDR corrects the bit rate adjusted by the BRR register." line.byte 0x1 "DCCR,Data Compare Match Control Register" bitfld.byte 0x1 7. "DCME,Data Compare Match Enable(Valid only in asynchronous mode(including multi-processor)" "0: Address match function is disabled.,1: Address match function is enabled" bitfld.byte 0x1 6. "IDSEL,ID frame select(Valid only in asynchronous mode(including multi-processor)" "0: Always compare data regardless of the value of..,1: Compare data when the MPB bit is 1 (ID frame).." newline bitfld.byte 0x1 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x1 4. "DFER,Data Compare Match Framing Error Flag" "0: No framing error occurred,1: A framing error has occurred" newline bitfld.byte 0x1 3. "DPER,Data Compare Match Parity Error Flag" "0: No parity error occurred,1: A parity error has occurred" bitfld.byte 0x1 1.--2. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" newline bitfld.byte 0x1 0. "DCMF,Data Compare Match Flag" "0: No matched,1: Matched" group.word 0x1A++0x1 line.word 0x0 "CDR,Compare Match Data Register" hexmask.word.byte 0x0 9.--15. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." hexmask.word 0x0 0.--8. 1. "CMPD,Compare Match DataCompare data pattern for address match wake-up function" group.byte 0x1C++0x0 line.byte 0x0 "SPTR,Serial Port Register" hexmask.byte 0x0 3.--7. 1. "Reserved,These bits are read as 00000. The write value should be 00000." bitfld.byte 0x0 2. "SPB2IO,Serial port break I/O bit(It's selected whether the value of SPB2DT is output to TxD terminal.)" "0: The value of SPB2DT bit is not output in TXD pin.,1: The value of SPB2DT bit is output in TXD pin." newline bitfld.byte 0x0 1. "SPB2DT,Serial port break data select bit(The output level of TxD terminal is selected when SCR.TE = 0.)" "0: Low level is output on TXD pin,1: High level is output on TXD pin" rbitfld.byte 0x0 0. "RXDMON,Serial input data monitor bit(The state of the RXD terminal is shown.)" "0: RXD pin is low.,1: RXD pin is high." tree.end tree "SCI4" base ad:0x40070080 group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register (SCMR.SMIF = 0)" bitfld.byte 0x0 7. "CM,Communication Mode" "0: Asynchronous mode or simple I2C mode,1: Clock synchronous mode" bitfld.byte 0x0 6. "CHR,Character Length(Valid only in asynchronous mode)" "0: Transmit/receive in 9-bit data..,1: Transmit/receive in 9-bit data.." newline bitfld.byte 0x0 5. "PE,Parity Enable(Valid only in asynchronous mode)" "0: Parity bit addition is not performed..,1: The parity bit is added (transmitting) / The.." bitfld.byte 0x0 4. "PM,Parity Mode (Valid only when the PE bit is 1)" "0: Selects even parity,1: Selects odd parity" newline bitfld.byte 0x0 3. "STOP,Stop Bit Length(Valid only in asynchronous mode)" "0: 1 stop bit,1: 2 stop bits" bitfld.byte 0x0 2. "MP,Multi-Processor Mode(Valid only in asynchronous mode)" "0: Multi-processor communications function is..,1: Multi-processor communications function is enabled" newline bitfld.byte 0x0 0.--1. "CKS,Clock Select" "0: PCLK clock,1: PCLK/4 clock,?,?" group.byte 0x0++0x2 line.byte 0x0 "SMR_SMCI,Serial mode register (SCMR.SMIF = 1)" bitfld.byte 0x0 7. "GM,GSM Mode" "0: Normal mode operation,1: GSM mode operation" bitfld.byte 0x0 6. "BLK,Block Transfer Mode" "0: Normal mode operation,1: Block transfer mode operation" newline bitfld.byte 0x0 5. "PE,Parity Enable(Valid only in asynchronous mode)" "0: Setting Prohibited,1: Set this bit to 1 in smart card interface mode." bitfld.byte 0x0 4. "PM,Parity Mode (Valid only when the PE bit is 1)" "0: Selects even parity,1: Selects odd parity" newline bitfld.byte 0x0 2.--3. "BCP,Base Clock Pulse(Valid only in asynchronous mode)" "0: 93 clock cycles(S=93) (SCMR.BCP2=0) / 32 clock..,1: 128 clock cycles(S=128) (SCMR.BCP2=0) / 64 clock..,?,?" bitfld.byte 0x0 0.--1. "CKS,Clock Select" "0: PCLK clock,1: PCLK/4 clock,?,?" line.byte 0x1 "BRR,Bit Rate Register" hexmask.byte 0x1 0.--7. 1. "BRR,BRR is an 8-bit register that adjusts the bit rate." line.byte 0x2 "SCR,Serial Control Register (SCMR.SMIF = 0)" bitfld.byte 0x2 7. "TIE,Transmit Interrupt Enable" "0: SCI_TXI interrupt request is disabled,1: SCI_TXI interrupt request is enabled" bitfld.byte 0x2 6. "RIE,Receive Interrupt Enable" "0: SCI_RXI and SCI_ERI interrupt requests are..,1: SCI_RXI and SCI_ERI interrupt requests are enabled" newline bitfld.byte 0x2 5. "TE,Transmit Enable" "0: Serial transmission is disabled,1: Serial transmission is enabled" bitfld.byte 0x2 4. "RE,Receive Enable" "0: Serial reception is disabled,1: Serial reception is enabled" newline bitfld.byte 0x2 3. "MPIE,Multi-Processor Interrupt Enable(Valid in asynchronous mode when SMR.MP = 1)" "0: Normal reception,1: When the data with the multi-processor bit set.." bitfld.byte 0x2 2. "TEIE,Transmit End Interrupt Enable" "0: SCI_TEI interrupt request is disabled,1: SCI_TEI interrupt request is enabled" newline bitfld.byte 0x2 0.--1. "CKE,Clock Enable" "0: The clock with a frequency 16 times the bit rate..,1: The clock with the same frequency as the bit..,?,?" group.byte 0x2++0x2 line.byte 0x0 "SCR_SMCI,Serial Control Register (SCMR.SMIF =1)" bitfld.byte 0x0 7. "TIE,Transmit Interrupt Enable" "0: A SCI_TXI interrupt request is disabled,1: A SCI_TXI interrupt request is enabled" bitfld.byte 0x0 6. "RIE,Receive Interrupt Enable" "0: SCI_RXI and SCI_ERI interrupt requests are..,1: SCI_RXI and SCI_ERI interrupt requests are enabled" newline bitfld.byte 0x0 5. "TE,Transmit Enable" "0: Serial transmission is disabled,1: Serial transmission is enabled" bitfld.byte 0x0 4. "RE,Receive Enable" "0: Serial reception is disabled,1: Serial reception is enabled" newline bitfld.byte 0x0 3. "MPIE,Multi-Processor Interrupt Enable" "0,1" bitfld.byte 0x0 2. "TEIE,Transmit End Interrupt Enable" "0,1" newline bitfld.byte 0x0 0.--1. "CKE,Clock Enable" "0: Output disabled(SMR_SMCI.GM=0) / Output fixed..,1: Clock Output,?,?" line.byte 0x1 "TDR,Transmit Data Register" hexmask.byte 0x1 0.--7. 1. "TDR,TDR is an 8-bit register that stores transmit data." line.byte 0x2 "SSR,Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0)" bitfld.byte 0x2 7. "TDRE,Transmit Data Empty Flag" "0: Transmit data is in TDR register,1: No transmit data is in TDR register" bitfld.byte 0x2 6. "RDRF,Receive Data Full Flag" "0: No received data is in RDR register,1: Received data is in RDR register" newline bitfld.byte 0x2 5. "ORER,Overrun Error Flag" "0: No overrun error occurred,1: An overrun error has occurred" bitfld.byte 0x2 4. "FER,Framing Error Flag" "0: No framing error occurred,1: A framing error has occurred" newline bitfld.byte 0x2 3. "PER,Parity Error Flag" "0: No parity error occurred,1: A parity error has occurred" rbitfld.byte 0x2 2. "TEND,Transmit End Flag" "0: A character is being transmitted.,1: Character transfer has been completed." newline rbitfld.byte 0x2 1. "MPB,Multi-Processor" "0: Data transmission cycles,1: ID transmission cycles" bitfld.byte 0x2 0. "MPBT,Multi-Processor Bit Transfer" "0: Data transmission cycles,1: ID transmission cycles" group.byte 0x4++0x0 line.byte 0x0 "SSR_SMCI,Serial Status Register(SCMR.SMIF = 1)" bitfld.byte 0x0 7. "TDRE,Transmit Data Empty Flag" "0: Transmit data is in TDR register,1: No transmit data is in TDR register" bitfld.byte 0x0 6. "RDRF,Receive Data Full Flag" "0: No received data is in RDR register,1: Received data is in RDR register" newline bitfld.byte 0x0 5. "ORER,Overrun Error Flag" "0: No overrun error occurred,1: An overrun error has occurred" bitfld.byte 0x0 4. "ERS,Error Signal Status Flag" "0: Low error signal not responded,1: Low error signal responded" newline bitfld.byte 0x0 3. "PER,Parity Error Flag" "0: No parity error occurred,1: A parity error has occurred" rbitfld.byte 0x0 2. "TEND,Transmit End Flag" "0: A character is being transmitted.,1: Character transfer has been completed." newline rbitfld.byte 0x0 1. "MPB,Multi-ProcessorThis bit should be 0 in smart card interface mode." "0,1" bitfld.byte 0x0 0. "MPBT,Multi-Processor Bit TransferThis bit should be 0 in smart card interface mode." "0,1" rgroup.byte 0x5++0x0 line.byte 0x0 "RDR,Receive Data Register" hexmask.byte 0x0 0.--7. 1. "RDR,RDR is an 8-bit register that stores receive data." group.byte 0x6++0x5 line.byte 0x0 "SCMR,Smart Card Mode Register" bitfld.byte 0x0 7. "BCP2,Base Clock Pulse 2Selects the number of base clock cycles in combination with the SMR.BCP[1:0] bits" "0: S=93(SMR.BCP[1:0]=00) 128(SMR.BCP[1:0]=01)..,1: S=32(SMR.BCP[1:0]=00) 64(SMR.BCP[1:0]=01).." bitfld.byte 0x0 5.--6. "Reserved,These bits are read as 11. The write value should be 11." "0,1,2,3" newline bitfld.byte 0x0 4. "CHR1,Character Length 1(Only valid in asynchronous mode)" "0: Transmit/receive in 9-bit data length,1: Transmit/receive in 8-bit data length(SMR.CHR=0).." bitfld.byte 0x0 3. "SDIR,Transmitted/Received Data Transfer DirectionNOTE: The setting is invalid and a fixed data length of 8 bits is used in modes other than asynchronous mode.Set this bit to 1 if operation is to be in simple I2C mode." "0: Transfer with LSB first,1: Transfer with MSB first" newline bitfld.byte 0x0 2. "SINV,Transmitted/Received Data InvertSet this bit to 0 if operation is to be in simple I2C mode." "0: TDR contents are transmitted as they are.,1: TDR contents are inverted before being.." bitfld.byte 0x0 1. "Reserved,This bit is read as 1. The write value should be 1." "0,1" newline bitfld.byte 0x0 0. "SMIF,Smart Card Interface Mode Select" "0: Non-smart card interface mode(Asynchronous mode..,1: Smart card interface mode" line.byte 0x1 "SEMR,Serial Extended Mode Register" bitfld.byte 0x1 7. "RXDESEL,Asynchronous Start Bit Edge Detection Select(Valid only in asynchronous mode)" "0: The low level on the RXDn pin is detected as the..,1: A falling edge on the RXDn pin is detected as.." bitfld.byte 0x1 6. "BGDM,Baud Rate Generator Double-Speed Mode Select(Only valid the CKE[1] bit in SCR is 0 in asynchronous mode)." "0: Baud rate generator outputs the clock with..,1: Baud rate generator outputs the clock with.." newline bitfld.byte 0x1 5. "NFEN,Digital Noise Filter Function Enable(The NFEN bit should be 0 without simple I2C mode and asynchronous mode.)In asynchronous mode for RXDn input only. In simple I2C mode for RXDn/TxDn input." "0: Noise cancellation function for the RXDn/SSCLn..,1: Noise cancellation function for the RXDn/SSCLn.." bitfld.byte 0x1 4. "ABCS,Asynchronous Mode Base Clock Select(Valid only in asynchronous mode)" "0: Selects 16 base clock cycles for 1-bit period.,1: Selects 8 base clock cycles for 1-bit period." newline bitfld.byte 0x1 3. "ABCSE,Asynchronous Mode Extended Base Clock Select 1(Valid only in asynchronous mode and SCR.CKE[1]=0)" "0: Clock cycles for 1-bit period is decided with..,1: Baud rate is 6 base clock cycles for 1-bit.." bitfld.byte 0x1 2. "BRME,Bit Rate Modulation Enable" "0: Bit rate modulation function is disabled.,1: Bit rate modulation function is enabled." newline bitfld.byte 0x1 0.--1. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" line.byte 0x2 "SNFR,Noise Filter Setting Register" hexmask.byte 0x2 3.--7. 1. "Reserved,These bits are read as 00000. The write value should be 00000." bitfld.byte 0x2 0.--2. "NFCS,Noise Filter Clock Select" "0: Settings prohibited.,1: The clock signal divided by 1 is used with the..,?,?,?,?,?,?" line.byte 0x3 "SIMR1,I2C Mode Register 1" hexmask.byte 0x3 3.--7. 1. "IICDL,SDA Delay Output SelectCycles below are of the clock signal from the on-chip baud rate generator." bitfld.byte 0x3 1.--2. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" newline bitfld.byte 0x3 0. "IICM,Simple I2C Mode Select" "0: Asynchronous mode Multi-processor mode Clock..,1: Simple I2C mode(SCMR.SMIF=0) / Setting.." line.byte 0x4 "SIMR2,I2C Mode Register 2" bitfld.byte 0x4 6.--7. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.byte 0x4 5. "IICACKT,ACK Transmission Data" "0: ACK transmission,1: NACK transmission and reception of ACK/NACK" newline bitfld.byte 0x4 2.--4. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.byte 0x4 1. "IICCSC,Clock Synchronization" "0: No synchronization with the clock signal,1: Synchronization with the clock signal" newline bitfld.byte 0x4 0. "IICINTM,I2C Interrupt Mode Select" "0: Use ACK/NACK interrupts.,1: Use reception and transmission interrupts" line.byte 0x5 "SIMR3,I2C Mode Register 3" bitfld.byte 0x5 6.--7. "IICSCLS,SCL Output Select" "0: Serial clock output,1: Generate a start restart or stop condition.,?,?" bitfld.byte 0x5 4.--5. "IICSDAS,SDA Output Select" "0: Serial data output,1: Generate a start restart or stop condition.,?,?" newline bitfld.byte 0x5 3. "IICSTIF,Issuing of Start Restart or Stop Condition Completed Flag(When 0 is written to IICSTIF it is cleared to 0.)" "0: There are no requests for generating conditions..,1: A start restart or stop condition is completely.." bitfld.byte 0x5 2. "IICSTPREQ,Stop Condition Generation" "0: A stop condition is not generated.,1: A stop condition is generated." newline bitfld.byte 0x5 1. "IICRSTAREQ,Restart Condition Generation" "0: A restart condition is not generated.,1: A restart condition is generated." bitfld.byte 0x5 0. "IICSTAREQ,Start Condition Generation" "0: A start condition is not generated.,1: A start condition is generated." rgroup.byte 0xC++0x0 line.byte 0x0 "SISR,I2C Status Register" bitfld.byte 0x0 6.--7. "Reserved,These bits are read as 00." "0,1,2,3" bitfld.byte 0x0 5. "Reserved,This bit is read as 0." "0,1" newline bitfld.byte 0x0 4. "Reserved,This bit is read as 0." "0,1" bitfld.byte 0x0 3. "Reserved,This bit is read as 0." "0,1" newline bitfld.byte 0x0 2. "Reserved,This bit is read as 0." "0,1" bitfld.byte 0x0 1. "Reserved,This bit is read as 0." "0,1" newline bitfld.byte 0x0 0. "IICACKR,ACK Reception Data Flag" "0: ACK received,1: NACK received" group.byte 0xD++0x0 line.byte 0x0 "SPMR,SPI Mode Register" bitfld.byte 0x0 7. "CKPH,Clock Phase Select" "0: Clock is not delayed.,1: Clock is delayed." bitfld.byte 0x0 6. "CKPOL,Clock Polarity Select" "0: Clock polarity is not inverted.,1: Clock polarity is inverted" newline bitfld.byte 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 4. "MFF,Mode Fault Flag" "0: No mode fault error,1: Mode fault error" newline bitfld.byte 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 2. "MSS,Master Slave Select" "0: Transmission is through the TXDn pin and..,1: Reception is through the TXDn pin and.." newline bitfld.byte 0x0 1. "CTSE,CTS Enable" "0: CTS function is disabled (RTS output function is..,1: CTS function is enabled." bitfld.byte 0x0 0. "SSE,SSn Pin Function Enable" "0: SSn pin function is disabled.,1: SSn pin function is enabled." wgroup.word 0xE++0x1 line.word 0x0 "TDRHL,Transmit 9-bit Data Register" hexmask.word 0x0 0.--15. 1. "TDRHL,TDRHL is a 16-bit register that stores transmit data." rgroup.word 0x10++0x1 line.word 0x0 "RDRHL,Receive 9-bit Data Register" hexmask.word 0x0 0.--15. 1. "RDRHL,RDRHL is an 16-bit register that stores receive data." group.byte 0x12++0x1 line.byte 0x0 "MDDR,Modulation Duty Register" hexmask.byte 0x0 0.--7. 1. "MDDR,MDDR corrects the bit rate adjusted by the BRR register." line.byte 0x1 "DCCR,Data Compare Match Control Register" bitfld.byte 0x1 7. "DCME,Data Compare Match Enable(Valid only in asynchronous mode(including multi-processor)" "0: Address match function is disabled.,1: Address match function is enabled" bitfld.byte 0x1 6. "IDSEL,ID frame select(Valid only in asynchronous mode(including multi-processor)" "0: Always compare data regardless of the value of..,1: Compare data when the MPB bit is 1 (ID frame).." newline bitfld.byte 0x1 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x1 4. "DFER,Data Compare Match Framing Error Flag" "0: No framing error occurred,1: A framing error has occurred" newline bitfld.byte 0x1 3. "DPER,Data Compare Match Parity Error Flag" "0: No parity error occurred,1: A parity error has occurred" bitfld.byte 0x1 1.--2. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" newline bitfld.byte 0x1 0. "DCMF,Data Compare Match Flag" "0: No matched,1: Matched" group.word 0x1A++0x1 line.word 0x0 "CDR,Compare Match Data Register" hexmask.word.byte 0x0 9.--15. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." hexmask.word 0x0 0.--8. 1. "CMPD,Compare Match DataCompare data pattern for address match wake-up function" group.byte 0x1C++0x0 line.byte 0x0 "SPTR,Serial Port Register" hexmask.byte 0x0 3.--7. 1. "Reserved,These bits are read as 00000. The write value should be 00000." bitfld.byte 0x0 2. "SPB2IO,Serial port break I/O bit(It's selected whether the value of SPB2DT is output to TxD terminal.)" "0: The value of SPB2DT bit is not output in TXD pin.,1: The value of SPB2DT bit is output in TXD pin." newline bitfld.byte 0x0 1. "SPB2DT,Serial port break data select bit(The output level of TxD terminal is selected when SCR.TE = 0.)" "0: Low level is output on TXD pin,1: High level is output on TXD pin" rbitfld.byte 0x0 0. "RXDMON,Serial input data monitor bit(The state of the RXD terminal is shown.)" "0: RXD pin is low.,1: RXD pin is high." tree.end tree "SCI9" base ad:0x40070120 group.byte 0x0++0x0 line.byte 0x0 "SMR,Serial Mode Register (SCMR.SMIF = 0)" bitfld.byte 0x0 7. "CM,Communication Mode" "0: Asynchronous mode or simple I2C mode,1: Clock synchronous mode" bitfld.byte 0x0 6. "CHR,Character Length(Valid only in asynchronous mode)" "0: Transmit/receive in 9-bit data..,1: Transmit/receive in 9-bit data.." newline bitfld.byte 0x0 5. "PE,Parity Enable(Valid only in asynchronous mode)" "0: Parity bit addition is not performed..,1: The parity bit is added (transmitting) / The.." bitfld.byte 0x0 4. "PM,Parity Mode (Valid only when the PE bit is 1)" "0: Selects even parity,1: Selects odd parity" newline bitfld.byte 0x0 3. "STOP,Stop Bit Length(Valid only in asynchronous mode)" "0: 1 stop bit,1: 2 stop bits" bitfld.byte 0x0 2. "MP,Multi-Processor Mode(Valid only in asynchronous mode)" "0: Multi-processor communications function is..,1: Multi-processor communications function is enabled" newline bitfld.byte 0x0 0.--1. "CKS,Clock Select" "0: PCLK clock,1: PCLK/4 clock,?,?" group.byte 0x0++0x2 line.byte 0x0 "SMR_SMCI,Serial mode register (SCMR.SMIF = 1)" bitfld.byte 0x0 7. "GM,GSM Mode" "0: Normal mode operation,1: GSM mode operation" bitfld.byte 0x0 6. "BLK,Block Transfer Mode" "0: Normal mode operation,1: Block transfer mode operation" newline bitfld.byte 0x0 5. "PE,Parity Enable(Valid only in asynchronous mode)" "0: Setting Prohibited,1: Set this bit to 1 in smart card interface mode." bitfld.byte 0x0 4. "PM,Parity Mode (Valid only when the PE bit is 1)" "0: Selects even parity,1: Selects odd parity" newline bitfld.byte 0x0 2.--3. "BCP,Base Clock Pulse(Valid only in asynchronous mode)" "0: 93 clock cycles(S=93) (SCMR.BCP2=0) / 32 clock..,1: 128 clock cycles(S=128) (SCMR.BCP2=0) / 64 clock..,?,?" bitfld.byte 0x0 0.--1. "CKS,Clock Select" "0: PCLK clock,1: PCLK/4 clock,?,?" line.byte 0x1 "BRR,Bit Rate Register" hexmask.byte 0x1 0.--7. 1. "BRR,BRR is an 8-bit register that adjusts the bit rate." line.byte 0x2 "SCR,Serial Control Register (SCMR.SMIF = 0)" bitfld.byte 0x2 7. "TIE,Transmit Interrupt Enable" "0: SCI_TXI interrupt request is disabled,1: SCI_TXI interrupt request is enabled" bitfld.byte 0x2 6. "RIE,Receive Interrupt Enable" "0: SCI_RXI and SCI_ERI interrupt requests are..,1: SCI_RXI and SCI_ERI interrupt requests are enabled" newline bitfld.byte 0x2 5. "TE,Transmit Enable" "0: Serial transmission is disabled,1: Serial transmission is enabled" bitfld.byte 0x2 4. "RE,Receive Enable" "0: Serial reception is disabled,1: Serial reception is enabled" newline bitfld.byte 0x2 3. "MPIE,Multi-Processor Interrupt Enable(Valid in asynchronous mode when SMR.MP = 1)" "0: Normal reception,1: When the data with the multi-processor bit set.." bitfld.byte 0x2 2. "TEIE,Transmit End Interrupt Enable" "0: SCI_TEI interrupt request is disabled,1: SCI_TEI interrupt request is enabled" newline bitfld.byte 0x2 0.--1. "CKE,Clock Enable" "0: The clock with a frequency 16 times the bit rate..,1: The clock with the same frequency as the bit..,?,?" group.byte 0x2++0x2 line.byte 0x0 "SCR_SMCI,Serial Control Register (SCMR.SMIF =1)" bitfld.byte 0x0 7. "TIE,Transmit Interrupt Enable" "0: A SCI_TXI interrupt request is disabled,1: A SCI_TXI interrupt request is enabled" bitfld.byte 0x0 6. "RIE,Receive Interrupt Enable" "0: SCI_RXI and SCI_ERI interrupt requests are..,1: SCI_RXI and SCI_ERI interrupt requests are enabled" newline bitfld.byte 0x0 5. "TE,Transmit Enable" "0: Serial transmission is disabled,1: Serial transmission is enabled" bitfld.byte 0x0 4. "RE,Receive Enable" "0: Serial reception is disabled,1: Serial reception is enabled" newline bitfld.byte 0x0 3. "MPIE,Multi-Processor Interrupt Enable" "0,1" bitfld.byte 0x0 2. "TEIE,Transmit End Interrupt Enable" "0,1" newline bitfld.byte 0x0 0.--1. "CKE,Clock Enable" "0: Output disabled(SMR_SMCI.GM=0) / Output fixed..,1: Clock Output,?,?" line.byte 0x1 "TDR,Transmit Data Register" hexmask.byte 0x1 0.--7. 1. "TDR,TDR is an 8-bit register that stores transmit data." line.byte 0x2 "SSR,Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0)" bitfld.byte 0x2 7. "TDRE,Transmit Data Empty Flag" "0: Transmit data is in TDR register,1: No transmit data is in TDR register" bitfld.byte 0x2 6. "RDRF,Receive Data Full Flag" "0: No received data is in RDR register,1: Received data is in RDR register" newline bitfld.byte 0x2 5. "ORER,Overrun Error Flag" "0: No overrun error occurred,1: An overrun error has occurred" bitfld.byte 0x2 4. "FER,Framing Error Flag" "0: No framing error occurred,1: A framing error has occurred" newline bitfld.byte 0x2 3. "PER,Parity Error Flag" "0: No parity error occurred,1: A parity error has occurred" rbitfld.byte 0x2 2. "TEND,Transmit End Flag" "0: A character is being transmitted.,1: Character transfer has been completed." newline rbitfld.byte 0x2 1. "MPB,Multi-Processor" "0: Data transmission cycles,1: ID transmission cycles" bitfld.byte 0x2 0. "MPBT,Multi-Processor Bit Transfer" "0: Data transmission cycles,1: ID transmission cycles" group.byte 0x4++0x0 line.byte 0x0 "SSR_SMCI,Serial Status Register(SCMR.SMIF = 1)" bitfld.byte 0x0 7. "TDRE,Transmit Data Empty Flag" "0: Transmit data is in TDR register,1: No transmit data is in TDR register" bitfld.byte 0x0 6. "RDRF,Receive Data Full Flag" "0: No received data is in RDR register,1: Received data is in RDR register" newline bitfld.byte 0x0 5. "ORER,Overrun Error Flag" "0: No overrun error occurred,1: An overrun error has occurred" bitfld.byte 0x0 4. "ERS,Error Signal Status Flag" "0: Low error signal not responded,1: Low error signal responded" newline bitfld.byte 0x0 3. "PER,Parity Error Flag" "0: No parity error occurred,1: A parity error has occurred" rbitfld.byte 0x0 2. "TEND,Transmit End Flag" "0: A character is being transmitted.,1: Character transfer has been completed." newline rbitfld.byte 0x0 1. "MPB,Multi-ProcessorThis bit should be 0 in smart card interface mode." "0,1" bitfld.byte 0x0 0. "MPBT,Multi-Processor Bit TransferThis bit should be 0 in smart card interface mode." "0,1" rgroup.byte 0x5++0x0 line.byte 0x0 "RDR,Receive Data Register" hexmask.byte 0x0 0.--7. 1. "RDR,RDR is an 8-bit register that stores receive data." group.byte 0x6++0x5 line.byte 0x0 "SCMR,Smart Card Mode Register" bitfld.byte 0x0 7. "BCP2,Base Clock Pulse 2Selects the number of base clock cycles in combination with the SMR.BCP[1:0] bits" "0: S=93(SMR.BCP[1:0]=00) 128(SMR.BCP[1:0]=01)..,1: S=32(SMR.BCP[1:0]=00) 64(SMR.BCP[1:0]=01).." bitfld.byte 0x0 5.--6. "Reserved,These bits are read as 11. The write value should be 11." "0,1,2,3" newline bitfld.byte 0x0 4. "CHR1,Character Length 1(Only valid in asynchronous mode)" "0: Transmit/receive in 9-bit data length,1: Transmit/receive in 8-bit data length(SMR.CHR=0).." bitfld.byte 0x0 3. "SDIR,Transmitted/Received Data Transfer DirectionNOTE: The setting is invalid and a fixed data length of 8 bits is used in modes other than asynchronous mode.Set this bit to 1 if operation is to be in simple I2C mode." "0: Transfer with LSB first,1: Transfer with MSB first" newline bitfld.byte 0x0 2. "SINV,Transmitted/Received Data InvertSet this bit to 0 if operation is to be in simple I2C mode." "0: TDR contents are transmitted as they are.,1: TDR contents are inverted before being.." bitfld.byte 0x0 1. "Reserved,This bit is read as 1. The write value should be 1." "0,1" newline bitfld.byte 0x0 0. "SMIF,Smart Card Interface Mode Select" "0: Non-smart card interface mode(Asynchronous mode..,1: Smart card interface mode" line.byte 0x1 "SEMR,Serial Extended Mode Register" bitfld.byte 0x1 7. "RXDESEL,Asynchronous Start Bit Edge Detection Select(Valid only in asynchronous mode)" "0: The low level on the RXDn pin is detected as the..,1: A falling edge on the RXDn pin is detected as.." bitfld.byte 0x1 6. "BGDM,Baud Rate Generator Double-Speed Mode Select(Only valid the CKE[1] bit in SCR is 0 in asynchronous mode)." "0: Baud rate generator outputs the clock with..,1: Baud rate generator outputs the clock with.." newline bitfld.byte 0x1 5. "NFEN,Digital Noise Filter Function Enable(The NFEN bit should be 0 without simple I2C mode and asynchronous mode.)In asynchronous mode for RXDn input only. In simple I2C mode for RXDn/TxDn input." "0: Noise cancellation function for the RXDn/SSCLn..,1: Noise cancellation function for the RXDn/SSCLn.." bitfld.byte 0x1 4. "ABCS,Asynchronous Mode Base Clock Select(Valid only in asynchronous mode)" "0: Selects 16 base clock cycles for 1-bit period.,1: Selects 8 base clock cycles for 1-bit period." newline bitfld.byte 0x1 3. "ABCSE,Asynchronous Mode Extended Base Clock Select 1(Valid only in asynchronous mode and SCR.CKE[1]=0)" "0: Clock cycles for 1-bit period is decided with..,1: Baud rate is 6 base clock cycles for 1-bit.." bitfld.byte 0x1 2. "BRME,Bit Rate Modulation Enable" "0: Bit rate modulation function is disabled.,1: Bit rate modulation function is enabled." newline bitfld.byte 0x1 0.--1. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" line.byte 0x2 "SNFR,Noise Filter Setting Register" hexmask.byte 0x2 3.--7. 1. "Reserved,These bits are read as 00000. The write value should be 00000." bitfld.byte 0x2 0.--2. "NFCS,Noise Filter Clock Select" "0: Settings prohibited.,1: The clock signal divided by 1 is used with the..,?,?,?,?,?,?" line.byte 0x3 "SIMR1,I2C Mode Register 1" hexmask.byte 0x3 3.--7. 1. "IICDL,SDA Delay Output SelectCycles below are of the clock signal from the on-chip baud rate generator." bitfld.byte 0x3 1.--2. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" newline bitfld.byte 0x3 0. "IICM,Simple I2C Mode Select" "0: Asynchronous mode Multi-processor mode Clock..,1: Simple I2C mode(SCMR.SMIF=0) / Setting.." line.byte 0x4 "SIMR2,I2C Mode Register 2" bitfld.byte 0x4 6.--7. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.byte 0x4 5. "IICACKT,ACK Transmission Data" "0: ACK transmission,1: NACK transmission and reception of ACK/NACK" newline bitfld.byte 0x4 2.--4. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.byte 0x4 1. "IICCSC,Clock Synchronization" "0: No synchronization with the clock signal,1: Synchronization with the clock signal" newline bitfld.byte 0x4 0. "IICINTM,I2C Interrupt Mode Select" "0: Use ACK/NACK interrupts.,1: Use reception and transmission interrupts" line.byte 0x5 "SIMR3,I2C Mode Register 3" bitfld.byte 0x5 6.--7. "IICSCLS,SCL Output Select" "0: Serial clock output,1: Generate a start restart or stop condition.,?,?" bitfld.byte 0x5 4.--5. "IICSDAS,SDA Output Select" "0: Serial data output,1: Generate a start restart or stop condition.,?,?" newline bitfld.byte 0x5 3. "IICSTIF,Issuing of Start Restart or Stop Condition Completed Flag(When 0 is written to IICSTIF it is cleared to 0.)" "0: There are no requests for generating conditions..,1: A start restart or stop condition is completely.." bitfld.byte 0x5 2. "IICSTPREQ,Stop Condition Generation" "0: A stop condition is not generated.,1: A stop condition is generated." newline bitfld.byte 0x5 1. "IICRSTAREQ,Restart Condition Generation" "0: A restart condition is not generated.,1: A restart condition is generated." bitfld.byte 0x5 0. "IICSTAREQ,Start Condition Generation" "0: A start condition is not generated.,1: A start condition is generated." rgroup.byte 0xC++0x0 line.byte 0x0 "SISR,I2C Status Register" bitfld.byte 0x0 6.--7. "Reserved,These bits are read as 00." "0,1,2,3" bitfld.byte 0x0 5. "Reserved,This bit is read as 0." "0,1" newline bitfld.byte 0x0 4. "Reserved,This bit is read as 0." "0,1" bitfld.byte 0x0 3. "Reserved,This bit is read as 0." "0,1" newline bitfld.byte 0x0 2. "Reserved,This bit is read as 0." "0,1" bitfld.byte 0x0 1. "Reserved,This bit is read as 0." "0,1" newline bitfld.byte 0x0 0. "IICACKR,ACK Reception Data Flag" "0: ACK received,1: NACK received" group.byte 0xD++0x0 line.byte 0x0 "SPMR,SPI Mode Register" bitfld.byte 0x0 7. "CKPH,Clock Phase Select" "0: Clock is not delayed.,1: Clock is delayed." bitfld.byte 0x0 6. "CKPOL,Clock Polarity Select" "0: Clock polarity is not inverted.,1: Clock polarity is inverted" newline bitfld.byte 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 4. "MFF,Mode Fault Flag" "0: No mode fault error,1: Mode fault error" newline bitfld.byte 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 2. "MSS,Master Slave Select" "0: Transmission is through the TXDn pin and..,1: Reception is through the TXDn pin and.." newline bitfld.byte 0x0 1. "CTSE,CTS Enable" "0: CTS function is disabled (RTS output function is..,1: CTS function is enabled." bitfld.byte 0x0 0. "SSE,SSn Pin Function Enable" "0: SSn pin function is disabled.,1: SSn pin function is enabled." wgroup.word 0xE++0x1 line.word 0x0 "TDRHL,Transmit 9-bit Data Register" hexmask.word 0x0 0.--15. 1. "TDRHL,TDRHL is a 16-bit register that stores transmit data." rgroup.word 0x10++0x1 line.word 0x0 "RDRHL,Receive 9-bit Data Register" hexmask.word 0x0 0.--15. 1. "RDRHL,RDRHL is an 16-bit register that stores receive data." group.byte 0x12++0x1 line.byte 0x0 "MDDR,Modulation Duty Register" hexmask.byte 0x0 0.--7. 1. "MDDR,MDDR corrects the bit rate adjusted by the BRR register." line.byte 0x1 "DCCR,Data Compare Match Control Register" bitfld.byte 0x1 7. "DCME,Data Compare Match Enable(Valid only in asynchronous mode(including multi-processor)" "0: Address match function is disabled.,1: Address match function is enabled" bitfld.byte 0x1 6. "IDSEL,ID frame select(Valid only in asynchronous mode(including multi-processor)" "0: Always compare data regardless of the value of..,1: Compare data when the MPB bit is 1 (ID frame).." newline bitfld.byte 0x1 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x1 4. "DFER,Data Compare Match Framing Error Flag" "0: No framing error occurred,1: A framing error has occurred" newline bitfld.byte 0x1 3. "DPER,Data Compare Match Parity Error Flag" "0: No parity error occurred,1: A parity error has occurred" bitfld.byte 0x1 1.--2. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" newline bitfld.byte 0x1 0. "DCMF,Data Compare Match Flag" "0: No matched,1: Matched" group.word 0x1A++0x1 line.word 0x0 "CDR,Compare Match Data Register" hexmask.word.byte 0x0 9.--15. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." hexmask.word 0x0 0.--8. 1. "CMPD,Compare Match DataCompare data pattern for address match wake-up function" group.byte 0x1C++0x0 line.byte 0x0 "SPTR,Serial Port Register" hexmask.byte 0x0 3.--7. 1. "Reserved,These bits are read as 00000. The write value should be 00000." bitfld.byte 0x0 2. "SPB2IO,Serial port break I/O bit(It's selected whether the value of SPB2DT is output to TxD terminal.)" "0: The value of SPB2DT bit is not output in TXD pin.,1: The value of SPB2DT bit is output in TXD pin." newline bitfld.byte 0x0 1. "SPB2DT,Serial port break data select bit(The output level of TxD terminal is selected when SCR.TE = 0.)" "0: Low level is output on TXD pin,1: High level is output on TXD pin" rbitfld.byte 0x0 0. "RXDMON,Serial input data monitor bit(The state of the RXD terminal is shown.)" "0: RXD pin is low.,1: RXD pin is high." tree.end tree.end tree "SLCDC (Segment LCD Controller)" base ad:0x40082000 group.byte 0x0++0x3 line.byte 0x0 "LCDM0,LCD Mode Register 0" bitfld.byte 0x0 6.--7. "MDSET,LCD drive voltage generator selection" "0: External resistance division method,1: Internal voltage boosting method,?,?" bitfld.byte 0x0 5. "LWAVE,LCD display waveform selection" "0: Waveform A,1: Waveform B" newline bitfld.byte 0x0 2.--4. "LDTY,Time Slice of LCD Display Select" "0: Setting prohibited,1: 2-time slice,?,?,?,?,?,?" bitfld.byte 0x0 0.--1. "LBAS,LCD Display Bias Method Select" "0: 1/2 bias method,1: 1/3 bias method,?,?" line.byte 0x1 "LCDM1,LCD Mode Register 1" bitfld.byte 0x1 7. "LCDON,LCD Display Enable/Disable" "0: Output ground level to segment/common..,1: Output ground level to segment/common.." bitfld.byte 0x1 6. "SCOC,LCD Display Enable/Disable" "0: Output ground level to segment/common..,1: Display off (all segment outputs are.." newline bitfld.byte 0x1 5. "VLCON,Voltage boost circuit or capacitor split circuit operation enable/disable" "0: Stops voltage boost circuit or capacitor split..,1: Enables voltage boost circuit or capacitor split.." bitfld.byte 0x1 4. "BLON,Display data area control" "0: Displaying an A-pattern area data (lower four..,1: Alternately displaying A-pattern and B-pattern.." newline bitfld.byte 0x1 3. "LCDSEL,Display data area control" "0: Displaying an A-pattern area data (lower four..,1: Displaying a B-pattern area data (higher four.." bitfld.byte 0x1 1.--2. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" newline bitfld.byte 0x1 0. "LCDVLM,Voltage Boosting Pin Initial Value Switching Control" "0: Set when VDD >= 2.7 V,1: Set when VDD <= 4.2 V" line.byte 0x2 "LCDC0,LCD Clock Control Register 0" hexmask.byte 0x2 0.--5. 1. "LCDC,LCD clock (LCDCL)" line.byte 0x3 "VLCD,LCD Boost Level Control Register" hexmask.byte 0x3 0.--4. 1. "VLCD,Reference Voltage(Contrast Adjustment) Select" repeat 54. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2+0x100)++0x0 line.byte 0x0 "SEG$1,LCD Display Data Register %s" hexmask.byte 0x0 0.--7. 1. "SEG,LCD Display Data" repeat.end tree.end tree "SMPU (Bus Slave MPU)" base ad:0x40000C00 group.word 0x0++0x1 line.word 0x0 "SMPUCTL,Slave MPU Control Register" hexmask.word.byte 0x0 8.--15. 1. "KEY,Key Code This bit is used to enable or disable rewriting of the PROTECT and OAD bit." hexmask.word.byte 0x0 3.--7. 1. "Reserved,These bits are read as 00000. The write value should be 00000." newline bitfld.word 0x0 1.--2. "PROTECT,Protection of register Protected register SMPUMBIU SMPUFBIU SMPUSRAM0 SMPUP0BIU SMPUP2BIU SMPUP6BIU SMPUEXBIU SMPUEXBIU2" "0: All Bus Slave register writing is possible.,1: All Bus Slave register writing is protected.,?,?" bitfld.word 0x0 0. "OAD,Master Group enable" "0: Non-maskable interrupt.,1: Internal reset." group.word 0x10++0x1 line.word 0x0 "SMPUMBIU,Access Control Register for MBIU" hexmask.word 0x0 4.--15. 1. "Reserved,These bits are read as 000000000000. The write value should be 000000000000." bitfld.word 0x0 3. "WPGRPA,Master Group A Write protection" "0: Master group A write of memory protection..,1: Master group A write of memory protection enabled." newline bitfld.word 0x0 2. "RPGRPA,Master Group A Read protection" "0: Master group A read of memory protection disabled.,1: Master group A read of memory protection enabled." bitfld.word 0x0 0.--1. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" group.word 0x14++0x1 line.word 0x0 "SMPUFBIU,Access Control Register for FBIU" hexmask.word 0x0 4.--15. 1. "Reserved,These bits are read as 000000000000. The write value should be 000000000000." bitfld.word 0x0 3. "WPGRPA,Master Group A Write protection" "0: Master group A write of memory protection..,1: Master group A write of memory protection enabled." newline bitfld.word 0x0 2. "RPGRPA,Master Group A Read protection" "0: Master group A read of memory protection disabled.,1: Master group A read of memory protection enabled." bitfld.word 0x0 1. "WPCPU,CPU Write protection" "0: CPU write of memory protection disabled.,1: CPU write of memory protection enabled." newline bitfld.word 0x0 0. "RPCPU,CPU Read protection" "0: CPU read of memory protection disabled.,1: CPU read of memory protection enabled." group.word 0x18++0x1 line.word 0x0 "SMPUSRAM0,Access Control Register for SRAM0" hexmask.word 0x0 4.--15. 1. "Reserved,These bits are read as 000000000000. The write value should be 000000000000." bitfld.word 0x0 3. "WPGRPA,Master Group A Write protection" "0: Master group A write of memory protection..,1: Master group A write of memory protection enabled." newline bitfld.word 0x0 2. "RPGRPA,Master Group A Read protection" "0: Master group A read of memory protection disabled.,1: Master group A read of memory protection enabled." bitfld.word 0x0 1. "WPCPU,CPU Write protection" "0: CPU write of memory protection disabled.,1: CPU write of memory protection enabled." newline bitfld.word 0x0 0. "RPCPU,CPU Read protection" "0: CPU read of memory protection disabled.,1: CPU read of memory protection enabled." repeat 3. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x20)++0x1 line.word 0x0 "SMPUP$1BIU,Access Control Register for P%sBIU" hexmask.word 0x0 4.--15. 1. "Reserved,These bits are read as 000000000000. The write value should be 000000000000." bitfld.word 0x0 3. "WPGRPA,Master Group A Write protection" "0: Master group A write of memory protection..,1: Master group A write of memory protection enabled." newline bitfld.word 0x0 2. "RPGRPA,Master Group A Read protection" "0: Master group A read of memory protection disabled.,1: Master group A read of memory protection enabled." bitfld.word 0x0 1. "WPCPU,CPU Write protection" "0: CPU write of memory protection disabled.,1: CPU write of memory protection enabled." newline bitfld.word 0x0 0. "RPCPU,CPU Read protection" "0: CPU read of memory protection disabled.,1: CPU read of memory protection enabled." repeat.end group.word 0x30++0x1 line.word 0x0 "SMPUEXBIU,Access Control Register for EXBIU" hexmask.word 0x0 4.--15. 1. "Reserved,These bits are read as 000000000000. The write value should be 000000000000." bitfld.word 0x0 3. "WPGRPA,Master Group A Write protection" "0: Master group A write of memory protection..,1: Master group A write of memory protection enabled." newline bitfld.word 0x0 2. "RPGRPA,Master Group A Read protection" "0: Master group A read of memory protection disabled.,1: Master group A read of memory protection enabled." bitfld.word 0x0 1. "WPCPU,CPU Write protection" "0: CPU write of memory protection disabled.,1: CPU write of memory protection enabled." newline bitfld.word 0x0 0. "RPCPU,CPU Read protection" "0: CPU read of memory protection disabled.,1: CPU read of memory protection enabled." group.word 0x34++0x1 line.word 0x0 "SMPUEXBIU2,Access Control Register for EXBIU2" hexmask.word 0x0 4.--15. 1. "Reserved,These bits are read as 000000000000. The write value should be 000000000000." bitfld.word 0x0 3. "WPGRPA,Master Group A Write protection" "0: Master group A write of memory protection..,1: Master group A write of memory protection enabled." newline bitfld.word 0x0 2. "RPGRPA,Master Group A Read protection" "0: Master group A read of memory protection disabled.,1: Master group A read of memory protection enabled." bitfld.word 0x0 1. "WPCPU,CPU Write protection" "0: CPU write of memory protection disabled.,1: CPU write of memory protection enabled." newline bitfld.word 0x0 0. "RPCPU,CPU Read protection" "0: CPU read of memory protection disabled.,1: CPU read of memory protection enabled." tree.end tree "SPI (Serial Peripheral Interface)" base ad:0x0 tree "SPI0" base ad:0x40072000 group.byte 0x0++0x3 line.byte 0x0 "SPCR,SPI Control Register" bitfld.byte 0x0 7. "SPRIE,SPI Receive Buffer Full Interrupt Enable" "0: Disables the generation of SPI receive buffer..,1: Enables the generation of SPI receive buffer.." bitfld.byte 0x0 6. "SPE,SPI Function Enable" "0: Disables the SPI function,1: Enables the SPI function" newline bitfld.byte 0x0 5. "SPTIE,Transmit Buffer Empty Interrupt Enable" "0: Disables the generation of transmit buffer empty..,1: Enables the generation of transmit buffer empty.." bitfld.byte 0x0 4. "SPEIE,SPI Error Interrupt Enable" "0: Disables the generation of SPI error interrupt..,1: Enables the generation of SPI error interrupt.." newline bitfld.byte 0x0 3. "MSTR,SPI Master/Slave Mode Select" "0: Slave mode,1: Master mode" bitfld.byte 0x0 2. "MODFEN,Mode Fault Error Detection Enable" "0: Disables the detection of mode fault error,1: Enables the detection of mode fault error" newline bitfld.byte 0x0 1. "TXMD,Communications Operating Mode Select" "0: Full-duplex synchronous serial communications,1: Serial communications consisting of only.." bitfld.byte 0x0 0. "SPMS,SPI Mode Select" "0: SPI operation (4-wire method),1: Clock synchronous operation (3-wire method)" line.byte 0x1 "SSLP,SPI Slave Select Polarity Register" hexmask.byte 0x1 4.--7. 1. "Reserved,These bits are read as 0000. The write value should be 0000." bitfld.byte 0x1 3. "SSL3P,SSL3 Signal Polarity Setting" "0: SSL3 signal is active low,1: SSL3 signal is active high" newline bitfld.byte 0x1 2. "SSL2P,SSL2 Signal Polarity Setting" "0: SSL2 signal is active low,1: SSL2 signal is active high" bitfld.byte 0x1 1. "SSL1P,SSL1 Signal Polarity Setting" "0: SSL1 signal is active low,1: SSL1 signal is active high" newline bitfld.byte 0x1 0. "SSL0P,SSL0 Signal Polarity Setting" "0: SSL0 signal is active low,1: SSL0 signal is active high" line.byte 0x2 "SPPCR,SPI Pin Control Register" bitfld.byte 0x2 6.--7. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.byte 0x2 5. "MOIFE,MOSI Idle Value Fixing Enable" "0: MOSI output value equals final data from..,1: MOSI output value equals the value set in the.." newline bitfld.byte 0x2 4. "MOIFV,MOSI Idle Fixed Value" "0: The level output on the MOSIn pin during MOSI..,1: The level output on the MOSIn pin during MOSI.." bitfld.byte 0x2 2.--3. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" newline bitfld.byte 0x2 1. "SPLP2,RSPI Loopback 2" "0: Normal mode,1: Loopback mode (data is not inverted for.." bitfld.byte 0x2 0. "SPLP,RSPI Loopback" "0: Normal mode,1: Loopback mode (data is inverted for transmission)" line.byte 0x3 "SPSR,SPI Status Register" bitfld.byte 0x3 7. "SPRF,SPI Receive Buffer Full Flag" "0: No valid data in SPDR,1: Valid data found in SPDR" bitfld.byte 0x3 6. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.byte 0x3 5. "SPTEF,SPI Transmit Buffer Empty Flag" "0: Data found in the transmit buffer,1: No data in the transmit buffer" bitfld.byte 0x3 4. "UDRF,Underrun Error Flag(When MODF is 0 This bit is invalid.)" "0: A mode fault error occurs (MODF=1),1: An underrun error occurs (MODF=1)" newline bitfld.byte 0x3 3. "PERF,Parity Error Flag" "0: No parity error occurs,1: A parity error occurs" bitfld.byte 0x3 2. "MODF,Mode Fault Error Flag" "0: Neither mode fault error nor underrun error occurs,1: A mode fault error or an underrun error occurs." newline rbitfld.byte 0x3 1. "IDLNF,SPI Idle Flag" "0: SPI is in the idle state,1: SPI is in the transfer state" bitfld.byte 0x3 0. "OVRF,Overrun Error Flag" "0: No overrun error occurs,1: An overrun error occurs" group.long 0x4++0x3 line.long 0x0 "SPDR,SPI Data Register" hexmask.long 0x0 0.--31. 1. "SPDR,SPDR is the interface with the buffers that hold data for transmission and reception by the RSPI.When accessing in word (SPDCR.SPLW=1) access SPDR." group.word 0x4++0x1 line.word 0x0 "SPDR_HA,SPI Data Register ( halfword access )" hexmask.word 0x0 0.--15. 1. "SPDR_HA,SPDR is the interface with the buffers that hold data for transmission and reception by the RSPI.When accessing in halfword (SPDCR.SPLW=0) access SPDR_HA." group.byte 0x8++0x0 line.byte 0x0 "SPSCR,SPI Sequence Control Register" hexmask.byte 0x0 3.--7. 1. "Reserved,These bits are read as 00000. The write value should be 00000." bitfld.byte 0x0 0.--2. "SPSLN,RSPI Sequence Length SpecificationThe order in which the SPCMD0 to SPCMD07 registers are to be referenced is changed in accordance with the sequence length that is set in these bits. The relationship among the setting of these bits sequence.." "0: Length 1 SPDMDx x = 0->0->...,1: Length 2 SPDMDx x = 0->1->0->...,?,?,?,?,?,?" rgroup.byte 0x9++0x0 line.byte 0x0 "SPSSR,SPI Sequence Status Register" bitfld.byte 0x0 7. "Reserved,This bit is read as 0." "0,1" bitfld.byte 0x0 4.--6. "SPECM,SPI Error Command" "0: SPCMD0,1: SPCMD1,?,?,?,?,?,?" newline bitfld.byte 0x0 3. "Reserved,This bit is read as 0." "0,1" bitfld.byte 0x0 0.--2. "SPCP,SPI Command Pointer" "0: SPCMD0,1: SPCMD1,?,?,?,?,?,?" group.byte 0xA++0x5 line.byte 0x0 "SPBR,SPI Bit Rate Register" hexmask.byte 0x0 0.--7. 1. "SPR,SPBR sets the bit rate in master mode." line.byte 0x1 "SPDCR,SPI Data Control Register" bitfld.byte 0x1 6.--7. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.byte 0x1 5. "SPLW,SPI Word Access/Halfword Access Specification" "0: SPDR_HA is valid to access in halfwords,1: SPDR is valid (to access in words)." newline bitfld.byte 0x1 4. "SPRDTD,RSPI Receive/Transmit Data Selection" "0: SPDR values are read from the receive buffer,1: SPDR values are read from the transmit buffer.." bitfld.byte 0x1 2.--3. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" newline bitfld.byte 0x1 0.--1. "SPFC,Number of Frames Specification" "0: 1 frame,1: 2 frames,?,?" line.byte 0x2 "SPCKD,SPI Clock Delay Register" hexmask.byte 0x2 3.--7. 1. "Reserved,These bits are read as 00000. The write value should be 00000." bitfld.byte 0x2 0.--2. "SCKDL,RSPCK Delay Setting" "0: 1 RSPCK,1: 2 RSPCK,?,?,?,?,?,?" line.byte 0x3 "SSLND,SPI Slave Select Negation Delay Register" hexmask.byte 0x3 3.--7. 1. "Reserved,These bits are read as 00000. The write value should be 00000." bitfld.byte 0x3 0.--2. "SLNDL,SSL Negation Delay Setting" "0: 1 RSPCK,1: 2 RSPCK,?,?,?,?,?,?" line.byte 0x4 "SPND,SPI Next-Access Delay Register" hexmask.byte 0x4 3.--7. 1. "Reserved,These bits are read as 00000. The write value should be 00000." bitfld.byte 0x4 0.--2. "SPNDL,SPI Next-Access Delay Setting" "0: 1 RSPCK + 2 PCLK,1: 2 RSPCK + 2 PCLK,?,?,?,?,?,?" line.byte 0x5 "SPCR2,SPI Control Register 2" bitfld.byte 0x5 5.--7. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.byte 0x5 4. "SCKASE,RSPCK Auto-Stop Function Enable" "0: Disables the RSPCK auto-stop function,1: Enables the RSPCK auto-stop function" newline bitfld.byte 0x5 3. "PTE,Parity Self-Testing" "0: Disables the self-diagnosis function of the..,1: Enables the self-diagnosis function of the.." bitfld.byte 0x5 2. "SPIIE,SPI Idle Interrupt Enable" "0: Disables the generation of idle interrupt requests,1: Enables the generation of idle interrupt requests" newline bitfld.byte 0x5 1. "SPOE,Parity Mode" "0: Selects even parity for use in transmission and..,1: Selects odd parity for use in transmission and.." bitfld.byte 0x5 0. "SPPE,Parity Enable" "0: Does not add the parity bit to transmit data and..,1: Adds the parity bit to transmit data and checks.." repeat 8. (increment 0x0 0x1)(increment 0x0 0x2) group.word ($2+0x10)++0x1 line.word 0x0 "SPCMD$1,SPI Command Register %s" bitfld.word 0x0 15. "SCKDEN,RSPCK Delay Setting Enable" "0: An RSPCK delay of 1 RSPCK,1: An RSPCK delay is equal to the setting of the.." bitfld.word 0x0 14. "SLNDEN,SSL Negation Delay Setting Enable" "0: An SSL negation delay of 1 RSPCK,1: An SSL negation delay is equal to the setting of.." newline bitfld.word 0x0 13. "SPNDEN,RSPI Next-Access Delay Enable" "0: A next-access delay of 1 RSPCK + 2 PCLK,1: A next-access delay is equal to the setting of.." bitfld.word 0x0 12. "LSBF,RSPI LSB First" "0: MSB first,1: LSB first" newline hexmask.word.byte 0x0 8.--11. 1. "SPB,RSPI Data Length Setting" bitfld.word 0x0 7. "SSLKP,SSL Signal Level Keeping" "0: Negates all SSL signals upon completion of..,1: Keeps the SSL signal level from the end of.." newline bitfld.word 0x0 4.--6. "SSLA,SSL Signal Assertion Setting" "0: Setting prohibited,1: SSL1,?,?,?,?,?,?" bitfld.word 0x0 2.--3. "BRDV,Bit Rate Division Setting" "0: These bits select the base bit rate,1: These bits select the base bit rate divided by 2,?,?" newline bitfld.word 0x0 1. "CPOL,RSPCK Polarity Setting" "0: RSPCK is low when idle,1: RSPCK is high when idle" bitfld.word 0x0 0. "CPHA,RSPCK Phase Setting" "0: Data sampling on odd edge data variation on even..,1: Data variation on odd edge data sampling on even.." repeat.end tree.end tree "SPI1" base ad:0x40072100 group.byte 0x0++0x3 line.byte 0x0 "SPCR,SPI Control Register" bitfld.byte 0x0 7. "SPRIE,SPI Receive Buffer Full Interrupt Enable" "0: Disables the generation of SPI receive buffer..,1: Enables the generation of SPI receive buffer.." bitfld.byte 0x0 6. "SPE,SPI Function Enable" "0: Disables the SPI function,1: Enables the SPI function" newline bitfld.byte 0x0 5. "SPTIE,Transmit Buffer Empty Interrupt Enable" "0: Disables the generation of transmit buffer empty..,1: Enables the generation of transmit buffer empty.." bitfld.byte 0x0 4. "SPEIE,SPI Error Interrupt Enable" "0: Disables the generation of SPI error interrupt..,1: Enables the generation of SPI error interrupt.." newline bitfld.byte 0x0 3. "MSTR,SPI Master/Slave Mode Select" "0: Slave mode,1: Master mode" bitfld.byte 0x0 2. "MODFEN,Mode Fault Error Detection Enable" "0: Disables the detection of mode fault error,1: Enables the detection of mode fault error" newline bitfld.byte 0x0 1. "TXMD,Communications Operating Mode Select" "0: Full-duplex synchronous serial communications,1: Serial communications consisting of only.." bitfld.byte 0x0 0. "SPMS,SPI Mode Select" "0: SPI operation (4-wire method),1: Clock synchronous operation (3-wire method)" line.byte 0x1 "SSLP,SPI Slave Select Polarity Register" hexmask.byte 0x1 4.--7. 1. "Reserved,These bits are read as 0000. The write value should be 0000." bitfld.byte 0x1 3. "SSL3P,SSL3 Signal Polarity Setting" "0: SSL3 signal is active low,1: SSL3 signal is active high" newline bitfld.byte 0x1 2. "SSL2P,SSL2 Signal Polarity Setting" "0: SSL2 signal is active low,1: SSL2 signal is active high" bitfld.byte 0x1 1. "SSL1P,SSL1 Signal Polarity Setting" "0: SSL1 signal is active low,1: SSL1 signal is active high" newline bitfld.byte 0x1 0. "SSL0P,SSL0 Signal Polarity Setting" "0: SSL0 signal is active low,1: SSL0 signal is active high" line.byte 0x2 "SPPCR,SPI Pin Control Register" bitfld.byte 0x2 6.--7. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.byte 0x2 5. "MOIFE,MOSI Idle Value Fixing Enable" "0: MOSI output value equals final data from..,1: MOSI output value equals the value set in the.." newline bitfld.byte 0x2 4. "MOIFV,MOSI Idle Fixed Value" "0: The level output on the MOSIn pin during MOSI..,1: The level output on the MOSIn pin during MOSI.." bitfld.byte 0x2 2.--3. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" newline bitfld.byte 0x2 1. "SPLP2,RSPI Loopback 2" "0: Normal mode,1: Loopback mode (data is not inverted for.." bitfld.byte 0x2 0. "SPLP,RSPI Loopback" "0: Normal mode,1: Loopback mode (data is inverted for transmission)" line.byte 0x3 "SPSR,SPI Status Register" bitfld.byte 0x3 7. "SPRF,SPI Receive Buffer Full Flag" "0: No valid data in SPDR,1: Valid data found in SPDR" bitfld.byte 0x3 6. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.byte 0x3 5. "SPTEF,SPI Transmit Buffer Empty Flag" "0: Data found in the transmit buffer,1: No data in the transmit buffer" bitfld.byte 0x3 4. "UDRF,Underrun Error Flag(When MODF is 0 This bit is invalid.)" "0: A mode fault error occurs (MODF=1),1: An underrun error occurs (MODF=1)" newline bitfld.byte 0x3 3. "PERF,Parity Error Flag" "0: No parity error occurs,1: A parity error occurs" bitfld.byte 0x3 2. "MODF,Mode Fault Error Flag" "0: Neither mode fault error nor underrun error occurs,1: A mode fault error or an underrun error occurs." newline rbitfld.byte 0x3 1. "IDLNF,SPI Idle Flag" "0: SPI is in the idle state,1: SPI is in the transfer state" bitfld.byte 0x3 0. "OVRF,Overrun Error Flag" "0: No overrun error occurs,1: An overrun error occurs" group.long 0x4++0x3 line.long 0x0 "SPDR,SPI Data Register" hexmask.long 0x0 0.--31. 1. "SPDR,SPDR is the interface with the buffers that hold data for transmission and reception by the RSPI.When accessing in word (SPDCR.SPLW=1) access SPDR." group.word 0x4++0x1 line.word 0x0 "SPDR_HA,SPI Data Register ( halfword access )" hexmask.word 0x0 0.--15. 1. "SPDR_HA,SPDR is the interface with the buffers that hold data for transmission and reception by the RSPI.When accessing in halfword (SPDCR.SPLW=0) access SPDR_HA." group.byte 0xA++0x5 line.byte 0x0 "SPBR,SPI Bit Rate Register" hexmask.byte 0x0 0.--7. 1. "SPR,SPBR sets the bit rate in master mode." line.byte 0x1 "SPDCR,SPI Data Control Register" bitfld.byte 0x1 6.--7. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.byte 0x1 5. "SPLW,SPI Word Access/Halfword Access Specification" "0: SPDR_HA is valid to access in halfwords,1: SPDR is valid (to access in words)." newline bitfld.byte 0x1 4. "SPRDTD,RSPI Receive/Transmit Data Selection" "0: SPDR values are read from the receive buffer,1: SPDR values are read from the transmit buffer.." hexmask.byte 0x1 0.--3. 1. "Reserved,These bits are read as 0000. The write value should be 0000." line.byte 0x2 "SPCKD,SPI Clock Delay Register" hexmask.byte 0x2 3.--7. 1. "Reserved,These bits are read as 00000. The write value should be 00000." bitfld.byte 0x2 0.--2. "SCKDL,RSPCK Delay Setting" "0: 1 RSPCK,1: 2 RSPCK,?,?,?,?,?,?" line.byte 0x3 "SSLND,SPI Slave Select Negation Delay Register" hexmask.byte 0x3 3.--7. 1. "Reserved,These bits are read as 00000. The write value should be 00000." bitfld.byte 0x3 0.--2. "SLNDL,SSL Negation Delay Setting" "0: 1 RSPCK,1: 2 RSPCK,?,?,?,?,?,?" line.byte 0x4 "SPND,SPI Next-Access Delay Register" hexmask.byte 0x4 3.--7. 1. "Reserved,These bits are read as 00000. The write value should be 00000." bitfld.byte 0x4 0.--2. "SPNDL,SPI Next-Access Delay Setting" "0: 1 RSPCK + 2 PCLK,1: 2 RSPCK + 2 PCLK,?,?,?,?,?,?" line.byte 0x5 "SPCR2,SPI Control Register 2" bitfld.byte 0x5 5.--7. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.byte 0x5 4. "SCKASE,RSPCK Auto-Stop Function Enable" "0: Disables the RSPCK auto-stop function,1: Enables the RSPCK auto-stop function" newline bitfld.byte 0x5 3. "PTE,Parity Self-Testing" "0: Disables the self-diagnosis function of the..,1: Enables the self-diagnosis function of the.." bitfld.byte 0x5 2. "SPIIE,SPI Idle Interrupt Enable" "0: Disables the generation of idle interrupt requests,1: Enables the generation of idle interrupt requests" newline bitfld.byte 0x5 1. "SPOE,Parity Mode" "0: Selects even parity for use in transmission and..,1: Selects odd parity for use in transmission and.." bitfld.byte 0x5 0. "SPPE,Parity Enable" "0: Does not add the parity bit to transmit data and..,1: Adds the parity bit to transmit data and checks.." group.word 0x10++0x1 line.word 0x0 "SPCMD0,SPI Command Register 0" bitfld.word 0x0 15. "SCKDEN,RSPCK Delay Setting Enable" "0: An RSPCK delay of 1 RSPCK,1: An RSPCK delay is equal to the setting of the.." bitfld.word 0x0 14. "SLNDEN,SSL Negation Delay Setting Enable" "0: An SSL negation delay of 1 RSPCK,1: An SSL negation delay is equal to the setting of.." newline bitfld.word 0x0 13. "SPNDEN,RSPI Next-Access Delay Enable" "0: A next-access delay of 1 RSPCK + 2 PCLK,1: A next-access delay is equal to the setting of.." bitfld.word 0x0 12. "LSBF,RSPI LSB First" "0: MSB first,1: LSB first" newline hexmask.word.byte 0x0 8.--11. 1. "SPB,RSPI Data Length Setting" bitfld.word 0x0 7. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.word 0x0 4.--6. "SSLA,SSL Signal Assertion Setting" "0: Setting prohibited,1: SSL1,?,?,?,?,?,?" bitfld.word 0x0 2.--3. "BRDV,Bit Rate Division Setting" "0: These bits select the base bit rate,1: These bits select the base bit rate divided by 2,?,?" newline bitfld.word 0x0 1. "CPOL,RSPCK Polarity Setting" "0: RSPCK is low when idle,1: RSPCK is high when idle" bitfld.word 0x0 0. "CPHA,RSPCK Phase Setting" "0: Data sampling on odd edge data variation on even..,1: Data variation on odd edge data sampling on even.." tree.end tree.end tree "SPMON (CPU Stack Pointer Monitor)" base ad:0x40000D00 group.word 0x0++0x1 line.word 0x0 "MSPMPUOAD,Stack Pointer Monitor Operation After Detection Register" hexmask.word.byte 0x0 8.--15. 1. "KEY,Write Keyword The data written to these bits are not stored." hexmask.word.byte 0x0 1.--7. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." newline bitfld.word 0x0 0. "OAD,Operation after detection" "0: Non-maskable interrupt,1: Reset." group.word 0x4++0x3 line.word 0x0 "MSPMPUCTL,Stack Pointer Monitor Access Control Register" hexmask.word.byte 0x0 9.--15. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.word 0x0 8. "ERROR,Stack Pointer Monitor Error Flag" "0: Stack pointer has not overflowed or underflowed,1: Stack pointer has overflowed or underflowed" newline hexmask.word.byte 0x0 1.--7. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.word 0x0 0. "ENABLE,Stack Pointer Monitor Enable" "0: Stack pointer monitor is disabled,1: Stack pointer monitor is enabled." line.word 0x2 "MSPMPUPT,Stack Pointer Monitor Protection Register" hexmask.word.byte 0x2 8.--15. 1. "KEY,Write Keyword The data written to these bits are not stored." hexmask.word.byte 0x2 1.--7. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." newline bitfld.word 0x2 0. "PROTECT,Protection of register (MSPMPUAC MSPMPUSA and MSPMPUSE)" "0: Stack Pointer Monitor register writing is..,1: Stack Pointer Monitor register writing is.." group.long 0x8++0x7 line.long 0x0 "MSPMPUSA,Main Stack Pointer (MSP) Monitor Start Address Register" hexmask.long 0x0 0.--31. 1. "MSPMPUSA,Region start address register Address where the region starts for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFFC The low-order 2 bits are fixed to 0." line.long 0x4 "MSPMPUEA,Main Stack Pointer (MSP) Monitor End Address Register" hexmask.long 0x4 0.--31. 1. "MSPMPUEA,Region end address register Address where the region starts for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFFF The low-order 2 bits are fixed to 1." group.word 0x10++0x1 line.word 0x0 "PSPMPUOAD,Stack Pointer Monitor Operation After Detection Register" hexmask.word.byte 0x0 8.--15. 1. "KEY,Key CodeThe data written to these bits are not stored." hexmask.word.byte 0x0 1.--7. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." newline bitfld.word 0x0 0. "OAD,Operation after detection" "0: Non-maskable interrupt,1: Reset." group.word 0x14++0x3 line.word 0x0 "PSPMPUCTL,Stack Pointer Monitor Access Control Register" hexmask.word.byte 0x0 9.--15. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.word 0x0 8. "ERROR,Stack Pointer Monitor Error Flag" "0: Stack pointer has not overflowed or underflowed,1: Stack pointer has overflowed or underflowed" newline hexmask.word.byte 0x0 1.--7. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.word 0x0 0. "ENABLE,Stack Pointer Monitor Enable" "0: Stack pointer monitor is disabled,1: Stack pointer monitor is enabled" line.word 0x2 "PSPMPUPT,Stack Pointer Monitor Protection Register" hexmask.word.byte 0x2 8.--15. 1. "KEY,Key CodeThe data written to these bits are not stored." hexmask.word.byte 0x2 1.--7. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." newline bitfld.word 0x2 0. "PROTECT,Protection register (PSPMPUAC PSPMPUSA and PSPMPUSE)" "0: Stack Pointer Monitor register writing is..,1: Stack Pointer Monitor register writing is.." group.long 0x18++0x7 line.long 0x0 "PSPMPUSA,Process Stack Pointer (PSP) Monitor Start Address Register" hexmask.long 0x0 0.--31. 1. "PSPMPUSA,Region start address register Address where the region starts for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFFC The low-order 2 bits are fixed to 0." line.long 0x4 "PSPMPUEA,Process Stack Pointer (PSP) Monitor End Address Register" hexmask.long 0x4 0.--31. 1. "PSPMPUEA,Region end address register Address where the region starts for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFFF The low-order 2 bits are fixed to 1." tree.end tree "SRAM (SRAM Control)" base ad:0x40002000 group.byte 0x0++0x0 line.byte 0x0 "PARIOAD,SRAM Parity Error Operation After Detection Register" hexmask.byte 0x0 1.--7. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.byte 0x0 0. "OAD,Operation after Detection" "0: Non maskable interrupt.,1: Reset" group.byte 0x4++0x0 line.byte 0x0 "SRAMPRCR,SRAM Protection Register" hexmask.byte 0x0 1.--7. 1. "KW,Write Key Code" bitfld.byte 0x0 0. "SRAMPRCR,Register Write Control" "0: Disable writes to protected registers,1: Enable writes to protected registers." group.byte 0xC0++0x4 line.byte 0x0 "ECCMODE,ECC Operating Mode Control Register" hexmask.byte 0x0 2.--7. 1. "Reserved,These bits are read as 000000. The write value should be 000000." bitfld.byte 0x0 0.--1. "ECCMOD,ECC Operating Mode Select" "0: Disable ECC function,1: Setting prohibited,?,?" line.byte 0x1 "ECC2STS,ECC 2-Bit Error Status Register" hexmask.byte 0x1 1.--7. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.byte 0x1 0. "ECC2ERR,ECC 2-Bit Error Status" "0: No 2-bit ECC error occurred,1: 2-bit ECC error occurred." line.byte 0x2 "ECC1STSEN,ECC 1-Bit Error Information Update Enable Register" hexmask.byte 0x2 1.--7. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.byte 0x2 0. "E1STSEN,ECC 1-Bit Error Information Update Enable" "0: Disables updating of the 1-bit ECC error..,1: Bit Error Information Update Enable" line.byte 0x3 "ECC1STS,ECC 1-Bit Error Status Register" hexmask.byte 0x3 1.--7. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.byte 0x3 0. "ECC1ERR,ECC 1-Bit Error Status" "0: No 1-bit ECC error occurred,1: Bit Error Status" line.byte 0x4 "ECCPRCR,ECC Protection Register" hexmask.byte 0x4 1.--7. 1. "KW,Write Key Code" bitfld.byte 0x4 0. "ECCPRCR,Register Write Control" "0: Disable writes to the protected registers,1: Enable writes to the protected registers" group.byte 0xD0++0x0 line.byte 0x0 "ECCPRCR2,ECC Protection Register 2" hexmask.byte 0x0 1.--7. 1. "KW2,Write Key Code" bitfld.byte 0x0 0. "ECCPRCR2,Register Write Control" "0: Disable writes to the protected registers,1: Enable writes to the protected registers." group.byte 0xD4++0x0 line.byte 0x0 "ECCETST,ECC Test Control Register" hexmask.byte 0x0 1.--7. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.byte 0x0 0. "TSTBYP,ECC Bypass Select" "0: ECC bypass disabled.,1: ECC bypass enabled." group.byte 0xD8++0x0 line.byte 0x0 "ECCOAD,SRAM ECC Error Operation After Detection Register" hexmask.byte 0x0 1.--7. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.byte 0x0 0. "OAD,Operation after Detection" "0: Non-maskable interrupt,1: Reset" tree.end tree "SYSTEM (System Control)" base ad:0x4001E000 group.byte 0x41F++0x0 line.byte 0x0 "VBTCR1,VBATT Control Register1" hexmask.byte 0x0 1.--7. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.byte 0x0 0. "BPWSWSTP,Battery Power supply Switch Stop" "0: Battery Power supply Switch Enable,1: Battery Power supply Switch stop" group.byte 0x4B0++0x2 line.byte 0x0 "VBTCR2,VBATT Control Register2" bitfld.byte 0x0 6.--7. "VBTLVDLVL,VBATT Pin Voltage Low Voltage Detect Level Select Bit" "0: 2.7V,1: Setting prohibited,?,?" bitfld.byte 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.byte 0x0 4. "VBTLVDEN,VBATT Pin Low Voltage Detect Enable Bit" "0: VBATT pin low voltage detect disable,1: VBATT pin low voltage detect enable" hexmask.byte 0x0 0.--3. 1. "Reserved,These bits are read as 0000. The write value should be 0000." line.byte 0x1 "VBTSR,VBATT Status Register" bitfld.byte 0x1 5.--7. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" rbitfld.byte 0x1 4. "VBTRVLD,VBATT_R Valid" "0: VBATT_R area not valid,1: VBATT_R area valid" newline bitfld.byte 0x1 2.--3. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.byte 0x1 1. "VBTBLDF,VBATT Battery Low voltage Detect Flag" "0: VBATT pin low voltage not detected,1: VBATT pin low voltage detected." newline bitfld.byte 0x1 0. "VBTRDF,VBAT_R Reset Detect Flag" "0: VBATT_R voltage power-on reset not detected,1: VBATT_R selected voltage power-on reset detected." line.byte 0x2 "VBTCMPCR,VBATT Comparator Control Register" hexmask.byte 0x2 1.--7. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.byte 0x2 0. "VBTCMPE,VBATT pin low voltage detect circuit output enable" "0: VBATT pin low voltage detect circuit output..,1: VBATT pin low voltage detect circuit output.." group.byte 0x4B4++0x0 line.byte 0x0 "VBTLVDICR,VBATT Pin Low Voltage Detect Interrupt Control Register" hexmask.byte 0x0 2.--7. 1. "Reserved,These bits are read as 000000. The write value should be 000000." bitfld.byte 0x0 1. "VBTLVDISEL,Pin Low Voltage Detect Interrupt Select bit" "0: Non Maskable Interrupt,1: Maskable Interrupt" newline bitfld.byte 0x0 0. "VBTLVDIE,VBATT Pin Low Voltage Detect Interrupt Enable bit" "0: VBATT Pin Low Voltage Detect Interrupt Disable,1: VBATT Pin Low Voltage Detect Interrupt Enable" group.byte 0x4B6++0x0 line.byte 0x0 "VBTWCTLR,VBATT Wakeup function Control Register" hexmask.byte 0x0 1.--7. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.byte 0x0 0. "VWEN,VBATT wakeup enable" "0: Disable Wakeup function,1: Enable Wakeup function" group.byte 0x4B8++0x7 line.byte 0x0 "VBTWCH0OTSR,VBATT Wakeup I/O 0 Output Trigger Select Register" bitfld.byte 0x0 5.--7. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.byte 0x0 4. "CH0VRTCATE,VBATWIO0 Output RTC Alarm Signal Enable" "0: VBATT wakeup I/O 0 output trigger by the RTC..,1: VBATT wakeup I/O 0 output trigger by the RTC.." newline bitfld.byte 0x0 3. "CH0VRTCTE,VBATWIO0 Output RTC Periodic Signal Enable" "0: VBATT wakeup I/O 0 output trigger by the RTC..,1: VBATT wakeup I/O 0 output trigger by the RTC.." bitfld.byte 0x0 2. "CH0VCH2TE,VBATWIO0 Output VBATWIO2 Trigger Enable" "0: VBATT wakeup I/O 0 output trigger by the..,1: VBATT wakeup I/O 0 output trigger by the.." newline bitfld.byte 0x0 1. "CH0VCH1TE,VBATWIO0 Output VBATWIO1 Trigger Enable" "0: VBATT wakeup I/O 0 output trigger by the..,1: VBATT wakeup I/O 0 output trigger by the.." bitfld.byte 0x0 0. "Reserved,This bit is read as 0. The write value should be 0." "0,1" line.byte 0x1 "VBTWCH1OTSR,VBATT Wakeup I/O 1 Output Trigger Select Register" bitfld.byte 0x1 5.--7. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.byte 0x1 4. "CH1VRTCATE,VBATWIO1 Output RTC Alarm Signal Enable" "0: VBATT wakeup I/O 1 output trigger by the RTC..,1: VBATT wakeup I/O 1 output trigger by the RTC.." newline bitfld.byte 0x1 3. "CH1VRTCTE,VBATWIO1 Output RTC Periodic Signal Enable" "0: VBATT wakeup I/O 1 output trigger by the RTC..,1: VBATT wakeup I/O 1 output trigger by the RTC.." bitfld.byte 0x1 2. "CH1VCH2TE,VBATWIO1 Output VBATWIO2 Trigger Enable" "0: VBATT wakeup I/O 1 output trigger by the..,1: VBATT wakeup I/O 1 output trigger by the.." newline bitfld.byte 0x1 1. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x1 0. "CH1VCH0TE,VBATWIO1 Output VBATWIO0 Trigger Enable" "0: VBATT wakeup I/O 1 output trigger by the..,1: VBATT wakeup I/O 1 output trigger by the.." line.byte 0x2 "VBTWCH2OTSR,VBATT Wakeup I/O 2 Output Trigger Select Register" bitfld.byte 0x2 5.--7. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.byte 0x2 4. "CH2VRTCATE,VBATWIO2 Output RTC Alarm Signal Enable" "0: VBATT wakeup I/O 2 output trigger by the RTC..,1: VBATT wakeup I/O 2 output trigger by the RTC.." newline bitfld.byte 0x2 3. "CH2VRTCTE,VBATWIO2 Output RTC Periodic Signal Enable" "0: VBATT wakeup I/O 2 output trigger by the RTC..,1: VBATT wakeup I/O 2 output trigger by the RTC.." bitfld.byte 0x2 2. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.byte 0x2 1. "CH2VCH1TE,VBATWIO2 Output VBATWIO1 Trigger Enable" "0: VBATT wakeup I/O 2 output trigger by the..,1: VBATT wakeup I/O 2 output trigger by the.." bitfld.byte 0x2 0. "CH2VCH0TE,VBATWIO2 Output VBATWIO0 Trigger Enable" "0: VBATT wakeup I/O 2 output trigger by the..,1: VBATT wakeup I/O 2 output trigger by the.." line.byte 0x3 "VBTICTLR,VBATT Input Control Register" hexmask.byte 0x3 3.--7. 1. "Reserved,These bits are read as 00000. The write value should be 00000." bitfld.byte 0x3 2. "VCH2INEN,VBATT Wakeup I/O 2 Input Enable" "0: VBATWIO2 and RTCIC2 inputs disabled,1: VBATWIO2 and RTCIC2 inputs enabled." newline bitfld.byte 0x3 1. "VCH1INEN,VBATT Wakeup I/O 1 Input Enable" "0: VBATWIO1 RTCIC1 inputs disabled,1: VBATWIO1 RTCIC1 inputs enabled." bitfld.byte 0x3 0. "VCH0INEN,VBATT Wakeup I/O 0 Input Enable" "0: VBATWIO0 RTCIC0 inputs disabled,1: VBATWIO0 RTCIC0 inputs enabled." line.byte 0x4 "VBTOCTLR,VBATT Output Control Register" bitfld.byte 0x4 6.--7. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.byte 0x4 5. "VOUT2LSEL,VBATT Wakeup I/O 2 Output Level Selection" "0: Output L before VBATT wake up trigger,1: Output H before VBATT wake up trigger" newline bitfld.byte 0x4 4. "VCOU1LSEL,VBATT Wakeup I/O 1 Output Level Selection" "0: Output L before VBATT wake up trigger,1: Output H before VBATT wake up trigger" bitfld.byte 0x4 3. "VOUT0LSEL,VBATT Wakeup I/O 0 Output Level Selection" "0: Output L before VBATT wakeup trigger,1: Output H before VBATT wakeup trigger" newline bitfld.byte 0x4 2. "VCH2OEN,VBATT Wakeup I/O 2 Output Enable" "0: VBATWIO2 output disabled,1: VBATWIO2 output enabled" bitfld.byte 0x4 1. "VCH1OEN,VBATT Wakeup I/O 1 Output Enable" "0: VBATWIO1 output disabled,1: VBATWIO1 output enabled" newline bitfld.byte 0x4 0. "VCH0OEN,VBATT Wakeup I/O 0 Output Enable" "0: VBATWIO0 output disabled,1: VBATWIO0 output enabled" line.byte 0x5 "VBTWTER,VBATT Wakeup Trigger source Enable Register" bitfld.byte 0x5 5.--7. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.byte 0x5 4. "VRTCAE,RTC Alarm Signal Enable" "0: VBATT wakeup triggered by RTC alarm signal is..,1: VBATT wakeup triggered by RTC alarm signal is.." newline bitfld.byte 0x5 3. "VRTCIE,RTC Periodic Signal Enable" "0: VBATT wakeup triggered by RTC periodic signal is..,1: VBATT wakeup triggered by RTC periodic signal is.." bitfld.byte 0x5 2. "VCH2E,VBATWIO2 Pin Enable" "0: VBATT wakeup triggered by the VBATWIO2 pin is..,1: VBATT wakeup triggered by the VBATWIO2 pin is.." newline bitfld.byte 0x5 1. "VCH1E,VBATWIO1 Pin Enable" "0: VBATT wakeup triggered by the VBATWIO1 pin is..,1: VBATT wakeup triggered by the VBATWIO1 pin is.." bitfld.byte 0x5 0. "VCH0E,VBATWIO0 Pin Enable" "0: VBATT wakeup triggered by the VBATWIO0 pin is..,1: VBATT wakeup triggered by the VBATWIO0 pin is.." line.byte 0x6 "VBTWEGR,VBATT Wakeup Trigger source Edge Register" hexmask.byte 0x6 3.--7. 1. "Reserved,These bits are read as 00000. The write value should be 00000." bitfld.byte 0x6 2. "VCH2EG,VBATWIO2 Wakeup Trigger Source Edge Select" "0: Wakeup trigger is generated at a falling edge,1: Wakeup trigger is generated at a rising edge." newline bitfld.byte 0x6 1. "VCH1EG,VBATWIO1 Wakeup Trigger Source Edge Select" "0: Wakeup trigger is generated at a falling edge,1: Wakeup trigger is generated at a rising edge." bitfld.byte 0x6 0. "VCH0EG,VBATWIO0 Wakeup Trigger Source Edge Select" "0: Wakeup trigger is generated at a falling edge,1: Wakeup trigger is generated at a rising edge." line.byte 0x7 "VBTWFR,VBATT Wakeup trigger source Flag Register" bitfld.byte 0x7 5.--7. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.byte 0x7 4. "VRTCAF,VBATT RTC-Alarm Wakeup Trigger Flag" "0: No wakeup trigger by the RTC alarm is generated,1: A wakeup trigger by the RTC alarm is generated" newline bitfld.byte 0x7 3. "VRTCIF,VBATT RTC-Interval Wakeup Trigger Flag" "0: No wakeup trigger by the RTC interval is generated,1: A wakeup trigger by the RTC interval is generated" bitfld.byte 0x7 2. "VCH2F,VBATWIO2 Wakeup Trigger Flag" "0: No wakeup trigger by the VBATWIO2 pin is generated,1: A wakeup trigger by the VBATWIO2 pin is generated" newline bitfld.byte 0x7 1. "VCH1F,VBATWIO1 Wakeup Trigger Flag" "0: No wakeup trigger by the VBATWIO1 pin is generated,1: A wakeup trigger by the VBATWIO1 pin is generated" bitfld.byte 0x7 0. "VCH0F,VBATWIO0 Wakeup Trigger Flag" "0: No wakeup trigger by the VBATWIO0 pin is generated,1: A wakeup trigger by the VBATWIO0 pin is generated" repeat 512. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2+0x500)++0x0 line.byte 0x0 "VBTBKR[$1],VBATT Backup Register [%s]" hexmask.byte 0x0 0.--7. 1. "VBTBKR,VBTBKR is a 512-byte readable/writable register to store data powered by VBATT.The value of this register is retained even when VCC is not powered but VBATT is powered.VBTBKR is initialized by VBATT selected voltage power-on-reset." repeat.end group.byte 0x410++0x1 line.byte 0x0 "RSTSR0,Reset Status Register 0" hexmask.byte 0x0 4.--7. 1. "Reserved,These bits are read as 0000. The write value should be 0000." bitfld.byte 0x0 3. "LVD2RF,Voltage Monitor 2 Reset Detect FlagNote: Only 0 can be written to clear the flag. The reset flag must be written with 0 after the reset flag is read as 1." "0: Voltage Monitor 2 reset not detected.,1: Voltage Monitor 2 reset detected." newline bitfld.byte 0x0 2. "LVD1RF,Voltage Monitor 1 Reset Detect FlagNote: Only 0 can be written to clear the flag. The reset flag must be written with 0 after the reset flag is read as 1." "0: Voltage Monitor 1 reset not detected.,1: Voltage Monitor 1 reset detected." bitfld.byte 0x0 1. "LVD0RF,Voltage Monitor 0 Reset Detect FlagNote: Only 0 can be written to clear the flag. The reset flag must be written with 0 after the reset flag is read as 1." "0: Voltage Monitor 0 reset not detected.,1: Voltage Monitor 0 reset detected." newline bitfld.byte 0x0 0. "PORF,Power-On Reset Detect FlagNote: Only 0 can be written to clear the flag. The reset flag must be written with 0 after the reset flag is read as 1." "0: Power-on reset not detected.,1: Power-on reset detected." line.byte 0x1 "RSTSR2,Reset Status Register 2" hexmask.byte 0x1 1.--7. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.byte 0x1 0. "CWSF,Cold/Warm Start Determination FlagNote: Only 1 can be written to set the flag." "0: Cold start,1: Warm start" group.word 0xC0++0x1 line.word 0x0 "RSTSR1,Reset Status Register 1" bitfld.word 0x0 13.--15. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.word 0x0 12. "SPERF,SP Error Reset Detect FlagNote: Only 0 can be written to clear the flag. The reset flag must be written as 0 after the reset flag is read as 1." "0: SP error reset not detected.,1: SP error reset detected." newline bitfld.word 0x0 11. "BUSMRF,Bus Master MPU Reset Detect FlagNote: Only 0 can be written to clear the flag. The reset flag must be written as 0 after the reset flag is read as 1." "0: Bus Master MPU reset not detected.,1: Bus Master MPU reset detected." bitfld.word 0x0 10. "BUSSRF,Bus Slave MPU Reset Detect FlagNote: Only 0 can be written to clear the flag. The reset flag must be written as 0 after the reset flag is read as 1." "0: Bus Slave MPU reset not detected.,1: Bus Slave MPU reset detected." newline bitfld.word 0x0 9. "REERF,RAM ECC Error Reset Detect FlagNote: Only 0 can be written to clear the flag. The reset flag must be written as 0 after the reset flag is read as 1." "0: RAM ECC error reset not detected.,1: RAM ECC error reset detected." bitfld.word 0x0 8. "RPERF,RAM Parity Error Reset Detect FlagNote: Only 0 can be written to clear the flag. The reset flag must be written as 0 after the reset flag is read as 1." "0: RAM parity error reset not detected.,1: RAM parity error reset detected." newline hexmask.word.byte 0x0 3.--7. 1. "Reserved,These bits are read as 00000. The write value should be 00000." bitfld.word 0x0 2. "SWRF,Software Reset Detect FlagNote: Only 0 can be written to clear the flag. The reset flag must be written as 0 after the reset flag is read as 1." "0: Software reset not detected.,1: Software reset detected." newline bitfld.word 0x0 1. "WDTRF,Watchdog Timer Reset Detect FlagNote: Only 0 can be written to clear the flag. The reset flag must be written as 0 after the reset flag is read as 1." "0: Watchdog timer reset not detected.,1: Watchdog timer reset detected." bitfld.word 0x0 0. "IWDTRF,Independent Watchdog Timer Reset Detect FlagNote: Only 0 can be written to clear the flag. The reset flag must be written as 0 after the reset flag is read as 1." "0: Independent watchdog timer reset not detected.,1: Independent watchdog timer reset detected." group.word 0x3FE++0x1 line.word 0x0 "PRCR,Protect Register" hexmask.word.byte 0x0 8.--15. 1. "PRKEY,PRC Key Code" hexmask.word.byte 0x0 4.--7. 1. "Reserved,These bits are read as 0000. The write value should be 0000." newline bitfld.word 0x0 3. "PRC3,Protect Bit 3" "0: Writes protected.,1: Writes not protected." bitfld.word 0x0 2. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.word 0x0 1. "PRC1,Protect Bit 1" "0: Writes protected.,1: Writes not protected." bitfld.word 0x0 0. "PRC0,Protect Bit 0" "0: Writes protected.,1: Writes not protected." group.word 0xC++0x1 line.word 0x0 "SBYCR,Standby Control Register" bitfld.word 0x0 15. "SSBY,Software Standby" "0: Sleep mode,1: Software Standby mode" bitfld.word 0x0 14. "OPE,Output Port Enable" "0: In software standby mode Address output pins..,1: In software standby mode Address output pins.." newline hexmask.word 0x0 0.--13. 1. "Reserved,These bits are read as 00000000000000. The write value should be 00000000000000." group.long 0x1C++0x3 line.long 0x0 "MSTPCRA,Module Stop Control Register A" hexmask.long.word 0x0 23.--31. 1. "Reserved,These bits are read as 111111111. The write value should be 111111111." bitfld.long 0x0 22. "MSTPA22,DMA Controller/Data Transfer Controller Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" newline hexmask.long.word 0x0 7.--21. 1. "Reserved,These bits are read as 111111111111111. The write value should be 111111111111111." bitfld.long 0x0 6. "MSTPA6,ECCRAM Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" newline hexmask.long.byte 0x0 1.--5. 1. "Reserved,These bits are read as 11111. The write value should be 11111." bitfld.long 0x0 0. "MSTPA0,RAM0 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state" group.byte 0x92++0x0 line.byte 0x0 "SNZCR,Snooze Control Register" bitfld.byte 0x0 7. "SNZE,Snooze Mode Enable" "0: Disable Snooze Mode,1: Enable Snooze Mode" hexmask.byte 0x0 2.--6. 1. "Reserved,These bits are read as 00000. The write value should be 00000." newline bitfld.byte 0x0 1. "SNZDTCEN,DTC Enable in Snooze Mode" "0: Disable DTC operation,1: Enable DTC operation" bitfld.byte 0x0 0. "RXDREQEN,RXD0 Snooze Request Enable NOTE: Do not set to 1 other than in asynchronous mode." "0: Ignore RXD0 falling edge in Software Standby mode.,1: Accept RXD0 falling edge in Standby mode as a.." group.byte 0x94++0x0 line.byte 0x0 "SNZEDCR,Snooze End Control Register" bitfld.byte 0x0 7. "SCI0UMTED,SCI0 Address Mismatch Snooze End Enable" "0: Disable the Snooze End request,1: Enable the Snooze End request" bitfld.byte 0x0 5.--6. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" newline bitfld.byte 0x0 4. "AD0UMTED,ADC140 Compare Mismatch Snooze End Enable" "0: Disable the Snooze End request,1: Enable the Snooze End request" bitfld.byte 0x0 3. "AD0MATED,ADC140 Compare Match Snooze End Enable" "0: Disable the Snooze End request,1: Enable the Snooze End request" newline bitfld.byte 0x0 2. "DTCNZRED,Not Last DTC Transmission Completion Snooze End Enable" "0: Disable the Snooze End request,1: Enable the Snooze End request" bitfld.byte 0x0 1. "DTCZRED,Last DTC Transmission Completion Snooze End Enable" "0: Disable the Snooze End request,1: Enable the Snooze End request" newline bitfld.byte 0x0 0. "AGT1UNFED,AGT1 Underflow Snooze End Enable" "0: Disable the Snooze End request,1: Enable the Snooze End request" group.long 0x98++0x3 line.long 0x0 "SNZREQCR,Snooze Request Control Register" bitfld.long 0x0 31. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 30. "SNZREQEN30,Snooze Request Enable 30Enable AGT1 compare match B snooze request" "0: Disable snooze request,1: Enable snooze request" newline bitfld.long 0x0 29. "SNZREQEN29,Snooze Request Enable 29Enable AGT1 compare match A snooze request" "0: Disable snooze request,1: Enable snooze request" bitfld.long 0x0 28. "SNZREQEN28,Snooze Request Enable 28Enable AGT1 underflow snooze request" "0: Disable snooze request,1: Enable snooze request" newline bitfld.long 0x0 26.--27. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.long 0x0 25. "SNZREQEN25,Snooze Request Enable 25Enable RTC period snooze request" "0: Disable snooze request,1: Enable snooze request" newline bitfld.long 0x0 24. "SNZREQEN24,Snooze Request Enable 24Enable RTC alarm snooze request" "0: Disable snooze request,1: Enable snooze request" bitfld.long 0x0 23. "SNZREQEN23,Snooze Request Enable 23Enable RTC alarm snooze request" "0: Disable snooze request,1: Enable snooze request" newline hexmask.long.byte 0x0 18.--22. 1. "Reserved,These bits are read as 00000. The write value should be 00000." bitfld.long 0x0 17. "SNZREQEN17,Snooze Request Enable 17Enable KR snooze request" "0: Disable snooze request,1: Enable snooze request" newline bitfld.long 0x0 16. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 15. "SNZREQEN15,Snooze Request Enable 15Enable IRQ15 pin snooze request" "0: Disable snooze request,1: Enable snooze request" newline bitfld.long 0x0 14. "SNZREQEN14,Snooze Request Enable 14Enable IRQ14 pin snooze request" "0: Disable snooze request,1: Enable snooze request" bitfld.long 0x0 13. "SNZREQEN13,Snooze Request Enable 13Enable IRQ13 pin snooze request" "0: Disable snooze request,1: Enable snooze request" newline bitfld.long 0x0 12. "SNZREQEN12,Snooze Request Enable 12Enable IRQ12 pin snooze request" "0: Disable snooze request,1: Enable snooze request" bitfld.long 0x0 11. "SNZREQEN11,Snooze Request Enable 11Enable IRQ11 pin snooze request" "0: Disable snooze request,1: Enable snooze request" newline bitfld.long 0x0 10. "SNZREQEN10,Snooze Request Enable 10Enable IRQ10 pin snooze request" "0: Disable snooze request,1: Enable snooze request" bitfld.long 0x0 9. "SNZREQEN9,Snooze Request Enable 9Enable IRQ9 pin snooze request" "0: Disable snooze request,1: Enable snooze request" newline bitfld.long 0x0 8. "SNZREQEN8,Snooze Request Enable 8Enable IRQ8 pin snooze request" "0: Disable snooze request,1: Enable snooze request" bitfld.long 0x0 7. "SNZREQEN7,Snooze Request Enable 7Enable IRQ7 pin snooze request" "0: Disable snooze request,1: Enable snooze request" newline bitfld.long 0x0 6. "SNZREQEN6,Snooze Request Enable 6Enable IRQ6 pin snooze request" "0: Disable snooze request,1: Enable snooze request" bitfld.long 0x0 5. "SNZREQEN5,Snooze Request Enable 5Enable IRQ5 pin snooze request" "0: Disable snooze request,1: Enable snooze request" newline bitfld.long 0x0 4. "SNZREQEN4,Snooze Request Enable 4Enable IRQ4 pin snooze request" "0: Disable snooze request,1: Enable snooze request" bitfld.long 0x0 3. "SNZREQEN3,Snooze Request Enable 3Enable IRQ3 pin snooze request" "0: Disable snooze request,1: Enable snooze request" newline bitfld.long 0x0 2. "SNZREQEN2,Snooze Request Enable 2Enable IRQ2 pin snooze request" "0: Disable snooze request,1: Enable snooze request" bitfld.long 0x0 1. "SNZREQEN1,Snooze Request Enable 1Enable IRQ1 pin snooze request" "0: Disable snooze request,1: Enable snooze request" newline bitfld.long 0x0 0. "SNZREQEN0,Snooze Request Enable 0Enable IRQ0 pin snooze request" "0: Disable snooze request,1: Enable snooze request" group.byte 0x9F++0x0 line.byte 0x0 "PSMCR,Power Save Memory Control Register" hexmask.byte 0x0 2.--7. 1. "Reserved,These bits are read as 000000. The write value should be 000000." bitfld.byte 0x0 0.--1. "PSMC,Power save memory control." "0: Setting prohibited.,1: 48KB RAM is on in Software Standby mode.,?,?" group.byte 0x9E++0x0 line.byte 0x0 "FLSTOP,Flash Operation Control Register" bitfld.byte 0x0 5.--7. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.byte 0x0 4. "FLSTPF,Flash Memory Operation Status Flag" "0: Transition completed,1: During transition (from the flash-stop-status to.." newline bitfld.byte 0x0 1.--3. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.byte 0x0 0. "FLSTOP,Selecting ON/OFF of the Flash Memory Operation" "0: Code flash and data flash memory operates,1: Code flash and data flash memory stops." group.byte 0xA0++0x0 line.byte 0x0 "OPCCR,Operating Power Control Register" bitfld.byte 0x0 5.--7. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.byte 0x0 4. "OPCMTSF,Operating Power Control Mode Transition Status Flag" "0: Transition completed,1: During transition" newline bitfld.byte 0x0 2.--3. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.byte 0x0 0.--1. "OPCM,Operating Power Control Mode Select" "0: High-speed mode,1: Middle-speed mode,?,?" group.byte 0xAA++0x0 line.byte 0x0 "SOPCCR,Sub Operating Power Control Register" bitfld.byte 0x0 5.--7. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" rbitfld.byte 0x0 4. "SOPCMTSF,Sub Operating Power Control Mode Transition Status Flag" "0: Transition completed,1: During transition" newline bitfld.byte 0x0 1.--3. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.byte 0x0 0. "SOPCM,Sub Operating Power Control Mode Select" "0: Other than Subosc-speed mode,1: Subosc-speed mode" group.byte 0x40E++0x0 line.byte 0x0 "SYOCDCR,System Control OCD Control Register" bitfld.byte 0x0 7. "DBGEN,Debugger Enable bit" "0: On-chip debugger is disabled,1: On-chip debugger is enabled" hexmask.byte 0x0 0.--6. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." group.long 0x20++0x3 line.long 0x0 "SCKDIVCR,System Clock Division Control Register" bitfld.long 0x0 31. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 28.--30. "FCK,Flash IF Clock (FCLK) Select" "0: Setting prohibited,1: /2,?,?,?,?,?,?" newline bitfld.long 0x0 27. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 24.--26. "ICK,System Clock (ICLK) Select" "0: Setting prohibited,1: /2,?,?,?,?,?,?" newline hexmask.long.byte 0x0 19.--23. 1. "Reserved,These bits are read as 00000. The write value should be 00000." bitfld.long 0x0 16.--18. "BCK,External Bus Clock (BCLK) Select" "0: Setting prohibited,1: /2,?,?,?,?,?,?" newline bitfld.long 0x0 15. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 12.--14. "PCKA,Peripheral Module Clock A (PCLKA) Select" "0: Setting prohibited,1: /2,?,?,?,?,?,?" newline bitfld.long 0x0 11. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 8.--10. "PCKB,Peripheral Module Clock B (PCLKB) Select" "0: Setting prohibited,1: /2,?,?,?,?,?,?" newline bitfld.long 0x0 7. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 4.--6. "PCKC,Peripheral Module Clock C (PCLKC) Select" "0: Setting prohibited,1: /2,?,?,?,?,?,?" newline bitfld.long 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.long 0x0 0.--2. "PCKD,Peripheral Module Clock D (PCLKD) Select" "0: Setting prohibited,1: /2,?,?,?,?,?,?" group.byte 0x26++0x0 line.byte 0x0 "SCKSCR,System Clock Source Control Register" hexmask.byte 0x0 3.--7. 1. "Reserved,These bits are read as 00000. The write value should be 00000." bitfld.byte 0x0 0.--2. "CKSEL,Clock Source SelectSelecting the system clock source faster than 32MHz(system clock source > 32MHz ) is prohibit when SCKDIVCR.ICK[2:0] bits select the division-by-1 and MEMWAIT.MEMWAIT =0." "0: Setting prohibited,1: MOCO,?,?,?,?,?,?" group.byte 0x2A++0x1 line.byte 0x0 "PLLCR,PLL Control Register" hexmask.byte 0x0 1.--7. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.byte 0x0 0. "PLLSTP,PLL Stop Control" "0: PLL is operating.,1: PLL is stopped." line.byte 0x1 "PLLCCR2,PLL Clock Control Register2" bitfld.byte 0x1 6.--7. "PLODIV,PLL Output Frequency Division Ratio Select" "0: /1.,1: /2.,?,?" bitfld.byte 0x1 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline hexmask.byte 0x1 0.--4. 1. "PLLMUL,PLL Frequency Multiplication Factor Select" group.byte 0x30++0x2 line.byte 0x0 "BCKCR,External Bus Clock Control Register" hexmask.byte 0x0 1.--7. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.byte 0x0 0. "BCLKDIV,EBCLK Pin Output Select" "0: BCLK,1: BCLK/2" line.byte 0x1 "MEMWAIT,Memory Wait Cycle Control Register" hexmask.byte 0x1 1.--7. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.byte 0x1 0. "MEMWAIT,Memory Wait Cycle SelectNote: Writing 0 to the MEMWAIT is prohibited when SCKDIVCR.ICK selects division by 1 and SCKSCR.CKSEL[2:0] bits select thesystem clock source that is faster than 32 MHz (ICLK > 32 MHz)." "0: no wait,1: wait" line.byte 0x2 "MOSCCR,Main Clock Oscillator Control Register" hexmask.byte 0x2 1.--7. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.byte 0x2 0. "MOSTP,Main Clock Oscillator StopNote: MOMCR register must be set before setting MOSTP to 0." "0: Main clock oscillator is operating.,1: Main clock oscillator is stopped." group.byte 0x36++0x0 line.byte 0x0 "HOCOCR,High-Speed On-Chip Oscillator Control Register" hexmask.byte 0x0 1.--7. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.byte 0x0 0. "HCSTP,HOCO Stop" "0: HOCO is operating.,1: HOCO is stopped." group.byte 0x38++0x0 line.byte 0x0 "MOCOCR,Middle-Speed On-Chip Oscillator Control Register" hexmask.byte 0x0 1.--7. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.byte 0x0 0. "MCSTP,MOCO Stop" "0: MOCO is operating.,1: MOCO is stopped." rgroup.byte 0x3C++0x0 line.byte 0x0 "OSCSF,Oscillation Stabilization Flag Register" bitfld.byte 0x0 6.--7. "Reserved,These bits are read as 00." "0,1,2,3" bitfld.byte 0x0 5. "PLLSF,PLL Clock Oscillation Stabilization Flag" "0: The PLL clock is stopped or oscillation of the..,1: Oscillation of the PLL clock is stable so the.." newline bitfld.byte 0x0 4. "Reserved,This bit is read as 0." "0,1" bitfld.byte 0x0 3. "MOSCSF,Main Clock Oscillation Stabilization Flag" "0: MOSTP = 1 (stopping the main clock oscillator)..,1: Oscillation of the main clock is stable so the.." newline bitfld.byte 0x0 1.--2. "Reserved,These bits are read as 00." "0,1,2,3" bitfld.byte 0x0 0. "HOCOSF,HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF bit value after a reset is 1 when the OFS1.HOCOEN bit is 0. It is 0 when the OFS1.HOCOEN bit is 1." "0: The HOCO clock is stopped or oscillation of the..,1: Oscillation of the HOCO clock is stable so the.." group.byte 0x3E++0x3 line.byte 0x0 "CKOCR,Clock Out Control Register" bitfld.byte 0x0 7. "CKOEN,Clock out enable" "0: Clock Out disable,1: Clock Out enable" bitfld.byte 0x0 4.--6. "CKODIV,Clock out input frequency Division Select" "0: /1,1: /2,?,?,?,?,?,?" newline bitfld.byte 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 0.--2. "CKOSEL,Clock out source select" "0: Setting prohibited,1: MOCO,?,?,?,?,?,?" line.byte 0x1 "TRCKCR,Trace Clock Control Register" bitfld.byte 0x1 7. "TRCKEN,Trace Clock operating enable" "0: Operation disabled,1: Operation enabled." bitfld.byte 0x1 4.--6. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" newline hexmask.byte 0x1 0.--3. 1. "TRCK,Trace Clock operating frequency select" line.byte 0x2 "OSTDCR,Oscillation Stop Detection Control Register" bitfld.byte 0x2 7. "OSTDE,Oscillation Stop Detection Function Enable" "0: Oscillation stop detection function is disabled.,1: Oscillation stop detection function is enabled." hexmask.byte 0x2 1.--6. 1. "Reserved,These bits are read as 000000. The write value should be 000000." newline bitfld.byte 0x2 0. "OSTDIE,Oscillation Stop Detection Interrupt Enable" "0: The oscillation stop detection interrupt is..,1: The oscillation stop detection interrupt is.." line.byte 0x3 "OSTDSR,Oscillation Stop Detection Status Register" hexmask.byte 0x3 1.--7. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.byte 0x3 0. "OSTDF,Oscillation Stop Detection Flag" "0: The main clock oscillation stop has not been..,1: The main clock oscillation stop has been detected." group.byte 0x50++0x0 line.byte 0x0 "SLCDSCKCR,Segment LCD Source Clock Control Register" bitfld.byte 0x0 7. "LCDSCKEN,LCD Source Clock Out Enable" "0: LCD source clock out disabled,1: LCD source clock out enabled." hexmask.byte 0x0 3.--6. 1. "Reserved,These bits are read as 0000. The write value should be 0000." newline bitfld.byte 0x0 0.--2. "LCDSCKSEL,LCD Source Clock (LCDSRCCLK) Select" "0: Settings other than above are prohibited.,1: SOSC,?,?,?,?,?,?" group.byte 0x52++0x0 line.byte 0x0 "EBCKOCR,External Bus Clock Output Control Register" hexmask.byte 0x0 1.--7. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.byte 0x0 0. "EBCKOEN,EBCLK Pin Output Control" "0: BCLK pin output is disabled. (Fixed high),1: BCLK pin output is enabled" group.byte 0x61++0x1 line.byte 0x0 "MOCOUTCR,MOCO User Trimming Control Register" hexmask.byte 0x0 0.--7. 1. "MOCOUTRM,MOCO User Trimming 1000_0000 : -128 1000_0001 : -127 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : +126 0111_1111 : +127These bits are added to original MOCO.." line.byte 0x1 "HOCOUTCR,HOCO User Trimming Control Register" hexmask.byte 0x1 0.--7. 1. "HOCOUTRM,HOCO User Trimming 1000_0000 : -128 1000_0001 : -127 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : +126 0111_1111 : +127These bits are added to original HOCO.." group.byte 0xA2++0x0 line.byte 0x0 "MOSCWTCR,Main Clock Oscillator Wait Control Register" hexmask.byte 0x0 4.--7. 1. "Reserved,These bits are read as 0000. The write value should be 0000." hexmask.byte 0x0 0.--3. 1. "MSTS,Main clock oscillator wait time setting" group.byte 0xA5++0x0 line.byte 0x0 "HOCOWTCR,High-Speed On-Chip Oscillator Wait Control Register" hexmask.byte 0x0 3.--7. 1. "Reserved,These bits are read as 00000. The write value should be 00000." bitfld.byte 0x0 0.--2. "HSTS,HOCO wait time setting" "0: Setting prohibited,?,?,?,?,?,?,?" group.byte 0xD0++0x0 line.byte 0x0 "USBCKCR,USB Clock Control register" hexmask.byte 0x0 1.--7. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.byte 0x0 0. "HSTS,USB Clock Source Select" "0: PLL(Value after reset),1: HOCO" group.byte 0x413++0x0 line.byte 0x0 "MOMCR,Main Clock Oscillator Mode Oscillation Control Register" bitfld.byte 0x0 7. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 6. "MOSEL,Main Clock Oscillator Switching" "0: Resonator,1: External clock input" newline bitfld.byte 0x0 4.--5. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.byte 0x0 3. "MODRV1,Main Clock Oscillator Drive Capability 1 Switching" "0: 10 MHz to 20 MHz,1: 1 MHz to 10 MHz." newline bitfld.byte 0x0 0.--2. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" group.byte 0x480++0x1 line.byte 0x0 "SOSCCR,Sub-Clock Oscillator Control Register" hexmask.byte 0x0 1.--7. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.byte 0x0 0. "SOSTP,Sub-Clock Oscillator Stop" "0: Sub-clock oscillator is operating.,1: Sub-clock oscillator is stopped." line.byte 0x1 "SOMCR,Sub Clock Oscillator Mode Control Register" hexmask.byte 0x1 2.--7. 1. "Reserved,These bits are read as 000000. The write value should be 000000." bitfld.byte 0x1 0.--1. "SODRV,Sub-Clock Oscillator Drive Capability Switching" "0: Normal mode,1: Low power mode 1,?,?" group.byte 0x490++0x0 line.byte 0x0 "LOCOCR,Low-Speed On-Chip Oscillator Control Register" hexmask.byte 0x0 1.--7. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.byte 0x0 0. "LCSTP,LOCO Stop" "0: LOCO is operating.,1: LOCO is stopped." group.byte 0x492++0x0 line.byte 0x0 "LOCOUTCR,LOCO User Trimming Control Register" hexmask.byte 0x0 0.--7. 1. "LOCOUTRM,LOCO User Trimming 1000_0000 : -128 1000_0001 : -127 1000_0010 : -126 . . . 1111_1111 : -1 0000_0000 : Center Code 0000_0001 : +1 . . . 0111_1101 : +125 0111_1110 : +126 0111_1111 : +127These bits are added to original LOCO.." group.byte 0xC6++0x0 line.byte 0x0 "BKRACR,Backup Register Access Control Register" hexmask.byte 0x0 3.--7. 1. "Reserved,These bits are read as 00000. The write value should be 00000." bitfld.byte 0x0 0.--2. "BKRACS,Backup Register Access Control Register" "0: Setting prohibited,?,?,?,?,?,?,?" group.byte 0x417++0x1 line.byte 0x0 "LVCMPCR,Voltage Monitor Circuit Control Register" bitfld.byte 0x0 7. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 6. "LVD2E,Voltage Detection 2 Enable" "0: Voltage detection 2 circuit disabled,1: Voltage detection 2 circuit enabled" newline bitfld.byte 0x0 5. "LVD1E,Voltage Detection 1 Enable" "0: Voltage detection 1 circuit disabled,1: Voltage detection 1 circuit enabled" bitfld.byte 0x0 4. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.byte 0x0 2.--3. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.byte 0x0 0.--1. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" line.byte 0x1 "LVDLVLR,Voltage Detection Level Select Register" bitfld.byte 0x1 5.--7. "LVD2LVL,Voltage Detection 2 Level Select (Standard voltage during drop in voltage)" "0: Setting prohibited.,1: 4.14V (Vdet2_1),?,?,?,?,?,?" hexmask.byte 0x1 0.--4. 1. "LVD1LVL,Voltage Detection 1 Level Select (Standard voltage during drop in voltage)" repeat 2. (increment 0x0 0x1)(increment 0x0 0x1) group.byte ($2+0x41A)++0x0 line.byte 0x0 "LVD$1CR0,Voltage Monitor %s Circuit Control Register 0" bitfld.byte 0x0 7. "RN,Voltage Monitor Reset Negate Select" "0: Negation follows a stabilization time (tLVD)..,1: Negation follows a stabilization time (tLVD).." bitfld.byte 0x0 6. "RI,Voltage Monitor Circuit Mode Select" "0: Voltage Monitor interrupt during Vdet1 passage,1: Voltage Monitor reset enabled when the voltage.." newline bitfld.byte 0x0 3.--5. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.byte 0x0 2. "CMPE,Voltage Monitor Circuit Comparison Result Output Enable" "0: Voltage Monitor circuit comparison result output..,1: Voltage Monitor circuit comparison result output.." newline bitfld.byte 0x0 1. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.byte 0x0 0. "RIE,Voltage Monitor Interrupt/Reset Enable" "0: Disabled,1: Enabled" repeat.end repeat 2. (increment 0x0 0x1)(increment 0x0 0x2) group.byte ($2+0xE0)++0x0 line.byte 0x0 "LVD$1CR1,Voltage Monitor %s Circuit Control Register 1" hexmask.byte 0x0 3.--7. 1. "Reserved,These bits are read as 00000. The write value should be 00000." bitfld.byte 0x0 2. "IRQSEL,Voltage Monitor Interrupt Type Select" "0: Non-maskable interrupt,1: Maskable interrupt" newline bitfld.byte 0x0 0.--1. "IDTSEL,Voltage Monitor Interrupt Generation Condition Select" "0: When VCC>=Vdet (rise) is detected,1: When VCC= Vdet or MON bit is disabled" newline bitfld.byte 0x0 0. "DET,Voltage Monitor Voltage Change Detection Flag NOTE: Only 0 can be written to this bit. After writing 0 to this bit it takes 2 system clock cycles for the bit to be read as 0." "0: Not detected,1: Vdet1 passage detection" repeat.end tree.end tree "TSN (Temperature Sensor)" base ad:0x407EC000 rgroup.byte 0x228++0x1 line.byte 0x0 "TSCDRH,Temperature Sensor Calibration Data Register H" hexmask.byte 0x0 0.--7. 1. "TSCDRH,The calibration data stores the higher 8 bits of the convertedvalue." line.byte 0x1 "TSCDRL,Temperature Sensor Calibration Data Register L" hexmask.byte 0x1 0.--7. 1. "TSCDRL,The calibration data stores the lower 8 bits of the convertedvalue." tree.end tree "USBFS (USB 2.0 Full-Speed Module)" base ad:0x40090000 group.word 0x0++0x1 line.word 0x0 "SYSCFG,System Configuration Control Register" hexmask.word.byte 0x0 11.--15. 1. "Reserved,These bits are read as 00000. The write value should be 00000." bitfld.word 0x0 10. "SCKE,USB Clock Enable" "0: Clock supply to the USBFS stopped,1: Clock supply to the USBFS enabled." newline bitfld.word 0x0 9. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x0 8. "CNEN,CNEN Single End Receiver Enable" "0: Single end receiver disabled,1: Single end receiver enabled" newline bitfld.word 0x0 7. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x0 6. "DCFM,Controller Function Select" "0: Device controller selected,1: Host controller selected." newline bitfld.word 0x0 5. "DRPD,D+/D- Line Resistor Control" "0: Line pull-down disabled,1: Line pull-down enabled." bitfld.word 0x0 4. "DPRPU,D+ Line Resistor Control" "0: Line pull-down disabled,1: Line pull-down enabled." newline bitfld.word 0x0 3. "DMRPU,D- Line Resistor Control" "0: Line pull-up disabled,1: Line pull-up enabled." bitfld.word 0x0 0. "USBE,USB Operation Enable" "0: Disabled,1: Enabled." rgroup.word 0x4++0x1 line.word 0x0 "SYSSTS0,System Configuration Status Register 0" bitfld.word 0x0 14.--15. "OVCMON,External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe OCVMON[1] bit indicates the status of the USBHS_OVRCURA pin. The OCVMON[0] bit indicates the status of the USBHS_OVRCURB pin." "0,1,2,3" hexmask.word.byte 0x0 7.--13. 1. "Reserved,These bits are read as 0000000." newline bitfld.word 0x0 6. "HTACT,USB Host Sequencer Status Monitor" "0: Host sequencer completely stopped,1: Host sequencer not completely stopped." bitfld.word 0x0 3.--5. "Reserved,These bits are read as 000." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 2. "IDMON,External ID0 Input Pin Monitor" "0: USB0_ID pin is low,1: USB0_ID pin is high" bitfld.word 0x0 0.--1. "LNST,USB Data Line Status Monitor" "0: SE0,1: K-State (FS) / J-State(LS),?,?" group.word 0x8++0x1 line.word 0x0 "DVSTCTR0,Device State Control Register 0" hexmask.word.byte 0x0 12.--15. 1. "Reserved,These bits are read as 0000. The write value should be 0000." bitfld.word 0x0 11. "HNPBTOA,Host Negotiation Protocol (HNP) Control This bit is used when switching from device B to device A while in OTG mode. If the HNPBTOA bit is 1 the internal function control keeps the suspended state until the HNP processing ends even though.." "0: Normal Operation,1: Switching from device B to device A is enabled" newline bitfld.word 0x0 10. "EXICEN,USB_EXICEN Output Pin Control" "0: External USB_EXICEN pin outputs low,1: External USB_EXICEN pin outputs high" bitfld.word 0x0 9. "VBUSEN,USB_VBUSEN Output Pin Control" "0: External USB_VBUSEN pin outputs low,1: External USB_VBUSEN pin outputs high" newline bitfld.word 0x0 8. "WKUP,Wakeup Output" "0: Remote wakeup signal is not output.,1: Remote wakeup signal is output." bitfld.word 0x0 7. "RWUPE,Wakeup Detection Enable" "0: Downstream port wakeup is disabled.,1: Downstream port wakeup is enabled." newline bitfld.word 0x0 6. "USBRST,USB Bus Reset Output" "0: USB bus reset signal is not output.,1: USB bus reset signal is output." bitfld.word 0x0 5. "RESUME,Resume Output" "0: Resume signal is not output.,1: Resume signal is output." newline bitfld.word 0x0 4. "UACT,USB Bus Enable" "0: Downstream port is disabled (SOF transmission is..,1: Downstream port is enabled (SOF transmission is.." bitfld.word 0x0 3. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline rbitfld.word 0x0 0.--2. "RHST,USB Bus Reset Status" "0: USB bus reset in progress(When the host..,1: Low-speed connection(When the host controller is..,?,?,?,?,?,?" group.word 0x14++0x1 line.word 0x0 "CFIFO,CFIFO Port Register" hexmask.word 0x0 0.--15. 1. "FIFOPORT,FIFO PortRead receive data from the FIFO buffer or write transmit data to the FIFO buffer by accessing these bits." group.byte 0x14++0x0 line.byte 0x0 "CFIFOL,CFIFO Port Register L" group.word 0x18++0x1 line.word 0x0 "D0FIFO,D0FIFO Port Register" hexmask.word 0x0 0.--15. 1. "FIFOPORT,FIFO PortRead receive data from the FIFO buffer or write transmit data to the FIFO buffer by accessing these bits." group.byte 0x18++0x0 line.byte 0x0 "D0FIFOL,D0FIFO Port Register L" group.word 0x1C++0x1 line.word 0x0 "D1FIFO,D1FIFO Port Register" hexmask.word 0x0 0.--15. 1. "FIFOPORT,FIFO PortRead receive data from the FIFO buffer or write transmit data to the FIFO buffer by accessing these bits." group.byte 0x1C++0x0 line.byte 0x0 "D1FIFOL,D1FIFO Port Register L" group.word 0x20++0x3 line.word 0x0 "CFIFOSEL,CFIFO Port Select Register" bitfld.word 0x0 15. "RCNT,Read Count Mode" "0: The DTLN[8:0] bits (CFIFOCRT.DTLN[8:0]..,1: The DTLN[8:0] bits are decremented each time the.." bitfld.word 0x0 14. "REW,Buffer Pointer Rewind" "0: The buffer pointer is not rewound.,1: The buffer pointer is rewound." newline bitfld.word 0x0 11.--13. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.word 0x0 10. "MBW,CFIFO Port Access Bit Width" "0: 8-bit width,1: 16-bit width" newline bitfld.word 0x0 9. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x0 8. "BIGEND,CFIFO Port Endian Control" "0: Little endian,1: Big endian" newline bitfld.word 0x0 6.--7. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.word 0x0 5. "ISEL,CFIFO Port Access Direction When DCP is Selected" "0: Reading from the buffer memory is selected,1: Writing to the buffer memory is selected" newline bitfld.word 0x0 4. "Reserved,This bit is read as 0. The write value should be 0." "0,1" hexmask.word.byte 0x0 0.--3. 1. "CURPIPE,CFIFO Port Access Pipe Specification" line.word 0x2 "CFIFOCTR,CFIFO Port Control Register" bitfld.word 0x2 15. "BVAL,Buffer Memory Valid Flag" "0: Invalid,1: Writing ended" bitfld.word 0x2 14. "BCLR,CPU Buffer ClearNote: Only 0 can be read." "0: Does not operate,1: FIFO buffer cleared on the CPU side." newline rbitfld.word 0x2 13. "FRDY,FIFO Port Ready" "0: FIFO port access is disabled.,1: FIFO port access is enabled." hexmask.word.byte 0x2 9.--12. 1. "Reserved,These bits are read as 0000. The write value should be 0000." newline hexmask.word 0x2 0.--8. 1. "DTLN,Receive Data LengthIndicates the length of the receive data." group.word 0x28++0xB line.word 0x0 "D0FIFOSEL,D0FIFO Port Select Register" bitfld.word 0x0 15. "RCNT,Read Count Mode" "0: The DTLN[8:0] bits (CFIFOCRT.DTLN[8:0]..,1: The DTLN[8:0] bits are decremented each time the.." bitfld.word 0x0 14. "REW,Buffer Pointer RewindNote: Only 0 can be read." "0: The buffer pointer is not rewound.,1: The buffer pointer is rewound." newline bitfld.word 0x0 13. "DCLRM,Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read" "0: Auto buffer clear mode is disabled.,1: Auto buffer clear mode is enabled." bitfld.word 0x0 12. "DREQE,DMA/DTC Transfer Request Enable" "0: DMA/DTC transfer request is disabled.,1: DMA/DTC transfer request is enabled." newline bitfld.word 0x0 11. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x0 10. "MBW,FIFO Port Access Bit Width" "0: 8-bit width,1: 16-bit width" newline bitfld.word 0x0 9. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x0 8. "BIGEND,FIFO Port Endian Control" "0: Little endian,1: Big endian" newline hexmask.word.byte 0x0 4.--7. 1. "Reserved,These bits are read as 0000. The write value should be 0000." hexmask.word.byte 0x0 0.--3. 1. "CURPIPE,FIFO Port Access Pipe Specification" line.word 0x2 "D0FIFOCTR,D0FIFO Port Control Register" bitfld.word 0x2 15. "BVAL,Buffer Memory Valid Flag" "0: Invalid,1: Writing ended" bitfld.word 0x2 14. "BCLR,CPU Buffer ClearNote: Only 0 can be read." "0: Does not operate,1: FIFO buffer cleared on the CPU side." newline rbitfld.word 0x2 13. "FRDY,FIFO Port Ready" "0: FIFO port access is disabled.,1: FIFO port access is enabled." hexmask.word.byte 0x2 9.--12. 1. "Reserved,These bits are read as 0000. The write value should be 0000." newline hexmask.word 0x2 0.--8. 1. "DTLN,Receive Data LengthIndicates the length of the receive data." line.word 0x4 "D1FIFOSEL,D1FIFO Port Select Register" bitfld.word 0x4 15. "RCNT,Read Count Mode" "0: The DTLN[8:0] bits (CFIFOCRT.DTLN[8:0]..,1: The DTLN[8:0] bits are decremented each time the.." bitfld.word 0x4 14. "REW,Buffer Pointer Rewind" "0: The buffer pointer is not rewound.,1: The buffer pointer is rewound." newline bitfld.word 0x4 13. "DCLRM,Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read" "0: Auto buffer clear mode is disabled.,1: Auto buffer clear mode is enabled." bitfld.word 0x4 12. "DREQE,DMA/DTC Transfer Request Enable" "0: DMA/DTC transfer request is disabled.,1: DMA/DTC transfer request is enabled." newline bitfld.word 0x4 11. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x4 10. "MBW,FIFO Port Access Bit Width" "0: 8-bit width,1: 16-bit width" newline bitfld.word 0x4 9. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x4 8. "BIGEND,FIFO Port Endian Control" "0: Little endian,1: Big endian" newline hexmask.word.byte 0x4 4.--7. 1. "Reserved,These bits are read as 0000. The write value should be 0000." hexmask.word.byte 0x4 0.--3. 1. "CURPIPE,FIFO Port Access Pipe Specification" line.word 0x6 "D1FIFOCTR,D1FIFO Port Control Register" bitfld.word 0x6 15. "BVAL,Buffer Memory Valid Flag" "0: Invalid,1: Writing ended" bitfld.word 0x6 14. "BCLR,CPU Buffer ClearNote: Only 0 can be read." "0: Does not operate,1: FIFO buffer cleared on the CPU side." newline rbitfld.word 0x6 13. "FRDY,FIFO Port Ready" "0: FIFO port access is disabled.,1: FIFO port access is enabled." hexmask.word.byte 0x6 9.--12. 1. "Reserved,These bits are read as 0000. The write value should be 0000." newline hexmask.word 0x6 0.--8. 1. "DTLN,Receive Data LengthIndicates the length of the receive data." line.word 0x8 "INTENB0,Interrupt Enable Register 0" bitfld.word 0x8 15. "VBSE,VBUS Interrupt Enable" "0: Interrupt output disabled,1: Interrupt output enabled" bitfld.word 0x8 14. "RSME,Resume Interrupt Enable" "0: Interrupt output disabled,1: Interrupt output enabled" newline bitfld.word 0x8 13. "SOFE,Frame Number Update Interrupt Enable" "0: Interrupt output disabled,1: Interrupt output enabled" bitfld.word 0x8 12. "DVSE,Device State Transition Interrupt Enable" "0: Interrupt output disabled,1: Interrupt output enabled" newline bitfld.word 0x8 11. "CTRE,Control Transfer Stage Transition Interrupt Enable" "0: Interrupt output disabled,1: Interrupt output enabled" bitfld.word 0x8 10. "BEMPE,Buffer Empty Interrupt Enable" "0: Interrupt output disabled,1: Interrupt output enabled" newline bitfld.word 0x8 9. "NRDYE,Buffer Not Ready Response Interrupt Enable" "0: Interrupt output disabled,1: Interrupt output enabled" bitfld.word 0x8 8. "BRDYE,Buffer Ready Interrupt Enable" "0: Interrupt output disabled,1: Interrupt output enabled" newline hexmask.word.byte 0x8 0.--7. 1. "Reserved,These bits are read as 00000000. The write value should be 00000000." line.word 0xA "INTENB1,Interrupt Enable Register 1" bitfld.word 0xA 15. "OVRCRE,Overcurrent Input Change Interrupt Enable" "0: Interrupt output disabled,1: Interrupt output enabled" bitfld.word 0xA 14. "BCHGE,USB Bus Change Interrupt Enable" "0: Interrupt output disabled,1: Interrupt output enabled" newline bitfld.word 0xA 13. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0xA 12. "DTCHE,Disconnection Detection Interrupt Enable" "0: Interrupt output disabled,1: Interrupt output enabled" newline bitfld.word 0xA 11. "ATTCHE,Connection Detection Interrupt Enable" "0: Interrupt output disabled,1: Interrupt output enabled" hexmask.word.byte 0xA 7.--10. 1. "Reserved,These bits are read as 0000. The write value should be 0000." newline bitfld.word 0xA 6. "EOFERRE,EOF Error Detection Interrupt Enable" "0: Interrupt output disabled,1: Interrupt output enabled" bitfld.word 0xA 5. "SIGNE,Setup Transaction Error Interrupt Enable" "0: Interrupt output disabled,1: Interrupt output enabled" newline bitfld.word 0xA 4. "SACKE,Setup Transaction Normal Response Interrupt Enable" "0: Interrupt output disabled,1: Interrupt output enabled" bitfld.word 0xA 1.--3. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" newline bitfld.word 0xA 0. "PDDETINTE0,PDDETINT0 Detection Interrupt Enable" "0: Interrupt output disabled,1: Interrupt output enabled" group.word 0x36++0x7 line.word 0x0 "BRDYENB,BRDY Interrupt Enable Register" hexmask.word.byte 0x0 10.--15. 1. "Reserved,These bits are read as 000000. The write value should be 000000." bitfld.word 0x0 9. "PIPE9BRDYE,BRDY Interrupt Enable for PIPE9" "0: Interrupt output disabled,1: Interrupt output enabled" newline bitfld.word 0x0 8. "PIPE8BRDYE,BRDY Interrupt Enable for PIPE8" "0: Interrupt output disabled,1: Interrupt output enabled" bitfld.word 0x0 7. "PIPE7BRDYE,BRDY Interrupt Enable for PIPE7" "0: Interrupt output disabled,1: Interrupt output enabled" newline bitfld.word 0x0 6. "PIPE6BRDYE,BRDY Interrupt Enable for PIPE6" "0: Interrupt output disabled,1: Interrupt output enabled" bitfld.word 0x0 5. "PIPE5BRDYE,BRDY Interrupt Enable for PIPE5" "0: Interrupt output disabled,1: Interrupt output enabled" newline bitfld.word 0x0 4. "PIPE4BRDYE,BRDY Interrupt Enable for PIPE4" "0: Interrupt output disabled,1: Interrupt output enabled" bitfld.word 0x0 3. "PIPE3BRDYE,BRDY Interrupt Enable for PIPE3" "0: Interrupt output disabled,1: Interrupt output enabled" newline bitfld.word 0x0 2. "PIPE2BRDYE,BRDY Interrupt Enable for PIPE2" "0: Interrupt output disabled,1: Interrupt output enabled" bitfld.word 0x0 1. "PIPE1BRDYE,BRDY Interrupt Enable for PIPE1" "0: Interrupt output disabled,1: Interrupt output enabled" newline bitfld.word 0x0 0. "PIPE0BRDYE,BRDY Interrupt Enable for PIPE0" "0: Interrupt output disabled,1: Interrupt output enabled" line.word 0x2 "NRDYENB,NRDY Interrupt Enable Register" hexmask.word.byte 0x2 10.--15. 1. "Reserved,These bits are read as 000000. The write value should be 000000." bitfld.word 0x2 9. "PIPE9NRDYE,NRDY Interrupt Enable for PIPE9" "0: Interrupt output disabled,1: Interrupt output enabled" newline bitfld.word 0x2 8. "PIPE8NRDYE,NRDY Interrupt Enable for PIPE8" "0: Interrupt output disabled,1: Interrupt output enabled" bitfld.word 0x2 7. "PIPE7NRDYE,NRDY Interrupt Enable for PIPE7" "0: Interrupt output disabled,1: Interrupt output enabled" newline bitfld.word 0x2 6. "PIPE6NRDYE,NRDY Interrupt Enable for PIPE6" "0: Interrupt output disabled,1: Interrupt output enabled" bitfld.word 0x2 5. "PIPE5NRDYE,NRDY Interrupt Enable for PIPE5" "0: Interrupt output disabled,1: Interrupt output enabled" newline bitfld.word 0x2 4. "PIPE4NRDYE,NRDY Interrupt Enable for PIPE4" "0: Interrupt output disabled,1: Interrupt output enabled" bitfld.word 0x2 3. "PIPE3NRDYE,NRDY Interrupt Enable for PIPE3" "0: Interrupt output disabled,1: Interrupt output enabled" newline bitfld.word 0x2 2. "PIPE2NRDYE,NRDY Interrupt Enable for PIPE2" "0: Interrupt output disabled,1: Interrupt output enabled" bitfld.word 0x2 1. "PIPE1NRDYE,NRDY Interrupt Enable for PIPE1" "0: Interrupt output disabled,1: Interrupt output enabled" newline bitfld.word 0x2 0. "PIPE0NRDYE,NRDY Interrupt Enable for PIPE0" "0: Interrupt output disabled,1: Interrupt output enabled" line.word 0x4 "BEMPENB,BEMP Interrupt Enable Register" hexmask.word.byte 0x4 10.--15. 1. "Reserved,These bits are read as 000000. The write value should be 000000." bitfld.word 0x4 9. "PIPE9BEMPE,BEMP Interrupt Enable for PIPE9" "0: Interrupt output disabled,1: Interrupt output enabled" newline bitfld.word 0x4 8. "PIPE8BEMPE,BEMP Interrupt Enable for PIPE8" "0: Interrupt output disabled,1: Interrupt output enabled" bitfld.word 0x4 7. "PIPE7BEMPE,BEMP Interrupt Enable for PIPE7" "0: Interrupt output disabled,1: Interrupt output enabled" newline bitfld.word 0x4 6. "PIPE6BEMPE,BEMP Interrupt Enable for PIPE6" "0: Interrupt output disabled,1: Interrupt output enabled" bitfld.word 0x4 5. "PIPE5BEMPE,BEMP Interrupt Enable for PIPE5" "0: Interrupt output disabled,1: Interrupt output enabled" newline bitfld.word 0x4 4. "PIPE4BEMPE,BEMP Interrupt Enable for PIPE4" "0: Interrupt output disabled,1: Interrupt output enabled" bitfld.word 0x4 3. "PIPE3BEMPE,BEMP Interrupt Enable for PIPE3" "0: Interrupt output disabled,1: Interrupt output enabled" newline bitfld.word 0x4 2. "PIPE2BEMPE,BEMP Interrupt Enable for PIPE2" "0: Interrupt output disabled,1: Interrupt output enabled" bitfld.word 0x4 1. "PIPE1BEMPE,BEMP Interrupt Enable for PIPE1" "0: Interrupt output disabled,1: Interrupt output enabled" newline bitfld.word 0x4 0. "PIPE0BEMPE,BEMP Interrupt Enable for PIPE0" "0: Interrupt output disabled,1: Interrupt output enabled" line.word 0x6 "SOFCFG,SOF Output Configuration Register" hexmask.word.byte 0x6 9.--15. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." bitfld.word 0x6 8. "TRNENSEL,Transaction-Enabled Time Select" "0: Not low-speed communication,1: Low-speed communication." newline bitfld.word 0x6 7. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x6 6. "BRDYM,BRDY Interrupt Status Clear Timing" "0: BRDY flag cleared by software,1: BRDY flag cleared by the USBFS through a data.." newline bitfld.word 0x6 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" rbitfld.word 0x6 4. "EDGESTS,Edge Interrupt Output Status Monitor" "0: before stopping the clock supply to the USB module,1: the edge interrupt output signal is in the.." newline hexmask.word.byte 0x6 0.--3. 1. "Reserved,These bits are read as 0000. The write value should be 0000." group.word 0x40++0x3 line.word 0x0 "INTSTS0,Interrupt Status Register 0" bitfld.word 0x0 15. "VBINT,VBUS Interrupt Status" "0: VBUS interrupts are not generated.,1: VBUS interrupts are generated." bitfld.word 0x0 14. "RESM,Resume Interrupt Status" "0: Resume interrupts are not generated.,1: Resume interrupts are generated." newline bitfld.word 0x0 13. "SOFR,Frame Number Refresh Interrupt Status" "0: SOF interrupts are not generated.,1: SOF interrupts are generated." bitfld.word 0x0 12. "DVST,Device State Transition Interrupt Status" "0: Device state transition interrupts are not..,1: Device state transition interrupts are generated." newline bitfld.word 0x0 11. "CTRT,Control Transfer Stage Transition Interrupt Status" "0: Control transfer stage transition interrupts are..,1: Control transfer stage transition interrupts are.." rbitfld.word 0x0 10. "BEMP,Buffer Empty Interrupt Status" "0: BEMP interrupts are not generated.,1: BEMP interrupts are generated." newline rbitfld.word 0x0 9. "NRDY,Buffer Not Ready Interrupt Status" "0: NRDY interrupts are not generated.,1: NRDY interrupts are generated." rbitfld.word 0x0 8. "BRDY,Buffer Ready Interrupt Status" "0: BRDY interrupts are not generated.,1: BRDY interrupts are generated." newline rbitfld.word 0x0 7. "VBSTS,VBUS Input Status" "0: USB_VBUS pin is low.,1: USB_VBUS pin is high." rbitfld.word 0x0 4.--6. "DVSQ,Device State" "0: Suspended state,1: Default state,?,?,?,?,?,?" newline bitfld.word 0x0 3. "VALID,USB Request Reception" "0: Setup packet is not received,1: Setup packet is received" rbitfld.word 0x0 0.--2. "CTSQ,Control Transfer Stage" "0: Setting prohibited,1: Control read data stage,?,?,?,?,?,?" line.word 0x2 "INTSTS1,Interrupt Status Register 1" bitfld.word 0x2 15. "OVRCR,Overcurrent Input Change Interrupt Status" "0: OVRCR interrupts are not generated.,1: OVRCR interrupts are generated." bitfld.word 0x2 14. "BCHG,USB Bus Change Interrupt Status" "0: BCHG interrupts are not generated.,1: BCHG interrupts are generated." newline bitfld.word 0x2 13. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x2 12. "DTCH,USB Disconnection Detection Interrupt Status" "0: DTCH interrupts are not generated.,1: DTCH interrupts are generated." newline bitfld.word 0x2 11. "ATTCH,ATTCH Interrupt Status" "0: ATTCH interrupts are not generated.,1: ATTCH interrupts are generated." hexmask.word.byte 0x2 7.--10. 1. "Reserved,These bits are read as 0000. The write value should be 0000." newline bitfld.word 0x2 6. "EOFERR,EOF Error Detection Interrupt Status" "0: EOFERR interrupts are not generated.,1: EOFERR interrupts are generated." bitfld.word 0x2 5. "SIGN,Setup Transaction Error Interrupt Status" "0: SIGN interrupts are not generated.,1: SIGN interrupts are generated." newline bitfld.word 0x2 4. "SACK,Setup Transaction Normal Response Interrupt Status" "0: SACK interrupts are not generated.,1: SACK interrupts are generated." bitfld.word 0x2 1.--3. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" newline bitfld.word 0x2 0. "PDDETINT0,PDDET0 Detection Interrupt Status" "0: PDDET0 detection interrupts are not generated.,1: PDDET0 detection interrupts are generated." group.word 0x46++0x7 line.word 0x0 "BRDYSTS,BRDY Interrupt Status Register" hexmask.word.byte 0x0 10.--15. 1. "Reserved,These bits are read as 000000. The write value should be 000000." bitfld.word 0x0 9. "PIPE9BRDY,BRDY Interrupt Status for PIPE9" "0: Interrupts are not generated.,1: Interrupts are generated." newline bitfld.word 0x0 8. "PIPE8BRDY,BRDY Interrupt Status for PIPE8" "0: Interrupts are not generated.,1: Interrupts are generated." bitfld.word 0x0 7. "PIPE7BRDY,BRDY Interrupt Status for PIPE7" "0: Interrupts are not generated.,1: Interrupts are generated." newline bitfld.word 0x0 6. "PIPE6BRDY,BRDY Interrupt Status for PIPE6" "0: Interrupts are not generated.,1: Interrupts are generated." bitfld.word 0x0 5. "PIPE5BRDY,BRDY Interrupt Status for PIPE5" "0: Interrupts are not generated.,1: Interrupts are generated." newline bitfld.word 0x0 4. "PIPE4BRDY,BRDY Interrupt Status for PIPE4" "0: Interrupts are not generated.,1: Interrupts are generated." bitfld.word 0x0 3. "PIPE3BRDY,BRDY Interrupt Status for PIPE3" "0: Interrupts are not generated.,1: Interrupts are generated." newline bitfld.word 0x0 2. "PIPE2BRDY,BRDY Interrupt Status for PIPE2" "0: Interrupts are not generated.,1: Interrupts are generated." bitfld.word 0x0 1. "PIPE1BRDY,BRDY Interrupt Status for PIPE1" "0: Interrupts are not generated.,1: Interrupts are generated." newline bitfld.word 0x0 0. "PIPE0BRDY,BRDY Interrupt Status for PIPE0" "0: Interrupts are not generated.,1: Interrupts are generated." line.word 0x2 "NRDYSTS,NRDY Interrupt Status Register" hexmask.word.byte 0x2 10.--15. 1. "Reserved,These bits are read as 000000. The write value should be 000000." bitfld.word 0x2 9. "PIPE9NRDY,NRDY Interrupt Status for PIPE9" "0: Interrupts are not generated.,1: Interrupts are generated." newline bitfld.word 0x2 8. "PIPE8NRDY,NRDY Interrupt Status for PIPE8" "0: Interrupts are not generated.,1: Interrupts are generated." bitfld.word 0x2 7. "PIPE7NRDY,NRDY Interrupt Status for PIPE7" "0: Interrupts are not generated.,1: Interrupts are generated." newline bitfld.word 0x2 6. "PIPE6NRDY,NRDY Interrupt Status for PIPE6" "0: Interrupts are not generated.,1: Interrupts are generated." bitfld.word 0x2 5. "PIPE5NRDY,NRDY Interrupt Status for PIPE5" "0: Interrupts are not generated.,1: Interrupts are generated." newline bitfld.word 0x2 4. "PIPE4NRDY,NRDY Interrupt Status for PIPE4" "0: Interrupts are not generated.,1: Interrupts are generated." bitfld.word 0x2 3. "PIPE3NRDY,NRDY Interrupt Status for PIPE3" "0: Interrupts are not generated.,1: Interrupts are generated." newline bitfld.word 0x2 2. "PIPE2NRDY,NRDY Interrupt Status for PIPE2" "0: Interrupts are not generated.,1: Interrupts are generated." bitfld.word 0x2 1. "PIPE1NRDY,NRDY Interrupt Status for PIPE1" "0: Interrupts are not generated.,1: Interrupts are generated." newline bitfld.word 0x2 0. "PIPE0NRDY,NRDY Interrupt Status for PIPE0" "0: Interrupts are not generated.,1: Interrupts are generated." line.word 0x4 "BEMPSTS,BEMP Interrupt Status Register" hexmask.word.byte 0x4 10.--15. 1. "Reserved,These bits are read as 000000. The write value should be 000000." bitfld.word 0x4 9. "PIPE9BEMP,BEMP Interrupt Status for PIPE9" "0: Interrupts are not generated.,1: Interrupts are generated." newline bitfld.word 0x4 8. "PIPE8BEMP,BEMP Interrupt Status for PIPE8" "0: Interrupts are not generated.,1: Interrupts are generated." bitfld.word 0x4 7. "PIPE7BEMP,BEMP Interrupt Status for PIPE7" "0: Interrupts are not generated.,1: Interrupts are generated." newline bitfld.word 0x4 6. "PIPE6BEMP,BEMP Interrupt Status for PIPE6" "0: Interrupts are not generated.,1: Interrupts are generated." bitfld.word 0x4 5. "PIPE5BEMP,BEMP Interrupt Status for PIPE5" "0: Interrupts are not generated.,1: Interrupts are generated." newline bitfld.word 0x4 4. "PIPE4BEMP,BEMP Interrupt Status for PIPE4" "0: Interrupts are not generated.,1: Interrupts are generated." bitfld.word 0x4 3. "PIPE3BEMP,BEMP Interrupt Status for PIPE3" "0: Interrupts are not generated.,1: Interrupts are generated." newline bitfld.word 0x4 2. "PIPE2BEMP,BEMP Interrupt Status for PIPE2" "0: Interrupts are not generated.,1: Interrupts are generated." bitfld.word 0x4 1. "PIPE1BEMP,BEMP Interrupt Status for PIPE1" "0: Interrupts are not generated.,1: Interrupts are generated." newline bitfld.word 0x4 0. "PIPE0BEMP,BEMP Interrupt Status for PIPE0" "0: Interrupts are not generated.,1: Interrupts are generated." line.word 0x6 "FRMNUM,Frame Number Register" bitfld.word 0x6 15. "OVRN,Overrun/Underrun Detection Status" "0: No error,1: An error occurred" bitfld.word 0x6 14. "CRCE,Receive Data Error" "0: No error,1: An error occurred" newline bitfld.word 0x6 11.--13. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" hexmask.word 0x6 0.--10. 1. "FRNM,Frame NumberLatest frame number" group.word 0x54++0xD line.word 0x0 "USBREQ,USB Request Type Register" hexmask.word.byte 0x0 8.--15. 1. "BREQUEST,RequestThese bits store the USB request bRequest value." hexmask.word.byte 0x0 0.--7. 1. "BMREQUESTTYPE,Request TypeThese bits store the USB request bmRequestType value." line.word 0x2 "USBVAL,USB Request Value Register" hexmask.word 0x2 0.--15. 1. "WVALUE,ValueThese bits store the USB request Value value." line.word 0x4 "USBINDX,USB Request Index Register" hexmask.word 0x4 0.--15. 1. "WINDEX,IndexThese bits store the USB request wIndex value." line.word 0x6 "USBLENG,USB Request Length Register" hexmask.word 0x6 0.--15. 1. "WLENGTH,LengthThese bits store the USB request wLength value." line.word 0x8 "DCPCFG,DCP Configuration Register" hexmask.word.byte 0x8 8.--15. 1. "Reserved,These bits are read as 00000000. The write value should be 00000000." bitfld.word 0x8 7. "SHTNAK,Pipe Disabled at End of Transfer" "0: Pipe continued at the end of transfer,1: Pipe disabled at the end of transfer" newline bitfld.word 0x8 5.--6. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.word 0x8 4. "DIR,Transfer Direction" "0: Data receiving direction,1: Data transmitting direction" newline hexmask.word.byte 0x8 0.--3. 1. "Reserved,These bits are read as 0000. The write value should be 0000." line.word 0xA "DCPMAXP,DCP Maximum Packet Size Register" hexmask.word.byte 0xA 12.--15. 1. "DEVSEL,Device Select" hexmask.word.byte 0xA 7.--11. 1. "Reserved,These bits are read as 00000. The write value should be 00000." newline hexmask.word.byte 0xA 0.--6. 1. "MXPS,Maximum Packet SizeThese bits set the maximum amount of data (maximum packet size) in payloads for the DCP." line.word 0xC "DCPCTR,DCP Control Register" rbitfld.word 0xC 15. "BSTS,Buffer Status" "0: Buffer access is disabled.,1: Buffer access is enabled." bitfld.word 0xC 14. "SUREQ,Setup Token Transmission" "0: Invalid,1: Transmits the setup packet." newline bitfld.word 0xC 12.--13. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.word 0xC 11. "SUREQCLR,SUREQ Bit Clear" "0: Invalid,1: Clears the SUREQ bit to 0." newline bitfld.word 0xC 9.--10. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.word 0xC 8. "SQCLR,Sequence Toggle Bit Clear" "0: Invalid,1: Specifies DATA0." newline bitfld.word 0xC 7. "SQSET,Sequence Toggle Bit Set" "0: Invalid,1: Specifies DATA1." rbitfld.word 0xC 6. "SQMON,Sequence Toggle Bit Monitor" "0: DATA0,1: DATA1" newline rbitfld.word 0xC 5. "PBUSY,Pipe Busy" "0: DCP is not used for the transaction.,1: DCP is used for the transaction." bitfld.word 0xC 3.--4. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" newline bitfld.word 0xC 2. "CCPL,Control Transfer End Enable" "0: Invalid,1: Completion of control transfer is enabled." bitfld.word 0xC 0.--1. "PID,Response PID" "0: NAK response,1: BUF response (depending on the buffer state),?,?" group.word 0x64++0x1 line.word 0x0 "PIPESEL,Pipe Window Select Register" hexmask.word 0x0 4.--15. 1. "Reserved,These bits are read as 000000000000. The write value should be 000000000000." hexmask.word.byte 0x0 0.--3. 1. "PIPESEL,Pipe Window Select" group.word 0x68++0x1 line.word 0x0 "PIPECFG,Pipe Configuration Register" bitfld.word 0x0 14.--15. "TYPE,Transfer Type" "0: Pipe not used,1: Bulk transfer(PIPE1 and PIPE5) /Setting..,?,?" bitfld.word 0x0 11.--13. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10. "BFRE,BRDY Interrupt Operation Specification" "0: BRDY interrupt upon transmitting or receiving data,1: BRDY interrupt upon completion of reading data" bitfld.word 0x0 9. "DBLB,Double Buffer Mode" "0: Single buffer,1: Double buffer" newline bitfld.word 0x0 8. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x0 7. "SHTNAK,Pipe Disabled at End of Transfer" "0: Continue pipe operation after transfer ends,1: Disable pipe operation after transfer ends." newline bitfld.word 0x0 6. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x0 5. "Reserved,This bit is read as 0. The write value should be 0." "0,1" newline bitfld.word 0x0 4. "DIR,Transfer Direction" "0: Receiving direction,1: Transmitting direction" hexmask.word.byte 0x0 0.--3. 1. "EPNUM,Endpoint NumberThese bits specify the endpoint number for the selected pipe.Setting 0000b means unused pipe." group.word 0x6C++0x3 line.word 0x0 "PIPEMAXP,Pipe Maximum Packet Size Register" hexmask.word.byte 0x0 12.--15. 1. "DEVSEL,Device Select" bitfld.word 0x0 9.--11. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 0.--8. 1. "MXPS,Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to 256 bytes (100h)PIPE3 to PIPE5: 8 bytes (008h) 16 bytes (010h) 32 bytes (020h) 64 bytes (040h) (Bits [8:7] and [2:0] are not provided.)PIPE6 to PIPE9: 1 byte (001h) to 64 bytes (040h).." line.word 0x2 "PIPEPERI,Pipe Cycle Control Register" bitfld.word 0x2 13.--15. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.word 0x2 12. "IFIS,Isochronous IN Buffer Flush" "0: The buffer is not flushed.,1: The buffer is flushed." newline hexmask.word 0x2 3.--11. 1. "Reserved,These bits are read as 000000000. The write value should be 000000000." bitfld.word 0x2 0.--2. "IITV,Interval Error Detection IntervalSpecifies the interval error detection timing for the selected pipe in terms of frames which is expressed as nth power of 2." "0,1,2,3,4,5,6,7" repeat 5. (increment 0x0 0x1)(increment 0x0 0x2) group.word ($2+0x70)++0x1 line.word 0x0 "PIPE$1CTR,Pipe %s Control Register" rbitfld.word 0x0 15. "BSTS,Buffer Status" "0: Buffer access by the CPU is disabled.,1: Buffer access by the CPU is enabled." rbitfld.word 0x0 14. "INBUFM,Transmit Buffer Monitor" "0: No data to be transmitted is in the FIFO buffer,1: Data to be transmitted is in the FIFO buffer" newline bitfld.word 0x0 11.--13. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" bitfld.word 0x0 10. "ATREPM,Auto Response Mode" "0: Auto response disabled.,1: Auto response enabled." newline bitfld.word 0x0 9. "ACLRM,Auto Buffer Clear Mode" "0: Disabled,1: Enabled (all buffers are initialized)" bitfld.word 0x0 8. "SQCLR,Sequence Toggle Bit Clear" "0: Write disabled,1: Specifies DATA0." newline bitfld.word 0x0 7. "SQSET,Sequence Toggle Bit Set" "0: Write disabled,1: Specifies DATA1." rbitfld.word 0x0 6. "SQMON,Sequence Toggle Bit Confirmation" "0: DATA0,1: DATA1" newline rbitfld.word 0x0 5. "PBUSY,Pipe Busy" "0: Pipe n not in use for the transaction,1: Pipe n in use for the transaction." bitfld.word 0x0 2.--4. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0.--1. "PID,Response PID" "0: NAK response,1: BUF response (depending on the buffer state),?,?" repeat.end repeat 4. (increment 0x0 0x1)(increment 0x0 0x2) group.word ($2+0x7A)++0x1 line.word 0x0 "PIPE$1CTR,Pipe %s Control Register" rbitfld.word 0x0 15. "BSTS,Buffer Status" "0: Buffer access is disabled.,1: Buffer access is enabled." hexmask.word.byte 0x0 10.--14. 1. "Reserved,These bits are read as 00000. The write value should be 00000." newline bitfld.word 0x0 9. "ACLRM,Auto Buffer Clear Mode" "0: Auto buffer clear mode is disabled.,1: Auto buffer clear mode is enabled (all buffers.." bitfld.word 0x0 8. "SQCLR,Sequence Toggle Bit Clear" "0: Invalid,1: Specifies DATA0." newline bitfld.word 0x0 7. "SQSET,Sequence Toggle Bit Set" "0: Invalid,1: Specifies DATA1." rbitfld.word 0x0 6. "SQMON,Sequence Toggle Bit Confirmation" "0: DATA0,1: DATA1" newline rbitfld.word 0x0 5. "PBUSY,Pipe Busy" "0: Pipe n not in use for the transaction,1: Pipe n in use for the transaction." bitfld.word 0x0 2.--4. "Reserved,These bits are read as 000. The write value should be 000." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0.--1. "PID,Response PID" "0: NAK response,1: BUF response (depending on the buffer state),?,?" repeat.end repeat 5. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x90)++0x1 line.word 0x0 "PIPE$1TRE,Pipe %s Transaction Counter Enable Register" hexmask.word.byte 0x0 10.--15. 1. "Reserved,These bits are read as 000000. The write value should be 000000." bitfld.word 0x0 9. "TRENB,Transaction Counter Enable" "0: Transaction counter is disabled.,1: Transaction counter is enabled." newline bitfld.word 0x0 8. "TRCLR,Transaction Counter Clear" "0: Invalid,1: The current counter value is cleared." hexmask.word.byte 0x0 0.--7. 1. "Reserved,These bits are read as 00000000. The write value should be 00000000." repeat.end repeat 5. (increment 0x0 0x1)(increment 0x0 0x4) group.word ($2+0x92)++0x1 line.word 0x0 "PIPE$1TRN,Pipe %s Transaction Counter Register" hexmask.word 0x0 0.--15. 1. "TRNCNT,Transaction Counter" repeat.end repeat 6. (increment 0x0 0x1)(increment 0x0 0x2) group.word ($2+0xD0)++0x1 line.word 0x0 "DEVADD$1,Device Address %s Configuration Register" hexmask.word.byte 0x0 8.--15. 1. "Reserved,These bits are read as 00000000. The write value should be 00000000." bitfld.word 0x0 6.--7. "USBSPD,Transfer Speed of Communication Target Device" "0: DEVADDn is not used,1: Low speed,?,?" newline hexmask.word.byte 0x0 0.--5. 1. "Reserved,These bits are read as 000000. The write value should be 000000." repeat.end group.word 0xCC++0x1 line.word 0x0 "USBMC,USB Module Control Register" hexmask.word.byte 0x0 8.--15. 1. "Reserved,These bits are read as 00000000. The write value should be 00000000." bitfld.word 0x0 7. "VDCEN,USB Regulator On/Off Control" "0: USB regulator off,1: USB regulator on" newline hexmask.word.byte 0x0 2.--6. 1. "Reserved,These bits are read as 00000. The write value should be 00000." bitfld.word 0x0 1. "Reserved,This bit is read as 1. The write value should be 1." "0,1" newline bitfld.word 0x0 0. "VDDUSBE,USB Reference Power Supply Circuit On/Off Control" "0: USB reference power supply circuit off,1: USB reference power supply circuit on" group.word 0xB0++0x1 line.word 0x0 "USBBCCTRL0,BC Control Register 0" hexmask.word.byte 0x0 10.--15. 1. "Reserved,These bits are read as 000000. The write value should be 000000." rbitfld.word 0x0 9. "PDDETSTS0,D+ Pin 0.6 V Input Detection Status" "0: Not detected,1: Detected" newline rbitfld.word 0x0 8. "CHGDETSTS0,D- Pin 0.6 V Input Detection Status" "0: Not detected,1: Detected" bitfld.word 0x0 7. "BATCHGE0,BC (Battery Charger) Function Ch0 General Enable Control" "0: Disabled,1: Enabled" newline bitfld.word 0x0 6. "Reserved,This bit is read as 0. The write value should be 0." "0,1" bitfld.word 0x0 5. "VDMSRCE0,D- Pin VDMSRC (0.6 V) Output Control" "0: Stop,1: 0.6V output" newline bitfld.word 0x0 4. "IDPSINKE0,D+ Pin 0.6 V Input Detection (Comparator and Sink) Control" "0: Detection off,1: Detection on ( Comparator and sink current on )" bitfld.word 0x0 3. "VDPSRCE0,D+ Pin VDPSRC (0.6 V) Output Control" "0: Stop,1: 0.6V output" newline bitfld.word 0x0 2. "IDMSINKE0,D- Pin 0.6 V Input Detection (Comparator and Sink) Control" "0: Detection off,1: Detection on ( Comparator and sink current on )" bitfld.word 0x0 1. "IDPSRCE0,D+ Pin IDPSRC Output Control" "0: Stop,1: 10uA output" newline bitfld.word 0x0 0. "RPDME0,D- Pin Pull-Down Control" "0: Pull-down off,1: Pull-down on" tree.end tree "WDT (Watchdog Timer)" base ad:0x40044200 group.byte 0x0++0x0 line.byte 0x0 "WDTRR,WDT Refresh Register" hexmask.byte 0x0 0.--7. 1. "WDTRR,WDTRR is an 8-bit register that refreshes the down-counter of the WDT." group.word 0x2++0x3 line.word 0x0 "WDTCR,WDT Control Register" bitfld.word 0x0 14.--15. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" bitfld.word 0x0 12.--13. "RPSS,Window Start Position Selection" "0: 25 percent,1: 50 percent,?,?" bitfld.word 0x0 10.--11. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" newline bitfld.word 0x0 8.--9. "RPES,Window End Position Selection" "0: 75 percent,1: 50 percent,?,?" hexmask.word.byte 0x0 4.--7. 1. "CKS,Clock Division Ratio Selection" bitfld.word 0x0 2.--3. "Reserved,These bits are read as 00. The write value should be 00." "0,1,2,3" newline bitfld.word 0x0 0.--1. "TOPS,Timeout Period Selection" "0: 1 024 cycles (03FFh),1: 4 096 cycles (0FFFh),?,?" line.word 0x2 "WDTSR,WDT Status Register" bitfld.word 0x2 15. "REFEF,Refresh Error Flag" "0: No refresh error occurred,1: Refresh error occurred" bitfld.word 0x2 14. "UNDFF,Underflow Flag" "0: No underflow occurred,1: Underflow occurred" hexmask.word 0x2 0.--13. 1. "CNTVAL,Down-Counter ValueValue counted by the down-counter" group.byte 0x6++0x0 line.byte 0x0 "WDTRCR,WDT Reset Control Register" bitfld.byte 0x0 7. "RSTIRQS,Reset Interrupt Request Selection" "0: Non-maskable interrupt request or interrupt..,1: Reset output is enabled." group.byte 0x8++0x0 line.byte 0x0 "WDTCSTPR,WDT Count Stop Control Register" bitfld.byte 0x0 7. "SLCSTP,Sleep-Mode Count Stop Control" "0: Count stop is disabled.,1: Count is stopped at a transition to sleep mode." hexmask.byte 0x0 0.--6. 1. "Reserved,These bits are read as 0000000. The write value should be 0000000." tree.end AUTOINDENT.OFF