; -------------------------------------------------------------------------------- ; @Title: PSoC 4200L On-Chip Peripherals ; @Props: Released ; @Author: KMB, AJK ; @Changelog: 2017-11-03 KMB ; @Manufacturer: CYPRESS - Cypress Semiconductor Corporation ; @Doc: 001-97952_PSoC_4200L_Family_PSoC_4_Architecture_Technical_Reference_Manual_TRM.pdf (Rev. *A) ; PSoC 4200L Family Psoc 4 Registers Technical Reference Manual (TRM).pdf (Rev. *B) ; PSoC_4_PSoC_4200L_Family_Datasheet.pdf (Rev. *E, 2016-05-23) ; @Core: Cortex-M0 ; @Chip: CY8C4246AZI-L423, CY8C4246AZI-L433, CY8C4246AZI-L435, CY8C4246AZI-L445, ; CY8C4246LTI-L445, CY8C4247AZI-L423, CY8C4247AZI-L433, CY8C4247AZI-L445, ; CY8C4247AZI-L475, CY8C4247AZI-L485, CY8C4247BZI-L479, CY8C4247BZI-L489, ; CY8C4247LTI-L445, CY8C4247LTI-L475, CY8C4247LTI-L485, CY8C4248AZI-L475, ; CY8C4248AZI-L485, CY8C4248BZI-L479, CY8C4248BZI-L489, CY8C4248LTI-L475, ; CY8C4248LTI-L485 ; @Copyright: (C) 1989-2017 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: perpsoc4200l.per 8451 2017-11-03 16:19:43Z askoncej $ config 16. 8. tree.close "Core Registers (Cortex-M0)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 0x8 if (CORENAME()=="CORTEXM1") group.long 0x10++0x0b line.long 0x00 "STCSR,SysTick Control and Status Register" bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1" bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock" textline " " bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick" bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled" line.long 0x04 "STRVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0" line.long 0x08 "STCVR,SysTick Current Value Register" hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter" else group.long 0x10++0x0b line.long 0x00 "STCSR,SysTick Control and Status Register" bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1" bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock" textline " " bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick" bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled" line.long 0x04 "STRVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0" line.long 0x08 "STCVR,SysTick Current Value Register" hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter" endif if (CORENAME()=="CORTEXM1") rgroup.long 0x1c++0x03 line.long 0x00 "STCR,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1" bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1" textline " " hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known" else rgroup.long 0x1c++0x03 line.long 0x00 "STCR,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" textline " " hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors" endif rgroup.long 0xd00++0x03 line.long 0x00 "CPUID,CPU ID Base Register" hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code" hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number" textline " " hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family" hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number" group.long 0xd04++0x03 line.long 0x00 "ICSR,Interrupt Control State Register" bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending" bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending" textline " " bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending" bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending" textline " " bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending" bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service" textline " " bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt" hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field" textline " " hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field" if (CORENAME()=="CORTEXM0+") group.long 0xd08++0x03 line.long 0x00 "VTOR,Vector Table Offset Register" hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address" else textline " " endif group.long 0xd0c++0x03 line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key" bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian" textline " " bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset" bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear" group.long 0xd10++0x03 line.long 0x00 "SCR,System Control Register" bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" textline " " bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" rgroup.long 0xd14++0x03 line.long 0x00 "CCR,Configuration and Control Register" bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned" bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped" group.long 0xd1c++0x0b line.long 0x00 "SHPR2,System Handler Priority Register 2" bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11" line.long 0x04 "SHPR3,System Handler Priority Register 3" bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11" bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11" line.long 0x08 "SHCSR,System Handler Control and State Register" bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending" if (CORENAME()=="CORTEXM0+") hgroup.long 0x08++0x03 hide.long 0x00 "ACTLR,Auxiliary Control Register" else textline " " endif else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller (NVIC)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. tree "Interrupt Enable Registers" group.long 0x100++0x03 line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" tree.end tree "Interrupt Pending Registers" group.long 0x200++0x03 line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" tree.end width 6. tree "Interrupt Priority Registers" group.long 0x400++0x1F line.long 0x00 "INT0,Interrupt Priority Register" bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3" bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3" bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3" bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3" line.long 0x04 "INT1,Interrupt Priority Register" bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3" bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3" bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3" bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3" line.long 0x08 "INT2,Interrupt Priority Register" bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3" bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3" bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3" bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3" line.long 0x0C "INT3,Interrupt Priority Register" bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3" bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3" bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3" bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3" line.long 0x10 "INT4,Interrupt Priority Register" bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3" bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3" bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3" bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3" line.long 0x14 "INT5,Interrupt Priority Register" bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3" bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3" bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3" bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3" line.long 0x18 "INT6,Interrupt Priority Register" bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3" bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3" bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3" bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3" line.long 0x1C "INT7,Interrupt Priority Register" bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3" bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3" bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3" bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3" tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 0xA group.long 0xD30++0x03 line.long 0x00 "DFSR,Data Fault Status Register" eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred" eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred" textline " " eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match" textline " " eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match" eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request" if (CORENAME()=="CORTEXM1") if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00) group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " textline " " textfld " " bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" else group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked" bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted" textline " " bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted" bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" endif else if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00) group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up" bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " textline " " textfld " " bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" else group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up" bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked" bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted" textline " " bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted" bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" endif endif wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Selector Register" bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write" bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..." group.long 0xDF8++0x07 line.long 0x00 "DCRDR,Debug Core Register Data Register" hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor" line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled" bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error" textline " " bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset" width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Breakpoint Unit (BPU)" sif COMPonent.AVAILABLE("BPU") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1)) width 8. group.long 0x00++0x03 line.long 0x00 "BP_CTRL,Breakpoint Control Register" bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. " KEY ,Key field" "No write,Write" bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled" group.long 0x8++0x03 line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled" group.long 0xC++0x03 line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled" group.long 0x10++0x03 line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled" group.long 0x14++0x03 line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled" else newline textline "BPU component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 14. rgroup.long 0x00++0x03 line.long 0x00 "DW_CTRL,DW Control Register " bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x1c++0x03 line.long 0x00 "DW_PCSR,DW Program Counter Sample Register" hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF" group.long 0x20++0x0b line.long 0x00 "DW_COMP0,DW Comparator Register 0" hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address" line.long 0x04 "DW_MASK0,DW Mask Register 0" hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP" line.long 0x08 "DW_FUNCTION0,DW Function Register 0" bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match" bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..." group.long 0x30++0x0b line.long 0x00 "DW_COMP1,DW Comparator Register 1" hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address" line.long 0x04 "DW_MASK1,DW Mask Register 1 " hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP" line.long 0x08 "DW_FUNCTION1,DW Function Register 1" bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match" bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..." else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end sif (cpuis("CY8C424?BZI-L489")||cpuis("CY8C424??ZI-L485")||cpuis("CY8C424?LTI-L485")) tree "CAN" tree "CAN0" base ad:0x402E0000 width 18. tree "CSR" group.long 0x00++0x07 line.long 0x00 "INT_SR,Interrupt Status Register" sif (cpuis("CY8C424?BZI-L489")||cpuis("CY8C424??ZI-L485")||cpuis("CY8C424?LTI-L485")) eventfld.long 0x00 15. " SST_FAILURE ,Single shot transmission failure Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 14. " STUCK_AT_0 ,Stuck at dominant error Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 13. " RTR_MSG ,RTR auto-reply Msg sent Interrupt" "No interrupt,Interrupt" textline " " endif eventfld.long 0x00 12. " RX_MSG ,Msg received" "No interrupt,Interrupt" eventfld.long 0x00 11. " TX_MSG ,Tx Msg Sent" "No interrupt,Interrupt" textline " " eventfld.long 0x00 10. " RX_MSG_LOSS ,Rx Msg loss Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 9. " BUS_OFF ,Bus Off State" "No interrupt,Interrupt" textline " " eventfld.long 0x00 8. " CRC_ERR ,CRC Error Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 7. " FORM_ERR ,Form Error Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 6. " ACK_ERR ,Ack Error Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 5. " STUFF_ERR ,Stuff Error Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 4. " BIT_ERR ,Bit Error Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 3. " OVR_LOAD ,Overload Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 2. " ARB_LOSS ,Arbitration Loss" "No interrupt,Interrupt" line.long 0x04 "INT_EN,Interrupt Enable Register" sif (cpuis("CY8C424?BZI-L489")||cpuis("CY8C424??ZI-L485")||cpuis("CY8C424?LTI-L485")) bitfld.long 0x04 15. " SST_FAILURE ,Single shot transmission failure Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x04 14. " STUCK_AT_0 ,Stuck at dominant error Interrupt" "Disabled,Enabled" bitfld.long 0x04 13. " RTR_MSG ,RTR auto-reply Msg sent Interrupt" "Disabled,Enabled" textline " " endif bitfld.long 0x04 12. " RX_MSG ,Msg received Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 11. " TX_MSG ,Tx Msg Sent Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 10. " RX_MSG_LOSS ,Rx Msg Loss Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 9. " BUS_OFF ,Busoff State Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 8. " CRC_ERR ,CRC Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 7. " FORM_ERR ,Form Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 6. " ACK_ERR ,Ack Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 5. " STUFF_ERR ,Stuff Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 4. " BIT_ERR ,Bit Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 3. " OVR_LOAD ,Overload Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 2. " ARB_LOSS ,Arbitration Loss Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 0. " INT_EBL ,Global Interrupt Enable Flag" "Disabled,Enabled" hgroup.long 0x08++0x03 hide.long 0x00 "BUF_SR,Buffer Status Register" in rgroup.long 0x0c++0x03 line.long 0x00 "ERR_SR,Error Status Register" bitfld.long 0x00 19. " RXGTE96 ,Rx Error Count is greater or equal to 96 Decimal" "Equal,Greater" bitfld.long 0x00 18. " TXGTE96 ,Tx Error Count is greater or equal to 96 Decimal" "Equal,Greater" textline " " bitfld.long 0x00 16.--17. " ERR_STATE ,Error State of CAN node" "Active,Passive,Buss off,Buss off" hexmask.long.byte 0x00 8.--15. 1. " RX_ERR_CNT ,Rx error Count" textline " " hexmask.long.byte 0x00 0.--7. 1. " TX_ERR_CNT ,Tx error Count" group.long 0x10++0x07 line.long 0x00 "CMD,Command Register" sif (cpuis("CY8C424?BZI-L489")||cpuis("CY8C424??ZI-L485")||cpuis("CY8C424?LTI-L485")) bitfld.long 0x00 28.--31. " IP_MAJOR_VERSION ,IP Major Version Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " IP_MINOR_VERSION ,IP Minor Version Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x00 16.--23. 1. " IP_REV_NUMBER ,IP Revision Number" bitfld.long 0x00 3. " SRAM_TEST ,SRAM test Mode" "Normal,Enabled" textline " " bitfld.long 0x00 1.--2. " TEST_MODE ,Loopback[2]/Listen[1] Test mode" "Normal,Listen-only,External loopback,Internal loopback" bitfld.long 0x00 0. " RUN_STOP ,Run/Stop mode" "Stop,Run" else bitfld.long 0x00 3. " SRAM_TEST ,SRAM test Mode" "Normal,Enabled" bitfld.long 0x00 1. " LISTEN ,Listen only mode" "Active,CAN listen only" textline " " bitfld.long 0x00 0. " RUN_STOP ,Run/Stop mode" "Stop,Run" endif line.long 0x04 "CFG,Configuration Register" hexmask.long.word 0x04 16.--30. 1. " CFG_BITRATE ,CAN configuration Bit rate" sif (cpuis("CY8C424?BZI-L489")||cpuis("CY8C424??ZI-L485")||cpuis("CY8C424?LTI-L485")) bitfld.long 0x04 14. " ECR_MODE ,Error Capture mode" "Free running,Capture mode" textline " " bitfld.long 0x04 13. " SWAP_ENDIAN ,Swap Endian" "Big endian,Little endian" endif bitfld.long 0x04 12. " CFG_ARBITER ,Tx buffer Arbiter" "Round robin,Fixed priority" textline " " bitfld.long 0x04 8.--11. " CFG_TSEG1 ,Length of time segment1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 5.--7. " CFG_TSEG2 ,Length of time segment2" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x04 4. " AUTO_RST ,Auto Restart" "Disabled,Enabled" bitfld.long 0x04 2.--3. " CFG_SJW ,Synchronization Jump Width" "0,1,2,3" textline " " bitfld.long 0x04 1. " SAMPLING_MODE ,CAN bus Bit sampling" "1 point,3 points" bitfld.long 0x04 0. " EDGE_MODE ,CAN bus synchronization logic" "Edge from 'R' to 'D',Both" sif (cpuis("CY8C424?BZI-L489")||cpuis("CY8C424??ZI-L485")||cpuis("CY8C424?LTI-L485")) rgroup.long 0x18++0x03 line.long 0x00 "ECR,Error Capture Register" bitfld.long 0x00 12.--16. " FIELD ,Error capture field" "Stopped,Synchronize,,,,Interframe,Bus Idle,Start of Frame,Arbitration,Control,Data,CRC,ACK,End of frame,,,Error flag,Error echo,Error delimiter,,,,,,Overload flag,Overload echo,Overload delimiter,?..." bitfld.long 0x00 6.--11. " BIT ,Bit number inside of Field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 5. " TX_MODE ,Tx Mode" "No status,Transmitter" bitfld.long 0x00 4. " RX_MODE ,Rx Mode" "No status,Receiver" textline " " bitfld.long 0x00 1.--3. " ERROR_TYPE ,Error type" "Arbitration loss,Bit Error,Bit Stuffing Error,Acknowledge Error,Form Error,CRC Error,?..." bitfld.long 0x00 0. " ECR_STATUS ,ECR Status" "Error/Free running,No error" group.long 0x400++0x17 line.long 0x00 "CNTL,Control Register" bitfld.long 0x00 31. " IP_ENABLE ,Can enable" "Disabled/Reset,Enabled/Running" bitfld.long 0x00 0. " TT_ENABLE ,TTCAN enable" "Disabled,Enabled" line.long 0x04 "TTCAN_COUNTER,TTCAN Level1 16-Bit Local Time Counter Register" hexmask.long.word 0x04 16.--31. 1. " LOCAL_TIME ,Bit time counter in TTCAN level 1" line.long 0x08 "TTCAN_COMPARE, Level1 Compare Configuration Register" hexmask.long.word 0x08 16.--31. 1. " TIME_MARK ,Compare target" line.long 0x0C "TTCAN_CAPTURE,TTCAN Level1 Capture Configuration Register" hexmask.long.word 0x0C 16.--31. 1. " SYNC_MARK ,Copy TTCAN_COUNTER.LOCAL_TIME, when SOF detected" line.long 0x10 "TTCAN_TIMING,TTCAN Level1 Timing Configuration Register" hexmask.long.word 0x10 16.--30. 1. " CFG_BITRATE ,Prescaler for generating the time quantum" bitfld.long 0x10 8.--11. " CFG_TSEG1 ,Time segment 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x10 5.--7. " CFG_TSEG2 ,Time segment 2" "0,1,2,3,4,5,6,7" bitfld.long 0x10 1. " SAMPLING_MODE ,CAN bus bit sampling" "One point,3 points" line.long 0x14 "INTR_CAN_set/clr,CAN Interrupt Cause Register" setclrfld.long 0x14 2. 0x18 2. 0x14 2. " TT_CAPTURE , TT Capture Interrupt" "No interrupt,Interrupt" setclrfld.long 0x14 1. 0x18 1. 0x14 1. " TT_COMPARE , TT Compare Interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x14 0. 0x18 0. 0x14 0. " INT_STATUS , INT_Status Interrupt" "No interrupt,Interrupt" group.long 0x41C++0x03 line.long 0x00 "INTR_CAN_MASK,Can Interrupt Mask Register" bitfld.long 0x00 2. " TT_CAPTURE ,TT_CAPTURE Interrupt mask" "Not masked,Masked" bitfld.long 0x00 1. " TT_COMPARE ,TT_COMPARE Interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 0. " INT_STATUS ,INT_STATUS Interrupt mask" "Not masked,Masked" rgroup.long 0x420++0x03 line.long 0x00 "INTR_CAN_MASKED,Can Interrupt Masked Register" bitfld.long 0x00 2. " TT_CAPTURE ,Logical and of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 1. " TT_COMPARE ,Logical and of corresponding request and mask bits" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " INT_STATUS ,Logical and of corresponding request and mask bits" "No interrupt,Interrupt" endif tree.end width 9. tree "TX Registers" group.long 0x20++0x03 "TX0" line.long 0x00 "TX0_CMD,CAN Tx Command Register" bitfld.long 0x00 23. " WPN2 ,Write protect bit" "Not protected,Protected" bitfld.long 0x00 21. " RTR ,RTR remote bit" "Standard,RTR" textline " " bitfld.long 0x00 20. " IDE ,Extended identifier" "Standard,Extended" bitfld.long 0x00 16.--19. " DLC ,Data length of the Tx Msg" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" textline " " bitfld.long 0x00 3. " WPN1 ,Write protect not flag bit 2" "Unchanged,Modified" bitfld.long 0x00 2. " TXINT_EBL ,Transmit interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Requested" bitfld.long 0x00 0. " TXREQ ,Transmit request" "Idle,Requested" if (((per.l(ad:0x402E0000+0x20))&0x100000)==0x00) group.long (0x20+0x04)++0x03 line.long 0x00 "TX0_ID,CAN Tx Msg Identifier" bitfld.long 0x00 13. " ID ,Tx0 Msg Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Tx0 Msg Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Tx0 Msg Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Tx0 Msg Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Tx0 Msg Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Tx0 Msg Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Tx0 Msg Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Tx0 Msg Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Tx0 Msg Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Tx0 Msg Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Tx0 Msg Identifier bit 0" "0,1" else group.long (0x20+0x04)++0x03 line.long 0x00 "TX0_ID,CAN Tx Msg Identifier" bitfld.long 0x00 31. " ID ,Tx0 Msg Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Tx0 Msg Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Tx0 Msg Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Tx0 Msg Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Tx0 Msg Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Tx0 Msg Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Tx0 Msg Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Tx0 Msg Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Tx0 Msg Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Tx0 Msg Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Tx0 Msg Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Tx0 Msg Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Tx0 Msg Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Tx0 Msg Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Tx0 Msg Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Tx0 Msg Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Tx0 Msg Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Tx0 Msg Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Tx0 Msg Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Tx0 Msg Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Tx0 Msg Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Tx0 Msg Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Tx0 Msg Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Tx0 Msg Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Tx0 Msg Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Tx0 Msg Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Tx0 Msg Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Tx0 Msg Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Tx0 Msg Identifier bit 0" "0,1" endif group.long (0x20+0x08)++0x07 line.long 0x00 "TX0_DH,CAN Tx Msg Upper Data Bytes" line.long 0x04 "TX0_DL,CAN Tx Msg Lower Data Bytes" group.long 0x30++0x03 "TX1" line.long 0x00 "TX1_CMD,CAN Tx Command Register" bitfld.long 0x00 23. " WPN2 ,Write protect bit" "Not protected,Protected" bitfld.long 0x00 21. " RTR ,RTR remote bit" "Standard,RTR" textline " " bitfld.long 0x00 20. " IDE ,Extended identifier" "Standard,Extended" bitfld.long 0x00 16.--19. " DLC ,Data length of the Tx Msg" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" textline " " bitfld.long 0x00 3. " WPN1 ,Write protect not flag bit 2" "Unchanged,Modified" bitfld.long 0x00 2. " TXINT_EBL ,Transmit interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Requested" bitfld.long 0x00 0. " TXREQ ,Transmit request" "Idle,Requested" if (((per.l(ad:0x402E0000+0x30))&0x100000)==0x00) group.long (0x30+0x04)++0x03 line.long 0x00 "TX1_ID,CAN Tx Msg Identifier" bitfld.long 0x00 13. " ID ,Tx1 Msg Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Tx1 Msg Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Tx1 Msg Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Tx1 Msg Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Tx1 Msg Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Tx1 Msg Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Tx1 Msg Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Tx1 Msg Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Tx1 Msg Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Tx1 Msg Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Tx1 Msg Identifier bit 0" "0,1" else group.long (0x30+0x04)++0x03 line.long 0x00 "TX1_ID,CAN Tx Msg Identifier" bitfld.long 0x00 31. " ID ,Tx1 Msg Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Tx1 Msg Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Tx1 Msg Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Tx1 Msg Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Tx1 Msg Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Tx1 Msg Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Tx1 Msg Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Tx1 Msg Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Tx1 Msg Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Tx1 Msg Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Tx1 Msg Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Tx1 Msg Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Tx1 Msg Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Tx1 Msg Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Tx1 Msg Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Tx1 Msg Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Tx1 Msg Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Tx1 Msg Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Tx1 Msg Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Tx1 Msg Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Tx1 Msg Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Tx1 Msg Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Tx1 Msg Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Tx1 Msg Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Tx1 Msg Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Tx1 Msg Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Tx1 Msg Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Tx1 Msg Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Tx1 Msg Identifier bit 0" "0,1" endif group.long (0x30+0x08)++0x07 line.long 0x00 "TX1_DH,CAN Tx Msg Upper Data Bytes" line.long 0x04 "TX1_DL,CAN Tx Msg Lower Data Bytes" group.long 0x40++0x03 "TX2" line.long 0x00 "TX2_CMD,CAN Tx Command Register" bitfld.long 0x00 23. " WPN2 ,Write protect bit" "Not protected,Protected" bitfld.long 0x00 21. " RTR ,RTR remote bit" "Standard,RTR" textline " " bitfld.long 0x00 20. " IDE ,Extended identifier" "Standard,Extended" bitfld.long 0x00 16.--19. " DLC ,Data length of the Tx Msg" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" textline " " bitfld.long 0x00 3. " WPN1 ,Write protect not flag bit 2" "Unchanged,Modified" bitfld.long 0x00 2. " TXINT_EBL ,Transmit interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Requested" bitfld.long 0x00 0. " TXREQ ,Transmit request" "Idle,Requested" if (((per.l(ad:0x402E0000+0x40))&0x100000)==0x00) group.long (0x40+0x04)++0x03 line.long 0x00 "TX2_ID,CAN Tx Msg Identifier" bitfld.long 0x00 13. " ID ,Tx2 Msg Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Tx2 Msg Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Tx2 Msg Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Tx2 Msg Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Tx2 Msg Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Tx2 Msg Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Tx2 Msg Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Tx2 Msg Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Tx2 Msg Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Tx2 Msg Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Tx2 Msg Identifier bit 0" "0,1" else group.long (0x40+0x04)++0x03 line.long 0x00 "TX2_ID,CAN Tx Msg Identifier" bitfld.long 0x00 31. " ID ,Tx2 Msg Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Tx2 Msg Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Tx2 Msg Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Tx2 Msg Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Tx2 Msg Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Tx2 Msg Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Tx2 Msg Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Tx2 Msg Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Tx2 Msg Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Tx2 Msg Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Tx2 Msg Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Tx2 Msg Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Tx2 Msg Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Tx2 Msg Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Tx2 Msg Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Tx2 Msg Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Tx2 Msg Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Tx2 Msg Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Tx2 Msg Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Tx2 Msg Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Tx2 Msg Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Tx2 Msg Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Tx2 Msg Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Tx2 Msg Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Tx2 Msg Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Tx2 Msg Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Tx2 Msg Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Tx2 Msg Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Tx2 Msg Identifier bit 0" "0,1" endif group.long (0x40+0x08)++0x07 line.long 0x00 "TX2_DH,CAN Tx Msg Upper Data Bytes" line.long 0x04 "TX2_DL,CAN Tx Msg Lower Data Bytes" group.long 0x50++0x03 "TX3" line.long 0x00 "TX3_CMD,CAN Tx Command Register" bitfld.long 0x00 23. " WPN2 ,Write protect bit" "Not protected,Protected" bitfld.long 0x00 21. " RTR ,RTR remote bit" "Standard,RTR" textline " " bitfld.long 0x00 20. " IDE ,Extended identifier" "Standard,Extended" bitfld.long 0x00 16.--19. " DLC ,Data length of the Tx Msg" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" textline " " bitfld.long 0x00 3. " WPN1 ,Write protect not flag bit 2" "Unchanged,Modified" bitfld.long 0x00 2. " TXINT_EBL ,Transmit interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Requested" bitfld.long 0x00 0. " TXREQ ,Transmit request" "Idle,Requested" if (((per.l(ad:0x402E0000+0x50))&0x100000)==0x00) group.long (0x50+0x04)++0x03 line.long 0x00 "TX3_ID,CAN Tx Msg Identifier" bitfld.long 0x00 13. " ID ,Tx3 Msg Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Tx3 Msg Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Tx3 Msg Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Tx3 Msg Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Tx3 Msg Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Tx3 Msg Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Tx3 Msg Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Tx3 Msg Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Tx3 Msg Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Tx3 Msg Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Tx3 Msg Identifier bit 0" "0,1" else group.long (0x50+0x04)++0x03 line.long 0x00 "TX3_ID,CAN Tx Msg Identifier" bitfld.long 0x00 31. " ID ,Tx3 Msg Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Tx3 Msg Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Tx3 Msg Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Tx3 Msg Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Tx3 Msg Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Tx3 Msg Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Tx3 Msg Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Tx3 Msg Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Tx3 Msg Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Tx3 Msg Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Tx3 Msg Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Tx3 Msg Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Tx3 Msg Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Tx3 Msg Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Tx3 Msg Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Tx3 Msg Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Tx3 Msg Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Tx3 Msg Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Tx3 Msg Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Tx3 Msg Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Tx3 Msg Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Tx3 Msg Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Tx3 Msg Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Tx3 Msg Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Tx3 Msg Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Tx3 Msg Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Tx3 Msg Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Tx3 Msg Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Tx3 Msg Identifier bit 0" "0,1" endif group.long (0x50+0x08)++0x07 line.long 0x00 "TX3_DH,CAN Tx Msg Upper Data Bytes" line.long 0x04 "TX3_DL,CAN Tx Msg Lower Data Bytes" group.long 0x60++0x03 "TX4" line.long 0x00 "TX4_CMD,CAN Tx Command Register" bitfld.long 0x00 23. " WPN2 ,Write protect bit" "Not protected,Protected" bitfld.long 0x00 21. " RTR ,RTR remote bit" "Standard,RTR" textline " " bitfld.long 0x00 20. " IDE ,Extended identifier" "Standard,Extended" bitfld.long 0x00 16.--19. " DLC ,Data length of the Tx Msg" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" textline " " bitfld.long 0x00 3. " WPN1 ,Write protect not flag bit 2" "Unchanged,Modified" bitfld.long 0x00 2. " TXINT_EBL ,Transmit interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Requested" bitfld.long 0x00 0. " TXREQ ,Transmit request" "Idle,Requested" if (((per.l(ad:0x402E0000+0x60))&0x100000)==0x00) group.long (0x60+0x04)++0x03 line.long 0x00 "TX4_ID,CAN Tx Msg Identifier" bitfld.long 0x00 13. " ID ,Tx4 Msg Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Tx4 Msg Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Tx4 Msg Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Tx4 Msg Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Tx4 Msg Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Tx4 Msg Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Tx4 Msg Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Tx4 Msg Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Tx4 Msg Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Tx4 Msg Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Tx4 Msg Identifier bit 0" "0,1" else group.long (0x60+0x04)++0x03 line.long 0x00 "TX4_ID,CAN Tx Msg Identifier" bitfld.long 0x00 31. " ID ,Tx4 Msg Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Tx4 Msg Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Tx4 Msg Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Tx4 Msg Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Tx4 Msg Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Tx4 Msg Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Tx4 Msg Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Tx4 Msg Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Tx4 Msg Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Tx4 Msg Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Tx4 Msg Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Tx4 Msg Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Tx4 Msg Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Tx4 Msg Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Tx4 Msg Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Tx4 Msg Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Tx4 Msg Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Tx4 Msg Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Tx4 Msg Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Tx4 Msg Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Tx4 Msg Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Tx4 Msg Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Tx4 Msg Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Tx4 Msg Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Tx4 Msg Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Tx4 Msg Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Tx4 Msg Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Tx4 Msg Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Tx4 Msg Identifier bit 0" "0,1" endif group.long (0x60+0x08)++0x07 line.long 0x00 "TX4_DH,CAN Tx Msg Upper Data Bytes" line.long 0x04 "TX4_DL,CAN Tx Msg Lower Data Bytes" group.long 0x70++0x03 "TX5" line.long 0x00 "TX5_CMD,CAN Tx Command Register" bitfld.long 0x00 23. " WPN2 ,Write protect bit" "Not protected,Protected" bitfld.long 0x00 21. " RTR ,RTR remote bit" "Standard,RTR" textline " " bitfld.long 0x00 20. " IDE ,Extended identifier" "Standard,Extended" bitfld.long 0x00 16.--19. " DLC ,Data length of the Tx Msg" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" textline " " bitfld.long 0x00 3. " WPN1 ,Write protect not flag bit 2" "Unchanged,Modified" bitfld.long 0x00 2. " TXINT_EBL ,Transmit interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Requested" bitfld.long 0x00 0. " TXREQ ,Transmit request" "Idle,Requested" if (((per.l(ad:0x402E0000+0x70))&0x100000)==0x00) group.long (0x70+0x04)++0x03 line.long 0x00 "TX5_ID,CAN Tx Msg Identifier" bitfld.long 0x00 13. " ID ,Tx5 Msg Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Tx5 Msg Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Tx5 Msg Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Tx5 Msg Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Tx5 Msg Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Tx5 Msg Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Tx5 Msg Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Tx5 Msg Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Tx5 Msg Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Tx5 Msg Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Tx5 Msg Identifier bit 0" "0,1" else group.long (0x70+0x04)++0x03 line.long 0x00 "TX5_ID,CAN Tx Msg Identifier" bitfld.long 0x00 31. " ID ,Tx5 Msg Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Tx5 Msg Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Tx5 Msg Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Tx5 Msg Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Tx5 Msg Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Tx5 Msg Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Tx5 Msg Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Tx5 Msg Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Tx5 Msg Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Tx5 Msg Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Tx5 Msg Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Tx5 Msg Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Tx5 Msg Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Tx5 Msg Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Tx5 Msg Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Tx5 Msg Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Tx5 Msg Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Tx5 Msg Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Tx5 Msg Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Tx5 Msg Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Tx5 Msg Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Tx5 Msg Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Tx5 Msg Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Tx5 Msg Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Tx5 Msg Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Tx5 Msg Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Tx5 Msg Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Tx5 Msg Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Tx5 Msg Identifier bit 0" "0,1" endif group.long (0x70+0x08)++0x07 line.long 0x00 "TX5_DH,CAN Tx Msg Upper Data Bytes" line.long 0x04 "TX5_DL,CAN Tx Msg Lower Data Bytes" group.long 0x80++0x03 "TX6" line.long 0x00 "TX6_CMD,CAN Tx Command Register" bitfld.long 0x00 23. " WPN2 ,Write protect bit" "Not protected,Protected" bitfld.long 0x00 21. " RTR ,RTR remote bit" "Standard,RTR" textline " " bitfld.long 0x00 20. " IDE ,Extended identifier" "Standard,Extended" bitfld.long 0x00 16.--19. " DLC ,Data length of the Tx Msg" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" textline " " bitfld.long 0x00 3. " WPN1 ,Write protect not flag bit 2" "Unchanged,Modified" bitfld.long 0x00 2. " TXINT_EBL ,Transmit interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Requested" bitfld.long 0x00 0. " TXREQ ,Transmit request" "Idle,Requested" if (((per.l(ad:0x402E0000+0x80))&0x100000)==0x00) group.long (0x80+0x04)++0x03 line.long 0x00 "TX6_ID,CAN Tx Msg Identifier" bitfld.long 0x00 13. " ID ,Tx6 Msg Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Tx6 Msg Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Tx6 Msg Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Tx6 Msg Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Tx6 Msg Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Tx6 Msg Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Tx6 Msg Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Tx6 Msg Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Tx6 Msg Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Tx6 Msg Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Tx6 Msg Identifier bit 0" "0,1" else group.long (0x80+0x04)++0x03 line.long 0x00 "TX6_ID,CAN Tx Msg Identifier" bitfld.long 0x00 31. " ID ,Tx6 Msg Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Tx6 Msg Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Tx6 Msg Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Tx6 Msg Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Tx6 Msg Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Tx6 Msg Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Tx6 Msg Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Tx6 Msg Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Tx6 Msg Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Tx6 Msg Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Tx6 Msg Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Tx6 Msg Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Tx6 Msg Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Tx6 Msg Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Tx6 Msg Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Tx6 Msg Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Tx6 Msg Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Tx6 Msg Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Tx6 Msg Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Tx6 Msg Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Tx6 Msg Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Tx6 Msg Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Tx6 Msg Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Tx6 Msg Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Tx6 Msg Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Tx6 Msg Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Tx6 Msg Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Tx6 Msg Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Tx6 Msg Identifier bit 0" "0,1" endif group.long (0x80+0x08)++0x07 line.long 0x00 "TX6_DH,CAN Tx Msg Upper Data Bytes" line.long 0x04 "TX6_DL,CAN Tx Msg Lower Data Bytes" group.long 0x90++0x03 "TX7" line.long 0x00 "TX7_CMD,CAN Tx Command Register" bitfld.long 0x00 23. " WPN2 ,Write protect bit" "Not protected,Protected" bitfld.long 0x00 21. " RTR ,RTR remote bit" "Standard,RTR" textline " " bitfld.long 0x00 20. " IDE ,Extended identifier" "Standard,Extended" bitfld.long 0x00 16.--19. " DLC ,Data length of the Tx Msg" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" textline " " bitfld.long 0x00 3. " WPN1 ,Write protect not flag bit 2" "Unchanged,Modified" bitfld.long 0x00 2. " TXINT_EBL ,Transmit interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Requested" bitfld.long 0x00 0. " TXREQ ,Transmit request" "Idle,Requested" if (((per.l(ad:0x402E0000+0x90))&0x100000)==0x00) group.long (0x90+0x04)++0x03 line.long 0x00 "TX7_ID,CAN Tx Msg Identifier" bitfld.long 0x00 13. " ID ,Tx7 Msg Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Tx7 Msg Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Tx7 Msg Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Tx7 Msg Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Tx7 Msg Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Tx7 Msg Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Tx7 Msg Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Tx7 Msg Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Tx7 Msg Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Tx7 Msg Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Tx7 Msg Identifier bit 0" "0,1" else group.long (0x90+0x04)++0x03 line.long 0x00 "TX7_ID,CAN Tx Msg Identifier" bitfld.long 0x00 31. " ID ,Tx7 Msg Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Tx7 Msg Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Tx7 Msg Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Tx7 Msg Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Tx7 Msg Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Tx7 Msg Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Tx7 Msg Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Tx7 Msg Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Tx7 Msg Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Tx7 Msg Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Tx7 Msg Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Tx7 Msg Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Tx7 Msg Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Tx7 Msg Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Tx7 Msg Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Tx7 Msg Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Tx7 Msg Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Tx7 Msg Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Tx7 Msg Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Tx7 Msg Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Tx7 Msg Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Tx7 Msg Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Tx7 Msg Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Tx7 Msg Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Tx7 Msg Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Tx7 Msg Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Tx7 Msg Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Tx7 Msg Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Tx7 Msg Identifier bit 0" "0,1" endif group.long (0x90+0x08)++0x07 line.long 0x00 "TX7_DH,CAN Tx Msg Upper Data Bytes" line.long 0x04 "TX7_DL,CAN Tx Msg Lower Data Bytes" tree.end width 11. tree "RX Registers" group.long 0xA0++0x03 "RX0" line.long 0x00 "RX0_CMD,CAN Rx Command Register" bitfld.long 0x00 23. " WPNH ,Write Protect Bit" "Not protected,Protected" bitfld.long 0x00 21. " RTR ,RTR Remote bit" "Standard,RTR" textline " " bitfld.long 0x00 20. " IDE ,Extended identifier" "Standard,Extended" bitfld.long 0x00 16.--19. " DLC ,Data Length of the Tx Msg" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" textline " " bitfld.long 0x00 7. " WPNL ,Write protect not Flag Bits 6:3" "Unchanged,Modified" bitfld.long 0x00 6. " LK_FLG ,Link Flag used to link the Rx Buffer" "Not linked,Linked" textline " " bitfld.long 0x00 5. " RX_INT_EBL ,Receive Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " RTR_RPLY ,Automatic RTR Message Handling" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " BUF_EBL ,Buffer Enable" "Disabled,Enabled" bitfld.long 0x00 2. " RTR_ABORT ,RTR Abort Request" "Idle,Requested" textline " " bitfld.long 0x00 1. " RTR_RPY_PND ,RTR Reply request Pending" "Not pending,Pending" bitfld.long 0x00 0. " MSG_AV ,Message Available" "Not available,Available" if (((per.l(ad:0x402E0000+0xA0))&0x100000)==0x00) group.long (0xA0+0x04)++0x03 line.long 0x00 "RX0_ID,CAN Rx Msg Identifier" bitfld.long 0x00 13. " ID ,Rx Msg Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" else group.long (0xA0+0x04)++0x03 line.long 0x00 "RX0_ID,CAN Rx Msg Identifier" bitfld.long 0x00 31. " ID ,RX Msg Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" endif group.long (0xA0+0x08)++0x07 line.long 0x00 "RX0_DH,CAN Rx Msg Upper Data Bytes" line.long 0x04 "RX0_DL,CAN Rx Msg Lower Data Bytes" if (((per.l(ad:0x402E0000+0xA0+0x10))&0x4)==0x00) group.long (0xA0+0x10)++0x03 line.long 0x00 "RX0_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0xA0+0x10)++0x03 line.long 0x00 "RX0_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif if (((per.l(ad:0x402E0000+0xA0+0x14))&0x4)==0x00) group.long (0xA0+0x14)++0x03 line.long 0x00 "RX0_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0xA0+0x14)++0x03 line.long 0x00 "RX0_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif group.long (0xA0+0x18)++0x07 line.long 0x00 "RX0_AMRD,CAN Rx Acceptance mask data" hexmask.long.word 0x00 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" line.long 0x04 "RX0_ACRD,CAN Rx Acceptance code data" hexmask.long.word 0x04 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" group.long 0xC0++0x03 "RX1" line.long 0x00 "RX1_CMD,CAN Rx Command Register" bitfld.long 0x00 23. " WPNH ,Write Protect Bit" "Not protected,Protected" bitfld.long 0x00 21. " RTR ,RTR Remote bit" "Standard,RTR" textline " " bitfld.long 0x00 20. " IDE ,Extended identifier" "Standard,Extended" bitfld.long 0x00 16.--19. " DLC ,Data Length of the Tx Msg" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" textline " " bitfld.long 0x00 7. " WPNL ,Write protect not Flag Bits 6:3" "Unchanged,Modified" bitfld.long 0x00 6. " LK_FLG ,Link Flag used to link the Rx Buffer" "Not linked,Linked" textline " " bitfld.long 0x00 5. " RX_INT_EBL ,Receive Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " RTR_RPLY ,Automatic RTR Message Handling" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " BUF_EBL ,Buffer Enable" "Disabled,Enabled" bitfld.long 0x00 2. " RTR_ABORT ,RTR Abort Request" "Idle,Requested" textline " " bitfld.long 0x00 1. " RTR_RPY_PND ,RTR Reply request Pending" "Not pending,Pending" bitfld.long 0x00 0. " MSG_AV ,Message Available" "Not available,Available" if (((per.l(ad:0x402E0000+0xC0))&0x100000)==0x00) group.long (0xC0+0x04)++0x03 line.long 0x00 "RX1_ID,CAN Rx Msg Identifier" bitfld.long 0x00 13. " ID ,Rx Msg Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" else group.long (0xC0+0x04)++0x03 line.long 0x00 "RX1_ID,CAN Rx Msg Identifier" bitfld.long 0x00 31. " ID ,RX Msg Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" endif group.long (0xC0+0x08)++0x07 line.long 0x00 "RX1_DH,CAN Rx Msg Upper Data Bytes" line.long 0x04 "RX1_DL,CAN Rx Msg Lower Data Bytes" if (((per.l(ad:0x402E0000+0xC0+0x10))&0x4)==0x00) group.long (0xC0+0x10)++0x03 line.long 0x00 "RX1_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0xC0+0x10)++0x03 line.long 0x00 "RX1_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif if (((per.l(ad:0x402E0000+0xC0+0x14))&0x4)==0x00) group.long (0xC0+0x14)++0x03 line.long 0x00 "RX1_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0xC0+0x14)++0x03 line.long 0x00 "RX1_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif group.long (0xC0+0x18)++0x07 line.long 0x00 "RX1_AMRD,CAN Rx Acceptance mask data" hexmask.long.word 0x00 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" line.long 0x04 "RX1_ACRD,CAN Rx Acceptance code data" hexmask.long.word 0x04 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" group.long 0xE0++0x03 "RX2" line.long 0x00 "RX2_CMD,CAN Rx Command Register" bitfld.long 0x00 23. " WPNH ,Write Protect Bit" "Not protected,Protected" bitfld.long 0x00 21. " RTR ,RTR Remote bit" "Standard,RTR" textline " " bitfld.long 0x00 20. " IDE ,Extended identifier" "Standard,Extended" bitfld.long 0x00 16.--19. " DLC ,Data Length of the Tx Msg" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" textline " " bitfld.long 0x00 7. " WPNL ,Write protect not Flag Bits 6:3" "Unchanged,Modified" bitfld.long 0x00 6. " LK_FLG ,Link Flag used to link the Rx Buffer" "Not linked,Linked" textline " " bitfld.long 0x00 5. " RX_INT_EBL ,Receive Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " RTR_RPLY ,Automatic RTR Message Handling" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " BUF_EBL ,Buffer Enable" "Disabled,Enabled" bitfld.long 0x00 2. " RTR_ABORT ,RTR Abort Request" "Idle,Requested" textline " " bitfld.long 0x00 1. " RTR_RPY_PND ,RTR Reply request Pending" "Not pending,Pending" bitfld.long 0x00 0. " MSG_AV ,Message Available" "Not available,Available" if (((per.l(ad:0x402E0000+0xE0))&0x100000)==0x00) group.long (0xE0+0x04)++0x03 line.long 0x00 "RX2_ID,CAN Rx Msg Identifier" bitfld.long 0x00 13. " ID ,Rx Msg Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" else group.long (0xE0+0x04)++0x03 line.long 0x00 "RX2_ID,CAN Rx Msg Identifier" bitfld.long 0x00 31. " ID ,RX Msg Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" endif group.long (0xE0+0x08)++0x07 line.long 0x00 "RX2_DH,CAN Rx Msg Upper Data Bytes" line.long 0x04 "RX2_DL,CAN Rx Msg Lower Data Bytes" if (((per.l(ad:0x402E0000+0xE0+0x10))&0x4)==0x00) group.long (0xE0+0x10)++0x03 line.long 0x00 "RX2_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0xE0+0x10)++0x03 line.long 0x00 "RX2_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif if (((per.l(ad:0x402E0000+0xE0+0x14))&0x4)==0x00) group.long (0xE0+0x14)++0x03 line.long 0x00 "RX2_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0xE0+0x14)++0x03 line.long 0x00 "RX2_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif group.long (0xE0+0x18)++0x07 line.long 0x00 "RX2_AMRD,CAN Rx Acceptance mask data" hexmask.long.word 0x00 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" line.long 0x04 "RX2_ACRD,CAN Rx Acceptance code data" hexmask.long.word 0x04 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" group.long 0x100++0x03 "RX3" line.long 0x00 "RX3_CMD,CAN Rx Command Register" bitfld.long 0x00 23. " WPNH ,Write Protect Bit" "Not protected,Protected" bitfld.long 0x00 21. " RTR ,RTR Remote bit" "Standard,RTR" textline " " bitfld.long 0x00 20. " IDE ,Extended identifier" "Standard,Extended" bitfld.long 0x00 16.--19. " DLC ,Data Length of the Tx Msg" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" textline " " bitfld.long 0x00 7. " WPNL ,Write protect not Flag Bits 6:3" "Unchanged,Modified" bitfld.long 0x00 6. " LK_FLG ,Link Flag used to link the Rx Buffer" "Not linked,Linked" textline " " bitfld.long 0x00 5. " RX_INT_EBL ,Receive Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " RTR_RPLY ,Automatic RTR Message Handling" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " BUF_EBL ,Buffer Enable" "Disabled,Enabled" bitfld.long 0x00 2. " RTR_ABORT ,RTR Abort Request" "Idle,Requested" textline " " bitfld.long 0x00 1. " RTR_RPY_PND ,RTR Reply request Pending" "Not pending,Pending" bitfld.long 0x00 0. " MSG_AV ,Message Available" "Not available,Available" if (((per.l(ad:0x402E0000+0x100))&0x100000)==0x00) group.long (0x100+0x04)++0x03 line.long 0x00 "RX3_ID,CAN Rx Msg Identifier" bitfld.long 0x00 13. " ID ,Rx Msg Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" else group.long (0x100+0x04)++0x03 line.long 0x00 "RX3_ID,CAN Rx Msg Identifier" bitfld.long 0x00 31. " ID ,RX Msg Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" endif group.long (0x100+0x08)++0x07 line.long 0x00 "RX3_DH,CAN Rx Msg Upper Data Bytes" line.long 0x04 "RX3_DL,CAN Rx Msg Lower Data Bytes" if (((per.l(ad:0x402E0000+0x100+0x10))&0x4)==0x00) group.long (0x100+0x10)++0x03 line.long 0x00 "RX3_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0x100+0x10)++0x03 line.long 0x00 "RX3_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif if (((per.l(ad:0x402E0000+0x100+0x14))&0x4)==0x00) group.long (0x100+0x14)++0x03 line.long 0x00 "RX3_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0x100+0x14)++0x03 line.long 0x00 "RX3_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif group.long (0x100+0x18)++0x07 line.long 0x00 "RX3_AMRD,CAN Rx Acceptance mask data" hexmask.long.word 0x00 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" line.long 0x04 "RX3_ACRD,CAN Rx Acceptance code data" hexmask.long.word 0x04 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" group.long 0x120++0x03 "RX4" line.long 0x00 "RX4_CMD,CAN Rx Command Register" bitfld.long 0x00 23. " WPNH ,Write Protect Bit" "Not protected,Protected" bitfld.long 0x00 21. " RTR ,RTR Remote bit" "Standard,RTR" textline " " bitfld.long 0x00 20. " IDE ,Extended identifier" "Standard,Extended" bitfld.long 0x00 16.--19. " DLC ,Data Length of the Tx Msg" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" textline " " bitfld.long 0x00 7. " WPNL ,Write protect not Flag Bits 6:3" "Unchanged,Modified" bitfld.long 0x00 6. " LK_FLG ,Link Flag used to link the Rx Buffer" "Not linked,Linked" textline " " bitfld.long 0x00 5. " RX_INT_EBL ,Receive Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " RTR_RPLY ,Automatic RTR Message Handling" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " BUF_EBL ,Buffer Enable" "Disabled,Enabled" bitfld.long 0x00 2. " RTR_ABORT ,RTR Abort Request" "Idle,Requested" textline " " bitfld.long 0x00 1. " RTR_RPY_PND ,RTR Reply request Pending" "Not pending,Pending" bitfld.long 0x00 0. " MSG_AV ,Message Available" "Not available,Available" if (((per.l(ad:0x402E0000+0x120))&0x100000)==0x00) group.long (0x120+0x04)++0x03 line.long 0x00 "RX4_ID,CAN Rx Msg Identifier" bitfld.long 0x00 13. " ID ,Rx Msg Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" else group.long (0x120+0x04)++0x03 line.long 0x00 "RX4_ID,CAN Rx Msg Identifier" bitfld.long 0x00 31. " ID ,RX Msg Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" endif group.long (0x120+0x08)++0x07 line.long 0x00 "RX4_DH,CAN Rx Msg Upper Data Bytes" line.long 0x04 "RX4_DL,CAN Rx Msg Lower Data Bytes" if (((per.l(ad:0x402E0000+0x120+0x10))&0x4)==0x00) group.long (0x120+0x10)++0x03 line.long 0x00 "RX4_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0x120+0x10)++0x03 line.long 0x00 "RX4_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif if (((per.l(ad:0x402E0000+0x120+0x14))&0x4)==0x00) group.long (0x120+0x14)++0x03 line.long 0x00 "RX4_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0x120+0x14)++0x03 line.long 0x00 "RX4_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif group.long (0x120+0x18)++0x07 line.long 0x00 "RX4_AMRD,CAN Rx Acceptance mask data" hexmask.long.word 0x00 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" line.long 0x04 "RX4_ACRD,CAN Rx Acceptance code data" hexmask.long.word 0x04 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" group.long 0x140++0x03 "RX5" line.long 0x00 "RX5_CMD,CAN Rx Command Register" bitfld.long 0x00 23. " WPNH ,Write Protect Bit" "Not protected,Protected" bitfld.long 0x00 21. " RTR ,RTR Remote bit" "Standard,RTR" textline " " bitfld.long 0x00 20. " IDE ,Extended identifier" "Standard,Extended" bitfld.long 0x00 16.--19. " DLC ,Data Length of the Tx Msg" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" textline " " bitfld.long 0x00 7. " WPNL ,Write protect not Flag Bits 6:3" "Unchanged,Modified" bitfld.long 0x00 6. " LK_FLG ,Link Flag used to link the Rx Buffer" "Not linked,Linked" textline " " bitfld.long 0x00 5. " RX_INT_EBL ,Receive Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " RTR_RPLY ,Automatic RTR Message Handling" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " BUF_EBL ,Buffer Enable" "Disabled,Enabled" bitfld.long 0x00 2. " RTR_ABORT ,RTR Abort Request" "Idle,Requested" textline " " bitfld.long 0x00 1. " RTR_RPY_PND ,RTR Reply request Pending" "Not pending,Pending" bitfld.long 0x00 0. " MSG_AV ,Message Available" "Not available,Available" if (((per.l(ad:0x402E0000+0x140))&0x100000)==0x00) group.long (0x140+0x04)++0x03 line.long 0x00 "RX5_ID,CAN Rx Msg Identifier" bitfld.long 0x00 13. " ID ,Rx Msg Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" else group.long (0x140+0x04)++0x03 line.long 0x00 "RX5_ID,CAN Rx Msg Identifier" bitfld.long 0x00 31. " ID ,RX Msg Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" endif group.long (0x140+0x08)++0x07 line.long 0x00 "RX5_DH,CAN Rx Msg Upper Data Bytes" line.long 0x04 "RX5_DL,CAN Rx Msg Lower Data Bytes" if (((per.l(ad:0x402E0000+0x140+0x10))&0x4)==0x00) group.long (0x140+0x10)++0x03 line.long 0x00 "RX5_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0x140+0x10)++0x03 line.long 0x00 "RX5_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif if (((per.l(ad:0x402E0000+0x140+0x14))&0x4)==0x00) group.long (0x140+0x14)++0x03 line.long 0x00 "RX5_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0x140+0x14)++0x03 line.long 0x00 "RX5_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif group.long (0x140+0x18)++0x07 line.long 0x00 "RX5_AMRD,CAN Rx Acceptance mask data" hexmask.long.word 0x00 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" line.long 0x04 "RX5_ACRD,CAN Rx Acceptance code data" hexmask.long.word 0x04 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" group.long 0x160++0x03 "RX6" line.long 0x00 "RX6_CMD,CAN Rx Command Register" bitfld.long 0x00 23. " WPNH ,Write Protect Bit" "Not protected,Protected" bitfld.long 0x00 21. " RTR ,RTR Remote bit" "Standard,RTR" textline " " bitfld.long 0x00 20. " IDE ,Extended identifier" "Standard,Extended" bitfld.long 0x00 16.--19. " DLC ,Data Length of the Tx Msg" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" textline " " bitfld.long 0x00 7. " WPNL ,Write protect not Flag Bits 6:3" "Unchanged,Modified" bitfld.long 0x00 6. " LK_FLG ,Link Flag used to link the Rx Buffer" "Not linked,Linked" textline " " bitfld.long 0x00 5. " RX_INT_EBL ,Receive Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " RTR_RPLY ,Automatic RTR Message Handling" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " BUF_EBL ,Buffer Enable" "Disabled,Enabled" bitfld.long 0x00 2. " RTR_ABORT ,RTR Abort Request" "Idle,Requested" textline " " bitfld.long 0x00 1. " RTR_RPY_PND ,RTR Reply request Pending" "Not pending,Pending" bitfld.long 0x00 0. " MSG_AV ,Message Available" "Not available,Available" if (((per.l(ad:0x402E0000+0x160))&0x100000)==0x00) group.long (0x160+0x04)++0x03 line.long 0x00 "RX6_ID,CAN Rx Msg Identifier" bitfld.long 0x00 13. " ID ,Rx Msg Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" else group.long (0x160+0x04)++0x03 line.long 0x00 "RX6_ID,CAN Rx Msg Identifier" bitfld.long 0x00 31. " ID ,RX Msg Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" endif group.long (0x160+0x08)++0x07 line.long 0x00 "RX6_DH,CAN Rx Msg Upper Data Bytes" line.long 0x04 "RX6_DL,CAN Rx Msg Lower Data Bytes" if (((per.l(ad:0x402E0000+0x160+0x10))&0x4)==0x00) group.long (0x160+0x10)++0x03 line.long 0x00 "RX6_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0x160+0x10)++0x03 line.long 0x00 "RX6_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif if (((per.l(ad:0x402E0000+0x160+0x14))&0x4)==0x00) group.long (0x160+0x14)++0x03 line.long 0x00 "RX6_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0x160+0x14)++0x03 line.long 0x00 "RX6_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif group.long (0x160+0x18)++0x07 line.long 0x00 "RX6_AMRD,CAN Rx Acceptance mask data" hexmask.long.word 0x00 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" line.long 0x04 "RX6_ACRD,CAN Rx Acceptance code data" hexmask.long.word 0x04 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" group.long 0x180++0x03 "RX7" line.long 0x00 "RX7_CMD,CAN Rx Command Register" bitfld.long 0x00 23. " WPNH ,Write Protect Bit" "Not protected,Protected" bitfld.long 0x00 21. " RTR ,RTR Remote bit" "Standard,RTR" textline " " bitfld.long 0x00 20. " IDE ,Extended identifier" "Standard,Extended" bitfld.long 0x00 16.--19. " DLC ,Data Length of the Tx Msg" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" textline " " bitfld.long 0x00 7. " WPNL ,Write protect not Flag Bits 6:3" "Unchanged,Modified" bitfld.long 0x00 6. " LK_FLG ,Link Flag used to link the Rx Buffer" "Not linked,Linked" textline " " bitfld.long 0x00 5. " RX_INT_EBL ,Receive Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " RTR_RPLY ,Automatic RTR Message Handling" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " BUF_EBL ,Buffer Enable" "Disabled,Enabled" bitfld.long 0x00 2. " RTR_ABORT ,RTR Abort Request" "Idle,Requested" textline " " bitfld.long 0x00 1. " RTR_RPY_PND ,RTR Reply request Pending" "Not pending,Pending" bitfld.long 0x00 0. " MSG_AV ,Message Available" "Not available,Available" if (((per.l(ad:0x402E0000+0x180))&0x100000)==0x00) group.long (0x180+0x04)++0x03 line.long 0x00 "RX7_ID,CAN Rx Msg Identifier" bitfld.long 0x00 13. " ID ,Rx Msg Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" else group.long (0x180+0x04)++0x03 line.long 0x00 "RX7_ID,CAN Rx Msg Identifier" bitfld.long 0x00 31. " ID ,RX Msg Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" endif group.long (0x180+0x08)++0x07 line.long 0x00 "RX7_DH,CAN Rx Msg Upper Data Bytes" line.long 0x04 "RX7_DL,CAN Rx Msg Lower Data Bytes" if (((per.l(ad:0x402E0000+0x180+0x10))&0x4)==0x00) group.long (0x180+0x10)++0x03 line.long 0x00 "RX7_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0x180+0x10)++0x03 line.long 0x00 "RX7_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif if (((per.l(ad:0x402E0000+0x180+0x14))&0x4)==0x00) group.long (0x180+0x14)++0x03 line.long 0x00 "RX7_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0x180+0x14)++0x03 line.long 0x00 "RX7_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif group.long (0x180+0x18)++0x07 line.long 0x00 "RX7_AMRD,CAN Rx Acceptance mask data" hexmask.long.word 0x00 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" line.long 0x04 "RX7_ACRD,CAN Rx Acceptance code data" hexmask.long.word 0x04 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" group.long 0x1A0++0x03 "RX8" line.long 0x00 "RX8_CMD,CAN Rx Command Register" bitfld.long 0x00 23. " WPNH ,Write Protect Bit" "Not protected,Protected" bitfld.long 0x00 21. " RTR ,RTR Remote bit" "Standard,RTR" textline " " bitfld.long 0x00 20. " IDE ,Extended identifier" "Standard,Extended" bitfld.long 0x00 16.--19. " DLC ,Data Length of the Tx Msg" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" textline " " bitfld.long 0x00 7. " WPNL ,Write protect not Flag Bits 6:3" "Unchanged,Modified" bitfld.long 0x00 6. " LK_FLG ,Link Flag used to link the Rx Buffer" "Not linked,Linked" textline " " bitfld.long 0x00 5. " RX_INT_EBL ,Receive Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " RTR_RPLY ,Automatic RTR Message Handling" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " BUF_EBL ,Buffer Enable" "Disabled,Enabled" bitfld.long 0x00 2. " RTR_ABORT ,RTR Abort Request" "Idle,Requested" textline " " bitfld.long 0x00 1. " RTR_RPY_PND ,RTR Reply request Pending" "Not pending,Pending" bitfld.long 0x00 0. " MSG_AV ,Message Available" "Not available,Available" if (((per.l(ad:0x402E0000+0x1A0))&0x100000)==0x00) group.long (0x1A0+0x04)++0x03 line.long 0x00 "RX8_ID,CAN Rx Msg Identifier" bitfld.long 0x00 13. " ID ,Rx Msg Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" else group.long (0x1A0+0x04)++0x03 line.long 0x00 "RX8_ID,CAN Rx Msg Identifier" bitfld.long 0x00 31. " ID ,RX Msg Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" endif group.long (0x1A0+0x08)++0x07 line.long 0x00 "RX8_DH,CAN Rx Msg Upper Data Bytes" line.long 0x04 "RX8_DL,CAN Rx Msg Lower Data Bytes" if (((per.l(ad:0x402E0000+0x1A0+0x10))&0x4)==0x00) group.long (0x1A0+0x10)++0x03 line.long 0x00 "RX8_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0x1A0+0x10)++0x03 line.long 0x00 "RX8_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif if (((per.l(ad:0x402E0000+0x1A0+0x14))&0x4)==0x00) group.long (0x1A0+0x14)++0x03 line.long 0x00 "RX8_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0x1A0+0x14)++0x03 line.long 0x00 "RX8_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif group.long (0x1A0+0x18)++0x07 line.long 0x00 "RX8_AMRD,CAN Rx Acceptance mask data" hexmask.long.word 0x00 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" line.long 0x04 "RX8_ACRD,CAN Rx Acceptance code data" hexmask.long.word 0x04 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" group.long 0x1C0++0x03 "RX9" line.long 0x00 "RX9_CMD,CAN Rx Command Register" bitfld.long 0x00 23. " WPNH ,Write Protect Bit" "Not protected,Protected" bitfld.long 0x00 21. " RTR ,RTR Remote bit" "Standard,RTR" textline " " bitfld.long 0x00 20. " IDE ,Extended identifier" "Standard,Extended" bitfld.long 0x00 16.--19. " DLC ,Data Length of the Tx Msg" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" textline " " bitfld.long 0x00 7. " WPNL ,Write protect not Flag Bits 6:3" "Unchanged,Modified" bitfld.long 0x00 6. " LK_FLG ,Link Flag used to link the Rx Buffer" "Not linked,Linked" textline " " bitfld.long 0x00 5. " RX_INT_EBL ,Receive Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " RTR_RPLY ,Automatic RTR Message Handling" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " BUF_EBL ,Buffer Enable" "Disabled,Enabled" bitfld.long 0x00 2. " RTR_ABORT ,RTR Abort Request" "Idle,Requested" textline " " bitfld.long 0x00 1. " RTR_RPY_PND ,RTR Reply request Pending" "Not pending,Pending" bitfld.long 0x00 0. " MSG_AV ,Message Available" "Not available,Available" if (((per.l(ad:0x402E0000+0x1C0))&0x100000)==0x00) group.long (0x1C0+0x04)++0x03 line.long 0x00 "RX9_ID,CAN Rx Msg Identifier" bitfld.long 0x00 13. " ID ,Rx Msg Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" else group.long (0x1C0+0x04)++0x03 line.long 0x00 "RX9_ID,CAN Rx Msg Identifier" bitfld.long 0x00 31. " ID ,RX Msg Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" endif group.long (0x1C0+0x08)++0x07 line.long 0x00 "RX9_DH,CAN Rx Msg Upper Data Bytes" line.long 0x04 "RX9_DL,CAN Rx Msg Lower Data Bytes" if (((per.l(ad:0x402E0000+0x1C0+0x10))&0x4)==0x00) group.long (0x1C0+0x10)++0x03 line.long 0x00 "RX9_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0x1C0+0x10)++0x03 line.long 0x00 "RX9_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif if (((per.l(ad:0x402E0000+0x1C0+0x14))&0x4)==0x00) group.long (0x1C0+0x14)++0x03 line.long 0x00 "RX9_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0x1C0+0x14)++0x03 line.long 0x00 "RX9_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif group.long (0x1C0+0x18)++0x07 line.long 0x00 "RX9_AMRD,CAN Rx Acceptance mask data" hexmask.long.word 0x00 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" line.long 0x04 "RX9_ACRD,CAN Rx Acceptance code data" hexmask.long.word 0x04 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" group.long 0x1E0++0x03 "RX10" line.long 0x00 "RX10_CMD,CAN Rx Command Register" bitfld.long 0x00 23. " WPNH ,Write Protect Bit" "Not protected,Protected" bitfld.long 0x00 21. " RTR ,RTR Remote bit" "Standard,RTR" textline " " bitfld.long 0x00 20. " IDE ,Extended identifier" "Standard,Extended" bitfld.long 0x00 16.--19. " DLC ,Data Length of the Tx Msg" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" textline " " bitfld.long 0x00 7. " WPNL ,Write protect not Flag Bits 6:3" "Unchanged,Modified" bitfld.long 0x00 6. " LK_FLG ,Link Flag used to link the Rx Buffer" "Not linked,Linked" textline " " bitfld.long 0x00 5. " RX_INT_EBL ,Receive Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " RTR_RPLY ,Automatic RTR Message Handling" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " BUF_EBL ,Buffer Enable" "Disabled,Enabled" bitfld.long 0x00 2. " RTR_ABORT ,RTR Abort Request" "Idle,Requested" textline " " bitfld.long 0x00 1. " RTR_RPY_PND ,RTR Reply request Pending" "Not pending,Pending" bitfld.long 0x00 0. " MSG_AV ,Message Available" "Not available,Available" if (((per.l(ad:0x402E0000+0x1E0))&0x100000)==0x00) group.long (0x1E0+0x04)++0x03 line.long 0x00 "RX10_ID,CAN Rx Msg Identifier" bitfld.long 0x00 13. " ID ,Rx Msg Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" else group.long (0x1E0+0x04)++0x03 line.long 0x00 "RX10_ID,CAN Rx Msg Identifier" bitfld.long 0x00 31. " ID ,RX Msg Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" endif group.long (0x1E0+0x08)++0x07 line.long 0x00 "RX10_DH,CAN Rx Msg Upper Data Bytes" line.long 0x04 "RX10_DL,CAN Rx Msg Lower Data Bytes" if (((per.l(ad:0x402E0000+0x1E0+0x10))&0x4)==0x00) group.long (0x1E0+0x10)++0x03 line.long 0x00 "RX10_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0x1E0+0x10)++0x03 line.long 0x00 "RX10_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif if (((per.l(ad:0x402E0000+0x1E0+0x14))&0x4)==0x00) group.long (0x1E0+0x14)++0x03 line.long 0x00 "RX10_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0x1E0+0x14)++0x03 line.long 0x00 "RX10_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif group.long (0x1E0+0x18)++0x07 line.long 0x00 "RX10_AMRD,CAN Rx Acceptance mask data" hexmask.long.word 0x00 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" line.long 0x04 "RX10_ACRD,CAN Rx Acceptance code data" hexmask.long.word 0x04 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" group.long 0x200++0x03 "RX11" line.long 0x00 "RX11_CMD,CAN Rx Command Register" bitfld.long 0x00 23. " WPNH ,Write Protect Bit" "Not protected,Protected" bitfld.long 0x00 21. " RTR ,RTR Remote bit" "Standard,RTR" textline " " bitfld.long 0x00 20. " IDE ,Extended identifier" "Standard,Extended" bitfld.long 0x00 16.--19. " DLC ,Data Length of the Tx Msg" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" textline " " bitfld.long 0x00 7. " WPNL ,Write protect not Flag Bits 6:3" "Unchanged,Modified" bitfld.long 0x00 6. " LK_FLG ,Link Flag used to link the Rx Buffer" "Not linked,Linked" textline " " bitfld.long 0x00 5. " RX_INT_EBL ,Receive Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " RTR_RPLY ,Automatic RTR Message Handling" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " BUF_EBL ,Buffer Enable" "Disabled,Enabled" bitfld.long 0x00 2. " RTR_ABORT ,RTR Abort Request" "Idle,Requested" textline " " bitfld.long 0x00 1. " RTR_RPY_PND ,RTR Reply request Pending" "Not pending,Pending" bitfld.long 0x00 0. " MSG_AV ,Message Available" "Not available,Available" if (((per.l(ad:0x402E0000+0x200))&0x100000)==0x00) group.long (0x200+0x04)++0x03 line.long 0x00 "RX11_ID,CAN Rx Msg Identifier" bitfld.long 0x00 13. " ID ,Rx Msg Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" else group.long (0x200+0x04)++0x03 line.long 0x00 "RX11_ID,CAN Rx Msg Identifier" bitfld.long 0x00 31. " ID ,RX Msg Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" endif group.long (0x200+0x08)++0x07 line.long 0x00 "RX11_DH,CAN Rx Msg Upper Data Bytes" line.long 0x04 "RX11_DL,CAN Rx Msg Lower Data Bytes" if (((per.l(ad:0x402E0000+0x200+0x10))&0x4)==0x00) group.long (0x200+0x10)++0x03 line.long 0x00 "RX11_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0x200+0x10)++0x03 line.long 0x00 "RX11_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif if (((per.l(ad:0x402E0000+0x200+0x14))&0x4)==0x00) group.long (0x200+0x14)++0x03 line.long 0x00 "RX11_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0x200+0x14)++0x03 line.long 0x00 "RX11_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif group.long (0x200+0x18)++0x07 line.long 0x00 "RX11_AMRD,CAN Rx Acceptance mask data" hexmask.long.word 0x00 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" line.long 0x04 "RX11_ACRD,CAN Rx Acceptance code data" hexmask.long.word 0x04 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" group.long 0x220++0x03 "RX12" line.long 0x00 "RX12_CMD,CAN Rx Command Register" bitfld.long 0x00 23. " WPNH ,Write Protect Bit" "Not protected,Protected" bitfld.long 0x00 21. " RTR ,RTR Remote bit" "Standard,RTR" textline " " bitfld.long 0x00 20. " IDE ,Extended identifier" "Standard,Extended" bitfld.long 0x00 16.--19. " DLC ,Data Length of the Tx Msg" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" textline " " bitfld.long 0x00 7. " WPNL ,Write protect not Flag Bits 6:3" "Unchanged,Modified" bitfld.long 0x00 6. " LK_FLG ,Link Flag used to link the Rx Buffer" "Not linked,Linked" textline " " bitfld.long 0x00 5. " RX_INT_EBL ,Receive Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " RTR_RPLY ,Automatic RTR Message Handling" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " BUF_EBL ,Buffer Enable" "Disabled,Enabled" bitfld.long 0x00 2. " RTR_ABORT ,RTR Abort Request" "Idle,Requested" textline " " bitfld.long 0x00 1. " RTR_RPY_PND ,RTR Reply request Pending" "Not pending,Pending" bitfld.long 0x00 0. " MSG_AV ,Message Available" "Not available,Available" if (((per.l(ad:0x402E0000+0x220))&0x100000)==0x00) group.long (0x220+0x04)++0x03 line.long 0x00 "RX12_ID,CAN Rx Msg Identifier" bitfld.long 0x00 13. " ID ,Rx Msg Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" else group.long (0x220+0x04)++0x03 line.long 0x00 "RX12_ID,CAN Rx Msg Identifier" bitfld.long 0x00 31. " ID ,RX Msg Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" endif group.long (0x220+0x08)++0x07 line.long 0x00 "RX12_DH,CAN Rx Msg Upper Data Bytes" line.long 0x04 "RX12_DL,CAN Rx Msg Lower Data Bytes" if (((per.l(ad:0x402E0000+0x220+0x10))&0x4)==0x00) group.long (0x220+0x10)++0x03 line.long 0x00 "RX12_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0x220+0x10)++0x03 line.long 0x00 "RX12_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif if (((per.l(ad:0x402E0000+0x220+0x14))&0x4)==0x00) group.long (0x220+0x14)++0x03 line.long 0x00 "RX12_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0x220+0x14)++0x03 line.long 0x00 "RX12_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif group.long (0x220+0x18)++0x07 line.long 0x00 "RX12_AMRD,CAN Rx Acceptance mask data" hexmask.long.word 0x00 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" line.long 0x04 "RX12_ACRD,CAN Rx Acceptance code data" hexmask.long.word 0x04 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" group.long 0x240++0x03 "RX13" line.long 0x00 "RX13_CMD,CAN Rx Command Register" bitfld.long 0x00 23. " WPNH ,Write Protect Bit" "Not protected,Protected" bitfld.long 0x00 21. " RTR ,RTR Remote bit" "Standard,RTR" textline " " bitfld.long 0x00 20. " IDE ,Extended identifier" "Standard,Extended" bitfld.long 0x00 16.--19. " DLC ,Data Length of the Tx Msg" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" textline " " bitfld.long 0x00 7. " WPNL ,Write protect not Flag Bits 6:3" "Unchanged,Modified" bitfld.long 0x00 6. " LK_FLG ,Link Flag used to link the Rx Buffer" "Not linked,Linked" textline " " bitfld.long 0x00 5. " RX_INT_EBL ,Receive Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " RTR_RPLY ,Automatic RTR Message Handling" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " BUF_EBL ,Buffer Enable" "Disabled,Enabled" bitfld.long 0x00 2. " RTR_ABORT ,RTR Abort Request" "Idle,Requested" textline " " bitfld.long 0x00 1. " RTR_RPY_PND ,RTR Reply request Pending" "Not pending,Pending" bitfld.long 0x00 0. " MSG_AV ,Message Available" "Not available,Available" if (((per.l(ad:0x402E0000+0x240))&0x100000)==0x00) group.long (0x240+0x04)++0x03 line.long 0x00 "RX13_ID,CAN Rx Msg Identifier" bitfld.long 0x00 13. " ID ,Rx Msg Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" else group.long (0x240+0x04)++0x03 line.long 0x00 "RX13_ID,CAN Rx Msg Identifier" bitfld.long 0x00 31. " ID ,RX Msg Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" endif group.long (0x240+0x08)++0x07 line.long 0x00 "RX13_DH,CAN Rx Msg Upper Data Bytes" line.long 0x04 "RX13_DL,CAN Rx Msg Lower Data Bytes" if (((per.l(ad:0x402E0000+0x240+0x10))&0x4)==0x00) group.long (0x240+0x10)++0x03 line.long 0x00 "RX13_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0x240+0x10)++0x03 line.long 0x00 "RX13_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif if (((per.l(ad:0x402E0000+0x240+0x14))&0x4)==0x00) group.long (0x240+0x14)++0x03 line.long 0x00 "RX13_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0x240+0x14)++0x03 line.long 0x00 "RX13_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif group.long (0x240+0x18)++0x07 line.long 0x00 "RX13_AMRD,CAN Rx Acceptance mask data" hexmask.long.word 0x00 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" line.long 0x04 "RX13_ACRD,CAN Rx Acceptance code data" hexmask.long.word 0x04 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" group.long 0x260++0x03 "RX14" line.long 0x00 "RX14_CMD,CAN Rx Command Register" bitfld.long 0x00 23. " WPNH ,Write Protect Bit" "Not protected,Protected" bitfld.long 0x00 21. " RTR ,RTR Remote bit" "Standard,RTR" textline " " bitfld.long 0x00 20. " IDE ,Extended identifier" "Standard,Extended" bitfld.long 0x00 16.--19. " DLC ,Data Length of the Tx Msg" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" textline " " bitfld.long 0x00 7. " WPNL ,Write protect not Flag Bits 6:3" "Unchanged,Modified" bitfld.long 0x00 6. " LK_FLG ,Link Flag used to link the Rx Buffer" "Not linked,Linked" textline " " bitfld.long 0x00 5. " RX_INT_EBL ,Receive Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " RTR_RPLY ,Automatic RTR Message Handling" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " BUF_EBL ,Buffer Enable" "Disabled,Enabled" bitfld.long 0x00 2. " RTR_ABORT ,RTR Abort Request" "Idle,Requested" textline " " bitfld.long 0x00 1. " RTR_RPY_PND ,RTR Reply request Pending" "Not pending,Pending" bitfld.long 0x00 0. " MSG_AV ,Message Available" "Not available,Available" if (((per.l(ad:0x402E0000+0x260))&0x100000)==0x00) group.long (0x260+0x04)++0x03 line.long 0x00 "RX14_ID,CAN Rx Msg Identifier" bitfld.long 0x00 13. " ID ,Rx Msg Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" else group.long (0x260+0x04)++0x03 line.long 0x00 "RX14_ID,CAN Rx Msg Identifier" bitfld.long 0x00 31. " ID ,RX Msg Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" endif group.long (0x260+0x08)++0x07 line.long 0x00 "RX14_DH,CAN Rx Msg Upper Data Bytes" line.long 0x04 "RX14_DL,CAN Rx Msg Lower Data Bytes" if (((per.l(ad:0x402E0000+0x260+0x10))&0x4)==0x00) group.long (0x260+0x10)++0x03 line.long 0x00 "RX14_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0x260+0x10)++0x03 line.long 0x00 "RX14_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif if (((per.l(ad:0x402E0000+0x260+0x14))&0x4)==0x00) group.long (0x260+0x14)++0x03 line.long 0x00 "RX14_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0x260+0x14)++0x03 line.long 0x00 "RX14_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif group.long (0x260+0x18)++0x07 line.long 0x00 "RX14_AMRD,CAN Rx Acceptance mask data" hexmask.long.word 0x00 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" line.long 0x04 "RX14_ACRD,CAN Rx Acceptance code data" hexmask.long.word 0x04 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" group.long 0x280++0x03 "RX15" line.long 0x00 "RX15_CMD,CAN Rx Command Register" bitfld.long 0x00 23. " WPNH ,Write Protect Bit" "Not protected,Protected" bitfld.long 0x00 21. " RTR ,RTR Remote bit" "Standard,RTR" textline " " bitfld.long 0x00 20. " IDE ,Extended identifier" "Standard,Extended" bitfld.long 0x00 16.--19. " DLC ,Data Length of the Tx Msg" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" textline " " bitfld.long 0x00 7. " WPNL ,Write protect not Flag Bits 6:3" "Unchanged,Modified" bitfld.long 0x00 6. " LK_FLG ,Link Flag used to link the Rx Buffer" "Not linked,Linked" textline " " bitfld.long 0x00 5. " RX_INT_EBL ,Receive Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " RTR_RPLY ,Automatic RTR Message Handling" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " BUF_EBL ,Buffer Enable" "Disabled,Enabled" bitfld.long 0x00 2. " RTR_ABORT ,RTR Abort Request" "Idle,Requested" textline " " bitfld.long 0x00 1. " RTR_RPY_PND ,RTR Reply request Pending" "Not pending,Pending" bitfld.long 0x00 0. " MSG_AV ,Message Available" "Not available,Available" if (((per.l(ad:0x402E0000+0x280))&0x100000)==0x00) group.long (0x280+0x04)++0x03 line.long 0x00 "RX15_ID,CAN Rx Msg Identifier" bitfld.long 0x00 13. " ID ,Rx Msg Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" else group.long (0x280+0x04)++0x03 line.long 0x00 "RX15_ID,CAN Rx Msg Identifier" bitfld.long 0x00 31. " ID ,RX Msg Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" endif group.long (0x280+0x08)++0x07 line.long 0x00 "RX15_DH,CAN Rx Msg Upper Data Bytes" line.long 0x04 "RX15_DL,CAN Rx Msg Lower Data Bytes" if (((per.l(ad:0x402E0000+0x280+0x10))&0x4)==0x00) group.long (0x280+0x10)++0x03 line.long 0x00 "RX15_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0x280+0x10)++0x03 line.long 0x00 "RX15_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif if (((per.l(ad:0x402E0000+0x280+0x14))&0x4)==0x00) group.long (0x280+0x14)++0x03 line.long 0x00 "RX15_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0x280+0x14)++0x03 line.long 0x00 "RX15_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif group.long (0x280+0x18)++0x07 line.long 0x00 "RX15_AMRD,CAN Rx Acceptance mask data" hexmask.long.word 0x00 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" line.long 0x04 "RX15_ACRD,CAN Rx Acceptance code data" hexmask.long.word 0x04 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" tree.end width 0x0B tree.end tree "CAN1" base ad:0x402F0000 width 18. tree "CSR" group.long 0x00++0x07 line.long 0x00 "INT_SR,Interrupt Status Register" sif (cpuis("CY8C424?BZI-L489")||cpuis("CY8C424??ZI-L485")||cpuis("CY8C424?LTI-L485")) eventfld.long 0x00 15. " SST_FAILURE ,Single shot transmission failure Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 14. " STUCK_AT_0 ,Stuck at dominant error Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 13. " RTR_MSG ,RTR auto-reply Msg sent Interrupt" "No interrupt,Interrupt" textline " " endif eventfld.long 0x00 12. " RX_MSG ,Msg received" "No interrupt,Interrupt" eventfld.long 0x00 11. " TX_MSG ,Tx Msg Sent" "No interrupt,Interrupt" textline " " eventfld.long 0x00 10. " RX_MSG_LOSS ,Rx Msg loss Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 9. " BUS_OFF ,Bus Off State" "No interrupt,Interrupt" textline " " eventfld.long 0x00 8. " CRC_ERR ,CRC Error Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 7. " FORM_ERR ,Form Error Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 6. " ACK_ERR ,Ack Error Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 5. " STUFF_ERR ,Stuff Error Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 4. " BIT_ERR ,Bit Error Interrupt" "No interrupt,Interrupt" eventfld.long 0x00 3. " OVR_LOAD ,Overload Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 2. " ARB_LOSS ,Arbitration Loss" "No interrupt,Interrupt" line.long 0x04 "INT_EN,Interrupt Enable Register" sif (cpuis("CY8C424?BZI-L489")||cpuis("CY8C424??ZI-L485")||cpuis("CY8C424?LTI-L485")) bitfld.long 0x04 15. " SST_FAILURE ,Single shot transmission failure Interrupt" "Disabled,Enabled" textline " " bitfld.long 0x04 14. " STUCK_AT_0 ,Stuck at dominant error Interrupt" "Disabled,Enabled" bitfld.long 0x04 13. " RTR_MSG ,RTR auto-reply Msg sent Interrupt" "Disabled,Enabled" textline " " endif bitfld.long 0x04 12. " RX_MSG ,Msg received Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 11. " TX_MSG ,Tx Msg Sent Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 10. " RX_MSG_LOSS ,Rx Msg Loss Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 9. " BUS_OFF ,Busoff State Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 8. " CRC_ERR ,CRC Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 7. " FORM_ERR ,Form Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 6. " ACK_ERR ,Ack Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 5. " STUFF_ERR ,Stuff Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 4. " BIT_ERR ,Bit Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 3. " OVR_LOAD ,Overload Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 2. " ARB_LOSS ,Arbitration Loss Interrupt Enable" "Disabled,Enabled" bitfld.long 0x04 0. " INT_EBL ,Global Interrupt Enable Flag" "Disabled,Enabled" hgroup.long 0x08++0x03 hide.long 0x00 "BUF_SR,Buffer Status Register" in rgroup.long 0x0c++0x03 line.long 0x00 "ERR_SR,Error Status Register" bitfld.long 0x00 19. " RXGTE96 ,Rx Error Count is greater or equal to 96 Decimal" "Equal,Greater" bitfld.long 0x00 18. " TXGTE96 ,Tx Error Count is greater or equal to 96 Decimal" "Equal,Greater" textline " " bitfld.long 0x00 16.--17. " ERR_STATE ,Error State of CAN node" "Active,Passive,Buss off,Buss off" hexmask.long.byte 0x00 8.--15. 1. " RX_ERR_CNT ,Rx error Count" textline " " hexmask.long.byte 0x00 0.--7. 1. " TX_ERR_CNT ,Tx error Count" group.long 0x10++0x07 line.long 0x00 "CMD,Command Register" sif (cpuis("CY8C424?BZI-L489")||cpuis("CY8C424??ZI-L485")||cpuis("CY8C424?LTI-L485")) bitfld.long 0x00 28.--31. " IP_MAJOR_VERSION ,IP Major Version Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " IP_MINOR_VERSION ,IP Minor Version Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x00 16.--23. 1. " IP_REV_NUMBER ,IP Revision Number" bitfld.long 0x00 3. " SRAM_TEST ,SRAM test Mode" "Normal,Enabled" textline " " bitfld.long 0x00 1.--2. " TEST_MODE ,Loopback[2]/Listen[1] Test mode" "Normal,Listen-only,External loopback,Internal loopback" bitfld.long 0x00 0. " RUN_STOP ,Run/Stop mode" "Stop,Run" else bitfld.long 0x00 3. " SRAM_TEST ,SRAM test Mode" "Normal,Enabled" bitfld.long 0x00 1. " LISTEN ,Listen only mode" "Active,CAN listen only" textline " " bitfld.long 0x00 0. " RUN_STOP ,Run/Stop mode" "Stop,Run" endif line.long 0x04 "CFG,Configuration Register" hexmask.long.word 0x04 16.--30. 1. " CFG_BITRATE ,CAN configuration Bit rate" sif (cpuis("CY8C424?BZI-L489")||cpuis("CY8C424??ZI-L485")||cpuis("CY8C424?LTI-L485")) bitfld.long 0x04 14. " ECR_MODE ,Error Capture mode" "Free running,Capture mode" textline " " bitfld.long 0x04 13. " SWAP_ENDIAN ,Swap Endian" "Big endian,Little endian" endif bitfld.long 0x04 12. " CFG_ARBITER ,Tx buffer Arbiter" "Round robin,Fixed priority" textline " " bitfld.long 0x04 8.--11. " CFG_TSEG1 ,Length of time segment1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 5.--7. " CFG_TSEG2 ,Length of time segment2" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x04 4. " AUTO_RST ,Auto Restart" "Disabled,Enabled" bitfld.long 0x04 2.--3. " CFG_SJW ,Synchronization Jump Width" "0,1,2,3" textline " " bitfld.long 0x04 1. " SAMPLING_MODE ,CAN bus Bit sampling" "1 point,3 points" bitfld.long 0x04 0. " EDGE_MODE ,CAN bus synchronization logic" "Edge from 'R' to 'D',Both" sif (cpuis("CY8C424?BZI-L489")||cpuis("CY8C424??ZI-L485")||cpuis("CY8C424?LTI-L485")) rgroup.long 0x18++0x03 line.long 0x00 "ECR,Error Capture Register" bitfld.long 0x00 12.--16. " FIELD ,Error capture field" "Stopped,Synchronize,,,,Interframe,Bus Idle,Start of Frame,Arbitration,Control,Data,CRC,ACK,End of frame,,,Error flag,Error echo,Error delimiter,,,,,,Overload flag,Overload echo,Overload delimiter,?..." bitfld.long 0x00 6.--11. " BIT ,Bit number inside of Field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 5. " TX_MODE ,Tx Mode" "No status,Transmitter" bitfld.long 0x00 4. " RX_MODE ,Rx Mode" "No status,Receiver" textline " " bitfld.long 0x00 1.--3. " ERROR_TYPE ,Error type" "Arbitration loss,Bit Error,Bit Stuffing Error,Acknowledge Error,Form Error,CRC Error,?..." bitfld.long 0x00 0. " ECR_STATUS ,ECR Status" "Error/Free running,No error" group.long 0x400++0x17 line.long 0x00 "CNTL,Control Register" bitfld.long 0x00 31. " IP_ENABLE ,Can enable" "Disabled/Reset,Enabled/Running" bitfld.long 0x00 0. " TT_ENABLE ,TTCAN enable" "Disabled,Enabled" line.long 0x04 "TTCAN_COUNTER,TTCAN Level1 16-Bit Local Time Counter Register" hexmask.long.word 0x04 16.--31. 1. " LOCAL_TIME ,Bit time counter in TTCAN level 1" line.long 0x08 "TTCAN_COMPARE, Level1 Compare Configuration Register" hexmask.long.word 0x08 16.--31. 1. " TIME_MARK ,Compare target" line.long 0x0C "TTCAN_CAPTURE,TTCAN Level1 Capture Configuration Register" hexmask.long.word 0x0C 16.--31. 1. " SYNC_MARK ,Copy TTCAN_COUNTER.LOCAL_TIME, when SOF detected" line.long 0x10 "TTCAN_TIMING,TTCAN Level1 Timing Configuration Register" hexmask.long.word 0x10 16.--30. 1. " CFG_BITRATE ,Prescaler for generating the time quantum" bitfld.long 0x10 8.--11. " CFG_TSEG1 ,Time segment 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x10 5.--7. " CFG_TSEG2 ,Time segment 2" "0,1,2,3,4,5,6,7" bitfld.long 0x10 1. " SAMPLING_MODE ,CAN bus bit sampling" "One point,3 points" line.long 0x14 "INTR_CAN_set/clr,CAN Interrupt Cause Register" setclrfld.long 0x14 2. 0x18 2. 0x14 2. " TT_CAPTURE , TT Capture Interrupt" "No interrupt,Interrupt" setclrfld.long 0x14 1. 0x18 1. 0x14 1. " TT_COMPARE , TT Compare Interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x14 0. 0x18 0. 0x14 0. " INT_STATUS , INT_Status Interrupt" "No interrupt,Interrupt" group.long 0x41C++0x03 line.long 0x00 "INTR_CAN_MASK,Can Interrupt Mask Register" bitfld.long 0x00 2. " TT_CAPTURE ,TT_CAPTURE Interrupt mask" "Not masked,Masked" bitfld.long 0x00 1. " TT_COMPARE ,TT_COMPARE Interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 0. " INT_STATUS ,INT_STATUS Interrupt mask" "Not masked,Masked" rgroup.long 0x420++0x03 line.long 0x00 "INTR_CAN_MASKED,Can Interrupt Masked Register" bitfld.long 0x00 2. " TT_CAPTURE ,Logical and of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 1. " TT_COMPARE ,Logical and of corresponding request and mask bits" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " INT_STATUS ,Logical and of corresponding request and mask bits" "No interrupt,Interrupt" endif tree.end width 9. tree "TX Registers" group.long 0x20++0x03 "TX0" line.long 0x00 "TX0_CMD,CAN Tx Command Register" bitfld.long 0x00 23. " WPN2 ,Write protect bit" "Not protected,Protected" bitfld.long 0x00 21. " RTR ,RTR remote bit" "Standard,RTR" textline " " bitfld.long 0x00 20. " IDE ,Extended identifier" "Standard,Extended" bitfld.long 0x00 16.--19. " DLC ,Data length of the Tx Msg" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" textline " " bitfld.long 0x00 3. " WPN1 ,Write protect not flag bit 2" "Unchanged,Modified" bitfld.long 0x00 2. " TXINT_EBL ,Transmit interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Requested" bitfld.long 0x00 0. " TXREQ ,Transmit request" "Idle,Requested" if (((per.l(ad:0x402F0000+0x20))&0x100000)==0x00) group.long (0x20+0x04)++0x03 line.long 0x00 "TX0_ID,CAN Tx Msg Identifier" bitfld.long 0x00 13. " ID ,Tx0 Msg Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Tx0 Msg Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Tx0 Msg Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Tx0 Msg Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Tx0 Msg Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Tx0 Msg Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Tx0 Msg Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Tx0 Msg Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Tx0 Msg Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Tx0 Msg Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Tx0 Msg Identifier bit 0" "0,1" else group.long (0x20+0x04)++0x03 line.long 0x00 "TX0_ID,CAN Tx Msg Identifier" bitfld.long 0x00 31. " ID ,Tx0 Msg Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Tx0 Msg Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Tx0 Msg Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Tx0 Msg Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Tx0 Msg Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Tx0 Msg Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Tx0 Msg Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Tx0 Msg Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Tx0 Msg Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Tx0 Msg Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Tx0 Msg Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Tx0 Msg Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Tx0 Msg Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Tx0 Msg Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Tx0 Msg Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Tx0 Msg Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Tx0 Msg Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Tx0 Msg Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Tx0 Msg Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Tx0 Msg Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Tx0 Msg Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Tx0 Msg Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Tx0 Msg Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Tx0 Msg Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Tx0 Msg Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Tx0 Msg Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Tx0 Msg Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Tx0 Msg Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Tx0 Msg Identifier bit 0" "0,1" endif group.long (0x20+0x08)++0x07 line.long 0x00 "TX0_DH,CAN Tx Msg Upper Data Bytes" line.long 0x04 "TX0_DL,CAN Tx Msg Lower Data Bytes" group.long 0x30++0x03 "TX1" line.long 0x00 "TX1_CMD,CAN Tx Command Register" bitfld.long 0x00 23. " WPN2 ,Write protect bit" "Not protected,Protected" bitfld.long 0x00 21. " RTR ,RTR remote bit" "Standard,RTR" textline " " bitfld.long 0x00 20. " IDE ,Extended identifier" "Standard,Extended" bitfld.long 0x00 16.--19. " DLC ,Data length of the Tx Msg" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" textline " " bitfld.long 0x00 3. " WPN1 ,Write protect not flag bit 2" "Unchanged,Modified" bitfld.long 0x00 2. " TXINT_EBL ,Transmit interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Requested" bitfld.long 0x00 0. " TXREQ ,Transmit request" "Idle,Requested" if (((per.l(ad:0x402F0000+0x30))&0x100000)==0x00) group.long (0x30+0x04)++0x03 line.long 0x00 "TX1_ID,CAN Tx Msg Identifier" bitfld.long 0x00 13. " ID ,Tx1 Msg Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Tx1 Msg Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Tx1 Msg Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Tx1 Msg Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Tx1 Msg Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Tx1 Msg Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Tx1 Msg Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Tx1 Msg Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Tx1 Msg Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Tx1 Msg Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Tx1 Msg Identifier bit 0" "0,1" else group.long (0x30+0x04)++0x03 line.long 0x00 "TX1_ID,CAN Tx Msg Identifier" bitfld.long 0x00 31. " ID ,Tx1 Msg Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Tx1 Msg Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Tx1 Msg Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Tx1 Msg Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Tx1 Msg Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Tx1 Msg Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Tx1 Msg Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Tx1 Msg Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Tx1 Msg Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Tx1 Msg Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Tx1 Msg Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Tx1 Msg Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Tx1 Msg Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Tx1 Msg Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Tx1 Msg Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Tx1 Msg Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Tx1 Msg Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Tx1 Msg Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Tx1 Msg Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Tx1 Msg Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Tx1 Msg Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Tx1 Msg Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Tx1 Msg Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Tx1 Msg Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Tx1 Msg Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Tx1 Msg Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Tx1 Msg Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Tx1 Msg Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Tx1 Msg Identifier bit 0" "0,1" endif group.long (0x30+0x08)++0x07 line.long 0x00 "TX1_DH,CAN Tx Msg Upper Data Bytes" line.long 0x04 "TX1_DL,CAN Tx Msg Lower Data Bytes" group.long 0x40++0x03 "TX2" line.long 0x00 "TX2_CMD,CAN Tx Command Register" bitfld.long 0x00 23. " WPN2 ,Write protect bit" "Not protected,Protected" bitfld.long 0x00 21. " RTR ,RTR remote bit" "Standard,RTR" textline " " bitfld.long 0x00 20. " IDE ,Extended identifier" "Standard,Extended" bitfld.long 0x00 16.--19. " DLC ,Data length of the Tx Msg" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" textline " " bitfld.long 0x00 3. " WPN1 ,Write protect not flag bit 2" "Unchanged,Modified" bitfld.long 0x00 2. " TXINT_EBL ,Transmit interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Requested" bitfld.long 0x00 0. " TXREQ ,Transmit request" "Idle,Requested" if (((per.l(ad:0x402F0000+0x40))&0x100000)==0x00) group.long (0x40+0x04)++0x03 line.long 0x00 "TX2_ID,CAN Tx Msg Identifier" bitfld.long 0x00 13. " ID ,Tx2 Msg Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Tx2 Msg Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Tx2 Msg Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Tx2 Msg Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Tx2 Msg Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Tx2 Msg Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Tx2 Msg Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Tx2 Msg Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Tx2 Msg Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Tx2 Msg Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Tx2 Msg Identifier bit 0" "0,1" else group.long (0x40+0x04)++0x03 line.long 0x00 "TX2_ID,CAN Tx Msg Identifier" bitfld.long 0x00 31. " ID ,Tx2 Msg Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Tx2 Msg Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Tx2 Msg Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Tx2 Msg Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Tx2 Msg Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Tx2 Msg Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Tx2 Msg Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Tx2 Msg Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Tx2 Msg Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Tx2 Msg Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Tx2 Msg Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Tx2 Msg Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Tx2 Msg Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Tx2 Msg Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Tx2 Msg Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Tx2 Msg Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Tx2 Msg Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Tx2 Msg Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Tx2 Msg Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Tx2 Msg Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Tx2 Msg Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Tx2 Msg Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Tx2 Msg Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Tx2 Msg Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Tx2 Msg Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Tx2 Msg Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Tx2 Msg Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Tx2 Msg Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Tx2 Msg Identifier bit 0" "0,1" endif group.long (0x40+0x08)++0x07 line.long 0x00 "TX2_DH,CAN Tx Msg Upper Data Bytes" line.long 0x04 "TX2_DL,CAN Tx Msg Lower Data Bytes" group.long 0x50++0x03 "TX3" line.long 0x00 "TX3_CMD,CAN Tx Command Register" bitfld.long 0x00 23. " WPN2 ,Write protect bit" "Not protected,Protected" bitfld.long 0x00 21. " RTR ,RTR remote bit" "Standard,RTR" textline " " bitfld.long 0x00 20. " IDE ,Extended identifier" "Standard,Extended" bitfld.long 0x00 16.--19. " DLC ,Data length of the Tx Msg" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" textline " " bitfld.long 0x00 3. " WPN1 ,Write protect not flag bit 2" "Unchanged,Modified" bitfld.long 0x00 2. " TXINT_EBL ,Transmit interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Requested" bitfld.long 0x00 0. " TXREQ ,Transmit request" "Idle,Requested" if (((per.l(ad:0x402F0000+0x50))&0x100000)==0x00) group.long (0x50+0x04)++0x03 line.long 0x00 "TX3_ID,CAN Tx Msg Identifier" bitfld.long 0x00 13. " ID ,Tx3 Msg Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Tx3 Msg Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Tx3 Msg Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Tx3 Msg Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Tx3 Msg Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Tx3 Msg Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Tx3 Msg Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Tx3 Msg Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Tx3 Msg Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Tx3 Msg Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Tx3 Msg Identifier bit 0" "0,1" else group.long (0x50+0x04)++0x03 line.long 0x00 "TX3_ID,CAN Tx Msg Identifier" bitfld.long 0x00 31. " ID ,Tx3 Msg Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Tx3 Msg Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Tx3 Msg Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Tx3 Msg Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Tx3 Msg Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Tx3 Msg Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Tx3 Msg Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Tx3 Msg Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Tx3 Msg Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Tx3 Msg Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Tx3 Msg Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Tx3 Msg Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Tx3 Msg Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Tx3 Msg Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Tx3 Msg Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Tx3 Msg Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Tx3 Msg Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Tx3 Msg Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Tx3 Msg Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Tx3 Msg Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Tx3 Msg Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Tx3 Msg Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Tx3 Msg Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Tx3 Msg Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Tx3 Msg Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Tx3 Msg Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Tx3 Msg Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Tx3 Msg Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Tx3 Msg Identifier bit 0" "0,1" endif group.long (0x50+0x08)++0x07 line.long 0x00 "TX3_DH,CAN Tx Msg Upper Data Bytes" line.long 0x04 "TX3_DL,CAN Tx Msg Lower Data Bytes" group.long 0x60++0x03 "TX4" line.long 0x00 "TX4_CMD,CAN Tx Command Register" bitfld.long 0x00 23. " WPN2 ,Write protect bit" "Not protected,Protected" bitfld.long 0x00 21. " RTR ,RTR remote bit" "Standard,RTR" textline " " bitfld.long 0x00 20. " IDE ,Extended identifier" "Standard,Extended" bitfld.long 0x00 16.--19. " DLC ,Data length of the Tx Msg" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" textline " " bitfld.long 0x00 3. " WPN1 ,Write protect not flag bit 2" "Unchanged,Modified" bitfld.long 0x00 2. " TXINT_EBL ,Transmit interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Requested" bitfld.long 0x00 0. " TXREQ ,Transmit request" "Idle,Requested" if (((per.l(ad:0x402F0000+0x60))&0x100000)==0x00) group.long (0x60+0x04)++0x03 line.long 0x00 "TX4_ID,CAN Tx Msg Identifier" bitfld.long 0x00 13. " ID ,Tx4 Msg Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Tx4 Msg Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Tx4 Msg Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Tx4 Msg Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Tx4 Msg Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Tx4 Msg Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Tx4 Msg Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Tx4 Msg Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Tx4 Msg Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Tx4 Msg Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Tx4 Msg Identifier bit 0" "0,1" else group.long (0x60+0x04)++0x03 line.long 0x00 "TX4_ID,CAN Tx Msg Identifier" bitfld.long 0x00 31. " ID ,Tx4 Msg Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Tx4 Msg Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Tx4 Msg Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Tx4 Msg Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Tx4 Msg Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Tx4 Msg Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Tx4 Msg Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Tx4 Msg Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Tx4 Msg Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Tx4 Msg Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Tx4 Msg Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Tx4 Msg Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Tx4 Msg Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Tx4 Msg Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Tx4 Msg Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Tx4 Msg Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Tx4 Msg Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Tx4 Msg Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Tx4 Msg Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Tx4 Msg Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Tx4 Msg Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Tx4 Msg Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Tx4 Msg Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Tx4 Msg Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Tx4 Msg Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Tx4 Msg Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Tx4 Msg Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Tx4 Msg Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Tx4 Msg Identifier bit 0" "0,1" endif group.long (0x60+0x08)++0x07 line.long 0x00 "TX4_DH,CAN Tx Msg Upper Data Bytes" line.long 0x04 "TX4_DL,CAN Tx Msg Lower Data Bytes" group.long 0x70++0x03 "TX5" line.long 0x00 "TX5_CMD,CAN Tx Command Register" bitfld.long 0x00 23. " WPN2 ,Write protect bit" "Not protected,Protected" bitfld.long 0x00 21. " RTR ,RTR remote bit" "Standard,RTR" textline " " bitfld.long 0x00 20. " IDE ,Extended identifier" "Standard,Extended" bitfld.long 0x00 16.--19. " DLC ,Data length of the Tx Msg" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" textline " " bitfld.long 0x00 3. " WPN1 ,Write protect not flag bit 2" "Unchanged,Modified" bitfld.long 0x00 2. " TXINT_EBL ,Transmit interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Requested" bitfld.long 0x00 0. " TXREQ ,Transmit request" "Idle,Requested" if (((per.l(ad:0x402F0000+0x70))&0x100000)==0x00) group.long (0x70+0x04)++0x03 line.long 0x00 "TX5_ID,CAN Tx Msg Identifier" bitfld.long 0x00 13. " ID ,Tx5 Msg Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Tx5 Msg Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Tx5 Msg Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Tx5 Msg Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Tx5 Msg Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Tx5 Msg Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Tx5 Msg Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Tx5 Msg Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Tx5 Msg Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Tx5 Msg Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Tx5 Msg Identifier bit 0" "0,1" else group.long (0x70+0x04)++0x03 line.long 0x00 "TX5_ID,CAN Tx Msg Identifier" bitfld.long 0x00 31. " ID ,Tx5 Msg Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Tx5 Msg Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Tx5 Msg Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Tx5 Msg Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Tx5 Msg Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Tx5 Msg Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Tx5 Msg Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Tx5 Msg Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Tx5 Msg Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Tx5 Msg Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Tx5 Msg Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Tx5 Msg Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Tx5 Msg Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Tx5 Msg Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Tx5 Msg Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Tx5 Msg Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Tx5 Msg Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Tx5 Msg Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Tx5 Msg Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Tx5 Msg Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Tx5 Msg Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Tx5 Msg Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Tx5 Msg Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Tx5 Msg Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Tx5 Msg Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Tx5 Msg Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Tx5 Msg Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Tx5 Msg Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Tx5 Msg Identifier bit 0" "0,1" endif group.long (0x70+0x08)++0x07 line.long 0x00 "TX5_DH,CAN Tx Msg Upper Data Bytes" line.long 0x04 "TX5_DL,CAN Tx Msg Lower Data Bytes" group.long 0x80++0x03 "TX6" line.long 0x00 "TX6_CMD,CAN Tx Command Register" bitfld.long 0x00 23. " WPN2 ,Write protect bit" "Not protected,Protected" bitfld.long 0x00 21. " RTR ,RTR remote bit" "Standard,RTR" textline " " bitfld.long 0x00 20. " IDE ,Extended identifier" "Standard,Extended" bitfld.long 0x00 16.--19. " DLC ,Data length of the Tx Msg" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" textline " " bitfld.long 0x00 3. " WPN1 ,Write protect not flag bit 2" "Unchanged,Modified" bitfld.long 0x00 2. " TXINT_EBL ,Transmit interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Requested" bitfld.long 0x00 0. " TXREQ ,Transmit request" "Idle,Requested" if (((per.l(ad:0x402F0000+0x80))&0x100000)==0x00) group.long (0x80+0x04)++0x03 line.long 0x00 "TX6_ID,CAN Tx Msg Identifier" bitfld.long 0x00 13. " ID ,Tx6 Msg Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Tx6 Msg Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Tx6 Msg Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Tx6 Msg Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Tx6 Msg Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Tx6 Msg Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Tx6 Msg Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Tx6 Msg Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Tx6 Msg Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Tx6 Msg Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Tx6 Msg Identifier bit 0" "0,1" else group.long (0x80+0x04)++0x03 line.long 0x00 "TX6_ID,CAN Tx Msg Identifier" bitfld.long 0x00 31. " ID ,Tx6 Msg Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Tx6 Msg Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Tx6 Msg Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Tx6 Msg Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Tx6 Msg Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Tx6 Msg Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Tx6 Msg Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Tx6 Msg Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Tx6 Msg Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Tx6 Msg Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Tx6 Msg Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Tx6 Msg Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Tx6 Msg Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Tx6 Msg Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Tx6 Msg Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Tx6 Msg Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Tx6 Msg Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Tx6 Msg Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Tx6 Msg Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Tx6 Msg Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Tx6 Msg Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Tx6 Msg Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Tx6 Msg Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Tx6 Msg Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Tx6 Msg Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Tx6 Msg Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Tx6 Msg Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Tx6 Msg Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Tx6 Msg Identifier bit 0" "0,1" endif group.long (0x80+0x08)++0x07 line.long 0x00 "TX6_DH,CAN Tx Msg Upper Data Bytes" line.long 0x04 "TX6_DL,CAN Tx Msg Lower Data Bytes" group.long 0x90++0x03 "TX7" line.long 0x00 "TX7_CMD,CAN Tx Command Register" bitfld.long 0x00 23. " WPN2 ,Write protect bit" "Not protected,Protected" bitfld.long 0x00 21. " RTR ,RTR remote bit" "Standard,RTR" textline " " bitfld.long 0x00 20. " IDE ,Extended identifier" "Standard,Extended" bitfld.long 0x00 16.--19. " DLC ,Data length of the Tx Msg" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" textline " " bitfld.long 0x00 3. " WPN1 ,Write protect not flag bit 2" "Unchanged,Modified" bitfld.long 0x00 2. " TXINT_EBL ,Transmit interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " TXABORT ,Transmit abort request" "Idle,Requested" bitfld.long 0x00 0. " TXREQ ,Transmit request" "Idle,Requested" if (((per.l(ad:0x402F0000+0x90))&0x100000)==0x00) group.long (0x90+0x04)++0x03 line.long 0x00 "TX7_ID,CAN Tx Msg Identifier" bitfld.long 0x00 13. " ID ,Tx7 Msg Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Tx7 Msg Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Tx7 Msg Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Tx7 Msg Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Tx7 Msg Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Tx7 Msg Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Tx7 Msg Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Tx7 Msg Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Tx7 Msg Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Tx7 Msg Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Tx7 Msg Identifier bit 0" "0,1" else group.long (0x90+0x04)++0x03 line.long 0x00 "TX7_ID,CAN Tx Msg Identifier" bitfld.long 0x00 31. " ID ,Tx7 Msg Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Tx7 Msg Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Tx7 Msg Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Tx7 Msg Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Tx7 Msg Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Tx7 Msg Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Tx7 Msg Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Tx7 Msg Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Tx7 Msg Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Tx7 Msg Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Tx7 Msg Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Tx7 Msg Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Tx7 Msg Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Tx7 Msg Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Tx7 Msg Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Tx7 Msg Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Tx7 Msg Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Tx7 Msg Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Tx7 Msg Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Tx7 Msg Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Tx7 Msg Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Tx7 Msg Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Tx7 Msg Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Tx7 Msg Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Tx7 Msg Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Tx7 Msg Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Tx7 Msg Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Tx7 Msg Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Tx7 Msg Identifier bit 0" "0,1" endif group.long (0x90+0x08)++0x07 line.long 0x00 "TX7_DH,CAN Tx Msg Upper Data Bytes" line.long 0x04 "TX7_DL,CAN Tx Msg Lower Data Bytes" tree.end width 11. tree "RX Registers" group.long 0xA0++0x03 "RX0" line.long 0x00 "RX0_CMD,CAN Rx Command Register" bitfld.long 0x00 23. " WPNH ,Write Protect Bit" "Not protected,Protected" bitfld.long 0x00 21. " RTR ,RTR Remote bit" "Standard,RTR" textline " " bitfld.long 0x00 20. " IDE ,Extended identifier" "Standard,Extended" bitfld.long 0x00 16.--19. " DLC ,Data Length of the Tx Msg" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" textline " " bitfld.long 0x00 7. " WPNL ,Write protect not Flag Bits 6:3" "Unchanged,Modified" bitfld.long 0x00 6. " LK_FLG ,Link Flag used to link the Rx Buffer" "Not linked,Linked" textline " " bitfld.long 0x00 5. " RX_INT_EBL ,Receive Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " RTR_RPLY ,Automatic RTR Message Handling" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " BUF_EBL ,Buffer Enable" "Disabled,Enabled" bitfld.long 0x00 2. " RTR_ABORT ,RTR Abort Request" "Idle,Requested" textline " " bitfld.long 0x00 1. " RTR_RPY_PND ,RTR Reply request Pending" "Not pending,Pending" bitfld.long 0x00 0. " MSG_AV ,Message Available" "Not available,Available" if (((per.l(ad:0x402F0000+0xA0))&0x100000)==0x00) group.long (0xA0+0x04)++0x03 line.long 0x00 "RX0_ID,CAN Rx Msg Identifier" bitfld.long 0x00 13. " ID ,Rx Msg Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" else group.long (0xA0+0x04)++0x03 line.long 0x00 "RX0_ID,CAN Rx Msg Identifier" bitfld.long 0x00 31. " ID ,RX Msg Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" endif group.long (0xA0+0x08)++0x07 line.long 0x00 "RX0_DH,CAN Rx Msg Upper Data Bytes" line.long 0x04 "RX0_DL,CAN Rx Msg Lower Data Bytes" if (((per.l(ad:0x402F0000+0xA0+0x10))&0x4)==0x00) group.long (0xA0+0x10)++0x03 line.long 0x00 "RX0_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0xA0+0x10)++0x03 line.long 0x00 "RX0_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif if (((per.l(ad:0x402F0000+0xA0+0x14))&0x4)==0x00) group.long (0xA0+0x14)++0x03 line.long 0x00 "RX0_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0xA0+0x14)++0x03 line.long 0x00 "RX0_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif group.long (0xA0+0x18)++0x07 line.long 0x00 "RX0_AMRD,CAN Rx Acceptance mask data" hexmask.long.word 0x00 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" line.long 0x04 "RX0_ACRD,CAN Rx Acceptance code data" hexmask.long.word 0x04 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" group.long 0xC0++0x03 "RX1" line.long 0x00 "RX1_CMD,CAN Rx Command Register" bitfld.long 0x00 23. " WPNH ,Write Protect Bit" "Not protected,Protected" bitfld.long 0x00 21. " RTR ,RTR Remote bit" "Standard,RTR" textline " " bitfld.long 0x00 20. " IDE ,Extended identifier" "Standard,Extended" bitfld.long 0x00 16.--19. " DLC ,Data Length of the Tx Msg" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" textline " " bitfld.long 0x00 7. " WPNL ,Write protect not Flag Bits 6:3" "Unchanged,Modified" bitfld.long 0x00 6. " LK_FLG ,Link Flag used to link the Rx Buffer" "Not linked,Linked" textline " " bitfld.long 0x00 5. " RX_INT_EBL ,Receive Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " RTR_RPLY ,Automatic RTR Message Handling" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " BUF_EBL ,Buffer Enable" "Disabled,Enabled" bitfld.long 0x00 2. " RTR_ABORT ,RTR Abort Request" "Idle,Requested" textline " " bitfld.long 0x00 1. " RTR_RPY_PND ,RTR Reply request Pending" "Not pending,Pending" bitfld.long 0x00 0. " MSG_AV ,Message Available" "Not available,Available" if (((per.l(ad:0x402F0000+0xC0))&0x100000)==0x00) group.long (0xC0+0x04)++0x03 line.long 0x00 "RX1_ID,CAN Rx Msg Identifier" bitfld.long 0x00 13. " ID ,Rx Msg Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" else group.long (0xC0+0x04)++0x03 line.long 0x00 "RX1_ID,CAN Rx Msg Identifier" bitfld.long 0x00 31. " ID ,RX Msg Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" endif group.long (0xC0+0x08)++0x07 line.long 0x00 "RX1_DH,CAN Rx Msg Upper Data Bytes" line.long 0x04 "RX1_DL,CAN Rx Msg Lower Data Bytes" if (((per.l(ad:0x402F0000+0xC0+0x10))&0x4)==0x00) group.long (0xC0+0x10)++0x03 line.long 0x00 "RX1_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0xC0+0x10)++0x03 line.long 0x00 "RX1_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif if (((per.l(ad:0x402F0000+0xC0+0x14))&0x4)==0x00) group.long (0xC0+0x14)++0x03 line.long 0x00 "RX1_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0xC0+0x14)++0x03 line.long 0x00 "RX1_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif group.long (0xC0+0x18)++0x07 line.long 0x00 "RX1_AMRD,CAN Rx Acceptance mask data" hexmask.long.word 0x00 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" line.long 0x04 "RX1_ACRD,CAN Rx Acceptance code data" hexmask.long.word 0x04 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" group.long 0xE0++0x03 "RX2" line.long 0x00 "RX2_CMD,CAN Rx Command Register" bitfld.long 0x00 23. " WPNH ,Write Protect Bit" "Not protected,Protected" bitfld.long 0x00 21. " RTR ,RTR Remote bit" "Standard,RTR" textline " " bitfld.long 0x00 20. " IDE ,Extended identifier" "Standard,Extended" bitfld.long 0x00 16.--19. " DLC ,Data Length of the Tx Msg" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" textline " " bitfld.long 0x00 7. " WPNL ,Write protect not Flag Bits 6:3" "Unchanged,Modified" bitfld.long 0x00 6. " LK_FLG ,Link Flag used to link the Rx Buffer" "Not linked,Linked" textline " " bitfld.long 0x00 5. " RX_INT_EBL ,Receive Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " RTR_RPLY ,Automatic RTR Message Handling" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " BUF_EBL ,Buffer Enable" "Disabled,Enabled" bitfld.long 0x00 2. " RTR_ABORT ,RTR Abort Request" "Idle,Requested" textline " " bitfld.long 0x00 1. " RTR_RPY_PND ,RTR Reply request Pending" "Not pending,Pending" bitfld.long 0x00 0. " MSG_AV ,Message Available" "Not available,Available" if (((per.l(ad:0x402F0000+0xE0))&0x100000)==0x00) group.long (0xE0+0x04)++0x03 line.long 0x00 "RX2_ID,CAN Rx Msg Identifier" bitfld.long 0x00 13. " ID ,Rx Msg Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" else group.long (0xE0+0x04)++0x03 line.long 0x00 "RX2_ID,CAN Rx Msg Identifier" bitfld.long 0x00 31. " ID ,RX Msg Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" endif group.long (0xE0+0x08)++0x07 line.long 0x00 "RX2_DH,CAN Rx Msg Upper Data Bytes" line.long 0x04 "RX2_DL,CAN Rx Msg Lower Data Bytes" if (((per.l(ad:0x402F0000+0xE0+0x10))&0x4)==0x00) group.long (0xE0+0x10)++0x03 line.long 0x00 "RX2_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0xE0+0x10)++0x03 line.long 0x00 "RX2_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif if (((per.l(ad:0x402F0000+0xE0+0x14))&0x4)==0x00) group.long (0xE0+0x14)++0x03 line.long 0x00 "RX2_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0xE0+0x14)++0x03 line.long 0x00 "RX2_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif group.long (0xE0+0x18)++0x07 line.long 0x00 "RX2_AMRD,CAN Rx Acceptance mask data" hexmask.long.word 0x00 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" line.long 0x04 "RX2_ACRD,CAN Rx Acceptance code data" hexmask.long.word 0x04 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" group.long 0x100++0x03 "RX3" line.long 0x00 "RX3_CMD,CAN Rx Command Register" bitfld.long 0x00 23. " WPNH ,Write Protect Bit" "Not protected,Protected" bitfld.long 0x00 21. " RTR ,RTR Remote bit" "Standard,RTR" textline " " bitfld.long 0x00 20. " IDE ,Extended identifier" "Standard,Extended" bitfld.long 0x00 16.--19. " DLC ,Data Length of the Tx Msg" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" textline " " bitfld.long 0x00 7. " WPNL ,Write protect not Flag Bits 6:3" "Unchanged,Modified" bitfld.long 0x00 6. " LK_FLG ,Link Flag used to link the Rx Buffer" "Not linked,Linked" textline " " bitfld.long 0x00 5. " RX_INT_EBL ,Receive Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " RTR_RPLY ,Automatic RTR Message Handling" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " BUF_EBL ,Buffer Enable" "Disabled,Enabled" bitfld.long 0x00 2. " RTR_ABORT ,RTR Abort Request" "Idle,Requested" textline " " bitfld.long 0x00 1. " RTR_RPY_PND ,RTR Reply request Pending" "Not pending,Pending" bitfld.long 0x00 0. " MSG_AV ,Message Available" "Not available,Available" if (((per.l(ad:0x402F0000+0x100))&0x100000)==0x00) group.long (0x100+0x04)++0x03 line.long 0x00 "RX3_ID,CAN Rx Msg Identifier" bitfld.long 0x00 13. " ID ,Rx Msg Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" else group.long (0x100+0x04)++0x03 line.long 0x00 "RX3_ID,CAN Rx Msg Identifier" bitfld.long 0x00 31. " ID ,RX Msg Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" endif group.long (0x100+0x08)++0x07 line.long 0x00 "RX3_DH,CAN Rx Msg Upper Data Bytes" line.long 0x04 "RX3_DL,CAN Rx Msg Lower Data Bytes" if (((per.l(ad:0x402F0000+0x100+0x10))&0x4)==0x00) group.long (0x100+0x10)++0x03 line.long 0x00 "RX3_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0x100+0x10)++0x03 line.long 0x00 "RX3_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif if (((per.l(ad:0x402F0000+0x100+0x14))&0x4)==0x00) group.long (0x100+0x14)++0x03 line.long 0x00 "RX3_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0x100+0x14)++0x03 line.long 0x00 "RX3_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif group.long (0x100+0x18)++0x07 line.long 0x00 "RX3_AMRD,CAN Rx Acceptance mask data" hexmask.long.word 0x00 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" line.long 0x04 "RX3_ACRD,CAN Rx Acceptance code data" hexmask.long.word 0x04 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" group.long 0x120++0x03 "RX4" line.long 0x00 "RX4_CMD,CAN Rx Command Register" bitfld.long 0x00 23. " WPNH ,Write Protect Bit" "Not protected,Protected" bitfld.long 0x00 21. " RTR ,RTR Remote bit" "Standard,RTR" textline " " bitfld.long 0x00 20. " IDE ,Extended identifier" "Standard,Extended" bitfld.long 0x00 16.--19. " DLC ,Data Length of the Tx Msg" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" textline " " bitfld.long 0x00 7. " WPNL ,Write protect not Flag Bits 6:3" "Unchanged,Modified" bitfld.long 0x00 6. " LK_FLG ,Link Flag used to link the Rx Buffer" "Not linked,Linked" textline " " bitfld.long 0x00 5. " RX_INT_EBL ,Receive Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " RTR_RPLY ,Automatic RTR Message Handling" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " BUF_EBL ,Buffer Enable" "Disabled,Enabled" bitfld.long 0x00 2. " RTR_ABORT ,RTR Abort Request" "Idle,Requested" textline " " bitfld.long 0x00 1. " RTR_RPY_PND ,RTR Reply request Pending" "Not pending,Pending" bitfld.long 0x00 0. " MSG_AV ,Message Available" "Not available,Available" if (((per.l(ad:0x402F0000+0x120))&0x100000)==0x00) group.long (0x120+0x04)++0x03 line.long 0x00 "RX4_ID,CAN Rx Msg Identifier" bitfld.long 0x00 13. " ID ,Rx Msg Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" else group.long (0x120+0x04)++0x03 line.long 0x00 "RX4_ID,CAN Rx Msg Identifier" bitfld.long 0x00 31. " ID ,RX Msg Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" endif group.long (0x120+0x08)++0x07 line.long 0x00 "RX4_DH,CAN Rx Msg Upper Data Bytes" line.long 0x04 "RX4_DL,CAN Rx Msg Lower Data Bytes" if (((per.l(ad:0x402F0000+0x120+0x10))&0x4)==0x00) group.long (0x120+0x10)++0x03 line.long 0x00 "RX4_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0x120+0x10)++0x03 line.long 0x00 "RX4_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif if (((per.l(ad:0x402F0000+0x120+0x14))&0x4)==0x00) group.long (0x120+0x14)++0x03 line.long 0x00 "RX4_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0x120+0x14)++0x03 line.long 0x00 "RX4_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif group.long (0x120+0x18)++0x07 line.long 0x00 "RX4_AMRD,CAN Rx Acceptance mask data" hexmask.long.word 0x00 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" line.long 0x04 "RX4_ACRD,CAN Rx Acceptance code data" hexmask.long.word 0x04 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" group.long 0x140++0x03 "RX5" line.long 0x00 "RX5_CMD,CAN Rx Command Register" bitfld.long 0x00 23. " WPNH ,Write Protect Bit" "Not protected,Protected" bitfld.long 0x00 21. " RTR ,RTR Remote bit" "Standard,RTR" textline " " bitfld.long 0x00 20. " IDE ,Extended identifier" "Standard,Extended" bitfld.long 0x00 16.--19. " DLC ,Data Length of the Tx Msg" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" textline " " bitfld.long 0x00 7. " WPNL ,Write protect not Flag Bits 6:3" "Unchanged,Modified" bitfld.long 0x00 6. " LK_FLG ,Link Flag used to link the Rx Buffer" "Not linked,Linked" textline " " bitfld.long 0x00 5. " RX_INT_EBL ,Receive Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " RTR_RPLY ,Automatic RTR Message Handling" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " BUF_EBL ,Buffer Enable" "Disabled,Enabled" bitfld.long 0x00 2. " RTR_ABORT ,RTR Abort Request" "Idle,Requested" textline " " bitfld.long 0x00 1. " RTR_RPY_PND ,RTR Reply request Pending" "Not pending,Pending" bitfld.long 0x00 0. " MSG_AV ,Message Available" "Not available,Available" if (((per.l(ad:0x402F0000+0x140))&0x100000)==0x00) group.long (0x140+0x04)++0x03 line.long 0x00 "RX5_ID,CAN Rx Msg Identifier" bitfld.long 0x00 13. " ID ,Rx Msg Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" else group.long (0x140+0x04)++0x03 line.long 0x00 "RX5_ID,CAN Rx Msg Identifier" bitfld.long 0x00 31. " ID ,RX Msg Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" endif group.long (0x140+0x08)++0x07 line.long 0x00 "RX5_DH,CAN Rx Msg Upper Data Bytes" line.long 0x04 "RX5_DL,CAN Rx Msg Lower Data Bytes" if (((per.l(ad:0x402F0000+0x140+0x10))&0x4)==0x00) group.long (0x140+0x10)++0x03 line.long 0x00 "RX5_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0x140+0x10)++0x03 line.long 0x00 "RX5_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif if (((per.l(ad:0x402F0000+0x140+0x14))&0x4)==0x00) group.long (0x140+0x14)++0x03 line.long 0x00 "RX5_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0x140+0x14)++0x03 line.long 0x00 "RX5_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif group.long (0x140+0x18)++0x07 line.long 0x00 "RX5_AMRD,CAN Rx Acceptance mask data" hexmask.long.word 0x00 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" line.long 0x04 "RX5_ACRD,CAN Rx Acceptance code data" hexmask.long.word 0x04 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" group.long 0x160++0x03 "RX6" line.long 0x00 "RX6_CMD,CAN Rx Command Register" bitfld.long 0x00 23. " WPNH ,Write Protect Bit" "Not protected,Protected" bitfld.long 0x00 21. " RTR ,RTR Remote bit" "Standard,RTR" textline " " bitfld.long 0x00 20. " IDE ,Extended identifier" "Standard,Extended" bitfld.long 0x00 16.--19. " DLC ,Data Length of the Tx Msg" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" textline " " bitfld.long 0x00 7. " WPNL ,Write protect not Flag Bits 6:3" "Unchanged,Modified" bitfld.long 0x00 6. " LK_FLG ,Link Flag used to link the Rx Buffer" "Not linked,Linked" textline " " bitfld.long 0x00 5. " RX_INT_EBL ,Receive Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " RTR_RPLY ,Automatic RTR Message Handling" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " BUF_EBL ,Buffer Enable" "Disabled,Enabled" bitfld.long 0x00 2. " RTR_ABORT ,RTR Abort Request" "Idle,Requested" textline " " bitfld.long 0x00 1. " RTR_RPY_PND ,RTR Reply request Pending" "Not pending,Pending" bitfld.long 0x00 0. " MSG_AV ,Message Available" "Not available,Available" if (((per.l(ad:0x402F0000+0x160))&0x100000)==0x00) group.long (0x160+0x04)++0x03 line.long 0x00 "RX6_ID,CAN Rx Msg Identifier" bitfld.long 0x00 13. " ID ,Rx Msg Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" else group.long (0x160+0x04)++0x03 line.long 0x00 "RX6_ID,CAN Rx Msg Identifier" bitfld.long 0x00 31. " ID ,RX Msg Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" endif group.long (0x160+0x08)++0x07 line.long 0x00 "RX6_DH,CAN Rx Msg Upper Data Bytes" line.long 0x04 "RX6_DL,CAN Rx Msg Lower Data Bytes" if (((per.l(ad:0x402F0000+0x160+0x10))&0x4)==0x00) group.long (0x160+0x10)++0x03 line.long 0x00 "RX6_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0x160+0x10)++0x03 line.long 0x00 "RX6_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif if (((per.l(ad:0x402F0000+0x160+0x14))&0x4)==0x00) group.long (0x160+0x14)++0x03 line.long 0x00 "RX6_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0x160+0x14)++0x03 line.long 0x00 "RX6_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif group.long (0x160+0x18)++0x07 line.long 0x00 "RX6_AMRD,CAN Rx Acceptance mask data" hexmask.long.word 0x00 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" line.long 0x04 "RX6_ACRD,CAN Rx Acceptance code data" hexmask.long.word 0x04 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" group.long 0x180++0x03 "RX7" line.long 0x00 "RX7_CMD,CAN Rx Command Register" bitfld.long 0x00 23. " WPNH ,Write Protect Bit" "Not protected,Protected" bitfld.long 0x00 21. " RTR ,RTR Remote bit" "Standard,RTR" textline " " bitfld.long 0x00 20. " IDE ,Extended identifier" "Standard,Extended" bitfld.long 0x00 16.--19. " DLC ,Data Length of the Tx Msg" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" textline " " bitfld.long 0x00 7. " WPNL ,Write protect not Flag Bits 6:3" "Unchanged,Modified" bitfld.long 0x00 6. " LK_FLG ,Link Flag used to link the Rx Buffer" "Not linked,Linked" textline " " bitfld.long 0x00 5. " RX_INT_EBL ,Receive Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " RTR_RPLY ,Automatic RTR Message Handling" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " BUF_EBL ,Buffer Enable" "Disabled,Enabled" bitfld.long 0x00 2. " RTR_ABORT ,RTR Abort Request" "Idle,Requested" textline " " bitfld.long 0x00 1. " RTR_RPY_PND ,RTR Reply request Pending" "Not pending,Pending" bitfld.long 0x00 0. " MSG_AV ,Message Available" "Not available,Available" if (((per.l(ad:0x402F0000+0x180))&0x100000)==0x00) group.long (0x180+0x04)++0x03 line.long 0x00 "RX7_ID,CAN Rx Msg Identifier" bitfld.long 0x00 13. " ID ,Rx Msg Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" else group.long (0x180+0x04)++0x03 line.long 0x00 "RX7_ID,CAN Rx Msg Identifier" bitfld.long 0x00 31. " ID ,RX Msg Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" endif group.long (0x180+0x08)++0x07 line.long 0x00 "RX7_DH,CAN Rx Msg Upper Data Bytes" line.long 0x04 "RX7_DL,CAN Rx Msg Lower Data Bytes" if (((per.l(ad:0x402F0000+0x180+0x10))&0x4)==0x00) group.long (0x180+0x10)++0x03 line.long 0x00 "RX7_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0x180+0x10)++0x03 line.long 0x00 "RX7_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif if (((per.l(ad:0x402F0000+0x180+0x14))&0x4)==0x00) group.long (0x180+0x14)++0x03 line.long 0x00 "RX7_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0x180+0x14)++0x03 line.long 0x00 "RX7_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif group.long (0x180+0x18)++0x07 line.long 0x00 "RX7_AMRD,CAN Rx Acceptance mask data" hexmask.long.word 0x00 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" line.long 0x04 "RX7_ACRD,CAN Rx Acceptance code data" hexmask.long.word 0x04 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" group.long 0x1A0++0x03 "RX8" line.long 0x00 "RX8_CMD,CAN Rx Command Register" bitfld.long 0x00 23. " WPNH ,Write Protect Bit" "Not protected,Protected" bitfld.long 0x00 21. " RTR ,RTR Remote bit" "Standard,RTR" textline " " bitfld.long 0x00 20. " IDE ,Extended identifier" "Standard,Extended" bitfld.long 0x00 16.--19. " DLC ,Data Length of the Tx Msg" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" textline " " bitfld.long 0x00 7. " WPNL ,Write protect not Flag Bits 6:3" "Unchanged,Modified" bitfld.long 0x00 6. " LK_FLG ,Link Flag used to link the Rx Buffer" "Not linked,Linked" textline " " bitfld.long 0x00 5. " RX_INT_EBL ,Receive Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " RTR_RPLY ,Automatic RTR Message Handling" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " BUF_EBL ,Buffer Enable" "Disabled,Enabled" bitfld.long 0x00 2. " RTR_ABORT ,RTR Abort Request" "Idle,Requested" textline " " bitfld.long 0x00 1. " RTR_RPY_PND ,RTR Reply request Pending" "Not pending,Pending" bitfld.long 0x00 0. " MSG_AV ,Message Available" "Not available,Available" if (((per.l(ad:0x402F0000+0x1A0))&0x100000)==0x00) group.long (0x1A0+0x04)++0x03 line.long 0x00 "RX8_ID,CAN Rx Msg Identifier" bitfld.long 0x00 13. " ID ,Rx Msg Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" else group.long (0x1A0+0x04)++0x03 line.long 0x00 "RX8_ID,CAN Rx Msg Identifier" bitfld.long 0x00 31. " ID ,RX Msg Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" endif group.long (0x1A0+0x08)++0x07 line.long 0x00 "RX8_DH,CAN Rx Msg Upper Data Bytes" line.long 0x04 "RX8_DL,CAN Rx Msg Lower Data Bytes" if (((per.l(ad:0x402F0000+0x1A0+0x10))&0x4)==0x00) group.long (0x1A0+0x10)++0x03 line.long 0x00 "RX8_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0x1A0+0x10)++0x03 line.long 0x00 "RX8_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif if (((per.l(ad:0x402F0000+0x1A0+0x14))&0x4)==0x00) group.long (0x1A0+0x14)++0x03 line.long 0x00 "RX8_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0x1A0+0x14)++0x03 line.long 0x00 "RX8_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif group.long (0x1A0+0x18)++0x07 line.long 0x00 "RX8_AMRD,CAN Rx Acceptance mask data" hexmask.long.word 0x00 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" line.long 0x04 "RX8_ACRD,CAN Rx Acceptance code data" hexmask.long.word 0x04 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" group.long 0x1C0++0x03 "RX9" line.long 0x00 "RX9_CMD,CAN Rx Command Register" bitfld.long 0x00 23. " WPNH ,Write Protect Bit" "Not protected,Protected" bitfld.long 0x00 21. " RTR ,RTR Remote bit" "Standard,RTR" textline " " bitfld.long 0x00 20. " IDE ,Extended identifier" "Standard,Extended" bitfld.long 0x00 16.--19. " DLC ,Data Length of the Tx Msg" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" textline " " bitfld.long 0x00 7. " WPNL ,Write protect not Flag Bits 6:3" "Unchanged,Modified" bitfld.long 0x00 6. " LK_FLG ,Link Flag used to link the Rx Buffer" "Not linked,Linked" textline " " bitfld.long 0x00 5. " RX_INT_EBL ,Receive Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " RTR_RPLY ,Automatic RTR Message Handling" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " BUF_EBL ,Buffer Enable" "Disabled,Enabled" bitfld.long 0x00 2. " RTR_ABORT ,RTR Abort Request" "Idle,Requested" textline " " bitfld.long 0x00 1. " RTR_RPY_PND ,RTR Reply request Pending" "Not pending,Pending" bitfld.long 0x00 0. " MSG_AV ,Message Available" "Not available,Available" if (((per.l(ad:0x402F0000+0x1C0))&0x100000)==0x00) group.long (0x1C0+0x04)++0x03 line.long 0x00 "RX9_ID,CAN Rx Msg Identifier" bitfld.long 0x00 13. " ID ,Rx Msg Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" else group.long (0x1C0+0x04)++0x03 line.long 0x00 "RX9_ID,CAN Rx Msg Identifier" bitfld.long 0x00 31. " ID ,RX Msg Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" endif group.long (0x1C0+0x08)++0x07 line.long 0x00 "RX9_DH,CAN Rx Msg Upper Data Bytes" line.long 0x04 "RX9_DL,CAN Rx Msg Lower Data Bytes" if (((per.l(ad:0x402F0000+0x1C0+0x10))&0x4)==0x00) group.long (0x1C0+0x10)++0x03 line.long 0x00 "RX9_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0x1C0+0x10)++0x03 line.long 0x00 "RX9_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif if (((per.l(ad:0x402F0000+0x1C0+0x14))&0x4)==0x00) group.long (0x1C0+0x14)++0x03 line.long 0x00 "RX9_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0x1C0+0x14)++0x03 line.long 0x00 "RX9_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif group.long (0x1C0+0x18)++0x07 line.long 0x00 "RX9_AMRD,CAN Rx Acceptance mask data" hexmask.long.word 0x00 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" line.long 0x04 "RX9_ACRD,CAN Rx Acceptance code data" hexmask.long.word 0x04 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" group.long 0x1E0++0x03 "RX10" line.long 0x00 "RX10_CMD,CAN Rx Command Register" bitfld.long 0x00 23. " WPNH ,Write Protect Bit" "Not protected,Protected" bitfld.long 0x00 21. " RTR ,RTR Remote bit" "Standard,RTR" textline " " bitfld.long 0x00 20. " IDE ,Extended identifier" "Standard,Extended" bitfld.long 0x00 16.--19. " DLC ,Data Length of the Tx Msg" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" textline " " bitfld.long 0x00 7. " WPNL ,Write protect not Flag Bits 6:3" "Unchanged,Modified" bitfld.long 0x00 6. " LK_FLG ,Link Flag used to link the Rx Buffer" "Not linked,Linked" textline " " bitfld.long 0x00 5. " RX_INT_EBL ,Receive Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " RTR_RPLY ,Automatic RTR Message Handling" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " BUF_EBL ,Buffer Enable" "Disabled,Enabled" bitfld.long 0x00 2. " RTR_ABORT ,RTR Abort Request" "Idle,Requested" textline " " bitfld.long 0x00 1. " RTR_RPY_PND ,RTR Reply request Pending" "Not pending,Pending" bitfld.long 0x00 0. " MSG_AV ,Message Available" "Not available,Available" if (((per.l(ad:0x402F0000+0x1E0))&0x100000)==0x00) group.long (0x1E0+0x04)++0x03 line.long 0x00 "RX10_ID,CAN Rx Msg Identifier" bitfld.long 0x00 13. " ID ,Rx Msg Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" else group.long (0x1E0+0x04)++0x03 line.long 0x00 "RX10_ID,CAN Rx Msg Identifier" bitfld.long 0x00 31. " ID ,RX Msg Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" endif group.long (0x1E0+0x08)++0x07 line.long 0x00 "RX10_DH,CAN Rx Msg Upper Data Bytes" line.long 0x04 "RX10_DL,CAN Rx Msg Lower Data Bytes" if (((per.l(ad:0x402F0000+0x1E0+0x10))&0x4)==0x00) group.long (0x1E0+0x10)++0x03 line.long 0x00 "RX10_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0x1E0+0x10)++0x03 line.long 0x00 "RX10_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif if (((per.l(ad:0x402F0000+0x1E0+0x14))&0x4)==0x00) group.long (0x1E0+0x14)++0x03 line.long 0x00 "RX10_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0x1E0+0x14)++0x03 line.long 0x00 "RX10_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif group.long (0x1E0+0x18)++0x07 line.long 0x00 "RX10_AMRD,CAN Rx Acceptance mask data" hexmask.long.word 0x00 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" line.long 0x04 "RX10_ACRD,CAN Rx Acceptance code data" hexmask.long.word 0x04 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" group.long 0x200++0x03 "RX11" line.long 0x00 "RX11_CMD,CAN Rx Command Register" bitfld.long 0x00 23. " WPNH ,Write Protect Bit" "Not protected,Protected" bitfld.long 0x00 21. " RTR ,RTR Remote bit" "Standard,RTR" textline " " bitfld.long 0x00 20. " IDE ,Extended identifier" "Standard,Extended" bitfld.long 0x00 16.--19. " DLC ,Data Length of the Tx Msg" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" textline " " bitfld.long 0x00 7. " WPNL ,Write protect not Flag Bits 6:3" "Unchanged,Modified" bitfld.long 0x00 6. " LK_FLG ,Link Flag used to link the Rx Buffer" "Not linked,Linked" textline " " bitfld.long 0x00 5. " RX_INT_EBL ,Receive Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " RTR_RPLY ,Automatic RTR Message Handling" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " BUF_EBL ,Buffer Enable" "Disabled,Enabled" bitfld.long 0x00 2. " RTR_ABORT ,RTR Abort Request" "Idle,Requested" textline " " bitfld.long 0x00 1. " RTR_RPY_PND ,RTR Reply request Pending" "Not pending,Pending" bitfld.long 0x00 0. " MSG_AV ,Message Available" "Not available,Available" if (((per.l(ad:0x402F0000+0x200))&0x100000)==0x00) group.long (0x200+0x04)++0x03 line.long 0x00 "RX11_ID,CAN Rx Msg Identifier" bitfld.long 0x00 13. " ID ,Rx Msg Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" else group.long (0x200+0x04)++0x03 line.long 0x00 "RX11_ID,CAN Rx Msg Identifier" bitfld.long 0x00 31. " ID ,RX Msg Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" endif group.long (0x200+0x08)++0x07 line.long 0x00 "RX11_DH,CAN Rx Msg Upper Data Bytes" line.long 0x04 "RX11_DL,CAN Rx Msg Lower Data Bytes" if (((per.l(ad:0x402F0000+0x200+0x10))&0x4)==0x00) group.long (0x200+0x10)++0x03 line.long 0x00 "RX11_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0x200+0x10)++0x03 line.long 0x00 "RX11_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif if (((per.l(ad:0x402F0000+0x200+0x14))&0x4)==0x00) group.long (0x200+0x14)++0x03 line.long 0x00 "RX11_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0x200+0x14)++0x03 line.long 0x00 "RX11_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif group.long (0x200+0x18)++0x07 line.long 0x00 "RX11_AMRD,CAN Rx Acceptance mask data" hexmask.long.word 0x00 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" line.long 0x04 "RX11_ACRD,CAN Rx Acceptance code data" hexmask.long.word 0x04 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" group.long 0x220++0x03 "RX12" line.long 0x00 "RX12_CMD,CAN Rx Command Register" bitfld.long 0x00 23. " WPNH ,Write Protect Bit" "Not protected,Protected" bitfld.long 0x00 21. " RTR ,RTR Remote bit" "Standard,RTR" textline " " bitfld.long 0x00 20. " IDE ,Extended identifier" "Standard,Extended" bitfld.long 0x00 16.--19. " DLC ,Data Length of the Tx Msg" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" textline " " bitfld.long 0x00 7. " WPNL ,Write protect not Flag Bits 6:3" "Unchanged,Modified" bitfld.long 0x00 6. " LK_FLG ,Link Flag used to link the Rx Buffer" "Not linked,Linked" textline " " bitfld.long 0x00 5. " RX_INT_EBL ,Receive Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " RTR_RPLY ,Automatic RTR Message Handling" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " BUF_EBL ,Buffer Enable" "Disabled,Enabled" bitfld.long 0x00 2. " RTR_ABORT ,RTR Abort Request" "Idle,Requested" textline " " bitfld.long 0x00 1. " RTR_RPY_PND ,RTR Reply request Pending" "Not pending,Pending" bitfld.long 0x00 0. " MSG_AV ,Message Available" "Not available,Available" if (((per.l(ad:0x402F0000+0x220))&0x100000)==0x00) group.long (0x220+0x04)++0x03 line.long 0x00 "RX12_ID,CAN Rx Msg Identifier" bitfld.long 0x00 13. " ID ,Rx Msg Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" else group.long (0x220+0x04)++0x03 line.long 0x00 "RX12_ID,CAN Rx Msg Identifier" bitfld.long 0x00 31. " ID ,RX Msg Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" endif group.long (0x220+0x08)++0x07 line.long 0x00 "RX12_DH,CAN Rx Msg Upper Data Bytes" line.long 0x04 "RX12_DL,CAN Rx Msg Lower Data Bytes" if (((per.l(ad:0x402F0000+0x220+0x10))&0x4)==0x00) group.long (0x220+0x10)++0x03 line.long 0x00 "RX12_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0x220+0x10)++0x03 line.long 0x00 "RX12_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif if (((per.l(ad:0x402F0000+0x220+0x14))&0x4)==0x00) group.long (0x220+0x14)++0x03 line.long 0x00 "RX12_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0x220+0x14)++0x03 line.long 0x00 "RX12_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif group.long (0x220+0x18)++0x07 line.long 0x00 "RX12_AMRD,CAN Rx Acceptance mask data" hexmask.long.word 0x00 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" line.long 0x04 "RX12_ACRD,CAN Rx Acceptance code data" hexmask.long.word 0x04 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" group.long 0x240++0x03 "RX13" line.long 0x00 "RX13_CMD,CAN Rx Command Register" bitfld.long 0x00 23. " WPNH ,Write Protect Bit" "Not protected,Protected" bitfld.long 0x00 21. " RTR ,RTR Remote bit" "Standard,RTR" textline " " bitfld.long 0x00 20. " IDE ,Extended identifier" "Standard,Extended" bitfld.long 0x00 16.--19. " DLC ,Data Length of the Tx Msg" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" textline " " bitfld.long 0x00 7. " WPNL ,Write protect not Flag Bits 6:3" "Unchanged,Modified" bitfld.long 0x00 6. " LK_FLG ,Link Flag used to link the Rx Buffer" "Not linked,Linked" textline " " bitfld.long 0x00 5. " RX_INT_EBL ,Receive Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " RTR_RPLY ,Automatic RTR Message Handling" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " BUF_EBL ,Buffer Enable" "Disabled,Enabled" bitfld.long 0x00 2. " RTR_ABORT ,RTR Abort Request" "Idle,Requested" textline " " bitfld.long 0x00 1. " RTR_RPY_PND ,RTR Reply request Pending" "Not pending,Pending" bitfld.long 0x00 0. " MSG_AV ,Message Available" "Not available,Available" if (((per.l(ad:0x402F0000+0x240))&0x100000)==0x00) group.long (0x240+0x04)++0x03 line.long 0x00 "RX13_ID,CAN Rx Msg Identifier" bitfld.long 0x00 13. " ID ,Rx Msg Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" else group.long (0x240+0x04)++0x03 line.long 0x00 "RX13_ID,CAN Rx Msg Identifier" bitfld.long 0x00 31. " ID ,RX Msg Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" endif group.long (0x240+0x08)++0x07 line.long 0x00 "RX13_DH,CAN Rx Msg Upper Data Bytes" line.long 0x04 "RX13_DL,CAN Rx Msg Lower Data Bytes" if (((per.l(ad:0x402F0000+0x240+0x10))&0x4)==0x00) group.long (0x240+0x10)++0x03 line.long 0x00 "RX13_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0x240+0x10)++0x03 line.long 0x00 "RX13_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif if (((per.l(ad:0x402F0000+0x240+0x14))&0x4)==0x00) group.long (0x240+0x14)++0x03 line.long 0x00 "RX13_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0x240+0x14)++0x03 line.long 0x00 "RX13_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif group.long (0x240+0x18)++0x07 line.long 0x00 "RX13_AMRD,CAN Rx Acceptance mask data" hexmask.long.word 0x00 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" line.long 0x04 "RX13_ACRD,CAN Rx Acceptance code data" hexmask.long.word 0x04 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" group.long 0x260++0x03 "RX14" line.long 0x00 "RX14_CMD,CAN Rx Command Register" bitfld.long 0x00 23. " WPNH ,Write Protect Bit" "Not protected,Protected" bitfld.long 0x00 21. " RTR ,RTR Remote bit" "Standard,RTR" textline " " bitfld.long 0x00 20. " IDE ,Extended identifier" "Standard,Extended" bitfld.long 0x00 16.--19. " DLC ,Data Length of the Tx Msg" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" textline " " bitfld.long 0x00 7. " WPNL ,Write protect not Flag Bits 6:3" "Unchanged,Modified" bitfld.long 0x00 6. " LK_FLG ,Link Flag used to link the Rx Buffer" "Not linked,Linked" textline " " bitfld.long 0x00 5. " RX_INT_EBL ,Receive Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " RTR_RPLY ,Automatic RTR Message Handling" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " BUF_EBL ,Buffer Enable" "Disabled,Enabled" bitfld.long 0x00 2. " RTR_ABORT ,RTR Abort Request" "Idle,Requested" textline " " bitfld.long 0x00 1. " RTR_RPY_PND ,RTR Reply request Pending" "Not pending,Pending" bitfld.long 0x00 0. " MSG_AV ,Message Available" "Not available,Available" if (((per.l(ad:0x402F0000+0x260))&0x100000)==0x00) group.long (0x260+0x04)++0x03 line.long 0x00 "RX14_ID,CAN Rx Msg Identifier" bitfld.long 0x00 13. " ID ,Rx Msg Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" else group.long (0x260+0x04)++0x03 line.long 0x00 "RX14_ID,CAN Rx Msg Identifier" bitfld.long 0x00 31. " ID ,RX Msg Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" endif group.long (0x260+0x08)++0x07 line.long 0x00 "RX14_DH,CAN Rx Msg Upper Data Bytes" line.long 0x04 "RX14_DL,CAN Rx Msg Lower Data Bytes" if (((per.l(ad:0x402F0000+0x260+0x10))&0x4)==0x00) group.long (0x260+0x10)++0x03 line.long 0x00 "RX14_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0x260+0x10)++0x03 line.long 0x00 "RX14_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif if (((per.l(ad:0x402F0000+0x260+0x14))&0x4)==0x00) group.long (0x260+0x14)++0x03 line.long 0x00 "RX14_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0x260+0x14)++0x03 line.long 0x00 "RX14_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif group.long (0x260+0x18)++0x07 line.long 0x00 "RX14_AMRD,CAN Rx Acceptance mask data" hexmask.long.word 0x00 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" line.long 0x04 "RX14_ACRD,CAN Rx Acceptance code data" hexmask.long.word 0x04 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" group.long 0x280++0x03 "RX15" line.long 0x00 "RX15_CMD,CAN Rx Command Register" bitfld.long 0x00 23. " WPNH ,Write Protect Bit" "Not protected,Protected" bitfld.long 0x00 21. " RTR ,RTR Remote bit" "Standard,RTR" textline " " bitfld.long 0x00 20. " IDE ,Extended identifier" "Standard,Extended" bitfld.long 0x00 16.--19. " DLC ,Data Length of the Tx Msg" "0,1,2,3,4,5,6,7,8,8,8,8,8,8,8,8" textline " " bitfld.long 0x00 7. " WPNL ,Write protect not Flag Bits 6:3" "Unchanged,Modified" bitfld.long 0x00 6. " LK_FLG ,Link Flag used to link the Rx Buffer" "Not linked,Linked" textline " " bitfld.long 0x00 5. " RX_INT_EBL ,Receive Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. " RTR_RPLY ,Automatic RTR Message Handling" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " BUF_EBL ,Buffer Enable" "Disabled,Enabled" bitfld.long 0x00 2. " RTR_ABORT ,RTR Abort Request" "Idle,Requested" textline " " bitfld.long 0x00 1. " RTR_RPY_PND ,RTR Reply request Pending" "Not pending,Pending" bitfld.long 0x00 0. " MSG_AV ,Message Available" "Not available,Available" if (((per.l(ad:0x402F0000+0x280))&0x100000)==0x00) group.long (0x280+0x04)++0x03 line.long 0x00 "RX15_ID,CAN Rx Msg Identifier" bitfld.long 0x00 13. " ID ,Rx Msg Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" else group.long (0x280+0x04)++0x03 line.long 0x00 "RX15_ID,CAN Rx Msg Identifier" bitfld.long 0x00 31. " ID ,RX Msg Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 0.--2. " ZEROES ,Zeros" "0,1,2,3,4,5,6,7" endif group.long (0x280+0x08)++0x07 line.long 0x00 "RX15_DH,CAN Rx Msg Upper Data Bytes" line.long 0x04 "RX15_DL,CAN Rx Msg Lower Data Bytes" if (((per.l(ad:0x402F0000+0x280+0x10))&0x4)==0x00) group.long (0x280+0x10)++0x03 line.long 0x00 "RX15_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0x280+0x10)++0x03 line.long 0x00 "RX15_AMR,CAN Rx Acceptance mask value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif if (((per.l(ad:0x402F0000+0x280+0x14))&0x4)==0x00) group.long (0x280+0x14)++0x03 line.long 0x00 "RX15_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 13. " ID ,Identifier bit 10 (Standard)" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" else group.long (0x280+0x14)++0x03 line.long 0x00 "RX15_ACR,CAN Rx Acceptance Code value" bitfld.long 0x00 31. " ID ,Identifier bit 28 (Extended)" "0,1" bitfld.long 0x00 30. ",Identifier bit 27" "0,1" bitfld.long 0x00 29. ",Identifier bit 26" "0,1" bitfld.long 0x00 28. ",Identifier bit 25" "0,1" bitfld.long 0x00 27. ",Identifier bit 24" "0,1" bitfld.long 0x00 26. ",Identifier bit 23" "0,1" bitfld.long 0x00 25. ",Identifier bit 22" "0,1" bitfld.long 0x00 24. ",Identifier bit 21" "0,1" bitfld.long 0x00 23. ",Identifier bit 20" "0,1" bitfld.long 0x00 22. ",Identifier bit 19" "0,1" bitfld.long 0x00 21. ",Identifier bit 18" "0,1" bitfld.long 0x00 20. ",Identifier bit 17" "0,1" bitfld.long 0x00 19. ",Identifier bit 16" "0,1" bitfld.long 0x00 18. ",Identifier bit 15" "0,1" bitfld.long 0x00 17. ",Identifier bit 14" "0,1" bitfld.long 0x00 16. ",Identifier bit 13" "0,1" bitfld.long 0x00 15. ",Identifier bit 12" "0,1" bitfld.long 0x00 14. ",Identifier bit 11" "0,1" bitfld.long 0x00 13. ",Identifier bit 10" "0,1" bitfld.long 0x00 12. ",Identifier bit 9" "0,1" bitfld.long 0x00 11. ",Identifier bit 8" "0,1" bitfld.long 0x00 10. ",Identifier bit 7" "0,1" bitfld.long 0x00 9. ",Identifier bit 6" "0,1" bitfld.long 0x00 8. ",Identifier bit 5" "0,1" bitfld.long 0x00 7. ",Identifier bit 4" "0,1" bitfld.long 0x00 6. ",Identifier bit 3" "0,1" bitfld.long 0x00 5. ",Identifier bit 2" "0,1" bitfld.long 0x00 4. ",Identifier bit 1" "0,1" bitfld.long 0x00 3. ",Identifier bit 0" "0,1" textline " " bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended" bitfld.long 0x00 1. " RTR ,RTR bit" "Standard,RTR" endif group.long (0x280+0x18)++0x07 line.long 0x00 "RX15_AMRD,CAN Rx Acceptance mask data" hexmask.long.word 0x00 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" line.long 0x04 "RX15_ACRD,CAN Rx Acceptance code data" hexmask.long.word 0x04 0.--15. 1. " DATA_LSB ,Upper 2 Bytes of Data" tree.end width 0x0B tree.end tree.end endif tree "CPUSS (CPU Sub-System)" base ad:0x40100000 width 17. group.long 0x00++0x0B line.long 0x00 "CPUSS_CONFIG,Configuration Register" bitfld.long 0x00 0. " VECT_IN_RAM ,Vector Table location" "FLASH,SRAM" line.long 0x04 "CPUSS_SYSREQ,SYSCALL Control Register" bitfld.long 0x04 31. " SYSCALL_REQ ,SystemCall request" "Not requested,Requested" rbitfld.long 0x04 30. " HMASTER_0 ,Source of the write access to the SYSREQ register" "CPU,DAP" rbitfld.long 0x04 29. " ROM_ACCESS_EN ,Boot ROM executing enable" "Disabled,Enabled" textline " " bitfld.long 0x04 28. " PRIVILEGED ,Privileged mode" "User,Privileged" bitfld.long 0x04 27. " DIS_RESET_VECT_REL ,Reset Vector fetch relocation disable" "Enabled,Disabled" hexmask.long.word 0x04 0.--15. 1. " SYSCALL_COMMAND ,Opcode of the system call being requested" line.long 0x08 "CPUSS_SYSARG,SYSARG Control Register" group.long 0x20++0x0B line.long 0x00 "CPUSS_INT_SEL,Interrupt Multiplexer Select Register" bitfld.long 0x00 31. " DSI[31] ,DSI 31 interrupt source" "Fixed function,DSI" bitfld.long 0x00 30. " DSI[30] ,DSI 30 interrupt source" "Fixed function,DSI" bitfld.long 0x00 29. " DSI[29] ,DSI 29 interrupt source" "Fixed function,DSI" textline " " bitfld.long 0x00 28. " DSI[28] ,DSI 28 interrupt source" "Fixed function,DSI" bitfld.long 0x00 27. " DSI[27] ,DSI 27 interrupt source" "Fixed function,DSI" bitfld.long 0x00 26. " DSI[26] ,DSI 26 interrupt source" "Fixed function,DSI" textline " " bitfld.long 0x00 25. " DSI[25] ,DSI 25 interrupt source" "Fixed function,DSI" bitfld.long 0x00 24. " DSI[24] ,DSI 24 interrupt source" "Fixed function,DSI" bitfld.long 0x00 23. " DSI[23] ,DSI 23 interrupt source" "Fixed function,DSI" textline " " bitfld.long 0x00 22. " DSI[22] ,DSI 22 interrupt source" "Fixed function,DSI" bitfld.long 0x00 21. " DSI[21] ,DSI 21 interrupt source" "Fixed function,DSI" bitfld.long 0x00 20. " DSI[20] ,DSI 20 interrupt source" "Fixed function,DSI" textline " " bitfld.long 0x00 19. " DSI[19] ,DSI 19 interrupt source" "Fixed function,DSI" bitfld.long 0x00 18. " DSI[18] ,DSI 18 interrupt source" "Fixed function,DSI" bitfld.long 0x00 17. " DSI[17] ,DSI 17 interrupt source" "Fixed function,DSI" textline " " bitfld.long 0x00 16. " DSI[16] ,DSI 16 interrupt source" "Fixed function,DSI" bitfld.long 0x00 15. " DSI[15] ,DSI 15 interrupt source" "Fixed function,DSI" bitfld.long 0x00 14. " DSI[14] ,DSI 14 interrupt source" "Fixed function,DSI" textline " " bitfld.long 0x00 13. " DSI[13] ,DSI 13 interrupt source" "Fixed function,DSI" bitfld.long 0x00 12. " DSI[12] ,DSI 12 interrupt source" "Fixed function,DSI" bitfld.long 0x00 11. " DSI[11] ,DSI 11 interrupt source" "Fixed function,DSI" textline " " bitfld.long 0x00 10. " DSI[10] ,DSI 10 interrupt source" "Fixed function,DSI" bitfld.long 0x00 9. " DSI[9] ,DSI 9 interrupt source" "Fixed function,DSI" bitfld.long 0x00 8. " DSI[8] ,DSI 8 interrupt source" "Fixed function,DSI" textline " " bitfld.long 0x00 7. " DSI[7] ,DSI 7 interrupt source" "Fixed function,DSI" bitfld.long 0x00 6. " DSI[6] ,DSI 6 interrupt source" "Fixed function,DSI" bitfld.long 0x00 5. " DSI[5] ,DSI 5 interrupt source" "Fixed function,DSI" textline " " bitfld.long 0x00 4. " DSI[4] ,DSI 4 interrupt source" "Fixed function,DSI" bitfld.long 0x00 3. " DSI[3] ,DSI 3 interrupt source" "Fixed function,DSI" bitfld.long 0x00 2. " DSI[2] ,DSI 2 interrupt source" "Fixed function,DSI" textline " " bitfld.long 0x00 1. " DSI[1] ,DSI 1 interrupt source" "Fixed function,DSI" bitfld.long 0x00 0. " DSI[0] ,DSI 0 interrupt source" "Fixed function,DSI" line.long 0x04 "CPUSS_INT_MODE,DSI Interrupt Pulse Mode Register" bitfld.long 0x04 31. " DSI_INT_PULSE[31] ,DSI 31 interrupt format" "Level sensitive,Pulse generator on rising edge" bitfld.long 0x04 30. " DSI_INT_PULSE[30] ,DSI 30 interrupt format" "Level sensitive,Pulse generator on rising edge" bitfld.long 0x04 29. " DSI_INT_PULSE[29] ,DSI 29 interrupt format" "Level sensitive,Pulse generator on rising edge" textline " " bitfld.long 0x04 28. " DSI_INT_PULSE[28] ,DSI 28 interrupt format" "Level sensitive,Pulse generator on rising edge" bitfld.long 0x04 27. " DSI_INT_PULSE[27] ,DSI 27 interrupt format" "Level sensitive,Pulse generator on rising edge" bitfld.long 0x04 26. " DSI_INT_PULSE[26] ,DSI 26 interrupt format" "Level sensitive,Pulse generator on rising edge" textline " " bitfld.long 0x04 25. " DSI_INT_PULSE[25] ,DSI 25 interrupt format" "Level sensitive,Pulse generator on rising edge" bitfld.long 0x04 24. " DSI_INT_PULSE[24] ,DSI 24 interrupt format" "Level sensitive,Pulse generator on rising edge" bitfld.long 0x04 23. " DSI_INT_PULSE[23] ,DSI 23 interrupt format" "Level sensitive,Pulse generator on rising edge" textline " " bitfld.long 0x04 22. " DSI_INT_PULSE[22] ,DSI 22 interrupt format" "Level sensitive,Pulse generator on rising edge" bitfld.long 0x04 21. " DSI_INT_PULSE[21] ,DSI 21 interrupt format" "Level sensitive,Pulse generator on rising edge" bitfld.long 0x04 20. " DSI_INT_PULSE[20] ,DSI 20 interrupt format" "Level sensitive,Pulse generator on rising edge" textline " " bitfld.long 0x04 19. " DSI_INT_PULSE[19] ,DSI 19 interrupt format" "Level sensitive,Pulse generator on rising edge" bitfld.long 0x04 18. " DSI_INT_PULSE[18] ,DSI 18 interrupt format" "Level sensitive,Pulse generator on rising edge" bitfld.long 0x04 17. " DSI_INT_PULSE[17] ,DSI 17 interrupt format" "Level sensitive,Pulse generator on rising edge" textline " " bitfld.long 0x04 16. " DSI_INT_PULSE[16] ,DSI 16 interrupt format" "Level sensitive,Pulse generator on rising edge" bitfld.long 0x04 15. " DSI_INT_PULSE[15] ,DSI 15 interrupt format" "Level sensitive,Pulse generator on rising edge" bitfld.long 0x04 14. " DSI_INT_PULSE[14] ,DSI 14 interrupt format" "Level sensitive,Pulse generator on rising edge" textline " " bitfld.long 0x04 13. " DSI_INT_PULSE[13] ,DSI 13 interrupt format" "Level sensitive,Pulse generator on rising edge" bitfld.long 0x04 12. " DSI_INT_PULSE[12] ,DSI 12 interrupt format" "Level sensitive,Pulse generator on rising edge" bitfld.long 0x04 11. " DSI_INT_PULSE[11] ,DSI 11 interrupt format" "Level sensitive,Pulse generator on rising edge" textline " " bitfld.long 0x04 10. " DSI_INT_PULSE[10] ,DSI 10 interrupt format" "Level sensitive,Pulse generator on rising edge" bitfld.long 0x04 9. " DSI_INT_PULSE[9] ,DSI 9 interrupt format" "Level sensitive,Pulse generator on rising edge" bitfld.long 0x04 8. " DSI_INT_PULSE[8] ,DSI 8 interrupt format" "Level sensitive,Pulse generator on rising edge" textline " " bitfld.long 0x04 7. " DSI_INT_PULSE[7] ,DSI 7 interrupt format" "Level sensitive,Pulse generator on rising edge" bitfld.long 0x04 6. " DSI_INT_PULSE[6] ,DSI 6 interrupt format" "Level sensitive,Pulse generator on rising edge" bitfld.long 0x04 5. " DSI_INT_PULSE[5] ,DSI 5 interrupt format" "Level sensitive,Pulse generator on rising edge" textline " " bitfld.long 0x04 4. " DSI_INT_PULSE[4] ,DSI 4 interrupt format" "Level sensitive,Pulse generator on rising edge" bitfld.long 0x04 3. " DSI_INT_PULSE[3] ,DSI 3 interrupt format" "Level sensitive,Pulse generator on rising edge" bitfld.long 0x04 2. " DSI_INT_PULSE[2] ,DSI 2 interrupt format" "Level sensitive,Pulse generator on rising edge" textline " " bitfld.long 0x04 1. " DSI_INT_PULSE[1] ,DSI 1 interrupt format" "Level sensitive,Pulse generator on rising edge" bitfld.long 0x04 0. " DSI_INT_PULSE[0] ,DSI 0 interrupt format" "Level sensitive,Pulse generator on rising edge" line.long 0x08 "CPUSS_NMI_MODE,DSI NMI Pulse Mode Register" bitfld.long 0x08 0. " DSI_NMI_PULSE ,DSI NMI format" "Level sensitive,Pulse generator on rising edge" group.long 0x30++0x03 line.long 0x00 "CPUSS_FLASH_CTL,FLASH Control Register" bitfld.long 0x00 16.--17. " ARB ,Arbitration policy" "CPU,DW/DMA,Roundrobin,Roundrobin - sticky" bitfld.long 0x00 8. " FLASH_INVALIDATE ,Flash controller's buffers content invalidate" "Not invalidated,Invalidated" bitfld.long 0x00 4. " PREF_EN ,Prefetch enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " FLASH_WS ,ROM wait states" "0,1,2,?..." group.long 0x38++0x07 line.long 0x00 "CPUSS_RAM_CTL,RAM Control Register" bitfld.long 0x00 16.--17. " ARB ,Arbitration policy" "CPU,DW/DMA,Roundrobin,Roundrobin - sticky" line.long 0x04 "CPUSS_DMAC_CTL,DMA Controller Register" bitfld.long 0x04 16.--17. " ARB ,Arbitration policy" "CPU,DW/DMA,Roundrobin,Roundrobin - sticky" group.long 0x100++0x0B line.long 0x00 "CPUSS_SL_CTL0,Slave Control 0 Register" bitfld.long 0x00 16.--17. " ARB ,Arbitration policy" "CPU,DW/DMA,Roundrobin,Roundrobin - sticky" line.long 0x04 "CPUSS_SL_CTL1,Slave Control 1 Register" bitfld.long 0x04 16.--17. " ARB ,Arbitration policy" "CPU,DW/DMA,Roundrobin,Roundrobin - sticky" line.long 0x08 "CPUSS_SL_CTL2,Slave Control 2 Register" bitfld.long 0x08 16.--17. " ARB ,Arbitration policy" "CPU,DW/DMA,Roundrobin,Roundrobin - sticky" width 0x0B tree.end tree "CSD (CapSense Sigma-Delta)" sif (!cpuis("CY8C424?AZI-L433")&&!cpuis("CY8C4246AZI-L435")) tree "CSD0" base ad:0x40280000 width 14. rgroup.long 0x00++0x03 line.long 0x00 "CSD0_ID,ID & Revision Register" hexmask.long.word 0x00 16.--31. 1. " REVISION ,Version number" hexmask.long.word 0x00 0.--15. 1. " ID ,ID of CSD peripheral" group.long 0x04++0x0B line.long 0x00 "CSD0_CONFIG,Configuration and Control Register" bitfld.long 0x00 31. " ENABLE ,CSD master enable" "Disabled,Enabled" bitfld.long 0x00 23.--24. " REFBUF_DRV ,Current drive strength for reference buffer" "Off,Lowest,Mid,Highest" bitfld.long 0x00 22. " SENSE_INSEL ,Cmod capacitor connection" "SENSE_CHANNEL1,SENSE_AMUXA" bitfld.long 0x00 21. " REBUF_OUTSEL ,Reference buffer to AMUXBUS connection" "AMUXA,AMUXB" textline " " bitfld.long 0x00 19. " SENSE_COMP_EN ,Sense comparator enable" "Disabled,Enabled" bitfld.long 0x00 17. " POLARITY2 ,IDAC2 polarity control" "VSSIO,VDDIO" bitfld.long 0x00 16. " POLARITY ,IDAC polarity control" "VSSIO,VDDIO" bitfld.long 0x00 15. " COMP_PIN ,Reference buffer comparator connection" "CHANNEL1,CHANNEL2" textline " " bitfld.long 0x00 14. " COMP_MODE ,Comparator charging select" "CHARGE_BUF,CHARGE_IO" bitfld.long 0x00 13. " REFBUF_EN ,Reference buffer/comparator circuits for charging enable" "Disabled,Enabled" bitfld.long 0x00 12. " SENSE_EN ,Sensor and shield clocks enable" "Disabled,Enabled" bitfld.long 0x00 11. " SENSE_COMP_BW ,Selects bandwidth for sensing comparator" "LOW,HIGH" textline " " bitfld.long 0x00 9.--10. " SHIELD_DELAY ,Delay between shield clock and sensor clock" "OFF,,50NS,10NS" bitfld.long 0x00 8. " DSI_SENSE_EN ,DSI sensor clock enable" "Disabled,Enabled" bitfld.long 0x00 7. " PRS_12_8 ,Selects between 8-bit or 12-bit PRS sequence" "8-bit,12-bit" bitfld.long 0x00 6. " PRS_SELECT ,Selects between PRS and divide-by-2 for sensor clock" "DIV2,PRS" textline " " bitfld.long 0x00 5. " PRS_CLEAR ,Pseudo-random generator initial state set" "Disabled,Enabled" bitfld.long 0x00 3. " FILTER_ENABLE ,Digital filtering on the CSD comparator enable" "FILTER_OFF,FILTER_ON" bitfld.long 0x00 2. " BYPASS_SEL ,Selects the source of sensor clock" "PRS_OR_DIV2,DIRECT_CLOCK" bitfld.long 0x00 1. " SAMPLE_SYNC ,Double synchronizing of sample input from DSI enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " DSI_SAMPLE_EN ,DSI samples enable" "Disabled,Enabled" line.long 0x04 "CSD0_IDAC,CSD0 IDAC Configuration Register" bitfld.long 0x04 30. " FEEDBACK_MODE ,IDAC feedback mode select" "FLOP,COMP" bitfld.long 0x04 28. " POLARITY2_MIR ,IDAC2 polarity control" "VSSIO,VDDIO" bitfld.long 0x04 26. " IDAC2_RANGE ,Current multiplier setting for IDAC2" "4X,8X" bitfld.long 0x04 24.--25. " IDAC2_MODE ,IDAC2 mode select" "OFF,FIXED,VARIABLE,DSI" textline " " hexmask.long.byte 0x04 16.--22. 1. " IDAC2 ,Current setting for IDAC2" bitfld.long 0x04 12. " POLARITY1_MIR ,IDAC polarity control" "VSSIO,VDDIO" bitfld.long 0x04 10. " IDAC1_RANGE ,Current multiplier setting for IDAC1" "4X,8X" bitfld.long 0x04 8.--9. " IDAC1_MODE ,Controls the usage mode of IDAC1" "OFF,FIXED,VARIABLE,DSI" textline " " hexmask.long.byte 0x04 0.--7. 1. " IDAC1 ,Current setting for IDAC1" line.long 0x08 "CSD0_COUNTER,CSD Counter Register" hexmask.long.word 0x08 16.--31. 1. " PERIOD ,Remaining period" hexmask.long.word 0x08 0.--15. 1. " COUNTER ,Sample counter" rgroup.long 0x10++0x03 line.long 0x00 "CSD0_STATUS,CSD0 Status Register" bitfld.long 0x00 3. " SAMPLE ,CSD Sample output status" "High,Low" bitfld.long 0x00 2. " COMP_OUT ,CSD comparator output status" "C_LT_VREF,C_GT_VREF" bitfld.long 0x00 1. " CSD_SENSE ,CSD internal signal status" "High,Low" bitfld.long 0x00 0. " CSD_CHARGE ,CSD charge status" "High,Low" group.long 0x14++0x03 line.long 0x00 "CSD0_INTR,CSD0 Interrupt Request Register" setclrfld.long 0x00 0. 0x04 0. 0x00 0. " CSD ,CSD Interrupt" "No interrupt,Interrupt" group.long 0x1C++0x03 line.long 0x00 "CSD0_PWM,CSD0 PWM Register" bitfld.long 0x00 4.--5. " PWM_SEL ,PWM modulator mode" "OFF,,FIXED_HIGH,FIXED_LOW" bitfld.long 0x00 0.--3. " PWM_COUNT ,PWM counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xFF00++0x07 line.long 0x00 "CSD0_TRIM1,CSD0 Trim 1 Register" bitfld.long 0x00 4.--7. " IDAC2_SRC_TRIM ,IDAC2 trim bits for gain control in current source mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " IDAC1_SRC_TRIM ,IDAC1 trim bits for gain control in current source mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "CSD0_TRIM2,CSD0 Trim 2 Register" bitfld.long 0x04 4.--7. " IDAC2_SNK_TRIM ,IDAC2 trim bits for gain control in current sink mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " IDAC1_SNK_TRIM ,IDAC1 trim bits for gain control in current sink mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end endif sif (!cpuis("CY8C424?AZI-L433")&&!cpuis("CY8C4246AZI-L435")&&!cpuis("CY8C424?AZI-L423")) tree "CSD1" base ad:0x40290000 width 14. rgroup.long 0x00++0x03 line.long 0x00 "CSD1_ID,ID & Revision Register" hexmask.long.word 0x00 16.--31. 1. " REVISION ,Version number" hexmask.long.word 0x00 0.--15. 1. " ID ,ID of CSD peripheral" group.long 0x04++0x0B line.long 0x00 "CSD1_CONFIG,Configuration and Control Register" bitfld.long 0x00 31. " ENABLE ,CSD master enable" "Disabled,Enabled" bitfld.long 0x00 23.--24. " REFBUF_DRV ,Current drive strength for reference buffer" "Off,Lowest,Mid,Highest" bitfld.long 0x00 22. " SENSE_INSEL ,Cmod capacitor connection" "SENSE_CHANNEL1,SENSE_AMUXA" bitfld.long 0x00 21. " REBUF_OUTSEL ,Reference buffer to AMUXBUS connection" "AMUXA,AMUXB" textline " " bitfld.long 0x00 19. " SENSE_COMP_EN ,Sense comparator enable" "Disabled,Enabled" bitfld.long 0x00 17. " POLARITY2 ,IDAC2 polarity control" "VSSIO,VDDIO" bitfld.long 0x00 16. " POLARITY ,IDAC polarity control" "VSSIO,VDDIO" bitfld.long 0x00 15. " COMP_PIN ,Reference buffer comparator connection" "CHANNEL1,CHANNEL2" textline " " bitfld.long 0x00 14. " COMP_MODE ,Comparator charging select" "CHARGE_BUF,CHARGE_IO" bitfld.long 0x00 13. " REFBUF_EN ,Reference buffer/comparator circuits for charging enable" "Disabled,Enabled" bitfld.long 0x00 12. " SENSE_EN ,Sensor and shield clocks enable" "Disabled,Enabled" bitfld.long 0x00 11. " SENSE_COMP_BW ,Selects bandwidth for sensing comparator" "LOW,HIGH" textline " " bitfld.long 0x00 9.--10. " SHIELD_DELAY ,Delay between shield clock and sensor clock" "OFF,,50NS,10NS" bitfld.long 0x00 8. " DSI_SENSE_EN ,DSI sensor clock enable" "Disabled,Enabled" bitfld.long 0x00 7. " PRS_12_8 ,Selects between 8-bit or 12-bit PRS sequence" "8-bit,12-bit" bitfld.long 0x00 6. " PRS_SELECT ,Selects between PRS and divide-by-2 for sensor clock" "DIV2,PRS" textline " " bitfld.long 0x00 5. " PRS_CLEAR ,Pseudo-random generator initial state set" "Disabled,Enabled" bitfld.long 0x00 3. " FILTER_ENABLE ,Digital filtering on the CSD comparator enable" "FILTER_OFF,FILTER_ON" bitfld.long 0x00 2. " BYPASS_SEL ,Selects the source of sensor clock" "PRS_OR_DIV2,DIRECT_CLOCK" bitfld.long 0x00 1. " SAMPLE_SYNC ,Double synchronizing of sample input from DSI enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " DSI_SAMPLE_EN ,DSI samples enable" "Disabled,Enabled" line.long 0x04 "CSD1_IDAC,CSD1 IDAC Configuration Register" bitfld.long 0x04 30. " FEEDBACK_MODE ,IDAC feedback mode select" "FLOP,COMP" bitfld.long 0x04 28. " POLARITY2_MIR ,IDAC2 polarity control" "VSSIO,VDDIO" bitfld.long 0x04 26. " IDAC2_RANGE ,Current multiplier setting for IDAC2" "4X,8X" bitfld.long 0x04 24.--25. " IDAC2_MODE ,IDAC2 mode select" "OFF,FIXED,VARIABLE,DSI" textline " " hexmask.long.byte 0x04 16.--22. 1. " IDAC2 ,Current setting for IDAC2" bitfld.long 0x04 12. " POLARITY1_MIR ,IDAC polarity control" "VSSIO,VDDIO" bitfld.long 0x04 10. " IDAC1_RANGE ,Current multiplier setting for IDAC1" "4X,8X" bitfld.long 0x04 8.--9. " IDAC1_MODE ,Controls the usage mode of IDAC1" "OFF,FIXED,VARIABLE,DSI" textline " " hexmask.long.byte 0x04 0.--7. 1. " IDAC1 ,Current setting for IDAC1" line.long 0x08 "CSD1_COUNTER,CSD Counter Register" hexmask.long.word 0x08 16.--31. 1. " PERIOD ,Remaining period" hexmask.long.word 0x08 0.--15. 1. " COUNTER ,Sample counter" rgroup.long 0x10++0x03 line.long 0x00 "CSD1_STATUS,CSD1 Status Register" bitfld.long 0x00 3. " SAMPLE ,CSD Sample output status" "High,Low" bitfld.long 0x00 2. " COMP_OUT ,CSD comparator output status" "C_LT_VREF,C_GT_VREF" bitfld.long 0x00 1. " CSD_SENSE ,CSD internal signal status" "High,Low" bitfld.long 0x00 0. " CSD_CHARGE ,CSD charge status" "High,Low" group.long 0x14++0x03 line.long 0x00 "CSD1_INTR,CSD1 Interrupt Request Register" setclrfld.long 0x00 0. 0x04 0. 0x00 0. " CSD ,CSD Interrupt" "No interrupt,Interrupt" group.long 0x1C++0x03 line.long 0x00 "CSD1_PWM,CSD1 PWM Register" bitfld.long 0x00 4.--5. " PWM_SEL ,PWM modulator mode" "OFF,,FIXED_HIGH,FIXED_LOW" bitfld.long 0x00 0.--3. " PWM_COUNT ,PWM counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xFF00++0x07 line.long 0x00 "CSD1_TRIM1,CSD1 Trim 1 Register" bitfld.long 0x00 4.--7. " IDAC2_SRC_TRIM ,IDAC2 trim bits for gain control in current source mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " IDAC1_SRC_TRIM ,IDAC1 trim bits for gain control in current source mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "CSD1_TRIM2,CSD1 Trim 2 Register" bitfld.long 0x04 4.--7. " IDAC2_SNK_TRIM ,IDAC2 trim bits for gain control in current sink mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " IDAC1_SNK_TRIM ,IDAC1 trim bits for gain control in current sink mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end endif tree.end tree "CTBM (Continuous Time Block Mini)" tree "CTBM0" base ad:0x40300000 width 32. if (((per.l(ad:0x40300000))&0x40000000)==0x40000000) group.long 0x00++0x03 line.long 0x00 "CTBM0_CTB_CTRL,Global CTB And Power Control Register" bitfld.long 0x00 31. " ENABLED ,CTBM0 block enable" "Disabled,Enabled" bitfld.long 0x00 30. " DEEPSLEEP_ON ,CTBM0 in deepsleep power mode enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "CTBM0_CTB_CTRL,Global CTB And Power Control Register" bitfld.long 0x00 31. " ENABLED ,CTBM0 block enable" "Disabled,Enabled" bitfld.long 0x00 30. " DEEPSLEEP_ON ,CTBM0 in deepsleep power mode enable" "Disabled,?..." endif group.long 0x04++0x07 line.long 0x00 "CTBM0_OA_RES0_CTRL,Opamp0 and Resistor0 Control Register" sif CPUIS("CY8C6*") bitfld.long 0x00 12. " OA0_BOOST_EN ,Opamp0 gain booster enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 11. " OA0_PUMP_EN ,Opamp0 pump enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " OA0_COMPINT ,Opamp0 comparator edge detect" "Disabled,Rising,Falling,Both" bitfld.long 0x00 7. " OA0_DSI_LEVEL ,Opamp0 comparator DSI out level" "Pulse,Level" bitfld.long 0x00 6. " OA0_BYPASS_DSI_SYNC ,Opamp0 bypass comparator output synchronization for DSI (trigger) output" "Synchronize,Bypass" textline " " bitfld.long 0x00 5. " OA0_HYST_EN ,Opamp0 hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 4. " OA0_COMP_EN ,Opamp0 comparator enable" "Disabled,Enabled" sif CPUIS("CY8C6*") textline " " bitfld.long 0x00 3. " OA0_DRIVE_STR_SEL ,Opamp0 output drive strength select" "1X,10X" bitfld.long 0x00 0.--2. " OA0_PWR_MODE ,Opamp0 power mode select" "Off,Low,Medium,High,,PS_LOW,PS_MEDIUM,PS_HIGH" else textline " " bitfld.long 0x00 2. " OA0_DRIVE_STR_SEL ,Opamp0 output drive strength select" "1X,10X" bitfld.long 0x00 0.--1. " OA0_PWR_MODE ,Opamp0 power mode select" "Off,Low,Medium,High" endif line.long 0x04 "CTBM0_OA_RES1_CTRL,Opamp1 and resistor1 control" sif CPUIS("CY8C6*") bitfld.long 0x04 12. " OA1_BOOST_EN ,Opamp1 gain booster enable" "Disabled,Enabled" textline " " endif bitfld.long 0x04 11. " OA1_PUMP_EN ,Opamp1 pump enable" "Disabled,Enabled" bitfld.long 0x04 8.--9. " OA1_COMPINT ,Opamp1 comparator edge detect" "Disabled,Rising,Falling,Both" bitfld.long 0x04 7. " OA1_DSI_LEVEL ,Opamp1 comparator DSI out level" "Pulse,Level" bitfld.long 0x04 6. " OA1_BYPASS_DSI_SYNC ,Opamp1 bypass comparator output synchronization for DSI (trigger) output" "Synchronize,Bypass" textline " " bitfld.long 0x04 5. " OA1_HYST_EN ,Opamp1 hysteresis enable" "Disabled,Enabled" bitfld.long 0x04 4. " OA1_COMP_EN ,Opamp1 comparator enable" "Disabled,Enabled" sif CPUIS("CY8C6*") textline " " bitfld.long 0x04 3. " OA1_DRIVE_STR_SEL ,Opamp1 output drive strength select" "1X,10X" bitfld.long 0x04 0.--2. " OA1_PWR_MODE ,Opamp1 power mode select" "Off,Low,Medium,High,,PS_LOW,PS_MEDIUM,PS_HIGH" else textline " " bitfld.long 0x04 2. " OA1_DRIVE_STR_SEL ,Opamp1 output drive strength select" "1X,10X" bitfld.long 0x04 0.--1. " OA1_PWR_MODE ,Opamp1 power mode select" "Off,Low,Medium,High" endif rgroup.long 0x0C++0x03 line.long 0x00 "CTBM0_COMP_STAT,Comparator Status Register" bitfld.long 0x00 16. " OA1_COMP ,Opamp1 current comparator status" "0,1" bitfld.long 0x00 0. " OA0_COMP ,Opamp0 current comparator status" "0,1" sif CPUIS("CY8C6*") group.long 0x20++0x0B line.long 0x00 "CTBM0_INTR,Interrupt Request Register" eventfld.long 0x00 1. " COMP1 ,Comparator 1 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " COMP0 ,Comparator 0 interrupt" "No interrupt,Interrupt" line.long 0x04 "CTBM0_INTR_SET,Interrupt Set Register" bitfld.long 0x04 1. " COMP1 ,Set CTBM0_INTR.COMP1" "No effect,Set" bitfld.long 0x04 0. " COMP0 ,Set CTBM0_INTR.COMP0" "No effect,Set" line.long 0x08 "CTBM0_INTR_MASK,Interrupt Request Mask Register" bitfld.long 0x08 1. " COMP1_MASK ,Mask CTBM0_INTR.COMP1" "Masked,Not masked" bitfld.long 0x08 0. " COMP0_MASK ,Mask CTBM0_INTR.COMP0" "Masked,Not masked" rgroup.long 0x2C++0x03 line.long 0x00 "CTBM0_INTR_MASKED,Interrupt Request Masked Register" bitfld.long 0x00 1. " COMP1_MASKED ,Logical and of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 0. " COMP0_MASKED ,Logical and of corresponding request and mask bits" "No interrupt,Interrupt" else group.long 0x20++0x03 line.long 0x00 "CTBM0_INTR_set/clr,Interrupt Request Register" setclrfld.long 0x00 1. 0x04 1. 0x00 1. " COMP1 ,Comparator 1 interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 0. 0x04 0. 0x00 0. " COMP0 ,Comparator 0 interrupt" "No interrupt,Interrupt" group.long 0x28++0x03 line.long 0x00 "CTBM0_INTR_MASK,Interrupt Request Mask Register" bitfld.long 0x00 1. " COMP1_MASK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked" bitfld.long 0x00 0. " COMP0_MASK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked" rgroup.long 0x2C++0x03 line.long 0x00 "CTBM0_INTR_MASKED,Interrupt Request Masked Register" bitfld.long 0x00 1. " COMP1_MASKED ,Logical and of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 0. " COMP0_MASKED ,Logical and of corresponding request and mask bits" "No interrupt,Interrupt" endif group.long 0x80++0x0F line.long 0x00 "CTBM0_OA0_SW,Opamp0 Switch Control Register" bitfld.long 0x00 21. " OA0O_D81 ,Opamp0 output switch to short 1x with 10x drive" "Disabled,Enabled" bitfld.long 0x00 18. " OA0O_D51 ,Opamp0 output sarbus0 (ctbbus2 in CTB)" "Disabled,Enabled" bitfld.long 0x00 14. " OA0M_A81 ,Opamp0 negative terminal Opamp0 bottom" "Disabled,Enabled" bitfld.long 0x00 8. " OA0M_A11 ,Opamp0 negative terminal P1" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " OA0P_A30 ,Opamp0 positive terminal ctbbus0" "Disabled,Enabled" bitfld.long 0x00 2. " OA0P_A20 ,Opamp0 positive terminal P0" "Disabled,Enabled" bitfld.long 0x00 0. " OA0P_A00 ,Opamp0 positive terminal amuxbusa" "Disabled,Enabled" line.long 0x04 "CTBM0_OA0_SW_CLEAR,Opamp0 Switch Control Clear Register" eventfld.long 0x04 21. " OA0O_D81 ,Opamp0 output switch to short 1x with 10x drive clear" "No effect,Cleared" eventfld.long 0x04 18. " OA0O_D51 ,Opamp0 output sarbus0 (ctbbus2 in CTB) clear" "No effect,Cleared" eventfld.long 0x04 14. " OA0M_A81 ,Opamp0 negative terminal Opamp0 bottom clear" "No effect,Cleared" eventfld.long 0x04 8. " OA0M_A11 ,Opamp0 negative terminal P1 clear" "No effect,Cleared" textline " " eventfld.long 0x04 3. " OA0P_A30 ,Opamp0 positive terminal ctbbus0 clear" "No effect,Cleared" eventfld.long 0x04 2. " OA0P_A20 ,Opamp0 positive terminal P0 clear" "No effect,Cleared" eventfld.long 0x04 0. " OA0P_A00 ,Opamp0 positive terminal amuxbusa clear" "No effect,Cleared" line.long 0x08 "CTBM0_OA1_SW,Opamp1 Switch Control Register" bitfld.long 0x08 21. " OA1O_D82 ,Opamp1 output switch to short 1x with 10x drive" "Disabled,Enabled" bitfld.long 0x08 19. " OA1O_D62 ,Opamp1 output sarbus1 (ctbbus3 in CTB)" "Disabled,Enabled" bitfld.long 0x08 18. " OA1O_D52 ,Opamp1 output sarbus0 (ctbbus2 in CTB)" "Disabled,Enabled" bitfld.long 0x08 14. " OA1M_A82 ,Opamp1 negative terminal Opamp1 bottom" "Disabled,Enabled" textline " " bitfld.long 0x08 8. " OA1M_A22 ,Opamp1 negative terminal P4" "Disabled,Enabled" sif CPUIS("CY8C6*") textline " " bitfld.long 0x08 7. " OA1P_A73 ,Opamp1 positive terminal vref1" "Disabled,Enabled" textline " " endif textline " " bitfld.long 0x08 4. " OA1P_A43 ,Opamp1 positive terminal ctbbus1" "Disabled,Enabled" bitfld.long 0x08 1. " OA1P_A13 ,Opamp1 positive terminal P5" "Disabled,Enabled" bitfld.long 0x08 0. " OA1P_A03 ,Opamp1 positive terminal amuxbusb" "Disabled,Enabled" line.long 0x0C "CTBM0_OA1_SW_CLEAR,Opamp1 Switch Control Clear" eventfld.long 0x0C 21. " OA1O_D82 ,Opamp1 output switch to short 1x with 10x drive clear" "No effect,Cleared" eventfld.long 0x0C 19. " OA1O_D62 ,Opamp1 output sarbus1 (ctbbus3 in CTB) clear" "No effect,Cleared" eventfld.long 0x0C 18. " OA1O_D52 ,Opamp1 output sarbus0 (ctbbus2 in CTB) clear" "No effect,Cleared" eventfld.long 0x0C 14. " OA1M_A82 ,Opamp1 negative terminal Opamp1 bottom clear" "No effect,Cleared" textline " " eventfld.long 0x0C 8. " OA1M_A22 ,Opamp1 negative terminal P4 clear" "No effect,Cleared" sif CPUIS("CY8C6*") textline " " eventfld.long 0x0C 7. " OA1P_A73 ,Opamp1 positive terminal vref1" "Disabled,Enabled" textline " " endif textline " " eventfld.long 0x0C 4. " OA1P_A43 ,Opamp1 positive terminal ctbbus1 clear" "No effect,Cleared" eventfld.long 0x0C 1. " OA1P_A13 ,Opamp1 positive terminal P5 clear" "No effect,Cleared" eventfld.long 0x0C 0. " OA1P_A03 ,Opamp1 positive terminal amuxbusb clear" "No effect,Cleared" sif CPUIS("CY8C6*") group.long 0xA0++0x07 line.long 0x00 "CTBM0_CTD_SW,CTDAC Connection Switch Control" bitfld.long 0x00 15. " CTDH_ILR ,Hold capacitor leakage reduction" "Disabled,Enabled" bitfld.long 0x00 14. " CTDH_CIS ,Hold capacitor isolation" "Disabled,Enabled" bitfld.long 0x00 13. " CTDH_CA0 ,Hold capacitor to opamp input" "Disabled,Enabled" bitfld.long 0x00 12. " CTDH_CHD ,Hold capacitor disconnect" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " CTDH_COB ,Drive the CTDAC output with CTBM 1x output" "Disabled,Enabled" bitfld.long 0x00 9. " CTDO_COS ,ctdvout to Hold capacitor" "Disabled,Enabled" bitfld.long 0x00 8. " CTDO_C6H ,P6 pin to Hold capacitor" "Disabled,Enabled" bitfld.long 0x00 5. " CTDS_COR ,ctdvout to opamp input" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " CTDS_CRS ,ctdrefsense to opamp input" "Disabled,Enabled" bitfld.long 0x00 1. " CTDD_CRD ,Reference opamp output to ctdrefdrive" "Disabled,Enabled" line.long 0x04 "CTBM0_CTD_SW_CLEAR,CTDAC Connection Switch Control Clear" eventfld.long 0x04 15. " CTDH_ILR ,Hold capacitor leakage reduction clear" "No effect,Cleared" eventfld.long 0x04 14. " CTDH_CIS ,Hold capacitor isolation clear" "No effect,Cleared" eventfld.long 0x04 13. " CTDH_CA0 ,Hold capacitor to opamp input clear" "No effect,Cleared" eventfld.long 0x04 12. " CTDH_CHD ,Hold capacitor disconnect clear" "No effect,Cleared" textline " " eventfld.long 0x04 10. " CTDH_COB ,Drive the CTDAC output with CTBM 1x output clear" "No effect,Cleared" eventfld.long 0x04 9. " CTDO_COS ,ctdvout to Hold capacitor clear" "No effect,Cleared" eventfld.long 0x04 8. " CTDO_C6H ,P6 pin to Hold capacitor clear" "No effect,Cleared" eventfld.long 0x04 5. " CTDS_COR ,ctdvout to opamp input clear" "No effect,Cleared" textline " " eventfld.long 0x04 4. " CTDS_CRS ,ctdrefsense to opamp input clear" "No effect,Cleared" eventfld.long 0x04 1. " CTDD_CRD ,Reference opamp output to ctdrefdrive clear" "No effect,Cleared" group.long 0xC0++0x07 line.long 0x00 "CTBM0_SW_DS_CTRL,CTB Bus Switch Control" bitfld.long 0x00 31. " CTD_COS_DS_CTRL ,Hold capacitor Sample switch" "Disabled,Enabled" bitfld.long 0x00 11. " P3_DS_CTRL23 ,For P33, D52, D62" "Disabled,Enabled" bitfld.long 0x00 10. " P2_DS_CTRL23 ,For P22, D51" "Disabled,Enabled" line.long 0x04 "CTBM0_SW_SQ_CTRL,CTB Bus Switch SAR Sequencer Control" bitfld.long 0x04 11. " P3_SQ_CTRL23 ,For D52, D62" "Disabled,Enabled" bitfld.long 0x04 10. " P2_SQ_CTRL23 ,For D51" "Disabled,Enabled" rgroup.long 0xC8++0x03 line.long 0x00 "CTBM0_SW_STATUS,CTB Bus Switch Control Status" bitfld.long 0x00 31. " CTD_COS_STAT ,ctdvout to hold capacitor status" "Disabled,Enabled" bitfld.long 0x00 30. " OA1O_D62_STAT ,Opamp1 output sarbus1 (ctbbus3 in CTB) status" "Disabled,Enabled" bitfld.long 0x00 29. " OA1O_D52_STAT ,Opamp1 output sarbus0 (ctbbus2 in CTB) status" "Disabled,Enabled" bitfld.long 0x00 28. " OA0O_D51_STAT ,Opamp0 output sarbus0 (ctbbus2 in CTB) status" "Disabled,Enabled" else group.long 0xC0++0x03 line.long 0x00 "CTBM0_CTB_SW_HW_CTRL,CTB Bus Switch Control" bitfld.long 0x00 3. " P3_HW_CTRL ,Pin P3 switch" "0,1" bitfld.long 0x00 2. " P2_HW_CTRL ,Pin P2 switch" "0,1" rgroup.long 0xC4++0x03 line.long 0x00 "CTBM0_CTB_SW_STATUS,CTB Bus Switch Control Status Register" bitfld.long 0x00 30. " OA1O_D62_STAT ,Opamp1 output ctbbus3 status" "Disabled,Enabled" bitfld.long 0x00 29. " OA1O_D52_STAT ,Opamp1 output ctbbus2 status" "Disabled,Enabled" bitfld.long 0x00 28. " OA0O_D51_STAT ,Opamp0 output ctbbus2 status" "Disabled,Enabled" endif group.long 0xF00++0x17 line.long 0x00 "CTBM0_OA0_OFFSET_TRIM,Opamp0 Trim Control Register" bitfld.long 0x00 0.--5. " OA0_OFFSET_TRIM ,Opamp0 offset trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "CTBM0_OA0_SLOPE_OFFSET_TRIM,Opamp0 Slope Trim Control Register" bitfld.long 0x04 0.--5. " OA0_SLOPE_OFFSET_TRIM ,Opamp0 slope offset drift trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "CTBM0_OA0_COMP_TRIM,Opamp0 Compensation Trim Control Register" bitfld.long 0x08 0.--1. " OA0_COMP_TRIM ,Opamp0 compensation capacitor trim" "Disabled,Minimum,Medium,Maximum" line.long 0x0C "CTBM0_OA1_OFFSET_TRIM,Opamp1 Trim Control Register" bitfld.long 0x0C 0.--5. " OA1_OFFSET_TRIM ,Opamp1 offset trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "CTBM0_OA1_SLOPE_OFFSET_TRIM,Opamp1 Slope Trim Control Register" bitfld.long 0x10 0.--5. " OA1_SLOPE_OFFSET_TRIM ,Opamp1 slope offset drift trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x14 "CTBM0_OA1_COMP_TRIM,Opamp1 Compensation Trim Control Register" bitfld.long 0x14 0.--1. " OA1_COMP_TRIM ,Opamp1 compensation capacitor trim" "Disabled,Minimum,Medium,Maximum" width 0x0B tree.end sif (cpuis("*-L475")||cpuis("*-L479")||cpuis("*-L485")||cpuis("*-L489")) tree "CTBM1" base ad:0x40310000 width 32. if (((per.l(ad:0x40300000))&0x40000000)==0x40000000) group.long 0x00++0x03 line.long 0x00 "CTBM1_CTB_CTRL,Global CTB And Power Control Register" bitfld.long 0x00 31. " ENABLED ,CTBM0 block enable" "Disabled,Enabled" bitfld.long 0x00 30. " DEEPSLEEP_ON ,CTBM0 in deepsleep power mode enable" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "CTBM1_CTB_CTRL,Global CTB And Power Control Register" bitfld.long 0x00 31. " ENABLED ,CTBM0 block enable" "Disabled,Enabled" bitfld.long 0x00 30. " DEEPSLEEP_ON ,CTBM0 in deepsleep power mode enable" "Disabled,?..." endif group.long 0x04++0x07 line.long 0x00 "CTBM1_OA_RES0_CTRL,Opamp0 and Resistor0 Control Register" sif CPUIS("CY8C6*") bitfld.long 0x00 12. " OA0_BOOST_EN ,Opamp0 gain booster enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 11. " OA0_PUMP_EN ,Opamp0 pump enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " OA0_COMPINT ,Opamp0 comparator edge detect" "Disabled,Rising,Falling,Both" bitfld.long 0x00 7. " OA0_DSI_LEVEL ,Opamp0 comparator DSI out level" "Pulse,Level" bitfld.long 0x00 6. " OA0_BYPASS_DSI_SYNC ,Opamp0 bypass comparator output synchronization for DSI (trigger) output" "Synchronize,Bypass" textline " " bitfld.long 0x00 5. " OA0_HYST_EN ,Opamp0 hysteresis enable" "Disabled,Enabled" bitfld.long 0x00 4. " OA0_COMP_EN ,Opamp0 comparator enable" "Disabled,Enabled" sif CPUIS("CY8C6*") textline " " bitfld.long 0x00 3. " OA0_DRIVE_STR_SEL ,Opamp0 output drive strength select" "1X,10X" bitfld.long 0x00 0.--2. " OA0_PWR_MODE ,Opamp0 power mode select" "Off,Low,Medium,High,,PS_LOW,PS_MEDIUM,PS_HIGH" else textline " " bitfld.long 0x00 2. " OA0_DRIVE_STR_SEL ,Opamp0 output drive strength select" "1X,10X" bitfld.long 0x00 0.--1. " OA0_PWR_MODE ,Opamp0 power mode select" "Off,Low,Medium,High" endif line.long 0x04 "CTBM1_OA_RES1_CTRL,Opamp1 and resistor1 control" sif CPUIS("CY8C6*") bitfld.long 0x04 12. " OA1_BOOST_EN ,Opamp1 gain booster enable" "Disabled,Enabled" textline " " endif bitfld.long 0x04 11. " OA1_PUMP_EN ,Opamp1 pump enable" "Disabled,Enabled" bitfld.long 0x04 8.--9. " OA1_COMPINT ,Opamp1 comparator edge detect" "Disabled,Rising,Falling,Both" bitfld.long 0x04 7. " OA1_DSI_LEVEL ,Opamp1 comparator DSI out level" "Pulse,Level" bitfld.long 0x04 6. " OA1_BYPASS_DSI_SYNC ,Opamp1 bypass comparator output synchronization for DSI (trigger) output" "Synchronize,Bypass" textline " " bitfld.long 0x04 5. " OA1_HYST_EN ,Opamp1 hysteresis enable" "Disabled,Enabled" bitfld.long 0x04 4. " OA1_COMP_EN ,Opamp1 comparator enable" "Disabled,Enabled" sif CPUIS("CY8C6*") textline " " bitfld.long 0x04 3. " OA1_DRIVE_STR_SEL ,Opamp1 output drive strength select" "1X,10X" bitfld.long 0x04 0.--2. " OA1_PWR_MODE ,Opamp1 power mode select" "Off,Low,Medium,High,,PS_LOW,PS_MEDIUM,PS_HIGH" else textline " " bitfld.long 0x04 2. " OA1_DRIVE_STR_SEL ,Opamp1 output drive strength select" "1X,10X" bitfld.long 0x04 0.--1. " OA1_PWR_MODE ,Opamp1 power mode select" "Off,Low,Medium,High" endif rgroup.long 0x0C++0x03 line.long 0x00 "CTBM1_COMP_STAT,Comparator Status Register" bitfld.long 0x00 16. " OA1_COMP ,Opamp1 current comparator status" "0,1" bitfld.long 0x00 0. " OA0_COMP ,Opamp0 current comparator status" "0,1" sif CPUIS("CY8C6*") group.long 0x20++0x0B line.long 0x00 "CTBM1_INTR,Interrupt Request Register" eventfld.long 0x00 1. " COMP1 ,Comparator 1 interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " COMP0 ,Comparator 0 interrupt" "No interrupt,Interrupt" line.long 0x04 "CTBM1_INTR_SET,Interrupt Set Register" bitfld.long 0x04 1. " COMP1 ,Set CTBM1_INTR.COMP1" "No effect,Set" bitfld.long 0x04 0. " COMP0 ,Set CTBM1_INTR.COMP0" "No effect,Set" line.long 0x08 "CTBM1_INTR_MASK,Interrupt Request Mask Register" bitfld.long 0x08 1. " COMP1_MASK ,Mask CTBM1_INTR.COMP1" "Masked,Not masked" bitfld.long 0x08 0. " COMP0_MASK ,Mask CTBM1_INTR.COMP0" "Masked,Not masked" rgroup.long 0x2C++0x03 line.long 0x00 "CTBM1_INTR_MASKED,Interrupt Request Masked Register" bitfld.long 0x00 1. " COMP1_MASKED ,Logical and of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 0. " COMP0_MASKED ,Logical and of corresponding request and mask bits" "No interrupt,Interrupt" else group.long 0x20++0x03 line.long 0x00 "CTBM1_INTR_set/clr,Interrupt Request Register" setclrfld.long 0x00 1. 0x04 1. 0x00 1. " COMP1 ,Comparator 1 interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 0. 0x04 0. 0x00 0. " COMP0 ,Comparator 0 interrupt" "No interrupt,Interrupt" group.long 0x28++0x03 line.long 0x00 "CTBM1_INTR_MASK,Interrupt Request Mask Register" bitfld.long 0x00 1. " COMP1_MASK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked" bitfld.long 0x00 0. " COMP0_MASK ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked" rgroup.long 0x2C++0x03 line.long 0x00 "CTBM1_INTR_MASKED,Interrupt Request Masked Register" bitfld.long 0x00 1. " COMP1_MASKED ,Logical and of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 0. " COMP0_MASKED ,Logical and of corresponding request and mask bits" "No interrupt,Interrupt" endif group.long 0x80++0x0F line.long 0x00 "CTBM1_OA0_SW,Opamp0 Switch Control Register" bitfld.long 0x00 21. " OA0O_D81 ,Opamp0 output switch to short 1x with 10x drive" "Disabled,Enabled" bitfld.long 0x00 18. " OA0O_D51 ,Opamp0 output sarbus0 (ctbbus2 in CTB)" "Disabled,Enabled" bitfld.long 0x00 14. " OA0M_A81 ,Opamp0 negative terminal Opamp0 bottom" "Disabled,Enabled" bitfld.long 0x00 8. " OA0M_A11 ,Opamp0 negative terminal P1" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " OA0P_A30 ,Opamp0 positive terminal ctbbus0" "Disabled,Enabled" bitfld.long 0x00 2. " OA0P_A20 ,Opamp0 positive terminal P0" "Disabled,Enabled" bitfld.long 0x00 0. " OA0P_A00 ,Opamp0 positive terminal amuxbusa" "Disabled,Enabled" line.long 0x04 "CTBM1_OA0_SW_CLEAR,Opamp0 Switch Control Clear Register" eventfld.long 0x04 21. " OA0O_D81 ,Opamp0 output switch to short 1x with 10x drive clear" "No effect,Cleared" eventfld.long 0x04 18. " OA0O_D51 ,Opamp0 output sarbus0 (ctbbus2 in CTB) clear" "No effect,Cleared" eventfld.long 0x04 14. " OA0M_A81 ,Opamp0 negative terminal Opamp0 bottom clear" "No effect,Cleared" eventfld.long 0x04 8. " OA0M_A11 ,Opamp0 negative terminal P1 clear" "No effect,Cleared" textline " " eventfld.long 0x04 3. " OA0P_A30 ,Opamp0 positive terminal ctbbus0 clear" "No effect,Cleared" eventfld.long 0x04 2. " OA0P_A20 ,Opamp0 positive terminal P0 clear" "No effect,Cleared" eventfld.long 0x04 0. " OA0P_A00 ,Opamp0 positive terminal amuxbusa clear" "No effect,Cleared" line.long 0x08 "CTBM1_OA1_SW,Opamp1 Switch Control Register" bitfld.long 0x08 21. " OA1O_D82 ,Opamp1 output switch to short 1x with 10x drive" "Disabled,Enabled" bitfld.long 0x08 19. " OA1O_D62 ,Opamp1 output sarbus1 (ctbbus3 in CTB)" "Disabled,Enabled" bitfld.long 0x08 18. " OA1O_D52 ,Opamp1 output sarbus0 (ctbbus2 in CTB)" "Disabled,Enabled" bitfld.long 0x08 14. " OA1M_A82 ,Opamp1 negative terminal Opamp1 bottom" "Disabled,Enabled" textline " " bitfld.long 0x08 8. " OA1M_A22 ,Opamp1 negative terminal P4" "Disabled,Enabled" sif CPUIS("CY8C6*") textline " " bitfld.long 0x08 7. " OA1P_A73 ,Opamp1 positive terminal vref1" "Disabled,Enabled" textline " " endif textline " " bitfld.long 0x08 4. " OA1P_A43 ,Opamp1 positive terminal ctbbus1" "Disabled,Enabled" bitfld.long 0x08 1. " OA1P_A13 ,Opamp1 positive terminal P5" "Disabled,Enabled" bitfld.long 0x08 0. " OA1P_A03 ,Opamp1 positive terminal amuxbusb" "Disabled,Enabled" line.long 0x0C "CTBM1_OA1_SW_CLEAR,Opamp1 Switch Control Clear" eventfld.long 0x0C 21. " OA1O_D82 ,Opamp1 output switch to short 1x with 10x drive clear" "No effect,Cleared" eventfld.long 0x0C 19. " OA1O_D62 ,Opamp1 output sarbus1 (ctbbus3 in CTB) clear" "No effect,Cleared" eventfld.long 0x0C 18. " OA1O_D52 ,Opamp1 output sarbus0 (ctbbus2 in CTB) clear" "No effect,Cleared" eventfld.long 0x0C 14. " OA1M_A82 ,Opamp1 negative terminal Opamp1 bottom clear" "No effect,Cleared" textline " " eventfld.long 0x0C 8. " OA1M_A22 ,Opamp1 negative terminal P4 clear" "No effect,Cleared" sif CPUIS("CY8C6*") textline " " eventfld.long 0x0C 7. " OA1P_A73 ,Opamp1 positive terminal vref1" "Disabled,Enabled" textline " " endif textline " " eventfld.long 0x0C 4. " OA1P_A43 ,Opamp1 positive terminal ctbbus1 clear" "No effect,Cleared" eventfld.long 0x0C 1. " OA1P_A13 ,Opamp1 positive terminal P5 clear" "No effect,Cleared" eventfld.long 0x0C 0. " OA1P_A03 ,Opamp1 positive terminal amuxbusb clear" "No effect,Cleared" sif CPUIS("CY8C6*") group.long 0xA0++0x07 line.long 0x00 "CTBM1_CTD_SW,CTDAC Connection Switch Control" bitfld.long 0x00 15. " CTDH_ILR ,Hold capacitor leakage reduction" "Disabled,Enabled" bitfld.long 0x00 14. " CTDH_CIS ,Hold capacitor isolation" "Disabled,Enabled" bitfld.long 0x00 13. " CTDH_CA0 ,Hold capacitor to opamp input" "Disabled,Enabled" bitfld.long 0x00 12. " CTDH_CHD ,Hold capacitor disconnect" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " CTDH_COB ,Drive the CTDAC output with CTBM 1x output" "Disabled,Enabled" bitfld.long 0x00 9. " CTDO_COS ,ctdvout to Hold capacitor" "Disabled,Enabled" bitfld.long 0x00 8. " CTDO_C6H ,P6 pin to Hold capacitor" "Disabled,Enabled" bitfld.long 0x00 5. " CTDS_COR ,ctdvout to opamp input" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " CTDS_CRS ,ctdrefsense to opamp input" "Disabled,Enabled" bitfld.long 0x00 1. " CTDD_CRD ,Reference opamp output to ctdrefdrive" "Disabled,Enabled" line.long 0x04 "CTBM1_CTD_SW_CLEAR,CTDAC Connection Switch Control Clear" eventfld.long 0x04 15. " CTDH_ILR ,Hold capacitor leakage reduction clear" "No effect,Cleared" eventfld.long 0x04 14. " CTDH_CIS ,Hold capacitor isolation clear" "No effect,Cleared" eventfld.long 0x04 13. " CTDH_CA0 ,Hold capacitor to opamp input clear" "No effect,Cleared" eventfld.long 0x04 12. " CTDH_CHD ,Hold capacitor disconnect clear" "No effect,Cleared" textline " " eventfld.long 0x04 10. " CTDH_COB ,Drive the CTDAC output with CTBM 1x output clear" "No effect,Cleared" eventfld.long 0x04 9. " CTDO_COS ,ctdvout to Hold capacitor clear" "No effect,Cleared" eventfld.long 0x04 8. " CTDO_C6H ,P6 pin to Hold capacitor clear" "No effect,Cleared" eventfld.long 0x04 5. " CTDS_COR ,ctdvout to opamp input clear" "No effect,Cleared" textline " " eventfld.long 0x04 4. " CTDS_CRS ,ctdrefsense to opamp input clear" "No effect,Cleared" eventfld.long 0x04 1. " CTDD_CRD ,Reference opamp output to ctdrefdrive clear" "No effect,Cleared" group.long 0xC0++0x07 line.long 0x00 "CTBM1_SW_DS_CTRL,CTB Bus Switch Control" bitfld.long 0x00 31. " CTD_COS_DS_CTRL ,Hold capacitor Sample switch" "Disabled,Enabled" bitfld.long 0x00 11. " P3_DS_CTRL23 ,For P33, D52, D62" "Disabled,Enabled" bitfld.long 0x00 10. " P2_DS_CTRL23 ,For P22, D51" "Disabled,Enabled" line.long 0x04 "CTBM1_SW_SQ_CTRL,CTB Bus Switch SAR Sequencer Control" bitfld.long 0x04 11. " P3_SQ_CTRL23 ,For D52, D62" "Disabled,Enabled" bitfld.long 0x04 10. " P2_SQ_CTRL23 ,For D51" "Disabled,Enabled" rgroup.long 0xC8++0x03 line.long 0x00 "CTBM1_SW_STATUS,CTB Bus Switch Control Status" bitfld.long 0x00 31. " CTD_COS_STAT ,ctdvout to hold capacitor status" "Disabled,Enabled" bitfld.long 0x00 30. " OA1O_D62_STAT ,Opamp1 output sarbus1 (ctbbus3 in CTB) status" "Disabled,Enabled" bitfld.long 0x00 29. " OA1O_D52_STAT ,Opamp1 output sarbus0 (ctbbus2 in CTB) status" "Disabled,Enabled" bitfld.long 0x00 28. " OA0O_D51_STAT ,Opamp0 output sarbus0 (ctbbus2 in CTB) status" "Disabled,Enabled" else group.long 0xC0++0x03 line.long 0x00 "CTBM1_CTB_SW_HW_CTRL,CTB Bus Switch Control" bitfld.long 0x00 3. " P3_HW_CTRL ,Pin P3 switch" "0,1" bitfld.long 0x00 2. " P2_HW_CTRL ,Pin P2 switch" "0,1" rgroup.long 0xC4++0x03 line.long 0x00 "CTBM1_CTB_SW_STATUS,CTB Bus Switch Control Status Register" bitfld.long 0x00 30. " OA1O_D62_STAT ,Opamp1 output ctbbus3 status" "Disabled,Enabled" bitfld.long 0x00 29. " OA1O_D52_STAT ,Opamp1 output ctbbus2 status" "Disabled,Enabled" bitfld.long 0x00 28. " OA0O_D51_STAT ,Opamp0 output ctbbus2 status" "Disabled,Enabled" endif group.long 0xF00++0x17 line.long 0x00 "CTBM1_OA0_OFFSET_TRIM,Opamp0 Trim Control Register" bitfld.long 0x00 0.--5. " OA0_OFFSET_TRIM ,Opamp0 offset trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "CTBM1_OA0_SLOPE_OFFSET_TRIM,Opamp0 Slope Trim Control Register" bitfld.long 0x04 0.--5. " OA0_SLOPE_OFFSET_TRIM ,Opamp0 slope offset drift trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "CTBM1_OA0_COMP_TRIM,Opamp0 Compensation Trim Control Register" bitfld.long 0x08 0.--1. " OA0_COMP_TRIM ,Opamp0 compensation capacitor trim" "Disabled,Minimum,Medium,Maximum" line.long 0x0C "CTBM1_OA1_OFFSET_TRIM,Opamp1 Trim Control Register" bitfld.long 0x0C 0.--5. " OA1_OFFSET_TRIM ,Opamp1 offset trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "CTBM1_OA1_SLOPE_OFFSET_TRIM,Opamp1 Slope Trim Control Register" bitfld.long 0x10 0.--5. " OA1_SLOPE_OFFSET_TRIM ,Opamp1 slope offset drift trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x14 "CTBM1_OA1_COMP_TRIM,Opamp1 Compensation Trim Control Register" bitfld.long 0x14 0.--1. " OA1_COMP_TRIM ,Opamp1 compensation capacitor trim" "Disabled,Minimum,Medium,Maximum" width 0x0B tree.end endif tree.end tree "DMAC (Direct-Memory Access)" base ad:0x40101000 width 22. group.long 0x00++0x03 line.long 0x00 "DMAC_CTL,DMAC Control Register" bitfld.long 0x00 31. " ENABLED , DMAC enable" "Disabled,Enabled" rgroup.long 0x10++0x0F line.long 0x00 "DMAC_STATUS,DMAC Status Register" bitfld.long 0x00 31. " ACTIVE ,Specifies if there is a currently active channel in the data transfer engine" "No active,Active" bitfld.long 0x00 30. " PING_PONG ,Currently use channel descriptor" "Ping,Pong" bitfld.long 0x00 28.--29. " PRIO ,Currently active channel priority" "0,1,2,3" bitfld.long 0x00 24.--26. " STATE ,State of the data transfer engine" "Default,Loading descriptor,Loading data from source,Storing data at destination,Storing descriptor,Wait for trigger deactivation,Storing descriptor response,?..." textline " " bitfld.long 0x00 16.--20. " CH_ADDR ,Currently active channel number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Currently active data transfer index" line.long 0x04 "DMAC_STATUS_SRC_ADDR,Source Address Status Register" line.long 0x08 "DMAC_STATUS_DST_ADDR,Destination Address Status Register" line.long 0x0C "DMAC_STATUS_CH_ACT,Channel Activation Status Register" group.long 0x80++0x03 line.long 0x00 "DMAC_CH_CTL0,Channel 0 Control Register" bitfld.long 0x00 31. " ENABLED ,Channel 0 enable" "Disabled,Enabled" bitfld.long 0x00 30. " PING_PONG ,Currently use channel descriptor" "PING,PONG" bitfld.long 0x00 28.--29. " PRIO ,Channel 0 priority level" "0,1,2,3" group.long 0x84++0x03 line.long 0x00 "DMAC_CH_CTL1,Channel 1 Control Register" bitfld.long 0x00 31. " ENABLED ,Channel 1 enable" "Disabled,Enabled" bitfld.long 0x00 30. " PING_PONG ,Currently use channel descriptor" "PING,PONG" bitfld.long 0x00 28.--29. " PRIO ,Channel 1 priority level" "0,1,2,3" group.long 0x88++0x03 line.long 0x00 "DMAC_CH_CTL2,Channel 2 Control Register" bitfld.long 0x00 31. " ENABLED ,Channel 2 enable" "Disabled,Enabled" bitfld.long 0x00 30. " PING_PONG ,Currently use channel descriptor" "PING,PONG" bitfld.long 0x00 28.--29. " PRIO ,Channel 2 priority level" "0,1,2,3" group.long 0x8C++0x03 line.long 0x00 "DMAC_CH_CTL3,Channel 3 Control Register" bitfld.long 0x00 31. " ENABLED ,Channel 3 enable" "Disabled,Enabled" bitfld.long 0x00 30. " PING_PONG ,Currently use channel descriptor" "PING,PONG" bitfld.long 0x00 28.--29. " PRIO ,Channel 3 priority level" "0,1,2,3" group.long 0x90++0x03 line.long 0x00 "DMAC_CH_CTL4,Channel 4 Control Register" bitfld.long 0x00 31. " ENABLED ,Channel 4 enable" "Disabled,Enabled" bitfld.long 0x00 30. " PING_PONG ,Currently use channel descriptor" "PING,PONG" bitfld.long 0x00 28.--29. " PRIO ,Channel 4 priority level" "0,1,2,3" group.long 0x94++0x03 line.long 0x00 "DMAC_CH_CTL5,Channel 5 Control Register" bitfld.long 0x00 31. " ENABLED ,Channel 5 enable" "Disabled,Enabled" bitfld.long 0x00 30. " PING_PONG ,Currently use channel descriptor" "PING,PONG" bitfld.long 0x00 28.--29. " PRIO ,Channel 5 priority level" "0,1,2,3" group.long 0x98++0x03 line.long 0x00 "DMAC_CH_CTL6,Channel 6 Control Register" bitfld.long 0x00 31. " ENABLED ,Channel 6 enable" "Disabled,Enabled" bitfld.long 0x00 30. " PING_PONG ,Currently use channel descriptor" "PING,PONG" bitfld.long 0x00 28.--29. " PRIO ,Channel 6 priority level" "0,1,2,3" group.long 0x9C++0x03 line.long 0x00 "DMAC_CH_CTL7,Channel 7 Control Register" bitfld.long 0x00 31. " ENABLED ,Channel 7 enable" "Disabled,Enabled" bitfld.long 0x00 30. " PING_PONG ,Currently use channel descriptor" "PING,PONG" bitfld.long 0x00 28.--29. " PRIO ,Channel 7 priority level" "0,1,2,3" group.long 0xA0++0x03 line.long 0x00 "DMAC_CH_CTL8,Channel 8 Control Register" bitfld.long 0x00 31. " ENABLED ,Channel 8 enable" "Disabled,Enabled" bitfld.long 0x00 30. " PING_PONG ,Currently use channel descriptor" "PING,PONG" bitfld.long 0x00 28.--29. " PRIO ,Channel 8 priority level" "0,1,2,3" group.long 0xA4++0x03 line.long 0x00 "DMAC_CH_CTL9,Channel 9 Control Register" bitfld.long 0x00 31. " ENABLED ,Channel 9 enable" "Disabled,Enabled" bitfld.long 0x00 30. " PING_PONG ,Currently use channel descriptor" "PING,PONG" bitfld.long 0x00 28.--29. " PRIO ,Channel 9 priority level" "0,1,2,3" group.long 0xA8++0x03 line.long 0x00 "DMAC_CH_CTL10,Channel 10 Control Register" bitfld.long 0x00 31. " ENABLED ,Channel 10 enable" "Disabled,Enabled" bitfld.long 0x00 30. " PING_PONG ,Currently use channel descriptor" "PING,PONG" bitfld.long 0x00 28.--29. " PRIO ,Channel 10 priority level" "0,1,2,3" group.long 0xAC++0x03 line.long 0x00 "DMAC_CH_CTL11,Channel 11 Control Register" bitfld.long 0x00 31. " ENABLED ,Channel 11 enable" "Disabled,Enabled" bitfld.long 0x00 30. " PING_PONG ,Currently use channel descriptor" "PING,PONG" bitfld.long 0x00 28.--29. " PRIO ,Channel 11 priority level" "0,1,2,3" group.long 0xB0++0x03 line.long 0x00 "DMAC_CH_CTL12,Channel 12 Control Register" bitfld.long 0x00 31. " ENABLED ,Channel 12 enable" "Disabled,Enabled" bitfld.long 0x00 30. " PING_PONG ,Currently use channel descriptor" "PING,PONG" bitfld.long 0x00 28.--29. " PRIO ,Channel 12 priority level" "0,1,2,3" group.long 0xB4++0x03 line.long 0x00 "DMAC_CH_CTL13,Channel 13 Control Register" bitfld.long 0x00 31. " ENABLED ,Channel 13 enable" "Disabled,Enabled" bitfld.long 0x00 30. " PING_PONG ,Currently use channel descriptor" "PING,PONG" bitfld.long 0x00 28.--29. " PRIO ,Channel 13 priority level" "0,1,2,3" group.long 0xB8++0x03 line.long 0x00 "DMAC_CH_CTL14,Channel 14 Control Register" bitfld.long 0x00 31. " ENABLED ,Channel 14 enable" "Disabled,Enabled" bitfld.long 0x00 30. " PING_PONG ,Currently use channel descriptor" "PING,PONG" bitfld.long 0x00 28.--29. " PRIO ,Channel 14 priority level" "0,1,2,3" group.long 0xBC++0x03 line.long 0x00 "DMAC_CH_CTL15,Channel 15 Control Register" bitfld.long 0x00 31. " ENABLED ,Channel 15 enable" "Disabled,Enabled" bitfld.long 0x00 30. " PING_PONG ,Currently use channel descriptor" "PING,PONG" bitfld.long 0x00 28.--29. " PRIO ,Channel 15 priority level" "0,1,2,3" group.long 0xC0++0x03 line.long 0x00 "DMAC_CH_CTL16,Channel 16 Control Register" bitfld.long 0x00 31. " ENABLED ,Channel 16 enable" "Disabled,Enabled" bitfld.long 0x00 30. " PING_PONG ,Currently use channel descriptor" "PING,PONG" bitfld.long 0x00 28.--29. " PRIO ,Channel 16 priority level" "0,1,2,3" group.long 0xC4++0x03 line.long 0x00 "DMAC_CH_CTL17,Channel 17 Control Register" bitfld.long 0x00 31. " ENABLED ,Channel 17 enable" "Disabled,Enabled" bitfld.long 0x00 30. " PING_PONG ,Currently use channel descriptor" "PING,PONG" bitfld.long 0x00 28.--29. " PRIO ,Channel 17 priority level" "0,1,2,3" group.long 0xC8++0x03 line.long 0x00 "DMAC_CH_CTL18,Channel 18 Control Register" bitfld.long 0x00 31. " ENABLED ,Channel 18 enable" "Disabled,Enabled" bitfld.long 0x00 30. " PING_PONG ,Currently use channel descriptor" "PING,PONG" bitfld.long 0x00 28.--29. " PRIO ,Channel 18 priority level" "0,1,2,3" group.long 0xCC++0x03 line.long 0x00 "DMAC_CH_CTL19,Channel 19 Control Register" bitfld.long 0x00 31. " ENABLED ,Channel 19 enable" "Disabled,Enabled" bitfld.long 0x00 30. " PING_PONG ,Currently use channel descriptor" "PING,PONG" bitfld.long 0x00 28.--29. " PRIO ,Channel 19 priority level" "0,1,2,3" group.long 0xD0++0x03 line.long 0x00 "DMAC_CH_CTL20,Channel 20 Control Register" bitfld.long 0x00 31. " ENABLED ,Channel 20 enable" "Disabled,Enabled" bitfld.long 0x00 30. " PING_PONG ,Currently use channel descriptor" "PING,PONG" bitfld.long 0x00 28.--29. " PRIO ,Channel 20 priority level" "0,1,2,3" group.long 0xD4++0x03 line.long 0x00 "DMAC_CH_CTL21,Channel 21 Control Register" bitfld.long 0x00 31. " ENABLED ,Channel 21 enable" "Disabled,Enabled" bitfld.long 0x00 30. " PING_PONG ,Currently use channel descriptor" "PING,PONG" bitfld.long 0x00 28.--29. " PRIO ,Channel 21 priority level" "0,1,2,3" group.long 0xD8++0x03 line.long 0x00 "DMAC_CH_CTL22,Channel 22 Control Register" bitfld.long 0x00 31. " ENABLED ,Channel 22 enable" "Disabled,Enabled" bitfld.long 0x00 30. " PING_PONG ,Currently use channel descriptor" "PING,PONG" bitfld.long 0x00 28.--29. " PRIO ,Channel 22 priority level" "0,1,2,3" group.long 0xDC++0x03 line.long 0x00 "DMAC_CH_CTL23,Channel 23 Control Register" bitfld.long 0x00 31. " ENABLED ,Channel 23 enable" "Disabled,Enabled" bitfld.long 0x00 30. " PING_PONG ,Currently use channel descriptor" "PING,PONG" bitfld.long 0x00 28.--29. " PRIO ,Channel 23 priority level" "0,1,2,3" group.long 0xE0++0x03 line.long 0x00 "DMAC_CH_CTL24,Channel 24 Control Register" bitfld.long 0x00 31. " ENABLED ,Channel 24 enable" "Disabled,Enabled" bitfld.long 0x00 30. " PING_PONG ,Currently use channel descriptor" "PING,PONG" bitfld.long 0x00 28.--29. " PRIO ,Channel 24 priority level" "0,1,2,3" group.long 0xE4++0x03 line.long 0x00 "DMAC_CH_CTL25,Channel 25 Control Register" bitfld.long 0x00 31. " ENABLED ,Channel 25 enable" "Disabled,Enabled" bitfld.long 0x00 30. " PING_PONG ,Currently use channel descriptor" "PING,PONG" bitfld.long 0x00 28.--29. " PRIO ,Channel 25 priority level" "0,1,2,3" group.long 0xE8++0x03 line.long 0x00 "DMAC_CH_CTL26,Channel 26 Control Register" bitfld.long 0x00 31. " ENABLED ,Channel 26 enable" "Disabled,Enabled" bitfld.long 0x00 30. " PING_PONG ,Currently use channel descriptor" "PING,PONG" bitfld.long 0x00 28.--29. " PRIO ,Channel 26 priority level" "0,1,2,3" group.long 0xEC++0x03 line.long 0x00 "DMAC_CH_CTL27,Channel 27 Control Register" bitfld.long 0x00 31. " ENABLED ,Channel 27 enable" "Disabled,Enabled" bitfld.long 0x00 30. " PING_PONG ,Currently use channel descriptor" "PING,PONG" bitfld.long 0x00 28.--29. " PRIO ,Channel 27 priority level" "0,1,2,3" group.long 0xF0++0x03 line.long 0x00 "DMAC_CH_CTL28,Channel 28 Control Register" bitfld.long 0x00 31. " ENABLED ,Channel 28 enable" "Disabled,Enabled" bitfld.long 0x00 30. " PING_PONG ,Currently use channel descriptor" "PING,PONG" bitfld.long 0x00 28.--29. " PRIO ,Channel 28 priority level" "0,1,2,3" group.long 0xF4++0x03 line.long 0x00 "DMAC_CH_CTL29,Channel 29 Control Register" bitfld.long 0x00 31. " ENABLED ,Channel 29 enable" "Disabled,Enabled" bitfld.long 0x00 30. " PING_PONG ,Currently use channel descriptor" "PING,PONG" bitfld.long 0x00 28.--29. " PRIO ,Channel 29 priority level" "0,1,2,3" group.long 0xF8++0x03 line.long 0x00 "DMAC_CH_CTL30,Channel 30 Control Register" bitfld.long 0x00 31. " ENABLED ,Channel 30 enable" "Disabled,Enabled" bitfld.long 0x00 30. " PING_PONG ,Currently use channel descriptor" "PING,PONG" bitfld.long 0x00 28.--29. " PRIO ,Channel 30 priority level" "0,1,2,3" group.long 0xFC++0x03 line.long 0x00 "DMAC_CH_CTL31,Channel 31 Control Register" bitfld.long 0x00 31. " ENABLED ,Channel 31 enable" "Disabled,Enabled" bitfld.long 0x00 30. " PING_PONG ,Currently use channel descriptor" "PING,PONG" bitfld.long 0x00 28.--29. " PRIO ,Channel 31 priority level" "0,1,2,3" group.long 0x7F0++0x0B line.long 0x00 "DMAC_INTR,DMAC Interrupt Register" setclrfld.long 0x00 31. 0x04 31. 0x00 31. " CH[31] ,Channel 31 interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 30. 0x04 30. 0x00 30. " [30] ,Channel 30 interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 29. 0x04 29. 0x00 29. " [29] ,Channel 29 interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 28. 0x04 28. 0x00 28. " [28] ,Channel 28 interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 27. 0x04 27. 0x00 27. " CH[27] ,Channel 27 interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 26. 0x04 26. 0x00 26. " [26] ,Channel 26 interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 25. 0x04 25. 0x00 25. " [25] ,Channel 25 interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 24. 0x04 24. 0x00 24. " [24] ,Channel 24 interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 23. 0x04 23. 0x00 23. " CH[23] ,Channel 23 interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 22. 0x04 22. 0x00 22. " [22] ,Channel 22 interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 21. 0x04 21. 0x00 21. " [21] ,Channel 21 interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 20. 0x04 20. 0x00 20. " [20] ,Channel 20 interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 19. 0x04 19. 0x00 19. " CH[19] ,Channel 19 interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 18. 0x04 18. 0x00 18. " [18] ,Channel 18 interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 17. 0x04 17. 0x00 17. " [17] ,Channel 17 interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 16. 0x04 16. 0x00 16. " [16] ,Channel 16 interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 15. 0x04 15. 0x00 15. " CH[15] ,Channel 15 interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 14. 0x04 14. 0x00 14. " [14] ,Channel 14 interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 13. 0x04 13. 0x00 13. " [13] ,Channel 13 interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 12. 0x04 12. 0x00 12. " [12] ,Channel 12 interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 11. 0x04 11. 0x00 11. " CH[11] ,Channel 11 interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 10. 0x04 10. 0x00 10. " [10] ,Channel 10 interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 9. 0x04 9. 0x00 9. " [9] ,Channel 9 interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 8. 0x04 8. 0x00 8. " [8] ,Channel 8 interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 7. 0x04 7. 0x00 7. " CH[7] ,Channel 7 interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 6. 0x04 6. 0x00 6. " [6] ,Channel 6 interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 5. 0x04 5. 0x00 5. " [5] ,Channel 5 interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 4. 0x04 4. 0x00 4. " [4] ,Channel 4 interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 3. 0x04 3. 0x00 3. " CH[3] ,Channel 3 interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 2. 0x04 2. 0x00 2. " [2] ,Channel 2 interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 1. 0x04 1. 0x00 1. " [1] ,Channel 1 interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 0. 0x04 0. 0x00 0. " [0] ,Channel 0 interrupt" "No interrupt,Interrupt" group.long 0x7F8++0x03 line.long 0x00 "DMAC_INTR_MASK,DMAC Interrupt Mask Register" bitfld.long 0x00 31. " CH[31] ,Channel 31 interrupt mask" "Not masked,Masked" bitfld.long 0x00 30. " [30] ,Channel 30 interrupt mask" "Not masked,Masked" bitfld.long 0x00 29. " [29] ,Channel 29 interrupt mask" "Not masked,Masked" bitfld.long 0x00 28. " [28] ,Channel 28 interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 27. " CH[27] ,Channel 27 interrupt mask" "Not masked,Masked" bitfld.long 0x00 26. " [26] ,Channel 26 interrupt mask" "Not masked,Masked" bitfld.long 0x00 25. " [25] ,Channel 25 interrupt mask" "Not masked,Masked" bitfld.long 0x00 24. " [24] ,Channel 24 interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 23. " CH[23] ,Channel 23 interrupt mask" "Not masked,Masked" bitfld.long 0x00 22. " [22] ,Channel 22 interrupt mask" "Not masked,Masked" bitfld.long 0x00 21. " [21] ,Channel 21 interrupt mask" "Not masked,Masked" bitfld.long 0x00 20. " [20] ,Channel 20 interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 19. " CH[19] ,Channel 19 interrupt mask" "Not masked,Masked" bitfld.long 0x00 18. " [18] ,Channel 18 interrupt mask" "Not masked,Masked" bitfld.long 0x00 17. " [17] ,Channel 17 interrupt mask" "Not masked,Masked" bitfld.long 0x00 16. " [16] ,Channel 16 interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 15. " CH[15] ,Channel 15 interrupt mask" "Not masked,Masked" bitfld.long 0x00 14. " [14] ,Channel 14 interrupt mask" "Not masked,Masked" bitfld.long 0x00 13. " [13] ,Channel 13 interrupt mask" "Not masked,Masked" bitfld.long 0x00 12. " [12] ,Channel 12 interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 11. " CH[11] ,Channel 11 interrupt mask" "Not masked,Masked" bitfld.long 0x00 10. " [10] ,Channel 10 interrupt mask" "Not masked,Masked" bitfld.long 0x00 9. " [9] ,Channel 9 interrupt mask" "Not masked,Masked" bitfld.long 0x00 8. " [8] ,Channel 8 interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 7. " CH[7] ,Channel 7 interrupt mask" "Not masked,Masked" bitfld.long 0x00 6. " [6] ,Channel 6 interrupt mask" "Not masked,Masked" bitfld.long 0x00 5. " [5] ,Channel 5 interrupt mask" "Not masked,Masked" bitfld.long 0x00 4. " [4] ,Channel 4 interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 3. " CH[3] ,Channel 3 interrupt mask" "Not masked,Masked" bitfld.long 0x00 2. " [2] ,Channel 2 interrupt mask" "Not masked,Masked" bitfld.long 0x00 1. " [1] ,Channel 1 interrupt mask" "Not masked,Masked" bitfld.long 0x00 0. " [0] ,Channel 0 interrupt mask" "Not masked,Masked" rgroup.long 0x7FC++0x03 line.long 0x00 "DMAC_INTR_MASKED,Interrupt Masked Register" bitfld.long 0x00 31. " CH[31] ,Channel 31 logical and of corresponding request and mask fields" "No interrupt,Interrupt" bitfld.long 0x00 30. " [30] ,Channel 30 logical and of corresponding request and mask fields" "No interrupt,Interrupt" bitfld.long 0x00 29. " [29] ,Channel 29 logical and of corresponding request and mask fields" "No interrupt,Interrupt" bitfld.long 0x00 28. " [28] ,Channel 28 logical and of corresponding request and mask fields" "No interrupt,Interrupt" textline " " bitfld.long 0x00 27. " CH[27] ,Channel 27 logical and of corresponding request and mask fields" "No interrupt,Interrupt" bitfld.long 0x00 26. " [26] ,Channel 26 logical and of corresponding request and mask fields" "No interrupt,Interrupt" bitfld.long 0x00 25. " [25] ,Channel 25 logical and of corresponding request and mask fields" "No interrupt,Interrupt" bitfld.long 0x00 24. " [24] ,Channel 24 logical and of corresponding request and mask fields" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " CH[23] ,Channel 23 logical and of corresponding request and mask fields" "No interrupt,Interrupt" bitfld.long 0x00 22. " [22] ,Channel 22 logical and of corresponding request and mask fields" "No interrupt,Interrupt" bitfld.long 0x00 21. " [21] ,Channel 21 logical and of corresponding request and mask fields" "No interrupt,Interrupt" bitfld.long 0x00 20. " [20] ,Channel 20 logical and of corresponding request and mask fields" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " CH[19] ,Channel 19 logical and of corresponding request and mask fields" "No interrupt,Interrupt" bitfld.long 0x00 18. " [18] ,Channel 18 logical and of corresponding request and mask fields" "No interrupt,Interrupt" bitfld.long 0x00 17. " [17] ,Channel 17 logical and of corresponding request and mask fields" "No interrupt,Interrupt" bitfld.long 0x00 16. " [16] ,Channel 16 logical and of corresponding request and mask fields" "No interrupt,Interrupt" textline " " bitfld.long 0x00 15. " CH[15] ,Channel 15 logical and of corresponding request and mask fields" "No interrupt,Interrupt" bitfld.long 0x00 14. " [14] ,Channel 14 logical and of corresponding request and mask fields" "No interrupt,Interrupt" bitfld.long 0x00 13. " [13] ,Channel 13 logical and of corresponding request and mask fields" "No interrupt,Interrupt" bitfld.long 0x00 12. " [12] ,Channel 12 logical and of corresponding request and mask fields" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " CH[11] ,Channel 11 logical and of corresponding request and mask fields" "No interrupt,Interrupt" bitfld.long 0x00 10. " [10] ,Channel 10 logical and of corresponding request and mask fields" "No interrupt,Interrupt" bitfld.long 0x00 9. " [9] ,Channel 9 logical and of corresponding request and mask fields" "No interrupt,Interrupt" bitfld.long 0x00 8. " [8] ,Channel 8 logical and of corresponding request and mask fields" "No interrupt,Interrupt" textline " " bitfld.long 0x00 7. " CH[7] ,Channel 7 logical and of corresponding request and mask fields" "No interrupt,Interrupt" bitfld.long 0x00 6. " [6] ,Channel 6 logical and of corresponding request and mask fields" "No interrupt,Interrupt" bitfld.long 0x00 5. " [5] ,Channel 5 logical and of corresponding request and mask fields" "No interrupt,Interrupt" bitfld.long 0x00 4. " [4] ,Channel 4 logical and of corresponding request and mask fields" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " CH[3] ,Channel 3 logical and of corresponding request and mask fields" "No interrupt,Interrupt" bitfld.long 0x00 2. " [2] ,Channel 2 logical and of corresponding request and mask fields" "No interrupt,Interrupt" bitfld.long 0x00 1. " [1] ,Channel 1 logical and of corresponding request and mask fields" "No interrupt,Interrupt" bitfld.long 0x00 0. " [0] ,Channel 0 logical and of corresponding request and mask fields" "No interrupt,Interrupt" width 26. tree "DMAC Descriptor Registers" group.long 0x800++0x07 line.long 0x00 "DMAC_DESCR0_PING_SRC,Ping Source Address" line.long 0x04 "DMAC_DESCR0_PING_DST,Ping Destination Address" if (((per.l(ad:0x40101000+0x0C+0x800))&0x80000000)==0x80000000) group.long (0x800+0x08)++0x03 line.long 0x00 "DMAC_DESCR0_PING_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0x800+0x08)++0x03 line.long 0x00 "DMAC_DESCR0_PING_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0x800+0x0C)++0x0B line.long 0x00 "DMAC_DESCR0_PING_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" line.long 0x04 "DMAC_DESCR0_PONG_SRC,Pong Source Address" line.long 0x08 "DMAC_DESCR0_PONG_DST,Pong Destination Address" if (((per.l(ad:0x40101000+0x1C+0x800))&0x80000000)==0x80000000) group.long (0x800+0x18)++0x03 line.long 0x00 "DMAC_DESCR0_PONG_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0x800+0x18)++0x03 line.long 0x00 "DMAC_DESCR0_PONG_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0x800+0x1C)++0x03 line.long 0x00 "DMAC_DESCR0_PONG_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" group.long 0x820++0x07 line.long 0x00 "DMAC_DESCR1_PING_SRC,Ping Source Address" line.long 0x04 "DMAC_DESCR1_PING_DST,Ping Destination Address" if (((per.l(ad:0x40101000+0x0C+0x820))&0x80000000)==0x80000000) group.long (0x820+0x08)++0x03 line.long 0x00 "DMAC_DESCR1_PING_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0x820+0x08)++0x03 line.long 0x00 "DMAC_DESCR1_PING_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0x820+0x0C)++0x0B line.long 0x00 "DMAC_DESCR1_PING_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" line.long 0x04 "DMAC_DESCR1_PONG_SRC,Pong Source Address" line.long 0x08 "DMAC_DESCR1_PONG_DST,Pong Destination Address" if (((per.l(ad:0x40101000+0x1C+0x820))&0x80000000)==0x80000000) group.long (0x820+0x18)++0x03 line.long 0x00 "DMAC_DESCR1_PONG_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0x820+0x18)++0x03 line.long 0x00 "DMAC_DESCR1_PONG_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0x820+0x1C)++0x03 line.long 0x00 "DMAC_DESCR1_PONG_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" group.long 0x840++0x07 line.long 0x00 "DMAC_DESCR2_PING_SRC,Ping Source Address" line.long 0x04 "DMAC_DESCR2_PING_DST,Ping Destination Address" if (((per.l(ad:0x40101000+0x0C+0x840))&0x80000000)==0x80000000) group.long (0x840+0x08)++0x03 line.long 0x00 "DMAC_DESCR2_PING_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0x840+0x08)++0x03 line.long 0x00 "DMAC_DESCR2_PING_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0x840+0x0C)++0x0B line.long 0x00 "DMAC_DESCR2_PING_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" line.long 0x04 "DMAC_DESCR2_PONG_SRC,Pong Source Address" line.long 0x08 "DMAC_DESCR2_PONG_DST,Pong Destination Address" if (((per.l(ad:0x40101000+0x1C+0x840))&0x80000000)==0x80000000) group.long (0x840+0x18)++0x03 line.long 0x00 "DMAC_DESCR2_PONG_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0x840+0x18)++0x03 line.long 0x00 "DMAC_DESCR2_PONG_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0x840+0x1C)++0x03 line.long 0x00 "DMAC_DESCR2_PONG_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" group.long 0x860++0x07 line.long 0x00 "DMAC_DESCR3_PING_SRC,Ping Source Address" line.long 0x04 "DMAC_DESCR3_PING_DST,Ping Destination Address" if (((per.l(ad:0x40101000+0x0C+0x860))&0x80000000)==0x80000000) group.long (0x860+0x08)++0x03 line.long 0x00 "DMAC_DESCR3_PING_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0x860+0x08)++0x03 line.long 0x00 "DMAC_DESCR3_PING_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0x860+0x0C)++0x0B line.long 0x00 "DMAC_DESCR3_PING_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" line.long 0x04 "DMAC_DESCR3_PONG_SRC,Pong Source Address" line.long 0x08 "DMAC_DESCR3_PONG_DST,Pong Destination Address" if (((per.l(ad:0x40101000+0x1C+0x860))&0x80000000)==0x80000000) group.long (0x860+0x18)++0x03 line.long 0x00 "DMAC_DESCR3_PONG_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0x860+0x18)++0x03 line.long 0x00 "DMAC_DESCR3_PONG_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0x860+0x1C)++0x03 line.long 0x00 "DMAC_DESCR3_PONG_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" group.long 0x880++0x07 line.long 0x00 "DMAC_DESCR4_PING_SRC,Ping Source Address" line.long 0x04 "DMAC_DESCR4_PING_DST,Ping Destination Address" if (((per.l(ad:0x40101000+0x0C+0x880))&0x80000000)==0x80000000) group.long (0x880+0x08)++0x03 line.long 0x00 "DMAC_DESCR4_PING_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0x880+0x08)++0x03 line.long 0x00 "DMAC_DESCR4_PING_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0x880+0x0C)++0x0B line.long 0x00 "DMAC_DESCR4_PING_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" line.long 0x04 "DMAC_DESCR4_PONG_SRC,Pong Source Address" line.long 0x08 "DMAC_DESCR4_PONG_DST,Pong Destination Address" if (((per.l(ad:0x40101000+0x1C+0x880))&0x80000000)==0x80000000) group.long (0x880+0x18)++0x03 line.long 0x00 "DMAC_DESCR4_PONG_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0x880+0x18)++0x03 line.long 0x00 "DMAC_DESCR4_PONG_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0x880+0x1C)++0x03 line.long 0x00 "DMAC_DESCR4_PONG_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" group.long 0x8A0++0x07 line.long 0x00 "DMAC_DESCR5_PING_SRC,Ping Source Address" line.long 0x04 "DMAC_DESCR5_PING_DST,Ping Destination Address" if (((per.l(ad:0x40101000+0x0C+0x8A0))&0x80000000)==0x80000000) group.long (0x8A0+0x08)++0x03 line.long 0x00 "DMAC_DESCR5_PING_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0x8A0+0x08)++0x03 line.long 0x00 "DMAC_DESCR5_PING_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0x8A0+0x0C)++0x0B line.long 0x00 "DMAC_DESCR5_PING_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" line.long 0x04 "DMAC_DESCR5_PONG_SRC,Pong Source Address" line.long 0x08 "DMAC_DESCR5_PONG_DST,Pong Destination Address" if (((per.l(ad:0x40101000+0x1C+0x8A0))&0x80000000)==0x80000000) group.long (0x8A0+0x18)++0x03 line.long 0x00 "DMAC_DESCR5_PONG_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0x8A0+0x18)++0x03 line.long 0x00 "DMAC_DESCR5_PONG_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0x8A0+0x1C)++0x03 line.long 0x00 "DMAC_DESCR5_PONG_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" group.long 0x8C0++0x07 line.long 0x00 "DMAC_DESCR6_PING_SRC,Ping Source Address" line.long 0x04 "DMAC_DESCR6_PING_DST,Ping Destination Address" if (((per.l(ad:0x40101000+0x0C+0x8C0))&0x80000000)==0x80000000) group.long (0x8C0+0x08)++0x03 line.long 0x00 "DMAC_DESCR6_PING_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0x8C0+0x08)++0x03 line.long 0x00 "DMAC_DESCR6_PING_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0x8C0+0x0C)++0x0B line.long 0x00 "DMAC_DESCR6_PING_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" line.long 0x04 "DMAC_DESCR6_PONG_SRC,Pong Source Address" line.long 0x08 "DMAC_DESCR6_PONG_DST,Pong Destination Address" if (((per.l(ad:0x40101000+0x1C+0x8C0))&0x80000000)==0x80000000) group.long (0x8C0+0x18)++0x03 line.long 0x00 "DMAC_DESCR6_PONG_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0x8C0+0x18)++0x03 line.long 0x00 "DMAC_DESCR6_PONG_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0x8C0+0x1C)++0x03 line.long 0x00 "DMAC_DESCR6_PONG_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" group.long 0x8E0++0x07 line.long 0x00 "DMAC_DESCR7_PING_SRC,Ping Source Address" line.long 0x04 "DMAC_DESCR7_PING_DST,Ping Destination Address" if (((per.l(ad:0x40101000+0x0C+0x8E0))&0x80000000)==0x80000000) group.long (0x8E0+0x08)++0x03 line.long 0x00 "DMAC_DESCR7_PING_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0x8E0+0x08)++0x03 line.long 0x00 "DMAC_DESCR7_PING_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0x8E0+0x0C)++0x0B line.long 0x00 "DMAC_DESCR7_PING_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" line.long 0x04 "DMAC_DESCR7_PONG_SRC,Pong Source Address" line.long 0x08 "DMAC_DESCR7_PONG_DST,Pong Destination Address" if (((per.l(ad:0x40101000+0x1C+0x8E0))&0x80000000)==0x80000000) group.long (0x8E0+0x18)++0x03 line.long 0x00 "DMAC_DESCR7_PONG_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0x8E0+0x18)++0x03 line.long 0x00 "DMAC_DESCR7_PONG_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0x8E0+0x1C)++0x03 line.long 0x00 "DMAC_DESCR7_PONG_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" group.long 0x900++0x07 line.long 0x00 "DMAC_DESCR8_PING_SRC,Ping Source Address" line.long 0x04 "DMAC_DESCR8_PING_DST,Ping Destination Address" if (((per.l(ad:0x40101000+0x0C+0x900))&0x80000000)==0x80000000) group.long (0x900+0x08)++0x03 line.long 0x00 "DMAC_DESCR8_PING_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0x900+0x08)++0x03 line.long 0x00 "DMAC_DESCR8_PING_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0x900+0x0C)++0x0B line.long 0x00 "DMAC_DESCR8_PING_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" line.long 0x04 "DMAC_DESCR8_PONG_SRC,Pong Source Address" line.long 0x08 "DMAC_DESCR8_PONG_DST,Pong Destination Address" if (((per.l(ad:0x40101000+0x1C+0x900))&0x80000000)==0x80000000) group.long (0x900+0x18)++0x03 line.long 0x00 "DMAC_DESCR8_PONG_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0x900+0x18)++0x03 line.long 0x00 "DMAC_DESCR8_PONG_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0x900+0x1C)++0x03 line.long 0x00 "DMAC_DESCR8_PONG_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" group.long 0x920++0x07 line.long 0x00 "DMAC_DESCR9_PING_SRC,Ping Source Address" line.long 0x04 "DMAC_DESCR9_PING_DST,Ping Destination Address" if (((per.l(ad:0x40101000+0x0C+0x920))&0x80000000)==0x80000000) group.long (0x920+0x08)++0x03 line.long 0x00 "DMAC_DESCR9_PING_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0x920+0x08)++0x03 line.long 0x00 "DMAC_DESCR9_PING_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0x920+0x0C)++0x0B line.long 0x00 "DMAC_DESCR9_PING_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" line.long 0x04 "DMAC_DESCR9_PONG_SRC,Pong Source Address" line.long 0x08 "DMAC_DESCR9_PONG_DST,Pong Destination Address" if (((per.l(ad:0x40101000+0x1C+0x920))&0x80000000)==0x80000000) group.long (0x920+0x18)++0x03 line.long 0x00 "DMAC_DESCR9_PONG_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0x920+0x18)++0x03 line.long 0x00 "DMAC_DESCR9_PONG_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0x920+0x1C)++0x03 line.long 0x00 "DMAC_DESCR9_PONG_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" group.long 0x940++0x07 line.long 0x00 "DMAC_DESCR10_PING_SRC,Ping Source Address" line.long 0x04 "DMAC_DESCR10_PING_DST,Ping Destination Address" if (((per.l(ad:0x40101000+0x0C+0x940))&0x80000000)==0x80000000) group.long (0x940+0x08)++0x03 line.long 0x00 "DMAC_DESCR10_PING_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0x940+0x08)++0x03 line.long 0x00 "DMAC_DESCR10_PING_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0x940+0x0C)++0x0B line.long 0x00 "DMAC_DESCR10_PING_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" line.long 0x04 "DMAC_DESCR10_PONG_SRC,Pong Source Address" line.long 0x08 "DMAC_DESCR10_PONG_DST,Pong Destination Address" if (((per.l(ad:0x40101000+0x1C+0x940))&0x80000000)==0x80000000) group.long (0x940+0x18)++0x03 line.long 0x00 "DMAC_DESCR10_PONG_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0x940+0x18)++0x03 line.long 0x00 "DMAC_DESCR10_PONG_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0x940+0x1C)++0x03 line.long 0x00 "DMAC_DESCR10_PONG_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" group.long 0x960++0x07 line.long 0x00 "DMAC_DESCR11_PING_SRC,Ping Source Address" line.long 0x04 "DMAC_DESCR11_PING_DST,Ping Destination Address" if (((per.l(ad:0x40101000+0x0C+0x960))&0x80000000)==0x80000000) group.long (0x960+0x08)++0x03 line.long 0x00 "DMAC_DESCR11_PING_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0x960+0x08)++0x03 line.long 0x00 "DMAC_DESCR11_PING_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0x960+0x0C)++0x0B line.long 0x00 "DMAC_DESCR11_PING_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" line.long 0x04 "DMAC_DESCR11_PONG_SRC,Pong Source Address" line.long 0x08 "DMAC_DESCR11_PONG_DST,Pong Destination Address" if (((per.l(ad:0x40101000+0x1C+0x960))&0x80000000)==0x80000000) group.long (0x960+0x18)++0x03 line.long 0x00 "DMAC_DESCR11_PONG_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0x960+0x18)++0x03 line.long 0x00 "DMAC_DESCR11_PONG_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0x960+0x1C)++0x03 line.long 0x00 "DMAC_DESCR11_PONG_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" group.long 0x980++0x07 line.long 0x00 "DMAC_DESCR12_PING_SRC,Ping Source Address" line.long 0x04 "DMAC_DESCR12_PING_DST,Ping Destination Address" if (((per.l(ad:0x40101000+0x0C+0x980))&0x80000000)==0x80000000) group.long (0x980+0x08)++0x03 line.long 0x00 "DMAC_DESCR12_PING_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0x980+0x08)++0x03 line.long 0x00 "DMAC_DESCR12_PING_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0x980+0x0C)++0x0B line.long 0x00 "DMAC_DESCR12_PING_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" line.long 0x04 "DMAC_DESCR12_PONG_SRC,Pong Source Address" line.long 0x08 "DMAC_DESCR12_PONG_DST,Pong Destination Address" if (((per.l(ad:0x40101000+0x1C+0x980))&0x80000000)==0x80000000) group.long (0x980+0x18)++0x03 line.long 0x00 "DMAC_DESCR12_PONG_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0x980+0x18)++0x03 line.long 0x00 "DMAC_DESCR12_PONG_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0x980+0x1C)++0x03 line.long 0x00 "DMAC_DESCR12_PONG_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" group.long 0x9A0++0x07 line.long 0x00 "DMAC_DESCR13_PING_SRC,Ping Source Address" line.long 0x04 "DMAC_DESCR13_PING_DST,Ping Destination Address" if (((per.l(ad:0x40101000+0x0C+0x9A0))&0x80000000)==0x80000000) group.long (0x9A0+0x08)++0x03 line.long 0x00 "DMAC_DESCR13_PING_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0x9A0+0x08)++0x03 line.long 0x00 "DMAC_DESCR13_PING_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0x9A0+0x0C)++0x0B line.long 0x00 "DMAC_DESCR13_PING_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" line.long 0x04 "DMAC_DESCR13_PONG_SRC,Pong Source Address" line.long 0x08 "DMAC_DESCR13_PONG_DST,Pong Destination Address" if (((per.l(ad:0x40101000+0x1C+0x9A0))&0x80000000)==0x80000000) group.long (0x9A0+0x18)++0x03 line.long 0x00 "DMAC_DESCR13_PONG_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0x9A0+0x18)++0x03 line.long 0x00 "DMAC_DESCR13_PONG_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0x9A0+0x1C)++0x03 line.long 0x00 "DMAC_DESCR13_PONG_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" group.long 0x9C0++0x07 line.long 0x00 "DMAC_DESCR14_PING_SRC,Ping Source Address" line.long 0x04 "DMAC_DESCR14_PING_DST,Ping Destination Address" if (((per.l(ad:0x40101000+0x0C+0x9C0))&0x80000000)==0x80000000) group.long (0x9C0+0x08)++0x03 line.long 0x00 "DMAC_DESCR14_PING_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0x9C0+0x08)++0x03 line.long 0x00 "DMAC_DESCR14_PING_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0x9C0+0x0C)++0x0B line.long 0x00 "DMAC_DESCR14_PING_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" line.long 0x04 "DMAC_DESCR14_PONG_SRC,Pong Source Address" line.long 0x08 "DMAC_DESCR14_PONG_DST,Pong Destination Address" if (((per.l(ad:0x40101000+0x1C+0x9C0))&0x80000000)==0x80000000) group.long (0x9C0+0x18)++0x03 line.long 0x00 "DMAC_DESCR14_PONG_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0x9C0+0x18)++0x03 line.long 0x00 "DMAC_DESCR14_PONG_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0x9C0+0x1C)++0x03 line.long 0x00 "DMAC_DESCR14_PONG_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" group.long 0x9E0++0x07 line.long 0x00 "DMAC_DESCR15_PING_SRC,Ping Source Address" line.long 0x04 "DMAC_DESCR15_PING_DST,Ping Destination Address" if (((per.l(ad:0x40101000+0x0C+0x9E0))&0x80000000)==0x80000000) group.long (0x9E0+0x08)++0x03 line.long 0x00 "DMAC_DESCR15_PING_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0x9E0+0x08)++0x03 line.long 0x00 "DMAC_DESCR15_PING_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0x9E0+0x0C)++0x0B line.long 0x00 "DMAC_DESCR15_PING_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" line.long 0x04 "DMAC_DESCR15_PONG_SRC,Pong Source Address" line.long 0x08 "DMAC_DESCR15_PONG_DST,Pong Destination Address" if (((per.l(ad:0x40101000+0x1C+0x9E0))&0x80000000)==0x80000000) group.long (0x9E0+0x18)++0x03 line.long 0x00 "DMAC_DESCR15_PONG_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0x9E0+0x18)++0x03 line.long 0x00 "DMAC_DESCR15_PONG_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0x9E0+0x1C)++0x03 line.long 0x00 "DMAC_DESCR15_PONG_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" group.long 0xA00++0x07 line.long 0x00 "DMAC_DESCR16_PING_SRC,Ping Source Address" line.long 0x04 "DMAC_DESCR16_PING_DST,Ping Destination Address" if (((per.l(ad:0x40101000+0x0C+0xA00))&0x80000000)==0x80000000) group.long (0xA00+0x08)++0x03 line.long 0x00 "DMAC_DESCR16_PING_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0xA00+0x08)++0x03 line.long 0x00 "DMAC_DESCR16_PING_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0xA00+0x0C)++0x0B line.long 0x00 "DMAC_DESCR16_PING_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" line.long 0x04 "DMAC_DESCR16_PONG_SRC,Pong Source Address" line.long 0x08 "DMAC_DESCR16_PONG_DST,Pong Destination Address" if (((per.l(ad:0x40101000+0x1C+0xA00))&0x80000000)==0x80000000) group.long (0xA00+0x18)++0x03 line.long 0x00 "DMAC_DESCR16_PONG_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0xA00+0x18)++0x03 line.long 0x00 "DMAC_DESCR16_PONG_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0xA00+0x1C)++0x03 line.long 0x00 "DMAC_DESCR16_PONG_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" group.long 0xA20++0x07 line.long 0x00 "DMAC_DESCR17_PING_SRC,Ping Source Address" line.long 0x04 "DMAC_DESCR17_PING_DST,Ping Destination Address" if (((per.l(ad:0x40101000+0x0C+0xA20))&0x80000000)==0x80000000) group.long (0xA20+0x08)++0x03 line.long 0x00 "DMAC_DESCR17_PING_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0xA20+0x08)++0x03 line.long 0x00 "DMAC_DESCR17_PING_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0xA20+0x0C)++0x0B line.long 0x00 "DMAC_DESCR17_PING_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" line.long 0x04 "DMAC_DESCR17_PONG_SRC,Pong Source Address" line.long 0x08 "DMAC_DESCR17_PONG_DST,Pong Destination Address" if (((per.l(ad:0x40101000+0x1C+0xA20))&0x80000000)==0x80000000) group.long (0xA20+0x18)++0x03 line.long 0x00 "DMAC_DESCR17_PONG_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0xA20+0x18)++0x03 line.long 0x00 "DMAC_DESCR17_PONG_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0xA20+0x1C)++0x03 line.long 0x00 "DMAC_DESCR17_PONG_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" group.long 0xA40++0x07 line.long 0x00 "DMAC_DESCR18_PING_SRC,Ping Source Address" line.long 0x04 "DMAC_DESCR18_PING_DST,Ping Destination Address" if (((per.l(ad:0x40101000+0x0C+0xA40))&0x80000000)==0x80000000) group.long (0xA40+0x08)++0x03 line.long 0x00 "DMAC_DESCR18_PING_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0xA40+0x08)++0x03 line.long 0x00 "DMAC_DESCR18_PING_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0xA40+0x0C)++0x0B line.long 0x00 "DMAC_DESCR18_PING_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" line.long 0x04 "DMAC_DESCR18_PONG_SRC,Pong Source Address" line.long 0x08 "DMAC_DESCR18_PONG_DST,Pong Destination Address" if (((per.l(ad:0x40101000+0x1C+0xA40))&0x80000000)==0x80000000) group.long (0xA40+0x18)++0x03 line.long 0x00 "DMAC_DESCR18_PONG_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0xA40+0x18)++0x03 line.long 0x00 "DMAC_DESCR18_PONG_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0xA40+0x1C)++0x03 line.long 0x00 "DMAC_DESCR18_PONG_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" group.long 0xA60++0x07 line.long 0x00 "DMAC_DESCR19_PING_SRC,Ping Source Address" line.long 0x04 "DMAC_DESCR19_PING_DST,Ping Destination Address" if (((per.l(ad:0x40101000+0x0C+0xA60))&0x80000000)==0x80000000) group.long (0xA60+0x08)++0x03 line.long 0x00 "DMAC_DESCR19_PING_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0xA60+0x08)++0x03 line.long 0x00 "DMAC_DESCR19_PING_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0xA60+0x0C)++0x0B line.long 0x00 "DMAC_DESCR19_PING_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" line.long 0x04 "DMAC_DESCR19_PONG_SRC,Pong Source Address" line.long 0x08 "DMAC_DESCR19_PONG_DST,Pong Destination Address" if (((per.l(ad:0x40101000+0x1C+0xA60))&0x80000000)==0x80000000) group.long (0xA60+0x18)++0x03 line.long 0x00 "DMAC_DESCR19_PONG_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0xA60+0x18)++0x03 line.long 0x00 "DMAC_DESCR19_PONG_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0xA60+0x1C)++0x03 line.long 0x00 "DMAC_DESCR19_PONG_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" group.long 0xA80++0x07 line.long 0x00 "DMAC_DESCR20_PING_SRC,Ping Source Address" line.long 0x04 "DMAC_DESCR20_PING_DST,Ping Destination Address" if (((per.l(ad:0x40101000+0x0C+0xA80))&0x80000000)==0x80000000) group.long (0xA80+0x08)++0x03 line.long 0x00 "DMAC_DESCR20_PING_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0xA80+0x08)++0x03 line.long 0x00 "DMAC_DESCR20_PING_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0xA80+0x0C)++0x0B line.long 0x00 "DMAC_DESCR20_PING_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" line.long 0x04 "DMAC_DESCR20_PONG_SRC,Pong Source Address" line.long 0x08 "DMAC_DESCR20_PONG_DST,Pong Destination Address" if (((per.l(ad:0x40101000+0x1C+0xA80))&0x80000000)==0x80000000) group.long (0xA80+0x18)++0x03 line.long 0x00 "DMAC_DESCR20_PONG_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0xA80+0x18)++0x03 line.long 0x00 "DMAC_DESCR20_PONG_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0xA80+0x1C)++0x03 line.long 0x00 "DMAC_DESCR20_PONG_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" group.long 0xAA0++0x07 line.long 0x00 "DMAC_DESCR21_PING_SRC,Ping Source Address" line.long 0x04 "DMAC_DESCR21_PING_DST,Ping Destination Address" if (((per.l(ad:0x40101000+0x0C+0xAA0))&0x80000000)==0x80000000) group.long (0xAA0+0x08)++0x03 line.long 0x00 "DMAC_DESCR21_PING_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0xAA0+0x08)++0x03 line.long 0x00 "DMAC_DESCR21_PING_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0xAA0+0x0C)++0x0B line.long 0x00 "DMAC_DESCR21_PING_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" line.long 0x04 "DMAC_DESCR21_PONG_SRC,Pong Source Address" line.long 0x08 "DMAC_DESCR21_PONG_DST,Pong Destination Address" if (((per.l(ad:0x40101000+0x1C+0xAA0))&0x80000000)==0x80000000) group.long (0xAA0+0x18)++0x03 line.long 0x00 "DMAC_DESCR21_PONG_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0xAA0+0x18)++0x03 line.long 0x00 "DMAC_DESCR21_PONG_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0xAA0+0x1C)++0x03 line.long 0x00 "DMAC_DESCR21_PONG_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" group.long 0xAC0++0x07 line.long 0x00 "DMAC_DESCR22_PING_SRC,Ping Source Address" line.long 0x04 "DMAC_DESCR22_PING_DST,Ping Destination Address" if (((per.l(ad:0x40101000+0x0C+0xAC0))&0x80000000)==0x80000000) group.long (0xAC0+0x08)++0x03 line.long 0x00 "DMAC_DESCR22_PING_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0xAC0+0x08)++0x03 line.long 0x00 "DMAC_DESCR22_PING_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0xAC0+0x0C)++0x0B line.long 0x00 "DMAC_DESCR22_PING_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" line.long 0x04 "DMAC_DESCR22_PONG_SRC,Pong Source Address" line.long 0x08 "DMAC_DESCR22_PONG_DST,Pong Destination Address" if (((per.l(ad:0x40101000+0x1C+0xAC0))&0x80000000)==0x80000000) group.long (0xAC0+0x18)++0x03 line.long 0x00 "DMAC_DESCR22_PONG_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0xAC0+0x18)++0x03 line.long 0x00 "DMAC_DESCR22_PONG_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0xAC0+0x1C)++0x03 line.long 0x00 "DMAC_DESCR22_PONG_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" group.long 0xAE0++0x07 line.long 0x00 "DMAC_DESCR23_PING_SRC,Ping Source Address" line.long 0x04 "DMAC_DESCR23_PING_DST,Ping Destination Address" if (((per.l(ad:0x40101000+0x0C+0xAE0))&0x80000000)==0x80000000) group.long (0xAE0+0x08)++0x03 line.long 0x00 "DMAC_DESCR23_PING_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0xAE0+0x08)++0x03 line.long 0x00 "DMAC_DESCR23_PING_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0xAE0+0x0C)++0x0B line.long 0x00 "DMAC_DESCR23_PING_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" line.long 0x04 "DMAC_DESCR23_PONG_SRC,Pong Source Address" line.long 0x08 "DMAC_DESCR23_PONG_DST,Pong Destination Address" if (((per.l(ad:0x40101000+0x1C+0xAE0))&0x80000000)==0x80000000) group.long (0xAE0+0x18)++0x03 line.long 0x00 "DMAC_DESCR23_PONG_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0xAE0+0x18)++0x03 line.long 0x00 "DMAC_DESCR23_PONG_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0xAE0+0x1C)++0x03 line.long 0x00 "DMAC_DESCR23_PONG_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" group.long 0xB00++0x07 line.long 0x00 "DMAC_DESCR24_PING_SRC,Ping Source Address" line.long 0x04 "DMAC_DESCR24_PING_DST,Ping Destination Address" if (((per.l(ad:0x40101000+0x0C+0xB00))&0x80000000)==0x80000000) group.long (0xB00+0x08)++0x03 line.long 0x00 "DMAC_DESCR24_PING_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0xB00+0x08)++0x03 line.long 0x00 "DMAC_DESCR24_PING_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0xB00+0x0C)++0x0B line.long 0x00 "DMAC_DESCR24_PING_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" line.long 0x04 "DMAC_DESCR24_PONG_SRC,Pong Source Address" line.long 0x08 "DMAC_DESCR24_PONG_DST,Pong Destination Address" if (((per.l(ad:0x40101000+0x1C+0xB00))&0x80000000)==0x80000000) group.long (0xB00+0x18)++0x03 line.long 0x00 "DMAC_DESCR24_PONG_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0xB00+0x18)++0x03 line.long 0x00 "DMAC_DESCR24_PONG_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0xB00+0x1C)++0x03 line.long 0x00 "DMAC_DESCR24_PONG_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" group.long 0xB20++0x07 line.long 0x00 "DMAC_DESCR25_PING_SRC,Ping Source Address" line.long 0x04 "DMAC_DESCR25_PING_DST,Ping Destination Address" if (((per.l(ad:0x40101000+0x0C+0xB20))&0x80000000)==0x80000000) group.long (0xB20+0x08)++0x03 line.long 0x00 "DMAC_DESCR25_PING_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0xB20+0x08)++0x03 line.long 0x00 "DMAC_DESCR25_PING_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0xB20+0x0C)++0x0B line.long 0x00 "DMAC_DESCR25_PING_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" line.long 0x04 "DMAC_DESCR25_PONG_SRC,Pong Source Address" line.long 0x08 "DMAC_DESCR25_PONG_DST,Pong Destination Address" if (((per.l(ad:0x40101000+0x1C+0xB20))&0x80000000)==0x80000000) group.long (0xB20+0x18)++0x03 line.long 0x00 "DMAC_DESCR25_PONG_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0xB20+0x18)++0x03 line.long 0x00 "DMAC_DESCR25_PONG_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0xB20+0x1C)++0x03 line.long 0x00 "DMAC_DESCR25_PONG_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" group.long 0xB40++0x07 line.long 0x00 "DMAC_DESCR26_PING_SRC,Ping Source Address" line.long 0x04 "DMAC_DESCR26_PING_DST,Ping Destination Address" if (((per.l(ad:0x40101000+0x0C+0xB40))&0x80000000)==0x80000000) group.long (0xB40+0x08)++0x03 line.long 0x00 "DMAC_DESCR26_PING_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0xB40+0x08)++0x03 line.long 0x00 "DMAC_DESCR26_PING_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0xB40+0x0C)++0x0B line.long 0x00 "DMAC_DESCR26_PING_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" line.long 0x04 "DMAC_DESCR26_PONG_SRC,Pong Source Address" line.long 0x08 "DMAC_DESCR26_PONG_DST,Pong Destination Address" if (((per.l(ad:0x40101000+0x1C+0xB40))&0x80000000)==0x80000000) group.long (0xB40+0x18)++0x03 line.long 0x00 "DMAC_DESCR26_PONG_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0xB40+0x18)++0x03 line.long 0x00 "DMAC_DESCR26_PONG_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0xB40+0x1C)++0x03 line.long 0x00 "DMAC_DESCR26_PONG_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" group.long 0xB60++0x07 line.long 0x00 "DMAC_DESCR27_PING_SRC,Ping Source Address" line.long 0x04 "DMAC_DESCR27_PING_DST,Ping Destination Address" if (((per.l(ad:0x40101000+0x0C+0xB60))&0x80000000)==0x80000000) group.long (0xB60+0x08)++0x03 line.long 0x00 "DMAC_DESCR27_PING_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0xB60+0x08)++0x03 line.long 0x00 "DMAC_DESCR27_PING_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0xB60+0x0C)++0x0B line.long 0x00 "DMAC_DESCR27_PING_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" line.long 0x04 "DMAC_DESCR27_PONG_SRC,Pong Source Address" line.long 0x08 "DMAC_DESCR27_PONG_DST,Pong Destination Address" if (((per.l(ad:0x40101000+0x1C+0xB60))&0x80000000)==0x80000000) group.long (0xB60+0x18)++0x03 line.long 0x00 "DMAC_DESCR27_PONG_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0xB60+0x18)++0x03 line.long 0x00 "DMAC_DESCR27_PONG_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0xB60+0x1C)++0x03 line.long 0x00 "DMAC_DESCR27_PONG_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" group.long 0xB80++0x07 line.long 0x00 "DMAC_DESCR28_PING_SRC,Ping Source Address" line.long 0x04 "DMAC_DESCR28_PING_DST,Ping Destination Address" if (((per.l(ad:0x40101000+0x0C+0xB80))&0x80000000)==0x80000000) group.long (0xB80+0x08)++0x03 line.long 0x00 "DMAC_DESCR28_PING_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0xB80+0x08)++0x03 line.long 0x00 "DMAC_DESCR28_PING_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0xB80+0x0C)++0x0B line.long 0x00 "DMAC_DESCR28_PING_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" line.long 0x04 "DMAC_DESCR28_PONG_SRC,Pong Source Address" line.long 0x08 "DMAC_DESCR28_PONG_DST,Pong Destination Address" if (((per.l(ad:0x40101000+0x1C+0xB80))&0x80000000)==0x80000000) group.long (0xB80+0x18)++0x03 line.long 0x00 "DMAC_DESCR28_PONG_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0xB80+0x18)++0x03 line.long 0x00 "DMAC_DESCR28_PONG_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0xB80+0x1C)++0x03 line.long 0x00 "DMAC_DESCR28_PONG_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" group.long 0xBA0++0x07 line.long 0x00 "DMAC_DESCR29_PING_SRC,Ping Source Address" line.long 0x04 "DMAC_DESCR29_PING_DST,Ping Destination Address" if (((per.l(ad:0x40101000+0x0C+0xBA0))&0x80000000)==0x80000000) group.long (0xBA0+0x08)++0x03 line.long 0x00 "DMAC_DESCR29_PING_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0xBA0+0x08)++0x03 line.long 0x00 "DMAC_DESCR29_PING_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0xBA0+0x0C)++0x0B line.long 0x00 "DMAC_DESCR29_PING_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" line.long 0x04 "DMAC_DESCR29_PONG_SRC,Pong Source Address" line.long 0x08 "DMAC_DESCR29_PONG_DST,Pong Destination Address" if (((per.l(ad:0x40101000+0x1C+0xBA0))&0x80000000)==0x80000000) group.long (0xBA0+0x18)++0x03 line.long 0x00 "DMAC_DESCR29_PONG_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0xBA0+0x18)++0x03 line.long 0x00 "DMAC_DESCR29_PONG_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0xBA0+0x1C)++0x03 line.long 0x00 "DMAC_DESCR29_PONG_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" group.long 0xBC0++0x07 line.long 0x00 "DMAC_DESCR30_PING_SRC,Ping Source Address" line.long 0x04 "DMAC_DESCR30_PING_DST,Ping Destination Address" if (((per.l(ad:0x40101000+0x0C+0xBC0))&0x80000000)==0x80000000) group.long (0xBC0+0x08)++0x03 line.long 0x00 "DMAC_DESCR30_PING_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0xBC0+0x08)++0x03 line.long 0x00 "DMAC_DESCR30_PING_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0xBC0+0x0C)++0x0B line.long 0x00 "DMAC_DESCR30_PING_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" line.long 0x04 "DMAC_DESCR30_PONG_SRC,Pong Source Address" line.long 0x08 "DMAC_DESCR30_PONG_DST,Pong Destination Address" if (((per.l(ad:0x40101000+0x1C+0xBC0))&0x80000000)==0x80000000) group.long (0xBC0+0x18)++0x03 line.long 0x00 "DMAC_DESCR30_PONG_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0xBC0+0x18)++0x03 line.long 0x00 "DMAC_DESCR30_PONG_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0xBC0+0x1C)++0x03 line.long 0x00 "DMAC_DESCR30_PONG_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" group.long 0xBE0++0x07 line.long 0x00 "DMAC_DESCR31_PING_SRC,Ping Source Address" line.long 0x04 "DMAC_DESCR31_PING_DST,Ping Destination Address" if (((per.l(ad:0x40101000+0x0C+0xBE0))&0x80000000)==0x80000000) group.long (0xBE0+0x08)++0x03 line.long 0x00 "DMAC_DESCR31_PING_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0xBE0+0x08)++0x03 line.long 0x00 "DMAC_DESCR31_PING_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by DATA_SIZE,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0xBE0+0x0C)++0x0B line.long 0x00 "DMAC_DESCR31_PING_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" line.long 0x04 "DMAC_DESCR31_PONG_SRC,Pong Source Address" line.long 0x08 "DMAC_DESCR31_PONG_DST,Pong Destination Address" if (((per.l(ad:0x40101000+0x1C+0xBE0))&0x80000000)==0x80000000) group.long (0xBE0+0x18)++0x03 line.long 0x00 "DMAC_DESCR31_PONG_CTL,Ping Control Word" bitfld.long 0x00 30.--31. " OPCODE ,Specific data transfer" "Single data element,Single descriptor,Descriptor list,?..." bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" textline " " bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" textline " " bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" else group.long (0xBE0+0x18)++0x03 line.long 0x00 "DMAC_DESCR31_PONG_CTL,Ping Control Word" bitfld.long 0x00 29. " FLIPPING ,Current descriptor identifier flipping" "Not flipped,Flipped" bitfld.long 0x00 28. " PREEMPTABLE ,Transfer preemptable" "No,Yes" bitfld.long 0x00 27. " SET_CAUSE ,Setting Interrupt Cause" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " INV_DESCR ,Invalidate Descriptor" "Not invalidated,Invalidated" bitfld.long 0x00 24.--25. " WAIT_FOR_DEACT ,Data transfer engine wait for deactivation" "Not wait,Up to 4 cycles,Up to 8 cycles,Indefinitely" bitfld.long 0x00 23. " SRC_ADDR_INCR ,Destination location address increment" "No increment,Increment" textline " " bitfld.long 0x00 22. " SRC_TRANSFER_SIZE ,Bus transfer size to the source location" "Specified by DATA_SIZE,32 bits" bitfld.long 0x00 21. " DST_ADDR_INCR ,Destination location address increment" "No increment,Increment" bitfld.long 0x00 20. " DST_TRANSFER_SIZE ,Bus transfer size to the destination location" "Specified by data size,32 bits" textline " " bitfld.long 0x00 16.--17. " DATA_SIZE ,Data element size" "8 bits,16 bits,32 bits,?..." hexmask.long.word 0x00 0.--15. 1. " DATA_NR ,Number of data elements that are transferred by a single descriptor" endif group.long (0xBE0+0x1C)++0x03 line.long 0x00 "DMAC_DESCR31_PONG_STATUS,Ping Status Word" bitfld.long 0x00 31. " VALID ,Data transfer valid" "Invalid,Valid" bitfld.long 0x00 16.--18. " RESPONSE ,Response code" "NO_ERROR,DONE,SRC_BUS_ERROR,DST_BUS_ERROR,SRC_MISAL,DST_MISAL,INVALID_DESCR,?..." hexmask.long.word 0x00 0.--15. 1. " CURR_DATA_NR ,Current data transfer index" tree.end width 0x0B tree.end tree "GPIO" base ad:0x40041000 width 12. rgroup.long 0x1000++0x03 line.long 0x00 "INTR_CAUSE,Interrupt Port Cause Register" bitfld.long 0x00 13. " PORT_INT[13] ,Port 13 interrupt cause" "Not caused,Caused" bitfld.long 0x00 12. " PORT_INT[12] ,Port 12 interrupt cause" "Not caused,Caused" bitfld.long 0x00 11. " PORT_INT[11] ,Port 11 interrupt cause" "Not caused,Caused" bitfld.long 0x00 10. " PORT_INT[10] ,Port 10 interrupt cause" "Not caused,Caused" textline " " bitfld.long 0x00 9. " PORT_INT[9] ,Port 9 interrupt cause" "Not caused,Caused" bitfld.long 0x00 8. " PORT_INT[8] ,Port 8 interrupt cause" "Not caused,Caused" bitfld.long 0x00 7. " PORT_INT[7] ,Port 7 interrupt cause" "Not caused,Caused" bitfld.long 0x00 6. " PORT_INT[6] ,Port 6 interrupt cause" "Not caused,Caused" textline " " bitfld.long 0x00 5. " PORT_INT[5] ,Port 5 interrupt cause" "Not caused,Caused" bitfld.long 0x00 4. " PORT_INT[4] ,Port 4 interrupt cause" "Not caused,Caused" bitfld.long 0x00 3. " PORT_INT[3] ,Port 3 interrupt cause" "Not caused,Caused" bitfld.long 0x00 2. " PORT_INT[2] ,Port 2 interrupt cause" "Not caused,Caused" textline " " bitfld.long 0x00 1. " PORT_INT[1] ,Port 1 interrupt cause" "Not caused,Caused" bitfld.long 0x00 0. " PORT_INT[0] ,Port 0 interrupt cause" "Not caused,Caused" width 0x0B tree "PORT 0" base ad:0x40040000 width 23. group.long 0x00++0x03 line.long 0x00 "GPIO_PRT0_DR,Port 0 Output Data Register" bitfld.long 0x00 7. " DATA7 ,Pin 7 output data" "Low,High" bitfld.long 0x00 6. " DATA6 ,Pin 6 output data" "Low,High" bitfld.long 0x00 5. " DATA5 ,Pin 5 output data" "Low,High" bitfld.long 0x00 4. " DATA4 ,Pin 4 output data" "Low,High" textline " " bitfld.long 0x00 3. " DATA3 ,Pin 3 output data" "Low,High" bitfld.long 0x00 2. " DATA2 ,Pin 2 output data" "Low,High" bitfld.long 0x00 1. " DATA1 ,Pin 1 output data" "Low,High" bitfld.long 0x00 0. " DATA0 ,Pin 0 output data" "Low,High" rgroup.long 0x04++0x03 line.long 0x00 "GPIO_PRT0_PS,Port 0 IO Pad State Register" bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High" bitfld.long 0x00 7. " DATA7 ,Pin 7 state" "Low,High" bitfld.long 0x00 6. " DATA6 ,Pin 6 state" "Low,High" bitfld.long 0x00 5. " DATA5 ,Pin 5 state" "Low,High" textline " " bitfld.long 0x00 4. " DATA4 ,Pin 4 state" "Low,High" bitfld.long 0x00 3. " DATA3 ,Pin 3 state" "Low,High" bitfld.long 0x00 2. " DATA2 ,Pin 2 state" "Low,High" bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High" textline " " bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High" if (((per.l(ad:0x40040000+0x08))&0x1000000)==0x00) group.long 0x08++0x03 line.long 0x00 "GPIO_PRT0_PC,Port 0 Configuration Register" bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Port 0 input buffer mode select" "CMOS,VCCHIB,CMOS,VCCHIB" bitfld.long 0x00 25. " PORT_SLOW ,Output edge rate of all pins" "Fast,Slow" bitfld.long 0x00 24. " PORT_VTRIP_SEL ,Input buffer function select" "CMOS,LVTTL" bitfld.long 0x00 21.--23. " DM7 ,Pin 7 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 18.--20. " DM6 ,Pin 6 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 15.--17. " DM5 ,Pin 5 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 12.--14. " DM4 ,Pin 4 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 9.--11. " DM3 ,Pin 3 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 6.--8. " DM2 ,Pin 2 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 3.--5. " DM1 ,Pin 1 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 0.--2. " DM0 ,Pin 0 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" else group.long 0x08++0x03 line.long 0x00 "GPIO_PRT0_PC,Port 0 Configuration Register" bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Port 0 input buffer mode select" "LVTTL,VCCHIB,LVTTL,VCCHIB" bitfld.long 0x00 25. " PORT_SLOW ,Output edge rate of all pins" "Fast,Slow" bitfld.long 0x00 24. " PORT_VTRIP_SEL ,Input buffer function select" "CMOS,LVTTL" bitfld.long 0x00 21.--23. " DM7 ,Pin 7 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 18.--20. " DM6 ,Pin 6 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 15.--17. " DM5 ,Pin 5 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 12.--14. " DM4 ,Pin 4 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 9.--11. " DM3 ,Pin 3 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 6.--8. " DM2 ,Pin 2 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 3.--5. " DM1 ,Pin 1 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 0.--2. " DM0 ,Pin 0 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" endif group.long 0x0C++0x07 line.long 0x00 "GPIO_PRT0_INTR_CFG,Port 0 Interrupt Configuration Register" bitfld.long 0x00 18.--20. " FLT_SEL ,Glitch filter input selection" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " FLT_EDGE_SEL ,Glitch filter input edge selection" "Disabled,Rising,Falling,Both" bitfld.long 0x00 14.--15. " EDGE7_SEL ,Pin 7 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 12.--13. " EDGE6_SEL ,Pin 6 IRQ trigger edge select" "Disabled,Rising,Falling,Both" textline " " bitfld.long 0x00 10.--11. " EDGE5_SEL ,Pin 5 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 8.--9. " EDGE4_SEL ,Pin 4 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 6.--7. " EDGE3_SEL ,Pin 3 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 4.--5. " EDGE2_SEL ,Pin 2 IRQ trigger edge select" "Disabled,Rising,Falling,Both" textline " " bitfld.long 0x00 2.--3. " EDGE1_SEL ,Pin 1 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 0.--1. " EDGE0_SEL ,Pin 0 IRQ trigger edge select" "Disabled,Rising,Falling,Both" line.long 0x04 "GPIO_PRT0_INTR,Port 0 Interrupt Status Register" rbitfld.long 0x04 24. " PS_FLT_DATA ,Logical state of the filtered pin" "Low,High" rbitfld.long 0x04 23. " PS_DATA7 ,Pin 7 state" "Low,High" rbitfld.long 0x04 22. " PS_DATA6 ,Pin 6 state" "Low,High" rbitfld.long 0x04 21. " PS_DATA5 ,Pin 5 state" "Low,High" textline " " rbitfld.long 0x04 20. " PS_DATA4 ,Pin 4 state" "Low,High" rbitfld.long 0x04 19. " PS_DATA3 ,Pin 3 state" "Low,High" rbitfld.long 0x04 18. " PS_DATA2 ,Pin 2 state" "Low,High" rbitfld.long 0x04 17. " PS_DATA1 ,Pin 1 state" "Low,High" textline " " rbitfld.long 0x04 16. " PS_DATA0 ,Pin 0 state" "Low,High" eventfld.long 0x04 8. " FLT_DATA ,Interrupt status of the filtered pin" "No interrupt,Interrupt" eventfld.long 0x04 7. " DATA7 ,Pin 7 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 6. " DATA6 ,Pin 6 interrupt status" "No interrupt,Interrupt" textline " " eventfld.long 0x04 5. " DATA5 ,Pin 5 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 4. " DATA4 ,Pin 4 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 3. " DATA3 ,Pin 3 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 2. " DATA2 ,Pin 2 interrupt status" "No interrupt,Interrupt" textline " " eventfld.long 0x04 1. " DATA1 ,Pin 1 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 0. " DATA0 ,Pin 0 interrupt status" "No interrupt,Interrupt" group.long 0x18++0x03 line.long 0x00 "GPIO_PRT0_PC2,Port 0 Configuration Register 2" bitfld.long 0x00 7. " INP_DIS7 ,Pin 7 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 6. " INP_DIS6 ,Pin 6 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 5. " INP_DIS5 ,Pin 5 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 4. " INP_DIS4 ,Pin 4 input buffer disable" "Enabled,Disabled" textline " " bitfld.long 0x00 3. " INP_DIS3 ,Pin 3 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 2. " INP_DIS2 ,Pin 2 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 1. " INP_DIS1 ,Pin 1 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 0. " INP_DIS0 ,Pin 0 input buffer disable" "Enabled,Disabled" group.long 0x40++0x0B line.long 0x00 "GPIO_PRT0_DR_SET,Port 0 Output Data Set Register" bitfld.long 0x00 7. " DATA_7 ,Pin 7 data output set" "No effect,1" bitfld.long 0x00 6. " DATA_6 ,Pin 6 data output set" "No effect,1" bitfld.long 0x00 5. " DATA_5 ,Pin 5 data output set" "No effect,1" bitfld.long 0x00 4. " DATA_4 ,Pin 4 data output set" "No effect,1" textline " " bitfld.long 0x00 3. " DATA_3 ,Pin 3 data output set" "No effect,1" bitfld.long 0x00 2. " DATA_2 ,Pin 2 data output set" "No effect,1" bitfld.long 0x00 1. " DATA_1 ,Pin 1 data output set" "No effect,1" bitfld.long 0x00 0. " DATA_0 ,Pin 0 data output set" "No effect,1" line.long 0x04 "GPIO_PRT0_DR_CLR,Port 0 Output Data Clear Register" bitfld.long 0x04 7. " DATA_7 ,Pin 7 data output clear" "No effect,0" bitfld.long 0x04 6. " DATA_6 ,Pin 6 data output clear" "No effect,0" bitfld.long 0x04 5. " DATA_5 ,Pin 5 data output clear" "No effect,0" bitfld.long 0x04 4. " DATA_4 ,Pin 4 data output clear" "No effect,0" textline " " bitfld.long 0x04 3. " DATA_3 ,Pin 3 data output clear" "No effect,0" bitfld.long 0x04 2. " DATA_2 ,Pin 2 data output clear" "No effect,0" bitfld.long 0x04 1. " DATA_1 ,Pin 1 data output clear" "No effect,0" bitfld.long 0x04 0. " DATA_0 ,Pin 0 data output clear" "No effect,0" line.long 0x08 "GPIO_PRT0_DR_INV,Port 0 Output Data Invert Register" bitfld.long 0x08 7. " DATA_7 ,Pin 7 data invert" "No effect,Inverted" bitfld.long 0x08 6. " DATA_6 ,Pin 6 data output invert" "No effect,Inverted" bitfld.long 0x08 5. " DATA_5 ,Pin 5 data output invert" "No effect,Inverted" bitfld.long 0x08 4. " DATA_4 ,Pin 4 data output invert" "No effect,Inverted" textline " " bitfld.long 0x08 3. " DATA_3 ,Pin 3 data output invert" "No effect,Inverted" bitfld.long 0x08 2. " DATA_2 ,Pin 2 data output invert" "No effect,Inverted" bitfld.long 0x08 1. " DATA_1 ,Pin 1 data output invert" "No effect,Inverted" bitfld.long 0x08 0. " DATA_0 ,Pin 0 data output invert" "No effect,Inverted" width 0x0B tree.end tree "PORT 1" base ad:0x40040100 width 23. group.long 0x00++0x03 line.long 0x00 "GPIO_PRT1_DR,Port 1 Output Data Register" bitfld.long 0x00 7. " DATA7 ,Pin 7 output data" "Low,High" bitfld.long 0x00 6. " DATA6 ,Pin 6 output data" "Low,High" bitfld.long 0x00 5. " DATA5 ,Pin 5 output data" "Low,High" bitfld.long 0x00 4. " DATA4 ,Pin 4 output data" "Low,High" textline " " bitfld.long 0x00 3. " DATA3 ,Pin 3 output data" "Low,High" bitfld.long 0x00 2. " DATA2 ,Pin 2 output data" "Low,High" bitfld.long 0x00 1. " DATA1 ,Pin 1 output data" "Low,High" bitfld.long 0x00 0. " DATA0 ,Pin 0 output data" "Low,High" rgroup.long 0x04++0x03 line.long 0x00 "GPIO_PRT1_PS,Port 1 IO Pad State Register" bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High" bitfld.long 0x00 7. " DATA7 ,Pin 7 state" "Low,High" bitfld.long 0x00 6. " DATA6 ,Pin 6 state" "Low,High" bitfld.long 0x00 5. " DATA5 ,Pin 5 state" "Low,High" textline " " bitfld.long 0x00 4. " DATA4 ,Pin 4 state" "Low,High" bitfld.long 0x00 3. " DATA3 ,Pin 3 state" "Low,High" bitfld.long 0x00 2. " DATA2 ,Pin 2 state" "Low,High" bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High" textline " " bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High" if (((per.l(ad:0x40040100+0x08))&0x1000000)==0x00) group.long 0x08++0x03 line.long 0x00 "GPIO_PRT1_PC,Port 1 Configuration Register" bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Port 1 input buffer mode select" "CMOS,VCCHIB,CMOS,VCCHIB" bitfld.long 0x00 25. " PORT_SLOW ,Output edge rate of all pins" "Fast,Slow" bitfld.long 0x00 24. " PORT_VTRIP_SEL ,Input buffer function select" "CMOS,LVTTL" bitfld.long 0x00 21.--23. " DM7 ,Pin 7 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 18.--20. " DM6 ,Pin 6 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 15.--17. " DM5 ,Pin 5 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 12.--14. " DM4 ,Pin 4 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 9.--11. " DM3 ,Pin 3 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 6.--8. " DM2 ,Pin 2 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 3.--5. " DM1 ,Pin 1 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 0.--2. " DM0 ,Pin 0 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" else group.long 0x08++0x03 line.long 0x00 "GPIO_PRT1_PC,Port 1 Configuration Register" bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Port 1 input buffer mode select" "LVTTL,VCCHIB,LVTTL,VCCHIB" bitfld.long 0x00 25. " PORT_SLOW ,Output edge rate of all pins" "Fast,Slow" bitfld.long 0x00 24. " PORT_VTRIP_SEL ,Input buffer function select" "CMOS,LVTTL" bitfld.long 0x00 21.--23. " DM7 ,Pin 7 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 18.--20. " DM6 ,Pin 6 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 15.--17. " DM5 ,Pin 5 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 12.--14. " DM4 ,Pin 4 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 9.--11. " DM3 ,Pin 3 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 6.--8. " DM2 ,Pin 2 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 3.--5. " DM1 ,Pin 1 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 0.--2. " DM0 ,Pin 0 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" endif group.long 0x0C++0x07 line.long 0x00 "GPIO_PRT1_INTR_CFG,Port 1 Interrupt Configuration Register" bitfld.long 0x00 18.--20. " FLT_SEL ,Glitch filter input selection" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " FLT_EDGE_SEL ,Glitch filter input edge selection" "Disabled,Rising,Falling,Both" bitfld.long 0x00 14.--15. " EDGE7_SEL ,Pin 7 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 12.--13. " EDGE6_SEL ,Pin 6 IRQ trigger edge select" "Disabled,Rising,Falling,Both" textline " " bitfld.long 0x00 10.--11. " EDGE5_SEL ,Pin 5 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 8.--9. " EDGE4_SEL ,Pin 4 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 6.--7. " EDGE3_SEL ,Pin 3 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 4.--5. " EDGE2_SEL ,Pin 2 IRQ trigger edge select" "Disabled,Rising,Falling,Both" textline " " bitfld.long 0x00 2.--3. " EDGE1_SEL ,Pin 1 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 0.--1. " EDGE0_SEL ,Pin 0 IRQ trigger edge select" "Disabled,Rising,Falling,Both" line.long 0x04 "GPIO_PRT1_INTR,Port 1 Interrupt Status Register" rbitfld.long 0x04 24. " PS_FLT_DATA ,Logical state of the filtered pin" "Low,High" rbitfld.long 0x04 23. " PS_DATA7 ,Pin 7 state" "Low,High" rbitfld.long 0x04 22. " PS_DATA6 ,Pin 6 state" "Low,High" rbitfld.long 0x04 21. " PS_DATA5 ,Pin 5 state" "Low,High" textline " " rbitfld.long 0x04 20. " PS_DATA4 ,Pin 4 state" "Low,High" rbitfld.long 0x04 19. " PS_DATA3 ,Pin 3 state" "Low,High" rbitfld.long 0x04 18. " PS_DATA2 ,Pin 2 state" "Low,High" rbitfld.long 0x04 17. " PS_DATA1 ,Pin 1 state" "Low,High" textline " " rbitfld.long 0x04 16. " PS_DATA0 ,Pin 0 state" "Low,High" eventfld.long 0x04 8. " FLT_DATA ,Interrupt status of the filtered pin" "No interrupt,Interrupt" eventfld.long 0x04 7. " DATA7 ,Pin 7 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 6. " DATA6 ,Pin 6 interrupt status" "No interrupt,Interrupt" textline " " eventfld.long 0x04 5. " DATA5 ,Pin 5 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 4. " DATA4 ,Pin 4 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 3. " DATA3 ,Pin 3 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 2. " DATA2 ,Pin 2 interrupt status" "No interrupt,Interrupt" textline " " eventfld.long 0x04 1. " DATA1 ,Pin 1 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 0. " DATA0 ,Pin 0 interrupt status" "No interrupt,Interrupt" group.long 0x18++0x03 line.long 0x00 "GPIO_PRT1_PC2,Port 1 Configuration Register 2" bitfld.long 0x00 7. " INP_DIS7 ,Pin 7 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 6. " INP_DIS6 ,Pin 6 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 5. " INP_DIS5 ,Pin 5 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 4. " INP_DIS4 ,Pin 4 input buffer disable" "Enabled,Disabled" textline " " bitfld.long 0x00 3. " INP_DIS3 ,Pin 3 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 2. " INP_DIS2 ,Pin 2 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 1. " INP_DIS1 ,Pin 1 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 0. " INP_DIS0 ,Pin 0 input buffer disable" "Enabled,Disabled" group.long 0x40++0x0B line.long 0x00 "GPIO_PRT1_DR_SET,Port 1 Output Data Set Register" bitfld.long 0x00 7. " DATA_7 ,Pin 7 data output set" "No effect,1" bitfld.long 0x00 6. " DATA_6 ,Pin 6 data output set" "No effect,1" bitfld.long 0x00 5. " DATA_5 ,Pin 5 data output set" "No effect,1" bitfld.long 0x00 4. " DATA_4 ,Pin 4 data output set" "No effect,1" textline " " bitfld.long 0x00 3. " DATA_3 ,Pin 3 data output set" "No effect,1" bitfld.long 0x00 2. " DATA_2 ,Pin 2 data output set" "No effect,1" bitfld.long 0x00 1. " DATA_1 ,Pin 1 data output set" "No effect,1" bitfld.long 0x00 0. " DATA_0 ,Pin 0 data output set" "No effect,1" line.long 0x04 "GPIO_PRT1_DR_CLR,Port 1 Output Data Clear Register" bitfld.long 0x04 7. " DATA_7 ,Pin 7 data output clear" "No effect,0" bitfld.long 0x04 6. " DATA_6 ,Pin 6 data output clear" "No effect,0" bitfld.long 0x04 5. " DATA_5 ,Pin 5 data output clear" "No effect,0" bitfld.long 0x04 4. " DATA_4 ,Pin 4 data output clear" "No effect,0" textline " " bitfld.long 0x04 3. " DATA_3 ,Pin 3 data output clear" "No effect,0" bitfld.long 0x04 2. " DATA_2 ,Pin 2 data output clear" "No effect,0" bitfld.long 0x04 1. " DATA_1 ,Pin 1 data output clear" "No effect,0" bitfld.long 0x04 0. " DATA_0 ,Pin 0 data output clear" "No effect,0" line.long 0x08 "GPIO_PRT1_DR_INV,Port 1 Output Data Invert Register" bitfld.long 0x08 7. " DATA_7 ,Pin 7 data invert" "No effect,Inverted" bitfld.long 0x08 6. " DATA_6 ,Pin 6 data output invert" "No effect,Inverted" bitfld.long 0x08 5. " DATA_5 ,Pin 5 data output invert" "No effect,Inverted" bitfld.long 0x08 4. " DATA_4 ,Pin 4 data output invert" "No effect,Inverted" textline " " bitfld.long 0x08 3. " DATA_3 ,Pin 3 data output invert" "No effect,Inverted" bitfld.long 0x08 2. " DATA_2 ,Pin 2 data output invert" "No effect,Inverted" bitfld.long 0x08 1. " DATA_1 ,Pin 1 data output invert" "No effect,Inverted" bitfld.long 0x08 0. " DATA_0 ,Pin 0 data output invert" "No effect,Inverted" width 0x0B tree.end tree "PORT 2" base ad:0x40040200 width 23. group.long 0x00++0x03 line.long 0x00 "GPIO_PRT2_DR,Port 2 Output Data Register" bitfld.long 0x00 7. " DATA7 ,Pin 7 output data" "Low,High" bitfld.long 0x00 6. " DATA6 ,Pin 6 output data" "Low,High" bitfld.long 0x00 5. " DATA5 ,Pin 5 output data" "Low,High" bitfld.long 0x00 4. " DATA4 ,Pin 4 output data" "Low,High" textline " " bitfld.long 0x00 3. " DATA3 ,Pin 3 output data" "Low,High" bitfld.long 0x00 2. " DATA2 ,Pin 2 output data" "Low,High" bitfld.long 0x00 1. " DATA1 ,Pin 1 output data" "Low,High" bitfld.long 0x00 0. " DATA0 ,Pin 0 output data" "Low,High" rgroup.long 0x04++0x03 line.long 0x00 "GPIO_PRT2_PS,Port 2 IO Pad State Register" bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High" bitfld.long 0x00 7. " DATA7 ,Pin 7 state" "Low,High" bitfld.long 0x00 6. " DATA6 ,Pin 6 state" "Low,High" bitfld.long 0x00 5. " DATA5 ,Pin 5 state" "Low,High" textline " " bitfld.long 0x00 4. " DATA4 ,Pin 4 state" "Low,High" bitfld.long 0x00 3. " DATA3 ,Pin 3 state" "Low,High" bitfld.long 0x00 2. " DATA2 ,Pin 2 state" "Low,High" bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High" textline " " bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High" if (((per.l(ad:0x40040200+0x08))&0x1000000)==0x00) group.long 0x08++0x03 line.long 0x00 "GPIO_PRT2_PC,Port 2 Configuration Register" bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Port 2 input buffer mode select" "CMOS,VCCHIB,CMOS,VCCHIB" bitfld.long 0x00 25. " PORT_SLOW ,Output edge rate of all pins" "Fast,Slow" bitfld.long 0x00 24. " PORT_VTRIP_SEL ,Input buffer function select" "CMOS,LVTTL" bitfld.long 0x00 21.--23. " DM7 ,Pin 7 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 18.--20. " DM6 ,Pin 6 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 15.--17. " DM5 ,Pin 5 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 12.--14. " DM4 ,Pin 4 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 9.--11. " DM3 ,Pin 3 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 6.--8. " DM2 ,Pin 2 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 3.--5. " DM1 ,Pin 1 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 0.--2. " DM0 ,Pin 0 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" else group.long 0x08++0x03 line.long 0x00 "GPIO_PRT2_PC,Port 2 Configuration Register" bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Port 2 input buffer mode select" "LVTTL,VCCHIB,LVTTL,VCCHIB" bitfld.long 0x00 25. " PORT_SLOW ,Output edge rate of all pins" "Fast,Slow" bitfld.long 0x00 24. " PORT_VTRIP_SEL ,Input buffer function select" "CMOS,LVTTL" bitfld.long 0x00 21.--23. " DM7 ,Pin 7 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 18.--20. " DM6 ,Pin 6 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 15.--17. " DM5 ,Pin 5 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 12.--14. " DM4 ,Pin 4 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 9.--11. " DM3 ,Pin 3 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 6.--8. " DM2 ,Pin 2 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 3.--5. " DM1 ,Pin 1 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 0.--2. " DM0 ,Pin 0 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" endif group.long 0x0C++0x07 line.long 0x00 "GPIO_PRT2_INTR_CFG,Port 2 Interrupt Configuration Register" bitfld.long 0x00 18.--20. " FLT_SEL ,Glitch filter input selection" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " FLT_EDGE_SEL ,Glitch filter input edge selection" "Disabled,Rising,Falling,Both" bitfld.long 0x00 14.--15. " EDGE7_SEL ,Pin 7 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 12.--13. " EDGE6_SEL ,Pin 6 IRQ trigger edge select" "Disabled,Rising,Falling,Both" textline " " bitfld.long 0x00 10.--11. " EDGE5_SEL ,Pin 5 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 8.--9. " EDGE4_SEL ,Pin 4 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 6.--7. " EDGE3_SEL ,Pin 3 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 4.--5. " EDGE2_SEL ,Pin 2 IRQ trigger edge select" "Disabled,Rising,Falling,Both" textline " " bitfld.long 0x00 2.--3. " EDGE1_SEL ,Pin 1 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 0.--1. " EDGE0_SEL ,Pin 0 IRQ trigger edge select" "Disabled,Rising,Falling,Both" line.long 0x04 "GPIO_PRT2_INTR,Port 2 Interrupt Status Register" rbitfld.long 0x04 24. " PS_FLT_DATA ,Logical state of the filtered pin" "Low,High" rbitfld.long 0x04 23. " PS_DATA7 ,Pin 7 state" "Low,High" rbitfld.long 0x04 22. " PS_DATA6 ,Pin 6 state" "Low,High" rbitfld.long 0x04 21. " PS_DATA5 ,Pin 5 state" "Low,High" textline " " rbitfld.long 0x04 20. " PS_DATA4 ,Pin 4 state" "Low,High" rbitfld.long 0x04 19. " PS_DATA3 ,Pin 3 state" "Low,High" rbitfld.long 0x04 18. " PS_DATA2 ,Pin 2 state" "Low,High" rbitfld.long 0x04 17. " PS_DATA1 ,Pin 1 state" "Low,High" textline " " rbitfld.long 0x04 16. " PS_DATA0 ,Pin 0 state" "Low,High" eventfld.long 0x04 8. " FLT_DATA ,Interrupt status of the filtered pin" "No interrupt,Interrupt" eventfld.long 0x04 7. " DATA7 ,Pin 7 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 6. " DATA6 ,Pin 6 interrupt status" "No interrupt,Interrupt" textline " " eventfld.long 0x04 5. " DATA5 ,Pin 5 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 4. " DATA4 ,Pin 4 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 3. " DATA3 ,Pin 3 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 2. " DATA2 ,Pin 2 interrupt status" "No interrupt,Interrupt" textline " " eventfld.long 0x04 1. " DATA1 ,Pin 1 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 0. " DATA0 ,Pin 0 interrupt status" "No interrupt,Interrupt" group.long 0x18++0x03 line.long 0x00 "GPIO_PRT2_PC2,Port 2 Configuration Register 2" bitfld.long 0x00 7. " INP_DIS7 ,Pin 7 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 6. " INP_DIS6 ,Pin 6 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 5. " INP_DIS5 ,Pin 5 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 4. " INP_DIS4 ,Pin 4 input buffer disable" "Enabled,Disabled" textline " " bitfld.long 0x00 3. " INP_DIS3 ,Pin 3 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 2. " INP_DIS2 ,Pin 2 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 1. " INP_DIS1 ,Pin 1 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 0. " INP_DIS0 ,Pin 0 input buffer disable" "Enabled,Disabled" group.long 0x40++0x0B line.long 0x00 "GPIO_PRT2_DR_SET,Port 2 Output Data Set Register" bitfld.long 0x00 7. " DATA_7 ,Pin 7 data output set" "No effect,1" bitfld.long 0x00 6. " DATA_6 ,Pin 6 data output set" "No effect,1" bitfld.long 0x00 5. " DATA_5 ,Pin 5 data output set" "No effect,1" bitfld.long 0x00 4. " DATA_4 ,Pin 4 data output set" "No effect,1" textline " " bitfld.long 0x00 3. " DATA_3 ,Pin 3 data output set" "No effect,1" bitfld.long 0x00 2. " DATA_2 ,Pin 2 data output set" "No effect,1" bitfld.long 0x00 1. " DATA_1 ,Pin 1 data output set" "No effect,1" bitfld.long 0x00 0. " DATA_0 ,Pin 0 data output set" "No effect,1" line.long 0x04 "GPIO_PRT2_DR_CLR,Port 2 Output Data Clear Register" bitfld.long 0x04 7. " DATA_7 ,Pin 7 data output clear" "No effect,0" bitfld.long 0x04 6. " DATA_6 ,Pin 6 data output clear" "No effect,0" bitfld.long 0x04 5. " DATA_5 ,Pin 5 data output clear" "No effect,0" bitfld.long 0x04 4. " DATA_4 ,Pin 4 data output clear" "No effect,0" textline " " bitfld.long 0x04 3. " DATA_3 ,Pin 3 data output clear" "No effect,0" bitfld.long 0x04 2. " DATA_2 ,Pin 2 data output clear" "No effect,0" bitfld.long 0x04 1. " DATA_1 ,Pin 1 data output clear" "No effect,0" bitfld.long 0x04 0. " DATA_0 ,Pin 0 data output clear" "No effect,0" line.long 0x08 "GPIO_PRT2_DR_INV,Port 2 Output Data Invert Register" bitfld.long 0x08 7. " DATA_7 ,Pin 7 data invert" "No effect,Inverted" bitfld.long 0x08 6. " DATA_6 ,Pin 6 data output invert" "No effect,Inverted" bitfld.long 0x08 5. " DATA_5 ,Pin 5 data output invert" "No effect,Inverted" bitfld.long 0x08 4. " DATA_4 ,Pin 4 data output invert" "No effect,Inverted" textline " " bitfld.long 0x08 3. " DATA_3 ,Pin 3 data output invert" "No effect,Inverted" bitfld.long 0x08 2. " DATA_2 ,Pin 2 data output invert" "No effect,Inverted" bitfld.long 0x08 1. " DATA_1 ,Pin 1 data output invert" "No effect,Inverted" bitfld.long 0x08 0. " DATA_0 ,Pin 0 data output invert" "No effect,Inverted" width 0x0B tree.end tree "PORT 3" base ad:0x40040300 width 23. group.long 0x00++0x03 line.long 0x00 "GPIO_PRT3_DR,Port 3 Output Data Register" bitfld.long 0x00 7. " DATA7 ,Pin 7 output data" "Low,High" bitfld.long 0x00 6. " DATA6 ,Pin 6 output data" "Low,High" bitfld.long 0x00 5. " DATA5 ,Pin 5 output data" "Low,High" bitfld.long 0x00 4. " DATA4 ,Pin 4 output data" "Low,High" textline " " bitfld.long 0x00 3. " DATA3 ,Pin 3 output data" "Low,High" bitfld.long 0x00 2. " DATA2 ,Pin 2 output data" "Low,High" bitfld.long 0x00 1. " DATA1 ,Pin 1 output data" "Low,High" bitfld.long 0x00 0. " DATA0 ,Pin 0 output data" "Low,High" rgroup.long 0x04++0x03 line.long 0x00 "GPIO_PRT3_PS,Port 3 IO Pad State Register" bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High" bitfld.long 0x00 7. " DATA7 ,Pin 7 state" "Low,High" bitfld.long 0x00 6. " DATA6 ,Pin 6 state" "Low,High" bitfld.long 0x00 5. " DATA5 ,Pin 5 state" "Low,High" textline " " bitfld.long 0x00 4. " DATA4 ,Pin 4 state" "Low,High" bitfld.long 0x00 3. " DATA3 ,Pin 3 state" "Low,High" bitfld.long 0x00 2. " DATA2 ,Pin 2 state" "Low,High" bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High" textline " " bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High" if (((per.l(ad:0x40040300+0x08))&0x1000000)==0x00) group.long 0x08++0x03 line.long 0x00 "GPIO_PRT3_PC,Port 3 Configuration Register" bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Port 3 input buffer mode select" "CMOS,VCCHIB,CMOS,VCCHIB" bitfld.long 0x00 25. " PORT_SLOW ,Output edge rate of all pins" "Fast,Slow" bitfld.long 0x00 24. " PORT_VTRIP_SEL ,Input buffer function select" "CMOS,LVTTL" bitfld.long 0x00 21.--23. " DM7 ,Pin 7 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 18.--20. " DM6 ,Pin 6 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 15.--17. " DM5 ,Pin 5 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 12.--14. " DM4 ,Pin 4 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 9.--11. " DM3 ,Pin 3 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 6.--8. " DM2 ,Pin 2 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 3.--5. " DM1 ,Pin 1 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 0.--2. " DM0 ,Pin 0 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" else group.long 0x08++0x03 line.long 0x00 "GPIO_PRT3_PC,Port 3 Configuration Register" bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Port 3 input buffer mode select" "LVTTL,VCCHIB,LVTTL,VCCHIB" bitfld.long 0x00 25. " PORT_SLOW ,Output edge rate of all pins" "Fast,Slow" bitfld.long 0x00 24. " PORT_VTRIP_SEL ,Input buffer function select" "CMOS,LVTTL" bitfld.long 0x00 21.--23. " DM7 ,Pin 7 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 18.--20. " DM6 ,Pin 6 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 15.--17. " DM5 ,Pin 5 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 12.--14. " DM4 ,Pin 4 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 9.--11. " DM3 ,Pin 3 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 6.--8. " DM2 ,Pin 2 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 3.--5. " DM1 ,Pin 1 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 0.--2. " DM0 ,Pin 0 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" endif group.long 0x0C++0x07 line.long 0x00 "GPIO_PRT3_INTR_CFG,Port 3 Interrupt Configuration Register" bitfld.long 0x00 18.--20. " FLT_SEL ,Glitch filter input selection" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " FLT_EDGE_SEL ,Glitch filter input edge selection" "Disabled,Rising,Falling,Both" bitfld.long 0x00 14.--15. " EDGE7_SEL ,Pin 7 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 12.--13. " EDGE6_SEL ,Pin 6 IRQ trigger edge select" "Disabled,Rising,Falling,Both" textline " " bitfld.long 0x00 10.--11. " EDGE5_SEL ,Pin 5 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 8.--9. " EDGE4_SEL ,Pin 4 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 6.--7. " EDGE3_SEL ,Pin 3 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 4.--5. " EDGE2_SEL ,Pin 2 IRQ trigger edge select" "Disabled,Rising,Falling,Both" textline " " bitfld.long 0x00 2.--3. " EDGE1_SEL ,Pin 1 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 0.--1. " EDGE0_SEL ,Pin 0 IRQ trigger edge select" "Disabled,Rising,Falling,Both" line.long 0x04 "GPIO_PRT3_INTR,Port 3 Interrupt Status Register" rbitfld.long 0x04 24. " PS_FLT_DATA ,Logical state of the filtered pin" "Low,High" rbitfld.long 0x04 23. " PS_DATA7 ,Pin 7 state" "Low,High" rbitfld.long 0x04 22. " PS_DATA6 ,Pin 6 state" "Low,High" rbitfld.long 0x04 21. " PS_DATA5 ,Pin 5 state" "Low,High" textline " " rbitfld.long 0x04 20. " PS_DATA4 ,Pin 4 state" "Low,High" rbitfld.long 0x04 19. " PS_DATA3 ,Pin 3 state" "Low,High" rbitfld.long 0x04 18. " PS_DATA2 ,Pin 2 state" "Low,High" rbitfld.long 0x04 17. " PS_DATA1 ,Pin 1 state" "Low,High" textline " " rbitfld.long 0x04 16. " PS_DATA0 ,Pin 0 state" "Low,High" eventfld.long 0x04 8. " FLT_DATA ,Interrupt status of the filtered pin" "No interrupt,Interrupt" eventfld.long 0x04 7. " DATA7 ,Pin 7 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 6. " DATA6 ,Pin 6 interrupt status" "No interrupt,Interrupt" textline " " eventfld.long 0x04 5. " DATA5 ,Pin 5 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 4. " DATA4 ,Pin 4 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 3. " DATA3 ,Pin 3 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 2. " DATA2 ,Pin 2 interrupt status" "No interrupt,Interrupt" textline " " eventfld.long 0x04 1. " DATA1 ,Pin 1 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 0. " DATA0 ,Pin 0 interrupt status" "No interrupt,Interrupt" group.long 0x18++0x03 line.long 0x00 "GPIO_PRT3_PC2,Port 3 Configuration Register 2" bitfld.long 0x00 7. " INP_DIS7 ,Pin 7 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 6. " INP_DIS6 ,Pin 6 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 5. " INP_DIS5 ,Pin 5 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 4. " INP_DIS4 ,Pin 4 input buffer disable" "Enabled,Disabled" textline " " bitfld.long 0x00 3. " INP_DIS3 ,Pin 3 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 2. " INP_DIS2 ,Pin 2 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 1. " INP_DIS1 ,Pin 1 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 0. " INP_DIS0 ,Pin 0 input buffer disable" "Enabled,Disabled" group.long 0x40++0x0B line.long 0x00 "GPIO_PRT3_DR_SET,Port 3 Output Data Set Register" bitfld.long 0x00 7. " DATA_7 ,Pin 7 data output set" "No effect,1" bitfld.long 0x00 6. " DATA_6 ,Pin 6 data output set" "No effect,1" bitfld.long 0x00 5. " DATA_5 ,Pin 5 data output set" "No effect,1" bitfld.long 0x00 4. " DATA_4 ,Pin 4 data output set" "No effect,1" textline " " bitfld.long 0x00 3. " DATA_3 ,Pin 3 data output set" "No effect,1" bitfld.long 0x00 2. " DATA_2 ,Pin 2 data output set" "No effect,1" bitfld.long 0x00 1. " DATA_1 ,Pin 1 data output set" "No effect,1" bitfld.long 0x00 0. " DATA_0 ,Pin 0 data output set" "No effect,1" line.long 0x04 "GPIO_PRT3_DR_CLR,Port 3 Output Data Clear Register" bitfld.long 0x04 7. " DATA_7 ,Pin 7 data output clear" "No effect,0" bitfld.long 0x04 6. " DATA_6 ,Pin 6 data output clear" "No effect,0" bitfld.long 0x04 5. " DATA_5 ,Pin 5 data output clear" "No effect,0" bitfld.long 0x04 4. " DATA_4 ,Pin 4 data output clear" "No effect,0" textline " " bitfld.long 0x04 3. " DATA_3 ,Pin 3 data output clear" "No effect,0" bitfld.long 0x04 2. " DATA_2 ,Pin 2 data output clear" "No effect,0" bitfld.long 0x04 1. " DATA_1 ,Pin 1 data output clear" "No effect,0" bitfld.long 0x04 0. " DATA_0 ,Pin 0 data output clear" "No effect,0" line.long 0x08 "GPIO_PRT3_DR_INV,Port 3 Output Data Invert Register" bitfld.long 0x08 7. " DATA_7 ,Pin 7 data invert" "No effect,Inverted" bitfld.long 0x08 6. " DATA_6 ,Pin 6 data output invert" "No effect,Inverted" bitfld.long 0x08 5. " DATA_5 ,Pin 5 data output invert" "No effect,Inverted" bitfld.long 0x08 4. " DATA_4 ,Pin 4 data output invert" "No effect,Inverted" textline " " bitfld.long 0x08 3. " DATA_3 ,Pin 3 data output invert" "No effect,Inverted" bitfld.long 0x08 2. " DATA_2 ,Pin 2 data output invert" "No effect,Inverted" bitfld.long 0x08 1. " DATA_1 ,Pin 1 data output invert" "No effect,Inverted" bitfld.long 0x08 0. " DATA_0 ,Pin 0 data output invert" "No effect,Inverted" width 0x0B tree.end tree "PORT 4" base ad:0x40040400 width 23. group.long 0x00++0x03 line.long 0x00 "GPIO_PRT4_DR,Port 4 Output Data Register" sif (cpuis("CY8C4246AZI-L435")||cpuis("CY8C424?AZI-L445")||cpuis("CY8C424?AZI-L475")||cpuis("CY8C424?AZI-L485")) bitfld.long 0x00 6. " DATA6 ,Pin 6 output data" "Low,High" bitfld.long 0x00 5. " DATA5 ,Pin 5 output data" "Low,High" bitfld.long 0x00 4. " DATA4 ,Pin 4 output data" "Low,High" endif textline " " bitfld.long 0x00 3. " DATA3 ,Pin 3 output data" "Low,High" bitfld.long 0x00 2. " DATA2 ,Pin 2 output data" "Low,High" bitfld.long 0x00 1. " DATA1 ,Pin 1 output data" "Low,High" bitfld.long 0x00 0. " DATA0 ,Pin 0 output data" "Low,High" rgroup.long 0x04++0x03 line.long 0x00 "GPIO_PRT4_PS,Port 4 IO Pad State Register" sif (cpuis("CY8C4246AZI-L435")||cpuis("CY8C424?AZI-L445")||cpuis("CY8C424?AZI-L475")||cpuis("CY8C424?AZI-L485")) bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High" bitfld.long 0x00 6. " DATA6 ,Pin 6 state" "Low,High" bitfld.long 0x00 5. " DATA5 ,Pin 5 state" "Low,High" bitfld.long 0x00 4. " DATA4 ,Pin 4 state" "Low,High" textline " " bitfld.long 0x00 3. " DATA3 ,Pin 3 state" "Low,High" bitfld.long 0x00 2. " DATA2 ,Pin 2 state" "Low,High" bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High" bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High" else bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High" bitfld.long 0x00 3. " DATA3 ,Pin 3 state" "Low,High" bitfld.long 0x00 2. " DATA2 ,Pin 2 state" "Low,High" bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High" textline " " bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High" endif if (((per.l(ad:0x40040400+0x08))&0x1000000)==0x00) group.long 0x08++0x03 line.long 0x00 "GPIO_PRT4_PC,Port 4 Configuration Register" bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Port 4 input buffer mode select" "CMOS,VCCHIB,CMOS,VCCHIB" bitfld.long 0x00 25. " PORT_SLOW ,Output edge rate of all pins" "Fast,Slow" bitfld.long 0x00 24. " PORT_VTRIP_SEL ,Input buffer function select" "CMOS,LVTTL" textline " " sif (!cpuis("CY8C424?AZI-L423")&&!cpuis("CY8C424?AZI-L433")) bitfld.long 0x00 18.--20. " DM6 ,Pin 6 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 15.--17. " DM5 ,Pin 5 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 12.--14. " DM4 ,Pin 4 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 9.--11. " DM3 ,Pin 3 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 6.--8. " DM2 ,Pin 2 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 3.--5. " DM1 ,Pin 1 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 0.--2. " DM0 ,Pin 0 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" else bitfld.long 0x00 9.--11. " DM3 ,Pin 3 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 6.--8. " DM2 ,Pin 2 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 3.--5. " DM1 ,Pin 1 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 0.--2. " DM0 ,Pin 0 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" endif else group.long 0x08++0x03 line.long 0x00 "GPIO_PRT4_PC,Port 4 Configuration Register" bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Port 4 input buffer mode select" "LVTTL,VCCHIB,LVTTL,VCCHIB" bitfld.long 0x00 25. " PORT_SLOW ,Output edge rate of all pins" "Fast,Slow" bitfld.long 0x00 24. " PORT_VTRIP_SEL ,Input buffer function select" "CMOS,LVTTL" textline " " sif (!cpuis("CY8C424?AZI-L423")&&!cpuis("CY8C424?AZI-L433")) bitfld.long 0x00 18.--20. " DM6 ,Pin 6 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 15.--17. " DM5 ,Pin 5 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 12.--14. " DM4 ,Pin 4 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 9.--11. " DM3 ,Pin 3 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 6.--8. " DM2 ,Pin 2 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 3.--5. " DM1 ,Pin 1 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 0.--2. " DM0 ,Pin 0 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" else bitfld.long 0x00 9.--11. " DM3 ,Pin 3 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 6.--8. " DM2 ,Pin 2 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 3.--5. " DM1 ,Pin 1 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 0.--2. " DM0 ,Pin 0 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" endif endif group.long 0x0C++0x07 line.long 0x00 "GPIO_PRT4_INTR_CFG,Port 4 Interrupt Configuration Register" sif (cpuis("CY8C4246AZI-L435")||cpuis("CY8C424?AZI-L445")||cpuis("CY8C424?AZI-L475")||cpuis("CY8C424?AZI-L485")) bitfld.long 0x00 18.--20. " FLT_SEL ,Glitch filter input selection" "0,1,2,3,4,5,6,?..." bitfld.long 0x00 16.--17. " FLT_EDGE_SEL ,Glitch filter input edge selection" "Disabled,Rising,Falling,Both" bitfld.long 0x00 12.--13. " EDGE6_SEL ,Pin 6 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 10.--11. " EDGE5_SEL ,Pin 5 IRQ trigger edge select" "Disabled,Rising,Falling,Both" textline " " bitfld.long 0x00 8.--9. " EDGE4_SEL ,Pin 4 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 6.--7. " EDGE3_SEL ,Pin 3 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 4.--5. " EDGE2_SEL ,Pin 2 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 2.--3. " EDGE1_SEL ,Pin 1 IRQ trigger edge select" "Disabled,Rising,Falling,Both" textline " " bitfld.long 0x00 0.--1. " EDGE0_SEL ,Pin 0 IRQ trigger edge select" "Disabled,Rising,Falling,Both" else bitfld.long 0x00 18.--20. " FLT_SEL ,Glitch filter input selection" "0,1,2,3,?..." bitfld.long 0x00 16.--17. " FLT_EDGE_SEL ,Glitch filter input edge selection" "Disabled,Rising,Falling,Both" bitfld.long 0x00 6.--7. " EDGE3_SEL ,Pin 3 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 4.--5. " EDGE2_SEL ,Pin 2 IRQ trigger edge select" "Disabled,Rising,Falling,Both" textline " " bitfld.long 0x00 2.--3. " EDGE1_SEL ,Pin 1 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 0.--1. " EDGE0_SEL ,Pin 0 IRQ trigger edge select" "Disabled,Rising,Falling,Both" endif line.long 0x04 "GPIO_PRT4_INTR,Port 4 Interrupt Status Register" sif (cpuis("CY8C4246AZI-L435")||cpuis("CY8C424?AZI-L445")||cpuis("CY8C424?AZI-L475")||cpuis("CY8C424?AZI-L485")) rbitfld.long 0x04 24. " PS_FLT_DATA ,Logical state of the filtered pin" "Low,High" rbitfld.long 0x04 22. " PS_DATA6 ,Pin 6 state" "Low,High" rbitfld.long 0x04 21. " PS_DATA5 ,Pin 5 state" "Low,High" rbitfld.long 0x04 20. " PS_DATA4 ,Pin 4 state" "Low,High" textline " " rbitfld.long 0x04 19. " PS_DATA3 ,Pin 3 state" "Low,High" rbitfld.long 0x04 18. " PS_DATA2 ,Pin 2 state" "Low,High" rbitfld.long 0x04 17. " PS_DATA1 ,Pin 1 state" "Low,High" rbitfld.long 0x04 16. " PS_DATA0 ,Pin 0 state" "Low,High" textline " " eventfld.long 0x04 8. " FLT_DATA ,Interrupt status of the filtered pin" "No interrupt,Interrupt" eventfld.long 0x04 6. " DATA6 ,Pin 6 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 5. " DATA5 ,Pin 5 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 4. " DATA4 ,Pin 4 interrupt status" "No interrupt,Interrupt" textline " " eventfld.long 0x04 3. " DATA3 ,Pin 3 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 2. " DATA2 ,Pin 2 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 1. " DATA1 ,Pin 1 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 0. " DATA0 ,Pin 0 interrupt status" "No interrupt,Interrupt" else rbitfld.long 0x04 24. " PS_FLT_DATA ,Logical state of the filtered pin" "Low,High" rbitfld.long 0x04 19. " PS_DATA3 ,Pin 3 state" "Low,High" rbitfld.long 0x04 18. " PS_DATA2 ,Pin 2 state" "Low,High" rbitfld.long 0x04 17. " PS_DATA1 ,Pin 1 state" "Low,High" textline " " rbitfld.long 0x04 16. " PS_DATA0 ,Pin 0 state" "Low,High" rbitfld.long 0x04 24. " PS_FLT_DATA ,Logical state of the filtered pin" "Low,High" eventfld.long 0x04 3. " DATA3 ,Pin 3 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 2. " DATA2 ,Pin 2 interrupt status" "No interrupt,Interrupt" textline " " eventfld.long 0x04 1. " DATA1 ,Pin 1 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 0. " DATA0 ,Pin 0 interrupt status" "No interrupt,Interrupt" endif group.long 0x18++0x03 line.long 0x00 "GPIO_PRT4_PC2,Port 4 Configuration Register 2" sif (cpuis("CY8C4246AZI-L435")||cpuis("CY8C424?AZI-L445")||cpuis("CY8C424?AZI-L475")||cpuis("CY8C424?AZI-L485")) bitfld.long 0x00 6. " INP_DIS6 ,Pin 6 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 5. " INP_DIS5 ,Pin 5 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 4. " INP_DIS4 ,Pin 4 input buffer disable" "Enabled,Disabled" endif textline " " bitfld.long 0x00 3. " INP_DIS3 ,Pin 3 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 2. " INP_DIS2 ,Pin 2 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 1. " INP_DIS1 ,Pin 1 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 0. " INP_DIS0 ,Pin 0 input buffer disable" "Enabled,Disabled" group.long 0x40++0x0B line.long 0x00 "GPIO_PRT4_DR_SET,Port 4 Output Data Set Register" sif (cpuis("CY8C4246AZI-L435")||cpuis("CY8C424?AZI-L445")||cpuis("CY8C424?AZI-L475")||cpuis("CY8C424?AZI-L485")) bitfld.long 0x00 6. " DATA[6] ,Pin 6 data output set" "No effect,1" bitfld.long 0x00 5. " DATA[5] ,Pin 5 data output set" "No effect,1" bitfld.long 0x00 4. " DATA[4] ,Pin 4 data output set" "No effect,1" endif textline " " bitfld.long 0x00 3. " DATA[3] ,Pin 3 data output set" "No effect,1" bitfld.long 0x00 2. " DATA[2] ,Pin 2 data output set" "No effect,1" bitfld.long 0x00 1. " DATA[1] ,Pin 1 data output set" "No effect,1" bitfld.long 0x00 0. " DATA[0] ,Pin 0 data output set" "No effect,1" line.long 0x04 "GPIO_PRT4_DR_CLR,Port 4 Output Data Clear Register" sif (cpuis("CY8C4246AZI-L435")||cpuis("CY8C424?AZI-L445")||cpuis("CY8C424?AZI-L475")||cpuis("CY8C424?AZI-L485")) bitfld.long 0x04 6. " DATA[6] ,Pin 6 data output clear" "No effect,0" bitfld.long 0x04 5. " DATA[5] ,Pin 5 data output clear" "No effect,0" bitfld.long 0x04 4. " DATA[4] ,Pin 4 data output clear" "No effect,0" endif textline " " bitfld.long 0x04 3. " DATA[3] ,Pin 3 data output clear" "No effect,0" bitfld.long 0x04 2. " DATA[2] ,Pin 2 data output clear" "No effect,0" bitfld.long 0x04 1. " DATA[1] ,Pin 1 data output clear" "No effect,0" bitfld.long 0x04 0. " DATA[0] ,Pin 0 data output clear" "No effect,0" line.long 0x08 "GPIO_PRT4_DR_INV,Port 4 Output Data Invert Register" sif (cpuis("CY8C4246AZI-L435")||cpuis("CY8C424?AZI-L445")||cpuis("CY8C424?AZI-L475")||cpuis("CY8C424?AZI-L485")) bitfld.long 0x08 6. " DATA[6] ,Pin 6 data output invert" "No effect,Inverted" bitfld.long 0x08 5. " DATA[5] ,Pin 5 data output invert" "No effect,Inverted" bitfld.long 0x08 4. " DATA[4] ,Pin 4 data output invert" "No effect,Inverted" endif textline " " bitfld.long 0x08 3. " DATA[3] ,Pin 3 data output invert" "No effect,Inverted" bitfld.long 0x08 2. " DATA[2] ,Pin 2 data output invert" "No effect,Inverted" bitfld.long 0x08 1. " DATA[1] ,Pin 1 data output invert" "No effect,Inverted" bitfld.long 0x08 0. " DATA[0] ,Pin 0 data output invert" "No effect,Inverted" width 0x0B tree.end sif (!cpuis("CY8C424?AZI-L423")&&!cpuis("CY8C424?AZI-L433")) sif (cpuis("CY8C424?BZI-L489")||cpuis("CY8C424?BZI-L479")) tree "PORT 5" base ad:0x40040500 width 23. group.long 0x00++0x03 line.long 0x00 "GPIO_PRT5_DR,Port 5 Output Data Register" bitfld.long 0x00 7. " DATA7 ,Pin 7 output data" "Low,High" bitfld.long 0x00 6. " DATA6 ,Pin 6 output data" "Low,High" bitfld.long 0x00 5. " DATA5 ,Pin 5 output data" "Low,High" bitfld.long 0x00 4. " DATA4 ,Pin 4 output data" "Low,High" textline " " bitfld.long 0x00 3. " DATA3 ,Pin 3 output data" "Low,High" bitfld.long 0x00 2. " DATA2 ,Pin 2 output data" "Low,High" bitfld.long 0x00 1. " DATA1 ,Pin 1 output data" "Low,High" bitfld.long 0x00 0. " DATA0 ,Pin 0 output data" "Low,High" rgroup.long 0x04++0x03 line.long 0x00 "GPIO_PRT5_PS,Port 5 IO Pad State Register" bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High" bitfld.long 0x00 7. " DATA7 ,Pin 7 state" "Low,High" bitfld.long 0x00 6. " DATA6 ,Pin 6 state" "Low,High" bitfld.long 0x00 5. " DATA5 ,Pin 5 state" "Low,High" textline " " bitfld.long 0x00 4. " DATA4 ,Pin 4 state" "Low,High" bitfld.long 0x00 3. " DATA3 ,Pin 3 state" "Low,High" bitfld.long 0x00 2. " DATA2 ,Pin 2 state" "Low,High" bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High" textline " " bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High" if (((per.l(ad:0x40040500+0x08))&0x1000000)==0x00) group.long 0x08++0x03 line.long 0x00 "GPIO_PRT5_PC,Port 5 Configuration Register" bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Port 5 input buffer mode select" "CMOS,VCCHIB,CMOS,VCCHIB" bitfld.long 0x00 25. " PORT_SLOW ,Output edge rate of all pins" "Fast,Slow" bitfld.long 0x00 24. " PORT_VTRIP_SEL ,Input buffer function select" "CMOS,LVTTL" bitfld.long 0x00 21.--23. " DM7 ,Pin 7 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 18.--20. " DM6 ,Pin 6 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 15.--17. " DM5 ,Pin 5 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 12.--14. " DM4 ,Pin 4 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 9.--11. " DM3 ,Pin 3 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 6.--8. " DM2 ,Pin 2 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 3.--5. " DM1 ,Pin 1 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 0.--2. " DM0 ,Pin 0 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" else group.long 0x08++0x03 line.long 0x00 "GPIO_PRT5_PC,Port 5 Configuration Register" bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Port 5 input buffer mode select" "LVTTL,VCCHIB,LVTTL,VCCHIB" bitfld.long 0x00 25. " PORT_SLOW ,Output edge rate of all pins" "Fast,Slow" bitfld.long 0x00 24. " PORT_VTRIP_SEL ,Input buffer function select" "CMOS,LVTTL" bitfld.long 0x00 21.--23. " DM7 ,Pin 7 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 18.--20. " DM6 ,Pin 6 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 15.--17. " DM5 ,Pin 5 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 12.--14. " DM4 ,Pin 4 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 9.--11. " DM3 ,Pin 3 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 6.--8. " DM2 ,Pin 2 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 3.--5. " DM1 ,Pin 1 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 0.--2. " DM0 ,Pin 0 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" endif group.long 0x0C++0x07 line.long 0x00 "GPIO_PRT5_INTR_CFG,Port 5 Interrupt Configuration Register" bitfld.long 0x00 18.--20. " FLT_SEL ,Glitch filter input selection" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " FLT_EDGE_SEL ,Glitch filter input edge selection" "Disabled,Rising,Falling,Both" bitfld.long 0x00 14.--15. " EDGE7_SEL ,Pin 7 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 12.--13. " EDGE6_SEL ,Pin 6 IRQ trigger edge select" "Disabled,Rising,Falling,Both" textline " " bitfld.long 0x00 10.--11. " EDGE5_SEL ,Pin 5 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 8.--9. " EDGE4_SEL ,Pin 4 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 6.--7. " EDGE3_SEL ,Pin 3 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 4.--5. " EDGE2_SEL ,Pin 2 IRQ trigger edge select" "Disabled,Rising,Falling,Both" textline " " bitfld.long 0x00 2.--3. " EDGE1_SEL ,Pin 1 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 0.--1. " EDGE0_SEL ,Pin 0 IRQ trigger edge select" "Disabled,Rising,Falling,Both" line.long 0x04 "GPIO_PRT5_INTR,Port 5 Interrupt Status Register" rbitfld.long 0x04 24. " PS_FLT_DATA ,Logical state of the filtered pin" "Low,High" rbitfld.long 0x04 23. " PS_DATA7 ,Pin 7 state" "Low,High" rbitfld.long 0x04 22. " PS_DATA6 ,Pin 6 state" "Low,High" rbitfld.long 0x04 21. " PS_DATA5 ,Pin 5 state" "Low,High" textline " " rbitfld.long 0x04 20. " PS_DATA4 ,Pin 4 state" "Low,High" rbitfld.long 0x04 19. " PS_DATA3 ,Pin 3 state" "Low,High" rbitfld.long 0x04 18. " PS_DATA2 ,Pin 2 state" "Low,High" rbitfld.long 0x04 17. " PS_DATA1 ,Pin 1 state" "Low,High" textline " " rbitfld.long 0x04 16. " PS_DATA0 ,Pin 0 state" "Low,High" eventfld.long 0x04 8. " FLT_DATA ,Interrupt status of the filtered pin" "No interrupt,Interrupt" eventfld.long 0x04 7. " DATA7 ,Pin 7 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 6. " DATA6 ,Pin 6 interrupt status" "No interrupt,Interrupt" textline " " eventfld.long 0x04 5. " DATA5 ,Pin 5 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 4. " DATA4 ,Pin 4 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 3. " DATA3 ,Pin 3 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 2. " DATA2 ,Pin 2 interrupt status" "No interrupt,Interrupt" textline " " eventfld.long 0x04 1. " DATA1 ,Pin 1 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 0. " DATA0 ,Pin 0 interrupt status" "No interrupt,Interrupt" group.long 0x18++0x03 line.long 0x00 "GPIO_PRT5_PC2,Port 5 Configuration Register 2" bitfld.long 0x00 7. " INP_DIS7 ,Pin 7 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 6. " INP_DIS6 ,Pin 6 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 5. " INP_DIS5 ,Pin 5 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 4. " INP_DIS4 ,Pin 4 input buffer disable" "Enabled,Disabled" textline " " bitfld.long 0x00 3. " INP_DIS3 ,Pin 3 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 2. " INP_DIS2 ,Pin 2 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 1. " INP_DIS1 ,Pin 1 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 0. " INP_DIS0 ,Pin 0 input buffer disable" "Enabled,Disabled" group.long 0x40++0x0B line.long 0x00 "GPIO_PRT5_DR_SET,Port 5 Output Data Set Register" bitfld.long 0x00 7. " DATA_7 ,Pin 7 data output set" "No effect,1" bitfld.long 0x00 6. " DATA_6 ,Pin 6 data output set" "No effect,1" bitfld.long 0x00 5. " DATA_5 ,Pin 5 data output set" "No effect,1" bitfld.long 0x00 4. " DATA_4 ,Pin 4 data output set" "No effect,1" textline " " bitfld.long 0x00 3. " DATA_3 ,Pin 3 data output set" "No effect,1" bitfld.long 0x00 2. " DATA_2 ,Pin 2 data output set" "No effect,1" bitfld.long 0x00 1. " DATA_1 ,Pin 1 data output set" "No effect,1" bitfld.long 0x00 0. " DATA_0 ,Pin 0 data output set" "No effect,1" line.long 0x04 "GPIO_PRT5_DR_CLR,Port 5 Output Data Clear Register" bitfld.long 0x04 7. " DATA_7 ,Pin 7 data output clear" "No effect,0" bitfld.long 0x04 6. " DATA_6 ,Pin 6 data output clear" "No effect,0" bitfld.long 0x04 5. " DATA_5 ,Pin 5 data output clear" "No effect,0" bitfld.long 0x04 4. " DATA_4 ,Pin 4 data output clear" "No effect,0" textline " " bitfld.long 0x04 3. " DATA_3 ,Pin 3 data output clear" "No effect,0" bitfld.long 0x04 2. " DATA_2 ,Pin 2 data output clear" "No effect,0" bitfld.long 0x04 1. " DATA_1 ,Pin 1 data output clear" "No effect,0" bitfld.long 0x04 0. " DATA_0 ,Pin 0 data output clear" "No effect,0" line.long 0x08 "GPIO_PRT5_DR_INV,Port 5 Output Data Invert Register" bitfld.long 0x08 7. " DATA_7 ,Pin 7 data invert" "No effect,Inverted" bitfld.long 0x08 6. " DATA_6 ,Pin 6 data output invert" "No effect,Inverted" bitfld.long 0x08 5. " DATA_5 ,Pin 5 data output invert" "No effect,Inverted" bitfld.long 0x08 4. " DATA_4 ,Pin 4 data output invert" "No effect,Inverted" textline " " bitfld.long 0x08 3. " DATA_3 ,Pin 3 data output invert" "No effect,Inverted" bitfld.long 0x08 2. " DATA_2 ,Pin 2 data output invert" "No effect,Inverted" bitfld.long 0x08 1. " DATA_1 ,Pin 1 data output invert" "No effect,Inverted" bitfld.long 0x08 0. " DATA_0 ,Pin 0 data output invert" "No effect,Inverted" width 0x0B tree.end else tree "PORT 5" base ad:0x40040500 width 23. group.long 0x00++0x03 line.long 0x00 "GPIO_PRT5_DR,Port 5 Output Data Register" sif (cpuis("CY8C424?LTI-L485")||cpuis("CY8C424?LTI-L475")||cpuis("CY8C424?LTI-L445")) bitfld.long 0x00 5. " DATA5 ,Pin 5 output data" "Low,High" bitfld.long 0x00 4. " DATA4 ,Pin 4 output data" "Low,High" else bitfld.long 0x00 5. " DATA5 ,Pin 5 output data" "Low,High" endif textline " " bitfld.long 0x00 3. " DATA3 ,Pin 3 output data" "Low,High" bitfld.long 0x00 2. " DATA2 ,Pin 2 output data" "Low,High" bitfld.long 0x00 1. " DATA1 ,Pin 1 output data" "Low,High" bitfld.long 0x00 0. " DATA0 ,Pin 0 output data" "Low,High" rgroup.long 0x04++0x03 line.long 0x00 "GPIO_PRT5_PS,Port 5 IO Pad State Register" bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High" bitfld.long 0x00 5. " DATA5 ,Pin 5 state" "Low,High" textline " " sif (cpuis("CY8C424?LTI-L485")||cpuis("CY8C424?LTI-L475")||cpuis("CY8C424?LTI-L445")) bitfld.long 0x00 4. " DATA4 ,Pin 4 state" "Low,High" bitfld.long 0x00 3. " DATA3 ,Pin 3 state" "Low,High" else bitfld.long 0x00 3. " DATA3 ,Pin 3 state" "Low,High" endif textline " " bitfld.long 0x00 2. " DATA2 ,Pin 2 state" "Low,High" bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High" bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High" if (((per.l(ad:0x40040500+0x08))&0x1000000)==0x00) group.long 0x08++0x03 line.long 0x00 "GPIO_PRT5_PC,Port 5 Configuration Register" bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Port 5 input buffer mode select" "CMOS,VCCHIB,CMOS,VCCHIB" bitfld.long 0x00 25. " PORT_SLOW ,Output edge rate of all pins" "Fast,Slow" bitfld.long 0x00 24. " PORT_VTRIP_SEL ,Input buffer function select" "CMOS,LVTTL" bitfld.long 0x00 15.--17. " DM5 ,Pin 5 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " sif (cpuis("CY8C424?LTI-L485")||cpuis("CY8C424?LTI-L475")||cpuis("CY8C424?LTI-L445")) bitfld.long 0x00 12.--14. " DM4 ,Pin 4 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 9.--11. " DM3 ,Pin 3 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 6.--8. " DM2 ,Pin 2 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 3.--5. " DM1 ,Pin 1 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 0.--2. " DM0 ,Pin 0 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" else bitfld.long 0x00 9.--11. " DM3 ,Pin 3 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 6.--8. " DM2 ,Pin 2 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 3.--5. " DM1 ,Pin 1 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 0.--2. " DM0 ,Pin 0 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" endif else group.long 0x08++0x03 line.long 0x00 "GPIO_PRT5_PC,Port 5 Configuration Register" bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Port 5 input buffer mode select" "LVTTL,VCCHIB,LVTTL,VCCHIB" bitfld.long 0x00 25. " PORT_SLOW ,Output edge rate of all pins" "Fast,Slow" bitfld.long 0x00 24. " PORT_VTRIP_SEL ,Input buffer function select" "CMOS,LVTTL" bitfld.long 0x00 15.--17. " DM5 ,Pin 5 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " sif (cpuis("CY8C424?LTI-L485")||cpuis("CY8C424?LTI-L475")||cpuis("CY8C424?LTI-L445")) bitfld.long 0x00 12.--14. " DM4 ,Pin 4 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 9.--11. " DM3 ,Pin 3 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 6.--8. " DM2 ,Pin 2 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 3.--5. " DM1 ,Pin 1 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 0.--2. " DM0 ,Pin 0 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" else bitfld.long 0x00 9.--11. " DM3 ,Pin 3 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 6.--8. " DM2 ,Pin 2 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 3.--5. " DM1 ,Pin 1 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 0.--2. " DM0 ,Pin 0 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" endif endif group.long 0x0C++0x07 line.long 0x00 "GPIO_PRT5_INTR_CFG,Port 5 Interrupt Configuration Register" sif (cpuis("CY8C424?LTI-L485")||cpuis("CY8C424?LTI-L475")||cpuis("CY8C424?LTI-L445")) bitfld.long 0x00 18.--20. " FLT_SEL ,Glitch filter input selection" "0,1,2,3,4,5,?..." bitfld.long 0x00 16.--17. " FLT_EDGE_SEL ,Glitch filter input edge selection" "Disabled,Rising,Falling,Both" bitfld.long 0x00 10.--11. " EDGE5_SEL ,Pin 5 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 8.--9. " EDGE4_SEL ,Pin 4 IRQ trigger edge select" "Disabled,Rising,Falling,Both" textline " " bitfld.long 0x00 6.--7. " EDGE3_SEL ,Pin 3 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 4.--5. " EDGE2_SEL ,Pin 2 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 2.--3. " EDGE1_SEL ,Pin 1 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 0.--1. " EDGE0_SEL ,Pin 0 IRQ trigger edge select" "Disabled,Rising,Falling,Both" else bitfld.long 0x00 18.--20. " FLT_SEL ,Glitch filter input selection" "0,1,2,3,,5,?..." bitfld.long 0x00 16.--17. " FLT_EDGE_SEL ,Glitch filter input edge selection" "Disabled,Rising,Falling,Both" bitfld.long 0x00 10.--11. " EDGE5_SEL ,Pin 5 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 6.--7. " EDGE3_SEL ,Pin 3 IRQ trigger edge select" "Disabled,Rising,Falling,Both" textline " " bitfld.long 0x00 4.--5. " EDGE2_SEL ,Pin 2 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 2.--3. " EDGE1_SEL ,Pin 1 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 0.--1. " EDGE0_SEL ,Pin 0 IRQ trigger edge select" "Disabled,Rising,Falling,Both" endif line.long 0x04 "GPIO_PRT5_INTR,Port 5 Interrupt Status Register" sif (cpuis("CY8C424?LTI-L485")||cpuis("CY8C424?LTI-L475")||cpuis("CY8C424?LTI-L445")) rbitfld.long 0x04 24. " PS_FLT_DATA ,Logical state of the filtered pin" "Low,High" rbitfld.long 0x04 21. " PS_DATA5 ,Pin 5 state" "Low,High" rbitfld.long 0x04 20. " PS_DATA4 ,Pin 4 state" "Low,High" rbitfld.long 0x04 19. " PS_DATA3 ,Pin 3 state" "Low,High" textline " " rbitfld.long 0x04 18. " PS_DATA2 ,Pin 2 state" "Low,High" rbitfld.long 0x04 17. " PS_DATA1 ,Pin 1 state" "Low,High" rbitfld.long 0x04 16. " PS_DATA0 ,Pin 0 state" "Low,High" eventfld.long 0x04 8. " FLT_DATA ,Interrupt status of the filtered pin" "No interrupt,Interrupt" textline " " eventfld.long 0x04 5. " DATA5 ,Pin 5 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 4. " DATA4 ,Pin 4 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 3. " DATA3 ,Pin 3 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 2. " DATA2 ,Pin 2 interrupt status" "No interrupt,Interrupt" textline " " eventfld.long 0x04 1. " DATA1 ,Pin 1 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 0. " DATA0 ,Pin 0 interrupt status" "No interrupt,Interrupt" else rbitfld.long 0x04 24. " PS_FLT_DATA ,Logical state of the filtered pin" "Low,High" rbitfld.long 0x04 21. " PS_DATA5 ,Pin 5 state" "Low,High" rbitfld.long 0x04 19. " PS_DATA3 ,Pin 3 state" "Low,High" rbitfld.long 0x04 18. " PS_DATA2 ,Pin 2 state" "Low,High" textline " " rbitfld.long 0x04 17. " PS_DATA1 ,Pin 1 state" "Low,High" rbitfld.long 0x04 16. " PS_DATA0 ,Pin 0 state" "Low,High" eventfld.long 0x04 8. " FLT_DATA ,Interrupt status of the filtered pin" "No interrupt,Interrupt" eventfld.long 0x04 5. " DATA5 ,Pin 5 interrupt status" "No interrupt,Interrupt" textline " " eventfld.long 0x04 3. " DATA3 ,Pin 3 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 2. " DATA2 ,Pin 2 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 1. " DATA1 ,Pin 1 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 0. " DATA0 ,Pin 0 interrupt status" "No interrupt,Interrupt" endif group.long 0x18++0x03 line.long 0x00 "GPIO_PRT5_PC2,Port 5 Configuration Register 2" bitfld.long 0x00 5. " INP_DIS5 ,Pin 5 input buffer disable" "Enabled,Disabled" sif (cpuis("CY8C424?LTI-L485")||cpuis("CY8C424?LTI-L475")||cpuis("CY8C424?LTI-L445")) bitfld.long 0x00 4. " INP_DIS4 ,Pin 4 input buffer disable" "Enabled,Disabled" endif textline " " bitfld.long 0x00 3. " INP_DIS3 ,Pin 3 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 2. " INP_DIS2 ,Pin 2 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 1. " INP_DIS1 ,Pin 1 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 0. " INP_DIS0 ,Pin 0 input buffer disable" "Enabled,Disabled" group.long 0x40++0x0B line.long 0x00 "GPIO_PRT5_DR_SET,Port 5 Output Data Set Register" bitfld.long 0x00 5. " DATA[5] ,Pin 5 data output set" "No effect,1" sif (cpuis("CY8C424?LTI-L485")||cpuis("CY8C424?LTI-L475")||cpuis("CY8C424?LTI-L445")) bitfld.long 0x00 4. " DATA[4] ,Pin 4 data output set" "No effect,1" endif textline " " bitfld.long 0x00 3. " DATA[3] ,Pin 3 data output set" "No effect,1" bitfld.long 0x00 2. " DATA[2] ,Pin 2 data output set" "No effect,1" bitfld.long 0x00 1. " DATA[1] ,Pin 1 data output set" "No effect,1" bitfld.long 0x00 0. " DATA[0] ,Pin 0 data output set" "No effect,1" line.long 0x04 "GPIO_PRT5_DR_CLR,Port 5 Output Data Clear Register" bitfld.long 0x04 5. " DATA[5] ,Pin 5 data output clear" "No effect,0" sif (cpuis("CY8C424?LTI-L485")||cpuis("CY8C424?LTI-L475")||cpuis("CY8C424?LTI-L445")) bitfld.long 0x04 4. " DATA[4] ,Pin 4 data output clear" "No effect,0" endif textline " " bitfld.long 0x04 3. " DATA[3] ,Pin 3 data output clear" "No effect,0" bitfld.long 0x04 2. " DATA[2] ,Pin 2 data output clear" "No effect,0" bitfld.long 0x04 1. " DATA[1] ,Pin 1 data output clear" "No effect,0" bitfld.long 0x04 0. " DATA[0] ,Pin 0 data output clear" "No effect,0" line.long 0x08 "GPIO_PRT5_DR_INV,Port 5 Output Data Invert Register" bitfld.long 0x08 5. " DATA[5] ,Pin 5 data output invert" "No effect,Inverted" sif (cpuis("CY8C424?LTI-L485")||cpuis("CY8C424?LTI-L475")||cpuis("CY8C424?LTI-L445")) bitfld.long 0x08 4. " DATA[4] ,Pin 4 data output invert" "No effect,Inverted" endif textline " " bitfld.long 0x08 3. " DATA[3] ,Pin 3 data output invert" "No effect,Inverted" bitfld.long 0x08 2. " DATA[2] ,Pin 2 data output invert" "No effect,Inverted" bitfld.long 0x08 1. " DATA[1] ,Pin 1 data output invert" "No effect,Inverted" bitfld.long 0x08 0. " DATA[0] ,Pin 0 data output invert" "No effect,Inverted" width 0x0B tree.end endif tree "PORT 6" base ad:0x40040600 width 23. group.long 0x00++0x03 line.long 0x00 "GPIO_PRT6_DR,Port 6 Output Data Register" sif (cpuis("CY8C4246AZI-L435")||cpuis("CY8C424?AZI-L445")||cpuis("CY8C424?AZI-L475")||cpuis("CY8C424?AZI-L485")) bitfld.long 0x00 5. " DATA5 ,Pin 5 output data" "Low,High" bitfld.long 0x00 3. " DATA3 ,Pin 3 output data" "Low,High" bitfld.long 0x00 2. " DATA2 ,Pin 2 output data" "Low,High" bitfld.long 0x00 1. " DATA1 ,Pin 1 output data" "Low,High" textline " " bitfld.long 0x00 0. " DATA0 ,Pin 0 output data" "Low,High" else bitfld.long 0x00 5. " DATA5 ,Pin 5 output data" "Low,High" bitfld.long 0x00 4. " DATA4 ,Pin 4 output data" "Low,High" bitfld.long 0x00 3. " DATA3 ,Pin 3 output data" "Low,High" bitfld.long 0x00 2. " DATA2 ,Pin 2 output data" "Low,High" textline " " bitfld.long 0x00 1. " DATA1 ,Pin 1 output data" "Low,High" bitfld.long 0x00 0. " DATA0 ,Pin 0 output data" "Low,High" endif rgroup.long 0x04++0x03 line.long 0x00 "GPIO_PRT6_PS,Port 6 IO Pad State Register" sif (cpuis("CY8C4246AZI-L435")||cpuis("CY8C424?AZI-L445")||cpuis("CY8C424?AZI-L475")||cpuis("CY8C424?AZI-L485")) bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High" bitfld.long 0x00 5. " DATA5 ,Pin 5 state" "Low,High" bitfld.long 0x00 4. " DATA4 ,Pin 4 state" "Low,High" bitfld.long 0x00 2. " DATA2 ,Pin 2 state" "Low,High" textline " " bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High" bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High" else bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High" bitfld.long 0x00 5. " DATA5 ,Pin 5 state" "Low,High" bitfld.long 0x00 4. " DATA4 ,Pin 4 state" "Low,High" bitfld.long 0x00 3. " DATA3 ,Pin 3 state" "Low,High" textline " " bitfld.long 0x00 2. " DATA2 ,Pin 2 state" "Low,High" bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High" bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High" endif if (((per.l(ad:0x40040600+0x08))&0x1000000)==0x00) group.long 0x08++0x03 line.long 0x00 "GPIO_PRT6_PC,Port 6 Configuration Register" bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Port 6 input buffer mode select" "CMOS,VCCHIB,CMOS,VCCHIB" bitfld.long 0x00 25. " PORT_SLOW ,Output edge rate of all pins" "Fast,Slow" bitfld.long 0x00 24. " PORT_VTRIP_SEL ,Input buffer function select" "CMOS,LVTTL" bitfld.long 0x00 15.--17. " DM5 ,Pin 5 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " sif (cpuis("CY8C4246AZI-L435")||cpuis("CY8C424?AZI-L445")||cpuis("CY8C424?AZI-L475")||cpuis("CY8C424?AZI-L485")) bitfld.long 0x00 12.--14. " DM4 ,Pin 4 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 6.--8. " DM2 ,Pin 2 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 3.--5. " DM1 ,Pin 1 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 0.--2. " DM0 ,Pin 0 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" else bitfld.long 0x00 12.--14. " DM4 ,Pin 4 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 9.--11. " DM3 ,Pin 3 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 6.--8. " DM2 ,Pin 2 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 3.--5. " DM1 ,Pin 1 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 0.--2. " DM0 ,Pin 0 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" endif else group.long 0x08++0x03 line.long 0x00 "GPIO_PRT6_PC,Port 6 Configuration Register" bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Port 6 input buffer mode select" "LVTTL,VCCHIB,LVTTL,VCCHIB" bitfld.long 0x00 25. " PORT_SLOW ,Output edge rate of all pins" "Fast,Slow" bitfld.long 0x00 24. " PORT_VTRIP_SEL ,Input buffer function select" "CMOS,LVTTL" bitfld.long 0x00 15.--17. " DM5 ,Pin 5 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " sif (cpuis("CY8C4246AZI-L435")||cpuis("CY8C424?AZI-L445")||cpuis("CY8C424?AZI-L475")||cpuis("CY8C424?AZI-L485")) bitfld.long 0x00 12.--14. " DM4 ,Pin 4 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 6.--8. " DM2 ,Pin 2 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 3.--5. " DM1 ,Pin 1 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 0.--2. " DM0 ,Pin 0 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" else bitfld.long 0x00 12.--14. " DM4 ,Pin 4 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 9.--11. " DM3 ,Pin 3 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 6.--8. " DM2 ,Pin 2 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 3.--5. " DM1 ,Pin 1 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 0.--2. " DM0 ,Pin 0 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" endif endif group.long 0x0C++0x07 line.long 0x00 "GPIO_PRT6_INTR_CFG,Port 6 Interrupt Configuration Register" sif (cpuis("CY8C4246AZI-L435")||cpuis("CY8C424?AZI-L445")||cpuis("CY8C424?AZI-L475")||cpuis("CY8C424?AZI-L485")) bitfld.long 0x00 18.--20. " FLT_SEL ,Glitch filter input selection" "0,1,2,,4,5,?..." bitfld.long 0x00 16.--17. " FLT_EDGE_SEL ,Glitch filter input edge selection" "Disabled,Rising,Falling,Both" bitfld.long 0x00 10.--11. " EDGE5_SEL ,Pin 5 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 8.--9. " EDGE4_SEL ,Pin 4 IRQ trigger edge select" "Disabled,Rising,Falling,Both" textline " " bitfld.long 0x00 4.--5. " EDGE2_SEL ,Pin 2 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 2.--3. " EDGE1_SEL ,Pin 1 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 0.--1. " EDGE0_SEL ,Pin 0 IRQ trigger edge select" "Disabled,Rising,Falling,Both" else bitfld.long 0x00 18.--20. " FLT_SEL ,Glitch filter input selection" "0,1,2,3,4,5,?..." bitfld.long 0x00 16.--17. " FLT_EDGE_SEL ,Glitch filter input edge selection" "Disabled,Rising,Falling,Both" bitfld.long 0x00 10.--11. " EDGE5_SEL ,Pin 5 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 8.--9. " EDGE4_SEL ,Pin 4 IRQ trigger edge select" "Disabled,Rising,Falling,Both" textline " " bitfld.long 0x00 6.--7. " EDGE3_SEL ,Pin 3 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 4.--5. " EDGE2_SEL ,Pin 2 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 2.--3. " EDGE1_SEL ,Pin 1 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 0.--1. " EDGE0_SEL ,Pin 0 IRQ trigger edge select" "Disabled,Rising,Falling,Both" endif line.long 0x04 "GPIO_PRT6_INTR,Port 6 Interrupt Status Register" sif (cpuis("CY8C4246AZI-L435")||cpuis("CY8C424?AZI-L445")||cpuis("CY8C424?AZI-L475")||cpuis("CY8C424?AZI-L485")) rbitfld.long 0x04 24. " PS_FLT_DATA ,Logical state of the filtered pin" "Low,High" rbitfld.long 0x04 21. " PS_DATA5 ,Pin 5 state" "Low,High" rbitfld.long 0x04 20. " PS_DATA4 ,Pin 4 state" "Low,High" rbitfld.long 0x04 18. " PS_DATA2 ,Pin 2 state" "Low,High" textline " " rbitfld.long 0x04 17. " PS_DATA1 ,Pin 1 state" "Low,High" rbitfld.long 0x04 16. " PS_DATA0 ,Pin 0 state" "Low,High" eventfld.long 0x04 8. " FLT_DATA ,Interrupt status of the filtered pin" "No interrupt,Interrupt" eventfld.long 0x04 5. " DATA5 ,Pin 5 interrupt status" "No interrupt,Interrupt" textline " " eventfld.long 0x04 4. " DATA4 ,Pin 4 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 2. " DATA2 ,Pin 2 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 1. " DATA1 ,Pin 1 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 0. " DATA0 ,Pin 0 interrupt status" "No interrupt,Interrupt" else rbitfld.long 0x04 24. " PS_FLT_DATA ,Logical state of the filtered pin" "Low,High" rbitfld.long 0x04 21. " PS_DATA5 ,Pin 5 state" "Low,High" rbitfld.long 0x04 20. " PS_DATA4 ,Pin 4 state" "Low,High" rbitfld.long 0x04 19. " PS_DATA3 ,Pin 3 state" "Low,High" textline " " rbitfld.long 0x04 18. " PS_DATA2 ,Pin 2 state" "Low,High" rbitfld.long 0x04 17. " PS_DATA1 ,Pin 1 state" "Low,High" rbitfld.long 0x04 16. " PS_DATA0 ,Pin 0 state" "Low,High" eventfld.long 0x04 8. " FLT_DATA ,Interrupt status of the filtered pin" "No interrupt,Interrupt" textline " " eventfld.long 0x04 5. " DATA5 ,Pin 5 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 4. " DATA4 ,Pin 4 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 3. " DATA3 ,Pin 3 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 2. " DATA2 ,Pin 2 interrupt status" "No interrupt,Interrupt" textline " " eventfld.long 0x04 1. " DATA1 ,Pin 1 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 0. " DATA0 ,Pin 0 interrupt status" "No interrupt,Interrupt" endif group.long 0x18++0x03 line.long 0x00 "GPIO_PRT6_PC2,Port 6 Configuration Register 2" sif (cpuis("CY8C4246AZI-L435")||cpuis("CY8C424?AZI-L445")||cpuis("CY8C424?AZI-L475")||cpuis("CY8C424?AZI-L485")) bitfld.long 0x00 5. " INP_DIS5 ,Pin 5 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 4. " INP_DIS4 ,Pin 4 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 2. " INP_DIS2 ,Pin 2 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 1. " INP_DIS1 ,Pin 1 input buffer disable" "Enabled,Disabled" textline " " bitfld.long 0x00 0. " INP_DIS0 ,Pin 0 input buffer disable" "Enabled,Disabled" else bitfld.long 0x00 5. " INP_DIS5 ,Pin 5 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 4. " INP_DIS4 ,Pin 4 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 3. " INP_DIS3 ,Pin 3 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 2. " INP_DIS2 ,Pin 2 input buffer disable" "Enabled,Disabled" textline " " bitfld.long 0x00 1. " INP_DIS1 ,Pin 1 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 0. " INP_DIS0 ,Pin 0 input buffer disable" "Enabled,Disabled" endif group.long 0x40++0x0B line.long 0x00 "GPIO_PRT6_DR_SET,Port 6 Output Data Set Register" sif (cpuis("CY8C4246AZI-L435")||cpuis("CY8C424?AZI-L445")||cpuis("CY8C424?AZI-L475")||cpuis("CY8C424?AZI-L485")) bitfld.long 0x00 5. " DATA[5] ,Pin 5 data output set" "No effect,1" bitfld.long 0x00 4. " DATA[4] ,Pin 4 data output set" "No effect,1" bitfld.long 0x00 2. " DATA[2] ,Pin 2 data output set" "No effect,1" bitfld.long 0x00 1. " DATA[1] ,Pin 1 data output set" "No effect,1" textline " " bitfld.long 0x00 0. " DATA[0] ,Pin 0 data output set" "No effect,1" else bitfld.long 0x00 5. " DATA[5] ,Pin 5 data output set" "No effect,1" bitfld.long 0x00 4. " DATA[4] ,Pin 4 data output set" "No effect,1" bitfld.long 0x00 3. " DATA[3] ,Pin 3 data output set" "No effect,1" bitfld.long 0x00 2. " DATA[2] ,Pin 2 data output set" "No effect,1" textline " " bitfld.long 0x00 1. " DATA[1] ,Pin 1 data output set" "No effect,1" bitfld.long 0x00 0. " DATA[0] ,Pin 0 data output set" "No effect,1" endif line.long 0x04 "GPIO_PRT6_DR_CLR,Port 6 Output Data Clear Register" sif (cpuis("CY8C4246AZI-L435")||cpuis("CY8C424?AZI-L445")||cpuis("CY8C424?AZI-L475")||cpuis("CY8C424?AZI-L485")) bitfld.long 0x04 5. " DATA[5] ,Pin 5 data output clear" "No effect,0" bitfld.long 0x04 4. " DATA[4] ,Pin 4 data output clear" "No effect,0" bitfld.long 0x04 2. " DATA[2] ,Pin 2 data output clear" "No effect,0" bitfld.long 0x04 1. " DATA[1] ,Pin 1 data output clear" "No effect,0" textline " " bitfld.long 0x04 0. " DATA[0] ,Pin 0 data output clear" "No effect,0" else bitfld.long 0x04 5. " DATA[5] ,Pin 5 data output clear" "No effect,0" bitfld.long 0x04 4. " DATA[4] ,Pin 4 data output clear" "No effect,0" bitfld.long 0x04 3. " DATA[3] ,Pin 3 data output clear" "No effect,0" bitfld.long 0x04 2. " DATA[2] ,Pin 2 data output clear" "No effect,0" textline " " bitfld.long 0x04 1. " DATA[1] ,Pin 1 data output clear" "No effect,0" bitfld.long 0x04 0. " DATA[0] ,Pin 0 data output clear" "No effect,0" endif line.long 0x08 "GPIO_PRT6_DR_INV,Port 6 Output Data Invert Register" sif (cpuis("CY8C4246AZI-L435")||cpuis("CY8C424?AZI-L445")||cpuis("CY8C424?AZI-L475")||cpuis("CY8C424?AZI-L485")) bitfld.long 0x08 5. " DATA[5] ,Pin 5 data output clear" "No effect,Inverted" bitfld.long 0x08 4. " DATA[4] ,Pin 4 data output clear" "No effect,Inverted" bitfld.long 0x08 2. " DATA[2] ,Pin 2 data output clear" "No effect,Inverted" bitfld.long 0x08 1. " DATA[1] ,Pin 1 data output clear" "No effect,Inverted" textline " " bitfld.long 0x08 0. " DATA[0] ,Pin 0 data output clear" "No effect,Inverted" else bitfld.long 0x08 5. " DATA[5] ,Pin 5 data output clear" "No effect,Inverted" bitfld.long 0x08 4. " DATA[4] ,Pin 4 data output clear" "No effect,Inverted" bitfld.long 0x08 3. " DATA[3] ,Pin 3 data output clear" "No effect,Inverted" bitfld.long 0x08 2. " DATA[2] ,Pin 2 data output clear" "No effect,Inverted" textline " " bitfld.long 0x08 1. " DATA[1] ,Pin 1 data output clear" "No effect,Inverted" bitfld.long 0x08 0. " DATA[0] ,Pin 0 data output clear" "No effect,Inverted" endif width 0x0B tree.end endif sif (cpuis("CY8C424?BZI-L489")||cpuis("CY8C424?BZI-L479")) tree "PORT 7" base ad:0x40040700 width 23. group.long 0x00++0x03 line.long 0x00 "GPIO_PRT7_DR,Port 7 Output Data Register" bitfld.long 0x00 7. " DATA7 ,Pin 7 output data" "Low,High" bitfld.long 0x00 6. " DATA6 ,Pin 6 output data" "Low,High" bitfld.long 0x00 5. " DATA5 ,Pin 5 output data" "Low,High" bitfld.long 0x00 4. " DATA4 ,Pin 4 output data" "Low,High" textline " " bitfld.long 0x00 3. " DATA3 ,Pin 3 output data" "Low,High" bitfld.long 0x00 2. " DATA2 ,Pin 2 output data" "Low,High" bitfld.long 0x00 1. " DATA1 ,Pin 1 output data" "Low,High" bitfld.long 0x00 0. " DATA0 ,Pin 0 output data" "Low,High" rgroup.long 0x04++0x03 line.long 0x00 "GPIO_PRT7_PS,Port 7 IO Pad State Register" bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High" bitfld.long 0x00 7. " DATA7 ,Pin 7 state" "Low,High" bitfld.long 0x00 6. " DATA6 ,Pin 6 state" "Low,High" bitfld.long 0x00 5. " DATA5 ,Pin 5 state" "Low,High" textline " " bitfld.long 0x00 4. " DATA4 ,Pin 4 state" "Low,High" bitfld.long 0x00 3. " DATA3 ,Pin 3 state" "Low,High" bitfld.long 0x00 2. " DATA2 ,Pin 2 state" "Low,High" bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High" textline " " bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High" if (((per.l(ad:0x40040700+0x08))&0x1000000)==0x00) group.long 0x08++0x03 line.long 0x00 "GPIO_PRT7_PC,Port 7 Configuration Register" bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Port 7 input buffer mode select" "CMOS,VCCHIB,CMOS,VCCHIB" bitfld.long 0x00 25. " PORT_SLOW ,Output edge rate of all pins" "Fast,Slow" bitfld.long 0x00 24. " PORT_VTRIP_SEL ,Input buffer function select" "CMOS,LVTTL" bitfld.long 0x00 21.--23. " DM7 ,Pin 7 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 18.--20. " DM6 ,Pin 6 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 15.--17. " DM5 ,Pin 5 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 12.--14. " DM4 ,Pin 4 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 9.--11. " DM3 ,Pin 3 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 6.--8. " DM2 ,Pin 2 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 3.--5. " DM1 ,Pin 1 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 0.--2. " DM0 ,Pin 0 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" else group.long 0x08++0x03 line.long 0x00 "GPIO_PRT7_PC,Port 7 Configuration Register" bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Port 7 input buffer mode select" "LVTTL,VCCHIB,LVTTL,VCCHIB" bitfld.long 0x00 25. " PORT_SLOW ,Output edge rate of all pins" "Fast,Slow" bitfld.long 0x00 24. " PORT_VTRIP_SEL ,Input buffer function select" "CMOS,LVTTL" bitfld.long 0x00 21.--23. " DM7 ,Pin 7 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 18.--20. " DM6 ,Pin 6 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 15.--17. " DM5 ,Pin 5 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 12.--14. " DM4 ,Pin 4 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 9.--11. " DM3 ,Pin 3 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 6.--8. " DM2 ,Pin 2 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 3.--5. " DM1 ,Pin 1 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 0.--2. " DM0 ,Pin 0 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" endif group.long 0x0C++0x07 line.long 0x00 "GPIO_PRT7_INTR_CFG,Port 7 Interrupt Configuration Register" bitfld.long 0x00 18.--20. " FLT_SEL ,Glitch filter input selection" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " FLT_EDGE_SEL ,Glitch filter input edge selection" "Disabled,Rising,Falling,Both" bitfld.long 0x00 14.--15. " EDGE7_SEL ,Pin 7 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 12.--13. " EDGE6_SEL ,Pin 6 IRQ trigger edge select" "Disabled,Rising,Falling,Both" textline " " bitfld.long 0x00 10.--11. " EDGE5_SEL ,Pin 5 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 8.--9. " EDGE4_SEL ,Pin 4 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 6.--7. " EDGE3_SEL ,Pin 3 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 4.--5. " EDGE2_SEL ,Pin 2 IRQ trigger edge select" "Disabled,Rising,Falling,Both" textline " " bitfld.long 0x00 2.--3. " EDGE1_SEL ,Pin 1 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 0.--1. " EDGE0_SEL ,Pin 0 IRQ trigger edge select" "Disabled,Rising,Falling,Both" line.long 0x04 "GPIO_PRT7_INTR,Port 7 Interrupt Status Register" rbitfld.long 0x04 24. " PS_FLT_DATA ,Logical state of the filtered pin" "Low,High" rbitfld.long 0x04 23. " PS_DATA7 ,Pin 7 state" "Low,High" rbitfld.long 0x04 22. " PS_DATA6 ,Pin 6 state" "Low,High" rbitfld.long 0x04 21. " PS_DATA5 ,Pin 5 state" "Low,High" textline " " rbitfld.long 0x04 20. " PS_DATA4 ,Pin 4 state" "Low,High" rbitfld.long 0x04 19. " PS_DATA3 ,Pin 3 state" "Low,High" rbitfld.long 0x04 18. " PS_DATA2 ,Pin 2 state" "Low,High" rbitfld.long 0x04 17. " PS_DATA1 ,Pin 1 state" "Low,High" textline " " rbitfld.long 0x04 16. " PS_DATA0 ,Pin 0 state" "Low,High" eventfld.long 0x04 8. " FLT_DATA ,Interrupt status of the filtered pin" "No interrupt,Interrupt" eventfld.long 0x04 7. " DATA7 ,Pin 7 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 6. " DATA6 ,Pin 6 interrupt status" "No interrupt,Interrupt" textline " " eventfld.long 0x04 5. " DATA5 ,Pin 5 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 4. " DATA4 ,Pin 4 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 3. " DATA3 ,Pin 3 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 2. " DATA2 ,Pin 2 interrupt status" "No interrupt,Interrupt" textline " " eventfld.long 0x04 1. " DATA1 ,Pin 1 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 0. " DATA0 ,Pin 0 interrupt status" "No interrupt,Interrupt" group.long 0x18++0x03 line.long 0x00 "GPIO_PRT7_PC2,Port 7 Configuration Register 2" bitfld.long 0x00 7. " INP_DIS7 ,Pin 7 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 6. " INP_DIS6 ,Pin 6 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 5. " INP_DIS5 ,Pin 5 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 4. " INP_DIS4 ,Pin 4 input buffer disable" "Enabled,Disabled" textline " " bitfld.long 0x00 3. " INP_DIS3 ,Pin 3 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 2. " INP_DIS2 ,Pin 2 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 1. " INP_DIS1 ,Pin 1 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 0. " INP_DIS0 ,Pin 0 input buffer disable" "Enabled,Disabled" group.long 0x40++0x0B line.long 0x00 "GPIO_PRT7_DR_SET,Port 7 Output Data Set Register" bitfld.long 0x00 7. " DATA_7 ,Pin 7 data output set" "No effect,1" bitfld.long 0x00 6. " DATA_6 ,Pin 6 data output set" "No effect,1" bitfld.long 0x00 5. " DATA_5 ,Pin 5 data output set" "No effect,1" bitfld.long 0x00 4. " DATA_4 ,Pin 4 data output set" "No effect,1" textline " " bitfld.long 0x00 3. " DATA_3 ,Pin 3 data output set" "No effect,1" bitfld.long 0x00 2. " DATA_2 ,Pin 2 data output set" "No effect,1" bitfld.long 0x00 1. " DATA_1 ,Pin 1 data output set" "No effect,1" bitfld.long 0x00 0. " DATA_0 ,Pin 0 data output set" "No effect,1" line.long 0x04 "GPIO_PRT7_DR_CLR,Port 7 Output Data Clear Register" bitfld.long 0x04 7. " DATA_7 ,Pin 7 data output clear" "No effect,0" bitfld.long 0x04 6. " DATA_6 ,Pin 6 data output clear" "No effect,0" bitfld.long 0x04 5. " DATA_5 ,Pin 5 data output clear" "No effect,0" bitfld.long 0x04 4. " DATA_4 ,Pin 4 data output clear" "No effect,0" textline " " bitfld.long 0x04 3. " DATA_3 ,Pin 3 data output clear" "No effect,0" bitfld.long 0x04 2. " DATA_2 ,Pin 2 data output clear" "No effect,0" bitfld.long 0x04 1. " DATA_1 ,Pin 1 data output clear" "No effect,0" bitfld.long 0x04 0. " DATA_0 ,Pin 0 data output clear" "No effect,0" line.long 0x08 "GPIO_PRT7_DR_INV,Port 7 Output Data Invert Register" bitfld.long 0x08 7. " DATA_7 ,Pin 7 data invert" "No effect,Inverted" bitfld.long 0x08 6. " DATA_6 ,Pin 6 data output invert" "No effect,Inverted" bitfld.long 0x08 5. " DATA_5 ,Pin 5 data output invert" "No effect,Inverted" bitfld.long 0x08 4. " DATA_4 ,Pin 4 data output invert" "No effect,Inverted" textline " " bitfld.long 0x08 3. " DATA_3 ,Pin 3 data output invert" "No effect,Inverted" bitfld.long 0x08 2. " DATA_2 ,Pin 2 data output invert" "No effect,Inverted" bitfld.long 0x08 1. " DATA_1 ,Pin 1 data output invert" "No effect,Inverted" bitfld.long 0x08 0. " DATA_0 ,Pin 0 data output invert" "No effect,Inverted" width 0x0B tree.end else tree "PORT 7" base ad:0x40040700 width 23. group.long 0x00++0x03 line.long 0x00 "GPIO_PRT7_DR,Port 7 Output Data Register" sif (cpuis("CY8C4246AZI-L435")||cpuis("CY8C424?AZI-L445")||cpuis("CY8C424?AZI-L475")||cpuis("CY8C424?AZI-L485")) bitfld.long 0x00 1. " DATA1 ,Pin 1 output data" "Low,High" bitfld.long 0x00 0. " DATA0 ,Pin 0 output data" "Low,High" else bitfld.long 0x00 2. " DATA2 ,Pin 2 output data" "Low,High" bitfld.long 0x00 1. " DATA1 ,Pin 1 output data" "Low,High" bitfld.long 0x00 0. " DATA0 ,Pin 0 output data" "Low,High" endif rgroup.long 0x04++0x03 line.long 0x00 "GPIO_PRT7_PS,Port 7 IO Pad State Register" bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High" textline " " sif (cpuis("CY8C4246AZI-L435")||cpuis("CY8C424?AZI-L445")||cpuis("CY8C424?AZI-L475")||cpuis("CY8C424?AZI-L485")) bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High" bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High" else bitfld.long 0x00 2. " DATA2 ,Pin 2 state" "Low,High" bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High" bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High" endif if (((per.l(ad:0x40040700+0x08))&0x1000000)==0x00) group.long 0x08++0x03 line.long 0x00 "GPIO_PRT7_PC,Port 7 Configuration Register" sif (cpuis("CY8C4246AZI-L435")||cpuis("CY8C424?AZI-L445")||cpuis("CY8C424?AZI-L475")||cpuis("CY8C424?AZI-L485")) bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Port 7 input buffer mode select" "CMOS,VCCHIB,CMOS,VCCHIB" bitfld.long 0x00 25. " PORT_SLOW ,Output edge rate of all pins" "Fast,Slow" bitfld.long 0x00 24. " PORT_VTRIP_SEL ,Input buffer function select" "CMOS,LVTTL" bitfld.long 0x00 3.--5. " DM1 ,Pin 1 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 0.--2. " DM0 ,Pin 0 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" else bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Port 7 input buffer mode select" "CMOS,VCCHIB,CMOS,VCCHIB" bitfld.long 0x00 25. " PORT_SLOW ,Output edge rate of all pins" "Fast,Slow" bitfld.long 0x00 24. " PORT_VTRIP_SEL ,Input buffer function select" "CMOS,LVTTL" bitfld.long 0x00 6.--8. " DM2 ,Pin 2 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 3.--5. " DM1 ,Pin 1 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 0.--2. " DM0 ,Pin 0 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" endif else group.long 0x08++0x03 line.long 0x00 "GPIO_PRT7_PC,Port 7 Configuration Register" sif (cpuis("CY8C4246AZI-L435")||cpuis("CY8C424?AZI-L445")||cpuis("CY8C424?AZI-L475")||cpuis("CY8C424?AZI-L485")) bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Port 7 input buffer mode select" "LVTTL,VCCHIB,LVTTL,VCCHIB" bitfld.long 0x00 25. " PORT_SLOW ,Output edge rate of all pins" "Fast,Slow" bitfld.long 0x00 24. " PORT_VTRIP_SEL ,Input buffer function select" "CMOS,LVTTL" bitfld.long 0x00 3.--5. " DM1 ,Pin 1 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 0.--2. " DM0 ,Pin 0 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" else bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Port 7 input buffer mode select" "LVTTL,VCCHIB,LVTTL,VCCHIB" bitfld.long 0x00 25. " PORT_SLOW ,Output edge rate of all pins" "Fast,Slow" bitfld.long 0x00 24. " PORT_VTRIP_SEL ,Input buffer function select" "CMOS,LVTTL" bitfld.long 0x00 6.--8. " DM2 ,Pin 2 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 3.--5. " DM1 ,Pin 1 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 0.--2. " DM0 ,Pin 0 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" endif endif group.long 0x0C++0x07 line.long 0x00 "GPIO_PRT7_INTR_CFG,Port 7 Interrupt Configuration Register" sif (cpuis("CY8C424?LTI-L445")||cpuis("CY8C424?LTI-L475")||cpuis("CY8C424?LTI-L485")) bitfld.long 0x00 18.--20. " FLT_SEL ,Glitch filter input selection" "0,1,2,?..." bitfld.long 0x00 16.--17. " FLT_EDGE_SEL ,Glitch filter input edge selection" "Disabled,Rising,Falling,Both" bitfld.long 0x00 4.--5. " EDGE2_SEL ,Pin 2 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 2.--3. " EDGE1_SEL ,Pin 1 IRQ trigger edge select" "Disabled,Rising,Falling,Both" textline " " bitfld.long 0x00 0.--1. " EDGE0_SEL ,Pin 0 IRQ trigger edge select" "Disabled,Rising,Falling,Both" else bitfld.long 0x00 18.--20. " FLT_SEL ,Glitch filter input selection" "0,1,?..." bitfld.long 0x00 16.--17. " FLT_EDGE_SEL ,Glitch filter input edge selection" "Disabled,Rising,Falling,Both" bitfld.long 0x00 2.--3. " EDGE1_SEL ,Pin 1 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 0.--1. " EDGE0_SEL ,Pin 0 IRQ trigger edge select" "Disabled,Rising,Falling,Both" endif line.long 0x04 "GPIO_PRT7_INTR,Port 7 Interrupt Status Register" sif (cpuis("CY8C424?LTI-L445")||cpuis("CY8C424?LTI-L475")||cpuis("CY8C424?LTI-L485")) rbitfld.long 0x04 24. " PS_FLT_DATA ,Logical state of the filtered pin" "Low,High" rbitfld.long 0x04 18. " PS_DATA2 ,Pin 2 state" "Low,High" rbitfld.long 0x04 17. " PS_DATA1 ,Pin 1 state" "Low,High" rbitfld.long 0x04 16. " PS_DATA0 ,Pin 0 state" "Low,High" textline " " eventfld.long 0x04 8. " FLT_DATA ,Interrupt status of the filtered pin" "No interrupt,Interrupt" eventfld.long 0x04 2. " DATA2 ,Pin 2 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 1. " DATA1 ,Pin 1 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 0. " DATA0 ,Pin 0 interrupt status" "No interrupt,Interrupt" else rbitfld.long 0x04 24. " PS_FLT_DATA ,Logical state of the filtered pin" "Low,High" rbitfld.long 0x04 17. " PS_DATA1 ,Pin 1 state" "Low,High" rbitfld.long 0x04 16. " PS_DATA0 ,Pin 0 state" "Low,High" eventfld.long 0x04 8. " FLT_DATA ,Interrupt status of the filtered pin" "No interrupt,Interrupt" textline " " eventfld.long 0x04 1. " DATA1 ,Pin 1 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 0. " DATA0 ,Pin 0 interrupt status" "No interrupt,Interrupt" endif group.long 0x18++0x03 line.long 0x00 "GPIO_PRT7_PC2,Port 7 Configuration Register 2" sif (cpuis("CY8C424?LTI-L445")||cpuis("CY8C424?LTI-L475")||cpuis("CY8C424?LTI-L485")) bitfld.long 0x00 2. " INP_DIS2 ,Pin 2 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 1. " INP_DIS1 ,Pin 1 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 0. " INP_DIS0 ,Pin 0 input buffer disable" "Enabled,Disabled" else bitfld.long 0x00 1. " INP_DIS1 ,Pin 1 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 0. " INP_DIS0 ,Pin 0 input buffer disable" "Enabled,Disabled" endif group.long 0x40++0x0B line.long 0x00 "GPIO_PRT7_DR_SET,Port 7 Output Data Set Register" sif (cpuis("CY8C424?LTI-L445")||cpuis("CY8C424?LTI-L475")||cpuis("CY8C424?LTI-L485")) bitfld.long 0x00 2. " DATA[2] ,Pin 2 data output set" "No effect,1" bitfld.long 0x00 1. " DATA[1] ,Pin 1 data output set" "No effect,1" bitfld.long 0x00 0. " DATA[0] ,Pin 0 data output set" "No effect,1" else bitfld.long 0x00 1. " DATA[1] ,Pin 1 data output set" "No effect,1" bitfld.long 0x00 0. " DATA[0] ,Pin 0 data output set" "No effect,1" endif line.long 0x04 "GPIO_PRT7_DR_CLR,Port 7 Output Data Clear Register" sif (cpuis("CY8C424?LTI-L445")||cpuis("CY8C424?LTI-L475")||cpuis("CY8C424?LTI-L485")) bitfld.long 0x04 2. " DATA[2] ,Pin 2 data output clear" "No effect,0" bitfld.long 0x04 1. " DATA[1] ,Pin 1 data output clear" "No effect,0" bitfld.long 0x04 0. " DATA[0] ,Pin 0 data output clear" "No effect,0" else bitfld.long 0x04 1. " DATA[1] ,Pin 1 data output clear" "No effect,0" bitfld.long 0x04 0. " DATA[0] ,Pin 0 data output clear" "No effect,0" endif line.long 0x08 "GPIO_PRT7_DR_INV,Port 7 Output Data Invert Register" sif (cpuis("CY8C424?LTI-L445")||cpuis("CY8C424?LTI-L475")||cpuis("CY8C424?LTI-L485")) bitfld.long 0x08 2. " DATA[2] ,Pin 2 data output clear" "No effect,Inverted" bitfld.long 0x08 1. " DATA[1] ,Pin 1 data output clear" "No effect,Inverted" bitfld.long 0x08 0. " DATA[0] ,Pin 0 data output clear" "No effect,Inverted" else bitfld.long 0x08 1. " DATA[1] ,Pin 1 data output clear" "No effect,Inverted" bitfld.long 0x08 0. " DATA[0] ,Pin 0 data output clear" "No effect,Inverted" endif width 0x0B tree.end endif sif (cpuis("CY8C424?BZI-L489")||cpuis("CY8C424?BZI-L479")) tree "PORT 8" base ad:0x40040800 width 23. group.long 0x00++0x03 line.long 0x00 "GPIO_PRT8_DR,Port 8 Output Data Register" bitfld.long 0x00 7. " DATA7 ,Pin 7 output data" "Low,High" bitfld.long 0x00 6. " DATA6 ,Pin 6 output data" "Low,High" bitfld.long 0x00 5. " DATA5 ,Pin 5 output data" "Low,High" bitfld.long 0x00 4. " DATA4 ,Pin 4 output data" "Low,High" textline " " bitfld.long 0x00 3. " DATA3 ,Pin 3 output data" "Low,High" bitfld.long 0x00 2. " DATA2 ,Pin 2 output data" "Low,High" bitfld.long 0x00 1. " DATA1 ,Pin 1 output data" "Low,High" bitfld.long 0x00 0. " DATA0 ,Pin 0 output data" "Low,High" rgroup.long 0x04++0x03 line.long 0x00 "GPIO_PRT8_PS,Port 8 IO Pad State Register" bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High" bitfld.long 0x00 7. " DATA7 ,Pin 7 state" "Low,High" bitfld.long 0x00 6. " DATA6 ,Pin 6 state" "Low,High" bitfld.long 0x00 5. " DATA5 ,Pin 5 state" "Low,High" textline " " bitfld.long 0x00 4. " DATA4 ,Pin 4 state" "Low,High" bitfld.long 0x00 3. " DATA3 ,Pin 3 state" "Low,High" bitfld.long 0x00 2. " DATA2 ,Pin 2 state" "Low,High" bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High" textline " " bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High" if (((per.l(ad:0x40040800+0x08))&0x1000000)==0x00) group.long 0x08++0x03 line.long 0x00 "GPIO_PRT8_PC,Port 8 Configuration Register" bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Port 8 input buffer mode select" "CMOS,VCCHIB,CMOS,VCCHIB" bitfld.long 0x00 25. " PORT_SLOW ,Output edge rate of all pins" "Fast,Slow" bitfld.long 0x00 24. " PORT_VTRIP_SEL ,Input buffer function select" "CMOS,LVTTL" bitfld.long 0x00 21.--23. " DM7 ,Pin 7 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 18.--20. " DM6 ,Pin 6 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 15.--17. " DM5 ,Pin 5 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 12.--14. " DM4 ,Pin 4 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 9.--11. " DM3 ,Pin 3 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 6.--8. " DM2 ,Pin 2 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 3.--5. " DM1 ,Pin 1 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 0.--2. " DM0 ,Pin 0 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" else group.long 0x08++0x03 line.long 0x00 "GPIO_PRT8_PC,Port 8 Configuration Register" bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Port 8 input buffer mode select" "LVTTL,VCCHIB,LVTTL,VCCHIB" bitfld.long 0x00 25. " PORT_SLOW ,Output edge rate of all pins" "Fast,Slow" bitfld.long 0x00 24. " PORT_VTRIP_SEL ,Input buffer function select" "CMOS,LVTTL" bitfld.long 0x00 21.--23. " DM7 ,Pin 7 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 18.--20. " DM6 ,Pin 6 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 15.--17. " DM5 ,Pin 5 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 12.--14. " DM4 ,Pin 4 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 9.--11. " DM3 ,Pin 3 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 6.--8. " DM2 ,Pin 2 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 3.--5. " DM1 ,Pin 1 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 0.--2. " DM0 ,Pin 0 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" endif group.long 0x0C++0x07 line.long 0x00 "GPIO_PRT8_INTR_CFG,Port 8 Interrupt Configuration Register" bitfld.long 0x00 18.--20. " FLT_SEL ,Glitch filter input selection" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " FLT_EDGE_SEL ,Glitch filter input edge selection" "Disabled,Rising,Falling,Both" bitfld.long 0x00 14.--15. " EDGE7_SEL ,Pin 7 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 12.--13. " EDGE6_SEL ,Pin 6 IRQ trigger edge select" "Disabled,Rising,Falling,Both" textline " " bitfld.long 0x00 10.--11. " EDGE5_SEL ,Pin 5 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 8.--9. " EDGE4_SEL ,Pin 4 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 6.--7. " EDGE3_SEL ,Pin 3 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 4.--5. " EDGE2_SEL ,Pin 2 IRQ trigger edge select" "Disabled,Rising,Falling,Both" textline " " bitfld.long 0x00 2.--3. " EDGE1_SEL ,Pin 1 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 0.--1. " EDGE0_SEL ,Pin 0 IRQ trigger edge select" "Disabled,Rising,Falling,Both" line.long 0x04 "GPIO_PRT8_INTR,Port 8 Interrupt Status Register" rbitfld.long 0x04 24. " PS_FLT_DATA ,Logical state of the filtered pin" "Low,High" rbitfld.long 0x04 23. " PS_DATA7 ,Pin 7 state" "Low,High" rbitfld.long 0x04 22. " PS_DATA6 ,Pin 6 state" "Low,High" rbitfld.long 0x04 21. " PS_DATA5 ,Pin 5 state" "Low,High" textline " " rbitfld.long 0x04 20. " PS_DATA4 ,Pin 4 state" "Low,High" rbitfld.long 0x04 19. " PS_DATA3 ,Pin 3 state" "Low,High" rbitfld.long 0x04 18. " PS_DATA2 ,Pin 2 state" "Low,High" rbitfld.long 0x04 17. " PS_DATA1 ,Pin 1 state" "Low,High" textline " " rbitfld.long 0x04 16. " PS_DATA0 ,Pin 0 state" "Low,High" eventfld.long 0x04 8. " FLT_DATA ,Interrupt status of the filtered pin" "No interrupt,Interrupt" eventfld.long 0x04 7. " DATA7 ,Pin 7 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 6. " DATA6 ,Pin 6 interrupt status" "No interrupt,Interrupt" textline " " eventfld.long 0x04 5. " DATA5 ,Pin 5 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 4. " DATA4 ,Pin 4 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 3. " DATA3 ,Pin 3 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 2. " DATA2 ,Pin 2 interrupt status" "No interrupt,Interrupt" textline " " eventfld.long 0x04 1. " DATA1 ,Pin 1 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 0. " DATA0 ,Pin 0 interrupt status" "No interrupt,Interrupt" group.long 0x18++0x03 line.long 0x00 "GPIO_PRT8_PC2,Port 8 Configuration Register 2" bitfld.long 0x00 7. " INP_DIS7 ,Pin 7 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 6. " INP_DIS6 ,Pin 6 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 5. " INP_DIS5 ,Pin 5 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 4. " INP_DIS4 ,Pin 4 input buffer disable" "Enabled,Disabled" textline " " bitfld.long 0x00 3. " INP_DIS3 ,Pin 3 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 2. " INP_DIS2 ,Pin 2 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 1. " INP_DIS1 ,Pin 1 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 0. " INP_DIS0 ,Pin 0 input buffer disable" "Enabled,Disabled" group.long 0x40++0x0B line.long 0x00 "GPIO_PRT8_DR_SET,Port 8 Output Data Set Register" bitfld.long 0x00 7. " DATA_7 ,Pin 7 data output set" "No effect,1" bitfld.long 0x00 6. " DATA_6 ,Pin 6 data output set" "No effect,1" bitfld.long 0x00 5. " DATA_5 ,Pin 5 data output set" "No effect,1" bitfld.long 0x00 4. " DATA_4 ,Pin 4 data output set" "No effect,1" textline " " bitfld.long 0x00 3. " DATA_3 ,Pin 3 data output set" "No effect,1" bitfld.long 0x00 2. " DATA_2 ,Pin 2 data output set" "No effect,1" bitfld.long 0x00 1. " DATA_1 ,Pin 1 data output set" "No effect,1" bitfld.long 0x00 0. " DATA_0 ,Pin 0 data output set" "No effect,1" line.long 0x04 "GPIO_PRT8_DR_CLR,Port 8 Output Data Clear Register" bitfld.long 0x04 7. " DATA_7 ,Pin 7 data output clear" "No effect,0" bitfld.long 0x04 6. " DATA_6 ,Pin 6 data output clear" "No effect,0" bitfld.long 0x04 5. " DATA_5 ,Pin 5 data output clear" "No effect,0" bitfld.long 0x04 4. " DATA_4 ,Pin 4 data output clear" "No effect,0" textline " " bitfld.long 0x04 3. " DATA_3 ,Pin 3 data output clear" "No effect,0" bitfld.long 0x04 2. " DATA_2 ,Pin 2 data output clear" "No effect,0" bitfld.long 0x04 1. " DATA_1 ,Pin 1 data output clear" "No effect,0" bitfld.long 0x04 0. " DATA_0 ,Pin 0 data output clear" "No effect,0" line.long 0x08 "GPIO_PRT8_DR_INV,Port 8 Output Data Invert Register" bitfld.long 0x08 7. " DATA_7 ,Pin 7 data invert" "No effect,Inverted" bitfld.long 0x08 6. " DATA_6 ,Pin 6 data output invert" "No effect,Inverted" bitfld.long 0x08 5. " DATA_5 ,Pin 5 data output invert" "No effect,Inverted" bitfld.long 0x08 4. " DATA_4 ,Pin 4 data output invert" "No effect,Inverted" textline " " bitfld.long 0x08 3. " DATA_3 ,Pin 3 data output invert" "No effect,Inverted" bitfld.long 0x08 2. " DATA_2 ,Pin 2 data output invert" "No effect,Inverted" bitfld.long 0x08 1. " DATA_1 ,Pin 1 data output invert" "No effect,Inverted" bitfld.long 0x08 0. " DATA_0 ,Pin 0 data output invert" "No effect,Inverted" width 0x0B tree.end tree "PORT 9" base ad:0x40040900 width 23. group.long 0x00++0x03 line.long 0x00 "GPIO_PRT9_DR,Port 9 Output Data Register" bitfld.long 0x00 7. " DATA7 ,Pin 7 output data" "Low,High" bitfld.long 0x00 6. " DATA6 ,Pin 6 output data" "Low,High" bitfld.long 0x00 5. " DATA5 ,Pin 5 output data" "Low,High" bitfld.long 0x00 4. " DATA4 ,Pin 4 output data" "Low,High" textline " " bitfld.long 0x00 3. " DATA3 ,Pin 3 output data" "Low,High" bitfld.long 0x00 2. " DATA2 ,Pin 2 output data" "Low,High" bitfld.long 0x00 1. " DATA1 ,Pin 1 output data" "Low,High" bitfld.long 0x00 0. " DATA0 ,Pin 0 output data" "Low,High" rgroup.long 0x04++0x03 line.long 0x00 "GPIO_PRT9_PS,Port 9 IO Pad State Register" bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High" bitfld.long 0x00 7. " DATA7 ,Pin 7 state" "Low,High" bitfld.long 0x00 6. " DATA6 ,Pin 6 state" "Low,High" bitfld.long 0x00 5. " DATA5 ,Pin 5 state" "Low,High" textline " " bitfld.long 0x00 4. " DATA4 ,Pin 4 state" "Low,High" bitfld.long 0x00 3. " DATA3 ,Pin 3 state" "Low,High" bitfld.long 0x00 2. " DATA2 ,Pin 2 state" "Low,High" bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High" textline " " bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High" if (((per.l(ad:0x40040900+0x08))&0x1000000)==0x00) group.long 0x08++0x03 line.long 0x00 "GPIO_PRT9_PC,Port 9 Configuration Register" bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Port 9 input buffer mode select" "CMOS,VCCHIB,CMOS,VCCHIB" bitfld.long 0x00 25. " PORT_SLOW ,Output edge rate of all pins" "Fast,Slow" bitfld.long 0x00 24. " PORT_VTRIP_SEL ,Input buffer function select" "CMOS,LVTTL" bitfld.long 0x00 21.--23. " DM7 ,Pin 7 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 18.--20. " DM6 ,Pin 6 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 15.--17. " DM5 ,Pin 5 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 12.--14. " DM4 ,Pin 4 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 9.--11. " DM3 ,Pin 3 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 6.--8. " DM2 ,Pin 2 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 3.--5. " DM1 ,Pin 1 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 0.--2. " DM0 ,Pin 0 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" else group.long 0x08++0x03 line.long 0x00 "GPIO_PRT9_PC,Port 9 Configuration Register" bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Port 9 input buffer mode select" "LVTTL,VCCHIB,LVTTL,VCCHIB" bitfld.long 0x00 25. " PORT_SLOW ,Output edge rate of all pins" "Fast,Slow" bitfld.long 0x00 24. " PORT_VTRIP_SEL ,Input buffer function select" "CMOS,LVTTL" bitfld.long 0x00 21.--23. " DM7 ,Pin 7 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 18.--20. " DM6 ,Pin 6 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 15.--17. " DM5 ,Pin 5 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 12.--14. " DM4 ,Pin 4 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 9.--11. " DM3 ,Pin 3 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 6.--8. " DM2 ,Pin 2 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 3.--5. " DM1 ,Pin 1 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 0.--2. " DM0 ,Pin 0 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" endif group.long 0x0C++0x07 line.long 0x00 "GPIO_PRT9_INTR_CFG,Port 9 Interrupt Configuration Register" bitfld.long 0x00 18.--20. " FLT_SEL ,Glitch filter input selection" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " FLT_EDGE_SEL ,Glitch filter input edge selection" "Disabled,Rising,Falling,Both" bitfld.long 0x00 14.--15. " EDGE7_SEL ,Pin 7 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 12.--13. " EDGE6_SEL ,Pin 6 IRQ trigger edge select" "Disabled,Rising,Falling,Both" textline " " bitfld.long 0x00 10.--11. " EDGE5_SEL ,Pin 5 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 8.--9. " EDGE4_SEL ,Pin 4 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 6.--7. " EDGE3_SEL ,Pin 3 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 4.--5. " EDGE2_SEL ,Pin 2 IRQ trigger edge select" "Disabled,Rising,Falling,Both" textline " " bitfld.long 0x00 2.--3. " EDGE1_SEL ,Pin 1 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 0.--1. " EDGE0_SEL ,Pin 0 IRQ trigger edge select" "Disabled,Rising,Falling,Both" line.long 0x04 "GPIO_PRT9_INTR,Port 9 Interrupt Status Register" rbitfld.long 0x04 24. " PS_FLT_DATA ,Logical state of the filtered pin" "Low,High" rbitfld.long 0x04 23. " PS_DATA7 ,Pin 7 state" "Low,High" rbitfld.long 0x04 22. " PS_DATA6 ,Pin 6 state" "Low,High" rbitfld.long 0x04 21. " PS_DATA5 ,Pin 5 state" "Low,High" textline " " rbitfld.long 0x04 20. " PS_DATA4 ,Pin 4 state" "Low,High" rbitfld.long 0x04 19. " PS_DATA3 ,Pin 3 state" "Low,High" rbitfld.long 0x04 18. " PS_DATA2 ,Pin 2 state" "Low,High" rbitfld.long 0x04 17. " PS_DATA1 ,Pin 1 state" "Low,High" textline " " rbitfld.long 0x04 16. " PS_DATA0 ,Pin 0 state" "Low,High" eventfld.long 0x04 8. " FLT_DATA ,Interrupt status of the filtered pin" "No interrupt,Interrupt" eventfld.long 0x04 7. " DATA7 ,Pin 7 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 6. " DATA6 ,Pin 6 interrupt status" "No interrupt,Interrupt" textline " " eventfld.long 0x04 5. " DATA5 ,Pin 5 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 4. " DATA4 ,Pin 4 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 3. " DATA3 ,Pin 3 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 2. " DATA2 ,Pin 2 interrupt status" "No interrupt,Interrupt" textline " " eventfld.long 0x04 1. " DATA1 ,Pin 1 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 0. " DATA0 ,Pin 0 interrupt status" "No interrupt,Interrupt" group.long 0x18++0x03 line.long 0x00 "GPIO_PRT9_PC2,Port 9 Configuration Register 2" bitfld.long 0x00 7. " INP_DIS7 ,Pin 7 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 6. " INP_DIS6 ,Pin 6 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 5. " INP_DIS5 ,Pin 5 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 4. " INP_DIS4 ,Pin 4 input buffer disable" "Enabled,Disabled" textline " " bitfld.long 0x00 3. " INP_DIS3 ,Pin 3 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 2. " INP_DIS2 ,Pin 2 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 1. " INP_DIS1 ,Pin 1 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 0. " INP_DIS0 ,Pin 0 input buffer disable" "Enabled,Disabled" group.long 0x40++0x0B line.long 0x00 "GPIO_PRT9_DR_SET,Port 9 Output Data Set Register" bitfld.long 0x00 7. " DATA_7 ,Pin 7 data output set" "No effect,1" bitfld.long 0x00 6. " DATA_6 ,Pin 6 data output set" "No effect,1" bitfld.long 0x00 5. " DATA_5 ,Pin 5 data output set" "No effect,1" bitfld.long 0x00 4. " DATA_4 ,Pin 4 data output set" "No effect,1" textline " " bitfld.long 0x00 3. " DATA_3 ,Pin 3 data output set" "No effect,1" bitfld.long 0x00 2. " DATA_2 ,Pin 2 data output set" "No effect,1" bitfld.long 0x00 1. " DATA_1 ,Pin 1 data output set" "No effect,1" bitfld.long 0x00 0. " DATA_0 ,Pin 0 data output set" "No effect,1" line.long 0x04 "GPIO_PRT9_DR_CLR,Port 9 Output Data Clear Register" bitfld.long 0x04 7. " DATA_7 ,Pin 7 data output clear" "No effect,0" bitfld.long 0x04 6. " DATA_6 ,Pin 6 data output clear" "No effect,0" bitfld.long 0x04 5. " DATA_5 ,Pin 5 data output clear" "No effect,0" bitfld.long 0x04 4. " DATA_4 ,Pin 4 data output clear" "No effect,0" textline " " bitfld.long 0x04 3. " DATA_3 ,Pin 3 data output clear" "No effect,0" bitfld.long 0x04 2. " DATA_2 ,Pin 2 data output clear" "No effect,0" bitfld.long 0x04 1. " DATA_1 ,Pin 1 data output clear" "No effect,0" bitfld.long 0x04 0. " DATA_0 ,Pin 0 data output clear" "No effect,0" line.long 0x08 "GPIO_PRT9_DR_INV,Port 9 Output Data Invert Register" bitfld.long 0x08 7. " DATA_7 ,Pin 7 data invert" "No effect,Inverted" bitfld.long 0x08 6. " DATA_6 ,Pin 6 data output invert" "No effect,Inverted" bitfld.long 0x08 5. " DATA_5 ,Pin 5 data output invert" "No effect,Inverted" bitfld.long 0x08 4. " DATA_4 ,Pin 4 data output invert" "No effect,Inverted" textline " " bitfld.long 0x08 3. " DATA_3 ,Pin 3 data output invert" "No effect,Inverted" bitfld.long 0x08 2. " DATA_2 ,Pin 2 data output invert" "No effect,Inverted" bitfld.long 0x08 1. " DATA_1 ,Pin 1 data output invert" "No effect,Inverted" bitfld.long 0x08 0. " DATA_0 ,Pin 0 data output invert" "No effect,Inverted" width 0x0B tree.end tree "PORT 10" base ad:0x40040A00 width 23. group.long 0x00++0x03 line.long 0x00 "GPIO_PRT10_DR,Port 10 Output Data Register" bitfld.long 0x00 7. " DATA7 ,Pin 7 output data" "Low,High" bitfld.long 0x00 6. " DATA6 ,Pin 6 output data" "Low,High" bitfld.long 0x00 5. " DATA5 ,Pin 5 output data" "Low,High" bitfld.long 0x00 4. " DATA4 ,Pin 4 output data" "Low,High" textline " " bitfld.long 0x00 3. " DATA3 ,Pin 3 output data" "Low,High" bitfld.long 0x00 2. " DATA2 ,Pin 2 output data" "Low,High" bitfld.long 0x00 1. " DATA1 ,Pin 1 output data" "Low,High" bitfld.long 0x00 0. " DATA0 ,Pin 0 output data" "Low,High" rgroup.long 0x04++0x03 line.long 0x00 "GPIO_PRT10_PS,Port 10 IO Pad State Register" bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High" bitfld.long 0x00 7. " DATA7 ,Pin 7 state" "Low,High" bitfld.long 0x00 6. " DATA6 ,Pin 6 state" "Low,High" bitfld.long 0x00 5. " DATA5 ,Pin 5 state" "Low,High" textline " " bitfld.long 0x00 4. " DATA4 ,Pin 4 state" "Low,High" bitfld.long 0x00 3. " DATA3 ,Pin 3 state" "Low,High" bitfld.long 0x00 2. " DATA2 ,Pin 2 state" "Low,High" bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High" textline " " bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High" if (((per.l(ad:0x40040A00+0x08))&0x1000000)==0x00) group.long 0x08++0x03 line.long 0x00 "GPIO_PRT10_PC,Port 10 Configuration Register" bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Port 10 input buffer mode select" "CMOS,VCCHIB,CMOS,VCCHIB" bitfld.long 0x00 25. " PORT_SLOW ,Output edge rate of all pins" "Fast,Slow" bitfld.long 0x00 24. " PORT_VTRIP_SEL ,Input buffer function select" "CMOS,LVTTL" bitfld.long 0x00 21.--23. " DM7 ,Pin 7 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 18.--20. " DM6 ,Pin 6 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 15.--17. " DM5 ,Pin 5 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 12.--14. " DM4 ,Pin 4 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 9.--11. " DM3 ,Pin 3 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 6.--8. " DM2 ,Pin 2 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 3.--5. " DM1 ,Pin 1 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 0.--2. " DM0 ,Pin 0 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" else group.long 0x08++0x03 line.long 0x00 "GPIO_PRT10_PC,Port 10 Configuration Register" bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Port 10 input buffer mode select" "LVTTL,VCCHIB,LVTTL,VCCHIB" bitfld.long 0x00 25. " PORT_SLOW ,Output edge rate of all pins" "Fast,Slow" bitfld.long 0x00 24. " PORT_VTRIP_SEL ,Input buffer function select" "CMOS,LVTTL" bitfld.long 0x00 21.--23. " DM7 ,Pin 7 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 18.--20. " DM6 ,Pin 6 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 15.--17. " DM5 ,Pin 5 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 12.--14. " DM4 ,Pin 4 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 9.--11. " DM3 ,Pin 3 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 6.--8. " DM2 ,Pin 2 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 3.--5. " DM1 ,Pin 1 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 0.--2. " DM0 ,Pin 0 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" endif group.long 0x0C++0x07 line.long 0x00 "GPIO_PRT10_INTR_CFG,Port 10 Interrupt Configuration Register" bitfld.long 0x00 18.--20. " FLT_SEL ,Glitch filter input selection" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " FLT_EDGE_SEL ,Glitch filter input edge selection" "Disabled,Rising,Falling,Both" bitfld.long 0x00 14.--15. " EDGE7_SEL ,Pin 7 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 12.--13. " EDGE6_SEL ,Pin 6 IRQ trigger edge select" "Disabled,Rising,Falling,Both" textline " " bitfld.long 0x00 10.--11. " EDGE5_SEL ,Pin 5 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 8.--9. " EDGE4_SEL ,Pin 4 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 6.--7. " EDGE3_SEL ,Pin 3 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 4.--5. " EDGE2_SEL ,Pin 2 IRQ trigger edge select" "Disabled,Rising,Falling,Both" textline " " bitfld.long 0x00 2.--3. " EDGE1_SEL ,Pin 1 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 0.--1. " EDGE0_SEL ,Pin 0 IRQ trigger edge select" "Disabled,Rising,Falling,Both" line.long 0x04 "GPIO_PRT10_INTR,Port 10 Interrupt Status Register" rbitfld.long 0x04 24. " PS_FLT_DATA ,Logical state of the filtered pin" "Low,High" rbitfld.long 0x04 23. " PS_DATA7 ,Pin 7 state" "Low,High" rbitfld.long 0x04 22. " PS_DATA6 ,Pin 6 state" "Low,High" rbitfld.long 0x04 21. " PS_DATA5 ,Pin 5 state" "Low,High" textline " " rbitfld.long 0x04 20. " PS_DATA4 ,Pin 4 state" "Low,High" rbitfld.long 0x04 19. " PS_DATA3 ,Pin 3 state" "Low,High" rbitfld.long 0x04 18. " PS_DATA2 ,Pin 2 state" "Low,High" rbitfld.long 0x04 17. " PS_DATA1 ,Pin 1 state" "Low,High" textline " " rbitfld.long 0x04 16. " PS_DATA0 ,Pin 0 state" "Low,High" eventfld.long 0x04 8. " FLT_DATA ,Interrupt status of the filtered pin" "No interrupt,Interrupt" eventfld.long 0x04 7. " DATA7 ,Pin 7 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 6. " DATA6 ,Pin 6 interrupt status" "No interrupt,Interrupt" textline " " eventfld.long 0x04 5. " DATA5 ,Pin 5 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 4. " DATA4 ,Pin 4 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 3. " DATA3 ,Pin 3 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 2. " DATA2 ,Pin 2 interrupt status" "No interrupt,Interrupt" textline " " eventfld.long 0x04 1. " DATA1 ,Pin 1 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 0. " DATA0 ,Pin 0 interrupt status" "No interrupt,Interrupt" group.long 0x18++0x03 line.long 0x00 "GPIO_PRT10_PC2,Port 10 Configuration Register 2" bitfld.long 0x00 7. " INP_DIS7 ,Pin 7 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 6. " INP_DIS6 ,Pin 6 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 5. " INP_DIS5 ,Pin 5 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 4. " INP_DIS4 ,Pin 4 input buffer disable" "Enabled,Disabled" textline " " bitfld.long 0x00 3. " INP_DIS3 ,Pin 3 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 2. " INP_DIS2 ,Pin 2 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 1. " INP_DIS1 ,Pin 1 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 0. " INP_DIS0 ,Pin 0 input buffer disable" "Enabled,Disabled" group.long 0x40++0x0B line.long 0x00 "GPIO_PRT10_DR_SET,Port 10 Output Data Set Register" bitfld.long 0x00 7. " DATA_7 ,Pin 7 data output set" "No effect,1" bitfld.long 0x00 6. " DATA_6 ,Pin 6 data output set" "No effect,1" bitfld.long 0x00 5. " DATA_5 ,Pin 5 data output set" "No effect,1" bitfld.long 0x00 4. " DATA_4 ,Pin 4 data output set" "No effect,1" textline " " bitfld.long 0x00 3. " DATA_3 ,Pin 3 data output set" "No effect,1" bitfld.long 0x00 2. " DATA_2 ,Pin 2 data output set" "No effect,1" bitfld.long 0x00 1. " DATA_1 ,Pin 1 data output set" "No effect,1" bitfld.long 0x00 0. " DATA_0 ,Pin 0 data output set" "No effect,1" line.long 0x04 "GPIO_PRT10_DR_CLR,Port 10 Output Data Clear Register" bitfld.long 0x04 7. " DATA_7 ,Pin 7 data output clear" "No effect,0" bitfld.long 0x04 6. " DATA_6 ,Pin 6 data output clear" "No effect,0" bitfld.long 0x04 5. " DATA_5 ,Pin 5 data output clear" "No effect,0" bitfld.long 0x04 4. " DATA_4 ,Pin 4 data output clear" "No effect,0" textline " " bitfld.long 0x04 3. " DATA_3 ,Pin 3 data output clear" "No effect,0" bitfld.long 0x04 2. " DATA_2 ,Pin 2 data output clear" "No effect,0" bitfld.long 0x04 1. " DATA_1 ,Pin 1 data output clear" "No effect,0" bitfld.long 0x04 0. " DATA_0 ,Pin 0 data output clear" "No effect,0" line.long 0x08 "GPIO_PRT10_DR_INV,Port 10 Output Data Invert Register" bitfld.long 0x08 7. " DATA_7 ,Pin 7 data invert" "No effect,Inverted" bitfld.long 0x08 6. " DATA_6 ,Pin 6 data output invert" "No effect,Inverted" bitfld.long 0x08 5. " DATA_5 ,Pin 5 data output invert" "No effect,Inverted" bitfld.long 0x08 4. " DATA_4 ,Pin 4 data output invert" "No effect,Inverted" textline " " bitfld.long 0x08 3. " DATA_3 ,Pin 3 data output invert" "No effect,Inverted" bitfld.long 0x08 2. " DATA_2 ,Pin 2 data output invert" "No effect,Inverted" bitfld.long 0x08 1. " DATA_1 ,Pin 1 data output invert" "No effect,Inverted" bitfld.long 0x08 0. " DATA_0 ,Pin 0 data output invert" "No effect,Inverted" width 0x0B tree.end tree "PORT 11" base ad:0x40040B00 width 23. group.long 0x00++0x03 line.long 0x00 "GPIO_PRT11_DR,Port 11 Output Data Register" bitfld.long 0x00 7. " DATA7 ,Pin 7 output data" "Low,High" bitfld.long 0x00 6. " DATA6 ,Pin 6 output data" "Low,High" bitfld.long 0x00 5. " DATA5 ,Pin 5 output data" "Low,High" bitfld.long 0x00 4. " DATA4 ,Pin 4 output data" "Low,High" textline " " bitfld.long 0x00 3. " DATA3 ,Pin 3 output data" "Low,High" bitfld.long 0x00 2. " DATA2 ,Pin 2 output data" "Low,High" bitfld.long 0x00 1. " DATA1 ,Pin 1 output data" "Low,High" bitfld.long 0x00 0. " DATA0 ,Pin 0 output data" "Low,High" rgroup.long 0x04++0x03 line.long 0x00 "GPIO_PRT11_PS,Port 11 IO Pad State Register" bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High" bitfld.long 0x00 7. " DATA7 ,Pin 7 state" "Low,High" bitfld.long 0x00 6. " DATA6 ,Pin 6 state" "Low,High" bitfld.long 0x00 5. " DATA5 ,Pin 5 state" "Low,High" textline " " bitfld.long 0x00 4. " DATA4 ,Pin 4 state" "Low,High" bitfld.long 0x00 3. " DATA3 ,Pin 3 state" "Low,High" bitfld.long 0x00 2. " DATA2 ,Pin 2 state" "Low,High" bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High" textline " " bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High" if (((per.l(ad:0x40040B00+0x08))&0x1000000)==0x00) group.long 0x08++0x03 line.long 0x00 "GPIO_PRT11_PC,Port 11 Configuration Register" bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Port 11 input buffer mode select" "CMOS,VCCHIB,CMOS,VCCHIB" bitfld.long 0x00 25. " PORT_SLOW ,Output edge rate of all pins" "Fast,Slow" bitfld.long 0x00 24. " PORT_VTRIP_SEL ,Input buffer function select" "CMOS,LVTTL" bitfld.long 0x00 21.--23. " DM7 ,Pin 7 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 18.--20. " DM6 ,Pin 6 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 15.--17. " DM5 ,Pin 5 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 12.--14. " DM4 ,Pin 4 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 9.--11. " DM3 ,Pin 3 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 6.--8. " DM2 ,Pin 2 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 3.--5. " DM1 ,Pin 1 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 0.--2. " DM0 ,Pin 0 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" else group.long 0x08++0x03 line.long 0x00 "GPIO_PRT11_PC,Port 11 Configuration Register" bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Port 11 input buffer mode select" "LVTTL,VCCHIB,LVTTL,VCCHIB" bitfld.long 0x00 25. " PORT_SLOW ,Output edge rate of all pins" "Fast,Slow" bitfld.long 0x00 24. " PORT_VTRIP_SEL ,Input buffer function select" "CMOS,LVTTL" bitfld.long 0x00 21.--23. " DM7 ,Pin 7 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 18.--20. " DM6 ,Pin 6 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 15.--17. " DM5 ,Pin 5 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 12.--14. " DM4 ,Pin 4 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 9.--11. " DM3 ,Pin 3 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 6.--8. " DM2 ,Pin 2 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 3.--5. " DM1 ,Pin 1 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 0.--2. " DM0 ,Pin 0 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" endif group.long 0x0C++0x07 line.long 0x00 "GPIO_PRT11_INTR_CFG,Port 11 Interrupt Configuration Register" bitfld.long 0x00 18.--20. " FLT_SEL ,Glitch filter input selection" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " FLT_EDGE_SEL ,Glitch filter input edge selection" "Disabled,Rising,Falling,Both" bitfld.long 0x00 14.--15. " EDGE7_SEL ,Pin 7 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 12.--13. " EDGE6_SEL ,Pin 6 IRQ trigger edge select" "Disabled,Rising,Falling,Both" textline " " bitfld.long 0x00 10.--11. " EDGE5_SEL ,Pin 5 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 8.--9. " EDGE4_SEL ,Pin 4 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 6.--7. " EDGE3_SEL ,Pin 3 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 4.--5. " EDGE2_SEL ,Pin 2 IRQ trigger edge select" "Disabled,Rising,Falling,Both" textline " " bitfld.long 0x00 2.--3. " EDGE1_SEL ,Pin 1 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 0.--1. " EDGE0_SEL ,Pin 0 IRQ trigger edge select" "Disabled,Rising,Falling,Both" line.long 0x04 "GPIO_PRT11_INTR,Port 11 Interrupt Status Register" rbitfld.long 0x04 24. " PS_FLT_DATA ,Logical state of the filtered pin" "Low,High" rbitfld.long 0x04 23. " PS_DATA7 ,Pin 7 state" "Low,High" rbitfld.long 0x04 22. " PS_DATA6 ,Pin 6 state" "Low,High" rbitfld.long 0x04 21. " PS_DATA5 ,Pin 5 state" "Low,High" textline " " rbitfld.long 0x04 20. " PS_DATA4 ,Pin 4 state" "Low,High" rbitfld.long 0x04 19. " PS_DATA3 ,Pin 3 state" "Low,High" rbitfld.long 0x04 18. " PS_DATA2 ,Pin 2 state" "Low,High" rbitfld.long 0x04 17. " PS_DATA1 ,Pin 1 state" "Low,High" textline " " rbitfld.long 0x04 16. " PS_DATA0 ,Pin 0 state" "Low,High" eventfld.long 0x04 8. " FLT_DATA ,Interrupt status of the filtered pin" "No interrupt,Interrupt" eventfld.long 0x04 7. " DATA7 ,Pin 7 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 6. " DATA6 ,Pin 6 interrupt status" "No interrupt,Interrupt" textline " " eventfld.long 0x04 5. " DATA5 ,Pin 5 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 4. " DATA4 ,Pin 4 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 3. " DATA3 ,Pin 3 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 2. " DATA2 ,Pin 2 interrupt status" "No interrupt,Interrupt" textline " " eventfld.long 0x04 1. " DATA1 ,Pin 1 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 0. " DATA0 ,Pin 0 interrupt status" "No interrupt,Interrupt" group.long 0x18++0x03 line.long 0x00 "GPIO_PRT11_PC2,Port 11 Configuration Register 2" bitfld.long 0x00 7. " INP_DIS7 ,Pin 7 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 6. " INP_DIS6 ,Pin 6 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 5. " INP_DIS5 ,Pin 5 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 4. " INP_DIS4 ,Pin 4 input buffer disable" "Enabled,Disabled" textline " " bitfld.long 0x00 3. " INP_DIS3 ,Pin 3 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 2. " INP_DIS2 ,Pin 2 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 1. " INP_DIS1 ,Pin 1 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 0. " INP_DIS0 ,Pin 0 input buffer disable" "Enabled,Disabled" group.long 0x40++0x0B line.long 0x00 "GPIO_PRT11_DR_SET,Port 11 Output Data Set Register" bitfld.long 0x00 7. " DATA_7 ,Pin 7 data output set" "No effect,1" bitfld.long 0x00 6. " DATA_6 ,Pin 6 data output set" "No effect,1" bitfld.long 0x00 5. " DATA_5 ,Pin 5 data output set" "No effect,1" bitfld.long 0x00 4. " DATA_4 ,Pin 4 data output set" "No effect,1" textline " " bitfld.long 0x00 3. " DATA_3 ,Pin 3 data output set" "No effect,1" bitfld.long 0x00 2. " DATA_2 ,Pin 2 data output set" "No effect,1" bitfld.long 0x00 1. " DATA_1 ,Pin 1 data output set" "No effect,1" bitfld.long 0x00 0. " DATA_0 ,Pin 0 data output set" "No effect,1" line.long 0x04 "GPIO_PRT11_DR_CLR,Port 11 Output Data Clear Register" bitfld.long 0x04 7. " DATA_7 ,Pin 7 data output clear" "No effect,0" bitfld.long 0x04 6. " DATA_6 ,Pin 6 data output clear" "No effect,0" bitfld.long 0x04 5. " DATA_5 ,Pin 5 data output clear" "No effect,0" bitfld.long 0x04 4. " DATA_4 ,Pin 4 data output clear" "No effect,0" textline " " bitfld.long 0x04 3. " DATA_3 ,Pin 3 data output clear" "No effect,0" bitfld.long 0x04 2. " DATA_2 ,Pin 2 data output clear" "No effect,0" bitfld.long 0x04 1. " DATA_1 ,Pin 1 data output clear" "No effect,0" bitfld.long 0x04 0. " DATA_0 ,Pin 0 data output clear" "No effect,0" line.long 0x08 "GPIO_PRT11_DR_INV,Port 11 Output Data Invert Register" bitfld.long 0x08 7. " DATA_7 ,Pin 7 data invert" "No effect,Inverted" bitfld.long 0x08 6. " DATA_6 ,Pin 6 data output invert" "No effect,Inverted" bitfld.long 0x08 5. " DATA_5 ,Pin 5 data output invert" "No effect,Inverted" bitfld.long 0x08 4. " DATA_4 ,Pin 4 data output invert" "No effect,Inverted" textline " " bitfld.long 0x08 3. " DATA_3 ,Pin 3 data output invert" "No effect,Inverted" bitfld.long 0x08 2. " DATA_2 ,Pin 2 data output invert" "No effect,Inverted" bitfld.long 0x08 1. " DATA_1 ,Pin 1 data output invert" "No effect,Inverted" bitfld.long 0x08 0. " DATA_0 ,Pin 0 data output invert" "No effect,Inverted" width 0x0B tree.end tree "PORT 12" base ad:0x40040C00 width 23. group.long 0x00++0x03 line.long 0x00 "GPIO_PRT12_DR,Port 12 Output Data Register" bitfld.long 0x00 1. " DATA1 ,Pin 1 output data" "Low,High" bitfld.long 0x00 0. " DATA0 ,Pin 0 output data" "Low,High" rgroup.long 0x04++0x03 line.long 0x00 "GPIO_PRT12_PS,Port 12 IO Pad State Register" bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High" bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High" bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High" if (((per.l(ad:0x40040100+0x08))&0x1000000)==0x00) group.long 0x08++0x03 line.long 0x00 "GPIO_PRT12_PC,Port 12 Configuration Register" bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Port 12 input buffer mode select" "CMOS,VCCHIB,CMOS,VCCHIB" bitfld.long 0x00 25. " PORT_SLOW ,Output edge rate of all pins" "Fast,Slow" bitfld.long 0x00 24. " PORT_VTRIP_SEL ,Input buffer function select" "CMOS,LVTTL" bitfld.long 0x00 3.--5. " DM1 ,Pin 1 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 0.--2. " DM0 ,Pin 0 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" else group.long 0x08++0x03 line.long 0x00 "GPIO_PRT12_PC,Port 12 Configuration Register" bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Port 12 input buffer mode select" "LVTTL,VCCHIB,LVTTL,VCCHIB" bitfld.long 0x00 25. " PORT_SLOW ,Output edge rate of all pins" "Fast,Slow" bitfld.long 0x00 24. " PORT_VTRIP_SEL ,Input buffer function select" "CMOS,LVTTL" bitfld.long 0x00 3.--5. " DM1 ,Pin 1 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 0.--2. " DM0 ,Pin 0 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" endif group.long 0x0C++0x07 line.long 0x00 "GPIO_PRT12_INTR_CFG,Port 12 Interrupt Configuration Register" bitfld.long 0x00 18.--20. " FLT_SEL ,Glitch filter input selection" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--17. " FLT_EDGE_SEL ,Glitch filter input edge selection" "Disabled,Rising,Falling,Both" bitfld.long 0x00 2.--3. " EDGE1_SEL ,Pin 1 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 0.--1. " EDGE0_SEL ,Pin 0 IRQ trigger edge select" "Disabled,Rising,Falling,Both" line.long 0x04 "GPIO_PRT12_INTR,Port 12 Interrupt Status Register" rbitfld.long 0x04 24. " PS_FLT_DATA ,Logical state of the filtered pin" "Low,High" rbitfld.long 0x04 17. " PS_DATA1 ,Pin 1 state" "Low,High" rbitfld.long 0x04 16. " PS_DATA0 ,Pin 0 state" "Low,High" eventfld.long 0x04 8. " FLT_DATA ,Interrupt status of the filtered pin" "No interrupt,Interrupt" textline " " eventfld.long 0x04 1. " DATA1 ,Pin 1 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 0. " DATA0 ,Pin 0 interrupt status" "No interrupt,Interrupt" if (((per.l((ad:0x40040100+0x14)))&0x04)==0x00) group.long 0x14++0x03 line.long 0x00 "GPIO_PRT12_SIO,Port SIO Configuration Register" bitfld.long 0x00 5.--7. " PAIR_VOH01_SEL ,Voh output level" "Vref,1.25*Vref,1.49*Vref,1.67*Vref,2.08*Vref,2.5*Vref,2.78*Vref,4.16*Vref" bitfld.long 0x00 3.--4. " PAIR_VREF01_SEL ,Reference voltage select" "1.2V(Vddio as Vref),1.2V,AMUXBUS_A,AMUXBUS_B" bitfld.long 0x00 2. " PAIR_VTRIP01_SEL ,Trip point mode select" "CMOS,LVTTL" bitfld.long 0x00 1. " PAIR_IBUF01_SEL ,Input buffer mode select" "Singled ended,Differential" textline " " bitfld.long 0x00 0. " PAIR_VREG01_EN ,Output buffer mode select" "Unregulated,Regulated" elif (((per.l((ad:0x40040100+0x14)))&0x1C)==0x04) group.long 0x14++0x03 line.long 0x00 "GPIO_PRT12_SIO,Port SIO Configuration Register" bitfld.long 0x00 5.--7. " PAIR_VOH01_SEL ,Voh output level" "Vref,1.25*Vref,1.49*Vref,1.67*Vref,2.08*Vref,2.5*Vref,2.78*Vref,4.16*Vref" bitfld.long 0x00 3.--4. " PAIR_VREF01_SEL ,Reference voltage select" "1.2V(Vddio as Vref),1.2V,AMUXBUS_A,AMUXBUS_B" bitfld.long 0x00 2. " PAIR_VTRIP01_SEL ,Trip point mode" "50% Vddio,40% Vddio" bitfld.long 0x00 1. " PAIR_IBUF01_SEL ,Input buffer mode select" "Singled ended,Differential" textline " " bitfld.long 0x00 0. " PAIR_VREG01_EN ,Output buffer mode select" "Unregulated,Regulated" else group.long 0x14++0x03 line.long 0x00 "GPIO_PRT12_SIO,Port SIO Configuration Register" bitfld.long 0x00 5.--7. " PAIR_VOH01_SEL ,Voh output level" "Vref,1.25*Vref,1.49*Vref,1.67*Vref,2.08*Vref,2.5*Vref,2.78*Vref,4.16*Vref" bitfld.long 0x00 3.--4. " PAIR_VREF01_SEL ,Reference voltage select" "1.2V(Vddio as Vref),1.2V,AMUXBUS_A,AMUXBUS_B" bitfld.long 0x00 2. " PAIR_VTRIP01_SEL ,Trip point mode" "50% Voh_out,Vref" bitfld.long 0x00 1. " PAIR_IBUF01_SEL ,Input buffer mode select" "Singled ended,Differential" textline " " bitfld.long 0x00 0. " PAIR_VREG01_EN ,Output buffer mode select" "Unregulated,Regulated" endif group.long 0x18++0x03 line.long 0x00 "GPIO_PRT12_PC2,Port 12 Configuration Register 2" bitfld.long 0x00 1. " INP_DIS1 ,Pin 1 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 0. " INP_DIS0 ,Pin 0 input buffer disable" "Enabled,Disabled" group.long 0x40++0x0B line.long 0x00 "GPIO_PRT12_DR_SET,Port 12 Output Data Set Register" bitfld.long 0x00 1. " DATA[1] ,Pin 1 data output set" "No effect,1" bitfld.long 0x00 0. " DATA[0] ,Pin 0 data output set" "No effect,1" line.long 0x04 "GPIO_PRT12_DR_CLR,Port 12 Output Data Clear Register" bitfld.long 0x04 1. " DATA[1] ,Pin 1 data output clear" "No effect,0" bitfld.long 0x04 0. " DATA[0] ,Pin 0 data output clear" "No effect,0" line.long 0x08 "GPIO_PRT12_DR_INV,Port 12 Output Data Invert Register" bitfld.long 0x08 1. " DATA[1] ,Pin 1 data output clear" "No effect,Inverted" bitfld.long 0x08 0. " DATA[0] ,Pin 0 data output clear" "No effect,Inverted" width 0x0B tree.end endif sif (!cpuis("CY8C424?AZI-L423")||!cpuis("CY8C424?AZI-L433")) tree "PORT 13" base ad:0x40040D00 width 23. group.long 0x00++0x03 line.long 0x00 "GPIO_PRT13_DR,Port 13 Output Data Register" bitfld.long 0x00 2. " DATA2 ,Pin 2 output data" "Low,High" bitfld.long 0x00 1. " DATA1 ,Pin 1 output data" "Low,High" bitfld.long 0x00 0. " DATA0 ,Pin 0 output data" "Low,High" rgroup.long 0x04++0x03 line.long 0x00 "GPIO_PRT13_PS,Port 13 IO Pad State Register" bitfld.long 0x00 8. " FLT_DATA ,Logical state of the filtered pin" "Low,High" bitfld.long 0x00 2. " DATA2 ,Pin 2 state" "Low,High" bitfld.long 0x00 1. " DATA1 ,Pin 1 state" "Low,High" bitfld.long 0x00 0. " DATA0 ,Pin 0 state" "Low,High" if (((per.l(ad:0x40040D00+0x08))&0x1000000)==0x00) group.long 0x08++0x03 line.long 0x00 "GPIO_PRT13_PC,Port 13 Configuration Register" bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Port 13 input buffer mode select" "CMOS,VCCHIB,CMOS,VCCHIB" bitfld.long 0x00 25. " PORT_SLOW ,Output edge rate of all pins" "Fast,Slow" bitfld.long 0x00 24. " PORT_VTRIP_SEL ,Input buffer function select" "CMOS,LVTTL" bitfld.long 0x00 6.--8. " DM2 ,Pin 2 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 3.--5. " DM1 ,Pin 1 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 0.--2. " DM0 ,Pin 0 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" else group.long 0x08++0x03 line.long 0x00 "GPIO_PRT13_PC,Port 13 Configuration Register" bitfld.long 0x00 30.--31. " PORT_IB_MODE_SEL ,Port 13 input buffer mode select" "LVTTL,VCCHIB,LVTTL,VCCHIB" bitfld.long 0x00 25. " PORT_SLOW ,Output edge rate of all pins" "Fast,Slow" bitfld.long 0x00 24. " PORT_VTRIP_SEL ,Input buffer function select" "CMOS,LVTTL" bitfld.long 0x00 6.--8. " DM2 ,Pin 2 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" textline " " bitfld.long 0x00 3.--5. " DM1 ,Pin 1 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" bitfld.long 0x00 0.--2. " DM0 ,Pin 0 GPIO drive mode" "Off,Input,0_PU,PD_1,0_Z,Z_1,0_1,PD_PU" endif group.long 0x0C++0x07 line.long 0x00 "GPIO_PRT13_INTR_CFG,Port 13 Interrupt Configuration Register" bitfld.long 0x00 18.--20. " FLT_SEL ,Glitch filter input selection" "0,1,2,?..." bitfld.long 0x00 16.--17. " FLT_EDGE_SEL ,Glitch filter input edge selection" "Disabled,Rising,Falling,Both" bitfld.long 0x00 4.--5. " EDGE2_SEL ,Pin 2 IRQ trigger edge select" "Disabled,Rising,Falling,Both" bitfld.long 0x00 2.--3. " EDGE1_SEL ,Pin 1 IRQ trigger edge select" "Disabled,Rising,Falling,Both" textline " " bitfld.long 0x00 0.--1. " EDGE0_SEL ,Pin 0 IRQ trigger edge select" "Disabled,Rising,Falling,Both" line.long 0x04 "GPIO_PRT13_INTR,Port 13 Interrupt Status Register" rbitfld.long 0x04 24. " PS_FLT_DATA ,Logical state of the filtered pin" "Low,High" rbitfld.long 0x04 18. " PS_DATA2 ,Pin 2 state" "Low,High" rbitfld.long 0x04 17. " PS_DATA1 ,Pin 1 state" "Low,High" rbitfld.long 0x04 16. " PS_DATA0 ,Pin 0 state" "Low,High" textline " " eventfld.long 0x04 8. " FLT_DATA ,Interrupt status of the filtered pin" "No interrupt,Interrupt" eventfld.long 0x04 2. " DATA2 ,Pin 2 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 1. " DATA1 ,Pin 1 interrupt status" "No interrupt,Interrupt" eventfld.long 0x04 0. " DATA0 ,Pin 0 interrupt status" "No interrupt,Interrupt" group.long 0x18++0x03 line.long 0x00 "GPIO_PRT13_PC2,Port 13 Configuration Register 2" bitfld.long 0x00 2. " INP_DIS2 ,Pin 2 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 1. " INP_DIS1 ,Pin 1 input buffer disable" "Enabled,Disabled" bitfld.long 0x00 0. " INP_DIS0 ,Pin 0 input buffer disable" "Enabled,Disabled" group.long 0x40++0x0B line.long 0x00 "GPIO_PRT13_DR_SET,Port 13 Output Data Set Register" bitfld.long 0x00 2. " DATA[2] ,Pin 2 data output set" "No effect,1" bitfld.long 0x00 1. " DATA[1] ,Pin 1 data output set" "No effect,1" bitfld.long 0x00 0. " DATA[0] ,Pin 0 data output set" "No effect,1" line.long 0x04 "GPIO_PRT13_DR_CLR,Port 13 Output Data Clear Register" bitfld.long 0x04 2. " DATA[2] ,Pin 2 data output clear" "No effect,0" bitfld.long 0x04 1. " DATA[1] ,Pin 1 data output clear" "No effect,0" bitfld.long 0x04 0. " DATA[0] ,Pin 0 data output clear" "No effect,0" line.long 0x08 "GPIO_PRT13_DR_INV,Port 13 Output Data Invert Register" bitfld.long 0x08 2. " DATA[2] ,Pin 2 data output clear" "No effect,Inverted" bitfld.long 0x08 1. " DATA[1] ,Pin 1 data output clear" "No effect,Inverted" bitfld.long 0x08 0. " DATA[0] ,Pin 0 data output clear" "No effect,Inverted" width 0x0B tree.end endif tree.end tree "HSIOM (High Speed I/O Matrix)" base ad:0x40020000 width 23. tree.open "High Speed I/O Matrix Registers" group.long 0x2100++0x0B line.long 0x00 "HSIOM_AMUX_SPLIT_CTL0,AMUX Splitter Cell Control 0 Register" bitfld.long 0x00 6. " SWITCH_BB_S0 ,T-switch control for AMUXBUSB vssa/ground switch" "Open,Closed" bitfld.long 0x00 5. " SWITCH_BB_SR ,T-switch control for Right AMUXBUSB switch" "Open,Closed" bitfld.long 0x00 4. " SWITCH_BB_SL ,T-switch control for Left AMUXBUSB switch" "Open,Closed" bitfld.long 0x00 2. " SWITCH_AA_S0 ,T-switch control for AMUXBUSA vssa/ground switch" "Open,Closed" textline " " bitfld.long 0x00 1. " SWITCH_AA_SR ,T-switch control for Right AMUXBUSA switch" "Open,Closed" bitfld.long 0x00 0. " SWITCH_AA_SL ,T-switch control for Left AMUXBUSA switch" "Open,Closed" line.long 0x04 "HSIOM_AMUX_SPLIT_CTL1,AMUX Splitter Cell Control 1 Register" bitfld.long 0x04 6. " SWITCH_BB_S0 ,T-switch control for AMUXBUSB vssa/ground switch" "Open,Closed" bitfld.long 0x04 5. " SWITCH_BB_SR ,T-switch control for Right AMUXBUSB switch" "Open,Closed" bitfld.long 0x04 4. " SWITCH_BB_SL ,T-switch control for Left AMUXBUSB switch" "Open,Closed" bitfld.long 0x04 2. " SWITCH_AA_S0 ,T-switch control for AMUXBUSA vssa/ground switch" "Open,Closed" textline " " bitfld.long 0x04 1. " SWITCH_AA_SR ,T-switch control for Right AMUXBUSA switch" "Open,Closed" bitfld.long 0x04 0. " SWITCH_AA_SL ,T-switch control for Left AMUXBUSA switch" "Open,Closed" line.long 0x08 "HSIOM_AMUX_SPLIT_CTL2,AMUX Splitter Cell Control 2 Register" bitfld.long 0x08 6. " SWITCH_BB_S0 ,T-switch control for AMUXBUSB vssa/ground switch" "Open,Closed" bitfld.long 0x08 5. " SWITCH_BB_SR ,T-switch control for Right AMUXBUSB switch" "Open,Closed" bitfld.long 0x08 4. " SWITCH_BB_SL ,T-switch control for Left AMUXBUSB switch" "Open,Closed" bitfld.long 0x08 2. " SWITCH_AA_S0 ,T-switch control for AMUXBUSA vssa/ground switch" "Open,Closed" textline " " bitfld.long 0x08 1. " SWITCH_AA_SR ,T-switch control for Right AMUXBUSA switch" "Open,Closed" bitfld.long 0x08 0. " SWITCH_AA_SL ,T-switch control for Left AMUXBUSA switch" "Open,Closed" tree.end width 18. tree.open "High Speed I/O Port Registers" group.long 0x000++0x03 line.long 0x00 "HSIOM_PORT_SEL0,Port 0 Selection register" bitfld.long 0x00 28.--31. " IO7_SEL ,Pin 7 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,AMUXA,AMUXB,,ACT_1,ACT_2,,LCD_COM,LCD_SEG,DS_2,DS_3" bitfld.long 0x00 24.--27. " IO6_SEL ,Pin 6 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,AMUXA,AMUXB,ACT_0,ACT_1,ACT_2,,LCD_COM,LCD_SEG,,DS_3" bitfld.long 0x00 20.--23. " IO5_SEL ,Pin 5 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,AMUXA,AMUXB,,ACT_1,,,LCD_COM,LCD_SEG,DS_2,DS_3" bitfld.long 0x00 16.--19. " IO4_SEL ,Pin 4 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,AMUXA,AMUXB,,ACT_1,,,LCD_COM,LCD_SEG,DS_2,?..." textline " " bitfld.long 0x00 12.--15. " IO3_SEL ,Pin 3 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,AMUXA,AMUXB,,,,,LCD_COM,LCD_SEG,,DS_3" bitfld.long 0x00 8.--11. " IO2_SEL ,Pin 2 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,AMUXA,AMUXB,,,,,LCD_COM,LCD_SEG,,DS_3" bitfld.long 0x00 4.--7. " IO1_SEL ,Pin 1 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,,,,,,,LCD_COM,LCD_SEG,,DS_3" bitfld.long 0x00 0.--3. " IO0_SEL ,Pin 0 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,,,,,ACT_2,,LCD_COM,LCD_SEG,DS_2,DS_3" group.long 0x100++0x03 line.long 0x00 "HSIOM_PORT_SEL1,Port 1 Selection register" bitfld.long 0x00 28.--31. " IO7_SEL ,Pin 7 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,AMUXA,AMUXB,ACT_0,,,,LCD_COM,LCD_SEG,,DS_3" bitfld.long 0x00 24.--27. " IO6_SEL ,Pin 6 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,AMUXA,AMUXB,ACT_0,,,,LCD_COM,LCD_SEG,,DS_3" bitfld.long 0x00 20.--23. " IO5_SEL ,Pin 5 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,AMUXA,AMUXB,ACT_0,,,,LCD_COM,LCD_SEG,,DS_3" bitfld.long 0x00 16.--19. " IO4_SEL ,Pin 4 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,AMUXA,AMUXB,ACT_0,,,,LCD_COM,LCD_SEG,,DS_3" textline " " bitfld.long 0x00 12.--15. " IO3_SEL ,Pin 3 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,AMUXA,AMUXB,ACT_0,ACT_1,,,LCD_COM,LCD_SEG,,DS_3" bitfld.long 0x00 8.--11. " IO2_SEL ,Pin 2 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,AMUXA,AMUXB,ACT_0,ACT_1,,,LCD_COM,LCD_SEG,,DS_3" bitfld.long 0x00 4.--7. " IO1_SEL ,Pin 1 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,AMUXA,AMUXB,ACT_0,ACT_1,,,LCD_COM,LCD_SEG,DS_2,DS_3" bitfld.long 0x00 0.--3. " IO0_SEL ,Pin 0 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,AMUXA,AMUXB,ACT_0,ACT_1,,,LCD_COM,LCD_SEG,DS_2,?..." group.long 0x200++0x03 line.long 0x00 "HSIOM_PORT_SEL2,Port 2 Selection register" bitfld.long 0x00 28.--31. " IO7_SEL ,Pin 7 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,AMUXA,AMUXB,ACT_0,,,,LCD_COM,LCD_SEG,,DS_3" bitfld.long 0x00 24.--27. " IO6_SEL ,Pin 6 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,AMUXA,AMUXB,ACT_0,,,,LCD_COM,LCD_SEG,,DS_3" bitfld.long 0x00 20.--23. " IO5_SEL ,Pin 5 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,AMUXA,AMUXB,ACT_0,,,,LCD_COM,LCD_SEG,,DS_3" bitfld.long 0x00 16.--19. " IO4_SEL ,Pin 4 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,AMUXA,AMUXB,ACT_0,,,,LCD_COM,LCD_SEG,,DS_3" textline " " bitfld.long 0x00 12.--15. " IO3_SEL ,Pin 3 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,AMUXA,AMUXB,ACT_0,ACT_1,,,LCD_COM,LCD_SEG,,DS_3" bitfld.long 0x00 8.--11. " IO2_SEL ,Pin 2 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,AMUXA,AMUXB,ACT_0,ACT_1,,,LCD_COM,LCD_SEG,,DS_3" bitfld.long 0x00 4.--7. " IO1_SEL ,Pin 1 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,AMUXA,AMUXB,ACT_0,ACT_1,,,LCD_COM,LCD_SEG,DS_2,DS_3" bitfld.long 0x00 0.--3. " IO0_SEL ,Pin 0 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,AMUXA,AMUXB,ACT_0,ACT_1,,,LCD_COM,LCD_SEG,DS_2,?..." group.long 0x300++0x03 line.long 0x00 "HSIOM_PORT_SEL3,Port 3 Selection register" bitfld.long 0x00 28.--31. " IO7_SEL ,Pin 7 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,,,ACT_0,,,,LCD_COM,LCD_SEG,,DS_3" bitfld.long 0x00 24.--27. " IO6_SEL ,Pin 6 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,,,ACT_0,,,,LCD_COM,LCD_SEG,,DS_3" bitfld.long 0x00 20.--23. " IO5_SEL ,Pin 5 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,,,ACT_0,,,,LCD_COM,LCD_SEG,,DS_3" bitfld.long 0x00 16.--19. " IO4_SEL ,Pin 4 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,,,ACT_0,,,,LCD_COM,LCD_SEG,,DS_3" textline " " bitfld.long 0x00 12.--15. " IO3_SEL ,Pin 3 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,,,ACT_0,ACT_1,,,LCD_COM,LCD_SEG,DS_2,DS_3" bitfld.long 0x00 8.--11. " IO2_SEL ,Pin 2 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,,,ACT_0,ACT_1,,,LCD_COM,LCD_SEG,DS_2,DS_3" bitfld.long 0x00 4.--7. " IO1_SEL ,Pin 1 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,,,ACT_0,ACT_1,,,LCD_COM,LCD_SEG,DS_2,DS_3" bitfld.long 0x00 0.--3. " IO0_SEL ,Pin 0 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,,,ACT_0,ACT_1,,,LCD_COM,LCD_SEG,DS_2,?..." group.long 0x400++0x03 line.long 0x00 "HSIOM_PORT_SEL4,Port 4 Selection register" sif (cpuis("CY8C424?BZI-L489")||cpuis("CY8C424?BZI-L479")||cpuis("CY8C424?LTI-L485")||cpuis("CY8C424?LTI-L475")||cpuis("CY8C424?LTI-L445")) bitfld.long 0x00 28.--31. " IO7_SEL ,Pin 7 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,,,,,,,LCD_COM,LCD_SEG,,?..." bitfld.long 0x00 24.--27. " IO6_SEL ,Pin 6 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,,,,,ACT_2,,LCD_COM,LCD_SEG,,DS_3" bitfld.long 0x00 20.--23. " IO5_SEL ,Pin 5 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,,,,,ACT_2,,LCD_COM,LCD_SEG,,DS_3" bitfld.long 0x00 16.--19. " IO4_SEL ,Pin 4 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,,,,,ACT_2,,LCD_COM,LCD_SEG,,DS_3" textline " " bitfld.long 0x00 12.--15. " IO3_SEL ,Pin 3 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,,ACT_1,ACT_2,,LCD_COM,LCD_SEG,DS_2,DS_3" bitfld.long 0x00 8.--11. " IO2_SEL ,Pin 2 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,,ACT_1,ACT_2,,LCD_COM,LCD_SEG,DS_2,DS_3" bitfld.long 0x00 4.--7. " IO1_SEL ,Pin 1 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,,,,ACT_1,ACT_2,,LCD_COM,LCD_SEG,DS_2,DS_3" bitfld.long 0x00 0.--3. " IO0_SEL ,Pin 0 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,,,,ACT_1,ACT_2,,LCD_COM,LCD_SEG,DS_2,DS_3" elif (cpuis("CY8C424?AZI-L485")||cpuis("CY8C424?AZI-L475")||cpuis("CY8C424?AZI-L445")||cpuis("CY8C4246AZI-L435")) bitfld.long 0x00 24.--27. " IO6_SEL ,Pin 6 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,,,,,ACT_2,,LCD_COM,LCD_SEG,,DS_3" bitfld.long 0x00 20.--23. " IO5_SEL ,Pin 5 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,,,,,ACT_2,,LCD_COM,LCD_SEG,,DS_3" bitfld.long 0x00 16.--19. " IO4_SEL ,Pin 4 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,,,,,ACT_2,,LCD_COM,LCD_SEG,,DS_3" bitfld.long 0x00 12.--15. " IO3_SEL ,Pin 3 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,,ACT_1,ACT_2,,LCD_COM,LCD_SEG,DS_2,DS_3" textline " " bitfld.long 0x00 8.--11. " IO2_SEL ,Pin 2 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,,ACT_1,ACT_2,,LCD_COM,LCD_SEG,DS_2,DS_3" bitfld.long 0x00 4.--7. " IO1_SEL ,Pin 1 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,,,,ACT_1,ACT_2,,LCD_COM,LCD_SEG,DS_2,DS_3" bitfld.long 0x00 0.--3. " IO0_SEL ,Pin 0 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,,,,ACT_1,ACT_2,,LCD_COM,LCD_SEG,DS_2,DS_3" else bitfld.long 0x00 12.--15. " IO3_SEL ,Pin 3 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,,ACT_1,ACT_2,,LCD_COM,LCD_SEG,DS_2,DS_3" bitfld.long 0x00 8.--11. " IO2_SEL ,Pin 2 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,,ACT_1,ACT_2,,LCD_COM,LCD_SEG,DS_2,DS_3" bitfld.long 0x00 4.--7. " IO1_SEL ,Pin 1 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,,,,ACT_1,ACT_2,,LCD_COM,LCD_SEG,DS_2,DS_3" bitfld.long 0x00 0.--3. " IO0_SEL ,Pin 0 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,,,,ACT_1,ACT_2,,LCD_COM,LCD_SEG,DS_2,DS_3" endif sif (cpuis("CY8C424?BZI-L489")||cpuis("CY8C424?BZI-L479")) group.long 0x500++0x03 line.long 0x00 "HSIOM_PORT_SEL5,Port 5 Selection Register" bitfld.long 0x00 28.--31. " IO7_SEL ,Pin 7 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,AMUXA,AMUXB,ACT_0,,,,LCD_COM,LCD_SEG,,?..." bitfld.long 0x00 24.--27. " IO6_SEL ,Pin 6 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,AMUXA,AMUXB,ACT_0,,,,LCD_COM,LCD_SEG,,DS_3" bitfld.long 0x00 20.--23. " IO5_SEL ,Pin 5 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,AMUXA,AMUXB,ACT_0,,,,LCD_COM,LCD_SEG,,DS_3" bitfld.long 0x00 16.--19. " IO4_SEL ,Pin 4 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,AMUXA,AMUXB,ACT_0,,,,LCD_COM,LCD_SEG,,DS_3" textline " " bitfld.long 0x00 12.--15. " IO3_SEL ,Pin 3 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,AMUXA,AMUXB,ACT_0,ACT_1,,,LCD_COM,LCD_SEG,DS_2,DS_3" bitfld.long 0x00 8.--11. " IO2_SEL ,Pin 2 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,AMUXA,AMUXB,ACT_0,ACT_1,,,LCD_COM,LCD_SEG,DS_2,DS_3" bitfld.long 0x00 4.--7. " IO1_SEL ,Pin 1 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,,,LCD_COM,LCD_SEG,DS_2,DS_3" bitfld.long 0x00 0.--3. " IO0_SEL ,Pin 0 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,,,LCD_COM,LCD_SEG,DS_2,DS_3" elif (cpuis("CY8C424?AZI-L485")||cpuis("CY8C424?AZI-L475")||cpuis("CY8C424?AZI-L445")||cpuis("CY8C4246AZI-L435")) group.long 0x500++0x03 line.long 0x00 "HSIOM_PORT_SEL5,Port 5 Selection Register" bitfld.long 0x00 20.--23. " IO5_SEL ,Pin 5 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,AMUXA,AMUXB,ACT_0,,,,LCD_COM,LCD_SEG,,DS_3" bitfld.long 0x00 12.--15. " IO3_SEL ,Pin 3 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,AMUXA,AMUXB,ACT_0,ACT_1,,,LCD_COM,LCD_SEG,DS_2,DS_3" bitfld.long 0x00 8.--11. " IO2_SEL ,Pin 2 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,AMUXA,AMUXB,ACT_0,ACT_1,,,LCD_COM,LCD_SEG,DS_2,DS_3" bitfld.long 0x00 4.--7. " IO1_SEL ,Pin 1 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,,,LCD_COM,LCD_SEG,DS_2,DS_3" textline " " bitfld.long 0x00 0.--3. " IO0_SEL ,Pin 0 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,,,LCD_COM,LCD_SEG,DS_2,DS_3" elif (cpuis("CY8C424?LTI-L485")||cpuis("CY8C424?LTI-L475")||cpuis("CY8C424?LTI-L445")) group.long 0x500++0x03 line.long 0x00 "HSIOM_PORT_SEL5,Port 5 Selection Register" bitfld.long 0x00 20.--23. " IO5_SEL ,Pin 5 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,AMUXA,AMUXB,ACT_0,,,,LCD_COM,LCD_SEG,,DS_3" bitfld.long 0x00 16.--19. " IO4_SEL ,Pin 4 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,AMUXA,AMUXB,ACT_0,,,,LCD_COM,LCD_SEG,,DS_3" bitfld.long 0x00 12.--15. " IO3_SEL ,Pin 3 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,AMUXA,AMUXB,ACT_0,ACT_1,,,LCD_COM,LCD_SEG,DS_2,DS_3" bitfld.long 0x00 8.--11. " IO2_SEL ,Pin 2 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,AMUXA,AMUXB,ACT_0,ACT_1,,,LCD_COM,LCD_SEG,DS_2,DS_3" textline " " bitfld.long 0x00 4.--7. " IO1_SEL ,Pin 1 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,,,LCD_COM,LCD_SEG,DS_2,DS_3" bitfld.long 0x00 0.--3. " IO0_SEL ,Pin 0 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,CSD_SENSE,CSD_SHIELD,AMUXA,AMUXB,ACT_0,ACT_1,,,LCD_COM,LCD_SEG,DS_2,DS_3" endif sif (cpuis("CY8C424?BZI-L489")||cpuis("CY8C424?BZI-L479")||cpuis("CY8C424?LTI-L485")||cpuis("CY8C424?LTI-L475")||cpuis("CY8C424?LTI-L445")) group.long 0x600++0x03 line.long 0x00 "HSIOM_PORT_SEL6,Port 6 Selection Register" bitfld.long 0x00 20.--23. " IO5_SEL ,Pin 5 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,,,ACT_0,,,,LCD_COM,LCD_SEG,DS_2,DS_3" bitfld.long 0x00 16.--19. " IO4_SEL ,Pin 4 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,,,ACT_0,,,,LCD_COM,LCD_SEG,DS_2,DS_3" bitfld.long 0x00 12.--15. " IO3_SEL ,Pin 3 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,,,ACT_0,ACT_1,,,LCD_COM,LCD_SEG,DS_2,DS_3" bitfld.long 0x00 8.--11. " IO2_SEL ,Pin 2 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,,,ACT_0,ACT_1,ACT_2,,LCD_COM,LCD_SEG,DS_2,DS_3" textline " " bitfld.long 0x00 4.--7. " IO1_SEL ,Pin 1 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,,,ACT_0,ACT_1,ACT_2,,LCD_COM,LCD_SEG,DS_2,DS_3" bitfld.long 0x00 0.--3. " IO0_SEL ,Pin 0 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,,,ACT_0,ACT_1,ACT_2,,LCD_COM,LCD_SEG,DS_2,DS_3" elif (cpuis("CY8C424?AZI-L485")||cpuis("CY8C424?AZI-L475")||cpuis("CY8C424?AZI-L445")||cpuis("CY8C4246AZI-L435")) group.long 0x600++0x03 line.long 0x00 "HSIOM_PORT_SEL6,Port 6 Selection Register" bitfld.long 0x00 28.--31. " IO7_SEL ,Pin 7 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,,,ACT_0,,,,LCD_COM,LCD_SEG,DS_2,DS_3" bitfld.long 0x00 24.--27. " IO6_SEL ,Pin 6 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,,,ACT_0,,,,LCD_COM,LCD_SEG,DS_2,DS_3" bitfld.long 0x00 20.--23. " IO5_SEL ,Pin 5 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,,,ACT_0,,,,LCD_COM,LCD_SEG,DS_2,DS_3" bitfld.long 0x00 16.--19. " IO4_SEL ,Pin 4 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,,,ACT_0,,,,LCD_COM,LCD_SEG,DS_2,DS_3" textline " " bitfld.long 0x00 8.--11. " IO2_SEL ,Pin 2 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,,,ACT_0,ACT_1,ACT_2,,LCD_COM,LCD_SEG,DS_2,DS_3" bitfld.long 0x00 4.--7. " IO1_SEL ,Pin 1 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,,,ACT_0,ACT_1,ACT_2,,LCD_COM,LCD_SEG,DS_2,DS_3" bitfld.long 0x00 0.--3. " IO0_SEL ,Pin 0 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,,,ACT_0,ACT_1,ACT_2,,LCD_COM,LCD_SEG,DS_2,DS_3" endif group.long 0x700++0x03 line.long 0x00 "HSIOM_PORT_SEL7,Port 7 Selection Register" sif (cpuis("CY8C424?AZI-L423")||cpuis("CY8C424?AZI-L433")||cpuis("CY8C424?AZI-L485")||cpuis("CY8C424?AZI-L475")||cpuis("CY8C424?AZI-L445")) bitfld.long 0x00 4.--7. " IO1_SEL ,Pin 1 connection select" "GPIO,,,,,,AMUXA,AMUXB,ACT_0,ACT_1,,,LCD_COM,LCD_SEG,DS_2,DS_3" bitfld.long 0x00 0.--3. " IO0_SEL ,Pin 0 connection select" "GPIO,,,,,,AMUXA,AMUXB,ACT_0,ACT_1,,,LCD_COM,LCD_SEG,DS_2,DS_3" elif (cpuis("CY8C424?LTI-L485")||cpuis("CY8C424?LTI-L475")||cpuis("CY8C424?LTI-L445")) bitfld.long 0x00 8.--11. " IO2_SEL ,Pin 2 connection select" "GPIO,,,,,,,,ACT_0,ACT_1,,,LCD_COM,LCD_SEG,,DS_3" bitfld.long 0x00 4.--7. " IO1_SEL ,Pin 1 connection select" "GPIO,,,,,,AMUXA,AMUXB,ACT_0,ACT_1,,,LCD_COM,LCD_SEG,DS_2,DS_3" bitfld.long 0x00 0.--3. " IO0_SEL ,Pin 0 connection select" "GPIO,,,,,,AMUXA,AMUXB,ACT_0,ACT_1,,,LCD_COM,LCD_SEG,DS_2,DS_3" else bitfld.long 0x00 28.--31. " IO7_SEL ,Pin 7 connection select" "GPIO,,,,,,,,ACT_0,,,,LCD_COM,LCD_SEG,,?..." bitfld.long 0x00 24.--27. " IO6_SEL ,Pin 6 connection select" "GPIO,,,,,,,,ACT_0,,,,LCD_COM,LCD_SEG,,DS_3" bitfld.long 0x00 20.--23. " IO5_SEL ,Pin 5 connection select" "GPIO,,,,,,,,ACT_0,,,,LCD_COM,LCD_SEG,,DS_3" bitfld.long 0x00 16.--19. " IO4_SEL ,Pin 4 connection select" "GPIO,,,,,,,,ACT_0,,,,LCD_COM,LCD_SEG,,DS_3" textline " " bitfld.long 0x00 12.--15. " IO3_SEL ,Pin 3 connection select" "GPIO,,,,,,,,ACT_0,ACT_1,,,LCD_COM,LCD_SEG,,DS_3" bitfld.long 0x00 8.--11. " IO2_SEL ,Pin 2 connection select" "GPIO,,,,,,,,ACT_0,ACT_1,,,LCD_COM,LCD_SEG,,DS_3" bitfld.long 0x00 4.--7. " IO1_SEL ,Pin 1 connection select" "GPIO,,,,,,AMUXA,AMUXB,ACT_0,ACT_1,,,LCD_COM,LCD_SEG,DS_2,DS_3" bitfld.long 0x00 0.--3. " IO0_SEL ,Pin 0 connection select" "GPIO,,,,,,AMUXA,AMUXB,ACT_0,ACT_1,,,LCD_COM,LCD_SEG,DS_2,DS_3" endif sif (cpuis("CY8C424?BZI-L489")||cpuis("CY8C424?BZI-L479")) group.long 0x800++0x03 line.long 0x00 "HSIOM_PORT_SEL8,Port 8 Selection Register" bitfld.long 0x00 28.--31. " IO7_SEL ,Pin 7 connection select" "GPIO,,,,,,,,,,,,LCD_COM,LCD_SEG,,?..." bitfld.long 0x00 24.--27. " IO6_SEL ,Pin 6 connection select" "GPIO,,,,,,,,,,,,LCD_COM,LCD_SEG,,DS_3" bitfld.long 0x00 20.--23. " IO5_SEL ,Pin 5 connection select" "GPIO,,,,,,,,,,,,LCD_COM,LCD_SEG,,DS_3" bitfld.long 0x00 16.--19. " IO4_SEL ,Pin 4 connection select" "GPIO,,,,,,,,,,,,LCD_COM,LCD_SEG,,DS_3" textline " " bitfld.long 0x00 12.--15. " IO3_SEL ,Pin 3 connection select" "GPIO,,,,,,,,,ACT_1,,,LCD_COM,LCD_SEG,DS_2,DS_3" bitfld.long 0x00 8.--11. " IO2_SEL ,Pin 2 connection select" "GPIO,,,,,,,,,ACT_1,,,LCD_COM,LCD_SEG,DS_2,DS_3" bitfld.long 0x00 4.--7. " IO1_SEL ,Pin 1 connection select" "GPIO,,,,,,,,,ACT_1,,,LCD_COM,LCD_SEG,DS_2,DS_3" bitfld.long 0x00 0.--3. " IO0_SEL ,Pin 0 connection select" "GPIO,,,,,,,,,ACT_1,,,LCD_COM,LCD_SEG,DS_2,DS_3" group.long 0x900++0x03 line.long 0x00 "HSIOM_PORT_SEL9,Port 9 Selection Register" bitfld.long 0x00 28.--31. " IO7_SEL ,Pin 7 connection select" "GPIO,,,,,,,,ACT_0,,,,LCD_COM,LCD_SEG,DS_2,?..." bitfld.long 0x00 24.--27. " IO6_SEL ,Pin 6 connection select" "GPIO,,,,,,,,ACT_0,,,,LCD_COM,LCD_SEG,DS_2,DS_3" bitfld.long 0x00 20.--23. " IO5_SEL ,Pin 5 connection select" "GPIO,,,,,,,,ACT_0,,,,LCD_COM,LCD_SEG,,DS_3" bitfld.long 0x00 16.--19. " IO4_SEL ,Pin 4 connection select" "GPIO,,,,,,,,ACT_0,,,,LCD_COM,LCD_SEG,,DS_3" textline " " bitfld.long 0x00 12.--15. " IO3_SEL ,Pin 3 connection select" "GPIO,,,,,,,,ACT_0,ACT_1,,,LCD_COM,LCD_SEG,,DS_3" bitfld.long 0x00 8.--11. " IO2_SEL ,Pin 2 connection select" "GPIO,,,,,,,,ACT_0,ACT_1,,,LCD_COM,LCD_SEG,,DS_3" bitfld.long 0x00 4.--7. " IO1_SEL ,Pin 1 connection select" "GPIO,,,,,,,,ACT_0,ACT_1,,,LCD_COM,LCD_SEG,DS_2,DS_3" bitfld.long 0x00 0.--3. " IO0_SEL ,Pin 0 connection select" "GPIO,,,,,,,,ACT_0,ACT_1,,,LCD_COM,LCD_SEG,DS_2,DS_3" group.long 0xA00++0x03 line.long 0x00 "HSIOM_PORT_SEL10,Port 10 Selection Register" bitfld.long 0x00 28.--31. " IO7_SEL ,Pin 7 connection select" "GPIO,,,,,,,,,,,,LCD_COM,LCD_SEG,,?..." bitfld.long 0x00 24.--27. " IO6_SEL ,Pin 6 connection select" "GPIO,,,,,,,,,,,,LCD_COM,LCD_SEG,,DS_3" bitfld.long 0x00 20.--23. " IO5_SEL ,Pin 5 connection select" "GPIO,,,,,,,,,,,,LCD_COM,LCD_SEG,,DS_3" bitfld.long 0x00 16.--19. " IO4_SEL ,Pin 4 connection select" "GPIO,,,,,,,,,,,,LCD_COM,LCD_SEG,,DS_3" textline " " bitfld.long 0x00 12.--15. " IO3_SEL ,Pin 3 connection select" "GPIO,,,,,,,,,ACT_1,,,LCD_COM,LCD_SEG,,DS_3" bitfld.long 0x00 8.--11. " IO2_SEL ,Pin 2 connection select" "GPIO,,,,,,,,,ACT_1,,,LCD_COM,LCD_SEG,,DS_3" bitfld.long 0x00 4.--7. " IO1_SEL ,Pin 1 connection select" "GPIO,,,,,,,,,ACT_1,,,LCD_COM,LCD_SEG,DS_2,DS_3" bitfld.long 0x00 0.--3. " IO0_SEL ,Pin 0 connection select" "GPIO,,,,,,,,,ACT_1,,,LCD_COM,LCD_SEG,DS_2,DS_3" group.long 0xB00++0x03 line.long 0x00 "HSIOM_PORT_SEL11,Port 11 Selection Register" bitfld.long 0x00 28.--31. " IO7_SEL ,Pin 7 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,,,ACT_0,,,,LCD_COM,LCD_SEG,,?..." bitfld.long 0x00 24.--27. " IO6_SEL ,Pin 6 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,,,ACT_0,,,,LCD_COM,LCD_SEG,,DS_3" bitfld.long 0x00 20.--23. " IO5_SEL ,Pin 5 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,,,ACT_0,,,,LCD_COM,LCD_SEG,,DS_3" bitfld.long 0x00 16.--19. " IO4_SEL ,Pin 4 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,,,ACT_0,,,,LCD_COM,LCD_SEG,,DS_3" textline " " bitfld.long 0x00 12.--15. " IO3_SEL ,Pin 3 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,,,ACT_0,ACT_1,,,LCD_COM,LCD_SEG,DS_2,DS_3" bitfld.long 0x00 8.--11. " IO2_SEL ,Pin 2 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,,,ACT_0,ACT_1,,,LCD_COM,LCD_SEG,DS_2,DS_3" bitfld.long 0x00 4.--7. " IO1_SEL ,Pin 1 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,,,ACT_0,ACT_1,,,LCD_COM,LCD_SEG,DS_2,DS_3" bitfld.long 0x00 0.--3. " IO0_SEL ,Pin 0 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,,,ACT_0,ACT_1,,,LCD_COM,LCD_SEG,DS_2,DS_3" group.long 0xC00++0x03 line.long 0x00 "HSIOM_PORT_SEL12,Port 12 Selection Register" bitfld.long 0x00 4.--7. " IO1_SEL ,Pin 1 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,,,ACT_0,,,,LCD_COM,LCD_SEG,DS_2,?..." bitfld.long 0x00 0.--3. " IO0_SEL ,Pin 0 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,,,ACT_0,,,,LCD_COM,LCD_SEG,DS_2,DS_3" endif sif (!cpuis("CY8C424?AZI-L423")||!cpuis("CY8C424?AZI-L433")) group.long 0xD00++0x03 line.long 0x00 "HSIOM_PORT_SEL13,Port 13 Selection Register" bitfld.long 0x00 8.--11. " IO2_SEL ,Pin 2 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,,,,,,,LCD_COM,LCD_SEG,,?..." bitfld.long 0x00 4.--7. " IO1_SEL ,Pin 1 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,,,,,,,LCD_COM,LCD_SEG,,?..." bitfld.long 0x00 0.--3. " IO0_SEL ,Pin 0 connection select" "GPIO,GPIO_DSI,DSI_DSI,DSI_GPIO,,,,,,,,,LCD_COM,LCD_SEG,,?..." endif tree.end width 0x0B tree.end sif (cpuis("*-L423")||cpuis("*-L445")||cpuis("*-L485")||cpuis("*-L489")) tree "LCD" base ad:0x402A0000 width 13. rgroup.long 0x00++0x03 line.long 0x00 "LCD_ID,LCD ID & Revision Register" hexmask.long.word 0x00 16.--31. 1. " REVISION ,Version number" hexmask.long.word 0x00 0.--15. 1. " ID ,ID of LCD controller peripheral" group.long 0x04++0x07 line.long 0x00 "LCD_DIVIDER,LCD Divider Register" hexmask.long.word 0x00 16.--31. 1. " DEAD_DIV ,Dead time period in cycles length" hexmask.long.word 0x00 0.--15. 1. " SUBFR_DIV ,Input clock frequency divide value" line.long 0x04 "LCD_CONTROL,LCD Configuration Register" rbitfld.long 0x04 31. " LS_EN_STAT ,LS status bit enable" "Disabled,Enabled" bitfld.long 0x04 8.--11. " COM_NUM ,Number of COM connections" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." bitfld.long 0x04 5.--6. " BIAS ,PWM bias selection" "HALF,THIRD,FOURTH,FIFTH" bitfld.long 0x04 4. " OP_MODE ,Driving mode configuration" "PWM,Digital correlation" textline " " bitfld.long 0x04 3. " TYPE ,LCD driving waveform type configuration" "TYPE_A,TYPE_B" bitfld.long 0x04 2. " LCD_MODE ,HS/LS Mode selection" "LS,HS" bitfld.long 0x04 1. " HS_EN ,High speed generator enable" "Disabled,Enabled" bitfld.long 0x04 0. " LS_EN ,Low speed generator enable" "Disabled,Enabled" group.long 0x100++0x03 line.long 0x00 "LCD_DATA00,LCD Pin 0 Data Registers" group.long 0x104++0x03 line.long 0x00 "LCD_DATA01,LCD Pin 1 Data Registers" group.long 0x108++0x03 line.long 0x00 "LCD_DATA02,LCD Pin 2 Data Registers" group.long 0x10C++0x03 line.long 0x00 "LCD_DATA03,LCD Pin 3 Data Registers" group.long 0x110++0x03 line.long 0x00 "LCD_DATA04,LCD Pin 4 Data Registers" group.long 0x114++0x03 line.long 0x00 "LCD_DATA05,LCD Pin 5 Data Registers" group.long 0x118++0x03 line.long 0x00 "LCD_DATA06,LCD Pin 6 Data Registers" group.long 0x11C++0x03 line.long 0x00 "LCD_DATA07,LCD Pin 7 Data Registers" group.long 0x120++0x03 line.long 0x00 "LCD_DATA08,LCD Pin 8 Data Registers" group.long 0x124++0x03 line.long 0x00 "LCD_DATA09,LCD Pin 9 Data Registers" group.long 0x128++0x03 line.long 0x00 "LCD_DATA10,LCD Pin 10 Data Registers" group.long 0x12C++0x03 line.long 0x00 "LCD_DATA11,LCD Pin 11 Data Registers" group.long 0x130++0x03 line.long 0x00 "LCD_DATA12,LCD Pin 12 Data Registers" group.long 0x134++0x03 line.long 0x00 "LCD_DATA13,LCD Pin 13 Data Registers" group.long 0x138++0x03 line.long 0x00 "LCD_DATA14,LCD Pin 14 Data Registers" group.long 0x13C++0x03 line.long 0x00 "LCD_DATA15,LCD Pin 15 Data Registers" group.long 0x140++0x03 line.long 0x00 "LCD_DATA16,LCD Pin 16 Data Registers" group.long 0x144++0x03 line.long 0x00 "LCD_DATA17,LCD Pin 17 Data Registers" width 0x0B tree.end endif tree "LPCOMP (Low Power Comparator)" base ad:0x402B0000 width 27. rgroup.long 0x00++0x03 line.long 0x00 "LPCOMP_ID,ID & Revision" hexmask.long.word 0x00 16.--31. 1. " REVISION ,Version number" hexmask.long.word 0x00 0.--15. 1. " ID ,ID of LPCOMP" group.long 0x04++0x03 line.long 0x00 "LPCOMP_CONFIG,LPCOMP Configuration Register" bitfld.long 0x00 21. " DSI_LEVEL2 ,Opamp2 comparator DSI (trigger) out level" "Pulse,Level" bitfld.long 0x00 20. " DSI_BYPASS2 ,Opamp2 bypass comparator output synchronization for DSI output" "Synchronized,Bypassed" bitfld.long 0x00 17. " DSI_LEVEL1 ,Opamp1 comparator DSI (trigger) out level" "Pulse,Level" bitfld.long 0x00 16. " DSI_BYPASS1 ,Opamp1 bypass comparator output synchronization for DSI output" "Synchronized,Bypassed" textline " " bitfld.long 0x00 15. " ENABLE2 ,Comparator 2 enable" "Disabled,Enabled" rbitfld.long 0x00 14. " OUT2 ,Current output value of the comparator 2" "0,1" bitfld.long 0x00 12.--13. " INTTYPE2 ,Comparator 2 IRQ trigger edge set" "DISABLE,RISING,FALLING,BOTH" bitfld.long 0x00 10. " HYST2 ,Comparator 2 10mV hysteresis enable" "Enabled,Disabled" textline " " bitfld.long 0x00 8.--9. " MODE2 ,Comparator 2 operating mode" "SLOW,FAST,ULP,?..." bitfld.long 0x00 7. " ENABLE1 ,Comparator 1 enable" "Disabled,Enabled" rbitfld.long 0x00 6. " OUT1 ,Current output value of the comparator 1" "0,1" bitfld.long 0x00 4.--5. " INTTYPE1 ,Comparator 1 IRQ trigger edge set" "DISABLE,RISING,FALLING,BOTH" textline " " bitfld.long 0x00 2. " HYST1 ,Comparator 1 10mV hysteresis enable" "Enabled,Disabled" bitfld.long 0x00 0.--1. " MODE1 ,Comparator 1 operating mode" "SLOW,FAST,ULP,?..." group.long 0x10++0x03 line.long 0x00 "LPCOMP_INTR_set/clr,LPCOMP Interrupt Request Register" setclrfld.long 0x00 1. 0x04 1. 0x00 1. " COMP2 ,Comparator 2 Interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 0. 0x04 0. 0x00 0. " COMP1 ,Comparator 1 Interrupt" "No interrupt,Interrupt" group.long 0x18++0x03 line.long 0x00 "LPCOMP_INTR_MASK,LPCOMP Interrupt Request Mask" bitfld.long 0x00 1. " COMP2_MASK ,Comparator 2 interrupt mask" "Not masked,Masked" bitfld.long 0x00 0. " COMP1_MASK ,Comparator 1 interrupt mask" "Not masked,Masked" rgroup.long 0x1C++0x03 line.long 0x00 "LPCOMP_INTR_MASKED,LPCOMP Interrupt Request Masked" bitfld.long 0x00 1. " COMP2_MASKED ,Logical and of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 0. " COMP1_MASKED ,Logical and of corresponding request and mask bits" "No interrupt,Interrupt" group.long 0xFF00++0x0F line.long 0x00 "LPCOMP_TRIM1,LPCOMP Trim 1 Register" bitfld.long 0x00 0.--4. " COMP1_TRIMA ,Comparator 1 trim A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "LPCOMP_TRIM2,LPCOMP Trim 2 Register" bitfld.long 0x04 0.--4. " COMP1_TRIMB ,Comparator 1 trim B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "LPCOMP_TRIM3,LPCOMP Trim 3 Register" bitfld.long 0x08 0.--4. " COMP2_TRIMB ,Comparator 2 trim A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x0C "LPCOMP_TRIM4,LPCOMP Trim 4 Register" bitfld.long 0x0C 0.--4. " COMP2_TRIMB ,Comparator 2 trim B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "PASS (Programmable Analog Sub-System)" base ad:0x403F0000 width 21. rgroup.long 0x00++0x03 line.long 0x00 "PASS_INTR_CAUSE,Interrupt Cause Register" bitfld.long 0x00 1. " CTB1_INT ,CTB1 interrupt pending" "Not pending,Pending" bitfld.long 0x00 0. " CTB0_INT ,CTB0 interrupt pending" "Not pending,Pending" group.long 0xF00++0x03 line.long 0x00 "PASS_DSAB_TRIM,DSAB Trim Bits Register" bitfld.long 0x00 0.--3. " IBIAS_TRIM ,IBIAS trim" "15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0" group.long 0xE00++0x03 line.long 0x00 "PASS_DSAB_DSAB_CTRL,Global DSAB Control Register" bitfld.long 0x00 31. " ENABLED ,DSAB enable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " SEL_OUT ,Bias current select" "Bypass,Dsab_ibias,?..." bitfld.long 0x00 0.--5. " CURRENT_SEL ,Current selection for dsab_ibias" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" width 0x0B tree.end tree "ROM" base ad:0xF0000000 width 15. rgroup.long 0x00++0x03 line.long 0x00 "ROMTABLE_ADDR,Cortex M0 ROM Table Register" hexmask.long.tbyte 0x00 12.--31. 0x10 " ADDR_OFFSET ,Address offset of the Cortex-M0 ROM Table" bitfld.long 0x00 1. " FORMAT_32BIT ,ROM Table format" "8-bit,32-bit" bitfld.long 0x00 0. " PRESENT , Entry present" "0,1" rgroup.long 0xFCC++0x33 line.long 0x00 "ROMTABLE_DID,Device Type Identifier Register" line.long 0x04 "ROMTABLE_PID4,Peripheral Identification Register 4" bitfld.long 0x04 4.--7. " COUNT ,Size of ROM Table is 2^COUNT * 4 KByte" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " JEP_CONTINUATION ,JEP106 continuation code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "ROMTABLE_PID5,Peripheral Identification Register 5" line.long 0x0C "ROMTABLE_PID6,Peripheral Identification Register 6" line.long 0x10 "ROMTABLE_PID7,Peripheral Identification Register 7" line.long 0x14 "ROMTABLE_PID0,Peripheral Identification Register 0" hexmask.long.byte 0x14 0.--7. 1. " PN_MIN ,JEP106 part number" line.long 0x18 "ROMTABLE_PID1,Peripheral Identification Register 1" bitfld.long 0x18 4.--7. " JEPID_MIN ,JEP106 vendor id" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 0.--3. " PN_MAJ ,JEP106 part number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x1C "ROMTABLE_PID2,Peripheral Identification Register 2" bitfld.long 0x1C 4.--7. " REV ,Major REVision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1C 0.--2. " JEPID_MAJ ,JEP106 vendor id" "0,1,2,3,4,5,6,7" line.long 0x20 "ROMTABLE_PID3,Peripheral Identification Register 3" bitfld.long 0x20 4.--7. " REV_AND ,Minor REVision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x20 0.--3. " CM ,Customer modified field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x24 "ROMTABLE_CID0,Component Identification Register 0" line.long 0x28 "ROMTABLE_CID1,Component Identification Register 1" line.long 0x2C "ROMTABLE_CID2,Component Identification Register 2" line.long 0x30 "ROMTABLE_CID3,Component Identification Register 3" width 0x0B tree.end tree "SAR ADC" base ad:0x403A0000 width 23. sif CPUIS("CY8C6*") group.long 0x00++0x03 line.long 0x00 "CTRL,Analog Control Register" bitfld.long 0x00 31. " ENABLED ,SAR enable" "Disabled,Enabled" bitfld.long 0x00 30. " SWITCH_DISABLE ,Disable SAR sequencer from enabling routing switches" "Yes,No" bitfld.long 0x00 29. " DSI_MODE ,DSI control mode select" "Normal mode,DSI mode" textline " " bitfld.long 0x00 28. " DSI_SYNC_CONFIG ,DSI synchronization configuration" "Bypassed,Synchronized" bitfld.long 0x00 27. " DEEPSLEEP_ON ,SARMUX enable during DeepSleep power mode" "Disabled,Enabled" bitfld.long 0x00 24.--26. " COMP_PWR ,Comparator power mode" "P100,P80,P60,P50,P40,P30,P20,P10" textline " " bitfld.long 0x00 21. " REFBUF_EN ,Enable the SARREFBUF" "Disabled,Enabled" bitfld.long 0x00 20. " BOOSTPUMP_EN ,SARADC internal pump enable" "Disabled,Enabled" bitfld.long 0x00 16.--19. " SPARE ,Spare controls" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 14.--15. " COMP_DLY ,Set the comparator latch delay in accordance with SAR conversion rate" "D2P5,D4,D10,D12" bitfld.long 0x00 13. " HW_CTRL_NEGVREF ,Hardware control" "Firmware,Hardware" bitfld.long 0x00 9.--11. " NEG_SEL ,SARADC internal NEG selection for single ended conversion" "VSSA_KELVIN,ART_VSSA,P1,P3,P5,P7,ACORE,VREF" textline " " bitfld.long 0x00 7. " VREF_BYP_CAP_EN ,VREF bypass cap enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " VREF_SEL ,SARADC internal VREF selection" "VREF0,VREF1,VREF2,VREF_AROUTE,VBGR,VREF_EXT,VDDA_DIV_2,VDDA" bitfld.long 0x00 0.--2. " PWR_CTRL_VREF ,VREF buffer low power mode" "PWR_100,PWR_80,PWR_50,PWR_40,PWR_30,PWR_20,PWR_10,PWR_5" else if (((per.l(ad:0x403A0000+0x208))&0x80000000)==0x80000000) if (((per.l(ad:0x403A0000))&0x80000000)==0x80000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Analog Control Register" bitfld.long 0x00 31. " ENABLED ,SAR enable" "Disabled,Enabled" bitfld.long 0x00 30. " SWITCH_DISABLE ,SAR sequencer from enabling routing switches disable" "Normal mode,Disabled" bitfld.long 0x00 29. " DSI_MODE ,DSI control mode select" "Normal mode,DSI mode" textline " " bitfld.long 0x00 28. " DSI_SYNC_CONFIG ,DSI synchronization configuration" "Bypass,Synchronize" bitfld.long 0x00 27. " DEEPSLEEP_ON ,SARMUX enable during DeepSleep power mode" "Disabled,Enabled" bitfld.long 0x00 24.--25. " ICONT_LV ,SARADC low power mode" "NORMAL_PWR,HALF_PWR,MORE_PWR,QUARTER_PWR" textline " " bitfld.long 0x00 20. " BOOSTPUMP_EN ,SARADC internal pump enable" "Disabled,Enabled" bitfld.long 0x00 16.--19. " SPARE ,Spare controls" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " PWR_CTRL_VREF ,VREF buffer low power mode" "NORMAL_PWR,HALF_PWR,THIRD_PWR,QUARTER_PWR" textline " " bitfld.long 0x00 13. " HW_CTRL_NEGVREF ,Hardware control" "Only firmware,Hardware masked by firmware" bitfld.long 0x00 9.--11. " NEG_SEL ,SARADC internal NEG selection for single ended conversion" "VSSA_KELVIN,ART_VSSA,P1,P3,P5,P7,ACORE,VREF" bitfld.long 0x00 7. " VREF_BYP_CAP_EN ,VREF bypass cap enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--6. " VREF_SEL ,SARADC internal VREF selection" "VREF0,VREF1,VREF2,VREF_AROUTE,VBGR,VREF_EXT,VDDA_DIV_2,VDDA" else group.long 0x00++0x03 line.long 0x00 "CTRL,Analog Control Register" bitfld.long 0x00 31. " ENABLED ,SAR enable" "Disabled,Enabled" bitfld.long 0x00 30. " SWITCH_DISABLE ,SAR sequencer from enabling routing switches disable" "Normal mode,Disabled" bitfld.long 0x00 29. " DSI_MODE ,DSI control mode select" "Normal mode,DSI mode" textline " " bitfld.long 0x00 28. " DSI_SYNC_CONFIG ,DSI synchronization configuration" "Bypass,Synchronize" bitfld.long 0x00 27. " DEEPSLEEP_ON ,SARMUX enable during DeepSleep power mode" "Disabled,Enabled" bitfld.long 0x00 24.--25. " ICONT_LV ,SARADC low power mode" "NORMAL_PWR,HALF_PWR,MORE_PWR,QUARTER_PWR" textline " " bitfld.long 0x00 20. " BOOSTPUMP_EN ,SARADC internal pump enable" "Disabled,Enabled" bitfld.long 0x00 16.--19. " SPARE ,Spare controls" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " PWR_CTRL_VREF ,VREF buffer low power mode" "NORMAL_PWR,HALF_PWR,THIRD_PWR,QUARTER_PWR" textline " " bitfld.long 0x00 13. " HW_CTRL_NEGVREF ,Hardware control" "Only firmware,Hardware masked by firmware" bitfld.long 0x00 9.--11. " NEG_SEL ,SARADC internal NEG selection for single ended conversion" "VSSA_KELVIN,ART_VSSA,P1,P3,P5,P7,ACORE,VREF" bitfld.long 0x00 7. " VREF_BYP_CAP_EN ,VREF bypass cap enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--6. " VREF_SEL ,SARADC internal VREF selection" "VREF0,VREF1,VREF2,VREF_AROUTE,VBGR,VREF_EXT,VDDA_DIV_2,VDDA" endif else group.long 0x00++0x03 line.long 0x00 "CTRL,Analog Control Register" bitfld.long 0x00 31. " ENABLED ,SAR enable" "Disabled,?..." bitfld.long 0x00 30. " SWITCH_DISABLE ,SAR sequencer from enabling routing switches disable" "Normal mode,Disabled" bitfld.long 0x00 29. " DSI_MODE ,DSI control mode select" "Normal mode,DSI mode" textline " " bitfld.long 0x00 28. " DSI_SYNC_CONFIG ,DSI synchronization configuration" "Bypass,Synchronize" rbitfld.long 0x00 27. " DEEPSLEEP_ON ,SARMUX enable during DeepSleep power mode" "Disabled,Enabled" bitfld.long 0x00 24.--25. " ICONT_LV ,SARADC low power mode" "NORMAL_PWR,HALF_PWR,MORE_PWR,QUARTER_PWR" textline " " bitfld.long 0x00 20. " BOOSTPUMP_EN ,SARADC internal pump enable" "Disabled,Enabled" bitfld.long 0x00 16.--19. " SPARE ,Spare controls" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. " PWR_CTRL_VREF ,VREF buffer low power mode" "NORMAL_PWR,HALF_PWR,THIRD_PWR,QUARTER_PWR" textline " " bitfld.long 0x00 13. " HW_CTRL_NEGVREF ,Hardware control" "Only firmware,Hardware masked by firmware" bitfld.long 0x00 9.--11. " NEG_SEL ,SARADC internal NEG selection for single ended conversion" "VSSA_KELVIN,ART_VSSA,P1,P3,P5,P7,ACORE,VREF" bitfld.long 0x00 7. " VREF_BYP_CAP_EN ,VREF bypass cap enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--6. " VREF_SEL ,SARADC internal VREF selection" "VREF0,VREF1,VREF2,VREF_AROUTE,VBGR,VREF_EXT,VDDA_DIV_2,VDDA" endif endif group.long 0x04++0x03 line.long 0x00 "SAMPLE_CTRL,Sample Control Register" bitfld.long 0x00 31. " EOS_DSI_OUT_EN ,Output EOS_INTR to DSI enable" "Disabled,Enabled" bitfld.long 0x00 19. " DSI_SYNC_TRIGGER ,DSI trigger synchronization" "Bypassed,Synchronized" bitfld.long 0x00 18. " DSI_TRIGGER_LEVEL ,DSI trigger level" "Pulse,Level" textline " " bitfld.long 0x00 17. " DSI_TRIGGER_EN ,DSI hardware trigger enable" "Disabled,Enabled" bitfld.long 0x00 16. " CONTINUOUS ,Continuous scan enable" "Disabled,Enabled" sif CPUIS("CY8C6*") textline " " bitfld.long 0x00 8. " AVG_MODE ,Averaging mode" "ACCUNDUMP,INTERLEAVED" endif textline " " bitfld.long 0x00 7. " AVG_SHIFT ,Averaging shifting" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--6. " AVG_CNT ,Averaging count" "2 times,4 times,8 times,16 times,32 times,64 times,128 times,256 times" bitfld.long 0x00 3. " DIFFERENTIAL_SIGNED ,Output data from a differential conversion" "UNSIGNED,SIGNED" bitfld.long 0x00 2. " SINGLE_ENDED_SIGNED ,Output data from a single ended conversion" "UNSIGNED,SIGNED" textline " " bitfld.long 0x00 1. " LEFT_ALIGN ,Left align data enable" "Disabled,Enabled" sif !CPUIS("CY8C6*") bitfld.long 0x00 0. " SUB_RESOLUTION ,Conversion resolution" "8-bit,10-bit" endif group.long 0x10++0x17 line.long 0x00 "SAMPLE_TIME01,Sample Time Specification ST0 And ST1 Register" hexmask.long.word 0x00 16.--25. 1. " SAMPLE_TIME1 ,Sample time1" hexmask.long.word 0x00 0.--9. 1. " SAMPLE_TIME0 ,Sample time0" line.long 0x04 "SAMPLE_TIME23,Sample Time Specification ST2 And ST3 Register" hexmask.long.word 0x04 16.--25. 1. " SAMPLE_TIME3 ,Sample time3" hexmask.long.word 0x04 0.--9. 1. " SAMPLE_TIME2 ,Sample time2" line.long 0x08 "RANGE_THRES,Global Range Detect Threshold Register" hexmask.long.word 0x08 16.--31. 1. " RANGE_HIGH ,High threshold for range detect" hexmask.long.word 0x08 0.--15. 1. " RANGE_LOW ,Low threshold for range detect" line.long 0x0C "RANGE_COND,Global Range Detect Mode Register" bitfld.long 0x0C 30.--31. " RANGE_COND ,Range condition select" "BELOW,INSIDE,ABOVE,OUTSIDE" line.long 0x10 "CHAN_EN,Enable Bits For The Channels Register" bitfld.long 0x10 15. " CHAN_EN[15] ,Channel 15 enable" "Disabled,Enabled" bitfld.long 0x10 14. " [14] ,Channel 14 enable" "Disabled,Enabled" bitfld.long 0x10 13. " [13] ,Channel 13 enable" "Disabled,Enabled" textline " " bitfld.long 0x10 12. " [12] ,Channel 12 enable" "Disabled,Enabled" bitfld.long 0x10 11. " [11] ,Channel 11 enable" "Disabled,Enabled" bitfld.long 0x10 10. " [10] ,Channel 10 enable" "Disabled,Enabled" textline " " bitfld.long 0x10 9. " [9] ,Channel 9 enable" "Disabled,Enabled" bitfld.long 0x10 8. " [8] ,Channel 8 enable" "Disabled,Enabled" bitfld.long 0x10 7. " [7] ,Channel 7 enable" "Disabled,Enabled" textline " " bitfld.long 0x10 6. " [6] ,Channel 6 enable" "Disabled,Enabled" bitfld.long 0x10 5. " [5] ,Channel 5 enable" "Disabled,Enabled" bitfld.long 0x10 4. " [4] ,Channel 4 enable" "Disabled,Enabled" textline " " bitfld.long 0x10 3. " [3] ,Channel 3 enable" "Disabled,Enabled" bitfld.long 0x10 2. " [2] ,Channel 2 enable" "Disabled,Enabled" bitfld.long 0x10 1. " [1] ,Channel 1 enable" "Disabled,Enabled" textline " " bitfld.long 0x10 0. " [0] ,Channel 0 enable" "Disabled,Enabled" line.long 0x14 "START_CTRL,Start Control Register" bitfld.long 0x14 0. " FW_TRIGGER ,Firmware trigger" "No effect,Triggered" if (((per.l(ad:0x403A0000+0x80))&0x100)==0x100) group.long 0x80++0x03 line.long 0x00 "CHAN_CONFIG0,Channel 0 Configuration Register" bitfld.long 0x00 31. " DSI_OUT_EN ,DSI data output enable" "Disabled,Enabled" sif CPUIS("CY8C6*") textline " " bitfld.long 0x00 24. " NEG_ADDR_EN ,NEG_ADDR driver enable" "Disabled,Enabled" bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "SARMUX,,,,,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7" endif textline " " bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "ST0,ST1,ST2,ST3" bitfld.long 0x00 10. " AVG_EN ,Averaging enable" "Disabled,Enabled" sif !CPUIS("CY8C6*") textline " " bitfld.long 0x00 9. " RESOLUTION ,Resolution set" "MAXRES,SUBRES" endif textline " " bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " PORT_ADDR ,Address of the port that contains the pin to be sampled" "SARMUX,CTB0,CTB1,CTB2,CTB3,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" textline " " bitfld.long 0x00 1.--2. " PIN_ADDR ,Address of the pin to be sampled" "0,2,4,6" else group.long 0x80++0x03 line.long 0x00 "CHAN_CONFIG0,Channel 0 Configuration Register" bitfld.long 0x00 31. " DSI_OUT_EN ,DSI data output enable" "Disabled,Enabled" sif CPUIS("CY8C6*") textline " " bitfld.long 0x00 24. " NEG_ADDR_EN ,NEG_ADDR driver enable" "Disabled,Enabled" bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "SARMUX,,,,,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7" endif textline " " bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "ST0,ST1,ST2,ST3" bitfld.long 0x00 10. " AVG_EN ,Averaging enable" "Disabled,Enabled" sif !CPUIS("CY8C6*") textline " " bitfld.long 0x00 9. " RESOLUTION ,Resolution set" "MAXRES,SUBRES" endif textline " " bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " PORT_ADDR ,Address of the port that contains the pin to be sampled" "SARMUX,CTB0,CTB1,CTB2,CTB3,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" textline " " bitfld.long 0x00 0.--2. " PIN_ADDR ,Address of the pin to be sampled" "0,1,2,3,4,5,6,7" endif if (((per.l(ad:0x403A0000+0x84))&0x100)==0x100) group.long 0x84++0x03 line.long 0x00 "CHAN_CONFIG1,Channel 1 Configuration Register" bitfld.long 0x00 31. " DSI_OUT_EN ,DSI data output enable" "Disabled,Enabled" sif CPUIS("CY8C6*") textline " " bitfld.long 0x00 24. " NEG_ADDR_EN ,NEG_ADDR driver enable" "Disabled,Enabled" bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "SARMUX,,,,,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7" endif textline " " bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "ST0,ST1,ST2,ST3" bitfld.long 0x00 10. " AVG_EN ,Averaging enable" "Disabled,Enabled" sif !CPUIS("CY8C6*") textline " " bitfld.long 0x00 9. " RESOLUTION ,Resolution set" "MAXRES,SUBRES" endif textline " " bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " PORT_ADDR ,Address of the port that contains the pin to be sampled" "SARMUX,CTB0,CTB1,CTB2,CTB3,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" textline " " bitfld.long 0x00 1.--2. " PIN_ADDR ,Address of the pin to be sampled" "0,2,4,6" else group.long 0x84++0x03 line.long 0x00 "CHAN_CONFIG1,Channel 1 Configuration Register" bitfld.long 0x00 31. " DSI_OUT_EN ,DSI data output enable" "Disabled,Enabled" sif CPUIS("CY8C6*") textline " " bitfld.long 0x00 24. " NEG_ADDR_EN ,NEG_ADDR driver enable" "Disabled,Enabled" bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "SARMUX,,,,,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7" endif textline " " bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "ST0,ST1,ST2,ST3" bitfld.long 0x00 10. " AVG_EN ,Averaging enable" "Disabled,Enabled" sif !CPUIS("CY8C6*") textline " " bitfld.long 0x00 9. " RESOLUTION ,Resolution set" "MAXRES,SUBRES" endif textline " " bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " PORT_ADDR ,Address of the port that contains the pin to be sampled" "SARMUX,CTB0,CTB1,CTB2,CTB3,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" textline " " bitfld.long 0x00 0.--2. " PIN_ADDR ,Address of the pin to be sampled" "0,1,2,3,4,5,6,7" endif if (((per.l(ad:0x403A0000+0x88))&0x100)==0x100) group.long 0x88++0x03 line.long 0x00 "CHAN_CONFIG2,Channel 2 Configuration Register" bitfld.long 0x00 31. " DSI_OUT_EN ,DSI data output enable" "Disabled,Enabled" sif CPUIS("CY8C6*") textline " " bitfld.long 0x00 24. " NEG_ADDR_EN ,NEG_ADDR driver enable" "Disabled,Enabled" bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "SARMUX,,,,,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7" endif textline " " bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "ST0,ST1,ST2,ST3" bitfld.long 0x00 10. " AVG_EN ,Averaging enable" "Disabled,Enabled" sif !CPUIS("CY8C6*") textline " " bitfld.long 0x00 9. " RESOLUTION ,Resolution set" "MAXRES,SUBRES" endif textline " " bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " PORT_ADDR ,Address of the port that contains the pin to be sampled" "SARMUX,CTB0,CTB1,CTB2,CTB3,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" textline " " bitfld.long 0x00 1.--2. " PIN_ADDR ,Address of the pin to be sampled" "0,2,4,6" else group.long 0x88++0x03 line.long 0x00 "CHAN_CONFIG2,Channel 2 Configuration Register" bitfld.long 0x00 31. " DSI_OUT_EN ,DSI data output enable" "Disabled,Enabled" sif CPUIS("CY8C6*") textline " " bitfld.long 0x00 24. " NEG_ADDR_EN ,NEG_ADDR driver enable" "Disabled,Enabled" bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "SARMUX,,,,,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7" endif textline " " bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "ST0,ST1,ST2,ST3" bitfld.long 0x00 10. " AVG_EN ,Averaging enable" "Disabled,Enabled" sif !CPUIS("CY8C6*") textline " " bitfld.long 0x00 9. " RESOLUTION ,Resolution set" "MAXRES,SUBRES" endif textline " " bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " PORT_ADDR ,Address of the port that contains the pin to be sampled" "SARMUX,CTB0,CTB1,CTB2,CTB3,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" textline " " bitfld.long 0x00 0.--2. " PIN_ADDR ,Address of the pin to be sampled" "0,1,2,3,4,5,6,7" endif if (((per.l(ad:0x403A0000+0x8C))&0x100)==0x100) group.long 0x8C++0x03 line.long 0x00 "CHAN_CONFIG3,Channel 3 Configuration Register" bitfld.long 0x00 31. " DSI_OUT_EN ,DSI data output enable" "Disabled,Enabled" sif CPUIS("CY8C6*") textline " " bitfld.long 0x00 24. " NEG_ADDR_EN ,NEG_ADDR driver enable" "Disabled,Enabled" bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "SARMUX,,,,,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7" endif textline " " bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "ST0,ST1,ST2,ST3" bitfld.long 0x00 10. " AVG_EN ,Averaging enable" "Disabled,Enabled" sif !CPUIS("CY8C6*") textline " " bitfld.long 0x00 9. " RESOLUTION ,Resolution set" "MAXRES,SUBRES" endif textline " " bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " PORT_ADDR ,Address of the port that contains the pin to be sampled" "SARMUX,CTB0,CTB1,CTB2,CTB3,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" textline " " bitfld.long 0x00 1.--2. " PIN_ADDR ,Address of the pin to be sampled" "0,2,4,6" else group.long 0x8C++0x03 line.long 0x00 "CHAN_CONFIG3,Channel 3 Configuration Register" bitfld.long 0x00 31. " DSI_OUT_EN ,DSI data output enable" "Disabled,Enabled" sif CPUIS("CY8C6*") textline " " bitfld.long 0x00 24. " NEG_ADDR_EN ,NEG_ADDR driver enable" "Disabled,Enabled" bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "SARMUX,,,,,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7" endif textline " " bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "ST0,ST1,ST2,ST3" bitfld.long 0x00 10. " AVG_EN ,Averaging enable" "Disabled,Enabled" sif !CPUIS("CY8C6*") textline " " bitfld.long 0x00 9. " RESOLUTION ,Resolution set" "MAXRES,SUBRES" endif textline " " bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " PORT_ADDR ,Address of the port that contains the pin to be sampled" "SARMUX,CTB0,CTB1,CTB2,CTB3,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" textline " " bitfld.long 0x00 0.--2. " PIN_ADDR ,Address of the pin to be sampled" "0,1,2,3,4,5,6,7" endif if (((per.l(ad:0x403A0000+0x90))&0x100)==0x100) group.long 0x90++0x03 line.long 0x00 "CHAN_CONFIG4,Channel 4 Configuration Register" bitfld.long 0x00 31. " DSI_OUT_EN ,DSI data output enable" "Disabled,Enabled" sif CPUIS("CY8C6*") textline " " bitfld.long 0x00 24. " NEG_ADDR_EN ,NEG_ADDR driver enable" "Disabled,Enabled" bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "SARMUX,,,,,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7" endif textline " " bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "ST0,ST1,ST2,ST3" bitfld.long 0x00 10. " AVG_EN ,Averaging enable" "Disabled,Enabled" sif !CPUIS("CY8C6*") textline " " bitfld.long 0x00 9. " RESOLUTION ,Resolution set" "MAXRES,SUBRES" endif textline " " bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " PORT_ADDR ,Address of the port that contains the pin to be sampled" "SARMUX,CTB0,CTB1,CTB2,CTB3,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" textline " " bitfld.long 0x00 1.--2. " PIN_ADDR ,Address of the pin to be sampled" "0,2,4,6" else group.long 0x90++0x03 line.long 0x00 "CHAN_CONFIG4,Channel 4 Configuration Register" bitfld.long 0x00 31. " DSI_OUT_EN ,DSI data output enable" "Disabled,Enabled" sif CPUIS("CY8C6*") textline " " bitfld.long 0x00 24. " NEG_ADDR_EN ,NEG_ADDR driver enable" "Disabled,Enabled" bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "SARMUX,,,,,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7" endif textline " " bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "ST0,ST1,ST2,ST3" bitfld.long 0x00 10. " AVG_EN ,Averaging enable" "Disabled,Enabled" sif !CPUIS("CY8C6*") textline " " bitfld.long 0x00 9. " RESOLUTION ,Resolution set" "MAXRES,SUBRES" endif textline " " bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " PORT_ADDR ,Address of the port that contains the pin to be sampled" "SARMUX,CTB0,CTB1,CTB2,CTB3,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" textline " " bitfld.long 0x00 0.--2. " PIN_ADDR ,Address of the pin to be sampled" "0,1,2,3,4,5,6,7" endif if (((per.l(ad:0x403A0000+0x94))&0x100)==0x100) group.long 0x94++0x03 line.long 0x00 "CHAN_CONFIG5,Channel 5 Configuration Register" bitfld.long 0x00 31. " DSI_OUT_EN ,DSI data output enable" "Disabled,Enabled" sif CPUIS("CY8C6*") textline " " bitfld.long 0x00 24. " NEG_ADDR_EN ,NEG_ADDR driver enable" "Disabled,Enabled" bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "SARMUX,,,,,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7" endif textline " " bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "ST0,ST1,ST2,ST3" bitfld.long 0x00 10. " AVG_EN ,Averaging enable" "Disabled,Enabled" sif !CPUIS("CY8C6*") textline " " bitfld.long 0x00 9. " RESOLUTION ,Resolution set" "MAXRES,SUBRES" endif textline " " bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " PORT_ADDR ,Address of the port that contains the pin to be sampled" "SARMUX,CTB0,CTB1,CTB2,CTB3,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" textline " " bitfld.long 0x00 1.--2. " PIN_ADDR ,Address of the pin to be sampled" "0,2,4,6" else group.long 0x94++0x03 line.long 0x00 "CHAN_CONFIG5,Channel 5 Configuration Register" bitfld.long 0x00 31. " DSI_OUT_EN ,DSI data output enable" "Disabled,Enabled" sif CPUIS("CY8C6*") textline " " bitfld.long 0x00 24. " NEG_ADDR_EN ,NEG_ADDR driver enable" "Disabled,Enabled" bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "SARMUX,,,,,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7" endif textline " " bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "ST0,ST1,ST2,ST3" bitfld.long 0x00 10. " AVG_EN ,Averaging enable" "Disabled,Enabled" sif !CPUIS("CY8C6*") textline " " bitfld.long 0x00 9. " RESOLUTION ,Resolution set" "MAXRES,SUBRES" endif textline " " bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " PORT_ADDR ,Address of the port that contains the pin to be sampled" "SARMUX,CTB0,CTB1,CTB2,CTB3,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" textline " " bitfld.long 0x00 0.--2. " PIN_ADDR ,Address of the pin to be sampled" "0,1,2,3,4,5,6,7" endif if (((per.l(ad:0x403A0000+0x98))&0x100)==0x100) group.long 0x98++0x03 line.long 0x00 "CHAN_CONFIG6,Channel 6 Configuration Register" bitfld.long 0x00 31. " DSI_OUT_EN ,DSI data output enable" "Disabled,Enabled" sif CPUIS("CY8C6*") textline " " bitfld.long 0x00 24. " NEG_ADDR_EN ,NEG_ADDR driver enable" "Disabled,Enabled" bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "SARMUX,,,,,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7" endif textline " " bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "ST0,ST1,ST2,ST3" bitfld.long 0x00 10. " AVG_EN ,Averaging enable" "Disabled,Enabled" sif !CPUIS("CY8C6*") textline " " bitfld.long 0x00 9. " RESOLUTION ,Resolution set" "MAXRES,SUBRES" endif textline " " bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " PORT_ADDR ,Address of the port that contains the pin to be sampled" "SARMUX,CTB0,CTB1,CTB2,CTB3,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" textline " " bitfld.long 0x00 1.--2. " PIN_ADDR ,Address of the pin to be sampled" "0,2,4,6" else group.long 0x98++0x03 line.long 0x00 "CHAN_CONFIG6,Channel 6 Configuration Register" bitfld.long 0x00 31. " DSI_OUT_EN ,DSI data output enable" "Disabled,Enabled" sif CPUIS("CY8C6*") textline " " bitfld.long 0x00 24. " NEG_ADDR_EN ,NEG_ADDR driver enable" "Disabled,Enabled" bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "SARMUX,,,,,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7" endif textline " " bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "ST0,ST1,ST2,ST3" bitfld.long 0x00 10. " AVG_EN ,Averaging enable" "Disabled,Enabled" sif !CPUIS("CY8C6*") textline " " bitfld.long 0x00 9. " RESOLUTION ,Resolution set" "MAXRES,SUBRES" endif textline " " bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " PORT_ADDR ,Address of the port that contains the pin to be sampled" "SARMUX,CTB0,CTB1,CTB2,CTB3,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" textline " " bitfld.long 0x00 0.--2. " PIN_ADDR ,Address of the pin to be sampled" "0,1,2,3,4,5,6,7" endif if (((per.l(ad:0x403A0000+0x9C))&0x100)==0x100) group.long 0x9C++0x03 line.long 0x00 "CHAN_CONFIG7,Channel 7 Configuration Register" bitfld.long 0x00 31. " DSI_OUT_EN ,DSI data output enable" "Disabled,Enabled" sif CPUIS("CY8C6*") textline " " bitfld.long 0x00 24. " NEG_ADDR_EN ,NEG_ADDR driver enable" "Disabled,Enabled" bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "SARMUX,,,,,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7" endif textline " " bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "ST0,ST1,ST2,ST3" bitfld.long 0x00 10. " AVG_EN ,Averaging enable" "Disabled,Enabled" sif !CPUIS("CY8C6*") textline " " bitfld.long 0x00 9. " RESOLUTION ,Resolution set" "MAXRES,SUBRES" endif textline " " bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " PORT_ADDR ,Address of the port that contains the pin to be sampled" "SARMUX,CTB0,CTB1,CTB2,CTB3,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" textline " " bitfld.long 0x00 1.--2. " PIN_ADDR ,Address of the pin to be sampled" "0,2,4,6" else group.long 0x9C++0x03 line.long 0x00 "CHAN_CONFIG7,Channel 7 Configuration Register" bitfld.long 0x00 31. " DSI_OUT_EN ,DSI data output enable" "Disabled,Enabled" sif CPUIS("CY8C6*") textline " " bitfld.long 0x00 24. " NEG_ADDR_EN ,NEG_ADDR driver enable" "Disabled,Enabled" bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "SARMUX,,,,,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7" endif textline " " bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "ST0,ST1,ST2,ST3" bitfld.long 0x00 10. " AVG_EN ,Averaging enable" "Disabled,Enabled" sif !CPUIS("CY8C6*") textline " " bitfld.long 0x00 9. " RESOLUTION ,Resolution set" "MAXRES,SUBRES" endif textline " " bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " PORT_ADDR ,Address of the port that contains the pin to be sampled" "SARMUX,CTB0,CTB1,CTB2,CTB3,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" textline " " bitfld.long 0x00 0.--2. " PIN_ADDR ,Address of the pin to be sampled" "0,1,2,3,4,5,6,7" endif if (((per.l(ad:0x403A0000+0xA0))&0x100)==0x100) group.long 0xA0++0x03 line.long 0x00 "CHAN_CONFIG8,Channel 8 Configuration Register" bitfld.long 0x00 31. " DSI_OUT_EN ,DSI data output enable" "Disabled,Enabled" sif CPUIS("CY8C6*") textline " " bitfld.long 0x00 24. " NEG_ADDR_EN ,NEG_ADDR driver enable" "Disabled,Enabled" bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "SARMUX,,,,,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7" endif textline " " bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "ST0,ST1,ST2,ST3" bitfld.long 0x00 10. " AVG_EN ,Averaging enable" "Disabled,Enabled" sif !CPUIS("CY8C6*") textline " " bitfld.long 0x00 9. " RESOLUTION ,Resolution set" "MAXRES,SUBRES" endif textline " " bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " PORT_ADDR ,Address of the port that contains the pin to be sampled" "SARMUX,CTB0,CTB1,CTB2,CTB3,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" textline " " bitfld.long 0x00 1.--2. " PIN_ADDR ,Address of the pin to be sampled" "0,2,4,6" else group.long 0xA0++0x03 line.long 0x00 "CHAN_CONFIG8,Channel 8 Configuration Register" bitfld.long 0x00 31. " DSI_OUT_EN ,DSI data output enable" "Disabled,Enabled" sif CPUIS("CY8C6*") textline " " bitfld.long 0x00 24. " NEG_ADDR_EN ,NEG_ADDR driver enable" "Disabled,Enabled" bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "SARMUX,,,,,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7" endif textline " " bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "ST0,ST1,ST2,ST3" bitfld.long 0x00 10. " AVG_EN ,Averaging enable" "Disabled,Enabled" sif !CPUIS("CY8C6*") textline " " bitfld.long 0x00 9. " RESOLUTION ,Resolution set" "MAXRES,SUBRES" endif textline " " bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " PORT_ADDR ,Address of the port that contains the pin to be sampled" "SARMUX,CTB0,CTB1,CTB2,CTB3,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" textline " " bitfld.long 0x00 0.--2. " PIN_ADDR ,Address of the pin to be sampled" "0,1,2,3,4,5,6,7" endif if (((per.l(ad:0x403A0000+0xA4))&0x100)==0x100) group.long 0xA4++0x03 line.long 0x00 "CHAN_CONFIG9,Channel 9 Configuration Register" bitfld.long 0x00 31. " DSI_OUT_EN ,DSI data output enable" "Disabled,Enabled" sif CPUIS("CY8C6*") textline " " bitfld.long 0x00 24. " NEG_ADDR_EN ,NEG_ADDR driver enable" "Disabled,Enabled" bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "SARMUX,,,,,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7" endif textline " " bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "ST0,ST1,ST2,ST3" bitfld.long 0x00 10. " AVG_EN ,Averaging enable" "Disabled,Enabled" sif !CPUIS("CY8C6*") textline " " bitfld.long 0x00 9. " RESOLUTION ,Resolution set" "MAXRES,SUBRES" endif textline " " bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " PORT_ADDR ,Address of the port that contains the pin to be sampled" "SARMUX,CTB0,CTB1,CTB2,CTB3,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" textline " " bitfld.long 0x00 1.--2. " PIN_ADDR ,Address of the pin to be sampled" "0,2,4,6" else group.long 0xA4++0x03 line.long 0x00 "CHAN_CONFIG9,Channel 9 Configuration Register" bitfld.long 0x00 31. " DSI_OUT_EN ,DSI data output enable" "Disabled,Enabled" sif CPUIS("CY8C6*") textline " " bitfld.long 0x00 24. " NEG_ADDR_EN ,NEG_ADDR driver enable" "Disabled,Enabled" bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "SARMUX,,,,,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7" endif textline " " bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "ST0,ST1,ST2,ST3" bitfld.long 0x00 10. " AVG_EN ,Averaging enable" "Disabled,Enabled" sif !CPUIS("CY8C6*") textline " " bitfld.long 0x00 9. " RESOLUTION ,Resolution set" "MAXRES,SUBRES" endif textline " " bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " PORT_ADDR ,Address of the port that contains the pin to be sampled" "SARMUX,CTB0,CTB1,CTB2,CTB3,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" textline " " bitfld.long 0x00 0.--2. " PIN_ADDR ,Address of the pin to be sampled" "0,1,2,3,4,5,6,7" endif if (((per.l(ad:0x403A0000+0xA8))&0x100)==0x100) group.long 0xA8++0x03 line.long 0x00 "CHAN_CONFIG10,Channel 10 Configuration Register" bitfld.long 0x00 31. " DSI_OUT_EN ,DSI data output enable" "Disabled,Enabled" sif CPUIS("CY8C6*") textline " " bitfld.long 0x00 24. " NEG_ADDR_EN ,NEG_ADDR driver enable" "Disabled,Enabled" bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "SARMUX,,,,,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7" endif textline " " bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "ST0,ST1,ST2,ST3" bitfld.long 0x00 10. " AVG_EN ,Averaging enable" "Disabled,Enabled" sif !CPUIS("CY8C6*") textline " " bitfld.long 0x00 9. " RESOLUTION ,Resolution set" "MAXRES,SUBRES" endif textline " " bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " PORT_ADDR ,Address of the port that contains the pin to be sampled" "SARMUX,CTB0,CTB1,CTB2,CTB3,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" textline " " bitfld.long 0x00 1.--2. " PIN_ADDR ,Address of the pin to be sampled" "0,2,4,6" else group.long 0xA8++0x03 line.long 0x00 "CHAN_CONFIG10,Channel 10 Configuration Register" bitfld.long 0x00 31. " DSI_OUT_EN ,DSI data output enable" "Disabled,Enabled" sif CPUIS("CY8C6*") textline " " bitfld.long 0x00 24. " NEG_ADDR_EN ,NEG_ADDR driver enable" "Disabled,Enabled" bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "SARMUX,,,,,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7" endif textline " " bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "ST0,ST1,ST2,ST3" bitfld.long 0x00 10. " AVG_EN ,Averaging enable" "Disabled,Enabled" sif !CPUIS("CY8C6*") textline " " bitfld.long 0x00 9. " RESOLUTION ,Resolution set" "MAXRES,SUBRES" endif textline " " bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " PORT_ADDR ,Address of the port that contains the pin to be sampled" "SARMUX,CTB0,CTB1,CTB2,CTB3,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" textline " " bitfld.long 0x00 0.--2. " PIN_ADDR ,Address of the pin to be sampled" "0,1,2,3,4,5,6,7" endif if (((per.l(ad:0x403A0000+0xAC))&0x100)==0x100) group.long 0xAC++0x03 line.long 0x00 "CHAN_CONFIG11,Channel 11 Configuration Register" bitfld.long 0x00 31. " DSI_OUT_EN ,DSI data output enable" "Disabled,Enabled" sif CPUIS("CY8C6*") textline " " bitfld.long 0x00 24. " NEG_ADDR_EN ,NEG_ADDR driver enable" "Disabled,Enabled" bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "SARMUX,,,,,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7" endif textline " " bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "ST0,ST1,ST2,ST3" bitfld.long 0x00 10. " AVG_EN ,Averaging enable" "Disabled,Enabled" sif !CPUIS("CY8C6*") textline " " bitfld.long 0x00 9. " RESOLUTION ,Resolution set" "MAXRES,SUBRES" endif textline " " bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " PORT_ADDR ,Address of the port that contains the pin to be sampled" "SARMUX,CTB0,CTB1,CTB2,CTB3,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" textline " " bitfld.long 0x00 1.--2. " PIN_ADDR ,Address of the pin to be sampled" "0,2,4,6" else group.long 0xAC++0x03 line.long 0x00 "CHAN_CONFIG11,Channel 11 Configuration Register" bitfld.long 0x00 31. " DSI_OUT_EN ,DSI data output enable" "Disabled,Enabled" sif CPUIS("CY8C6*") textline " " bitfld.long 0x00 24. " NEG_ADDR_EN ,NEG_ADDR driver enable" "Disabled,Enabled" bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "SARMUX,,,,,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7" endif textline " " bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "ST0,ST1,ST2,ST3" bitfld.long 0x00 10. " AVG_EN ,Averaging enable" "Disabled,Enabled" sif !CPUIS("CY8C6*") textline " " bitfld.long 0x00 9. " RESOLUTION ,Resolution set" "MAXRES,SUBRES" endif textline " " bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " PORT_ADDR ,Address of the port that contains the pin to be sampled" "SARMUX,CTB0,CTB1,CTB2,CTB3,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" textline " " bitfld.long 0x00 0.--2. " PIN_ADDR ,Address of the pin to be sampled" "0,1,2,3,4,5,6,7" endif if (((per.l(ad:0x403A0000+0xB0))&0x100)==0x100) group.long 0xB0++0x03 line.long 0x00 "CHAN_CONFIG12,Channel 12 Configuration Register" bitfld.long 0x00 31. " DSI_OUT_EN ,DSI data output enable" "Disabled,Enabled" sif CPUIS("CY8C6*") textline " " bitfld.long 0x00 24. " NEG_ADDR_EN ,NEG_ADDR driver enable" "Disabled,Enabled" bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "SARMUX,,,,,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7" endif textline " " bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "ST0,ST1,ST2,ST3" bitfld.long 0x00 10. " AVG_EN ,Averaging enable" "Disabled,Enabled" sif !CPUIS("CY8C6*") textline " " bitfld.long 0x00 9. " RESOLUTION ,Resolution set" "MAXRES,SUBRES" endif textline " " bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " PORT_ADDR ,Address of the port that contains the pin to be sampled" "SARMUX,CTB0,CTB1,CTB2,CTB3,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" textline " " bitfld.long 0x00 1.--2. " PIN_ADDR ,Address of the pin to be sampled" "0,2,4,6" else group.long 0xB0++0x03 line.long 0x00 "CHAN_CONFIG12,Channel 12 Configuration Register" bitfld.long 0x00 31. " DSI_OUT_EN ,DSI data output enable" "Disabled,Enabled" sif CPUIS("CY8C6*") textline " " bitfld.long 0x00 24. " NEG_ADDR_EN ,NEG_ADDR driver enable" "Disabled,Enabled" bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "SARMUX,,,,,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7" endif textline " " bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "ST0,ST1,ST2,ST3" bitfld.long 0x00 10. " AVG_EN ,Averaging enable" "Disabled,Enabled" sif !CPUIS("CY8C6*") textline " " bitfld.long 0x00 9. " RESOLUTION ,Resolution set" "MAXRES,SUBRES" endif textline " " bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " PORT_ADDR ,Address of the port that contains the pin to be sampled" "SARMUX,CTB0,CTB1,CTB2,CTB3,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" textline " " bitfld.long 0x00 0.--2. " PIN_ADDR ,Address of the pin to be sampled" "0,1,2,3,4,5,6,7" endif if (((per.l(ad:0x403A0000+0xB4))&0x100)==0x100) group.long 0xB4++0x03 line.long 0x00 "CHAN_CONFIG13,Channel 13 Configuration Register" bitfld.long 0x00 31. " DSI_OUT_EN ,DSI data output enable" "Disabled,Enabled" sif CPUIS("CY8C6*") textline " " bitfld.long 0x00 24. " NEG_ADDR_EN ,NEG_ADDR driver enable" "Disabled,Enabled" bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "SARMUX,,,,,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7" endif textline " " bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "ST0,ST1,ST2,ST3" bitfld.long 0x00 10. " AVG_EN ,Averaging enable" "Disabled,Enabled" sif !CPUIS("CY8C6*") textline " " bitfld.long 0x00 9. " RESOLUTION ,Resolution set" "MAXRES,SUBRES" endif textline " " bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " PORT_ADDR ,Address of the port that contains the pin to be sampled" "SARMUX,CTB0,CTB1,CTB2,CTB3,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" textline " " bitfld.long 0x00 1.--2. " PIN_ADDR ,Address of the pin to be sampled" "0,2,4,6" else group.long 0xB4++0x03 line.long 0x00 "CHAN_CONFIG13,Channel 13 Configuration Register" bitfld.long 0x00 31. " DSI_OUT_EN ,DSI data output enable" "Disabled,Enabled" sif CPUIS("CY8C6*") textline " " bitfld.long 0x00 24. " NEG_ADDR_EN ,NEG_ADDR driver enable" "Disabled,Enabled" bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "SARMUX,,,,,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7" endif textline " " bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "ST0,ST1,ST2,ST3" bitfld.long 0x00 10. " AVG_EN ,Averaging enable" "Disabled,Enabled" sif !CPUIS("CY8C6*") textline " " bitfld.long 0x00 9. " RESOLUTION ,Resolution set" "MAXRES,SUBRES" endif textline " " bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " PORT_ADDR ,Address of the port that contains the pin to be sampled" "SARMUX,CTB0,CTB1,CTB2,CTB3,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" textline " " bitfld.long 0x00 0.--2. " PIN_ADDR ,Address of the pin to be sampled" "0,1,2,3,4,5,6,7" endif if (((per.l(ad:0x403A0000+0xB8))&0x100)==0x100) group.long 0xB8++0x03 line.long 0x00 "CHAN_CONFIG14,Channel 14 Configuration Register" bitfld.long 0x00 31. " DSI_OUT_EN ,DSI data output enable" "Disabled,Enabled" sif CPUIS("CY8C6*") textline " " bitfld.long 0x00 24. " NEG_ADDR_EN ,NEG_ADDR driver enable" "Disabled,Enabled" bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "SARMUX,,,,,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7" endif textline " " bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "ST0,ST1,ST2,ST3" bitfld.long 0x00 10. " AVG_EN ,Averaging enable" "Disabled,Enabled" sif !CPUIS("CY8C6*") textline " " bitfld.long 0x00 9. " RESOLUTION ,Resolution set" "MAXRES,SUBRES" endif textline " " bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " PORT_ADDR ,Address of the port that contains the pin to be sampled" "SARMUX,CTB0,CTB1,CTB2,CTB3,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" textline " " bitfld.long 0x00 1.--2. " PIN_ADDR ,Address of the pin to be sampled" "0,2,4,6" else group.long 0xB8++0x03 line.long 0x00 "CHAN_CONFIG14,Channel 14 Configuration Register" bitfld.long 0x00 31. " DSI_OUT_EN ,DSI data output enable" "Disabled,Enabled" sif CPUIS("CY8C6*") textline " " bitfld.long 0x00 24. " NEG_ADDR_EN ,NEG_ADDR driver enable" "Disabled,Enabled" bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "SARMUX,,,,,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7" endif textline " " bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "ST0,ST1,ST2,ST3" bitfld.long 0x00 10. " AVG_EN ,Averaging enable" "Disabled,Enabled" sif !CPUIS("CY8C6*") textline " " bitfld.long 0x00 9. " RESOLUTION ,Resolution set" "MAXRES,SUBRES" endif textline " " bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " PORT_ADDR ,Address of the port that contains the pin to be sampled" "SARMUX,CTB0,CTB1,CTB2,CTB3,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" textline " " bitfld.long 0x00 0.--2. " PIN_ADDR ,Address of the pin to be sampled" "0,1,2,3,4,5,6,7" endif if (((per.l(ad:0x403A0000+0xBC))&0x100)==0x100) group.long 0xBC++0x03 line.long 0x00 "CHAN_CONFIG15,Channel 15 Configuration Register" bitfld.long 0x00 31. " DSI_OUT_EN ,DSI data output enable" "Disabled,Enabled" sif CPUIS("CY8C6*") textline " " bitfld.long 0x00 24. " NEG_ADDR_EN ,NEG_ADDR driver enable" "Disabled,Enabled" bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "SARMUX,,,,,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7" endif textline " " bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "ST0,ST1,ST2,ST3" bitfld.long 0x00 10. " AVG_EN ,Averaging enable" "Disabled,Enabled" sif !CPUIS("CY8C6*") textline " " bitfld.long 0x00 9. " RESOLUTION ,Resolution set" "MAXRES,SUBRES" endif textline " " bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " PORT_ADDR ,Address of the port that contains the pin to be sampled" "SARMUX,CTB0,CTB1,CTB2,CTB3,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" textline " " bitfld.long 0x00 1.--2. " PIN_ADDR ,Address of the pin to be sampled" "0,2,4,6" else group.long 0xBC++0x03 line.long 0x00 "CHAN_CONFIG15,Channel 15 Configuration Register" bitfld.long 0x00 31. " DSI_OUT_EN ,DSI data output enable" "Disabled,Enabled" sif CPUIS("CY8C6*") textline " " bitfld.long 0x00 24. " NEG_ADDR_EN ,NEG_ADDR driver enable" "Disabled,Enabled" bitfld.long 0x00 20.--22. " NEG_PORT_ADDR ,Address of the neg port that contains the pin to be sampled by this channel" "SARMUX,,,,,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" bitfld.long 0x00 16.--18. " NEG_PIN_ADDR ,Address of the neg pin to be sampled by this channel" "0,1,2,3,4,5,6,7" endif textline " " bitfld.long 0x00 12.--13. " SAMPLE_TIME_SEL ,Sample time select" "ST0,ST1,ST2,ST3" bitfld.long 0x00 10. " AVG_EN ,Averaging enable" "Disabled,Enabled" sif !CPUIS("CY8C6*") textline " " bitfld.long 0x00 9. " RESOLUTION ,Resolution set" "MAXRES,SUBRES" endif textline " " bitfld.long 0x00 8. " DIFFERENTIAL_EN ,Differential enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " PORT_ADDR ,Address of the port that contains the pin to be sampled" "SARMUX,CTB0,CTB1,CTB2,CTB3,AROUTE_VIRT2,AROUTE_VIRT1,SARMUX_VIRT" textline " " bitfld.long 0x00 0.--2. " PIN_ADDR ,Address of the pin to be sampled" "0,1,2,3,4,5,6,7" endif textline " " rgroup.long 0x100++0x03 line.long 0x00 "CHAN_WORK0,Channel 0 Working Data Register" sif CPUIS("CY8C6*") bitfld.long 0x00 31. " CHAN_WORK_UPDATED_MIR ,Channel 0 WORK data updated" "Not Updated,Updated" else bitfld.long 0x00 31. " CHAN_WORK_VALID_MIR ,Channel 0 WORK data valid" "Not valid,Valid" endif hexmask.long.word 0x00 0.--15. 1. " WORK ,SAR conversion working data" rgroup.long 0x104++0x03 line.long 0x00 "CHAN_WORK1,Channel 1 Working Data Register" sif CPUIS("CY8C6*") bitfld.long 0x00 31. " CHAN_WORK_UPDATED_MIR ,Channel 1 WORK data updated" "Not Updated,Updated" else bitfld.long 0x00 31. " CHAN_WORK_VALID_MIR ,Channel 1 WORK data valid" "Not valid,Valid" endif hexmask.long.word 0x00 0.--15. 1. " WORK ,SAR conversion working data" rgroup.long 0x108++0x03 line.long 0x00 "CHAN_WORK2,Channel 2 Working Data Register" sif CPUIS("CY8C6*") bitfld.long 0x00 31. " CHAN_WORK_UPDATED_MIR ,Channel 2 WORK data updated" "Not Updated,Updated" else bitfld.long 0x00 31. " CHAN_WORK_VALID_MIR ,Channel 2 WORK data valid" "Not valid,Valid" endif hexmask.long.word 0x00 0.--15. 1. " WORK ,SAR conversion working data" rgroup.long 0x10C++0x03 line.long 0x00 "CHAN_WORK3,Channel 3 Working Data Register" sif CPUIS("CY8C6*") bitfld.long 0x00 31. " CHAN_WORK_UPDATED_MIR ,Channel 3 WORK data updated" "Not Updated,Updated" else bitfld.long 0x00 31. " CHAN_WORK_VALID_MIR ,Channel 3 WORK data valid" "Not valid,Valid" endif hexmask.long.word 0x00 0.--15. 1. " WORK ,SAR conversion working data" rgroup.long 0x110++0x03 line.long 0x00 "CHAN_WORK4,Channel 4 Working Data Register" sif CPUIS("CY8C6*") bitfld.long 0x00 31. " CHAN_WORK_UPDATED_MIR ,Channel 4 WORK data updated" "Not Updated,Updated" else bitfld.long 0x00 31. " CHAN_WORK_VALID_MIR ,Channel 4 WORK data valid" "Not valid,Valid" endif hexmask.long.word 0x00 0.--15. 1. " WORK ,SAR conversion working data" rgroup.long 0x114++0x03 line.long 0x00 "CHAN_WORK5,Channel 5 Working Data Register" sif CPUIS("CY8C6*") bitfld.long 0x00 31. " CHAN_WORK_UPDATED_MIR ,Channel 5 WORK data updated" "Not Updated,Updated" else bitfld.long 0x00 31. " CHAN_WORK_VALID_MIR ,Channel 5 WORK data valid" "Not valid,Valid" endif hexmask.long.word 0x00 0.--15. 1. " WORK ,SAR conversion working data" rgroup.long 0x118++0x03 line.long 0x00 "CHAN_WORK6,Channel 6 Working Data Register" sif CPUIS("CY8C6*") bitfld.long 0x00 31. " CHAN_WORK_UPDATED_MIR ,Channel 6 WORK data updated" "Not Updated,Updated" else bitfld.long 0x00 31. " CHAN_WORK_VALID_MIR ,Channel 6 WORK data valid" "Not valid,Valid" endif hexmask.long.word 0x00 0.--15. 1. " WORK ,SAR conversion working data" rgroup.long 0x11C++0x03 line.long 0x00 "CHAN_WORK7,Channel 7 Working Data Register" sif CPUIS("CY8C6*") bitfld.long 0x00 31. " CHAN_WORK_UPDATED_MIR ,Channel 7 WORK data updated" "Not Updated,Updated" else bitfld.long 0x00 31. " CHAN_WORK_VALID_MIR ,Channel 7 WORK data valid" "Not valid,Valid" endif hexmask.long.word 0x00 0.--15. 1. " WORK ,SAR conversion working data" rgroup.long 0x120++0x03 line.long 0x00 "CHAN_WORK8,Channel 8 Working Data Register" sif CPUIS("CY8C6*") bitfld.long 0x00 31. " CHAN_WORK_UPDATED_MIR ,Channel 8 WORK data updated" "Not Updated,Updated" else bitfld.long 0x00 31. " CHAN_WORK_VALID_MIR ,Channel 8 WORK data valid" "Not valid,Valid" endif hexmask.long.word 0x00 0.--15. 1. " WORK ,SAR conversion working data" rgroup.long 0x124++0x03 line.long 0x00 "CHAN_WORK9,Channel 9 Working Data Register" sif CPUIS("CY8C6*") bitfld.long 0x00 31. " CHAN_WORK_UPDATED_MIR ,Channel 9 WORK data updated" "Not Updated,Updated" else bitfld.long 0x00 31. " CHAN_WORK_VALID_MIR ,Channel 9 WORK data valid" "Not valid,Valid" endif hexmask.long.word 0x00 0.--15. 1. " WORK ,SAR conversion working data" rgroup.long 0x128++0x03 line.long 0x00 "CHAN_WORK10,Channel 10 Working Data Register" sif CPUIS("CY8C6*") bitfld.long 0x00 31. " CHAN_WORK_UPDATED_MIR ,Channel 10 WORK data updated" "Not Updated,Updated" else bitfld.long 0x00 31. " CHAN_WORK_VALID_MIR ,Channel 10 WORK data valid" "Not valid,Valid" endif hexmask.long.word 0x00 0.--15. 1. " WORK ,SAR conversion working data" rgroup.long 0x12C++0x03 line.long 0x00 "CHAN_WORK11,Channel 11 Working Data Register" sif CPUIS("CY8C6*") bitfld.long 0x00 31. " CHAN_WORK_UPDATED_MIR ,Channel 11 WORK data updated" "Not Updated,Updated" else bitfld.long 0x00 31. " CHAN_WORK_VALID_MIR ,Channel 11 WORK data valid" "Not valid,Valid" endif hexmask.long.word 0x00 0.--15. 1. " WORK ,SAR conversion working data" rgroup.long 0x130++0x03 line.long 0x00 "CHAN_WORK12,Channel 12 Working Data Register" sif CPUIS("CY8C6*") bitfld.long 0x00 31. " CHAN_WORK_UPDATED_MIR ,Channel 12 WORK data updated" "Not Updated,Updated" else bitfld.long 0x00 31. " CHAN_WORK_VALID_MIR ,Channel 12 WORK data valid" "Not valid,Valid" endif hexmask.long.word 0x00 0.--15. 1. " WORK ,SAR conversion working data" rgroup.long 0x134++0x03 line.long 0x00 "CHAN_WORK13,Channel 13 Working Data Register" sif CPUIS("CY8C6*") bitfld.long 0x00 31. " CHAN_WORK_UPDATED_MIR ,Channel 13 WORK data updated" "Not Updated,Updated" else bitfld.long 0x00 31. " CHAN_WORK_VALID_MIR ,Channel 13 WORK data valid" "Not valid,Valid" endif hexmask.long.word 0x00 0.--15. 1. " WORK ,SAR conversion working data" rgroup.long 0x138++0x03 line.long 0x00 "CHAN_WORK14,Channel 14 Working Data Register" sif CPUIS("CY8C6*") bitfld.long 0x00 31. " CHAN_WORK_UPDATED_MIR ,Channel 14 WORK data updated" "Not Updated,Updated" else bitfld.long 0x00 31. " CHAN_WORK_VALID_MIR ,Channel 14 WORK data valid" "Not valid,Valid" endif hexmask.long.word 0x00 0.--15. 1. " WORK ,SAR conversion working data" rgroup.long 0x13C++0x03 line.long 0x00 "CHAN_WORK15,Channel 15 Working Data Register" sif CPUIS("CY8C6*") bitfld.long 0x00 31. " CHAN_WORK_UPDATED_MIR ,Channel 15 WORK data updated" "Not Updated,Updated" else bitfld.long 0x00 31. " CHAN_WORK_VALID_MIR ,Channel 15 WORK data valid" "Not valid,Valid" endif hexmask.long.word 0x00 0.--15. 1. " WORK ,SAR conversion working data" rgroup.long 0x180++0x03 line.long 0x00 "CHAN_RESULT0,Channel 0 Result Data Register" sif CPUIS("CY8C6*") bitfld.long 0x00 31. " CHAN_RESULT_UPDATED_MIR ,RESULT data updated" "Not Updated,Updated" else bitfld.long 0x00 31. " CHAN_RESULT_VALID_MIR ,RESULT data valid" "Not valid,Valid" endif bitfld.long 0x00 30. " RANGE_INTR_MIR ,Range detect interrupt" "No interrupt,Interrupt" bitfld.long 0x00 29. " SATURATE_INTR_MIR ,Saturate interrupt" "No interrupt,Interrupt" textline " " hexmask.long.word 0x00 0.--15. 1. " RESULT ,SAR conversion result" rgroup.long 0x184++0x03 line.long 0x00 "CHAN_RESULT1,Channel 1 Result Data Register" sif CPUIS("CY8C6*") bitfld.long 0x00 31. " CHAN_RESULT_UPDATED_MIR ,RESULT data updated" "Not Updated,Updated" else bitfld.long 0x00 31. " CHAN_RESULT_VALID_MIR ,RESULT data valid" "Not valid,Valid" endif bitfld.long 0x00 30. " RANGE_INTR_MIR ,Range detect interrupt" "No interrupt,Interrupt" bitfld.long 0x00 29. " SATURATE_INTR_MIR ,Saturate interrupt" "No interrupt,Interrupt" textline " " hexmask.long.word 0x00 0.--15. 1. " RESULT ,SAR conversion result" rgroup.long 0x188++0x03 line.long 0x00 "CHAN_RESULT2,Channel 2 Result Data Register" sif CPUIS("CY8C6*") bitfld.long 0x00 31. " CHAN_RESULT_UPDATED_MIR ,RESULT data updated" "Not Updated,Updated" else bitfld.long 0x00 31. " CHAN_RESULT_VALID_MIR ,RESULT data valid" "Not valid,Valid" endif bitfld.long 0x00 30. " RANGE_INTR_MIR ,Range detect interrupt" "No interrupt,Interrupt" bitfld.long 0x00 29. " SATURATE_INTR_MIR ,Saturate interrupt" "No interrupt,Interrupt" textline " " hexmask.long.word 0x00 0.--15. 1. " RESULT ,SAR conversion result" rgroup.long 0x18C++0x03 line.long 0x00 "CHAN_RESULT3,Channel 3 Result Data Register" sif CPUIS("CY8C6*") bitfld.long 0x00 31. " CHAN_RESULT_UPDATED_MIR ,RESULT data updated" "Not Updated,Updated" else bitfld.long 0x00 31. " CHAN_RESULT_VALID_MIR ,RESULT data valid" "Not valid,Valid" endif bitfld.long 0x00 30. " RANGE_INTR_MIR ,Range detect interrupt" "No interrupt,Interrupt" bitfld.long 0x00 29. " SATURATE_INTR_MIR ,Saturate interrupt" "No interrupt,Interrupt" textline " " hexmask.long.word 0x00 0.--15. 1. " RESULT ,SAR conversion result" rgroup.long 0x190++0x03 line.long 0x00 "CHAN_RESULT4,Channel 4 Result Data Register" sif CPUIS("CY8C6*") bitfld.long 0x00 31. " CHAN_RESULT_UPDATED_MIR ,RESULT data updated" "Not Updated,Updated" else bitfld.long 0x00 31. " CHAN_RESULT_VALID_MIR ,RESULT data valid" "Not valid,Valid" endif bitfld.long 0x00 30. " RANGE_INTR_MIR ,Range detect interrupt" "No interrupt,Interrupt" bitfld.long 0x00 29. " SATURATE_INTR_MIR ,Saturate interrupt" "No interrupt,Interrupt" textline " " hexmask.long.word 0x00 0.--15. 1. " RESULT ,SAR conversion result" rgroup.long 0x194++0x03 line.long 0x00 "CHAN_RESULT5,Channel 5 Result Data Register" sif CPUIS("CY8C6*") bitfld.long 0x00 31. " CHAN_RESULT_UPDATED_MIR ,RESULT data updated" "Not Updated,Updated" else bitfld.long 0x00 31. " CHAN_RESULT_VALID_MIR ,RESULT data valid" "Not valid,Valid" endif bitfld.long 0x00 30. " RANGE_INTR_MIR ,Range detect interrupt" "No interrupt,Interrupt" bitfld.long 0x00 29. " SATURATE_INTR_MIR ,Saturate interrupt" "No interrupt,Interrupt" textline " " hexmask.long.word 0x00 0.--15. 1. " RESULT ,SAR conversion result" rgroup.long 0x198++0x03 line.long 0x00 "CHAN_RESULT6,Channel 6 Result Data Register" sif CPUIS("CY8C6*") bitfld.long 0x00 31. " CHAN_RESULT_UPDATED_MIR ,RESULT data updated" "Not Updated,Updated" else bitfld.long 0x00 31. " CHAN_RESULT_VALID_MIR ,RESULT data valid" "Not valid,Valid" endif bitfld.long 0x00 30. " RANGE_INTR_MIR ,Range detect interrupt" "No interrupt,Interrupt" bitfld.long 0x00 29. " SATURATE_INTR_MIR ,Saturate interrupt" "No interrupt,Interrupt" textline " " hexmask.long.word 0x00 0.--15. 1. " RESULT ,SAR conversion result" rgroup.long 0x19C++0x03 line.long 0x00 "CHAN_RESULT7,Channel 7 Result Data Register" sif CPUIS("CY8C6*") bitfld.long 0x00 31. " CHAN_RESULT_UPDATED_MIR ,RESULT data updated" "Not Updated,Updated" else bitfld.long 0x00 31. " CHAN_RESULT_VALID_MIR ,RESULT data valid" "Not valid,Valid" endif bitfld.long 0x00 30. " RANGE_INTR_MIR ,Range detect interrupt" "No interrupt,Interrupt" bitfld.long 0x00 29. " SATURATE_INTR_MIR ,Saturate interrupt" "No interrupt,Interrupt" textline " " hexmask.long.word 0x00 0.--15. 1. " RESULT ,SAR conversion result" rgroup.long 0x1A0++0x03 line.long 0x00 "CHAN_RESULT8,Channel 8 Result Data Register" sif CPUIS("CY8C6*") bitfld.long 0x00 31. " CHAN_RESULT_UPDATED_MIR ,RESULT data updated" "Not Updated,Updated" else bitfld.long 0x00 31. " CHAN_RESULT_VALID_MIR ,RESULT data valid" "Not valid,Valid" endif bitfld.long 0x00 30. " RANGE_INTR_MIR ,Range detect interrupt" "No interrupt,Interrupt" bitfld.long 0x00 29. " SATURATE_INTR_MIR ,Saturate interrupt" "No interrupt,Interrupt" textline " " hexmask.long.word 0x00 0.--15. 1. " RESULT ,SAR conversion result" rgroup.long 0x1A4++0x03 line.long 0x00 "CHAN_RESULT9,Channel 9 Result Data Register" sif CPUIS("CY8C6*") bitfld.long 0x00 31. " CHAN_RESULT_UPDATED_MIR ,RESULT data updated" "Not Updated,Updated" else bitfld.long 0x00 31. " CHAN_RESULT_VALID_MIR ,RESULT data valid" "Not valid,Valid" endif bitfld.long 0x00 30. " RANGE_INTR_MIR ,Range detect interrupt" "No interrupt,Interrupt" bitfld.long 0x00 29. " SATURATE_INTR_MIR ,Saturate interrupt" "No interrupt,Interrupt" textline " " hexmask.long.word 0x00 0.--15. 1. " RESULT ,SAR conversion result" rgroup.long 0x1A8++0x03 line.long 0x00 "CHAN_RESULT10,Channel 10 Result Data Register" sif CPUIS("CY8C6*") bitfld.long 0x00 31. " CHAN_RESULT_UPDATED_MIR ,RESULT data updated" "Not Updated,Updated" else bitfld.long 0x00 31. " CHAN_RESULT_VALID_MIR ,RESULT data valid" "Not valid,Valid" endif bitfld.long 0x00 30. " RANGE_INTR_MIR ,Range detect interrupt" "No interrupt,Interrupt" bitfld.long 0x00 29. " SATURATE_INTR_MIR ,Saturate interrupt" "No interrupt,Interrupt" textline " " hexmask.long.word 0x00 0.--15. 1. " RESULT ,SAR conversion result" rgroup.long 0x1AC++0x03 line.long 0x00 "CHAN_RESULT11,Channel 11 Result Data Register" sif CPUIS("CY8C6*") bitfld.long 0x00 31. " CHAN_RESULT_UPDATED_MIR ,RESULT data updated" "Not Updated,Updated" else bitfld.long 0x00 31. " CHAN_RESULT_VALID_MIR ,RESULT data valid" "Not valid,Valid" endif bitfld.long 0x00 30. " RANGE_INTR_MIR ,Range detect interrupt" "No interrupt,Interrupt" bitfld.long 0x00 29. " SATURATE_INTR_MIR ,Saturate interrupt" "No interrupt,Interrupt" textline " " hexmask.long.word 0x00 0.--15. 1. " RESULT ,SAR conversion result" rgroup.long 0x1B0++0x03 line.long 0x00 "CHAN_RESULT12,Channel 12 Result Data Register" sif CPUIS("CY8C6*") bitfld.long 0x00 31. " CHAN_RESULT_UPDATED_MIR ,RESULT data updated" "Not Updated,Updated" else bitfld.long 0x00 31. " CHAN_RESULT_VALID_MIR ,RESULT data valid" "Not valid,Valid" endif bitfld.long 0x00 30. " RANGE_INTR_MIR ,Range detect interrupt" "No interrupt,Interrupt" bitfld.long 0x00 29. " SATURATE_INTR_MIR ,Saturate interrupt" "No interrupt,Interrupt" textline " " hexmask.long.word 0x00 0.--15. 1. " RESULT ,SAR conversion result" rgroup.long 0x1B4++0x03 line.long 0x00 "CHAN_RESULT13,Channel 13 Result Data Register" sif CPUIS("CY8C6*") bitfld.long 0x00 31. " CHAN_RESULT_UPDATED_MIR ,RESULT data updated" "Not Updated,Updated" else bitfld.long 0x00 31. " CHAN_RESULT_VALID_MIR ,RESULT data valid" "Not valid,Valid" endif bitfld.long 0x00 30. " RANGE_INTR_MIR ,Range detect interrupt" "No interrupt,Interrupt" bitfld.long 0x00 29. " SATURATE_INTR_MIR ,Saturate interrupt" "No interrupt,Interrupt" textline " " hexmask.long.word 0x00 0.--15. 1. " RESULT ,SAR conversion result" rgroup.long 0x1B8++0x03 line.long 0x00 "CHAN_RESULT14,Channel 14 Result Data Register" sif CPUIS("CY8C6*") bitfld.long 0x00 31. " CHAN_RESULT_UPDATED_MIR ,RESULT data updated" "Not Updated,Updated" else bitfld.long 0x00 31. " CHAN_RESULT_VALID_MIR ,RESULT data valid" "Not valid,Valid" endif bitfld.long 0x00 30. " RANGE_INTR_MIR ,Range detect interrupt" "No interrupt,Interrupt" bitfld.long 0x00 29. " SATURATE_INTR_MIR ,Saturate interrupt" "No interrupt,Interrupt" textline " " hexmask.long.word 0x00 0.--15. 1. " RESULT ,SAR conversion result" rgroup.long 0x1BC++0x03 line.long 0x00 "CHAN_RESULT15,Channel 15 Result Data Register" sif CPUIS("CY8C6*") bitfld.long 0x00 31. " CHAN_RESULT_UPDATED_MIR ,RESULT data updated" "Not Updated,Updated" else bitfld.long 0x00 31. " CHAN_RESULT_VALID_MIR ,RESULT data valid" "Not valid,Valid" endif bitfld.long 0x00 30. " RANGE_INTR_MIR ,Range detect interrupt" "No interrupt,Interrupt" bitfld.long 0x00 29. " SATURATE_INTR_MIR ,Saturate interrupt" "No interrupt,Interrupt" textline " " hexmask.long.word 0x00 0.--15. 1. " RESULT ,SAR conversion result" textline " " sif CPUIS("CY8C6*") rgroup.long 0x200++0x07 line.long 0x00 "CHAN_WORK_UPDATED,Channel Working Data Register Updated Bits" bitfld.long 0x00 15. " CHAN_WORK_UPDATED[15] ,Channel 15 WORK data updated" "Not updated,Updated" bitfld.long 0x00 14. " [14] ,Channel 14 WORK data updated" "Not updated,Updated" bitfld.long 0x00 13. " [13] ,Channel 13 WORK data updated" "Not updated,Updated" textline " " bitfld.long 0x00 12. " [12] ,Channel 12 WORK data updated" "Not updated,Updated" bitfld.long 0x00 11. " [11] ,Channel 11 WORK data updated" "Not updated,Updated" bitfld.long 0x00 10. " [10] ,Channel 10 WORK data updated" "Not updated,Updated" textline " " bitfld.long 0x00 9. " [9] ,Channel 9 WORK data updated" "Not updated,Updated" bitfld.long 0x00 8. " [8] ,Channel 8 WORK data updated" "Not updated,Updated" bitfld.long 0x00 7. " [7] ,Channel 7 WORK data updated" "Not updated,Updated" textline " " bitfld.long 0x00 6. " [6] ,Channel 6 WORK data updated" "Not updated,Updated" bitfld.long 0x00 5. " [5] ,Channel 5 WORK data updated" "Not updated,Updated" bitfld.long 0x00 4. " [4] ,Channel 4 WORK data updated" "Not updated,Updated" textline " " bitfld.long 0x00 3. " [3] ,Channel 3 WORK data updated" "Not updated,Updated" bitfld.long 0x00 2. " [2] ,Channel 2 WORK data updated" "Not updated,Updated" bitfld.long 0x00 1. " [1] ,Channel 1 WORK data updated" "Not updated,Updated" textline " " bitfld.long 0x00 0. " [0] ,Channel 0 WORK data updated" "Not updated,Updated" line.long 0x04 "CHAN_RESULT_UPDATED,Channel Result Data Register Updated Bits" bitfld.long 0x04 15. " CHAN_RESULT_UPDATED[15] ,Channel 15 RESULT data updated" "Not updated,Updated" bitfld.long 0x04 14. " [14] ,Channel 14 RESULT data updated" "Not updated,Updated" bitfld.long 0x04 13. " [13] ,Channel 13 RESULT data updated" "Not updated,Updated" textline " " bitfld.long 0x04 12. " [12] ,Channel 12 RESULT data updated" "Not updated,Updated" bitfld.long 0x04 11. " [11] ,Channel 11 RESULT data updated" "Not updated,Updated" bitfld.long 0x04 10. " [10] ,Channel 10 RESULT data updated" "Not updated,Updated" textline " " bitfld.long 0x04 9. " [9] ,Channel 9 RESULT data updated" "Not updated,Updated" bitfld.long 0x04 8. " [8] ,Channel 8 RESULT data updated" "Not updated,Updated" bitfld.long 0x04 7. " [7] ,Channel 7 RESULT data updated" "Not updated,Updated" textline " " bitfld.long 0x04 6. " [6] ,Channel 6 RESULT data updated" "Not updated,Updated" bitfld.long 0x04 5. " [5] ,Channel 5 RESULT data updated" "Not updated,Updated" bitfld.long 0x04 4. " [4] ,Channel 4 RESULT data updated" "Not updated,Updated" textline " " bitfld.long 0x04 3. " [3] ,Channel 3 RESULT data updated" "Not updated,Updated" bitfld.long 0x04 2. " [2] ,Channel 2 RESULT data updated" "Not updated,Updated" bitfld.long 0x04 1. " [1] ,Channel 1 RESULT data updated" "Not updated,Updated" textline " " bitfld.long 0x04 0. " [0] ,Channel 0 RESULT data updated" "Not updated,Updated" else rgroup.long 0x200++0x07 line.long 0x00 "CHAN_WORK_VALID,Channel Working Data Register Valid Bits" bitfld.long 0x00 15. " CHAN_WORK_VALID[15] ,Channel 15 WORK data valid" "Not valid,Valid" bitfld.long 0x00 14. " [14] ,Channel 14 WORK data valid" "Not valid,Valid" bitfld.long 0x00 13. " [13] ,Channel 13 WORK data valid" "Not valid,Valid" textline " " bitfld.long 0x00 12. " [12] ,Channel 12 WORK data valid" "Not valid,Valid" bitfld.long 0x00 11. " [11] ,Channel 11 WORK data valid" "Not valid,Valid" bitfld.long 0x00 10. " [10] ,Channel 10 WORK data valid" "Not valid,Valid" textline " " bitfld.long 0x00 9. " [9] ,Channel 9 WORK data valid" "Not valid,Valid" bitfld.long 0x00 8. " [8] ,Channel 8 WORK data valid" "Not valid,Valid" bitfld.long 0x00 7. " [7] ,Channel 7 WORK data valid" "Not valid,Valid" textline " " bitfld.long 0x00 6. " [6] ,Channel 6 WORK data valid" "Not valid,Valid" bitfld.long 0x00 5. " [5] ,Channel 5 WORK data valid" "Not valid,Valid" bitfld.long 0x00 4. " [4] ,Channel 4 WORK data valid" "Not valid,Valid" textline " " bitfld.long 0x00 3. " [3] ,Channel 3 WORK data valid" "Not valid,Valid" bitfld.long 0x00 2. " [2] ,Channel 2 WORK data valid" "Not valid,Valid" bitfld.long 0x00 1. " [1] ,Channel 1 WORK data valid" "Not valid,Valid" textline " " bitfld.long 0x00 0. " [0] ,Channel 0 WORK data valid" "Not valid,Valid" line.long 0x04 "CHAN_RESULT_VALID,Channel Result Data Register Valid Bits" bitfld.long 0x04 15. " CHAN_RESULT_VALID[15] ,Channel 15 RESULT data valid" "Not valid,Valid" bitfld.long 0x04 14. " [14] ,Channel 14 RESULT data valid" "Not valid,Valid" bitfld.long 0x04 13. " [13] ,Channel 13 RESULT data valid" "Not valid,Valid" textline " " bitfld.long 0x04 12. " [12] ,Channel 12 RESULT data valid" "Not valid,Valid" bitfld.long 0x04 11. " [11] ,Channel 11 RESULT data valid" "Not valid,Valid" bitfld.long 0x04 10. " [10] ,Channel 10 RESULT data valid" "Not valid,Valid" textline " " bitfld.long 0x04 9. " [9] ,Channel 9 RESULT data valid" "Not valid,Valid" bitfld.long 0x04 8. " [8] ,Channel 8 RESULT data valid" "Not valid,Valid" bitfld.long 0x04 7. " [7] ,Channel 7 RESULT data valid" "Not valid,Valid" textline " " bitfld.long 0x04 6. " [6] ,Channel 6 RESULT data valid" "Not valid,Valid" bitfld.long 0x04 5. " [5] ,Channel 5 RESULT data valid" "Not valid,Valid" bitfld.long 0x04 4. " [4] ,Channel 4 RESULT data valid" "Not valid,Valid" textline " " bitfld.long 0x04 3. " [3] ,Channel 3 RESULT data valid" "Not valid,Valid" bitfld.long 0x04 2. " [2] ,Channel 2 RESULT data valid" "Not valid,Valid" bitfld.long 0x04 1. " [1] ,Channel 1 RESULT data valid" "Not valid,Valid" textline " " bitfld.long 0x04 0. " [0] ,Channel 0 RESULT data valid" "Not valid,Valid" endif sif !CPUIS("CY8C6*") if (((per.l(ad:0x403A0000+0x208))&0x80000000)==0x80000000) rgroup.long 0x208++0x03 line.long 0x00 "STATUS,Current Status of Internal SAR Registers" bitfld.long 0x00 31. " BUSY ,SAR with a conversion busy" "Not busy,Busy" bitfld.long 0x00 30. " SW_VREF_NEG ,Current switch status" "0,1" bitfld.long 0x00 0.--4. " CUR_CHAN ,Current channel being sampled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." else rgroup.long 0x208++0x03 line.long 0x00 "STATUS,Current Status of Internal SAR Registers" bitfld.long 0x00 31. " BUSY ,SAR with a conversion busy" "Not busy,Busy" bitfld.long 0x00 30. " SW_VREF_NEG ,Current switch status" "0,1" endif rgroup.long 0x20C++0x03 line.long 0x00 "AVG_STAT,Current Averaging Status Register" hexmask.long.byte 0x00 24.--31. 1. " CUR_AVG_CNT ,Current value of the averaging counter" hexmask.long.tbyte 0x00 0.--19. 1. " CUR_AVG_ACCU ,Current value of the averaging accumulator" endif sif CPUIS("CY8C6*") group.long 0x210++0x0B line.long 0x00 "INTR,Interrupt Request Register" eventfld.long 0x00 7. " INJ_COLLISION_INTR ,Injection collision interrupt" "No interrupt,Interrupt" eventfld.long 0x00 6. " INJ_RANGE_INTR ,Injection range detect interrupt" "No interrupt,Interrupt" eventfld.long 0x00 5. " INJ_SATURATE_INTR ,Injection saturation interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 4. " INJ_EOC_INTR ,Injection end of conversion interrupt" "No interrupt,Interrupt" eventfld.long 0x00 3. " DSI_COLLISION_INTR ,DSI collision interrupt" "No interrupt,Interrupt" eventfld.long 0x00 2. " FW_COLLISION_INTR ,Firmware collision interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 1. " OVERFLOW_INTR ,Overflow interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " EOS_INTR ,End of scan interrupt" "No interrupt,Interrupt" line.long 0x04 "INTR_SET,Interrupt Set Request Register" bitfld.long 0x04 7. " INJ_COLLISION_INTR ,Set INTR.INJ_COLLISION_INTR" "No effect,Set" bitfld.long 0x04 6. " INJ_RANGE_INTR ,Set INTR.INJ_RANGE_INTR" "No effect,Set" bitfld.long 0x04 5. " INJ_SATURATE_INTR ,Set INTR.INJ_SATURATE_INTR" "No effect,Set" textline " " bitfld.long 0x04 4. " INJ_EOC_INTR ,Set INTR.INJ_EOC_INTR" "No effect,Set" bitfld.long 0x04 3. " DSI_COLLISION_INTR ,Set INTR.DSI_COLLISION_INTR" "No effect,Set" bitfld.long 0x04 2. " FW_COLLISION_INTR ,Set INTR.FW_COLLISION_INTR" "No effect,Set" textline " " bitfld.long 0x04 1. " OVERFLOW_INTR ,Set INTR.OVERFLOW_INTR" "No effect,Set" bitfld.long 0x04 0. " EOS_INTR ,Set INTR.EOS_INTR" "No effect,Set" line.long 0x08 "INTR_MASK,Interrupt Mask Register" bitfld.long 0x08 7. " INJ_COLLISION_MASK ,Injection collision interrupt mask" "Masked,Not masked" bitfld.long 0x08 6. " INJ_RANGE_MASK ,Injection range detect interrupt mask" "Masked,Not masked" bitfld.long 0x08 5. " INJ_SATURATE_MASK ,Injection saturation interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x08 4. " INJ_EOC_MASK ,Injection end of conversion interrupt mask" "Masked,Not masked" bitfld.long 0x08 3. " DSI_COLLISION_MASK ,DSI collision interrupt mask" "Masked,Not masked" bitfld.long 0x08 2. " FW_COLLISION_MASK ,Firmware collision mask" "Masked,Not masked" textline " " bitfld.long 0x08 1. " OVERFLOW_MASK ,Overflow interrupt mask" "Masked,Not masked" bitfld.long 0x08 0. " EOS_MASK ,End of scan interrupt mask" "Masked,Not masked" else group.long 0x210++0x03 line.long 0x00 "INTR_SET/CLR,Interrupt Request Register" setclrfld.long 0x00 7. 0x04 7. 0x00 7. " INJ_COLLISION_INTR ,Injection collision interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 6. 0x04 6. 0x00 6. " INJ_RANGE_INTR ,Injection range detect interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 5. 0x04 5. 0x00 5. " INJ_SATURATE_INTR ,Injection saturation interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 4. 0x04 4. 0x00 4. " INJ_EOC_INTR ,Injection end of conversion interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 3. 0x04 3. 0x00 3. " DSI_COLLISION_INTR ,DSI collision interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 2. 0x04 2. 0x00 2. " FW_COLLISION_INTR ,Firmware collision interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 1. 0x04 1. 0x00 1. " OVERFLOW_INTR ,Overflow interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 0. 0x04 0. 0x00 0. " EOS_INTR ,End of scan interrupt" "No interrupt,Interrupt" group.long 0x218++0x03 line.long 0x00 "INTR_MASK,Interrupt Mask Register" bitfld.long 0x00 7. " INJ_COLLISION_MASK ,Injection collision interrupt mask" "Not masked,Masked" bitfld.long 0x00 6. " INJ_RANGE_MASK ,Injection range detect interrupt mask" "Not masked,Masked" bitfld.long 0x00 5. " INJ_SATURATE_MASK ,Injection saturation interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 4. " INJ_EOC_MASK ,Injection end of conversion interrupt mask" "Not masked,Masked" bitfld.long 0x00 3. " DSI_COLLISION_MASK ,DSI collision interrupt mask" "Not masked,Masked" bitfld.long 0x00 2. " FW_COLLISION_MASK ,Firmware collision mask" "Not masked,Masked" textline " " bitfld.long 0x00 1. " OVERFLOW_MASK ,Overflow interrupt mask" "Not masked,Masked" bitfld.long 0x00 0. " EOS_MASK ,End of scan interrupt mask" "Not masked,Masked" endif rgroup.long 0x21C++0x03 line.long 0x00 "INTR_MASKED,Interrupt Masked Request Register" bitfld.long 0x00 7. " INJ_COLLISION_MASKED ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 6. " INJ_RANGE_MASKED ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 5. " INJ_SATURATE_MASKED ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" textline " " bitfld.long 0x00 4. " INJ_EOC_MASKED ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 3. " DSI_COLLISION_MASKED ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 2. " FW_COLLISION_MASKED ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " OVERFLOW_MASKED ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 0. " EOS_MASKED ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" sif CPUIS("CY8C6*") group.long 0x220++0x0B line.long 0x00 "SATURATE_INTR,Saturate Interrupt Request Register" eventfld.long 0x00 15. " SATURATE_INTR[15] ,Channel 15 saturate interrupt" "No interrupt,Interrupt" eventfld.long 0x00 14. " [14] ,Channel 14 saturate interrupt" "No interrupt,Interrupt" eventfld.long 0x00 13. " [13] ,Channel 13 saturate interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 12. " [12] ,Channel 12 saturate interrupt" "No interrupt,Interrupt" eventfld.long 0x00 11. " [11] ,Channel 11 saturate interrupt" "No interrupt,Interrupt" eventfld.long 0x00 10. " [10] ,Channel 10 saturate interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 9. " [9] ,Channel 9 saturate interrupt" "No interrupt,Interrupt" eventfld.long 0x00 8. " [8] ,Channel 8 saturate interrupt" "No interrupt,Interrupt" eventfld.long 0x00 7. " [7] ,Channel 7 saturate interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 6. " [6] ,Channel 6 saturate interrupt" "No interrupt,Interrupt" eventfld.long 0x00 5. " [5] ,Channel 5 saturate interrupt" "No interrupt,Interrupt" eventfld.long 0x00 4. " [4] ,Channel 4 saturate interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " [3] ,Channel 3 saturate interrupt" "No interrupt,Interrupt" eventfld.long 0x00 2. " [2] ,Channel 2 saturate interrupt" "No interrupt,Interrupt" eventfld.long 0x00 1. " [1] ,Channel 1 saturate interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " [0] ,Channel 0 saturate interrupt" "No interrupt,Interrupt" line.long 0x04 "SATURATE_INTR_SET,Saturate Interrupt Set Request Register" bitfld.long 0x04 15. " SATURATE_SET[15] ,Set SATURATE_INTR.SATURATE_INTR[15]" "No effect,Set" bitfld.long 0x04 14. " [14] ,Set SATURATE_INTR.SATURATE_INTR[14]" "No effect,Set" bitfld.long 0x04 13. " [13] ,Set SATURATE_INTR.SATURATE_INTR[13]" "No effect,Set" textline " " bitfld.long 0x04 12. " [12] ,Set SATURATE_INTR.SATURATE_INTR[12]" "No effect,Set" bitfld.long 0x04 11. " [11] ,Set SATURATE_INTR.SATURATE_INTR[11]" "No effect,Set" bitfld.long 0x04 10. " [10] ,Set SATURATE_INTR.SATURATE_INTR[10]" "No effect,Set" textline " " bitfld.long 0x04 9. " [9] ,Set SATURATE_INTR.SATURATE_INTR[9]" "No effect,Set" bitfld.long 0x04 8. " [8] ,Set SATURATE_INTR.SATURATE_INTR[8]" "No effect,Set" bitfld.long 0x04 7. " [7] ,Set SATURATE_INTR.SATURATE_INTR[7]" "No effect,Set" textline " " bitfld.long 0x04 6. " [6] ,Set SATURATE_INTR.SATURATE_INTR[6]" "No effect,Set" bitfld.long 0x04 5. " [5] ,Set SATURATE_INTR.SATURATE_INTR[5]" "No effect,Set" bitfld.long 0x04 4. " [4] ,Set SATURATE_INTR.SATURATE_INTR[4]" "No effect,Set" textline " " bitfld.long 0x04 3. " [3] ,Set SATURATE_INTR.SATURATE_INTR[3]" "No effect,Set" bitfld.long 0x04 2. " [2] ,Set SATURATE_INTR.SATURATE_INTR[2]" "No effect,Set" bitfld.long 0x04 1. " [1] ,Set SATURATE_INTR.SATURATE_INTR[1]" "No effect,Set" textline " " bitfld.long 0x04 0. " [0] ,Set SATURATE_INTR.SATURATE_INTR[0]" "No effect,Set" line.long 0x08 "SATURATE_INTR_MASK,Saturate Interrupt Mask Register" bitfld.long 0x08 15. " SATURATE_MASK[15] ,Channel 15 saturate interrupt mask" "Masked,Not masked" bitfld.long 0x08 14. " [14] ,Channel 14 saturate interrupt mask" "Masked,Not masked" bitfld.long 0x08 13. " [13] ,Channel 13 saturate interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x08 12. " [12] ,Channel 12 saturate interrupt mask" "Masked,Not masked" bitfld.long 0x08 11. " [11] ,Channel 11 saturate interrupt mask" "Masked,Not masked" bitfld.long 0x08 10. " [10] ,Channel 10 saturate interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x08 9. " [9] ,Channel 9 saturate interrupt mask" "Masked,Not masked" bitfld.long 0x08 8. " [8] ,Channel 8 saturate interrupt mask" "Masked,Not masked" bitfld.long 0x08 7. " [7] ,Channel 7 saturate interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x08 6. " [6] ,Channel 6 saturate interrupt mask" "Masked,Not masked" bitfld.long 0x08 5. " [5] ,Channel 5 saturate interrupt mask" "Masked,Not masked" bitfld.long 0x08 4. " [4] ,Channel 4 saturate interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x08 3. " [3] ,Channel 3 saturate interrupt mask" "Masked,Not masked" bitfld.long 0x08 2. " [2] ,Channel 2 saturate interrupt mask" "Masked,Not masked" bitfld.long 0x08 1. " [1] ,Channel 1 saturate interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x08 0. " [0] ,Channel 0 saturate interrupt mask" "Masked,Not masked" else group.long 0x220++0x03 line.long 0x00 "SATURATE_INTR_SET/CLR,Saturate Interrupt Request Register" setclrfld.long 0x00 15. 0x04 15. 0x00 15. " SATURATE_INTR[15] ,Channel 15 saturate interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 14. 0x04 14. 0x00 14. " [14] ,Channel 14 saturate interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 13. 0x04 13. 0x00 13. " [13] ,Channel 13 saturate interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 12. 0x04 12. 0x00 12. " [12] ,Channel 12 saturate interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 11. 0x04 11. 0x00 11. " [11] ,Channel 11 saturate interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 10. 0x04 10. 0x00 10. " [10] ,Channel 10 saturate interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 9. 0x04 9. 0x00 9. " [9] ,Channel 9 saturate interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 8. 0x04 8. 0x00 8. " [8] ,Channel 8 saturate interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 7. 0x04 7. 0x00 7. " [7] ,Channel 7 saturate interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 6. 0x04 6. 0x00 6. " [6] ,Channel 6 saturate interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 5. 0x04 5. 0x00 5. " [5] ,Channel 5 saturate interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 4. 0x04 4. 0x00 4. " [4] ,Channel 4 saturate interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 3. 0x04 3. 0x00 3. " [3] ,Channel 3 saturate interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 2. 0x04 2. 0x00 2. " [2] ,Channel 2 saturate interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 1. 0x04 1. 0x00 1. " [1] ,Channel 1 saturate interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 0. 0x04 0. 0x00 0. " [0] ,Channel 0 saturate interrupt" "No interrupt,Interrupt" group.long 0x228++0x03 line.long 0x00 "SATURATE_INTR_MASK,Saturate Interrupt Mask Register" bitfld.long 0x00 15. " SATURATE_MASK[15] ,Channel 15 saturate interrupt mask" "Not masked,Masked" bitfld.long 0x00 14. " [14] ,Channel 14 saturate interrupt mask" "Not masked,Masked" bitfld.long 0x00 13. " [13] ,Channel 13 saturate interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 12. " [12] ,Channel 12 saturate interrupt mask" "Not masked,Masked" bitfld.long 0x00 11. " [11] ,Channel 11 saturate interrupt mask" "Not masked,Masked" bitfld.long 0x00 10. " [10] ,Channel 10 saturate interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 9. " [9] ,Channel 9 saturate interrupt mask" "Not masked,Masked" bitfld.long 0x00 8. " [8] ,Channel 8 saturate interrupt mask" "Not masked,Masked" bitfld.long 0x00 7. " [7] ,Channel 7 saturate interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 6. " [6] ,Channel 6 saturate interrupt mask" "Not masked,Masked" bitfld.long 0x00 5. " [5] ,Channel 5 saturate interrupt mask" "Not masked,Masked" bitfld.long 0x00 4. " [4] ,Channel 4 saturate interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 3. " [3] ,Channel 3 saturate interrupt mask" "Not masked,Masked" bitfld.long 0x00 2. " [2] ,Channel 2 saturate interrupt mask" "Not masked,Masked" bitfld.long 0x00 1. " [1] ,Channel 1 saturate interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 0. " [0] ,Channel 0 saturate interrupt mask" "Not masked,Masked" endif rgroup.long 0x22C++0x03 line.long 0x00 "SATURATE_INTR_MASKED,Saturate Interrupt Masked Request Register" bitfld.long 0x00 15. " SATURATE_MASKED[15] ,Channel 15 saturate interrupt masked" "No interrupt,Interrupt" bitfld.long 0x00 14. " [14] ,Channel 14 saturate interrupt masked" "No interrupt,Interrupt" bitfld.long 0x00 13. " [13] ,Channel 13 saturate interrupt masked" "No interrupt,Interrupt" textline " " bitfld.long 0x00 12. " [12] ,Channel 12 saturate interrupt masked" "No interrupt,Interrupt" bitfld.long 0x00 11. " [11] ,Channel 11 saturate interrupt masked" "No interrupt,Interrupt" bitfld.long 0x00 10. " [10] ,Channel 10 saturate interrupt masked" "No interrupt,Interrupt" textline " " bitfld.long 0x00 9. " [9] ,Channel 9 saturate interrupt masked" "No interrupt,Interrupt" bitfld.long 0x00 8. " [8] ,Channel 8 saturate interrupt masked" "No interrupt,Interrupt" bitfld.long 0x00 7. " [7] ,Channel 7 saturate interrupt masked" "No interrupt,Interrupt" textline " " bitfld.long 0x00 6. " [6] ,Channel 6 saturate interrupt masked" "No interrupt,Interrupt" bitfld.long 0x00 5. " [5] ,Channel 5 saturate interrupt masked" "No interrupt,Interrupt" bitfld.long 0x00 4. " [4] ,Channel 4 saturate interrupt masked" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " [3] ,Channel 3 saturate interrupt masked" "No interrupt,Interrupt" bitfld.long 0x00 2. " [2] ,Channel 2 saturate interrupt masked" "No interrupt,Interrupt" bitfld.long 0x00 1. " [1] ,Channel 1 saturate interrupt masked" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " [0] ,Channel 0 saturate interrupt masked" "No interrupt,Interrupt" sif CPUIS("CY8C6*") group.long 0x230++0x0B line.long 0x00 "RANGE_INTR,Range Detect Interrupt Request Register" eventfld.long 0x00 15. " RANGE_INTR[15] ,Channel 15 range detect interrupt" "No interrupt,Interrupt" eventfld.long 0x00 14. " [14] ,Channel 14 range detect interrupt" "No interrupt,Interrupt" eventfld.long 0x00 13. " [13] ,Channel 13 range detect interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 12. " [12] ,Channel 12 range detect interrupt" "No interrupt,Interrupt" eventfld.long 0x00 11. " [11] ,Channel 11 range detect interrupt" "No interrupt,Interrupt" eventfld.long 0x00 10. " [10] ,Channel 10 range detect interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 9. " [9] ,Channel 9 range detect interrupt" "No interrupt,Interrupt" eventfld.long 0x00 8. " [8] ,Channel 8 range detect interrupt" "No interrupt,Interrupt" eventfld.long 0x00 7. " [7] ,Channel 7 range detect interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 6. " [6] ,Channel 6 range detect interrupt" "No interrupt,Interrupt" eventfld.long 0x00 5. " [5] ,Channel 5 range detect interrupt" "No interrupt,Interrupt" eventfld.long 0x00 4. " [4] ,Channel 4 range detect interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " [3] ,Channel 3 range detect interrupt" "No interrupt,Interrupt" eventfld.long 0x00 2. " [2] ,Channel 2 range detect interrupt" "No interrupt,Interrupt" eventfld.long 0x00 1. " [1] ,Channel 1 range detect interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " [0] ,Channel 0 range detect interrupt" "No interrupt,Interrupt" line.long 0x04 "RANGE_INTR_SET,Range Detect Interrupt Set Request Register" bitfld.long 0x04 15. " RANGE_SET[15] ,Set INTR.RANGE_INTR[15]" "No effect,Set" bitfld.long 0x04 14. " [14] ,Set INTR.RANGE_INTR[14]" "No effect,Set" bitfld.long 0x04 13. " [13] ,Set INTR.RANGE_INTR[13]" "No effect,Set" textline " " bitfld.long 0x04 12. " [12] ,Set INTR.RANGE_INTR[12]" "No effect,Set" bitfld.long 0x04 11. " [11] ,Set INTR.RANGE_INTR[11]" "No effect,Set" bitfld.long 0x04 10. " [10] ,Set INTR.RANGE_INTR[10]" "No effect,Set" textline " " bitfld.long 0x04 9. " [9] ,Set INTR.RANGE_INTR[9]" "No effect,Set" bitfld.long 0x04 8. " [8] ,Set INTR.RANGE_INTR[8]" "No effect,Set" bitfld.long 0x04 7. " [7] ,Set INTR.RANGE_INTR[7]" "No effect,Set" textline " " bitfld.long 0x04 6. " [6] ,Set INTR.RANGE_INTR[6]" "No effect,Set" bitfld.long 0x04 5. " [5] ,Set INTR.RANGE_INTR[5]" "No effect,Set" bitfld.long 0x04 4. " [4] ,Set INTR.RANGE_INTR[4]" "No effect,Set" textline " " bitfld.long 0x04 3. " [3] ,Set INTR.RANGE_INTR[3]" "No effect,Set" bitfld.long 0x04 2. " [2] ,Set INTR.RANGE_INTR[2]" "No effect,Set" bitfld.long 0x04 1. " [1] ,Set INTR.RANGE_INTR[1]" "No effect,Set" textline " " bitfld.long 0x04 0. " [0] ,Set INTR.RANGE_INTR[0]" "No effect,Set" line.long 0x08 "RANGE_INTR_MASK,Range Detect Interrupt Mask Register" bitfld.long 0x08 15. " RANGE_MASK[15] ,Channel 15 range detect interrupt mask" "Masked,Not masked" bitfld.long 0x08 14. " [14] ,Channel 14 range detect interrupt mask" "Masked,Not masked" bitfld.long 0x08 13. " [13] ,Channel 13 range detect interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x08 12. " [12] ,Channel 12 range detect interrupt mask" "Masked,Not masked" bitfld.long 0x08 11. " [11] ,Channel 11 range detect interrupt mask" "Masked,Not masked" bitfld.long 0x08 10. " [10] ,Channel 10 range detect interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x08 9. " [9] ,Channel 9 range detect interrupt mask" "Masked,Not masked" bitfld.long 0x08 8. " [8] ,Channel 8 range detect interrupt mask" "Masked,Not masked" bitfld.long 0x08 7. " [7] ,Channel 7 range detect interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x08 6. " [6] ,Channel 6 range detect interrupt mask" "Masked,Not masked" bitfld.long 0x08 5. " [5] ,Channel 5 range detect interrupt mask" "Masked,Not masked" bitfld.long 0x08 4. " [4] ,Channel 4 range detect interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x08 3. " [3] ,Channel 3 range detect interrupt mask" "Masked,Not masked" bitfld.long 0x08 2. " [2] ,Channel 2 range detect interrupt mask" "Masked,Not masked" bitfld.long 0x08 1. " [1] ,Channel 1 range detect interrupt mask" "Masked,Not masked" textline " " bitfld.long 0x08 0. " [0] ,Channel 0 range detect interrupt mask" "Masked,Not masked" else group.long 0x230++0x03 line.long 0x00 "RANGE_INTR_set/clr,Range Detect Interrupt Request Register" setclrfld.long 0x00 15. 0x04 15. 0x00 15. " RANGE_INTR[15] ,Channel 15 range detect interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 14. 0x04 14. 0x00 14. " [14] ,Channel 14 range detect interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 13. 0x04 13. 0x00 13. " [13] ,Channel 13 range detect interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 12. 0x04 12. 0x00 12. " [12] ,Channel 12 range detect interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 11. 0x04 11. 0x00 11. " [11] ,Channel 11 range detect interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 10. 0x04 10. 0x00 10. " [10] ,Channel 10 range detect interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 9. 0x04 9. 0x00 9. " [9] ,Channel 9 range detect interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 8. 0x04 8. 0x00 8. " [8] ,Channel 8 range detect interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 7. 0x04 7. 0x00 7. " [7] ,Channel 7 range detect interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 6. 0x04 6. 0x00 6. " [6] ,Channel 6 range detect interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 5. 0x04 5. 0x00 5. " [5] ,Channel 5 range detect interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 4. 0x04 4. 0x00 4. " [4] ,Channel 4 range detect interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 3. 0x04 3. 0x00 3. " [3] ,Channel 3 range detect interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 2. 0x04 2. 0x00 2. " [2] ,Channel 2 range detect interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 1. 0x04 1. 0x00 1. " [1] ,Channel 1 range detect interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 0. 0x04 0. 0x00 0. " [0] ,Channel 0 range detect interrupt" "No interrupt,Interrupt" group.long 0x238++0x03 line.long 0x00 "RANGE_INTR_MASK,Range Detect Interrupt Mask Register" bitfld.long 0x00 15. " RANGE_MASK[15] ,Channel 15 range detect interrupt mask" "Not masked,Masked" bitfld.long 0x00 14. " [14] ,Channel 14 range detect interrupt mask" "Not masked,Masked" bitfld.long 0x00 13. " [13] ,Channel 13 range detect interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 12. " [12] ,Channel 12 range detect interrupt mask" "Not masked,Masked" bitfld.long 0x00 11. " [11] ,Channel 11 range detect interrupt mask" "Not masked,Masked" bitfld.long 0x00 10. " [10] ,Channel 10 range detect interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 9. " [9] ,Channel 9 range detect interrupt mask" "Not masked,Masked" bitfld.long 0x00 8. " [8] ,Channel 8 range detect interrupt mask" "Not masked,Masked" bitfld.long 0x00 7. " [7] ,Channel 7 range detect interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 6. " [6] ,Channel 6 range detect interrupt mask" "Not masked,Masked" bitfld.long 0x00 5. " [5] ,Channel 5 range detect interrupt mask" "Not masked,Masked" bitfld.long 0x00 4. " [4] ,Channel 4 range detect interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 3. " [3] ,Channel 3 range detect interrupt mask" "Not masked,Masked" bitfld.long 0x00 2. " [2] ,Channel 2 range detect interrupt mask" "Not masked,Masked" bitfld.long 0x00 1. " [1] ,Channel 1 range detect interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 0. " [0] ,Channel 0 range detect interrupt mask" "Not masked,Masked" endif rgroup.long 0x23C++0x07 line.long 0x00 "RANGE_INTR_MASKED,Range Interrupt Masked Request Register" bitfld.long 0x00 15. " RANGE_MASKED[15] ,Channel 15 range detect interrupt masked" "No interrupt,Interrupt" bitfld.long 0x00 14. " [14] ,Channel 14 range detect interrupt masked" "No interrupt,Interrupt" bitfld.long 0x00 13. " [13] ,Channel 13 range detect interrupt masked" "No interrupt,Interrupt" textline " " bitfld.long 0x00 12. " [12] ,Channel 12 range detect interrupt masked" "No interrupt,Interrupt" bitfld.long 0x00 11. " [11] ,Channel 11 range detect interrupt masked" "No interrupt,Interrupt" bitfld.long 0x00 10. " [10] ,Channel 10 range detect interrupt masked" "No interrupt,Interrupt" textline " " bitfld.long 0x00 9. " [9] ,Channel 9 range detect interrupt masked" "No interrupt,Interrupt" bitfld.long 0x00 8. " [8] ,Channel 8 range detect interrupt masked" "No interrupt,Interrupt" bitfld.long 0x00 7. " [7] ,Channel 7 range detect interrupt masked" "No interrupt,Interrupt" textline " " bitfld.long 0x00 6. " [6] ,Channel 6 range detect interrupt masked" "No interrupt,Interrupt" bitfld.long 0x00 5. " [5] ,Channel 5 range detect interrupt masked" "No interrupt,Interrupt" bitfld.long 0x00 4. " [4] ,Channel 4 range detect interrupt masked" "No interrupt,Interrupt" textline " " bitfld.long 0x00 3. " [3] ,Channel 3 range detect interrupt masked" "No interrupt,Interrupt" bitfld.long 0x00 2. " [2] ,Channel 2 range detect interrupt masked" "No interrupt,Interrupt" bitfld.long 0x00 1. " [1] ,Channel 1 range detect interrupt masked" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " [0] ,Channel 0 range detect interrupt masked" "No interrupt,Interrupt" line.long 0x04 "INTR_CAUSE,Interrupt Cause Register" bitfld.long 0x04 31. " RANGE_MASKED_RED ,Reduction OR of all RANGE_INTR_MASKED bits" "No interrupt,Interrupt" bitfld.long 0x04 30. " SATURATE_MASKED_RED ,Reduction OR of all SATURATION_INTR_MASKED bits" "No interrupt,Interrupt" bitfld.long 0x04 7. " INJ_COLLISION_MASKED_MIR ,Mirror copy of corresponding bit in INTR_MASKED" "No interrupt,Interrupt" textline " " bitfld.long 0x04 6. " INJ_RANGE_MASKED_MIR ,Mirror copy of corresponding bit in INTR_MASKED" "No interrupt,Interrupt" bitfld.long 0x04 5. " INJ_SATURATE_MASKED_MIR ,Mirror copy of corresponding bit in INTR_MASKED" "No interrupt,Interrupt" bitfld.long 0x04 4. " INJ_EOC_MASKED_MIR ,Mirror copy of corresponding bit in INTR_MASKED" "No interrupt,Interrupt" textline " " bitfld.long 0x04 3. " DSI_COLLISION_MASKED_MIR ,Mirror copy of corresponding bit in INTR_MASKED" "No interrupt,Interrupt" bitfld.long 0x04 2. " FW_COLLISION_MASKED_MIR ,Mirror copy of corresponding bit in INTR_MASKED" "No interrupt,Interrupt" bitfld.long 0x04 1. " OVERFLOW_MASKED_MIR ,Mirror copy of corresponding bit in INTR_MASKED" "No interrupt,Interrupt" textline " " bitfld.long 0x04 0. " EOS_MASKED_MIR ,Mirror copy of corresponding bit in INTR_MASKED" "No interrupt,Interrupt" if (((per.l(ad:0x403A0000+0x280))&0x100)==0x100) group.long 0x280++0x03 line.long 0x00 "INJ_CHAN_CONFIG,Injection Channel Configuration Register" bitfld.long 0x00 31. " INJ_START_EN ,Injection channel enable" "No effect,Enable" bitfld.long 0x00 30. " INJ_TAILGATING ,Injection channel tailgating" "No tailgating,Tailgating" bitfld.long 0x00 12.--13. " INJ_SAMPLE_TIME_SEL ,Injection sample time select" "ST0,ST1,ST2,ST3" textline " " bitfld.long 0x00 10. " INJ_AVG_EN ,Injection channel averaging enable" "Disabled,Enabled" sif !CPUIS("CY8C6*") textline " " bitfld.long 0x00 9. " INJ_RESOLUTION ,Injection channel resolution" "12-bit,SUBRES" endif textline " " bitfld.long 0x00 8. " INJ_DIFFERENTIAL_EN ,Injection channel differential enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " INJ_PORT_ADDR ,Address of the port that contains the pin to be sampled" "SARMUX,CTB0,CTB1,CTB2,CTB3,,AROUTE_VIRT,SARMUX_VIRT" bitfld.long 0x00 1.--2. " INJ_PIN_ADDR ,Address of the pin to be sampled by this injection channel" "0,2,4,6" else group.long 0x280++0x03 line.long 0x00 "INJ_CHAN_CONFIG,Injection Channel Configuration Register" bitfld.long 0x00 31. " INJ_START_EN ,Injection channel enable" "No effect,Enable" bitfld.long 0x00 30. " INJ_TAILGATING ,Injection channel tailgating" "No tailgating,Tailgating" bitfld.long 0x00 12.--13. " INJ_SAMPLE_TIME_SEL ,Injection sample time select" "ST0,ST1,ST2,ST3" textline " " bitfld.long 0x00 10. " INJ_AVG_EN ,Injection channel averaging enable" "Disabled,Enabled" sif !CPUIS("CY8C6*") textline " " bitfld.long 0x00 9. " INJ_RESOLUTION ,Injection channel resolution" "12-bit,SUBRES" endif textline " " bitfld.long 0x00 8. " INJ_DIFFERENTIAL_EN ,Injection channel differential enable" "Disabled,Enabled" bitfld.long 0x00 4.--6. " INJ_PORT_ADDR ,Address of the port that contains the pin to be sampled" "SARMUX,CTB0,CTB1,CTB2,CTB3,,AROUTE_VIRT,SARMUX_VIRT" bitfld.long 0x00 0.--2. " INJ_PIN_ADDR ,Address of the pin to be sampled by this injection channel" "0,1,2,3,4,5,6,7" endif rgroup.long 0x290++0x03 line.long 0x00 "INJ_RESULT,Injection Channel Result Register" bitfld.long 0x00 31. " INJ_EOC_INTR_MIR ,Mirror bit of corresponding bit in INTR register" "No interrupt,Interrupt" bitfld.long 0x00 30. " INJ_RANGE_INTR_MIR ,Mirror bit of corresponding bit in INTR register" "No interrupt,Interrupt" bitfld.long 0x00 29. " INJ_SATURATE_INTR_MIR ,Mirror bit of corresponding bit in INTR register" "No interrupt,Interrupt" textline " " bitfld.long 0x00 28. " INJ_COLLISION_INTR_MIR ,Mirror bit of corresponding bit in INTR register" "No interrupt,Interrupt" hexmask.long.word 0x00 0.--15. 1. " INJ_RESULT ,SAR conversion result of the channel" sif CPUIS("CY8C6*") if (((per.l(ad:0x403A0000+0x2A0))&0x80000000)==0x80000000) rgroup.long 0x2A0++0x03 line.long 0x00 "STATUS,Current Status of Internal SAR Registers" bitfld.long 0x00 31. " BUSY ,SAR with a conversion busy" "Not busy,Busy" bitfld.long 0x00 30. " SW_VREF_NEG ,Current switch status" "0,1" bitfld.long 0x00 0.--4. " CUR_CHAN ,Current channel being sampled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..." else rgroup.long 0x2A0++0x03 line.long 0x00 "STATUS,Current Status of Internal SAR Registers" bitfld.long 0x00 31. " BUSY ,SAR with a conversion busy" "Not busy,Busy" bitfld.long 0x00 30. " SW_VREF_NEG ,Current switch status" "0,1" endif rgroup.long 0x2A4++0x03 line.long 0x00 "AVG_STAT,Current Averaging Status Register" hexmask.long.byte 0x00 24.--31. 1. " CUR_AVG_CNT ,Current value of the averaging counter" bitfld.long 0x00 23. " INTRLV_BUSY ,SAR is in the middle of interleaved averaging spanning several scans" "Not busy,Busy" hexmask.long.tbyte 0x00 0.--19. 1. " CUR_AVG_ACCU ,Current value of the averaging accumulator" group.long 0x300++0x03 line.long 0x00 "MUX_SWICH0_SET/CLR,SARMUX Firmware Switch Controls Set/Clear" setclrfld.long 0x00 29. 0x00 29. 0x04 29. " MUX_FW_P7_COREIO3 ,Switch between P7 and coreio3 signal" "Open,Closed" setclrfld.long 0x00 28. 0x00 28. 0x04 28. " MUX_FW_P6_COREIO2 ,Switch between P6 and coreio2 signal" "Open,Closed" setclrfld.long 0x00 27. 0x00 27. 0x04 27. " MUX_FW_P5_COREIO1 ,Switch between P5 and coreio1 signal" "Open,Closed" textline " " setclrfld.long 0x00 26. 0x00 26. 0x04 26. " MUX_FW_P4_COREIO0 ,Switch between P4 and coreio0 signal" "Open,Closed" setclrfld.long 0x00 25. 0x00 25. 0x04 25. " MUX_FW_SARBUS1_VMINUS ,Switch between sarbus1 and vminus signal" "Open,Closed" setclrfld.long 0x00 24. 0x00 24. 0x04 24. " MUX_FW_SARBUS0_VMINUS ,Switch between sarbus0 and vminus signal" "Open,Closed" textline " " setclrfld.long 0x00 23. 0x00 23. 0x04 23. " MUX_FW_SARBUS1_VPLUS ,Switch between sarbus1 and vplus signal" "Open,Closed" setclrfld.long 0x00 22. 0x00 22. 0x04 22. " MUX_FW_SARBUS0_VPLUS ,Switch between sarbus0 and vplus signal" "Open,Closed" setclrfld.long 0x00 21. 0x00 21. 0x04 21. " MUX_FW_AMUXBUSB_VMINUS ,Switch between amuxbusb and vminus signal" "Open,Closed" textline " " setclrfld.long 0x00 20. 0x00 20. 0x04 20. " MUX_FW_AMUXBUSA_VMINUS ,Switch between amuxbusa and vminus signal" "Open,Closed" setclrfld.long 0x00 19. 0x00 19. 0x04 19. " MUX_FW_AMUXBUSB_VPLUS ,Switch between amuxbusb and vplus signal" "Open,Closed" setclrfld.long 0x00 18. 0x00 18. 0x04 18. " MUX_FW_AMUXBUSA_VPLUS ,Switch between amuxbusa and vplus signal" "Open,Closed" textline " " setclrfld.long 0x00 17. 0x00 17. 0x04 17. " MUX_FW_TEMP_VPLUS ,Switch between temperature sensor and vplus signal" "Open,Closed" setclrfld.long 0x00 16. 0x00 16. 0x04 16. " MUX_FW_VSSA_VMINUS ,Switch between vssa_kelvin and vminus signal" "Open,Closed" setclrfld.long 0x00 15. 0x00 15. 0x04 15. " MUX_FW_P7_VMINUS ,Switch between pin P7 and vminus signal" "Open,Closed" textline " " setclrfld.long 0x00 14. 0x00 14. 0x04 14. " MUX_FW_P6_VMINUS ,Switch between pin P6 and vminus signal" "Open,Closed" setclrfld.long 0x00 13. 0x00 13. 0x04 13. " MUX_FW_P5_VMINUS ,Switch between pin P5 and vminus signal" "Open,Closed" setclrfld.long 0x00 12. 0x00 12. 0x04 12. " MUX_FW_P4_VMINUS ,Switch between pin P4 and vminus signal" "Open,Closed" textline " " setclrfld.long 0x00 11. 0x00 11. 0x04 11. " MUX_W_P3_VMINUS ,Switch between pin P3 and vminus signal" "Open,Closed" setclrfld.long 0x00 10. 0x00 10. 0x04 10. " MUX_FW_P2_VMINUS ,Switch between pin P2 and vminus signal" "Open,Closed" setclrfld.long 0x00 9. 0x00 9. 0x04 9. " MUX_FW_P1_VMINUS ,Switch between pin P1 and vminus signal" "Open,Closed" textline " " setclrfld.long 0x00 8. 0x00 8. 0x04 8. " MUX_FW_P0_VMINUS ,Switch between pin P0 and vminus signal" "Open,Closed" setclrfld.long 0x00 7. 0x00 7. 0x04 7. " MUX_FW_P7_VPLUS ,Switch between pin P7 and vplus signal" "Open,Closed" setclrfld.long 0x00 6. 0x00 6. 0x04 6. " MUX_FW_P6_VPLUS ,Switch between pin P6 and vplus signal" "Open,Closed" textline " " setclrfld.long 0x00 5. 0x00 5. 0x04 5. " MUX_FW_P5_VPLUS ,Switch between pin P5 and vplus signal" "Open,Closed" setclrfld.long 0x00 4. 0x00 4. 0x04 4. " MUX_FW_P4_VPLUS ,Switch between pin P4 and vplus signal" "Open,Closed" setclrfld.long 0x00 3. 0x00 3. 0x04 3. " MUX_FW_P3_VPLUS ,Switch between pin P3 and vplus signal" "Open,Closed" textline " " setclrfld.long 0x00 2. 0x00 2. 0x04 2. " MUX_FW_P2_VPLUS ,Switch between pin P2 and vplus signal" "Open,Closed" setclrfld.long 0x00 1. 0x00 1. 0x04 1. " MUX_FW_P1_VPLUS ,Switch between pin P1 and vplus signal" "Open,Closed" setclrfld.long 0x00 0. 0x00 0. 0x04 0. " MUX_FW_P0_VPLUS ,Switch between pin P0 and vplus signal" "Open,Closed" group.long 0x340++0x07 line.long 0x00 "MUX_SWITCH_DS_CTRL,SARMUX Switch DSI Control" bitfld.long 0x00 23. " MUX_DS_CTRL_SARBUS1 ,Multiplex for SARBUS1 switch" "Disabled,Enabled" bitfld.long 0x00 22. " MUX_DS_CTRL_SARBUS0 ,Multiplex for SARBUS0 switch" "Disabled,Enabled" bitfld.long 0x00 19. " MUX_DS_CTRL_AMUXBUSB ,Multiplex for AMUXBUSB switch" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " MUX_DS_CTRL_AMUXBUSA ,Multiplex for AMUXBUSA switch" "Disabled,Enabled" bitfld.long 0x00 17. " MUX_DS_CTRL_TEMP ,Multiplex for TEMP switch" "Disabled,Enabled" bitfld.long 0x00 16. " MUX_DS_CTRL_VSSA ,Multiplex for VSSA switch" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " MUX_DS_CTRL_P7 ,Multiplex for P7 switch" "Disabled,Enabled" bitfld.long 0x00 6. " MUX_DS_CTRL_P6 ,Multiplex for P6 switch" "Disabled,Enabled" bitfld.long 0x00 5. " MUX_DS_CTRL_P5 ,Multiplex for P5 switch" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " MUX_DS_CTRL_P4 ,Multiplex for P4 switch" "Disabled,Enabled" bitfld.long 0x00 3. " MUX_DS_CTRL_P3 ,Multiplex for P3 switch" "Disabled,Enabled" bitfld.long 0x00 2. " MUX_DS_CTRL_P2 ,Multiplex for P2 switch" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " MUX_DS_CTRL_P1 ,Multiplex for P1 switch" "Disabled,Enabled" bitfld.long 0x00 0. " MUX_DS_CTRL_P0 ,Multiplex for P0 switch" "Disabled,Enabled" line.long 0x04 "MUX_SWITCH_SQ_CTRL,SARMUX Switch SAR Sequencer Control" bitfld.long 0x04 23. " MUX_DS_CTRL_SARBUS1 ,Multiplex for SARBUS1 switch" "Disabled,Enabled" bitfld.long 0x04 22. " MUX_DS_CTRL_SARBUS0 ,Multiplex for SARBUS0 switch" "Disabled,Enabled" bitfld.long 0x04 19. " MUX_DS_CTRL_AMUXBUSB ,Multiplex for AMUXBUSB switch" "Disabled,Enabled" textline " " bitfld.long 0x04 18. " MUX_DS_CTRL_AMUXBUSA ,Multiplex for AMUXBUSA switch" "Disabled,Enabled" bitfld.long 0x04 17. " MUX_DS_CTRL_TEMP ,Multiplex for TEMP switch" "Disabled,Enabled" bitfld.long 0x04 16. " MUX_DS_CTRL_VSSA ,Multiplex for VSSA switch" "Disabled,Enabled" textline " " bitfld.long 0x04 7. " MUX_DS_CTRL_P7 ,Multiplex for P7 switches" "Disabled,Enabled" bitfld.long 0x04 6. " MUX_DS_CTRL_P6 ,Multiplex for P6 switches" "Disabled,Enabled" bitfld.long 0x04 5. " MUX_DS_CTRL_P5 ,Multiplex for P5 switches" "Disabled,Enabled" textline " " bitfld.long 0x04 4. " MUX_DS_CTRL_P4 ,Multiplex for P4 switches" "Disabled,Enabled" bitfld.long 0x04 3. " MUX_DS_CTRL_P3 ,Multiplex for P3 switches" "Disabled,Enabled" bitfld.long 0x04 2. " MUX_DS_CTRL_P2 ,Multiplex for P2 switches" "Disabled,Enabled" textline " " bitfld.long 0x04 1. " MUX_DS_CTRL_P1 ,Multiplex for P1 switches" "Disabled,Enabled" bitfld.long 0x04 0. " MUX_DS_CTRL_P0 ,Multiplex for P0 switches" "Disabled,Enabled" rgroup.long 0x348++0x03 line.long 0x00 "MUX_SWITCH_STATUS,SARMUX Firmware Switch Status Register" bitfld.long 0x00 25. " MUX_FW_SARBUS1_VMINUS ,Switch between sarbus1 and vminus signal" "Open,Closed" bitfld.long 0x00 24. " MUX_FW_SARBUS0_VMINUS ,Switch between sarbus0 and vminus signal" "Open,Closed" textline " " bitfld.long 0x00 23. " MUX_FW_SARBUS1_VPLUS ,Switch between sarbus1 and vplus signal" "Open,Closed" bitfld.long 0x00 22. " MUX_FW_SARBUS0_VPLUS ,Switch between sarbus0 and vplus signal" "Open,Closed" bitfld.long 0x00 21. " MUX_FW_AMUXBUSB_VMINUS ,Switch between amuxbusb and vminus signal" "Open,Closed" textline " " bitfld.long 0x00 20. " MUX_FW_AMUXBUSA_VMINUS ,Switch between amuxbusa and vminus signal" "Open,Closed" bitfld.long 0x00 19. " MUX_FW_AMUXBUSB_VPLUS ,Switch between amuxbusb and vplus signal" "Open,Closed" bitfld.long 0x00 18. " MUX_FW_AMUXBUSA_VPLUS ,Switch between amuxbusa and vplus signal" "Open,Closed" textline " " bitfld.long 0x00 17. " MUX_FW_TEMP_VPLUS ,Switch between temperature sensor and vplus signal" "Open,Closed" bitfld.long 0x00 16. " MUX_FW_VSSA_VMINUS ,Switch between vssa_kelvin and vminus signal" "Open,Closed" bitfld.long 0x00 15. " MUX_FW_P7_VMINUS ,Switch between pin P7 and vminus signal" "Open,Closed" textline " " bitfld.long 0x00 14. " MUX_FW_P6_VMINUS ,Switch between pin P6 and vminus signal" "Open,Closed" bitfld.long 0x00 13. " MUX_FW_P5_VMINUS ,Switch between pin P5 and vminus signal" "Open,Closed" bitfld.long 0x00 12. " MUX_FW_P4_VMINUS ,Switch between pin P4 and vminus signal" "Open,Closed" textline " " bitfld.long 0x00 11. " MUX_W_P3_VMINUS ,Switch between pin P3 and vminus signal" "Open,Closed" bitfld.long 0x00 10. " MUX_FW_P2_VMINUS ,Switch between pin P2 and vminus signal" "Open,Closed" bitfld.long 0x00 9. " MUX_FW_P1_VMINUS ,Switch between pin P1 and vminus signal" "Open,Closed" textline " " bitfld.long 0x00 8. " MUX_FW_P0_VMINUS ,Switch between pin P0 and vminus signal" "Open,Closed" bitfld.long 0x00 7. " MUX_FW_P7_VPLUS ,Switch between pin P7 and vplus signal" "Open,Closed" bitfld.long 0x00 6. " MUX_FW_P6_VPLUS ,Switch between pin P6 and vplus signal" "Open,Closed" textline " " bitfld.long 0x00 5. " MUX_FW_P5_VPLUS ,Switch between pin P5 and vplus signal" "Open,Closed" bitfld.long 0x00 4. " MUX_FW_P4_VPLUS ,Switch between pin P4 and vplus signal" "Open,Closed" bitfld.long 0x00 3. " MUX_FW_P3_VPLUS ,Switch between pin P3 and vplus signal" "Open,Closed" textline " " bitfld.long 0x00 2. " MUX_FW_P2_VPLUS ,Switch between pin P2 and vplus signal" "Open,Closed" bitfld.long 0x00 1. " MUX_FW_P1_VPLUS ,Switch between pin P1 and vplus signal" "Open,Closed" bitfld.long 0x00 0. " MUX_FW_P0_VPLUS ,Switch between pin P0 and vplus signal" "Open,Closed" group.long 0xF00++0x07 line.long 0x00 "ANA_TRIM0,Analog Trim Register" bitfld.long 0x00 5. " TRIMUNIT ,Attenuation cap trimming" "0,1" bitfld.long 0x00 0.--4. " CAP_TRIM ,Attenuation cap trimming" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "ANA_TRIM1,Analog Trim Register" bitfld.long 0x04 0.--5. " REF_BUF_TRIM ,SAR Reference buffer trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else hgroup.long 0x308++0x07 hide.long 0x00 "MUX_SWITCH1,SARMUX Firmware Switch 1 Controls Register" hide.long 0x04 "MUX_SWITCH_CLEAR1,SARMUX Firmware Switch 1 Control Clear Register" group.long 0x340++0x03 line.long 0x00 "MUX_SWITCH_HW_CTRL,SARMUX Switch Hardware Control Register" bitfld.long 0x00 23. " MUX_HW_CTRL_SARBUS1 ,Sarbus1 switches hardware control mask" "Not masked,Masked" bitfld.long 0x00 22. " MUX_HW_CTRL_SARBUS0 ,Sarbus0 switches hardware control mask" "Not masked,Masked" bitfld.long 0x00 19. " MUX_HW_CTRL_AMUXBUSB ,Amuxbusb switches hardware control mask" "Not masked,Masked" textline " " bitfld.long 0x00 18. " MUX_HW_CTRL_AMUXBUSA ,Amuxbusa switches hardware control mask" "Not masked,Masked" bitfld.long 0x00 17. " MUX_HW_CTRL_TEMP ,Temp switch hardware control mask" "Not masked,Masked" bitfld.long 0x00 16. " MUX_HW_CTRL_VSSA ,Vssa switch hardware control mask" "Not masked,Masked" textline " " bitfld.long 0x00 7. " MUX_HW_CTRL_P7 ,Pin P7 switches hardware control mask" "Not masked,Masked" bitfld.long 0x00 6. " MUX_HW_CTRL_P6 ,Pin P6 switches hardware control mask" "Not masked,Masked" bitfld.long 0x00 5. " MUX_HW_CTRL_P5 ,Pin P5 switches hardware control mask" "Not masked,Masked" textline " " bitfld.long 0x00 4. " MUX_HW_CTRL_P4 ,Pin P4 switches hardware control mask" "Not masked,Masked" bitfld.long 0x00 3. " MUX_HW_CTRL_P3 ,Pin P3 switches hardware control mask" "Not masked,Masked" bitfld.long 0x00 2. " MUX_HW_CTRL_P2 ,Pin P2 switches hardware control mask" "Not masked,Masked" textline " " bitfld.long 0x00 1. " MUX_HW_CTRL_P1 ,Pin P1 switches hardware control mask" "Not masked,Masked" bitfld.long 0x00 0. " MUX_HW_CTRL_P0 ,Pin P0 switches hardware control mask" "Not masked,Masked" group.long 0x348++0x03 line.long 0x00 "MUX_SWITCH0_SET/CLR,SARMUX Firmware Switch 0 Controls Register" setclrfld.long 0x00 25. -0x48 25. -0x44 25. " MUX_FW_SARBUS1_VMINUS ,Switch between sarbus1 and vminus signal" "Open,Closed" setclrfld.long 0x00 24. -0x48 24. -0x44 24. " MUX_FW_SARBUS0_VMINUS ,Switch between sarbus0 and vminus signal" "Open,Closed" textline " " setclrfld.long 0x00 23. -0x48 23. -0x44 23. " MUX_FW_SARBUS1_VPLUS ,Switch between sarbus1 and vplus signal" "Open,Closed" setclrfld.long 0x00 22. -0x48 22. -0x44 22. " MUX_FW_SARBUS0_VPLUS ,Switch between sarbus0 and vplus signal" "Open,Closed" setclrfld.long 0x00 21. -0x48 21. -0x44 21. " MUX_FW_AMUXBUSB_VMINUS ,Switch between amuxbusb and vminus signal" "Open,Closed" textline " " setclrfld.long 0x00 20. -0x48 20. -0x44 20. " MUX_FW_AMUXBUSA_VMINUS ,Switch between amuxbusa and vminus signal" "Open,Closed" setclrfld.long 0x00 19. -0x48 19. -0x44 19. " MUX_FW_AMUXBUSB_VPLUS ,Switch between amuxbusb and vplus signal" "Open,Closed" setclrfld.long 0x00 18. -0x48 18. -0x44 18. " MUX_FW_AMUXBUSA_VPLUS ,Switch between amuxbusa and vplus signal" "Open,Closed" textline " " setclrfld.long 0x00 17. -0x48 17. -0x44 17. " MUX_FW_TEMP_VPLUS ,Switch between temperature sensor and vplus signal" "Open,Closed" setclrfld.long 0x00 16. -0x48 16. -0x44 16. " MUX_FW_VSSA_VMINUS ,Switch between vssa_kelvin and vminus signal" "Open,Closed" setclrfld.long 0x00 15. -0x48 15. -0x44 15. " MUX_FW_P7_VMINUS ,Switch between pin P7 and vminus signal" "Open,Closed" textline " " setclrfld.long 0x00 14. -0x48 14. -0x44 14. " MUX_FW_P6_VMINUS ,Switch between pin P6 and vminus signal" "Open,Closed" setclrfld.long 0x00 13. -0x48 13. -0x44 13. " MUX_FW_P5_VMINUS ,Switch between pin P5 and vminus signal" "Open,Closed" setclrfld.long 0x00 12. -0x48 12. -0x44 12. " MUX_FW_P4_VMINUS ,Switch between pin P4 and vminus signal" "Open,Closed" textline " " setclrfld.long 0x00 11. -0x48 11. -0x44 11. " MUX_W_P3_VMINUS ,Switch between pin P3 and vminus signal" "Open,Closed" setclrfld.long 0x00 10. -0x48 10. -0x44 10. " MUX_FW_P2_VMINUS ,Switch between pin P2 and vminus signal" "Open,Closed" setclrfld.long 0x00 9. -0x48 9. -0x44 9. " MUX_FW_P1_VMINUS ,Switch between pin P1 and vminus signal" "Open,Closed" textline " " setclrfld.long 0x00 8. -0x48 8. -0x44 8. " MUX_FW_P0_VMINUS ,Switch between pin P0 and vminus signal" "Open,Closed" setclrfld.long 0x00 7. -0x48 7. -0x44 7. " MUX_FW_P7_VPLUS ,Switch between pin P7 and vplus signal" "Open,Closed" setclrfld.long 0x00 6. -0x48 6. -0x44 6. " MUX_FW_P6_VPLUS ,Switch between pin P6 and vplus signal" "Open,Closed" textline " " setclrfld.long 0x00 5. -0x48 5. -0x44 5. " MUX_FW_P5_VPLUS ,Switch between pin P5 and vplus signal" "Open,Closed" setclrfld.long 0x00 4. -0x48 4. -0x44 4. " MUX_FW_P4_VPLUS ,Switch between pin P4 and vplus signal" "Open,Closed" setclrfld.long 0x00 3. -0x48 3. -0x44 3. " MUX_FW_P3_VPLUS ,Switch between pin P3 and vplus signal" "Open,Closed" textline " " setclrfld.long 0x00 2. -0x48 2. -0x44 2. " MUX_FW_P2_VPLUS ,Switch between pin P2 and vplus signal" "Open,Closed" setclrfld.long 0x00 1. -0x48 1. -0x44 1. " MUX_FW_P1_VPLUS ,Switch between pin P1 and vplus signal" "Open,Closed" setclrfld.long 0x00 0. -0x48 0. -0x44 0. " MUX_FW_P0_VPLUS ,Switch between pin P0 and vplus signal" "Open,Closed" group.long 0x380++0x03 line.long 0x00 "PUMP_CTRL,Switch Pump Control Register" bitfld.long 0x00 31. " ENABLED ,Pump output enable" "Disabled,Enabled" bitfld.long 0x00 0. " CLOCK_SEL ,Clock select" "External,Internal" group.long 0xF00++0x03 line.long 0x00 "ANA_TRIM,Analog Trim Register" bitfld.long 0x00 3. " TRIMUNIT ,Attenuation cap trimming" "0,1" bitfld.long 0x00 0.--2. " CAP_TRIM ,Attenuation cap trimming" "0,1,2,3,4,5,6,7" endif width 0x0B tree.end tree "SCB" tree "SCB0" base ad:0x40240000 if (((per.l(ad:0x40240000))&0x3000000)==0x0000000) width 12. if (((per.l(ad:0x40240000))&0x200)==0x200) if (((per.l(ad:0x40240000))&0x80000000)==0x80000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked" textline " " rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" else group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked" textline " " bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" endif else if (((per.l(ad:0x40240000))&0x80000000)==0x80000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." textline " " rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" else group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." textline " " bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" endif endif rgroup.long 0x04++0x03 line.long 0x00 "STATUS,Generic Status Register" bitfld.long 0x00 0. " EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy" if (((per.l(ad:0x40240000+0x60))&0xC0000000)==0xC0000000) if (((per.l(ad:0x40240000))&0x100)==0x100)&&((((per.l(ad:0x40240000))&0x200)==0x000)||(((per.l(ad:0x40240000+0x60))&0x800)==0x800)||(((per.l(ad:0x40240000))&0x400)==0x400)) if (((per.l(ad:0x40240000))&0x400)==0x000) group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 14. " S_NOT_READY_ADDR_NACK ,Slave not ready address NACK" "Ready,Not ready" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" else group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" endif elif (((per.l(ad:0x40240000))&0x100)==0x000)&&(((per.l(ad:0x40240000))&0x200)==0x000)&&(((per.l(ad:0x40240000))&0x400)==0x000) group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" else if (((per.l(ad:0x40240000))&0x400)==0x400) group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" else group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" endif endif elif (((per.l(ad:0x40240000+0x60))&0xC0000000)==0x80000000) if (((per.l(ad:0x40240000))&0x100)==0x100)&&((((per.l(ad:0x40240000))&0x200)==0x000)||(((per.l(ad:0x40240000+0x60))&0x800)==0x800)||(((per.l(ad:0x40240000))&0x400)==0x400)) if (((per.l(ad:0x40240000))&0x400)==0x000) group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 14. " S_NOT_READY_ADDR_NACK ,Slave not ready address NACK" "Ready,Not ready" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" bitfld.long 0x00 4.--7. " LOW_PHASE_OVS ,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " HIGH_PHASE_OVS ,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" bitfld.long 0x00 4.--7. " LOW_PHASE_OVS ,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " HIGH_PHASE_OVS ,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif (((per.l(ad:0x40240000))&0x100)==0x000)&&(((per.l(ad:0x40240000))&0x200)==0x000)&&(((per.l(ad:0x40240000))&0x400)==0x000) group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" bitfld.long 0x00 4.--7. " LOW_PHASE_OVS ,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " HIGH_PHASE_OVS ,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else if (((per.l(ad:0x40240000))&0x400)==0x400) group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" bitfld.long 0x00 4.--7. " LOW_PHASE_OVS ,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " HIGH_PHASE_OVS ,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" bitfld.long 0x00 4.--7. " LOW_PHASE_OVS ,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " HIGH_PHASE_OVS ,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif endif elif (((per.l(ad:0x40240000+0x60))&0xC0000000)==0x40000000) if (((per.l(ad:0x40240000))&0x100)==0x100)&&((((per.l(ad:0x40240000))&0x200)==0x000)||(((per.l(ad:0x40240000+0x60))&0x800)==0x800)||(((per.l(ad:0x40240000))&0x400)==0x400)) if (((per.l(ad:0x40240000))&0x400)==0x000) group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 14. " S_NOT_READY_ADDR_NACK ,Slave not ready address NACK" "Ready,Not ready" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" else group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" endif elif (((per.l(ad:0x40240000))&0x100)==0x000)&&(((per.l(ad:0x40240000))&0x200)==0x000)&&(((per.l(ad:0x40240000))&0x400)==0x000) group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" else if (((per.l(ad:0x40240000))&0x400)==0x400) group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" else group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" endif endif else if (((per.l(ad:0x40240000))&0x100)==0x100)&&((((per.l(ad:0x40240000))&0x200)==0x000)||(((per.l(ad:0x40240000+0x60))&0x800)==0x800)||(((per.l(ad:0x40240000))&0x400)==0x400)) if (((per.l(ad:0x40240000))&0x400)==0x000) group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 14. " S_NOT_READY_ADDR_NACK ,Slave not ready address NACK" "Ready,Not ready" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" else group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" endif elif (((per.l(ad:0x40240000))&0x100)==0x000)&&(((per.l(ad:0x40240000))&0x200)==0x000)&&(((per.l(ad:0x40240000))&0x400)==0x000) group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" else if (((per.l(ad:0x40240000))&0x400)==0x400) group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" else group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" endif endif endif if (((per.l(ad:0x40240000))&0x200)==0x000) rgroup.long 0x64++0x03 line.long 0x00 "I2C_STATUS,I2C Status Register" hexmask.long.byte 0x00 16.--23. 1. " BASE_EZ_ADDR ,I2C slave base EZ address" hexmask.long.byte 0x00 8.--15. 1. " CURR_EZ_ADDR ,I2C slave current EZ address" bitfld.long 0x00 5. " M_READ ,I2C master read transfer" "Write transfer,Read transfer" textline " " bitfld.long 0x00 4. " S_READ ,I2C slave read transfer" "Write transfer,Read transfer" bitfld.long 0x00 1. " I2C_EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy" bitfld.long 0x00 0. " BUS_BUSY ,I2C bus is busy" "Not busy,Busy" else rgroup.long 0x64++0x03 line.long 0x00 "I2C_STATUS,I2C Status Register" bitfld.long 0x00 5. " M_READ ,I2C master read transfer" "Write transfer,Read transfer" textline " " bitfld.long 0x00 4. " S_READ ,I2C slave read transfer" "Write transfer,Read transfer" bitfld.long 0x00 1. " I2C_EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy" bitfld.long 0x00 0. " BUS_BUSY ,I2C bus is busy" "Not busy,Busy" endif if (((per.l(ad:0x40240000+0x60))&0x80000000)==0x80000000) group.long 0x68++0x03 line.long 0x00 "I2C_M_CMD,I2C Master Command Register" bitfld.long 0x00 4. " M_STOP ,Master transmit STOP" "Disabled,ENABLED" bitfld.long 0x00 3. " M_NACK ,Master negative acknowledgement transmit" "Disabled,Enabled" bitfld.long 0x00 2. " M_ACK ,Master acknowledgement transmit" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " M_START_ON_IDLE ,Master START on idle" "Disabled,Enabled" bitfld.long 0x00 0. " M_START ,Master transmit START" "Disabled,Enabled" else hgroup.long 0x68++0x03 hide.long 0x00 "I2C_M_CMD,I2C Master Command Register" endif if (((per.l(ad:0x40240000+0x60))&0x40000000)==0x40000000) if (((per.l(ad:0x40240000))&0x400)==0x400) group.long 0x6C++0x03 line.long 0x00 "I2C_S_CMD,I2C Slave Command Register" bitfld.long 0x00 1. " S_NACK ,Slave negative acknowledgement transmit" "Disabled,Enabled" bitfld.long 0x00 0. " S_ACK ,Slave acknowledgement transmit" "Disabled,Enabled" else group.long 0x6C++0x03 line.long 0x00 "I2C_S_CMD,I2C Slave Command Register" bitfld.long 0x00 1. " S_NACK ,Slave negative acknowledgement transmit" "Disabled,Enabled" endif else hgroup.long 0x6C++0x03 hide.long 0x00 "I2C_S_CMD,I2C Slave Command Register" endif group.long 0x70++0x03 line.long 0x00 "I2C_CFG,I2C Configuration Register" bitfld.long 0x00 28.--29. " SDA_OUT_FILT_SEL ,Selection of cumulative 'i2c_sda_out' filter delay" "0 ns,50 ns,100 ns,150 ns" bitfld.long 0x00 20.--21. " SDA_OUT_FILT2_TRIM ,Trim bits for 'i2c_sda_out' 50 ns filter 2" "0,1,2,3" bitfld.long 0x00 18.--19. " SDA_OUT_FILT1_TRIM ,Trim bits for 'i2c_sda_out' 50 ns filter 1" "0,1,2,3" textline " " bitfld.long 0x00 16.--17. " SDA_OUT_FILT0_TRIM ,Trim bits for 'i2c_sda_out' 50 ns filter 0" "0,1,2,3" bitfld.long 0x00 12. " SCL_IN_FILT_SEL ,Selection of 'i2c_sda_in' filter delay" "0 ns,50 ns" bitfld.long 0x00 8.--9. " SCL_IN_FILT_TRIM ,Trim bits for 'i2c_sda_in' 50 ns filter" "0,1,2,3" textline " " bitfld.long 0x00 4. " SDA_IN_FILT_SEL ,Selection of 'i2c_sda_in' filter delay" "0 ns,50 ns" bitfld.long 0x00 0.--1. " SDA_IN_FILT_TRIM ,Trim bits for 'i2c_sda_in' 50 ns filter" "0,1,2,3" width 0x0B elif (((per.l(ad:0x40240000))&0x3000000)==0x1000000) width 22. if (((per.l(ad:0x40240000+0x20))&0x80000000)==0x80000000) if (((per.l(ad:0x40240000))&0x200)==0x200) if (((per.l(ad:0x40240000))&0x80000000)==0x80000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked" textline " " rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked" rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked" textline " " bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked" bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else if (((per.l(ad:0x40240000))&0x80000000)==0x80000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." textline " " rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked" rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." textline " " bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked" bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15" endif endif rgroup.long 0x04++0x03 line.long 0x00 "STATUS,Generic Status Register" bitfld.long 0x00 0. " EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy" if (((per.l(ad:0x40240000+0x20))&0x3000000)==0x0000000) if (((per.l(ad:0x40240000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40240000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x0000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40240000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40240000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x4000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40240000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40240000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x8000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40240000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40240000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0xC000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40240000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40240000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x0000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40240000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40240000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x4000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40240000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40240000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x8000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40240000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40240000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0xC000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40240000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40240000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x0000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40240000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40240000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x4000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40240000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40240000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x8000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40240000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40240000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0xC000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40240000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40240000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x0000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40240000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40240000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x4000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40240000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40240000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x8000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40240000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40240000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0xC000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" endif elif (((per.l(ad:0x40240000+0x20))&0x3000000)==0x2000000) if (((per.l(ad:0x40240000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x0000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40240000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x4000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40240000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x8000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40240000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0xC000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40240000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x0000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40240000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x4000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40240000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x8000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40240000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0xC000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" endif elif (((per.l(ad:0x40240000+0x20))&0x3000000)==0x1000000) if (((per.l(ad:0x40240000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x0000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "High,Low" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides" bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40240000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x4000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "High,Low" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides" bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40240000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x8000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "High,Low" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides" bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40240000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0xC000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "High,Low" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides" bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40240000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x0000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "High,Low" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides" bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40240000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x4000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "High,Low" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides" bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40240000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x8000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "High,Low" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides" bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40240000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0xC000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "High,Low" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides" bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" endif else if (((per.l(ad:0x40240000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x0000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40240000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x4000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40240000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x8000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40240000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0xC000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40240000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x0000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40240000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x4000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40240000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0x8000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40240000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40240000+0x20))&0xC000000)==0xC000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" endif endif else if (((per.l(ad:0x40240000))&0x200)==0x200) if (((per.l(ad:0x40240000))&0x80000000)==0x80000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked" textline " " rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked" else group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked" textline " " bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked" endif else if (((per.l(ad:0x40240000))&0x80000000)==0x80000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." textline " " rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" else group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." textline " " bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" endif endif rgroup.long 0x04++0x03 line.long 0x00 "STATUS,Generic Status Register" bitfld.long 0x00 0. " EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy" if (((per.l(ad:0x40240000+0x20))&0x3000000)==0x0000000) if (((per.l(ad:0x40240000+0x20))&0x8)==0x0) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge" else group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge" endif elif (((per.l(ad:0x40240000+0x20))&0x3000000)==0x2000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." elif (((per.l(ad:0x40240000+0x20))&0x3000000)==0x1000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." else group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." endif endif if (((per.l(ad:0x40240000))&0x200)==0x000) rgroup.long 0x24++0x03 line.long 0x00 "SPI_STATUS,SPI Status Register" hexmask.long.byte 0x00 16.--23. 0x01 " BASE_EZ_ADDR ,SPI base EZ address" hexmask.long.byte 0x00 8.--15. 0x01 " CURR_EZ_ADDR ,SPI current EZ address" bitfld.long 0x00 1. " SPI_EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy" textline " " bitfld.long 0x00 0. " BUS_BUSY ,SPI bus is busy" "Not busy,Busy" else rgroup.long 0x24++0x03 line.long 0x00 "SPI_STATUS,SPI Status Register" bitfld.long 0x00 1. " SPI_EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy" textline " " bitfld.long 0x00 0. " BUS_BUSY ,SPI bus is busy" "Not busy,Busy" endif width 0x0B elif (((per.l(ad:0x40240000))&0x3000000)==0x2000000) width 21. if (((per.l(ad:0x40240000))&0x200)==0x200) if (((per.l(ad:0x40240000))&0x80000000)==0x80000000) if (((per.l(ad:0x40240000+0x40))&0x3000000)==0x0000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked" textline " " rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15" elif (((per.l(ad:0x40240000+0x40))&0x3000000)==0x1000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked" textline " " rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15" elif (((per.l(ad:0x40240000+0x40))&0x3000000)==0x2000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked" textline " " rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" "16,32,48,96,192,768,1536,?..." endif else if (((per.l(ad:0x40240000+0x40))&0x3000000)==0x0000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked" textline " " bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15" elif (((per.l(ad:0x40240000+0x40))&0x3000000)==0x1000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked" textline " " bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15" elif (((per.l(ad:0x40240000+0x40))&0x3000000)==0x2000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked" textline " " bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" "16,32,48,96,192,768,1536,?..." endif endif else if (((per.l(ad:0x40240000))&0x80000000)==0x80000000) if (((per.l(ad:0x40240000+0x40))&0x3000000)==0x0000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." textline " " rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15" elif (((per.l(ad:0x40240000+0x40))&0x3000000)==0x1000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." textline " " rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15" elif (((per.l(ad:0x40240000+0x40))&0x3000000)==0x2000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." textline " " rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" "16,?..." endif else if (((per.l(ad:0x40240000+0x40))&0x3000000)==0x0000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." textline " " bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15" elif (((per.l(ad:0x40240000+0x40))&0x3000000)==0x1000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." textline " " bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15" elif (((per.l(ad:0x40240000+0x40))&0x3000000)==0x2000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." textline " " bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" "16,?..." endif endif endif rgroup.long 0x04++0x03 line.long 0x00 "STATUS,Generic Status Register" bitfld.long 0x00 0. " EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy" group.long 0x40++0x03 line.long 0x00 "UART_CTRL,UART Control Register" bitfld.long 0x00 24.--25. " MODE ,Submode of UART operation" "UART_STD,UART_SMARTCARD,UART_IRDA,?..." bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" if (((per.l(ad:0x40240000+0x40))&0x3000000)==0x0000000) group.long 0x44++0x07 line.long 0x00 "UART_TX_CTRL,UART Transmitter Control Register" bitfld.long 0x00 5. " PARITY_ENABLED ,Parity generation enabled" "Disabled,Enabled" rbitfld.long 0x00 4. " PARITY ,Parity bit" "Even,Odd" textline " " bitfld.long 0x00 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7" line.long 0x04 "UART_RX_CTRL,UART Receiver Control Register" bitfld.long 0x04 16.--19. " BREAK_WIDTH ,Break width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 13. " SKIP_START ,Skips start bit detection for the first received data frame" "Disabled,Enabled" bitfld.long 0x04 12. " LIN_MODE ,Break detection and baud rate detection on the incoming data" "Disabled,Enabled" textline " " bitfld.long 0x04 10. " MP_MODE ,Multi-processor mode" "Disabled,Enabled" bitfld.long 0x04 9. " DROP_ON_FRAME_ERROR ,Behaviour when an error is detected in a start or stop period" "Data send to RX FIFO,Data dropped" bitfld.long 0x04 8. " DROP_ON_PARITY_ERROR ,Behaviour when a parity check fails" "Data send to RX FIFO,Data dropped" textline " " bitfld.long 0x04 5. " PARITY_ENABLED ,Parity checking enabled" "Disabled,Enabled" bitfld.long 0x04 4. " PARITY ,Parity bit" "Even,Odd" bitfld.long 0x04 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7" elif (((per.l(ad:0x40240000+0x40))&0x3000000)==0x1000000) group.long 0x44++0x07 line.long 0x00 "UART_TX_CTRL,UART Transmitter Control Register" bitfld.long 0x00 8. " RETRY_ON_NACK ,Retransmitted when negative acknowledgement is received" "Not retransmitted,Retransmitted" rbitfld.long 0x00 4. " PARITY ,Parity bit" "Even,Odd" textline " " bitfld.long 0x00 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7" line.long 0x04 "UART_RX_CTRL,UART Receiver Control Register" bitfld.long 0x04 16.--19. " BREAK_WIDTH ,Break width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x04 10. " MP_MODE ,Multi-processor mode" "Disabled,Enabled" bitfld.long 0x04 9. " DROP_ON_FRAME_ERROR ,Behaviour when an error is detected in a start or stop period" "Data send to RX FIFO,Data dropped" bitfld.long 0x04 8. " DROP_ON_PARITY_ERROR ,Behaviour when a parity check fails" "Data send to RX FIFO,Data dropped" textline " " bitfld.long 0x04 4. " PARITY ,Parity bit" "Even,Odd" bitfld.long 0x04 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7" elif (((per.l(ad:0x40240000+0x40))&0x3000000)==0x2000000) group.long 0x44++0x07 line.long 0x00 "UART_TX_CTRL,UART Transmitter Control Register" bitfld.long 0x00 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7" line.long 0x04 "UART_RX_CTRL,UART Receiver Control Register" bitfld.long 0x04 16.--19. " BREAK_WIDTH ,Break width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x04 10. " MP_MODE ,Multi-processor mode" "Disabled,Enabled" bitfld.long 0x04 9. " DROP_ON_FRAME_ERROR ,Behaviour when an error is detected in a start or stop period" "Data send to RX FIFO,Data dropped" textline " " bitfld.long 0x04 6. " POLARITY ,Inverts incoming RX line signal" "Low,High" bitfld.long 0x04 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7" endif rgroup.long 0x4C++0x03 line.long 0x00 "UART_RX_STATUS,UART Receiver Status Register" hexmask.long.word 0x00 0.--11. 1. " BR_COUNTER ,Amount of peripheral clock periods that constitute the transmission of a 0x55 data frame" group.long 0x50++0x03 line.long 0x00 "UART_FLOW_CTRL,UART Flow Control Register" bitfld.long 0x00 25. " CTS_ENABLED ,Enable use of CTS input signal" "Disabled,Enabled" bitfld.long 0x00 24. " CTS_POLARITY ,Polarity of the CTS input signal" "Low,High" bitfld.long 0x00 16. " RTS_POLARITY ,Polarity of the RTS output signal" "Low,High" textline " " bitfld.long 0x00 0.--3. " TRIGGER_LEVEL ,Trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B else width 18. if (((per.l(ad:0x40240000))&0x80000000)==0x80000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." else group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." endif endif textline " " width 28. if (((per.l(ad:0x40240000))&0x3000000)==0x2000000) group.long 0x200++0x03 line.long 0x00 "SCB0_TX_CTRL,Transmitter Control Register" bitfld.long 0x00 8. " MSB_FIRST ,Most significant bit first" "LSB,MSB" bitfld.long 0x00 0.--3. " DATA_WIDTH ,Dataframe width" ",,,3,4,5,6,7,8,?..." elif (((per.l(ad:0x40240000))&0x3000000)==0x1000000) group.long 0x200++0x03 line.long 0x00 "SCB0_TX_CTRL,Transmitter Control Register" bitfld.long 0x00 8. " MSB_FIRST ,Most significant bit first" "LSB,MSB" bitfld.long 0x00 0.--3. " DATA_WIDTH ,Dataframe width" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x200++0x03 line.long 0x00 "SCB0_TX_CTRL,Transmitter Control Register" bitfld.long 0x00 8. " MSB_FIRST ,Most significant bit first" "LSB,MSB" bitfld.long 0x00 0.--3. " DATA_WIDTH ,Dataframe width" ",,,,,,,7,?..." endif group.long 0x204++0x03 line.long 0x00 "SCB0_TX_FIFO_CTRL,Transmitter FIFO Control Register" bitfld.long 0x00 17. " FREEZE ,FIFO entries remove freeze" "Disabled,Enabled" bitfld.long 0x00 16. " CLEAR ,FIFO and transmitter shift register clear" "Not cleared,Cleared" bitfld.long 0x00 0.--3. " TRIGGER_LEVEL ,Trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x208++0x03 line.long 0x00 "SCB0_TX_FIFO_STATUS,Transmitter FIFO Status Register" bitfld.long 0x00 24.--27. " WR_PTR ,FIFO write pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " RD_PTR ,FIFO read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " SR_VALID ,TX shift registers valid data frame hold" "No,Yes" textline " " bitfld.long 0x00 0.--4. " USED ,Amount of enties in the transmitter FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x40240000))&0x800)==0x800) wgroup.long 0x240++0x03 line.long 0x00 "SCB0_TX_FIFO_WR,Transmitter FIFO Write Register" hexmask.long.byte 0x00 0.--7. 1. " DATA ,Data frame written into the transmitter FIFO" else wgroup.long 0x240++0x03 line.long 0x00 "SCB0_TX_FIFO_WR,Transmitter FIFO Write Register" hexmask.long.word 0x00 0.--15. 1. " DATA ,Data frame written into the transmitter FIFO" endif if (((per.l(ad:0x40240000))&0x3000400)==0x1000400) group.long 0x300++0x03 line.long 0x00 "SCB0_RX_CTRL,Transmitter Control Register" bitfld.long 0x00 9. " MEDIAN ,Median filter" "Off,On" bitfld.long 0x00 8. " MSB_FIRST ,Most significant bit first" "LSB,MSB" bitfld.long 0x00 0.--3. " DATA_WIDTH ,Dataframe width" ",,,,,,,7,?..." elif (((per.l(ad:0x40240000))&0x3000400)==0x1000400) group.long 0x300++0x03 line.long 0x00 "SCB0_RX_CTRL,Transmitter Control Register" bitfld.long 0x00 9. " MEDIAN ,Median filter" "Off,On" bitfld.long 0x00 8. " MSB_FIRST ,Most significant bit first" "LSB,MSB" bitfld.long 0x00 0.--3. " DATA_WIDTH ,Dataframe width" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((per.l(ad:0x40240000))&0x3000000)==0x2000000) group.long 0x300++0x03 line.long 0x00 "SCB0_RX_CTRL,Transmitter Control Register" bitfld.long 0x00 9. " MEDIAN ,Median filter" "Off,On" bitfld.long 0x00 8. " MSB_FIRST ,Most significant bit first" "LSB,MSB" bitfld.long 0x00 0.--3. " DATA_WIDTH ,Dataframe width" ",,,3,4,5,6,7,8,?..." else group.long 0x300++0x03 line.long 0x00 "SCB0_RX_CTRL,Transmitter Control Register" bitfld.long 0x00 9. " MEDIAN ,Median filter" "Off,On" bitfld.long 0x00 8. " MSB_FIRST ,Most significant bit first" "LSB,MSB" bitfld.long 0x00 0.--3. " DATA_WIDTH ,Dataframe width" ",,,,,,,7,?..." endif group.long 0x304++0x03 line.long 0x00 "SCB0_RX_FIFO_CTRL,Receiver FIFO Control Register" bitfld.long 0x00 17. " FREEZE ,Receiver FIFO have no effect" "Disabled,Enabled" bitfld.long 0x00 16. " CLEAR ,FIFO and receiver shift register clear" "Not cleared,Cleared" bitfld.long 0x00 0.--3. " TRIGGER_LEVEL ,Trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x308++0x03 line.long 0x00 "SCB0_RX_FIFO_STATUS,Receiver FIFO Status Register" bitfld.long 0x00 24.--27. " WR_PTR ,FIFO write pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " RD_PTR ,FIFO read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " SR_VALID ,RX shift registers valid data frame hold" "No,Yes" textline " " bitfld.long 0x00 0.--4. " USED ,Amount of enties in the receiver FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x310++0x03 line.long 0x00 "SCB0_RX_MATCH,Slave Address and Mask Register" hexmask.long.byte 0x00 16.--23. 0x01 " MASK ,Slave device address mask" hexmask.long.byte 0x00 0.--7. 0x01 " ADDR ,Slave device address" if (((per.l(ad:0x40240000))&0x800)==0x800) rgroup.long 0x340++0x07 line.long 0x00 "SCB0_RX_FIFO_RD,Receiver FIFO Read Register" hexmask.long.word 0x00 0.--15. 0x01 " DATA ,Data read from the receiver FIFO" line.long 0x04 "SCB0_RX_FIFO_RD_SILENT,Receiver FIFO Read Register" hexmask.long.word 0x04 0.--15. 0x01 " DATA ,Data read from the receiver FIFO" else rgroup.long 0x340++0x07 line.long 0x00 "SCB0_RX_FIFO_RD,Receiver FIFO Read Register" hexmask.long.byte 0x00 0.--7. 0x01 " DATA ,Data read from the receiver FIFO" line.long 0x04 "SCB0_RX_FIFO_RD_SILENT,Receiver FIFO Read Register" hexmask.long.byte 0x04 0.--7. 0x01 " DATA ,Data read from the receiver FIFO" endif group.long 0x400++0x03 line.long 0x00 "SCB0_EZ_DATA0,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x404++0x03 line.long 0x00 "SCB0_EZ_DATA1,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x408++0x03 line.long 0x00 "SCB0_EZ_DATA2,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x40C++0x03 line.long 0x00 "SCB0_EZ_DATA3,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x410++0x03 line.long 0x00 "SCB0_EZ_DATA4,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x414++0x03 line.long 0x00 "SCB0_EZ_DATA5,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x418++0x03 line.long 0x00 "SCB0_EZ_DATA6,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x41C++0x03 line.long 0x00 "SCB0_EZ_DATA7,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x420++0x03 line.long 0x00 "SCB0_EZ_DATA8,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x424++0x03 line.long 0x00 "SCB0_EZ_DATA9,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x428++0x03 line.long 0x00 "SCB0_EZ_DATA10,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x42C++0x03 line.long 0x00 "SCB0_EZ_DATA11,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x430++0x03 line.long 0x00 "SCB0_EZ_DATA12,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x434++0x03 line.long 0x00 "SCB0_EZ_DATA13,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x438++0x03 line.long 0x00 "SCB0_EZ_DATA14,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x43C++0x03 line.long 0x00 "SCB0_EZ_DATA15,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x440++0x03 line.long 0x00 "SCB0_EZ_DATA16,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x444++0x03 line.long 0x00 "SCB0_EZ_DATA17,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x448++0x03 line.long 0x00 "SCB0_EZ_DATA18,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x44C++0x03 line.long 0x00 "SCB0_EZ_DATA19,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x450++0x03 line.long 0x00 "SCB0_EZ_DATA20,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x454++0x03 line.long 0x00 "SCB0_EZ_DATA21,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x458++0x03 line.long 0x00 "SCB0_EZ_DATA22,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x45C++0x03 line.long 0x00 "SCB0_EZ_DATA23,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x460++0x03 line.long 0x00 "SCB0_EZ_DATA24,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x464++0x03 line.long 0x00 "SCB0_EZ_DATA25,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x468++0x03 line.long 0x00 "SCB0_EZ_DATA26,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x46C++0x03 line.long 0x00 "SCB0_EZ_DATA27,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x470++0x03 line.long 0x00 "SCB0_EZ_DATA28,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x474++0x03 line.long 0x00 "SCB0_EZ_DATA29,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x478++0x03 line.long 0x00 "SCB0_EZ_DATA30,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x47C++0x03 line.long 0x00 "SCB0_EZ_DATA31,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" rgroup.long 0xE00++0x03 line.long 0x00 "SCB0_INTR_CAUSE,Active Clocked Interrupt Signal Register" bitfld.long 0x00 5. " SPI_EC ,Externally clocked SPI interrupt active" "Not active,Active" bitfld.long 0x00 4. " I2C_EC ,Externally clock I2C interrupt active" "Not active,Active" bitfld.long 0x00 3. " RX ,Receiver interrupt active" "Not active,Active" textline " " bitfld.long 0x00 2. " TX ,Transmitter interrupt active" "Not active,Active" bitfld.long 0x00 1. " S ,Slave interrupt active" "Not active,Active" bitfld.long 0x00 0. " M ,Master interrupt active" "Not active,Active" if (((per.l(ad:0x40240000))&0x700)==0x700) group.long 0xE80++0x03 line.long 0x00 "SCB0_INTR_I2C_EC,Externally Clocked I2C Interrupt Request Register" eventfld.long 0x00 3. " EZ_READ_STOP ,STOP detection after a read transfer occurred" "No interrupt,Interrupt" eventfld.long 0x00 2. " EZ_WRITE_STOP ,STOP detection after a write transfer occurred" "No interrupt,Interrupt" eventfld.long 0x00 1. " EZ_STOP ,STOP detection" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " WAKE_UP ,Wake up request" "No interrupt,Interrupt" group.long 0xE88++0x03 line.long 0x00 "SCB0_INTR_I2C_EC_MASK,Externally Clocked I2C Interrupt Mask Register" bitfld.long 0x00 3. " EZ_READ_STOP ,STOP detection after a read transfer occurred interrupt mask" "Not masked,Masked" bitfld.long 0x00 2. " EZ_WRITE_STOP ,STOP detection after a write transfer occurred interrupt mask" "Not masked,Masked" bitfld.long 0x00 1. " EZ_STOP ,STOP detection interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 0. " WAKE_UP ,Wake up request interrupt mask" "Not masked,Masked" rgroup.long 0xE8C++0x03 line.long 0x00 "SCB0_INTR_I2C_EC_MASKED,Externally Clocked I2C Interrupt Masked Register" bitfld.long 0x00 3. " EZ_READ_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 2. " EZ_WRITE_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 1. " EZ_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " WAKE_UP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" group.long 0xEC0++0x03 line.long 0x00 "SCB0_INTR_SPI_EC,Externally Clocked SPI Interrupt Request Register" eventfld.long 0x00 3. " EZ_READ_STOP ,STOP detection after a read transfer occurred" "No interrupt,Interrupt" eventfld.long 0x00 2. " EZ_WRITE_STOP ,STOP detection after a write transfer occurred" "No interrupt,Interrupt" eventfld.long 0x00 1. " EZ_STOP ,STOP detection" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " WAKE_UP ,Wake up request" "No interrupt,Interrupt" group.long 0xEC8++0x03 line.long 0x00 "SCB0_INTR_SPI_EC_MASK,Externally Clocked SPI Interrupt Mask Register" bitfld.long 0x00 3. " EZ_READ_STOP ,STOP detection after a read transfer occurred interrupt mask" "Not masked,Masked" bitfld.long 0x00 2. " EZ_WRITE_STOP ,STOP detection after a write transfer occurred interrupt mask" "Not masked,Masked" bitfld.long 0x00 1. " EZ_STOP ,STOP detection interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 0. " WAKE_UP ,Wake up request interrupt mask" "Not masked,Masked" rgroup.long 0xE8C++0x03 line.long 0x00 "SCB0_INTR_SPI_EC_MASKED,Externally Clocked SPI Interrupt Masked Register" bitfld.long 0x00 3. " EZ_READ_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 2. " EZ_WRITE_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 1. " EZ_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " WAKE_UP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" elif (((per.l(ad:0x40240000))&0x700)==0x600) group.long 0xE80++0x03 line.long 0x00 "SCB0_INTR_I2C_EC,Externally Clocked I2C Interrupt Request Register" eventfld.long 0x00 3. " EZ_READ_STOP ,STOP detection after a read transfer occurred" "No interrupt,Interrupt" eventfld.long 0x00 2. " EZ_WRITE_STOP ,STOP detection after a write transfer occurred" "No interrupt,Interrupt" eventfld.long 0x00 1. " EZ_STOP ,STOP detection" "No interrupt,Interrupt" group.long 0xE88++0x03 line.long 0x00 "SCB0_INTR_I2C_EC_MASK,Externally Clocked I2C Interrupt Mask Register" bitfld.long 0x00 3. " EZ_READ_STOP ,STOP detection after a read transfer occurred interrupt mask" "Not masked,Masked" bitfld.long 0x00 2. " EZ_WRITE_STOP ,STOP detection after a write transfer occurred interrupt mask" "Not masked,Masked" bitfld.long 0x00 1. " EZ_STOP ,STOP detection interrupt mask" "Not masked,Masked" rgroup.long 0xE8C++0x03 line.long 0x00 "SCB0_INTR_I2C_EC_MASKED,Externally Clocked I2C Interrupt Masked Register" bitfld.long 0x00 3. " EZ_READ_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 2. " EZ_WRITE_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 1. " EZ_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" group.long 0xEC0++0x03 line.long 0x00 "SCB0_INTR_SPI_EC,Externally Clocked SPI Interrupt Request Register" eventfld.long 0x00 3. " EZ_READ_STOP ,STOP detection after a read transfer occurred" "No interrupt,Interrupt" eventfld.long 0x00 2. " EZ_WRITE_STOP ,STOP detection after a write transfer occurred" "No interrupt,Interrupt" eventfld.long 0x00 1. " EZ_STOP ,STOP detection" "No interrupt,Interrupt" group.long 0xEC8++0x03 line.long 0x00 "SCB0_INTR_SPI_EC_MASK,Externally Clocked SPI Interrupt Mask Register" bitfld.long 0x00 3. " EZ_READ_STOP ,STOP detection after a read transfer occurred interrupt mask" "Not masked,Masked" bitfld.long 0x00 2. " EZ_WRITE_STOP ,STOP detection after a write transfer occurred interrupt mask" "Not masked,Masked" bitfld.long 0x00 1. " EZ_STOP ,STOP detection interrupt mask" "Not masked,Masked" rgroup.long 0xE8C++0x03 line.long 0x00 "SCB0_INTR_SPI_EC_MASKED,Externally Clocked SPI Interrupt Masked Register" bitfld.long 0x00 3. " EZ_READ_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 2. " EZ_WRITE_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 1. " EZ_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" elif (((per.l(ad:0x40240000))&0x700)==0x000) group.long 0xE80++0x03 line.long 0x00 "SCB0_INTR_I2C_EC,Externally Clocked I2C Interrupt Request Register" group.long 0xE88++0x03 line.long 0x00 "SCB0_INTR_I2C_EC_MASK,Externally Clocked I2C Interrupt Mask Register" rgroup.long 0xE8C++0x03 line.long 0x00 "SCB0_INTR_I2C_EC_MASKED,Externally Clocked I2C Interrupt Masked Register" group.long 0xEC0++0x03 line.long 0x00 "SCB0_INTR_SPI_EC,Externally Clocked SPI Interrupt Request Register" group.long 0xEC8++0x03 line.long 0x00 "SCB0_INTR_SPI_EC_MASK,Externally Clocked SPI Interrupt Mask Register" rgroup.long 0xE8C++0x03 line.long 0x00 "SCB0_INTR_SPI_EC_MASKED,Externally Clocked SPI Interrupt Masked Register" else group.long 0xE80++0x03 line.long 0x00 "SCB0_INTR_I2C_EC,Externally Clocked I2C Interrupt Request Register" textline " " eventfld.long 0x00 0. " WAKE_UP ,Wake up request" "No interrupt,Interrupt" group.long 0xE88++0x03 line.long 0x00 "SCB0_INTR_I2C_EC_MASK,Externally Clocked I2C Interrupt Mask Register" textline " " bitfld.long 0x00 0. " WAKE_UP ,Wake up request interrupt mask" "Not masked,Masked" rgroup.long 0xE8C++0x03 line.long 0x00 "SCB0_INTR_I2C_EC_MASKED,Externally Clocked I2C Interrupt Masked Register" textline " " bitfld.long 0x00 0. " WAKE_UP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" group.long 0xEC0++0x03 line.long 0x00 "SCB0_INTR_SPI_EC,Externally Clocked SPI Interrupt Request Register" textline " " eventfld.long 0x00 0. " WAKE_UP ,Wake up request" "No interrupt,Interrupt" group.long 0xEC8++0x03 line.long 0x00 "SCB0_INTR_SPI_EC_MASK,Externally Clocked SPI Interrupt Mask Register" textline " " bitfld.long 0x00 0. " WAKE_UP ,Wake up request interrupt mask" "Not masked,Masked" rgroup.long 0xE8C++0x03 line.long 0x00 "SCB0_INTR_SPI_EC_MASKED,Externally Clocked SPI Interrupt Masked Register" textline " " bitfld.long 0x00 0. " WAKE_UP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" endif group.long 0xF00++0x03 line.long 0x00 "SCB0_INTR_M_set/clr,Master Interrupt Register" setclrfld.long 0x00 9. 0x04 9. 0x00 9. " SPI_DONE ,SPI master transfer done event interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 8. 0x04 8. 0x00 8. " I2C_BUS_ERROR ,I2C master bus error interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 4. 0x04 4. 0x00 4. " I2C_STOP ,I2C master STOP interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 2. 0x04 2. 0x00 2. " I2C_ACK ,I2C master acknowledgement interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 1. 0x04 1. 0x00 1. " I2C_NACK ,I2C master negative acknowledgement interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 0. 0x04 0. 0x00 0. " I2C_ARB_LOST ,I2C master lost arbitration interrupt" "No interrupt,Interrupt" group.long 0xF08++0x03 line.long 0x00 "SCB0_INTR_M_MASK,Master Interrupt Mask Register" bitfld.long 0x00 9. " SPI_DONE ,SPI master transfer done event interrupt" "Not masked,Masked" bitfld.long 0x00 8. " I2C_BUS_ERROR ,I2C master bus error interrupt" "Not masked,Masked" bitfld.long 0x00 4. " I2C_STOP ,I2C master STOP interrupt" "Not masked,Masked" textline " " bitfld.long 0x00 2. " I2C_ACK ,I2C master acknowledgement interrupt" "Not masked,Masked" bitfld.long 0x00 1. " I2C_NACK ,I2C master negative acknowledgement interrupt" "Not masked,Masked" bitfld.long 0x00 0. " I2C_ARB_LOST ,I2C master lost arbitration interrupt" "Not masked,Masked" rgroup.long 0xF0C++0x03 line.long 0x00 "SCB0_INTR_M_MASKED,Master Interrupt Masked Request Register" bitfld.long 0x00 9. " SPI_DONE ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 8. " I2C_BUS_ERROR ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 4. " I2C_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" textline " " bitfld.long 0x00 2. " I2C_ACK ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 1. " I2C_NACK ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 0. " I2C_ARB_LOST ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" group.long 0xF40++0x03 line.long 0x00 "SCB0_INTR_S,Slave Interrupt Request Register" setclrfld.long 0x00 11. 0x04 11. 0x00 11. " SPI_BUS_ERROR ,SPI slave deselected at an unexpected time in the SPI transfer interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 10. 0x04 10. 0x00 10. " SPI_EZ_STOP ,SPI slave deselected after any EZ SPI transfer occurred interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 9. 0x04 9. 0x00 9. " SPI_EZ_WRITE_STOP ,SPI slave deselected after a write EZ SPI transfer occurred interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 8. 0x04 8. 0x00 8. " I2C_BUS_ERROR ,I2C slave bus error interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 7. 0x04 7. 0x00 7. " I2C_GENERAL ,I2C slave general call address received interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 6. 0x04 6. 0x00 6. " I2C_ADDR_MATCH ,I2C slave matching address received interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 5. 0x04 5. 0x00 5. " I2C_START ,I2C slave START received interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 4. 0x04 4. 0x00 4. " I2C_STOP ,I2C STOP event for I2C (read or write) transfer intended for this slave interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 3. 0x04 3. 0x00 3. " I2C_WRITE_STOP ,I2C STOP event for I2C write transfer intended for this slave interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 2. 0x04 2. 0x00 2. " I2C_ACK ,I2C slave acknowledgement received interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 1. 0x04 1. 0x00 1. " I2C_NACK ,I2C slave negative acknowledgement received interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 0. 0x04 0. 0x00 0. " I2C_ARB_LOST ,I2C slave lost arbitration interrupt" "No interrupt,Interrupt" group.long 0xF48++0x03 line.long 0x00 "SCB0_INTR_S_MASK,Slave Interrupt Mask Register" bitfld.long 0x00 11. " SPI_BUS_ERROR ,SPI slave deselected at an unexpected time in the SPI transfer interrupt mask" "Not masked,Masked" bitfld.long 0x00 10. " SPI_EZ_STOP ,SPI slave deselected after any EZ SPI transfer occurred interrupt mask" "Not masked,Masked" bitfld.long 0x00 9. " SPI_EZ_WRITE_STOP ,SPI slave deselected after a write EZ SPI transfer occurred interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 8. " I2C_BUS_ERROR ,I2C slave bus error interrupt mask" "Not masked,Masked" bitfld.long 0x00 7. " I2C_GENERAL ,I2C slave general call address received interrupt mask" "Not masked,Masked" bitfld.long 0x00 6. " I2C_ADDR_MATCH ,I2C slave matching address received interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 5. " I2C_START ,I2C slave START received interrupt mask" "Not masked,Masked" bitfld.long 0x00 4. " I2C_STOP ,I2C STOP event for I2C (read or write) transfer intended for this slave interrupt mask" "Not masked,Masked" bitfld.long 0x00 3. " I2C_WRITE_STOP ,SPI slave deselected at an unexpected time in the SPI transfer interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 2. " I2C_ACK ,SPI slave deselected at an unexpected time in the SPI transfer interrupt mask" "Not masked,Masked" bitfld.long 0x00 1. " I2C_NACK ,I2C slave negative acknowledgement received interrupt mask" "Not masked,Masked" bitfld.long 0x00 0. " I2C_ARB_LOST ,I2C slave lost arbitration interrupt mask" "Not masked,Masked" rgroup.long 0xF4C++0x03 line.long 0x00 "SCB0_INTR_S_MASKED,Slave Interrupt Masked Request Register" bitfld.long 0x00 11. " SPI_BUS_ERROR ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 10. " SPI_EZ_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 9. " SPI_EZ_WRITE_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" textline " " bitfld.long 0x00 8. " I2C_BUS_ERROR ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 7. " I2C_GENERAL ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 6. " I2C_ADDR_MATCH ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" textline " " bitfld.long 0x00 5. " I2C_START ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 4. " I2C_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 3. " I2C_WRITE_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" textline " " bitfld.long 0x00 2. " I2C_ACK ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 1. " I2C_NACK ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 0. " I2C_ARB_LOST ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" group.long 0xF80++0x03 line.long 0x00 "SCB0_INTR_TX_SET/CLR,Transmitter Interrupt Request Register" setclrfld.long 0x00 10. 0x04 10. 0x00 10. " UART_ARB_LOST ,UART lost arbitration interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 9. 0x04 9. 0x00 9. " UART_DONE ,UART transmitter done event interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 8. 0x04 8. 0x00 8. " UART_NACK ,UART transmitter received a negative acknowledgement in SmartCard mode interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 7. 0x04 7. 0x00 7. " BLOCKED ,AHB-Lite write transfer can not get access to the EZ memory interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 6. 0x04 6. 0x00 6. " UNDERFLOW ,Attempt to read from an empty TX FIFO interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 5. 0x04 5. 0x00 5. " OVERFLOW ,Attempt to write to a full TX FIFO interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 4. 0x04 4. 0x00 4. " EMPTY ,TX FIFO is empty interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 1. 0x04 1. 0x00 1. " NOT_FULL ,TX FIFO is not full interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 0. 0x04 0. 0x00 0. " TRIGGER ,Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL interrupt" "No interrupt,Interrupt" group.long 0xF88++0x03 line.long 0x00 "SCB0_INTR_TX_MASK,Transmitter Interrupt Mask Register" bitfld.long 0x00 10. " UART_ARB_LOST ,UART lost arbitration interrupt mask" "Not masked,Masked" bitfld.long 0x00 9. " UART_DONE ,UART transmitter done event interrupt mask" "Not masked,Masked" bitfld.long 0x00 8. " UART_NACK ,UART transmitter received a negative acknowledgement in SmartCard mode interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 7. " BLOCKED ,AHB-Lite write transfer can not get access to the EZ memory interrupt mask" "Not masked,Masked" bitfld.long 0x00 6. " UNDERFLOW ,Attempt to read from an empty TX FIFO interrupt mask" "Not masked,Masked" bitfld.long 0x00 5. " OVERFLOW ,Attempt to write to a full TX FIFO interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 4. " EMPTY ,TX FIFO is empty interrupt mask" "Not masked,Masked" bitfld.long 0x00 1. " NOT_FULL ,TX FIFO is not full interrupt mask" "Not masked,Masked" bitfld.long 0x00 0. " TRIGGER ,Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL interrupt mask" "Not masked,Masked" rgroup.long 0xF8C++0x03 line.long 0x00 "SCB0_INTR_TX_MASKED,Transmitter Interrupt Mask Register" bitfld.long 0x00 10. " UART_ARB_LOST ,Logical AND of corresponding request and mask bits" "Not masked,Masked" bitfld.long 0x00 9. " UART_DONE ,Logical AND of corresponding request and mask bits" "Not masked,Masked" bitfld.long 0x00 8. " UART_NACK ,Logical AND of corresponding request and mask bits" "Not masked,Masked" textline " " bitfld.long 0x00 7. " BLOCKED ,Logical AND of corresponding request and mask bits" "Not masked,Masked" bitfld.long 0x00 6. " UNDERFLOW ,Logical AND of corresponding request and mask bits" "Not masked,Masked" bitfld.long 0x00 5. " OVERFLOW ,Logical AND of corresponding request and mask bits" "Not masked,Masked" textline " " bitfld.long 0x00 4. " EMPTY ,Logical AND of corresponding request and mask bits" "Not masked,Masked" bitfld.long 0x00 1. " NOT_FULL ,Logical AND of corresponding request and mask bits" "Not masked,Masked" bitfld.long 0x00 0. " TRIGGER ,Logical AND of corresponding request and mask bits" "Not masked,Masked" group.long 0xFC0++0x03 line.long 0x00 "SCB0_INTR_RX,Receiver Interrupt Request Register" setclrfld.long 0x00 11. 0x04 11. 0x00 11. " BREAK_DETECT ,Break detection interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 10. 0x04 10. 0x00 10. " BAUD_DETECT ,LIN baudrate detection interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 9. 0x04 9. 0x00 9. " PARITY_ERROR ,Parity error in received data frame interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 8. 0x04 8. 0x00 8. " FRAME_ERROR ,Frame error in received data frame interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 7. 0x04 7. 0x00 7. " BLOCKED ,AHB-Lite read transfer access to the EZ memory interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 6. 0x04 6. 0x00 6. " UNDERFLOW ,Attempt to read from an empty RX FIFO interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 5. 0x04 5. 0x00 5. " OVERFLOW ,Attempt to write to a full RX FIFO interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 3. 0x04 3. 0x00 3. " FULL ,RX FIFO is full interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 2. 0x04 2. 0x00 2. " NOT_EMPTY ,RX FIFO is not empty interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 0. 0x04 0. 0x00 0. " TRIGGER ,More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in SCB_RX_FIFO_CTL interrupt" "No interrupt,Interrupt" group.long 0xFC8++0x03 line.long 0x00 "SCB0_INTR_RX_MASK,Receiver Interrupt Mask Register" bitfld.long 0x00 11. " BREAK_DETECT ,BREAK_DETECT interrupt mask" "Not masked,Masked" bitfld.long 0x00 10. " BAUD_DETECT ,BAUD_DETECT interrupt mask" "Not masked,Masked" bitfld.long 0x00 9. " PARITY_ERROR ,PARITY_ERROR interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 8. " FRAME_ERROR ,FRAME_ERROR interrupt mask" "Not masked,Masked" bitfld.long 0x00 7. " BLOCKED ,BLOCKED interrupt mask" "Not masked,Masked" bitfld.long 0x00 6. " UNDERFLOW ,UNDERFLOW interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 5. " OVERFLOW ,OVERFLOW interrupt mask" "Not masked,Masked" bitfld.long 0x00 3. " FULL ,FULL interrupt mask" "Not masked,Masked" bitfld.long 0x00 2. " NOT_EMPTY ,NOT_EMPTY interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 0. " TRIGGER ,TRIGGER interrupt mask" "Not masked,Masked" rgroup.long 0xFCC++0x03 line.long 0x00 "SCB0_INTR_RX_MASKED,Receiver Interrupt Masked Request Register" bitfld.long 0x00 11. " BREAK_DETECT ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 10. " BAUD_DETECT ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 9. " PARITY_ERROR ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" textline " " bitfld.long 0x00 8. " FRAME_ERROR ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 7. " BLOCKED ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 6. " UNDERFLOW ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" textline " " bitfld.long 0x00 5. " OVERFLOW ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 3. " FULL ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 2. " NOT_EMPTY ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " TRIGGER ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" width 0x0B tree.end tree "SCB1" base ad:0x40250000 if (((per.l(ad:0x40250000))&0x3000000)==0x0000000) width 12. if (((per.l(ad:0x40250000))&0x200)==0x200) if (((per.l(ad:0x40250000))&0x80000000)==0x80000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked" textline " " rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" else group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked" textline " " bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" endif else if (((per.l(ad:0x40250000))&0x80000000)==0x80000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." textline " " rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" else group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." textline " " bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" endif endif rgroup.long 0x04++0x03 line.long 0x00 "STATUS,Generic Status Register" bitfld.long 0x00 0. " EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy" if (((per.l(ad:0x40250000+0x60))&0xC0000000)==0xC0000000) if (((per.l(ad:0x40250000))&0x100)==0x100)&&((((per.l(ad:0x40250000))&0x200)==0x000)||(((per.l(ad:0x40250000+0x60))&0x800)==0x800)||(((per.l(ad:0x40250000))&0x400)==0x400)) if (((per.l(ad:0x40250000))&0x400)==0x000) group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 14. " S_NOT_READY_ADDR_NACK ,Slave not ready address NACK" "Ready,Not ready" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" else group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" endif elif (((per.l(ad:0x40250000))&0x100)==0x000)&&(((per.l(ad:0x40250000))&0x200)==0x000)&&(((per.l(ad:0x40250000))&0x400)==0x000) group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" else if (((per.l(ad:0x40250000))&0x400)==0x400) group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" else group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" endif endif elif (((per.l(ad:0x40250000+0x60))&0xC0000000)==0x80000000) if (((per.l(ad:0x40250000))&0x100)==0x100)&&((((per.l(ad:0x40250000))&0x200)==0x000)||(((per.l(ad:0x40250000+0x60))&0x800)==0x800)||(((per.l(ad:0x40250000))&0x400)==0x400)) if (((per.l(ad:0x40250000))&0x400)==0x000) group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 14. " S_NOT_READY_ADDR_NACK ,Slave not ready address NACK" "Ready,Not ready" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" bitfld.long 0x00 4.--7. " LOW_PHASE_OVS ,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " HIGH_PHASE_OVS ,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" bitfld.long 0x00 4.--7. " LOW_PHASE_OVS ,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " HIGH_PHASE_OVS ,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif (((per.l(ad:0x40250000))&0x100)==0x000)&&(((per.l(ad:0x40250000))&0x200)==0x000)&&(((per.l(ad:0x40250000))&0x400)==0x000) group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" bitfld.long 0x00 4.--7. " LOW_PHASE_OVS ,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " HIGH_PHASE_OVS ,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else if (((per.l(ad:0x40250000))&0x400)==0x400) group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" bitfld.long 0x00 4.--7. " LOW_PHASE_OVS ,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " HIGH_PHASE_OVS ,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" bitfld.long 0x00 4.--7. " LOW_PHASE_OVS ,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " HIGH_PHASE_OVS ,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif endif elif (((per.l(ad:0x40250000+0x60))&0xC0000000)==0x40000000) if (((per.l(ad:0x40250000))&0x100)==0x100)&&((((per.l(ad:0x40250000))&0x200)==0x000)||(((per.l(ad:0x40250000+0x60))&0x800)==0x800)||(((per.l(ad:0x40250000))&0x400)==0x400)) if (((per.l(ad:0x40250000))&0x400)==0x000) group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 14. " S_NOT_READY_ADDR_NACK ,Slave not ready address NACK" "Ready,Not ready" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" else group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" endif elif (((per.l(ad:0x40250000))&0x100)==0x000)&&(((per.l(ad:0x40250000))&0x200)==0x000)&&(((per.l(ad:0x40250000))&0x400)==0x000) group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" else if (((per.l(ad:0x40250000))&0x400)==0x400) group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" else group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" endif endif else if (((per.l(ad:0x40250000))&0x100)==0x100)&&((((per.l(ad:0x40250000))&0x200)==0x000)||(((per.l(ad:0x40250000+0x60))&0x800)==0x800)||(((per.l(ad:0x40250000))&0x400)==0x400)) if (((per.l(ad:0x40250000))&0x400)==0x000) group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 14. " S_NOT_READY_ADDR_NACK ,Slave not ready address NACK" "Ready,Not ready" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" else group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" endif elif (((per.l(ad:0x40250000))&0x100)==0x000)&&(((per.l(ad:0x40250000))&0x200)==0x000)&&(((per.l(ad:0x40250000))&0x400)==0x000) group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" else if (((per.l(ad:0x40250000))&0x400)==0x400) group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" else group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" endif endif endif if (((per.l(ad:0x40250000))&0x200)==0x000) rgroup.long 0x64++0x03 line.long 0x00 "I2C_STATUS,I2C Status Register" hexmask.long.byte 0x00 16.--23. 1. " BASE_EZ_ADDR ,I2C slave base EZ address" hexmask.long.byte 0x00 8.--15. 1. " CURR_EZ_ADDR ,I2C slave current EZ address" bitfld.long 0x00 5. " M_READ ,I2C master read transfer" "Write transfer,Read transfer" textline " " bitfld.long 0x00 4. " S_READ ,I2C slave read transfer" "Write transfer,Read transfer" bitfld.long 0x00 1. " I2C_EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy" bitfld.long 0x00 0. " BUS_BUSY ,I2C bus is busy" "Not busy,Busy" else rgroup.long 0x64++0x03 line.long 0x00 "I2C_STATUS,I2C Status Register" bitfld.long 0x00 5. " M_READ ,I2C master read transfer" "Write transfer,Read transfer" textline " " bitfld.long 0x00 4. " S_READ ,I2C slave read transfer" "Write transfer,Read transfer" bitfld.long 0x00 1. " I2C_EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy" bitfld.long 0x00 0. " BUS_BUSY ,I2C bus is busy" "Not busy,Busy" endif if (((per.l(ad:0x40250000+0x60))&0x80000000)==0x80000000) group.long 0x68++0x03 line.long 0x00 "I2C_M_CMD,I2C Master Command Register" bitfld.long 0x00 4. " M_STOP ,Master transmit STOP" "Disabled,ENABLED" bitfld.long 0x00 3. " M_NACK ,Master negative acknowledgement transmit" "Disabled,Enabled" bitfld.long 0x00 2. " M_ACK ,Master acknowledgement transmit" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " M_START_ON_IDLE ,Master START on idle" "Disabled,Enabled" bitfld.long 0x00 0. " M_START ,Master transmit START" "Disabled,Enabled" else hgroup.long 0x68++0x03 hide.long 0x00 "I2C_M_CMD,I2C Master Command Register" endif if (((per.l(ad:0x40250000+0x60))&0x40000000)==0x40000000) if (((per.l(ad:0x40250000))&0x400)==0x400) group.long 0x6C++0x03 line.long 0x00 "I2C_S_CMD,I2C Slave Command Register" bitfld.long 0x00 1. " S_NACK ,Slave negative acknowledgement transmit" "Disabled,Enabled" bitfld.long 0x00 0. " S_ACK ,Slave acknowledgement transmit" "Disabled,Enabled" else group.long 0x6C++0x03 line.long 0x00 "I2C_S_CMD,I2C Slave Command Register" bitfld.long 0x00 1. " S_NACK ,Slave negative acknowledgement transmit" "Disabled,Enabled" endif else hgroup.long 0x6C++0x03 hide.long 0x00 "I2C_S_CMD,I2C Slave Command Register" endif group.long 0x70++0x03 line.long 0x00 "I2C_CFG,I2C Configuration Register" bitfld.long 0x00 28.--29. " SDA_OUT_FILT_SEL ,Selection of cumulative 'i2c_sda_out' filter delay" "0 ns,50 ns,100 ns,150 ns" bitfld.long 0x00 20.--21. " SDA_OUT_FILT2_TRIM ,Trim bits for 'i2c_sda_out' 50 ns filter 2" "0,1,2,3" bitfld.long 0x00 18.--19. " SDA_OUT_FILT1_TRIM ,Trim bits for 'i2c_sda_out' 50 ns filter 1" "0,1,2,3" textline " " bitfld.long 0x00 16.--17. " SDA_OUT_FILT0_TRIM ,Trim bits for 'i2c_sda_out' 50 ns filter 0" "0,1,2,3" bitfld.long 0x00 12. " SCL_IN_FILT_SEL ,Selection of 'i2c_sda_in' filter delay" "0 ns,50 ns" bitfld.long 0x00 8.--9. " SCL_IN_FILT_TRIM ,Trim bits for 'i2c_sda_in' 50 ns filter" "0,1,2,3" textline " " bitfld.long 0x00 4. " SDA_IN_FILT_SEL ,Selection of 'i2c_sda_in' filter delay" "0 ns,50 ns" bitfld.long 0x00 0.--1. " SDA_IN_FILT_TRIM ,Trim bits for 'i2c_sda_in' 50 ns filter" "0,1,2,3" width 0x0B elif (((per.l(ad:0x40250000))&0x3000000)==0x1000000) width 22. if (((per.l(ad:0x40250000+0x20))&0x80000000)==0x80000000) if (((per.l(ad:0x40250000))&0x200)==0x200) if (((per.l(ad:0x40250000))&0x80000000)==0x80000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked" textline " " rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked" rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked" textline " " bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked" bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else if (((per.l(ad:0x40250000))&0x80000000)==0x80000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." textline " " rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked" rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." textline " " bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked" bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15" endif endif rgroup.long 0x04++0x03 line.long 0x00 "STATUS,Generic Status Register" bitfld.long 0x00 0. " EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy" if (((per.l(ad:0x40250000+0x20))&0x3000000)==0x0000000) if (((per.l(ad:0x40250000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40250000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x0000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40250000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40250000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x4000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40250000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40250000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x8000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40250000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40250000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0xC000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40250000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40250000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x0000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40250000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40250000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x4000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40250000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40250000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x8000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40250000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40250000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0xC000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40250000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40250000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x0000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40250000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40250000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x4000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40250000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40250000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x8000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40250000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40250000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0xC000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40250000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40250000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x0000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40250000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40250000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x4000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40250000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40250000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x8000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40250000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40250000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0xC000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" endif elif (((per.l(ad:0x40250000+0x20))&0x3000000)==0x2000000) if (((per.l(ad:0x40250000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x0000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40250000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x4000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40250000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x8000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40250000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0xC000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40250000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x0000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40250000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x4000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40250000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x8000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40250000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0xC000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" endif elif (((per.l(ad:0x40250000+0x20))&0x3000000)==0x1000000) if (((per.l(ad:0x40250000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x0000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "High,Low" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides" bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40250000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x4000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "High,Low" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides" bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40250000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x8000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "High,Low" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides" bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40250000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0xC000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "High,Low" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides" bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40250000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x0000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "High,Low" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides" bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40250000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x4000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "High,Low" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides" bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40250000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x8000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "High,Low" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides" bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40250000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0xC000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "High,Low" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides" bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" endif else if (((per.l(ad:0x40250000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x0000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40250000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x4000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40250000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x8000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40250000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0xC000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40250000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x0000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40250000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x4000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40250000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0x8000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40250000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40250000+0x20))&0xC000000)==0xC000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" endif endif else if (((per.l(ad:0x40250000))&0x200)==0x200) if (((per.l(ad:0x40250000))&0x80000000)==0x80000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked" textline " " rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked" else group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked" textline " " bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked" endif else if (((per.l(ad:0x40250000))&0x80000000)==0x80000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." textline " " rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" else group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." textline " " bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" endif endif rgroup.long 0x04++0x03 line.long 0x00 "STATUS,Generic Status Register" bitfld.long 0x00 0. " EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy" if (((per.l(ad:0x40250000+0x20))&0x3000000)==0x0000000) if (((per.l(ad:0x40250000+0x20))&0x8)==0x0) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge" else group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge" endif elif (((per.l(ad:0x40250000+0x20))&0x3000000)==0x2000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." elif (((per.l(ad:0x40250000+0x20))&0x3000000)==0x1000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." else group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." endif endif if (((per.l(ad:0x40250000))&0x200)==0x000) rgroup.long 0x24++0x03 line.long 0x00 "SPI_STATUS,SPI Status Register" hexmask.long.byte 0x00 16.--23. 0x01 " BASE_EZ_ADDR ,SPI base EZ address" hexmask.long.byte 0x00 8.--15. 0x01 " CURR_EZ_ADDR ,SPI current EZ address" bitfld.long 0x00 1. " SPI_EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy" textline " " bitfld.long 0x00 0. " BUS_BUSY ,SPI bus is busy" "Not busy,Busy" else rgroup.long 0x24++0x03 line.long 0x00 "SPI_STATUS,SPI Status Register" bitfld.long 0x00 1. " SPI_EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy" textline " " bitfld.long 0x00 0. " BUS_BUSY ,SPI bus is busy" "Not busy,Busy" endif width 0x0B elif (((per.l(ad:0x40250000))&0x3000000)==0x2000000) width 21. if (((per.l(ad:0x40250000))&0x200)==0x200) if (((per.l(ad:0x40250000))&0x80000000)==0x80000000) if (((per.l(ad:0x40250000+0x40))&0x3000000)==0x0000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked" textline " " rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15" elif (((per.l(ad:0x40250000+0x40))&0x3000000)==0x1000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked" textline " " rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15" elif (((per.l(ad:0x40250000+0x40))&0x3000000)==0x2000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked" textline " " rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" "16,32,48,96,192,768,1536,?..." endif else if (((per.l(ad:0x40250000+0x40))&0x3000000)==0x0000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked" textline " " bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15" elif (((per.l(ad:0x40250000+0x40))&0x3000000)==0x1000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked" textline " " bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15" elif (((per.l(ad:0x40250000+0x40))&0x3000000)==0x2000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked" textline " " bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" "16,32,48,96,192,768,1536,?..." endif endif else if (((per.l(ad:0x40250000))&0x80000000)==0x80000000) if (((per.l(ad:0x40250000+0x40))&0x3000000)==0x0000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." textline " " rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15" elif (((per.l(ad:0x40250000+0x40))&0x3000000)==0x1000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." textline " " rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15" elif (((per.l(ad:0x40250000+0x40))&0x3000000)==0x2000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." textline " " rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" "16,?..." endif else if (((per.l(ad:0x40250000+0x40))&0x3000000)==0x0000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." textline " " bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15" elif (((per.l(ad:0x40250000+0x40))&0x3000000)==0x1000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." textline " " bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15" elif (((per.l(ad:0x40250000+0x40))&0x3000000)==0x2000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." textline " " bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" "16,?..." endif endif endif rgroup.long 0x04++0x03 line.long 0x00 "STATUS,Generic Status Register" bitfld.long 0x00 0. " EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy" group.long 0x40++0x03 line.long 0x00 "UART_CTRL,UART Control Register" bitfld.long 0x00 24.--25. " MODE ,Submode of UART operation" "UART_STD,UART_SMARTCARD,UART_IRDA,?..." bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" if (((per.l(ad:0x40250000+0x40))&0x3000000)==0x0000000) group.long 0x44++0x07 line.long 0x00 "UART_TX_CTRL,UART Transmitter Control Register" bitfld.long 0x00 5. " PARITY_ENABLED ,Parity generation enabled" "Disabled,Enabled" rbitfld.long 0x00 4. " PARITY ,Parity bit" "Even,Odd" textline " " bitfld.long 0x00 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7" line.long 0x04 "UART_RX_CTRL,UART Receiver Control Register" bitfld.long 0x04 16.--19. " BREAK_WIDTH ,Break width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 13. " SKIP_START ,Skips start bit detection for the first received data frame" "Disabled,Enabled" bitfld.long 0x04 12. " LIN_MODE ,Break detection and baud rate detection on the incoming data" "Disabled,Enabled" textline " " bitfld.long 0x04 10. " MP_MODE ,Multi-processor mode" "Disabled,Enabled" bitfld.long 0x04 9. " DROP_ON_FRAME_ERROR ,Behaviour when an error is detected in a start or stop period" "Data send to RX FIFO,Data dropped" bitfld.long 0x04 8. " DROP_ON_PARITY_ERROR ,Behaviour when a parity check fails" "Data send to RX FIFO,Data dropped" textline " " bitfld.long 0x04 5. " PARITY_ENABLED ,Parity checking enabled" "Disabled,Enabled" bitfld.long 0x04 4. " PARITY ,Parity bit" "Even,Odd" bitfld.long 0x04 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7" elif (((per.l(ad:0x40250000+0x40))&0x3000000)==0x1000000) group.long 0x44++0x07 line.long 0x00 "UART_TX_CTRL,UART Transmitter Control Register" bitfld.long 0x00 8. " RETRY_ON_NACK ,Retransmitted when negative acknowledgement is received" "Not retransmitted,Retransmitted" rbitfld.long 0x00 4. " PARITY ,Parity bit" "Even,Odd" textline " " bitfld.long 0x00 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7" line.long 0x04 "UART_RX_CTRL,UART Receiver Control Register" bitfld.long 0x04 16.--19. " BREAK_WIDTH ,Break width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x04 10. " MP_MODE ,Multi-processor mode" "Disabled,Enabled" bitfld.long 0x04 9. " DROP_ON_FRAME_ERROR ,Behaviour when an error is detected in a start or stop period" "Data send to RX FIFO,Data dropped" bitfld.long 0x04 8. " DROP_ON_PARITY_ERROR ,Behaviour when a parity check fails" "Data send to RX FIFO,Data dropped" textline " " bitfld.long 0x04 4. " PARITY ,Parity bit" "Even,Odd" bitfld.long 0x04 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7" elif (((per.l(ad:0x40250000+0x40))&0x3000000)==0x2000000) group.long 0x44++0x07 line.long 0x00 "UART_TX_CTRL,UART Transmitter Control Register" bitfld.long 0x00 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7" line.long 0x04 "UART_RX_CTRL,UART Receiver Control Register" bitfld.long 0x04 16.--19. " BREAK_WIDTH ,Break width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x04 10. " MP_MODE ,Multi-processor mode" "Disabled,Enabled" bitfld.long 0x04 9. " DROP_ON_FRAME_ERROR ,Behaviour when an error is detected in a start or stop period" "Data send to RX FIFO,Data dropped" textline " " bitfld.long 0x04 6. " POLARITY ,Inverts incoming RX line signal" "Low,High" bitfld.long 0x04 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7" endif rgroup.long 0x4C++0x03 line.long 0x00 "UART_RX_STATUS,UART Receiver Status Register" hexmask.long.word 0x00 0.--11. 1. " BR_COUNTER ,Amount of peripheral clock periods that constitute the transmission of a 0x55 data frame" group.long 0x50++0x03 line.long 0x00 "UART_FLOW_CTRL,UART Flow Control Register" bitfld.long 0x00 25. " CTS_ENABLED ,Enable use of CTS input signal" "Disabled,Enabled" bitfld.long 0x00 24. " CTS_POLARITY ,Polarity of the CTS input signal" "Low,High" bitfld.long 0x00 16. " RTS_POLARITY ,Polarity of the RTS output signal" "Low,High" textline " " bitfld.long 0x00 0.--3. " TRIGGER_LEVEL ,Trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B else width 18. if (((per.l(ad:0x40250000))&0x80000000)==0x80000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." else group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." endif endif textline " " width 28. if (((per.l(ad:0x40250000))&0x3000000)==0x2000000) group.long 0x200++0x03 line.long 0x00 "SCB1_TX_CTRL,Transmitter Control Register" bitfld.long 0x00 8. " MSB_FIRST ,Most significant bit first" "LSB,MSB" bitfld.long 0x00 0.--3. " DATA_WIDTH ,Dataframe width" ",,,3,4,5,6,7,8,?..." elif (((per.l(ad:0x40250000))&0x3000000)==0x1000000) group.long 0x200++0x03 line.long 0x00 "SCB1_TX_CTRL,Transmitter Control Register" bitfld.long 0x00 8. " MSB_FIRST ,Most significant bit first" "LSB,MSB" bitfld.long 0x00 0.--3. " DATA_WIDTH ,Dataframe width" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x200++0x03 line.long 0x00 "SCB1_TX_CTRL,Transmitter Control Register" bitfld.long 0x00 8. " MSB_FIRST ,Most significant bit first" "LSB,MSB" bitfld.long 0x00 0.--3. " DATA_WIDTH ,Dataframe width" ",,,,,,,7,?..." endif group.long 0x204++0x03 line.long 0x00 "SCB1_TX_FIFO_CTRL,Transmitter FIFO Control Register" bitfld.long 0x00 17. " FREEZE ,FIFO entries remove freeze" "Disabled,Enabled" bitfld.long 0x00 16. " CLEAR ,FIFO and transmitter shift register clear" "Not cleared,Cleared" bitfld.long 0x00 0.--3. " TRIGGER_LEVEL ,Trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x208++0x03 line.long 0x00 "SCB1_TX_FIFO_STATUS,Transmitter FIFO Status Register" bitfld.long 0x00 24.--27. " WR_PTR ,FIFO write pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " RD_PTR ,FIFO read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " SR_VALID ,TX shift registers valid data frame hold" "No,Yes" textline " " bitfld.long 0x00 0.--4. " USED ,Amount of enties in the transmitter FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x40250000))&0x800)==0x800) wgroup.long 0x240++0x03 line.long 0x00 "SCB1_TX_FIFO_WR,Transmitter FIFO Write Register" hexmask.long.byte 0x00 0.--7. 1. " DATA ,Data frame written into the transmitter FIFO" else wgroup.long 0x240++0x03 line.long 0x00 "SCB1_TX_FIFO_WR,Transmitter FIFO Write Register" hexmask.long.word 0x00 0.--15. 1. " DATA ,Data frame written into the transmitter FIFO" endif if (((per.l(ad:0x40250000))&0x3000400)==0x1000400) group.long 0x300++0x03 line.long 0x00 "SCB1_RX_CTRL,Transmitter Control Register" bitfld.long 0x00 9. " MEDIAN ,Median filter" "Off,On" bitfld.long 0x00 8. " MSB_FIRST ,Most significant bit first" "LSB,MSB" bitfld.long 0x00 0.--3. " DATA_WIDTH ,Dataframe width" ",,,,,,,7,?..." elif (((per.l(ad:0x40250000))&0x3000400)==0x1000400) group.long 0x300++0x03 line.long 0x00 "SCB1_RX_CTRL,Transmitter Control Register" bitfld.long 0x00 9. " MEDIAN ,Median filter" "Off,On" bitfld.long 0x00 8. " MSB_FIRST ,Most significant bit first" "LSB,MSB" bitfld.long 0x00 0.--3. " DATA_WIDTH ,Dataframe width" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((per.l(ad:0x40250000))&0x3000000)==0x2000000) group.long 0x300++0x03 line.long 0x00 "SCB1_RX_CTRL,Transmitter Control Register" bitfld.long 0x00 9. " MEDIAN ,Median filter" "Off,On" bitfld.long 0x00 8. " MSB_FIRST ,Most significant bit first" "LSB,MSB" bitfld.long 0x00 0.--3. " DATA_WIDTH ,Dataframe width" ",,,3,4,5,6,7,8,?..." else group.long 0x300++0x03 line.long 0x00 "SCB1_RX_CTRL,Transmitter Control Register" bitfld.long 0x00 9. " MEDIAN ,Median filter" "Off,On" bitfld.long 0x00 8. " MSB_FIRST ,Most significant bit first" "LSB,MSB" bitfld.long 0x00 0.--3. " DATA_WIDTH ,Dataframe width" ",,,,,,,7,?..." endif group.long 0x304++0x03 line.long 0x00 "SCB1_RX_FIFO_CTRL,Receiver FIFO Control Register" bitfld.long 0x00 17. " FREEZE ,Receiver FIFO have no effect" "Disabled,Enabled" bitfld.long 0x00 16. " CLEAR ,FIFO and receiver shift register clear" "Not cleared,Cleared" bitfld.long 0x00 0.--3. " TRIGGER_LEVEL ,Trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x308++0x03 line.long 0x00 "SCB1_RX_FIFO_STATUS,Receiver FIFO Status Register" bitfld.long 0x00 24.--27. " WR_PTR ,FIFO write pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " RD_PTR ,FIFO read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " SR_VALID ,RX shift registers valid data frame hold" "No,Yes" textline " " bitfld.long 0x00 0.--4. " USED ,Amount of enties in the receiver FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x310++0x03 line.long 0x00 "SCB1_RX_MATCH,Slave Address and Mask Register" hexmask.long.byte 0x00 16.--23. 0x01 " MASK ,Slave device address mask" hexmask.long.byte 0x00 0.--7. 0x01 " ADDR ,Slave device address" if (((per.l(ad:0x40250000))&0x800)==0x800) rgroup.long 0x340++0x07 line.long 0x00 "SCB1_RX_FIFO_RD,Receiver FIFO Read Register" hexmask.long.word 0x00 0.--15. 0x01 " DATA ,Data read from the receiver FIFO" line.long 0x04 "SCB1_RX_FIFO_RD_SILENT,Receiver FIFO Read Register" hexmask.long.word 0x04 0.--15. 0x01 " DATA ,Data read from the receiver FIFO" else rgroup.long 0x340++0x07 line.long 0x00 "SCB1_RX_FIFO_RD,Receiver FIFO Read Register" hexmask.long.byte 0x00 0.--7. 0x01 " DATA ,Data read from the receiver FIFO" line.long 0x04 "SCB1_RX_FIFO_RD_SILENT,Receiver FIFO Read Register" hexmask.long.byte 0x04 0.--7. 0x01 " DATA ,Data read from the receiver FIFO" endif group.long 0x400++0x03 line.long 0x00 "SCB1_EZ_DATA0,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x404++0x03 line.long 0x00 "SCB1_EZ_DATA1,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x408++0x03 line.long 0x00 "SCB1_EZ_DATA2,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x40C++0x03 line.long 0x00 "SCB1_EZ_DATA3,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x410++0x03 line.long 0x00 "SCB1_EZ_DATA4,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x414++0x03 line.long 0x00 "SCB1_EZ_DATA5,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x418++0x03 line.long 0x00 "SCB1_EZ_DATA6,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x41C++0x03 line.long 0x00 "SCB1_EZ_DATA7,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x420++0x03 line.long 0x00 "SCB1_EZ_DATA8,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x424++0x03 line.long 0x00 "SCB1_EZ_DATA9,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x428++0x03 line.long 0x00 "SCB1_EZ_DATA10,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x42C++0x03 line.long 0x00 "SCB1_EZ_DATA11,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x430++0x03 line.long 0x00 "SCB1_EZ_DATA12,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x434++0x03 line.long 0x00 "SCB1_EZ_DATA13,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x438++0x03 line.long 0x00 "SCB1_EZ_DATA14,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x43C++0x03 line.long 0x00 "SCB1_EZ_DATA15,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x440++0x03 line.long 0x00 "SCB1_EZ_DATA16,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x444++0x03 line.long 0x00 "SCB1_EZ_DATA17,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x448++0x03 line.long 0x00 "SCB1_EZ_DATA18,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x44C++0x03 line.long 0x00 "SCB1_EZ_DATA19,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x450++0x03 line.long 0x00 "SCB1_EZ_DATA20,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x454++0x03 line.long 0x00 "SCB1_EZ_DATA21,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x458++0x03 line.long 0x00 "SCB1_EZ_DATA22,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x45C++0x03 line.long 0x00 "SCB1_EZ_DATA23,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x460++0x03 line.long 0x00 "SCB1_EZ_DATA24,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x464++0x03 line.long 0x00 "SCB1_EZ_DATA25,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x468++0x03 line.long 0x00 "SCB1_EZ_DATA26,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x46C++0x03 line.long 0x00 "SCB1_EZ_DATA27,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x470++0x03 line.long 0x00 "SCB1_EZ_DATA28,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x474++0x03 line.long 0x00 "SCB1_EZ_DATA29,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x478++0x03 line.long 0x00 "SCB1_EZ_DATA30,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x47C++0x03 line.long 0x00 "SCB1_EZ_DATA31,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" rgroup.long 0xE00++0x03 line.long 0x00 "SCB1_INTR_CAUSE,Active Clocked Interrupt Signal Register" bitfld.long 0x00 5. " SPI_EC ,Externally clocked SPI interrupt active" "Not active,Active" bitfld.long 0x00 4. " I2C_EC ,Externally clock I2C interrupt active" "Not active,Active" bitfld.long 0x00 3. " RX ,Receiver interrupt active" "Not active,Active" textline " " bitfld.long 0x00 2. " TX ,Transmitter interrupt active" "Not active,Active" bitfld.long 0x00 1. " S ,Slave interrupt active" "Not active,Active" bitfld.long 0x00 0. " M ,Master interrupt active" "Not active,Active" if (((per.l(ad:0x40250000))&0x700)==0x700) group.long 0xE80++0x03 line.long 0x00 "SCB1_INTR_I2C_EC,Externally Clocked I2C Interrupt Request Register" eventfld.long 0x00 3. " EZ_READ_STOP ,STOP detection after a read transfer occurred" "No interrupt,Interrupt" eventfld.long 0x00 2. " EZ_WRITE_STOP ,STOP detection after a write transfer occurred" "No interrupt,Interrupt" eventfld.long 0x00 1. " EZ_STOP ,STOP detection" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " WAKE_UP ,Wake up request" "No interrupt,Interrupt" group.long 0xE88++0x03 line.long 0x00 "SCB1_INTR_I2C_EC_MASK,Externally Clocked I2C Interrupt Mask Register" bitfld.long 0x00 3. " EZ_READ_STOP ,STOP detection after a read transfer occurred interrupt mask" "Not masked,Masked" bitfld.long 0x00 2. " EZ_WRITE_STOP ,STOP detection after a write transfer occurred interrupt mask" "Not masked,Masked" bitfld.long 0x00 1. " EZ_STOP ,STOP detection interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 0. " WAKE_UP ,Wake up request interrupt mask" "Not masked,Masked" rgroup.long 0xE8C++0x03 line.long 0x00 "SCB1_INTR_I2C_EC_MASKED,Externally Clocked I2C Interrupt Masked Register" bitfld.long 0x00 3. " EZ_READ_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 2. " EZ_WRITE_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 1. " EZ_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " WAKE_UP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" group.long 0xEC0++0x03 line.long 0x00 "SCB1_INTR_SPI_EC,Externally Clocked SPI Interrupt Request Register" eventfld.long 0x00 3. " EZ_READ_STOP ,STOP detection after a read transfer occurred" "No interrupt,Interrupt" eventfld.long 0x00 2. " EZ_WRITE_STOP ,STOP detection after a write transfer occurred" "No interrupt,Interrupt" eventfld.long 0x00 1. " EZ_STOP ,STOP detection" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " WAKE_UP ,Wake up request" "No interrupt,Interrupt" group.long 0xEC8++0x03 line.long 0x00 "SCB1_INTR_SPI_EC_MASK,Externally Clocked SPI Interrupt Mask Register" bitfld.long 0x00 3. " EZ_READ_STOP ,STOP detection after a read transfer occurred interrupt mask" "Not masked,Masked" bitfld.long 0x00 2. " EZ_WRITE_STOP ,STOP detection after a write transfer occurred interrupt mask" "Not masked,Masked" bitfld.long 0x00 1. " EZ_STOP ,STOP detection interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 0. " WAKE_UP ,Wake up request interrupt mask" "Not masked,Masked" rgroup.long 0xE8C++0x03 line.long 0x00 "SCB1_INTR_SPI_EC_MASKED,Externally Clocked SPI Interrupt Masked Register" bitfld.long 0x00 3. " EZ_READ_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 2. " EZ_WRITE_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 1. " EZ_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " WAKE_UP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" elif (((per.l(ad:0x40250000))&0x700)==0x600) group.long 0xE80++0x03 line.long 0x00 "SCB1_INTR_I2C_EC,Externally Clocked I2C Interrupt Request Register" eventfld.long 0x00 3. " EZ_READ_STOP ,STOP detection after a read transfer occurred" "No interrupt,Interrupt" eventfld.long 0x00 2. " EZ_WRITE_STOP ,STOP detection after a write transfer occurred" "No interrupt,Interrupt" eventfld.long 0x00 1. " EZ_STOP ,STOP detection" "No interrupt,Interrupt" group.long 0xE88++0x03 line.long 0x00 "SCB1_INTR_I2C_EC_MASK,Externally Clocked I2C Interrupt Mask Register" bitfld.long 0x00 3. " EZ_READ_STOP ,STOP detection after a read transfer occurred interrupt mask" "Not masked,Masked" bitfld.long 0x00 2. " EZ_WRITE_STOP ,STOP detection after a write transfer occurred interrupt mask" "Not masked,Masked" bitfld.long 0x00 1. " EZ_STOP ,STOP detection interrupt mask" "Not masked,Masked" rgroup.long 0xE8C++0x03 line.long 0x00 "SCB1_INTR_I2C_EC_MASKED,Externally Clocked I2C Interrupt Masked Register" bitfld.long 0x00 3. " EZ_READ_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 2. " EZ_WRITE_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 1. " EZ_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" group.long 0xEC0++0x03 line.long 0x00 "SCB1_INTR_SPI_EC,Externally Clocked SPI Interrupt Request Register" eventfld.long 0x00 3. " EZ_READ_STOP ,STOP detection after a read transfer occurred" "No interrupt,Interrupt" eventfld.long 0x00 2. " EZ_WRITE_STOP ,STOP detection after a write transfer occurred" "No interrupt,Interrupt" eventfld.long 0x00 1. " EZ_STOP ,STOP detection" "No interrupt,Interrupt" group.long 0xEC8++0x03 line.long 0x00 "SCB1_INTR_SPI_EC_MASK,Externally Clocked SPI Interrupt Mask Register" bitfld.long 0x00 3. " EZ_READ_STOP ,STOP detection after a read transfer occurred interrupt mask" "Not masked,Masked" bitfld.long 0x00 2. " EZ_WRITE_STOP ,STOP detection after a write transfer occurred interrupt mask" "Not masked,Masked" bitfld.long 0x00 1. " EZ_STOP ,STOP detection interrupt mask" "Not masked,Masked" rgroup.long 0xE8C++0x03 line.long 0x00 "SCB1_INTR_SPI_EC_MASKED,Externally Clocked SPI Interrupt Masked Register" bitfld.long 0x00 3. " EZ_READ_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 2. " EZ_WRITE_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 1. " EZ_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" elif (((per.l(ad:0x40250000))&0x700)==0x000) group.long 0xE80++0x03 line.long 0x00 "SCB1_INTR_I2C_EC,Externally Clocked I2C Interrupt Request Register" group.long 0xE88++0x03 line.long 0x00 "SCB1_INTR_I2C_EC_MASK,Externally Clocked I2C Interrupt Mask Register" rgroup.long 0xE8C++0x03 line.long 0x00 "SCB1_INTR_I2C_EC_MASKED,Externally Clocked I2C Interrupt Masked Register" group.long 0xEC0++0x03 line.long 0x00 "SCB1_INTR_SPI_EC,Externally Clocked SPI Interrupt Request Register" group.long 0xEC8++0x03 line.long 0x00 "SCB1_INTR_SPI_EC_MASK,Externally Clocked SPI Interrupt Mask Register" rgroup.long 0xE8C++0x03 line.long 0x00 "SCB1_INTR_SPI_EC_MASKED,Externally Clocked SPI Interrupt Masked Register" else group.long 0xE80++0x03 line.long 0x00 "SCB1_INTR_I2C_EC,Externally Clocked I2C Interrupt Request Register" textline " " eventfld.long 0x00 0. " WAKE_UP ,Wake up request" "No interrupt,Interrupt" group.long 0xE88++0x03 line.long 0x00 "SCB1_INTR_I2C_EC_MASK,Externally Clocked I2C Interrupt Mask Register" textline " " bitfld.long 0x00 0. " WAKE_UP ,Wake up request interrupt mask" "Not masked,Masked" rgroup.long 0xE8C++0x03 line.long 0x00 "SCB1_INTR_I2C_EC_MASKED,Externally Clocked I2C Interrupt Masked Register" textline " " bitfld.long 0x00 0. " WAKE_UP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" group.long 0xEC0++0x03 line.long 0x00 "SCB1_INTR_SPI_EC,Externally Clocked SPI Interrupt Request Register" textline " " eventfld.long 0x00 0. " WAKE_UP ,Wake up request" "No interrupt,Interrupt" group.long 0xEC8++0x03 line.long 0x00 "SCB1_INTR_SPI_EC_MASK,Externally Clocked SPI Interrupt Mask Register" textline " " bitfld.long 0x00 0. " WAKE_UP ,Wake up request interrupt mask" "Not masked,Masked" rgroup.long 0xE8C++0x03 line.long 0x00 "SCB1_INTR_SPI_EC_MASKED,Externally Clocked SPI Interrupt Masked Register" textline " " bitfld.long 0x00 0. " WAKE_UP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" endif group.long 0xF00++0x03 line.long 0x00 "SCB1_INTR_M_set/clr,Master Interrupt Register" setclrfld.long 0x00 9. 0x04 9. 0x00 9. " SPI_DONE ,SPI master transfer done event interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 8. 0x04 8. 0x00 8. " I2C_BUS_ERROR ,I2C master bus error interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 4. 0x04 4. 0x00 4. " I2C_STOP ,I2C master STOP interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 2. 0x04 2. 0x00 2. " I2C_ACK ,I2C master acknowledgement interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 1. 0x04 1. 0x00 1. " I2C_NACK ,I2C master negative acknowledgement interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 0. 0x04 0. 0x00 0. " I2C_ARB_LOST ,I2C master lost arbitration interrupt" "No interrupt,Interrupt" group.long 0xF08++0x03 line.long 0x00 "SCB1_INTR_M_MASK,Master Interrupt Mask Register" bitfld.long 0x00 9. " SPI_DONE ,SPI master transfer done event interrupt" "Not masked,Masked" bitfld.long 0x00 8. " I2C_BUS_ERROR ,I2C master bus error interrupt" "Not masked,Masked" bitfld.long 0x00 4. " I2C_STOP ,I2C master STOP interrupt" "Not masked,Masked" textline " " bitfld.long 0x00 2. " I2C_ACK ,I2C master acknowledgement interrupt" "Not masked,Masked" bitfld.long 0x00 1. " I2C_NACK ,I2C master negative acknowledgement interrupt" "Not masked,Masked" bitfld.long 0x00 0. " I2C_ARB_LOST ,I2C master lost arbitration interrupt" "Not masked,Masked" rgroup.long 0xF0C++0x03 line.long 0x00 "SCB1_INTR_M_MASKED,Master Interrupt Masked Request Register" bitfld.long 0x00 9. " SPI_DONE ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 8. " I2C_BUS_ERROR ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 4. " I2C_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" textline " " bitfld.long 0x00 2. " I2C_ACK ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 1. " I2C_NACK ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 0. " I2C_ARB_LOST ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" group.long 0xF40++0x03 line.long 0x00 "SCB1_INTR_S,Slave Interrupt Request Register" setclrfld.long 0x00 11. 0x04 11. 0x00 11. " SPI_BUS_ERROR ,SPI slave deselected at an unexpected time in the SPI transfer interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 10. 0x04 10. 0x00 10. " SPI_EZ_STOP ,SPI slave deselected after any EZ SPI transfer occurred interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 9. 0x04 9. 0x00 9. " SPI_EZ_WRITE_STOP ,SPI slave deselected after a write EZ SPI transfer occurred interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 8. 0x04 8. 0x00 8. " I2C_BUS_ERROR ,I2C slave bus error interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 7. 0x04 7. 0x00 7. " I2C_GENERAL ,I2C slave general call address received interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 6. 0x04 6. 0x00 6. " I2C_ADDR_MATCH ,I2C slave matching address received interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 5. 0x04 5. 0x00 5. " I2C_START ,I2C slave START received interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 4. 0x04 4. 0x00 4. " I2C_STOP ,I2C STOP event for I2C (read or write) transfer intended for this slave interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 3. 0x04 3. 0x00 3. " I2C_WRITE_STOP ,I2C STOP event for I2C write transfer intended for this slave interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 2. 0x04 2. 0x00 2. " I2C_ACK ,I2C slave acknowledgement received interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 1. 0x04 1. 0x00 1. " I2C_NACK ,I2C slave negative acknowledgement received interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 0. 0x04 0. 0x00 0. " I2C_ARB_LOST ,I2C slave lost arbitration interrupt" "No interrupt,Interrupt" group.long 0xF48++0x03 line.long 0x00 "SCB1_INTR_S_MASK,Slave Interrupt Mask Register" bitfld.long 0x00 11. " SPI_BUS_ERROR ,SPI slave deselected at an unexpected time in the SPI transfer interrupt mask" "Not masked,Masked" bitfld.long 0x00 10. " SPI_EZ_STOP ,SPI slave deselected after any EZ SPI transfer occurred interrupt mask" "Not masked,Masked" bitfld.long 0x00 9. " SPI_EZ_WRITE_STOP ,SPI slave deselected after a write EZ SPI transfer occurred interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 8. " I2C_BUS_ERROR ,I2C slave bus error interrupt mask" "Not masked,Masked" bitfld.long 0x00 7. " I2C_GENERAL ,I2C slave general call address received interrupt mask" "Not masked,Masked" bitfld.long 0x00 6. " I2C_ADDR_MATCH ,I2C slave matching address received interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 5. " I2C_START ,I2C slave START received interrupt mask" "Not masked,Masked" bitfld.long 0x00 4. " I2C_STOP ,I2C STOP event for I2C (read or write) transfer intended for this slave interrupt mask" "Not masked,Masked" bitfld.long 0x00 3. " I2C_WRITE_STOP ,SPI slave deselected at an unexpected time in the SPI transfer interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 2. " I2C_ACK ,SPI slave deselected at an unexpected time in the SPI transfer interrupt mask" "Not masked,Masked" bitfld.long 0x00 1. " I2C_NACK ,I2C slave negative acknowledgement received interrupt mask" "Not masked,Masked" bitfld.long 0x00 0. " I2C_ARB_LOST ,I2C slave lost arbitration interrupt mask" "Not masked,Masked" rgroup.long 0xF4C++0x03 line.long 0x00 "SCB1_INTR_S_MASKED,Slave Interrupt Masked Request Register" bitfld.long 0x00 11. " SPI_BUS_ERROR ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 10. " SPI_EZ_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 9. " SPI_EZ_WRITE_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" textline " " bitfld.long 0x00 8. " I2C_BUS_ERROR ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 7. " I2C_GENERAL ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 6. " I2C_ADDR_MATCH ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" textline " " bitfld.long 0x00 5. " I2C_START ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 4. " I2C_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 3. " I2C_WRITE_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" textline " " bitfld.long 0x00 2. " I2C_ACK ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 1. " I2C_NACK ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 0. " I2C_ARB_LOST ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" group.long 0xF80++0x03 line.long 0x00 "SCB1_INTR_TX_SET/CLR,Transmitter Interrupt Request Register" setclrfld.long 0x00 10. 0x04 10. 0x00 10. " UART_ARB_LOST ,UART lost arbitration interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 9. 0x04 9. 0x00 9. " UART_DONE ,UART transmitter done event interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 8. 0x04 8. 0x00 8. " UART_NACK ,UART transmitter received a negative acknowledgement in SmartCard mode interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 7. 0x04 7. 0x00 7. " BLOCKED ,AHB-Lite write transfer can not get access to the EZ memory interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 6. 0x04 6. 0x00 6. " UNDERFLOW ,Attempt to read from an empty TX FIFO interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 5. 0x04 5. 0x00 5. " OVERFLOW ,Attempt to write to a full TX FIFO interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 4. 0x04 4. 0x00 4. " EMPTY ,TX FIFO is empty interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 1. 0x04 1. 0x00 1. " NOT_FULL ,TX FIFO is not full interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 0. 0x04 0. 0x00 0. " TRIGGER ,Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL interrupt" "No interrupt,Interrupt" group.long 0xF88++0x03 line.long 0x00 "SCB1_INTR_TX_MASK,Transmitter Interrupt Mask Register" bitfld.long 0x00 10. " UART_ARB_LOST ,UART lost arbitration interrupt mask" "Not masked,Masked" bitfld.long 0x00 9. " UART_DONE ,UART transmitter done event interrupt mask" "Not masked,Masked" bitfld.long 0x00 8. " UART_NACK ,UART transmitter received a negative acknowledgement in SmartCard mode interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 7. " BLOCKED ,AHB-Lite write transfer can not get access to the EZ memory interrupt mask" "Not masked,Masked" bitfld.long 0x00 6. " UNDERFLOW ,Attempt to read from an empty TX FIFO interrupt mask" "Not masked,Masked" bitfld.long 0x00 5. " OVERFLOW ,Attempt to write to a full TX FIFO interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 4. " EMPTY ,TX FIFO is empty interrupt mask" "Not masked,Masked" bitfld.long 0x00 1. " NOT_FULL ,TX FIFO is not full interrupt mask" "Not masked,Masked" bitfld.long 0x00 0. " TRIGGER ,Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL interrupt mask" "Not masked,Masked" rgroup.long 0xF8C++0x03 line.long 0x00 "SCB1_INTR_TX_MASKED,Transmitter Interrupt Mask Register" bitfld.long 0x00 10. " UART_ARB_LOST ,Logical AND of corresponding request and mask bits" "Not masked,Masked" bitfld.long 0x00 9. " UART_DONE ,Logical AND of corresponding request and mask bits" "Not masked,Masked" bitfld.long 0x00 8. " UART_NACK ,Logical AND of corresponding request and mask bits" "Not masked,Masked" textline " " bitfld.long 0x00 7. " BLOCKED ,Logical AND of corresponding request and mask bits" "Not masked,Masked" bitfld.long 0x00 6. " UNDERFLOW ,Logical AND of corresponding request and mask bits" "Not masked,Masked" bitfld.long 0x00 5. " OVERFLOW ,Logical AND of corresponding request and mask bits" "Not masked,Masked" textline " " bitfld.long 0x00 4. " EMPTY ,Logical AND of corresponding request and mask bits" "Not masked,Masked" bitfld.long 0x00 1. " NOT_FULL ,Logical AND of corresponding request and mask bits" "Not masked,Masked" bitfld.long 0x00 0. " TRIGGER ,Logical AND of corresponding request and mask bits" "Not masked,Masked" group.long 0xFC0++0x03 line.long 0x00 "SCB1_INTR_RX,Receiver Interrupt Request Register" setclrfld.long 0x00 11. 0x04 11. 0x00 11. " BREAK_DETECT ,Break detection interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 10. 0x04 10. 0x00 10. " BAUD_DETECT ,LIN baudrate detection interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 9. 0x04 9. 0x00 9. " PARITY_ERROR ,Parity error in received data frame interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 8. 0x04 8. 0x00 8. " FRAME_ERROR ,Frame error in received data frame interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 7. 0x04 7. 0x00 7. " BLOCKED ,AHB-Lite read transfer access to the EZ memory interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 6. 0x04 6. 0x00 6. " UNDERFLOW ,Attempt to read from an empty RX FIFO interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 5. 0x04 5. 0x00 5. " OVERFLOW ,Attempt to write to a full RX FIFO interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 3. 0x04 3. 0x00 3. " FULL ,RX FIFO is full interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 2. 0x04 2. 0x00 2. " NOT_EMPTY ,RX FIFO is not empty interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 0. 0x04 0. 0x00 0. " TRIGGER ,More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in SCB_RX_FIFO_CTL interrupt" "No interrupt,Interrupt" group.long 0xFC8++0x03 line.long 0x00 "SCB1_INTR_RX_MASK,Receiver Interrupt Mask Register" bitfld.long 0x00 11. " BREAK_DETECT ,BREAK_DETECT interrupt mask" "Not masked,Masked" bitfld.long 0x00 10. " BAUD_DETECT ,BAUD_DETECT interrupt mask" "Not masked,Masked" bitfld.long 0x00 9. " PARITY_ERROR ,PARITY_ERROR interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 8. " FRAME_ERROR ,FRAME_ERROR interrupt mask" "Not masked,Masked" bitfld.long 0x00 7. " BLOCKED ,BLOCKED interrupt mask" "Not masked,Masked" bitfld.long 0x00 6. " UNDERFLOW ,UNDERFLOW interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 5. " OVERFLOW ,OVERFLOW interrupt mask" "Not masked,Masked" bitfld.long 0x00 3. " FULL ,FULL interrupt mask" "Not masked,Masked" bitfld.long 0x00 2. " NOT_EMPTY ,NOT_EMPTY interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 0. " TRIGGER ,TRIGGER interrupt mask" "Not masked,Masked" rgroup.long 0xFCC++0x03 line.long 0x00 "SCB1_INTR_RX_MASKED,Receiver Interrupt Masked Request Register" bitfld.long 0x00 11. " BREAK_DETECT ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 10. " BAUD_DETECT ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 9. " PARITY_ERROR ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" textline " " bitfld.long 0x00 8. " FRAME_ERROR ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 7. " BLOCKED ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 6. " UNDERFLOW ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" textline " " bitfld.long 0x00 5. " OVERFLOW ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 3. " FULL ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 2. " NOT_EMPTY ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " TRIGGER ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" width 0x0B tree.end tree "SCB2" base ad:0x40260000 if (((per.l(ad:0x40260000))&0x3000000)==0x0000000) width 12. if (((per.l(ad:0x40260000))&0x200)==0x200) if (((per.l(ad:0x40260000))&0x80000000)==0x80000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked" textline " " rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" else group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked" textline " " bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" endif else if (((per.l(ad:0x40260000))&0x80000000)==0x80000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." textline " " rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" else group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." textline " " bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" endif endif rgroup.long 0x04++0x03 line.long 0x00 "STATUS,Generic Status Register" bitfld.long 0x00 0. " EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy" if (((per.l(ad:0x40260000+0x60))&0xC0000000)==0xC0000000) if (((per.l(ad:0x40260000))&0x100)==0x100)&&((((per.l(ad:0x40260000))&0x200)==0x000)||(((per.l(ad:0x40260000+0x60))&0x800)==0x800)||(((per.l(ad:0x40260000))&0x400)==0x400)) if (((per.l(ad:0x40260000))&0x400)==0x000) group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 14. " S_NOT_READY_ADDR_NACK ,Slave not ready address NACK" "Ready,Not ready" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" else group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" endif elif (((per.l(ad:0x40260000))&0x100)==0x000)&&(((per.l(ad:0x40260000))&0x200)==0x000)&&(((per.l(ad:0x40260000))&0x400)==0x000) group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" else if (((per.l(ad:0x40260000))&0x400)==0x400) group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" else group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" endif endif elif (((per.l(ad:0x40260000+0x60))&0xC0000000)==0x80000000) if (((per.l(ad:0x40260000))&0x100)==0x100)&&((((per.l(ad:0x40260000))&0x200)==0x000)||(((per.l(ad:0x40260000+0x60))&0x800)==0x800)||(((per.l(ad:0x40260000))&0x400)==0x400)) if (((per.l(ad:0x40260000))&0x400)==0x000) group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 14. " S_NOT_READY_ADDR_NACK ,Slave not ready address NACK" "Ready,Not ready" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" bitfld.long 0x00 4.--7. " LOW_PHASE_OVS ,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " HIGH_PHASE_OVS ,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" bitfld.long 0x00 4.--7. " LOW_PHASE_OVS ,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " HIGH_PHASE_OVS ,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif (((per.l(ad:0x40260000))&0x100)==0x000)&&(((per.l(ad:0x40260000))&0x200)==0x000)&&(((per.l(ad:0x40260000))&0x400)==0x000) group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" bitfld.long 0x00 4.--7. " LOW_PHASE_OVS ,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " HIGH_PHASE_OVS ,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else if (((per.l(ad:0x40260000))&0x400)==0x400) group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" bitfld.long 0x00 4.--7. " LOW_PHASE_OVS ,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " HIGH_PHASE_OVS ,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" bitfld.long 0x00 4.--7. " LOW_PHASE_OVS ,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " HIGH_PHASE_OVS ,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif endif elif (((per.l(ad:0x40260000+0x60))&0xC0000000)==0x40000000) if (((per.l(ad:0x40260000))&0x100)==0x100)&&((((per.l(ad:0x40260000))&0x200)==0x000)||(((per.l(ad:0x40260000+0x60))&0x800)==0x800)||(((per.l(ad:0x40260000))&0x400)==0x400)) if (((per.l(ad:0x40260000))&0x400)==0x000) group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 14. " S_NOT_READY_ADDR_NACK ,Slave not ready address NACK" "Ready,Not ready" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" else group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" endif elif (((per.l(ad:0x40260000))&0x100)==0x000)&&(((per.l(ad:0x40260000))&0x200)==0x000)&&(((per.l(ad:0x40260000))&0x400)==0x000) group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" else if (((per.l(ad:0x40260000))&0x400)==0x400) group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" else group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" endif endif else if (((per.l(ad:0x40260000))&0x100)==0x100)&&((((per.l(ad:0x40260000))&0x200)==0x000)||(((per.l(ad:0x40260000+0x60))&0x800)==0x800)||(((per.l(ad:0x40260000))&0x400)==0x400)) if (((per.l(ad:0x40260000))&0x400)==0x000) group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 14. " S_NOT_READY_ADDR_NACK ,Slave not ready address NACK" "Ready,Not ready" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" else group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" endif elif (((per.l(ad:0x40260000))&0x100)==0x000)&&(((per.l(ad:0x40260000))&0x200)==0x000)&&(((per.l(ad:0x40260000))&0x400)==0x000) group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" else if (((per.l(ad:0x40260000))&0x400)==0x400) group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" else group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" endif endif endif if (((per.l(ad:0x40260000))&0x200)==0x000) rgroup.long 0x64++0x03 line.long 0x00 "I2C_STATUS,I2C Status Register" hexmask.long.byte 0x00 16.--23. 1. " BASE_EZ_ADDR ,I2C slave base EZ address" hexmask.long.byte 0x00 8.--15. 1. " CURR_EZ_ADDR ,I2C slave current EZ address" bitfld.long 0x00 5. " M_READ ,I2C master read transfer" "Write transfer,Read transfer" textline " " bitfld.long 0x00 4. " S_READ ,I2C slave read transfer" "Write transfer,Read transfer" bitfld.long 0x00 1. " I2C_EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy" bitfld.long 0x00 0. " BUS_BUSY ,I2C bus is busy" "Not busy,Busy" else rgroup.long 0x64++0x03 line.long 0x00 "I2C_STATUS,I2C Status Register" bitfld.long 0x00 5. " M_READ ,I2C master read transfer" "Write transfer,Read transfer" textline " " bitfld.long 0x00 4. " S_READ ,I2C slave read transfer" "Write transfer,Read transfer" bitfld.long 0x00 1. " I2C_EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy" bitfld.long 0x00 0. " BUS_BUSY ,I2C bus is busy" "Not busy,Busy" endif if (((per.l(ad:0x40260000+0x60))&0x80000000)==0x80000000) group.long 0x68++0x03 line.long 0x00 "I2C_M_CMD,I2C Master Command Register" bitfld.long 0x00 4. " M_STOP ,Master transmit STOP" "Disabled,ENABLED" bitfld.long 0x00 3. " M_NACK ,Master negative acknowledgement transmit" "Disabled,Enabled" bitfld.long 0x00 2. " M_ACK ,Master acknowledgement transmit" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " M_START_ON_IDLE ,Master START on idle" "Disabled,Enabled" bitfld.long 0x00 0. " M_START ,Master transmit START" "Disabled,Enabled" else hgroup.long 0x68++0x03 hide.long 0x00 "I2C_M_CMD,I2C Master Command Register" endif if (((per.l(ad:0x40260000+0x60))&0x40000000)==0x40000000) if (((per.l(ad:0x40260000))&0x400)==0x400) group.long 0x6C++0x03 line.long 0x00 "I2C_S_CMD,I2C Slave Command Register" bitfld.long 0x00 1. " S_NACK ,Slave negative acknowledgement transmit" "Disabled,Enabled" bitfld.long 0x00 0. " S_ACK ,Slave acknowledgement transmit" "Disabled,Enabled" else group.long 0x6C++0x03 line.long 0x00 "I2C_S_CMD,I2C Slave Command Register" bitfld.long 0x00 1. " S_NACK ,Slave negative acknowledgement transmit" "Disabled,Enabled" endif else hgroup.long 0x6C++0x03 hide.long 0x00 "I2C_S_CMD,I2C Slave Command Register" endif group.long 0x70++0x03 line.long 0x00 "I2C_CFG,I2C Configuration Register" bitfld.long 0x00 28.--29. " SDA_OUT_FILT_SEL ,Selection of cumulative 'i2c_sda_out' filter delay" "0 ns,50 ns,100 ns,150 ns" bitfld.long 0x00 20.--21. " SDA_OUT_FILT2_TRIM ,Trim bits for 'i2c_sda_out' 50 ns filter 2" "0,1,2,3" bitfld.long 0x00 18.--19. " SDA_OUT_FILT1_TRIM ,Trim bits for 'i2c_sda_out' 50 ns filter 1" "0,1,2,3" textline " " bitfld.long 0x00 16.--17. " SDA_OUT_FILT0_TRIM ,Trim bits for 'i2c_sda_out' 50 ns filter 0" "0,1,2,3" bitfld.long 0x00 12. " SCL_IN_FILT_SEL ,Selection of 'i2c_sda_in' filter delay" "0 ns,50 ns" bitfld.long 0x00 8.--9. " SCL_IN_FILT_TRIM ,Trim bits for 'i2c_sda_in' 50 ns filter" "0,1,2,3" textline " " bitfld.long 0x00 4. " SDA_IN_FILT_SEL ,Selection of 'i2c_sda_in' filter delay" "0 ns,50 ns" bitfld.long 0x00 0.--1. " SDA_IN_FILT_TRIM ,Trim bits for 'i2c_sda_in' 50 ns filter" "0,1,2,3" width 0x0B elif (((per.l(ad:0x40260000))&0x3000000)==0x1000000) width 22. if (((per.l(ad:0x40260000+0x20))&0x80000000)==0x80000000) if (((per.l(ad:0x40260000))&0x200)==0x200) if (((per.l(ad:0x40260000))&0x80000000)==0x80000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked" textline " " rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked" rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked" textline " " bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked" bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else if (((per.l(ad:0x40260000))&0x80000000)==0x80000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." textline " " rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked" rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." textline " " bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked" bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15" endif endif rgroup.long 0x04++0x03 line.long 0x00 "STATUS,Generic Status Register" bitfld.long 0x00 0. " EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy" if (((per.l(ad:0x40260000+0x20))&0x3000000)==0x0000000) if (((per.l(ad:0x40260000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40260000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40260000+0x20))&0xC000000)==0x0000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40260000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40260000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40260000+0x20))&0xC000000)==0x4000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40260000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40260000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40260000+0x20))&0xC000000)==0x8000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40260000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40260000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40260000+0x20))&0xC000000)==0xC000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40260000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40260000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40260000+0x20))&0xC000000)==0x0000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40260000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40260000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40260000+0x20))&0xC000000)==0x4000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40260000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40260000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40260000+0x20))&0xC000000)==0x8000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40260000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40260000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40260000+0x20))&0xC000000)==0xC000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40260000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40260000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40260000+0x20))&0xC000000)==0x0000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40260000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40260000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40260000+0x20))&0xC000000)==0x4000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40260000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40260000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40260000+0x20))&0xC000000)==0x8000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40260000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40260000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40260000+0x20))&0xC000000)==0xC000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40260000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40260000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40260000+0x20))&0xC000000)==0x0000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40260000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40260000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40260000+0x20))&0xC000000)==0x4000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40260000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40260000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40260000+0x20))&0xC000000)==0x8000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40260000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40260000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40260000+0x20))&0xC000000)==0xC000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" endif elif (((per.l(ad:0x40260000+0x20))&0x3000000)==0x2000000) if (((per.l(ad:0x40260000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40260000+0x20))&0xC000000)==0x0000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40260000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40260000+0x20))&0xC000000)==0x4000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40260000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40260000+0x20))&0xC000000)==0x8000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40260000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40260000+0x20))&0xC000000)==0xC000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40260000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40260000+0x20))&0xC000000)==0x0000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40260000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40260000+0x20))&0xC000000)==0x4000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40260000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40260000+0x20))&0xC000000)==0x8000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40260000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40260000+0x20))&0xC000000)==0xC000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" endif elif (((per.l(ad:0x40260000+0x20))&0x3000000)==0x1000000) if (((per.l(ad:0x40260000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40260000+0x20))&0xC000000)==0x0000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "High,Low" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides" bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40260000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40260000+0x20))&0xC000000)==0x4000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "High,Low" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides" bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40260000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40260000+0x20))&0xC000000)==0x8000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "High,Low" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides" bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40260000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40260000+0x20))&0xC000000)==0xC000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "High,Low" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides" bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40260000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40260000+0x20))&0xC000000)==0x0000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "High,Low" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides" bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40260000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40260000+0x20))&0xC000000)==0x4000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "High,Low" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides" bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40260000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40260000+0x20))&0xC000000)==0x8000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "High,Low" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides" bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40260000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40260000+0x20))&0xC000000)==0xC000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "High,Low" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides" bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" endif else if (((per.l(ad:0x40260000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40260000+0x20))&0xC000000)==0x0000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40260000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40260000+0x20))&0xC000000)==0x4000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40260000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40260000+0x20))&0xC000000)==0x8000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40260000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40260000+0x20))&0xC000000)==0xC000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40260000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40260000+0x20))&0xC000000)==0x0000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40260000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40260000+0x20))&0xC000000)==0x4000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40260000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40260000+0x20))&0xC000000)==0x8000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40260000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40260000+0x20))&0xC000000)==0xC000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" endif endif else if (((per.l(ad:0x40260000))&0x200)==0x200) if (((per.l(ad:0x40260000))&0x80000000)==0x80000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked" textline " " rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked" else group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked" textline " " bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked" endif else if (((per.l(ad:0x40260000))&0x80000000)==0x80000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." textline " " rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" else group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." textline " " bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" endif endif rgroup.long 0x04++0x03 line.long 0x00 "STATUS,Generic Status Register" bitfld.long 0x00 0. " EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy" if (((per.l(ad:0x40260000+0x20))&0x3000000)==0x0000000) if (((per.l(ad:0x40260000+0x20))&0x8)==0x0) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge" else group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge" endif elif (((per.l(ad:0x40260000+0x20))&0x3000000)==0x2000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." elif (((per.l(ad:0x40260000+0x20))&0x3000000)==0x1000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." else group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." endif endif if (((per.l(ad:0x40260000))&0x200)==0x000) rgroup.long 0x24++0x03 line.long 0x00 "SPI_STATUS,SPI Status Register" hexmask.long.byte 0x00 16.--23. 0x01 " BASE_EZ_ADDR ,SPI base EZ address" hexmask.long.byte 0x00 8.--15. 0x01 " CURR_EZ_ADDR ,SPI current EZ address" bitfld.long 0x00 1. " SPI_EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy" textline " " bitfld.long 0x00 0. " BUS_BUSY ,SPI bus is busy" "Not busy,Busy" else rgroup.long 0x24++0x03 line.long 0x00 "SPI_STATUS,SPI Status Register" bitfld.long 0x00 1. " SPI_EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy" textline " " bitfld.long 0x00 0. " BUS_BUSY ,SPI bus is busy" "Not busy,Busy" endif width 0x0B elif (((per.l(ad:0x40260000))&0x3000000)==0x2000000) width 21. if (((per.l(ad:0x40260000))&0x200)==0x200) if (((per.l(ad:0x40260000))&0x80000000)==0x80000000) if (((per.l(ad:0x40260000+0x40))&0x3000000)==0x0000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked" textline " " rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15" elif (((per.l(ad:0x40260000+0x40))&0x3000000)==0x1000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked" textline " " rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15" elif (((per.l(ad:0x40260000+0x40))&0x3000000)==0x2000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked" textline " " rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" "16,32,48,96,192,768,1536,?..." endif else if (((per.l(ad:0x40260000+0x40))&0x3000000)==0x0000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked" textline " " bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15" elif (((per.l(ad:0x40260000+0x40))&0x3000000)==0x1000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked" textline " " bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15" elif (((per.l(ad:0x40260000+0x40))&0x3000000)==0x2000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked" textline " " bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" "16,32,48,96,192,768,1536,?..." endif endif else if (((per.l(ad:0x40260000))&0x80000000)==0x80000000) if (((per.l(ad:0x40260000+0x40))&0x3000000)==0x0000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." textline " " rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15" elif (((per.l(ad:0x40260000+0x40))&0x3000000)==0x1000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." textline " " rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15" elif (((per.l(ad:0x40260000+0x40))&0x3000000)==0x2000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." textline " " rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" "16,?..." endif else if (((per.l(ad:0x40260000+0x40))&0x3000000)==0x0000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." textline " " bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15" elif (((per.l(ad:0x40260000+0x40))&0x3000000)==0x1000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." textline " " bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15" elif (((per.l(ad:0x40260000+0x40))&0x3000000)==0x2000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." textline " " bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" "16,?..." endif endif endif rgroup.long 0x04++0x03 line.long 0x00 "STATUS,Generic Status Register" bitfld.long 0x00 0. " EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy" group.long 0x40++0x03 line.long 0x00 "UART_CTRL,UART Control Register" bitfld.long 0x00 24.--25. " MODE ,Submode of UART operation" "UART_STD,UART_SMARTCARD,UART_IRDA,?..." bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" if (((per.l(ad:0x40260000+0x40))&0x3000000)==0x0000000) group.long 0x44++0x07 line.long 0x00 "UART_TX_CTRL,UART Transmitter Control Register" bitfld.long 0x00 5. " PARITY_ENABLED ,Parity generation enabled" "Disabled,Enabled" rbitfld.long 0x00 4. " PARITY ,Parity bit" "Even,Odd" textline " " bitfld.long 0x00 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7" line.long 0x04 "UART_RX_CTRL,UART Receiver Control Register" bitfld.long 0x04 16.--19. " BREAK_WIDTH ,Break width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 13. " SKIP_START ,Skips start bit detection for the first received data frame" "Disabled,Enabled" bitfld.long 0x04 12. " LIN_MODE ,Break detection and baud rate detection on the incoming data" "Disabled,Enabled" textline " " bitfld.long 0x04 10. " MP_MODE ,Multi-processor mode" "Disabled,Enabled" bitfld.long 0x04 9. " DROP_ON_FRAME_ERROR ,Behaviour when an error is detected in a start or stop period" "Data send to RX FIFO,Data dropped" bitfld.long 0x04 8. " DROP_ON_PARITY_ERROR ,Behaviour when a parity check fails" "Data send to RX FIFO,Data dropped" textline " " bitfld.long 0x04 5. " PARITY_ENABLED ,Parity checking enabled" "Disabled,Enabled" bitfld.long 0x04 4. " PARITY ,Parity bit" "Even,Odd" bitfld.long 0x04 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7" elif (((per.l(ad:0x40260000+0x40))&0x3000000)==0x1000000) group.long 0x44++0x07 line.long 0x00 "UART_TX_CTRL,UART Transmitter Control Register" bitfld.long 0x00 8. " RETRY_ON_NACK ,Retransmitted when negative acknowledgement is received" "Not retransmitted,Retransmitted" rbitfld.long 0x00 4. " PARITY ,Parity bit" "Even,Odd" textline " " bitfld.long 0x00 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7" line.long 0x04 "UART_RX_CTRL,UART Receiver Control Register" bitfld.long 0x04 16.--19. " BREAK_WIDTH ,Break width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x04 10. " MP_MODE ,Multi-processor mode" "Disabled,Enabled" bitfld.long 0x04 9. " DROP_ON_FRAME_ERROR ,Behaviour when an error is detected in a start or stop period" "Data send to RX FIFO,Data dropped" bitfld.long 0x04 8. " DROP_ON_PARITY_ERROR ,Behaviour when a parity check fails" "Data send to RX FIFO,Data dropped" textline " " bitfld.long 0x04 4. " PARITY ,Parity bit" "Even,Odd" bitfld.long 0x04 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7" elif (((per.l(ad:0x40260000+0x40))&0x3000000)==0x2000000) group.long 0x44++0x07 line.long 0x00 "UART_TX_CTRL,UART Transmitter Control Register" bitfld.long 0x00 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7" line.long 0x04 "UART_RX_CTRL,UART Receiver Control Register" bitfld.long 0x04 16.--19. " BREAK_WIDTH ,Break width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x04 10. " MP_MODE ,Multi-processor mode" "Disabled,Enabled" bitfld.long 0x04 9. " DROP_ON_FRAME_ERROR ,Behaviour when an error is detected in a start or stop period" "Data send to RX FIFO,Data dropped" textline " " bitfld.long 0x04 6. " POLARITY ,Inverts incoming RX line signal" "Low,High" bitfld.long 0x04 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7" endif rgroup.long 0x4C++0x03 line.long 0x00 "UART_RX_STATUS,UART Receiver Status Register" hexmask.long.word 0x00 0.--11. 1. " BR_COUNTER ,Amount of peripheral clock periods that constitute the transmission of a 0x55 data frame" group.long 0x50++0x03 line.long 0x00 "UART_FLOW_CTRL,UART Flow Control Register" bitfld.long 0x00 25. " CTS_ENABLED ,Enable use of CTS input signal" "Disabled,Enabled" bitfld.long 0x00 24. " CTS_POLARITY ,Polarity of the CTS input signal" "Low,High" bitfld.long 0x00 16. " RTS_POLARITY ,Polarity of the RTS output signal" "Low,High" textline " " bitfld.long 0x00 0.--3. " TRIGGER_LEVEL ,Trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B else width 18. if (((per.l(ad:0x40260000))&0x80000000)==0x80000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." else group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." endif endif textline " " width 28. if (((per.l(ad:0x40260000))&0x3000000)==0x2000000) group.long 0x200++0x03 line.long 0x00 "SCB2_TX_CTRL,Transmitter Control Register" bitfld.long 0x00 8. " MSB_FIRST ,Most significant bit first" "LSB,MSB" bitfld.long 0x00 0.--3. " DATA_WIDTH ,Dataframe width" ",,,3,4,5,6,7,8,?..." elif (((per.l(ad:0x40260000))&0x3000000)==0x1000000) group.long 0x200++0x03 line.long 0x00 "SCB2_TX_CTRL,Transmitter Control Register" bitfld.long 0x00 8. " MSB_FIRST ,Most significant bit first" "LSB,MSB" bitfld.long 0x00 0.--3. " DATA_WIDTH ,Dataframe width" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x200++0x03 line.long 0x00 "SCB2_TX_CTRL,Transmitter Control Register" bitfld.long 0x00 8. " MSB_FIRST ,Most significant bit first" "LSB,MSB" bitfld.long 0x00 0.--3. " DATA_WIDTH ,Dataframe width" ",,,,,,,7,?..." endif group.long 0x204++0x03 line.long 0x00 "SCB2_TX_FIFO_CTRL,Transmitter FIFO Control Register" bitfld.long 0x00 17. " FREEZE ,FIFO entries remove freeze" "Disabled,Enabled" bitfld.long 0x00 16. " CLEAR ,FIFO and transmitter shift register clear" "Not cleared,Cleared" bitfld.long 0x00 0.--3. " TRIGGER_LEVEL ,Trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x208++0x03 line.long 0x00 "SCB2_TX_FIFO_STATUS,Transmitter FIFO Status Register" bitfld.long 0x00 24.--27. " WR_PTR ,FIFO write pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " RD_PTR ,FIFO read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " SR_VALID ,TX shift registers valid data frame hold" "No,Yes" textline " " bitfld.long 0x00 0.--4. " USED ,Amount of enties in the transmitter FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x40260000))&0x800)==0x800) wgroup.long 0x240++0x03 line.long 0x00 "SCB2_TX_FIFO_WR,Transmitter FIFO Write Register" hexmask.long.byte 0x00 0.--7. 1. " DATA ,Data frame written into the transmitter FIFO" else wgroup.long 0x240++0x03 line.long 0x00 "SCB2_TX_FIFO_WR,Transmitter FIFO Write Register" hexmask.long.word 0x00 0.--15. 1. " DATA ,Data frame written into the transmitter FIFO" endif if (((per.l(ad:0x40260000))&0x3000400)==0x1000400) group.long 0x300++0x03 line.long 0x00 "SCB2_RX_CTRL,Transmitter Control Register" bitfld.long 0x00 9. " MEDIAN ,Median filter" "Off,On" bitfld.long 0x00 8. " MSB_FIRST ,Most significant bit first" "LSB,MSB" bitfld.long 0x00 0.--3. " DATA_WIDTH ,Dataframe width" ",,,,,,,7,?..." elif (((per.l(ad:0x40260000))&0x3000400)==0x1000400) group.long 0x300++0x03 line.long 0x00 "SCB2_RX_CTRL,Transmitter Control Register" bitfld.long 0x00 9. " MEDIAN ,Median filter" "Off,On" bitfld.long 0x00 8. " MSB_FIRST ,Most significant bit first" "LSB,MSB" bitfld.long 0x00 0.--3. " DATA_WIDTH ,Dataframe width" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((per.l(ad:0x40260000))&0x3000000)==0x2000000) group.long 0x300++0x03 line.long 0x00 "SCB2_RX_CTRL,Transmitter Control Register" bitfld.long 0x00 9. " MEDIAN ,Median filter" "Off,On" bitfld.long 0x00 8. " MSB_FIRST ,Most significant bit first" "LSB,MSB" bitfld.long 0x00 0.--3. " DATA_WIDTH ,Dataframe width" ",,,3,4,5,6,7,8,?..." else group.long 0x300++0x03 line.long 0x00 "SCB2_RX_CTRL,Transmitter Control Register" bitfld.long 0x00 9. " MEDIAN ,Median filter" "Off,On" bitfld.long 0x00 8. " MSB_FIRST ,Most significant bit first" "LSB,MSB" bitfld.long 0x00 0.--3. " DATA_WIDTH ,Dataframe width" ",,,,,,,7,?..." endif group.long 0x304++0x03 line.long 0x00 "SCB2_RX_FIFO_CTRL,Receiver FIFO Control Register" bitfld.long 0x00 17. " FREEZE ,Receiver FIFO have no effect" "Disabled,Enabled" bitfld.long 0x00 16. " CLEAR ,FIFO and receiver shift register clear" "Not cleared,Cleared" bitfld.long 0x00 0.--3. " TRIGGER_LEVEL ,Trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x308++0x03 line.long 0x00 "SCB2_RX_FIFO_STATUS,Receiver FIFO Status Register" bitfld.long 0x00 24.--27. " WR_PTR ,FIFO write pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " RD_PTR ,FIFO read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " SR_VALID ,RX shift registers valid data frame hold" "No,Yes" textline " " bitfld.long 0x00 0.--4. " USED ,Amount of enties in the receiver FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x310++0x03 line.long 0x00 "SCB2_RX_MATCH,Slave Address and Mask Register" hexmask.long.byte 0x00 16.--23. 0x01 " MASK ,Slave device address mask" hexmask.long.byte 0x00 0.--7. 0x01 " ADDR ,Slave device address" if (((per.l(ad:0x40260000))&0x800)==0x800) rgroup.long 0x340++0x07 line.long 0x00 "SCB2_RX_FIFO_RD,Receiver FIFO Read Register" hexmask.long.word 0x00 0.--15. 0x01 " DATA ,Data read from the receiver FIFO" line.long 0x04 "SCB2_RX_FIFO_RD_SILENT,Receiver FIFO Read Register" hexmask.long.word 0x04 0.--15. 0x01 " DATA ,Data read from the receiver FIFO" else rgroup.long 0x340++0x07 line.long 0x00 "SCB2_RX_FIFO_RD,Receiver FIFO Read Register" hexmask.long.byte 0x00 0.--7. 0x01 " DATA ,Data read from the receiver FIFO" line.long 0x04 "SCB2_RX_FIFO_RD_SILENT,Receiver FIFO Read Register" hexmask.long.byte 0x04 0.--7. 0x01 " DATA ,Data read from the receiver FIFO" endif group.long 0x400++0x03 line.long 0x00 "SCB2_EZ_DATA0,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x404++0x03 line.long 0x00 "SCB2_EZ_DATA1,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x408++0x03 line.long 0x00 "SCB2_EZ_DATA2,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x40C++0x03 line.long 0x00 "SCB2_EZ_DATA3,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x410++0x03 line.long 0x00 "SCB2_EZ_DATA4,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x414++0x03 line.long 0x00 "SCB2_EZ_DATA5,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x418++0x03 line.long 0x00 "SCB2_EZ_DATA6,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x41C++0x03 line.long 0x00 "SCB2_EZ_DATA7,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x420++0x03 line.long 0x00 "SCB2_EZ_DATA8,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x424++0x03 line.long 0x00 "SCB2_EZ_DATA9,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x428++0x03 line.long 0x00 "SCB2_EZ_DATA10,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x42C++0x03 line.long 0x00 "SCB2_EZ_DATA11,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x430++0x03 line.long 0x00 "SCB2_EZ_DATA12,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x434++0x03 line.long 0x00 "SCB2_EZ_DATA13,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x438++0x03 line.long 0x00 "SCB2_EZ_DATA14,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x43C++0x03 line.long 0x00 "SCB2_EZ_DATA15,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x440++0x03 line.long 0x00 "SCB2_EZ_DATA16,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x444++0x03 line.long 0x00 "SCB2_EZ_DATA17,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x448++0x03 line.long 0x00 "SCB2_EZ_DATA18,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x44C++0x03 line.long 0x00 "SCB2_EZ_DATA19,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x450++0x03 line.long 0x00 "SCB2_EZ_DATA20,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x454++0x03 line.long 0x00 "SCB2_EZ_DATA21,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x458++0x03 line.long 0x00 "SCB2_EZ_DATA22,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x45C++0x03 line.long 0x00 "SCB2_EZ_DATA23,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x460++0x03 line.long 0x00 "SCB2_EZ_DATA24,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x464++0x03 line.long 0x00 "SCB2_EZ_DATA25,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x468++0x03 line.long 0x00 "SCB2_EZ_DATA26,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x46C++0x03 line.long 0x00 "SCB2_EZ_DATA27,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x470++0x03 line.long 0x00 "SCB2_EZ_DATA28,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x474++0x03 line.long 0x00 "SCB2_EZ_DATA29,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x478++0x03 line.long 0x00 "SCB2_EZ_DATA30,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x47C++0x03 line.long 0x00 "SCB2_EZ_DATA31,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" rgroup.long 0xE00++0x03 line.long 0x00 "SCB2_INTR_CAUSE,Active Clocked Interrupt Signal Register" bitfld.long 0x00 5. " SPI_EC ,Externally clocked SPI interrupt active" "Not active,Active" bitfld.long 0x00 4. " I2C_EC ,Externally clock I2C interrupt active" "Not active,Active" bitfld.long 0x00 3. " RX ,Receiver interrupt active" "Not active,Active" textline " " bitfld.long 0x00 2. " TX ,Transmitter interrupt active" "Not active,Active" bitfld.long 0x00 1. " S ,Slave interrupt active" "Not active,Active" bitfld.long 0x00 0. " M ,Master interrupt active" "Not active,Active" if (((per.l(ad:0x40260000))&0x700)==0x700) group.long 0xE80++0x03 line.long 0x00 "SCB2_INTR_I2C_EC,Externally Clocked I2C Interrupt Request Register" eventfld.long 0x00 3. " EZ_READ_STOP ,STOP detection after a read transfer occurred" "No interrupt,Interrupt" eventfld.long 0x00 2. " EZ_WRITE_STOP ,STOP detection after a write transfer occurred" "No interrupt,Interrupt" eventfld.long 0x00 1. " EZ_STOP ,STOP detection" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " WAKE_UP ,Wake up request" "No interrupt,Interrupt" group.long 0xE88++0x03 line.long 0x00 "SCB2_INTR_I2C_EC_MASK,Externally Clocked I2C Interrupt Mask Register" bitfld.long 0x00 3. " EZ_READ_STOP ,STOP detection after a read transfer occurred interrupt mask" "Not masked,Masked" bitfld.long 0x00 2. " EZ_WRITE_STOP ,STOP detection after a write transfer occurred interrupt mask" "Not masked,Masked" bitfld.long 0x00 1. " EZ_STOP ,STOP detection interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 0. " WAKE_UP ,Wake up request interrupt mask" "Not masked,Masked" rgroup.long 0xE8C++0x03 line.long 0x00 "SCB2_INTR_I2C_EC_MASKED,Externally Clocked I2C Interrupt Masked Register" bitfld.long 0x00 3. " EZ_READ_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 2. " EZ_WRITE_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 1. " EZ_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " WAKE_UP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" group.long 0xEC0++0x03 line.long 0x00 "SCB2_INTR_SPI_EC,Externally Clocked SPI Interrupt Request Register" eventfld.long 0x00 3. " EZ_READ_STOP ,STOP detection after a read transfer occurred" "No interrupt,Interrupt" eventfld.long 0x00 2. " EZ_WRITE_STOP ,STOP detection after a write transfer occurred" "No interrupt,Interrupt" eventfld.long 0x00 1. " EZ_STOP ,STOP detection" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " WAKE_UP ,Wake up request" "No interrupt,Interrupt" group.long 0xEC8++0x03 line.long 0x00 "SCB2_INTR_SPI_EC_MASK,Externally Clocked SPI Interrupt Mask Register" bitfld.long 0x00 3. " EZ_READ_STOP ,STOP detection after a read transfer occurred interrupt mask" "Not masked,Masked" bitfld.long 0x00 2. " EZ_WRITE_STOP ,STOP detection after a write transfer occurred interrupt mask" "Not masked,Masked" bitfld.long 0x00 1. " EZ_STOP ,STOP detection interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 0. " WAKE_UP ,Wake up request interrupt mask" "Not masked,Masked" rgroup.long 0xE8C++0x03 line.long 0x00 "SCB2_INTR_SPI_EC_MASKED,Externally Clocked SPI Interrupt Masked Register" bitfld.long 0x00 3. " EZ_READ_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 2. " EZ_WRITE_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 1. " EZ_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " WAKE_UP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" elif (((per.l(ad:0x40260000))&0x700)==0x600) group.long 0xE80++0x03 line.long 0x00 "SCB2_INTR_I2C_EC,Externally Clocked I2C Interrupt Request Register" eventfld.long 0x00 3. " EZ_READ_STOP ,STOP detection after a read transfer occurred" "No interrupt,Interrupt" eventfld.long 0x00 2. " EZ_WRITE_STOP ,STOP detection after a write transfer occurred" "No interrupt,Interrupt" eventfld.long 0x00 1. " EZ_STOP ,STOP detection" "No interrupt,Interrupt" group.long 0xE88++0x03 line.long 0x00 "SCB2_INTR_I2C_EC_MASK,Externally Clocked I2C Interrupt Mask Register" bitfld.long 0x00 3. " EZ_READ_STOP ,STOP detection after a read transfer occurred interrupt mask" "Not masked,Masked" bitfld.long 0x00 2. " EZ_WRITE_STOP ,STOP detection after a write transfer occurred interrupt mask" "Not masked,Masked" bitfld.long 0x00 1. " EZ_STOP ,STOP detection interrupt mask" "Not masked,Masked" rgroup.long 0xE8C++0x03 line.long 0x00 "SCB2_INTR_I2C_EC_MASKED,Externally Clocked I2C Interrupt Masked Register" bitfld.long 0x00 3. " EZ_READ_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 2. " EZ_WRITE_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 1. " EZ_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" group.long 0xEC0++0x03 line.long 0x00 "SCB2_INTR_SPI_EC,Externally Clocked SPI Interrupt Request Register" eventfld.long 0x00 3. " EZ_READ_STOP ,STOP detection after a read transfer occurred" "No interrupt,Interrupt" eventfld.long 0x00 2. " EZ_WRITE_STOP ,STOP detection after a write transfer occurred" "No interrupt,Interrupt" eventfld.long 0x00 1. " EZ_STOP ,STOP detection" "No interrupt,Interrupt" group.long 0xEC8++0x03 line.long 0x00 "SCB2_INTR_SPI_EC_MASK,Externally Clocked SPI Interrupt Mask Register" bitfld.long 0x00 3. " EZ_READ_STOP ,STOP detection after a read transfer occurred interrupt mask" "Not masked,Masked" bitfld.long 0x00 2. " EZ_WRITE_STOP ,STOP detection after a write transfer occurred interrupt mask" "Not masked,Masked" bitfld.long 0x00 1. " EZ_STOP ,STOP detection interrupt mask" "Not masked,Masked" rgroup.long 0xE8C++0x03 line.long 0x00 "SCB2_INTR_SPI_EC_MASKED,Externally Clocked SPI Interrupt Masked Register" bitfld.long 0x00 3. " EZ_READ_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 2. " EZ_WRITE_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 1. " EZ_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" elif (((per.l(ad:0x40260000))&0x700)==0x000) group.long 0xE80++0x03 line.long 0x00 "SCB2_INTR_I2C_EC,Externally Clocked I2C Interrupt Request Register" group.long 0xE88++0x03 line.long 0x00 "SCB2_INTR_I2C_EC_MASK,Externally Clocked I2C Interrupt Mask Register" rgroup.long 0xE8C++0x03 line.long 0x00 "SCB2_INTR_I2C_EC_MASKED,Externally Clocked I2C Interrupt Masked Register" group.long 0xEC0++0x03 line.long 0x00 "SCB2_INTR_SPI_EC,Externally Clocked SPI Interrupt Request Register" group.long 0xEC8++0x03 line.long 0x00 "SCB2_INTR_SPI_EC_MASK,Externally Clocked SPI Interrupt Mask Register" rgroup.long 0xE8C++0x03 line.long 0x00 "SCB2_INTR_SPI_EC_MASKED,Externally Clocked SPI Interrupt Masked Register" else group.long 0xE80++0x03 line.long 0x00 "SCB2_INTR_I2C_EC,Externally Clocked I2C Interrupt Request Register" textline " " eventfld.long 0x00 0. " WAKE_UP ,Wake up request" "No interrupt,Interrupt" group.long 0xE88++0x03 line.long 0x00 "SCB2_INTR_I2C_EC_MASK,Externally Clocked I2C Interrupt Mask Register" textline " " bitfld.long 0x00 0. " WAKE_UP ,Wake up request interrupt mask" "Not masked,Masked" rgroup.long 0xE8C++0x03 line.long 0x00 "SCB2_INTR_I2C_EC_MASKED,Externally Clocked I2C Interrupt Masked Register" textline " " bitfld.long 0x00 0. " WAKE_UP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" group.long 0xEC0++0x03 line.long 0x00 "SCB2_INTR_SPI_EC,Externally Clocked SPI Interrupt Request Register" textline " " eventfld.long 0x00 0. " WAKE_UP ,Wake up request" "No interrupt,Interrupt" group.long 0xEC8++0x03 line.long 0x00 "SCB2_INTR_SPI_EC_MASK,Externally Clocked SPI Interrupt Mask Register" textline " " bitfld.long 0x00 0. " WAKE_UP ,Wake up request interrupt mask" "Not masked,Masked" rgroup.long 0xE8C++0x03 line.long 0x00 "SCB2_INTR_SPI_EC_MASKED,Externally Clocked SPI Interrupt Masked Register" textline " " bitfld.long 0x00 0. " WAKE_UP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" endif group.long 0xF00++0x03 line.long 0x00 "SCB2_INTR_M_set/clr,Master Interrupt Register" setclrfld.long 0x00 9. 0x04 9. 0x00 9. " SPI_DONE ,SPI master transfer done event interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 8. 0x04 8. 0x00 8. " I2C_BUS_ERROR ,I2C master bus error interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 4. 0x04 4. 0x00 4. " I2C_STOP ,I2C master STOP interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 2. 0x04 2. 0x00 2. " I2C_ACK ,I2C master acknowledgement interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 1. 0x04 1. 0x00 1. " I2C_NACK ,I2C master negative acknowledgement interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 0. 0x04 0. 0x00 0. " I2C_ARB_LOST ,I2C master lost arbitration interrupt" "No interrupt,Interrupt" group.long 0xF08++0x03 line.long 0x00 "SCB2_INTR_M_MASK,Master Interrupt Mask Register" bitfld.long 0x00 9. " SPI_DONE ,SPI master transfer done event interrupt" "Not masked,Masked" bitfld.long 0x00 8. " I2C_BUS_ERROR ,I2C master bus error interrupt" "Not masked,Masked" bitfld.long 0x00 4. " I2C_STOP ,I2C master STOP interrupt" "Not masked,Masked" textline " " bitfld.long 0x00 2. " I2C_ACK ,I2C master acknowledgement interrupt" "Not masked,Masked" bitfld.long 0x00 1. " I2C_NACK ,I2C master negative acknowledgement interrupt" "Not masked,Masked" bitfld.long 0x00 0. " I2C_ARB_LOST ,I2C master lost arbitration interrupt" "Not masked,Masked" rgroup.long 0xF0C++0x03 line.long 0x00 "SCB2_INTR_M_MASKED,Master Interrupt Masked Request Register" bitfld.long 0x00 9. " SPI_DONE ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 8. " I2C_BUS_ERROR ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 4. " I2C_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" textline " " bitfld.long 0x00 2. " I2C_ACK ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 1. " I2C_NACK ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 0. " I2C_ARB_LOST ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" group.long 0xF40++0x03 line.long 0x00 "SCB2_INTR_S,Slave Interrupt Request Register" setclrfld.long 0x00 11. 0x04 11. 0x00 11. " SPI_BUS_ERROR ,SPI slave deselected at an unexpected time in the SPI transfer interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 10. 0x04 10. 0x00 10. " SPI_EZ_STOP ,SPI slave deselected after any EZ SPI transfer occurred interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 9. 0x04 9. 0x00 9. " SPI_EZ_WRITE_STOP ,SPI slave deselected after a write EZ SPI transfer occurred interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 8. 0x04 8. 0x00 8. " I2C_BUS_ERROR ,I2C slave bus error interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 7. 0x04 7. 0x00 7. " I2C_GENERAL ,I2C slave general call address received interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 6. 0x04 6. 0x00 6. " I2C_ADDR_MATCH ,I2C slave matching address received interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 5. 0x04 5. 0x00 5. " I2C_START ,I2C slave START received interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 4. 0x04 4. 0x00 4. " I2C_STOP ,I2C STOP event for I2C (read or write) transfer intended for this slave interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 3. 0x04 3. 0x00 3. " I2C_WRITE_STOP ,I2C STOP event for I2C write transfer intended for this slave interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 2. 0x04 2. 0x00 2. " I2C_ACK ,I2C slave acknowledgement received interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 1. 0x04 1. 0x00 1. " I2C_NACK ,I2C slave negative acknowledgement received interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 0. 0x04 0. 0x00 0. " I2C_ARB_LOST ,I2C slave lost arbitration interrupt" "No interrupt,Interrupt" group.long 0xF48++0x03 line.long 0x00 "SCB2_INTR_S_MASK,Slave Interrupt Mask Register" bitfld.long 0x00 11. " SPI_BUS_ERROR ,SPI slave deselected at an unexpected time in the SPI transfer interrupt mask" "Not masked,Masked" bitfld.long 0x00 10. " SPI_EZ_STOP ,SPI slave deselected after any EZ SPI transfer occurred interrupt mask" "Not masked,Masked" bitfld.long 0x00 9. " SPI_EZ_WRITE_STOP ,SPI slave deselected after a write EZ SPI transfer occurred interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 8. " I2C_BUS_ERROR ,I2C slave bus error interrupt mask" "Not masked,Masked" bitfld.long 0x00 7. " I2C_GENERAL ,I2C slave general call address received interrupt mask" "Not masked,Masked" bitfld.long 0x00 6. " I2C_ADDR_MATCH ,I2C slave matching address received interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 5. " I2C_START ,I2C slave START received interrupt mask" "Not masked,Masked" bitfld.long 0x00 4. " I2C_STOP ,I2C STOP event for I2C (read or write) transfer intended for this slave interrupt mask" "Not masked,Masked" bitfld.long 0x00 3. " I2C_WRITE_STOP ,SPI slave deselected at an unexpected time in the SPI transfer interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 2. " I2C_ACK ,SPI slave deselected at an unexpected time in the SPI transfer interrupt mask" "Not masked,Masked" bitfld.long 0x00 1. " I2C_NACK ,I2C slave negative acknowledgement received interrupt mask" "Not masked,Masked" bitfld.long 0x00 0. " I2C_ARB_LOST ,I2C slave lost arbitration interrupt mask" "Not masked,Masked" rgroup.long 0xF4C++0x03 line.long 0x00 "SCB2_INTR_S_MASKED,Slave Interrupt Masked Request Register" bitfld.long 0x00 11. " SPI_BUS_ERROR ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 10. " SPI_EZ_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 9. " SPI_EZ_WRITE_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" textline " " bitfld.long 0x00 8. " I2C_BUS_ERROR ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 7. " I2C_GENERAL ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 6. " I2C_ADDR_MATCH ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" textline " " bitfld.long 0x00 5. " I2C_START ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 4. " I2C_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 3. " I2C_WRITE_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" textline " " bitfld.long 0x00 2. " I2C_ACK ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 1. " I2C_NACK ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 0. " I2C_ARB_LOST ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" group.long 0xF80++0x03 line.long 0x00 "SCB2_INTR_TX_SET/CLR,Transmitter Interrupt Request Register" setclrfld.long 0x00 10. 0x04 10. 0x00 10. " UART_ARB_LOST ,UART lost arbitration interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 9. 0x04 9. 0x00 9. " UART_DONE ,UART transmitter done event interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 8. 0x04 8. 0x00 8. " UART_NACK ,UART transmitter received a negative acknowledgement in SmartCard mode interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 7. 0x04 7. 0x00 7. " BLOCKED ,AHB-Lite write transfer can not get access to the EZ memory interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 6. 0x04 6. 0x00 6. " UNDERFLOW ,Attempt to read from an empty TX FIFO interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 5. 0x04 5. 0x00 5. " OVERFLOW ,Attempt to write to a full TX FIFO interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 4. 0x04 4. 0x00 4. " EMPTY ,TX FIFO is empty interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 1. 0x04 1. 0x00 1. " NOT_FULL ,TX FIFO is not full interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 0. 0x04 0. 0x00 0. " TRIGGER ,Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL interrupt" "No interrupt,Interrupt" group.long 0xF88++0x03 line.long 0x00 "SCB2_INTR_TX_MASK,Transmitter Interrupt Mask Register" bitfld.long 0x00 10. " UART_ARB_LOST ,UART lost arbitration interrupt mask" "Not masked,Masked" bitfld.long 0x00 9. " UART_DONE ,UART transmitter done event interrupt mask" "Not masked,Masked" bitfld.long 0x00 8. " UART_NACK ,UART transmitter received a negative acknowledgement in SmartCard mode interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 7. " BLOCKED ,AHB-Lite write transfer can not get access to the EZ memory interrupt mask" "Not masked,Masked" bitfld.long 0x00 6. " UNDERFLOW ,Attempt to read from an empty TX FIFO interrupt mask" "Not masked,Masked" bitfld.long 0x00 5. " OVERFLOW ,Attempt to write to a full TX FIFO interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 4. " EMPTY ,TX FIFO is empty interrupt mask" "Not masked,Masked" bitfld.long 0x00 1. " NOT_FULL ,TX FIFO is not full interrupt mask" "Not masked,Masked" bitfld.long 0x00 0. " TRIGGER ,Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL interrupt mask" "Not masked,Masked" rgroup.long 0xF8C++0x03 line.long 0x00 "SCB2_INTR_TX_MASKED,Transmitter Interrupt Mask Register" bitfld.long 0x00 10. " UART_ARB_LOST ,Logical AND of corresponding request and mask bits" "Not masked,Masked" bitfld.long 0x00 9. " UART_DONE ,Logical AND of corresponding request and mask bits" "Not masked,Masked" bitfld.long 0x00 8. " UART_NACK ,Logical AND of corresponding request and mask bits" "Not masked,Masked" textline " " bitfld.long 0x00 7. " BLOCKED ,Logical AND of corresponding request and mask bits" "Not masked,Masked" bitfld.long 0x00 6. " UNDERFLOW ,Logical AND of corresponding request and mask bits" "Not masked,Masked" bitfld.long 0x00 5. " OVERFLOW ,Logical AND of corresponding request and mask bits" "Not masked,Masked" textline " " bitfld.long 0x00 4. " EMPTY ,Logical AND of corresponding request and mask bits" "Not masked,Masked" bitfld.long 0x00 1. " NOT_FULL ,Logical AND of corresponding request and mask bits" "Not masked,Masked" bitfld.long 0x00 0. " TRIGGER ,Logical AND of corresponding request and mask bits" "Not masked,Masked" group.long 0xFC0++0x03 line.long 0x00 "SCB2_INTR_RX,Receiver Interrupt Request Register" setclrfld.long 0x00 11. 0x04 11. 0x00 11. " BREAK_DETECT ,Break detection interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 10. 0x04 10. 0x00 10. " BAUD_DETECT ,LIN baudrate detection interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 9. 0x04 9. 0x00 9. " PARITY_ERROR ,Parity error in received data frame interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 8. 0x04 8. 0x00 8. " FRAME_ERROR ,Frame error in received data frame interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 7. 0x04 7. 0x00 7. " BLOCKED ,AHB-Lite read transfer access to the EZ memory interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 6. 0x04 6. 0x00 6. " UNDERFLOW ,Attempt to read from an empty RX FIFO interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 5. 0x04 5. 0x00 5. " OVERFLOW ,Attempt to write to a full RX FIFO interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 3. 0x04 3. 0x00 3. " FULL ,RX FIFO is full interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 2. 0x04 2. 0x00 2. " NOT_EMPTY ,RX FIFO is not empty interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 0. 0x04 0. 0x00 0. " TRIGGER ,More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in SCB_RX_FIFO_CTL interrupt" "No interrupt,Interrupt" group.long 0xFC8++0x03 line.long 0x00 "SCB2_INTR_RX_MASK,Receiver Interrupt Mask Register" bitfld.long 0x00 11. " BREAK_DETECT ,BREAK_DETECT interrupt mask" "Not masked,Masked" bitfld.long 0x00 10. " BAUD_DETECT ,BAUD_DETECT interrupt mask" "Not masked,Masked" bitfld.long 0x00 9. " PARITY_ERROR ,PARITY_ERROR interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 8. " FRAME_ERROR ,FRAME_ERROR interrupt mask" "Not masked,Masked" bitfld.long 0x00 7. " BLOCKED ,BLOCKED interrupt mask" "Not masked,Masked" bitfld.long 0x00 6. " UNDERFLOW ,UNDERFLOW interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 5. " OVERFLOW ,OVERFLOW interrupt mask" "Not masked,Masked" bitfld.long 0x00 3. " FULL ,FULL interrupt mask" "Not masked,Masked" bitfld.long 0x00 2. " NOT_EMPTY ,NOT_EMPTY interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 0. " TRIGGER ,TRIGGER interrupt mask" "Not masked,Masked" rgroup.long 0xFCC++0x03 line.long 0x00 "SCB2_INTR_RX_MASKED,Receiver Interrupt Masked Request Register" bitfld.long 0x00 11. " BREAK_DETECT ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 10. " BAUD_DETECT ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 9. " PARITY_ERROR ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" textline " " bitfld.long 0x00 8. " FRAME_ERROR ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 7. " BLOCKED ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 6. " UNDERFLOW ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" textline " " bitfld.long 0x00 5. " OVERFLOW ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 3. " FULL ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 2. " NOT_EMPTY ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " TRIGGER ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" width 0x0B tree.end sif (!cpuis("CY8C424?AZI-L423")&&!cpuis("CY8C424?AZI-L433")) tree "SCB3" base ad:0x40270000 if (((per.l(ad:0x40270000))&0x3000000)==0x0000000) width 12. if (((per.l(ad:0x40270000))&0x200)==0x200) if (((per.l(ad:0x40270000))&0x80000000)==0x80000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked" textline " " rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" else group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked" textline " " bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" endif else if (((per.l(ad:0x40270000))&0x80000000)==0x80000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." textline " " rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" else group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." textline " " bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" endif endif rgroup.long 0x04++0x03 line.long 0x00 "STATUS,Generic Status Register" bitfld.long 0x00 0. " EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy" if (((per.l(ad:0x40270000+0x60))&0xC0000000)==0xC0000000) if (((per.l(ad:0x40270000))&0x100)==0x100)&&((((per.l(ad:0x40270000))&0x200)==0x000)||(((per.l(ad:0x40270000+0x60))&0x800)==0x800)||(((per.l(ad:0x40270000))&0x400)==0x400)) if (((per.l(ad:0x40270000))&0x400)==0x000) group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 14. " S_NOT_READY_ADDR_NACK ,Slave not ready address NACK" "Ready,Not ready" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" else group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" endif elif (((per.l(ad:0x40270000))&0x100)==0x000)&&(((per.l(ad:0x40270000))&0x200)==0x000)&&(((per.l(ad:0x40270000))&0x400)==0x000) group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" else if (((per.l(ad:0x40270000))&0x400)==0x400) group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" else group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" endif endif elif (((per.l(ad:0x40270000+0x60))&0xC0000000)==0x80000000) if (((per.l(ad:0x40270000))&0x100)==0x100)&&((((per.l(ad:0x40270000))&0x200)==0x000)||(((per.l(ad:0x40270000+0x60))&0x800)==0x800)||(((per.l(ad:0x40270000))&0x400)==0x400)) if (((per.l(ad:0x40270000))&0x400)==0x000) group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 14. " S_NOT_READY_ADDR_NACK ,Slave not ready address NACK" "Ready,Not ready" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" bitfld.long 0x00 4.--7. " LOW_PHASE_OVS ,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " HIGH_PHASE_OVS ,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" bitfld.long 0x00 4.--7. " LOW_PHASE_OVS ,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " HIGH_PHASE_OVS ,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif elif (((per.l(ad:0x40270000))&0x100)==0x000)&&(((per.l(ad:0x40270000))&0x200)==0x000)&&(((per.l(ad:0x40270000))&0x400)==0x000) group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" bitfld.long 0x00 4.--7. " LOW_PHASE_OVS ,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " HIGH_PHASE_OVS ,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else if (((per.l(ad:0x40270000))&0x400)==0x400) group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" bitfld.long 0x00 4.--7. " LOW_PHASE_OVS ,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " HIGH_PHASE_OVS ,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" bitfld.long 0x00 4.--7. " LOW_PHASE_OVS ,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " HIGH_PHASE_OVS ,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif endif elif (((per.l(ad:0x40270000+0x60))&0xC0000000)==0x40000000) if (((per.l(ad:0x40270000))&0x100)==0x100)&&((((per.l(ad:0x40270000))&0x200)==0x000)||(((per.l(ad:0x40270000+0x60))&0x800)==0x800)||(((per.l(ad:0x40270000))&0x400)==0x400)) if (((per.l(ad:0x40270000))&0x400)==0x000) group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 14. " S_NOT_READY_ADDR_NACK ,Slave not ready address NACK" "Ready,Not ready" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" else group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" endif elif (((per.l(ad:0x40270000))&0x100)==0x000)&&(((per.l(ad:0x40270000))&0x200)==0x000)&&(((per.l(ad:0x40270000))&0x400)==0x000) group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" else if (((per.l(ad:0x40270000))&0x400)==0x400) group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" else group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" endif endif else if (((per.l(ad:0x40270000))&0x100)==0x100)&&((((per.l(ad:0x40270000))&0x200)==0x000)||(((per.l(ad:0x40270000+0x60))&0x800)==0x800)||(((per.l(ad:0x40270000))&0x400)==0x400)) if (((per.l(ad:0x40270000))&0x400)==0x000) group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 14. " S_NOT_READY_ADDR_NACK ,Slave not ready address NACK" "Ready,Not ready" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" else group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" endif elif (((per.l(ad:0x40270000))&0x100)==0x000)&&(((per.l(ad:0x40270000))&0x200)==0x000)&&(((per.l(ad:0x40270000))&0x400)==0x000) group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" else if (((per.l(ad:0x40270000))&0x400)==0x400) group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" else group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode enabled" "Disabled,Enabled" bitfld.long 0x00 30. " SLAVE_MODE ,Slave mode enabled" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " S_NOT_READY_DATA_NACK ,Slave not ready data NACK" "Clock stretching,Data NACK" bitfld.long 0x00 13. " S_READY_DATA_ACK ,Slave ready data ACK" "Not ready,Ready" textline " " bitfld.long 0x00 12. " S_READY_ADDR_ACK ,Slave ready address ACK" "Not ready,Ready" bitfld.long 0x00 11. " S_GENERAL_IGNORE ,Slave general ignore" "Not ignored,Ignored" bitfld.long 0x00 9. " M_NOT_READY_DATA_NACK ,Master not ready data NACK" "Ready,Not ready" textline " " bitfld.long 0x00 8. " M_READY_DATA_ACK ,Master ready data ACK" "Not ready,Ready" endif endif endif if (((per.l(ad:0x40270000))&0x200)==0x000) rgroup.long 0x64++0x03 line.long 0x00 "I2C_STATUS,I2C Status Register" hexmask.long.byte 0x00 16.--23. 1. " BASE_EZ_ADDR ,I2C slave base EZ address" hexmask.long.byte 0x00 8.--15. 1. " CURR_EZ_ADDR ,I2C slave current EZ address" bitfld.long 0x00 5. " M_READ ,I2C master read transfer" "Write transfer,Read transfer" textline " " bitfld.long 0x00 4. " S_READ ,I2C slave read transfer" "Write transfer,Read transfer" bitfld.long 0x00 1. " I2C_EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy" bitfld.long 0x00 0. " BUS_BUSY ,I2C bus is busy" "Not busy,Busy" else rgroup.long 0x64++0x03 line.long 0x00 "I2C_STATUS,I2C Status Register" bitfld.long 0x00 5. " M_READ ,I2C master read transfer" "Write transfer,Read transfer" textline " " bitfld.long 0x00 4. " S_READ ,I2C slave read transfer" "Write transfer,Read transfer" bitfld.long 0x00 1. " I2C_EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy" bitfld.long 0x00 0. " BUS_BUSY ,I2C bus is busy" "Not busy,Busy" endif if (((per.l(ad:0x40270000+0x60))&0x80000000)==0x80000000) group.long 0x68++0x03 line.long 0x00 "I2C_M_CMD,I2C Master Command Register" bitfld.long 0x00 4. " M_STOP ,Master transmit STOP" "Disabled,ENABLED" bitfld.long 0x00 3. " M_NACK ,Master negative acknowledgement transmit" "Disabled,Enabled" bitfld.long 0x00 2. " M_ACK ,Master acknowledgement transmit" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " M_START_ON_IDLE ,Master START on idle" "Disabled,Enabled" bitfld.long 0x00 0. " M_START ,Master transmit START" "Disabled,Enabled" else hgroup.long 0x68++0x03 hide.long 0x00 "I2C_M_CMD,I2C Master Command Register" endif if (((per.l(ad:0x40270000+0x60))&0x40000000)==0x40000000) if (((per.l(ad:0x40270000))&0x400)==0x400) group.long 0x6C++0x03 line.long 0x00 "I2C_S_CMD,I2C Slave Command Register" bitfld.long 0x00 1. " S_NACK ,Slave negative acknowledgement transmit" "Disabled,Enabled" bitfld.long 0x00 0. " S_ACK ,Slave acknowledgement transmit" "Disabled,Enabled" else group.long 0x6C++0x03 line.long 0x00 "I2C_S_CMD,I2C Slave Command Register" bitfld.long 0x00 1. " S_NACK ,Slave negative acknowledgement transmit" "Disabled,Enabled" endif else hgroup.long 0x6C++0x03 hide.long 0x00 "I2C_S_CMD,I2C Slave Command Register" endif group.long 0x70++0x03 line.long 0x00 "I2C_CFG,I2C Configuration Register" bitfld.long 0x00 28.--29. " SDA_OUT_FILT_SEL ,Selection of cumulative 'i2c_sda_out' filter delay" "0 ns,50 ns,100 ns,150 ns" bitfld.long 0x00 20.--21. " SDA_OUT_FILT2_TRIM ,Trim bits for 'i2c_sda_out' 50 ns filter 2" "0,1,2,3" bitfld.long 0x00 18.--19. " SDA_OUT_FILT1_TRIM ,Trim bits for 'i2c_sda_out' 50 ns filter 1" "0,1,2,3" textline " " bitfld.long 0x00 16.--17. " SDA_OUT_FILT0_TRIM ,Trim bits for 'i2c_sda_out' 50 ns filter 0" "0,1,2,3" bitfld.long 0x00 12. " SCL_IN_FILT_SEL ,Selection of 'i2c_sda_in' filter delay" "0 ns,50 ns" bitfld.long 0x00 8.--9. " SCL_IN_FILT_TRIM ,Trim bits for 'i2c_sda_in' 50 ns filter" "0,1,2,3" textline " " bitfld.long 0x00 4. " SDA_IN_FILT_SEL ,Selection of 'i2c_sda_in' filter delay" "0 ns,50 ns" bitfld.long 0x00 0.--1. " SDA_IN_FILT_TRIM ,Trim bits for 'i2c_sda_in' 50 ns filter" "0,1,2,3" width 0x0B elif (((per.l(ad:0x40270000))&0x3000000)==0x1000000) width 22. if (((per.l(ad:0x40270000+0x20))&0x80000000)==0x80000000) if (((per.l(ad:0x40270000))&0x200)==0x200) if (((per.l(ad:0x40270000))&0x80000000)==0x80000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked" textline " " rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked" rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked" textline " " bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked" bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15" endif else if (((per.l(ad:0x40270000))&0x80000000)==0x80000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." textline " " rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked" rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." textline " " bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked" bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15" endif endif rgroup.long 0x04++0x03 line.long 0x00 "STATUS,Generic Status Register" bitfld.long 0x00 0. " EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy" if (((per.l(ad:0x40270000+0x20))&0x3000000)==0x0000000) if (((per.l(ad:0x40270000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40270000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40270000+0x20))&0xC000000)==0x0000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40270000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40270000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40270000+0x20))&0xC000000)==0x4000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40270000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40270000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40270000+0x20))&0xC000000)==0x8000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40270000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40270000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40270000+0x20))&0xC000000)==0xC000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40270000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40270000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40270000+0x20))&0xC000000)==0x0000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40270000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40270000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40270000+0x20))&0xC000000)==0x4000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40270000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40270000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40270000+0x20))&0xC000000)==0x8000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40270000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40270000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40270000+0x20))&0xC000000)==0xC000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40270000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40270000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40270000+0x20))&0xC000000)==0x0000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40270000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40270000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40270000+0x20))&0xC000000)==0x4000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40270000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40270000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40270000+0x20))&0xC000000)==0x8000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40270000+0x20))&0x8)==0x0)&&(((per.l(ad:0x40270000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40270000+0x20))&0xC000000)==0xC000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40270000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40270000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40270000+0x20))&0xC000000)==0x0000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40270000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40270000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40270000+0x20))&0xC000000)==0x4000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40270000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40270000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40270000+0x20))&0xC000000)==0x8000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40270000+0x20))&0x8)==0x8)&&(((per.l(ad:0x40270000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40270000+0x20))&0xC000000)==0xC000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" endif elif (((per.l(ad:0x40270000+0x20))&0x3000000)==0x2000000) if (((per.l(ad:0x40270000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40270000+0x20))&0xC000000)==0x0000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40270000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40270000+0x20))&0xC000000)==0x4000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40270000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40270000+0x20))&0xC000000)==0x8000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40270000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40270000+0x20))&0xC000000)==0xC000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40270000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40270000+0x20))&0xC000000)==0x0000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40270000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40270000+0x20))&0xC000000)==0x4000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40270000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40270000+0x20))&0xC000000)==0x8000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40270000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40270000+0x20))&0xC000000)==0xC000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" endif elif (((per.l(ad:0x40270000+0x20))&0x3000000)==0x1000000) if (((per.l(ad:0x40270000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40270000+0x20))&0xC000000)==0x0000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "High,Low" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides" bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40270000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40270000+0x20))&0xC000000)==0x4000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "High,Low" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides" bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40270000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40270000+0x20))&0xC000000)==0x8000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "High,Low" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides" bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40270000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40270000+0x20))&0xC000000)==0xC000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "High,Low" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides" bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40270000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40270000+0x20))&0xC000000)==0x0000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "High,Low" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides" bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40270000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40270000+0x20))&0xC000000)==0x4000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "High,Low" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides" bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40270000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40270000+0x20))&0xC000000)==0x8000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "High,Low" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides" bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40270000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40270000+0x20))&0xC000000)==0xC000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "High,Low" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 1. " SELECT_PRECEDE ,Data frame start indication in a pulse on the SELECT line" "Precedes,Coincides" bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" endif else if (((per.l(ad:0x40270000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40270000+0x20))&0xC000000)==0x0000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40270000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40270000+0x20))&0xC000000)==0x4000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40270000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40270000+0x20))&0xC000000)==0x8000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40270000))&0x80000000)==0x00000000)&&(((per.l(ad:0x40270000+0x20))&0xC000000)==0xC000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "Falling edge,Rising edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40270000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40270000+0x20))&0xC000000)==0x0000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 8. " SSEL_POLARITY0 ,Slave select polarity 0" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40270000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40270000+0x20))&0xC000000)==0x4000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 9. " SSEL_POLARITY1 ,Slave select polarity 1" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40270000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40270000+0x20))&0xC000000)==0x8000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 10. " SSEL_POLARITY2 ,Slave select polarity 2" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" elif (((per.l(ad:0x40270000))&0x80000000)==0x80000000)&&(((per.l(ad:0x40270000+0x20))&0xC000000)==0xC000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" rbitfld.long 0x00 26.--27. " SLAVE_SELECT ,Selects one of the four outgoing SPI slave select signals" "Slave 0/SPI_SELECT[0],Slave 1/SPI_SELECT[1],Slave 2/SPI_SELECT[2],Slave 3/SPI_SELECT[3]" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "Connected to MISO,Connected to MOSI" bitfld.long 0x00 11. " SSEL_POLARITY3 ,Slave select polarity 3" "Low,High" bitfld.long 0x00 5. " SCLK_CONTINUOUS ,This mode is useful for slave devices that use SCLK for functional operation other than just SPI functionality" "Data transmited,Only SPI enabled" textline " " bitfld.long 0x00 4. " LATE_MISO_SAMPLE ,Changes the SCLK edge on which MISO is captured" "CPOL and CPHA,Alternate clock edge" textline " " bitfld.long 0x00 0. " CONTINUOUS ,Continuous SPI data transfers enabled" "Disabled,Enabled" endif endif else if (((per.l(ad:0x40270000))&0x200)==0x200) if (((per.l(ad:0x40270000))&0x80000000)==0x80000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked" textline " " rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked" else group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked" textline " " bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked selection" "Internally clocked,Externally clocked" endif else if (((per.l(ad:0x40270000))&0x80000000)==0x80000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." textline " " rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" else group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." textline " " bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" endif endif rgroup.long 0x04++0x03 line.long 0x00 "STATUS,Generic Status Register" bitfld.long 0x00 0. " EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy" if (((per.l(ad:0x40270000+0x20))&0x3000000)==0x0000000) if (((per.l(ad:0x40270000+0x20))&0x8)==0x0) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on falling edge/MISO on rising edge,MOSI on rising edge/MISO on falling edge" else group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." textline " " bitfld.long 0x00 3. " CPOL ,Indicates clock polarity" "0,1" bitfld.long 0x00 2. " CPHA ,Indicates clock phase" "MOSI on rising edge/MISO on falling edge,MOSI on falling edge/MISO on rising edge" endif elif (((per.l(ad:0x40270000+0x20))&0x3000000)==0x2000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." elif (((per.l(ad:0x40270000+0x20))&0x3000000)==0x1000000) group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." else group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI Control Register" bitfld.long 0x00 31. " MASTER_MODE ,Master mode or slave mode" "Slave mode,Master mode" bitfld.long 0x00 24.--25. " MODE ,Submode of SPI operation" "SPI_MOTOROLA,SPI_TI,SPI_NS,?..." endif endif if (((per.l(ad:0x40270000))&0x200)==0x000) rgroup.long 0x24++0x03 line.long 0x00 "SPI_STATUS,SPI Status Register" hexmask.long.byte 0x00 16.--23. 0x01 " BASE_EZ_ADDR ,SPI base EZ address" hexmask.long.byte 0x00 8.--15. 0x01 " CURR_EZ_ADDR ,SPI current EZ address" bitfld.long 0x00 1. " SPI_EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy" textline " " bitfld.long 0x00 0. " BUS_BUSY ,SPI bus is busy" "Not busy,Busy" else rgroup.long 0x24++0x03 line.long 0x00 "SPI_STATUS,SPI Status Register" bitfld.long 0x00 1. " SPI_EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy" textline " " bitfld.long 0x00 0. " BUS_BUSY ,SPI bus is busy" "Not busy,Busy" endif width 0x0B elif (((per.l(ad:0x40270000))&0x3000000)==0x2000000) width 21. if (((per.l(ad:0x40270000))&0x200)==0x200) if (((per.l(ad:0x40270000))&0x80000000)==0x80000000) if (((per.l(ad:0x40270000+0x40))&0x3000000)==0x0000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked" textline " " rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15" elif (((per.l(ad:0x40270000+0x40))&0x3000000)==0x1000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked" textline " " rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15" elif (((per.l(ad:0x40270000+0x40))&0x3000000)==0x2000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." rbitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked" textline " " rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" "16,32,48,96,192,768,1536,?..." endif else if (((per.l(ad:0x40270000+0x40))&0x3000000)==0x0000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked" textline " " bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15" elif (((per.l(ad:0x40270000+0x40))&0x3000000)==0x1000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked" textline " " bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15" elif (((per.l(ad:0x40270000+0x40))&0x3000000)==0x2000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." bitfld.long 0x00 17. " BLOCK ,SW access block" "Not blocked,Blocked" textline " " bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" "16,32,48,96,192,768,1536,?..." endif endif else if (((per.l(ad:0x40270000))&0x80000000)==0x80000000) if (((per.l(ad:0x40270000+0x40))&0x3000000)==0x0000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." textline " " rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15" elif (((per.l(ad:0x40270000+0x40))&0x3000000)==0x1000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." textline " " rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15" elif (((per.l(ad:0x40270000+0x40))&0x3000000)==0x2000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." textline " " rbitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" rbitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" rbitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " rbitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" rbitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" rbitfld.long 0x00 0.--3. " OVS ,Oversampling factor" "16,?..." endif else if (((per.l(ad:0x40270000+0x40))&0x3000000)==0x0000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." textline " " bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15" elif (((per.l(ad:0x40270000+0x40))&0x3000000)==0x1000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." textline " " bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" ",,,,,,,7,8,9,10,11,12,13,14,15" elif (((per.l(ad:0x40270000+0x40))&0x3000000)==0x2000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." textline " " bitfld.long 0x00 16. " ADDR_ACCEPT ,Address acceptation" "Not accepted,Accepted" bitfld.long 0x00 11. " BYTE_MODE ,Number of bits per FIFO data elements" "16-bit,8-bit" bitfld.long 0x00 10. " EZ_MODE ,EZ mode" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " EC_OP_MODE ,Externally clocked operation mode" "Internally clocked,Externally clocked" bitfld.long 0x00 8. " EC_AM_MODE ,Externally clocked address matching" "Internally clocked,Externally clocked" bitfld.long 0x00 0.--3. " OVS ,Oversampling factor" "16,?..." endif endif endif rgroup.long 0x04++0x03 line.long 0x00 "STATUS,Generic Status Register" bitfld.long 0x00 0. " EC_BUSY ,Indicates whether the externally clocked logic is potentially accessing the EZ memory" "Not busy,Busy" group.long 0x40++0x03 line.long 0x00 "UART_CTRL,UART Control Register" bitfld.long 0x00 24.--25. " MODE ,Submode of UART operation" "UART_STD,UART_SMARTCARD,UART_IRDA,?..." bitfld.long 0x00 16. " LOOPBACK ,Local loopback control" "0,1" if (((per.l(ad:0x40270000+0x40))&0x3000000)==0x0000000) group.long 0x44++0x07 line.long 0x00 "UART_TX_CTRL,UART Transmitter Control Register" bitfld.long 0x00 5. " PARITY_ENABLED ,Parity generation enabled" "Disabled,Enabled" rbitfld.long 0x00 4. " PARITY ,Parity bit" "Even,Odd" textline " " bitfld.long 0x00 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7" line.long 0x04 "UART_RX_CTRL,UART Receiver Control Register" bitfld.long 0x04 16.--19. " BREAK_WIDTH ,Break width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 13. " SKIP_START ,Skips start bit detection for the first received data frame" "Disabled,Enabled" bitfld.long 0x04 12. " LIN_MODE ,Break detection and baud rate detection on the incoming data" "Disabled,Enabled" textline " " bitfld.long 0x04 10. " MP_MODE ,Multi-processor mode" "Disabled,Enabled" bitfld.long 0x04 9. " DROP_ON_FRAME_ERROR ,Behaviour when an error is detected in a start or stop period" "Data send to RX FIFO,Data dropped" bitfld.long 0x04 8. " DROP_ON_PARITY_ERROR ,Behaviour when a parity check fails" "Data send to RX FIFO,Data dropped" textline " " bitfld.long 0x04 5. " PARITY_ENABLED ,Parity checking enabled" "Disabled,Enabled" bitfld.long 0x04 4. " PARITY ,Parity bit" "Even,Odd" bitfld.long 0x04 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7" elif (((per.l(ad:0x40270000+0x40))&0x3000000)==0x1000000) group.long 0x44++0x07 line.long 0x00 "UART_TX_CTRL,UART Transmitter Control Register" bitfld.long 0x00 8. " RETRY_ON_NACK ,Retransmitted when negative acknowledgement is received" "Not retransmitted,Retransmitted" rbitfld.long 0x00 4. " PARITY ,Parity bit" "Even,Odd" textline " " bitfld.long 0x00 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7" line.long 0x04 "UART_RX_CTRL,UART Receiver Control Register" bitfld.long 0x04 16.--19. " BREAK_WIDTH ,Break width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x04 10. " MP_MODE ,Multi-processor mode" "Disabled,Enabled" bitfld.long 0x04 9. " DROP_ON_FRAME_ERROR ,Behaviour when an error is detected in a start or stop period" "Data send to RX FIFO,Data dropped" bitfld.long 0x04 8. " DROP_ON_PARITY_ERROR ,Behaviour when a parity check fails" "Data send to RX FIFO,Data dropped" textline " " bitfld.long 0x04 4. " PARITY ,Parity bit" "Even,Odd" bitfld.long 0x04 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7" elif (((per.l(ad:0x40270000+0x40))&0x3000000)==0x2000000) group.long 0x44++0x07 line.long 0x00 "UART_TX_CTRL,UART Transmitter Control Register" bitfld.long 0x00 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7" line.long 0x04 "UART_RX_CTRL,UART Receiver Control Register" bitfld.long 0x04 16.--19. " BREAK_WIDTH ,Break width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x04 10. " MP_MODE ,Multi-processor mode" "Disabled,Enabled" bitfld.long 0x04 9. " DROP_ON_FRAME_ERROR ,Behaviour when an error is detected in a start or stop period" "Data send to RX FIFO,Data dropped" textline " " bitfld.long 0x04 6. " POLARITY ,Inverts incoming RX line signal" "Low,High" bitfld.long 0x04 0.--2. " STOP_BITS ,Stop bits" "0,1,2,3,4,5,6,7" endif rgroup.long 0x4C++0x03 line.long 0x00 "UART_RX_STATUS,UART Receiver Status Register" hexmask.long.word 0x00 0.--11. 1. " BR_COUNTER ,Amount of peripheral clock periods that constitute the transmission of a 0x55 data frame" group.long 0x50++0x03 line.long 0x00 "UART_FLOW_CTRL,UART Flow Control Register" bitfld.long 0x00 25. " CTS_ENABLED ,Enable use of CTS input signal" "Disabled,Enabled" bitfld.long 0x00 24. " CTS_POLARITY ,Polarity of the CTS input signal" "Low,High" bitfld.long 0x00 16. " RTS_POLARITY ,Polarity of the RTS output signal" "Low,High" textline " " bitfld.long 0x00 0.--3. " TRIGGER_LEVEL ,Trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B else width 18. if (((per.l(ad:0x40270000))&0x80000000)==0x80000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" rbitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." else group.long 0x00++0x03 line.long 0x00 "CTRL,Generic Control Register" bitfld.long 0x00 31. " ENABLED ,IP enabled" "Disabled,Enabled" bitfld.long 0x00 24.--25. " MODE ,Mode of operation" "I2C,SPI,UART,?..." endif endif textline " " width 28. if (((per.l(ad:0x40270000))&0x3000000)==0x2000000) group.long 0x200++0x03 line.long 0x00 "SCB3_TX_CTRL,Transmitter Control Register" bitfld.long 0x00 8. " MSB_FIRST ,Most significant bit first" "LSB,MSB" bitfld.long 0x00 0.--3. " DATA_WIDTH ,Dataframe width" ",,,3,4,5,6,7,8,?..." elif (((per.l(ad:0x40270000))&0x3000000)==0x1000000) group.long 0x200++0x03 line.long 0x00 "SCB3_TX_CTRL,Transmitter Control Register" bitfld.long 0x00 8. " MSB_FIRST ,Most significant bit first" "LSB,MSB" bitfld.long 0x00 0.--3. " DATA_WIDTH ,Dataframe width" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15" else group.long 0x200++0x03 line.long 0x00 "SCB3_TX_CTRL,Transmitter Control Register" bitfld.long 0x00 8. " MSB_FIRST ,Most significant bit first" "LSB,MSB" bitfld.long 0x00 0.--3. " DATA_WIDTH ,Dataframe width" ",,,,,,,7,?..." endif group.long 0x204++0x03 line.long 0x00 "SCB3_TX_FIFO_CTRL,Transmitter FIFO Control Register" bitfld.long 0x00 17. " FREEZE ,FIFO entries remove freeze" "Disabled,Enabled" bitfld.long 0x00 16. " CLEAR ,FIFO and transmitter shift register clear" "Not cleared,Cleared" bitfld.long 0x00 0.--3. " TRIGGER_LEVEL ,Trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x208++0x03 line.long 0x00 "SCB3_TX_FIFO_STATUS,Transmitter FIFO Status Register" bitfld.long 0x00 24.--27. " WR_PTR ,FIFO write pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " RD_PTR ,FIFO read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " SR_VALID ,TX shift registers valid data frame hold" "No,Yes" textline " " bitfld.long 0x00 0.--4. " USED ,Amount of enties in the transmitter FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" if (((per.l(ad:0x40270000))&0x800)==0x800) wgroup.long 0x240++0x03 line.long 0x00 "SCB3_TX_FIFO_WR,Transmitter FIFO Write Register" hexmask.long.byte 0x00 0.--7. 1. " DATA ,Data frame written into the transmitter FIFO" else wgroup.long 0x240++0x03 line.long 0x00 "SCB3_TX_FIFO_WR,Transmitter FIFO Write Register" hexmask.long.word 0x00 0.--15. 1. " DATA ,Data frame written into the transmitter FIFO" endif if (((per.l(ad:0x40270000))&0x3000400)==0x1000400) group.long 0x300++0x03 line.long 0x00 "SCB3_RX_CTRL,Transmitter Control Register" bitfld.long 0x00 9. " MEDIAN ,Median filter" "Off,On" bitfld.long 0x00 8. " MSB_FIRST ,Most significant bit first" "LSB,MSB" bitfld.long 0x00 0.--3. " DATA_WIDTH ,Dataframe width" ",,,,,,,7,?..." elif (((per.l(ad:0x40270000))&0x3000400)==0x1000400) group.long 0x300++0x03 line.long 0x00 "SCB3_RX_CTRL,Transmitter Control Register" bitfld.long 0x00 9. " MEDIAN ,Median filter" "Off,On" bitfld.long 0x00 8. " MSB_FIRST ,Most significant bit first" "LSB,MSB" bitfld.long 0x00 0.--3. " DATA_WIDTH ,Dataframe width" ",,,3,4,5,6,7,8,9,10,11,12,13,14,15" elif (((per.l(ad:0x40270000))&0x3000000)==0x2000000) group.long 0x300++0x03 line.long 0x00 "SCB3_RX_CTRL,Transmitter Control Register" bitfld.long 0x00 9. " MEDIAN ,Median filter" "Off,On" bitfld.long 0x00 8. " MSB_FIRST ,Most significant bit first" "LSB,MSB" bitfld.long 0x00 0.--3. " DATA_WIDTH ,Dataframe width" ",,,3,4,5,6,7,8,?..." else group.long 0x300++0x03 line.long 0x00 "SCB3_RX_CTRL,Transmitter Control Register" bitfld.long 0x00 9. " MEDIAN ,Median filter" "Off,On" bitfld.long 0x00 8. " MSB_FIRST ,Most significant bit first" "LSB,MSB" bitfld.long 0x00 0.--3. " DATA_WIDTH ,Dataframe width" ",,,,,,,7,?..." endif group.long 0x304++0x03 line.long 0x00 "SCB3_RX_FIFO_CTRL,Receiver FIFO Control Register" bitfld.long 0x00 17. " FREEZE ,Receiver FIFO have no effect" "Disabled,Enabled" bitfld.long 0x00 16. " CLEAR ,FIFO and receiver shift register clear" "Not cleared,Cleared" bitfld.long 0x00 0.--3. " TRIGGER_LEVEL ,Trigger level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x308++0x03 line.long 0x00 "SCB3_RX_FIFO_STATUS,Receiver FIFO Status Register" bitfld.long 0x00 24.--27. " WR_PTR ,FIFO write pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " RD_PTR ,FIFO read pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 15. " SR_VALID ,RX shift registers valid data frame hold" "No,Yes" textline " " bitfld.long 0x00 0.--4. " USED ,Amount of enties in the receiver FIFO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x310++0x03 line.long 0x00 "SCB3_RX_MATCH,Slave Address and Mask Register" hexmask.long.byte 0x00 16.--23. 0x01 " MASK ,Slave device address mask" hexmask.long.byte 0x00 0.--7. 0x01 " ADDR ,Slave device address" if (((per.l(ad:0x40270000))&0x800)==0x800) rgroup.long 0x340++0x07 line.long 0x00 "SCB3_RX_FIFO_RD,Receiver FIFO Read Register" hexmask.long.word 0x00 0.--15. 0x01 " DATA ,Data read from the receiver FIFO" line.long 0x04 "SCB3_RX_FIFO_RD_SILENT,Receiver FIFO Read Register" hexmask.long.word 0x04 0.--15. 0x01 " DATA ,Data read from the receiver FIFO" else rgroup.long 0x340++0x07 line.long 0x00 "SCB3_RX_FIFO_RD,Receiver FIFO Read Register" hexmask.long.byte 0x00 0.--7. 0x01 " DATA ,Data read from the receiver FIFO" line.long 0x04 "SCB3_RX_FIFO_RD_SILENT,Receiver FIFO Read Register" hexmask.long.byte 0x04 0.--7. 0x01 " DATA ,Data read from the receiver FIFO" endif group.long 0x400++0x03 line.long 0x00 "SCB3_EZ_DATA0,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x404++0x03 line.long 0x00 "SCB3_EZ_DATA1,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x408++0x03 line.long 0x00 "SCB3_EZ_DATA2,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x40C++0x03 line.long 0x00 "SCB3_EZ_DATA3,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x410++0x03 line.long 0x00 "SCB3_EZ_DATA4,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x414++0x03 line.long 0x00 "SCB3_EZ_DATA5,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x418++0x03 line.long 0x00 "SCB3_EZ_DATA6,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x41C++0x03 line.long 0x00 "SCB3_EZ_DATA7,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x420++0x03 line.long 0x00 "SCB3_EZ_DATA8,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x424++0x03 line.long 0x00 "SCB3_EZ_DATA9,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x428++0x03 line.long 0x00 "SCB3_EZ_DATA10,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x42C++0x03 line.long 0x00 "SCB3_EZ_DATA11,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x430++0x03 line.long 0x00 "SCB3_EZ_DATA12,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x434++0x03 line.long 0x00 "SCB3_EZ_DATA13,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x438++0x03 line.long 0x00 "SCB3_EZ_DATA14,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x43C++0x03 line.long 0x00 "SCB3_EZ_DATA15,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x440++0x03 line.long 0x00 "SCB3_EZ_DATA16,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x444++0x03 line.long 0x00 "SCB3_EZ_DATA17,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x448++0x03 line.long 0x00 "SCB3_EZ_DATA18,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x44C++0x03 line.long 0x00 "SCB3_EZ_DATA19,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x450++0x03 line.long 0x00 "SCB3_EZ_DATA20,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x454++0x03 line.long 0x00 "SCB3_EZ_DATA21,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x458++0x03 line.long 0x00 "SCB3_EZ_DATA22,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x45C++0x03 line.long 0x00 "SCB3_EZ_DATA23,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x460++0x03 line.long 0x00 "SCB3_EZ_DATA24,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x464++0x03 line.long 0x00 "SCB3_EZ_DATA25,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x468++0x03 line.long 0x00 "SCB3_EZ_DATA26,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x46C++0x03 line.long 0x00 "SCB3_EZ_DATA27,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x470++0x03 line.long 0x00 "SCB3_EZ_DATA28,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x474++0x03 line.long 0x00 "SCB3_EZ_DATA29,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x478++0x03 line.long 0x00 "SCB3_EZ_DATA30,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" group.long 0x47C++0x03 line.long 0x00 "SCB3_EZ_DATA31,Memory Buffer register" hexmask.long.byte 0x00 0.--7. 0x01 " EZ_DATA ,Data in buffer memory location" rgroup.long 0xE00++0x03 line.long 0x00 "SCB3_INTR_CAUSE,Active Clocked Interrupt Signal Register" bitfld.long 0x00 5. " SPI_EC ,Externally clocked SPI interrupt active" "Not active,Active" bitfld.long 0x00 4. " I2C_EC ,Externally clock I2C interrupt active" "Not active,Active" bitfld.long 0x00 3. " RX ,Receiver interrupt active" "Not active,Active" textline " " bitfld.long 0x00 2. " TX ,Transmitter interrupt active" "Not active,Active" bitfld.long 0x00 1. " S ,Slave interrupt active" "Not active,Active" bitfld.long 0x00 0. " M ,Master interrupt active" "Not active,Active" if (((per.l(ad:0x40270000))&0x700)==0x700) group.long 0xE80++0x03 line.long 0x00 "SCB3_INTR_I2C_EC,Externally Clocked I2C Interrupt Request Register" eventfld.long 0x00 3. " EZ_READ_STOP ,STOP detection after a read transfer occurred" "No interrupt,Interrupt" eventfld.long 0x00 2. " EZ_WRITE_STOP ,STOP detection after a write transfer occurred" "No interrupt,Interrupt" eventfld.long 0x00 1. " EZ_STOP ,STOP detection" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " WAKE_UP ,Wake up request" "No interrupt,Interrupt" group.long 0xE88++0x03 line.long 0x00 "SCB3_INTR_I2C_EC_MASK,Externally Clocked I2C Interrupt Mask Register" bitfld.long 0x00 3. " EZ_READ_STOP ,STOP detection after a read transfer occurred interrupt mask" "Not masked,Masked" bitfld.long 0x00 2. " EZ_WRITE_STOP ,STOP detection after a write transfer occurred interrupt mask" "Not masked,Masked" bitfld.long 0x00 1. " EZ_STOP ,STOP detection interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 0. " WAKE_UP ,Wake up request interrupt mask" "Not masked,Masked" rgroup.long 0xE8C++0x03 line.long 0x00 "SCB3_INTR_I2C_EC_MASKED,Externally Clocked I2C Interrupt Masked Register" bitfld.long 0x00 3. " EZ_READ_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 2. " EZ_WRITE_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 1. " EZ_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " WAKE_UP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" group.long 0xEC0++0x03 line.long 0x00 "SCB3_INTR_SPI_EC,Externally Clocked SPI Interrupt Request Register" eventfld.long 0x00 3. " EZ_READ_STOP ,STOP detection after a read transfer occurred" "No interrupt,Interrupt" eventfld.long 0x00 2. " EZ_WRITE_STOP ,STOP detection after a write transfer occurred" "No interrupt,Interrupt" eventfld.long 0x00 1. " EZ_STOP ,STOP detection" "No interrupt,Interrupt" textline " " eventfld.long 0x00 0. " WAKE_UP ,Wake up request" "No interrupt,Interrupt" group.long 0xEC8++0x03 line.long 0x00 "SCB3_INTR_SPI_EC_MASK,Externally Clocked SPI Interrupt Mask Register" bitfld.long 0x00 3. " EZ_READ_STOP ,STOP detection after a read transfer occurred interrupt mask" "Not masked,Masked" bitfld.long 0x00 2. " EZ_WRITE_STOP ,STOP detection after a write transfer occurred interrupt mask" "Not masked,Masked" bitfld.long 0x00 1. " EZ_STOP ,STOP detection interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 0. " WAKE_UP ,Wake up request interrupt mask" "Not masked,Masked" rgroup.long 0xE8C++0x03 line.long 0x00 "SCB3_INTR_SPI_EC_MASKED,Externally Clocked SPI Interrupt Masked Register" bitfld.long 0x00 3. " EZ_READ_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 2. " EZ_WRITE_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 1. " EZ_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " WAKE_UP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" elif (((per.l(ad:0x40270000))&0x700)==0x600) group.long 0xE80++0x03 line.long 0x00 "SCB3_INTR_I2C_EC,Externally Clocked I2C Interrupt Request Register" eventfld.long 0x00 3. " EZ_READ_STOP ,STOP detection after a read transfer occurred" "No interrupt,Interrupt" eventfld.long 0x00 2. " EZ_WRITE_STOP ,STOP detection after a write transfer occurred" "No interrupt,Interrupt" eventfld.long 0x00 1. " EZ_STOP ,STOP detection" "No interrupt,Interrupt" group.long 0xE88++0x03 line.long 0x00 "SCB3_INTR_I2C_EC_MASK,Externally Clocked I2C Interrupt Mask Register" bitfld.long 0x00 3. " EZ_READ_STOP ,STOP detection after a read transfer occurred interrupt mask" "Not masked,Masked" bitfld.long 0x00 2. " EZ_WRITE_STOP ,STOP detection after a write transfer occurred interrupt mask" "Not masked,Masked" bitfld.long 0x00 1. " EZ_STOP ,STOP detection interrupt mask" "Not masked,Masked" rgroup.long 0xE8C++0x03 line.long 0x00 "SCB3_INTR_I2C_EC_MASKED,Externally Clocked I2C Interrupt Masked Register" bitfld.long 0x00 3. " EZ_READ_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 2. " EZ_WRITE_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 1. " EZ_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" group.long 0xEC0++0x03 line.long 0x00 "SCB3_INTR_SPI_EC,Externally Clocked SPI Interrupt Request Register" eventfld.long 0x00 3. " EZ_READ_STOP ,STOP detection after a read transfer occurred" "No interrupt,Interrupt" eventfld.long 0x00 2. " EZ_WRITE_STOP ,STOP detection after a write transfer occurred" "No interrupt,Interrupt" eventfld.long 0x00 1. " EZ_STOP ,STOP detection" "No interrupt,Interrupt" group.long 0xEC8++0x03 line.long 0x00 "SCB3_INTR_SPI_EC_MASK,Externally Clocked SPI Interrupt Mask Register" bitfld.long 0x00 3. " EZ_READ_STOP ,STOP detection after a read transfer occurred interrupt mask" "Not masked,Masked" bitfld.long 0x00 2. " EZ_WRITE_STOP ,STOP detection after a write transfer occurred interrupt mask" "Not masked,Masked" bitfld.long 0x00 1. " EZ_STOP ,STOP detection interrupt mask" "Not masked,Masked" rgroup.long 0xE8C++0x03 line.long 0x00 "SCB3_INTR_SPI_EC_MASKED,Externally Clocked SPI Interrupt Masked Register" bitfld.long 0x00 3. " EZ_READ_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 2. " EZ_WRITE_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 1. " EZ_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" elif (((per.l(ad:0x40270000))&0x700)==0x000) group.long 0xE80++0x03 line.long 0x00 "SCB3_INTR_I2C_EC,Externally Clocked I2C Interrupt Request Register" group.long 0xE88++0x03 line.long 0x00 "SCB3_INTR_I2C_EC_MASK,Externally Clocked I2C Interrupt Mask Register" rgroup.long 0xE8C++0x03 line.long 0x00 "SCB3_INTR_I2C_EC_MASKED,Externally Clocked I2C Interrupt Masked Register" group.long 0xEC0++0x03 line.long 0x00 "SCB3_INTR_SPI_EC,Externally Clocked SPI Interrupt Request Register" group.long 0xEC8++0x03 line.long 0x00 "SCB3_INTR_SPI_EC_MASK,Externally Clocked SPI Interrupt Mask Register" rgroup.long 0xE8C++0x03 line.long 0x00 "SCB3_INTR_SPI_EC_MASKED,Externally Clocked SPI Interrupt Masked Register" else group.long 0xE80++0x03 line.long 0x00 "SCB3_INTR_I2C_EC,Externally Clocked I2C Interrupt Request Register" textline " " eventfld.long 0x00 0. " WAKE_UP ,Wake up request" "No interrupt,Interrupt" group.long 0xE88++0x03 line.long 0x00 "SCB3_INTR_I2C_EC_MASK,Externally Clocked I2C Interrupt Mask Register" textline " " bitfld.long 0x00 0. " WAKE_UP ,Wake up request interrupt mask" "Not masked,Masked" rgroup.long 0xE8C++0x03 line.long 0x00 "SCB3_INTR_I2C_EC_MASKED,Externally Clocked I2C Interrupt Masked Register" textline " " bitfld.long 0x00 0. " WAKE_UP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" group.long 0xEC0++0x03 line.long 0x00 "SCB3_INTR_SPI_EC,Externally Clocked SPI Interrupt Request Register" textline " " eventfld.long 0x00 0. " WAKE_UP ,Wake up request" "No interrupt,Interrupt" group.long 0xEC8++0x03 line.long 0x00 "SCB3_INTR_SPI_EC_MASK,Externally Clocked SPI Interrupt Mask Register" textline " " bitfld.long 0x00 0. " WAKE_UP ,Wake up request interrupt mask" "Not masked,Masked" rgroup.long 0xE8C++0x03 line.long 0x00 "SCB3_INTR_SPI_EC_MASKED,Externally Clocked SPI Interrupt Masked Register" textline " " bitfld.long 0x00 0. " WAKE_UP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" endif group.long 0xF00++0x03 line.long 0x00 "SCB3_INTR_M_set/clr,Master Interrupt Register" setclrfld.long 0x00 9. 0x04 9. 0x00 9. " SPI_DONE ,SPI master transfer done event interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 8. 0x04 8. 0x00 8. " I2C_BUS_ERROR ,I2C master bus error interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 4. 0x04 4. 0x00 4. " I2C_STOP ,I2C master STOP interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 2. 0x04 2. 0x00 2. " I2C_ACK ,I2C master acknowledgement interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 1. 0x04 1. 0x00 1. " I2C_NACK ,I2C master negative acknowledgement interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 0. 0x04 0. 0x00 0. " I2C_ARB_LOST ,I2C master lost arbitration interrupt" "No interrupt,Interrupt" group.long 0xF08++0x03 line.long 0x00 "SCB3_INTR_M_MASK,Master Interrupt Mask Register" bitfld.long 0x00 9. " SPI_DONE ,SPI master transfer done event interrupt" "Not masked,Masked" bitfld.long 0x00 8. " I2C_BUS_ERROR ,I2C master bus error interrupt" "Not masked,Masked" bitfld.long 0x00 4. " I2C_STOP ,I2C master STOP interrupt" "Not masked,Masked" textline " " bitfld.long 0x00 2. " I2C_ACK ,I2C master acknowledgement interrupt" "Not masked,Masked" bitfld.long 0x00 1. " I2C_NACK ,I2C master negative acknowledgement interrupt" "Not masked,Masked" bitfld.long 0x00 0. " I2C_ARB_LOST ,I2C master lost arbitration interrupt" "Not masked,Masked" rgroup.long 0xF0C++0x03 line.long 0x00 "SCB3_INTR_M_MASKED,Master Interrupt Masked Request Register" bitfld.long 0x00 9. " SPI_DONE ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 8. " I2C_BUS_ERROR ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 4. " I2C_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" textline " " bitfld.long 0x00 2. " I2C_ACK ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 1. " I2C_NACK ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 0. " I2C_ARB_LOST ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" group.long 0xF40++0x03 line.long 0x00 "SCB3_INTR_S,Slave Interrupt Request Register" setclrfld.long 0x00 11. 0x04 11. 0x00 11. " SPI_BUS_ERROR ,SPI slave deselected at an unexpected time in the SPI transfer interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 10. 0x04 10. 0x00 10. " SPI_EZ_STOP ,SPI slave deselected after any EZ SPI transfer occurred interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 9. 0x04 9. 0x00 9. " SPI_EZ_WRITE_STOP ,SPI slave deselected after a write EZ SPI transfer occurred interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 8. 0x04 8. 0x00 8. " I2C_BUS_ERROR ,I2C slave bus error interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 7. 0x04 7. 0x00 7. " I2C_GENERAL ,I2C slave general call address received interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 6. 0x04 6. 0x00 6. " I2C_ADDR_MATCH ,I2C slave matching address received interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 5. 0x04 5. 0x00 5. " I2C_START ,I2C slave START received interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 4. 0x04 4. 0x00 4. " I2C_STOP ,I2C STOP event for I2C (read or write) transfer intended for this slave interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 3. 0x04 3. 0x00 3. " I2C_WRITE_STOP ,I2C STOP event for I2C write transfer intended for this slave interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 2. 0x04 2. 0x00 2. " I2C_ACK ,I2C slave acknowledgement received interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 1. 0x04 1. 0x00 1. " I2C_NACK ,I2C slave negative acknowledgement received interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 0. 0x04 0. 0x00 0. " I2C_ARB_LOST ,I2C slave lost arbitration interrupt" "No interrupt,Interrupt" group.long 0xF48++0x03 line.long 0x00 "SCB3_INTR_S_MASK,Slave Interrupt Mask Register" bitfld.long 0x00 11. " SPI_BUS_ERROR ,SPI slave deselected at an unexpected time in the SPI transfer interrupt mask" "Not masked,Masked" bitfld.long 0x00 10. " SPI_EZ_STOP ,SPI slave deselected after any EZ SPI transfer occurred interrupt mask" "Not masked,Masked" bitfld.long 0x00 9. " SPI_EZ_WRITE_STOP ,SPI slave deselected after a write EZ SPI transfer occurred interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 8. " I2C_BUS_ERROR ,I2C slave bus error interrupt mask" "Not masked,Masked" bitfld.long 0x00 7. " I2C_GENERAL ,I2C slave general call address received interrupt mask" "Not masked,Masked" bitfld.long 0x00 6. " I2C_ADDR_MATCH ,I2C slave matching address received interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 5. " I2C_START ,I2C slave START received interrupt mask" "Not masked,Masked" bitfld.long 0x00 4. " I2C_STOP ,I2C STOP event for I2C (read or write) transfer intended for this slave interrupt mask" "Not masked,Masked" bitfld.long 0x00 3. " I2C_WRITE_STOP ,SPI slave deselected at an unexpected time in the SPI transfer interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 2. " I2C_ACK ,SPI slave deselected at an unexpected time in the SPI transfer interrupt mask" "Not masked,Masked" bitfld.long 0x00 1. " I2C_NACK ,I2C slave negative acknowledgement received interrupt mask" "Not masked,Masked" bitfld.long 0x00 0. " I2C_ARB_LOST ,I2C slave lost arbitration interrupt mask" "Not masked,Masked" rgroup.long 0xF4C++0x03 line.long 0x00 "SCB3_INTR_S_MASKED,Slave Interrupt Masked Request Register" bitfld.long 0x00 11. " SPI_BUS_ERROR ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 10. " SPI_EZ_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 9. " SPI_EZ_WRITE_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" textline " " bitfld.long 0x00 8. " I2C_BUS_ERROR ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 7. " I2C_GENERAL ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 6. " I2C_ADDR_MATCH ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" textline " " bitfld.long 0x00 5. " I2C_START ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 4. " I2C_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 3. " I2C_WRITE_STOP ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" textline " " bitfld.long 0x00 2. " I2C_ACK ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 1. " I2C_NACK ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 0. " I2C_ARB_LOST ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" group.long 0xF80++0x03 line.long 0x00 "SCB3_INTR_TX_SET/CLR,Transmitter Interrupt Request Register" setclrfld.long 0x00 10. 0x04 10. 0x00 10. " UART_ARB_LOST ,UART lost arbitration interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 9. 0x04 9. 0x00 9. " UART_DONE ,UART transmitter done event interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 8. 0x04 8. 0x00 8. " UART_NACK ,UART transmitter received a negative acknowledgement in SmartCard mode interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 7. 0x04 7. 0x00 7. " BLOCKED ,AHB-Lite write transfer can not get access to the EZ memory interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 6. 0x04 6. 0x00 6. " UNDERFLOW ,Attempt to read from an empty TX FIFO interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 5. 0x04 5. 0x00 5. " OVERFLOW ,Attempt to write to a full TX FIFO interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 4. 0x04 4. 0x00 4. " EMPTY ,TX FIFO is empty interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 1. 0x04 1. 0x00 1. " NOT_FULL ,TX FIFO is not full interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 0. 0x04 0. 0x00 0. " TRIGGER ,Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL interrupt" "No interrupt,Interrupt" group.long 0xF88++0x03 line.long 0x00 "SCB3_INTR_TX_MASK,Transmitter Interrupt Mask Register" bitfld.long 0x00 10. " UART_ARB_LOST ,UART lost arbitration interrupt mask" "Not masked,Masked" bitfld.long 0x00 9. " UART_DONE ,UART transmitter done event interrupt mask" "Not masked,Masked" bitfld.long 0x00 8. " UART_NACK ,UART transmitter received a negative acknowledgement in SmartCard mode interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 7. " BLOCKED ,AHB-Lite write transfer can not get access to the EZ memory interrupt mask" "Not masked,Masked" bitfld.long 0x00 6. " UNDERFLOW ,Attempt to read from an empty TX FIFO interrupt mask" "Not masked,Masked" bitfld.long 0x00 5. " OVERFLOW ,Attempt to write to a full TX FIFO interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 4. " EMPTY ,TX FIFO is empty interrupt mask" "Not masked,Masked" bitfld.long 0x00 1. " NOT_FULL ,TX FIFO is not full interrupt mask" "Not masked,Masked" bitfld.long 0x00 0. " TRIGGER ,Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL interrupt mask" "Not masked,Masked" rgroup.long 0xF8C++0x03 line.long 0x00 "SCB3_INTR_TX_MASKED,Transmitter Interrupt Mask Register" bitfld.long 0x00 10. " UART_ARB_LOST ,Logical AND of corresponding request and mask bits" "Not masked,Masked" bitfld.long 0x00 9. " UART_DONE ,Logical AND of corresponding request and mask bits" "Not masked,Masked" bitfld.long 0x00 8. " UART_NACK ,Logical AND of corresponding request and mask bits" "Not masked,Masked" textline " " bitfld.long 0x00 7. " BLOCKED ,Logical AND of corresponding request and mask bits" "Not masked,Masked" bitfld.long 0x00 6. " UNDERFLOW ,Logical AND of corresponding request and mask bits" "Not masked,Masked" bitfld.long 0x00 5. " OVERFLOW ,Logical AND of corresponding request and mask bits" "Not masked,Masked" textline " " bitfld.long 0x00 4. " EMPTY ,Logical AND of corresponding request and mask bits" "Not masked,Masked" bitfld.long 0x00 1. " NOT_FULL ,Logical AND of corresponding request and mask bits" "Not masked,Masked" bitfld.long 0x00 0. " TRIGGER ,Logical AND of corresponding request and mask bits" "Not masked,Masked" group.long 0xFC0++0x03 line.long 0x00 "SCB3_INTR_RX,Receiver Interrupt Request Register" setclrfld.long 0x00 11. 0x04 11. 0x00 11. " BREAK_DETECT ,Break detection interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 10. 0x04 10. 0x00 10. " BAUD_DETECT ,LIN baudrate detection interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 9. 0x04 9. 0x00 9. " PARITY_ERROR ,Parity error in received data frame interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 8. 0x04 8. 0x00 8. " FRAME_ERROR ,Frame error in received data frame interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 7. 0x04 7. 0x00 7. " BLOCKED ,AHB-Lite read transfer access to the EZ memory interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 6. 0x04 6. 0x00 6. " UNDERFLOW ,Attempt to read from an empty RX FIFO interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 5. 0x04 5. 0x00 5. " OVERFLOW ,Attempt to write to a full RX FIFO interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 3. 0x04 3. 0x00 3. " FULL ,RX FIFO is full interrupt" "No interrupt,Interrupt" setclrfld.long 0x00 2. 0x04 2. 0x00 2. " NOT_EMPTY ,RX FIFO is not empty interrupt" "No interrupt,Interrupt" textline " " setclrfld.long 0x00 0. 0x04 0. 0x00 0. " TRIGGER ,More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in SCB_RX_FIFO_CTL interrupt" "No interrupt,Interrupt" group.long 0xFC8++0x03 line.long 0x00 "SCB3_INTR_RX_MASK,Receiver Interrupt Mask Register" bitfld.long 0x00 11. " BREAK_DETECT ,BREAK_DETECT interrupt mask" "Not masked,Masked" bitfld.long 0x00 10. " BAUD_DETECT ,BAUD_DETECT interrupt mask" "Not masked,Masked" bitfld.long 0x00 9. " PARITY_ERROR ,PARITY_ERROR interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 8. " FRAME_ERROR ,FRAME_ERROR interrupt mask" "Not masked,Masked" bitfld.long 0x00 7. " BLOCKED ,BLOCKED interrupt mask" "Not masked,Masked" bitfld.long 0x00 6. " UNDERFLOW ,UNDERFLOW interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 5. " OVERFLOW ,OVERFLOW interrupt mask" "Not masked,Masked" bitfld.long 0x00 3. " FULL ,FULL interrupt mask" "Not masked,Masked" bitfld.long 0x00 2. " NOT_EMPTY ,NOT_EMPTY interrupt mask" "Not masked,Masked" textline " " bitfld.long 0x00 0. " TRIGGER ,TRIGGER interrupt mask" "Not masked,Masked" rgroup.long 0xFCC++0x03 line.long 0x00 "SCB3_INTR_RX_MASKED,Receiver Interrupt Masked Request Register" bitfld.long 0x00 11. " BREAK_DETECT ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 10. " BAUD_DETECT ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 9. " PARITY_ERROR ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" textline " " bitfld.long 0x00 8. " FRAME_ERROR ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 7. " BLOCKED ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 6. " UNDERFLOW ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" textline " " bitfld.long 0x00 5. " OVERFLOW ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 3. " FULL ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" bitfld.long 0x00 2. " NOT_EMPTY ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " TRIGGER ,Logical AND of corresponding request and mask bits" "No interrupt,Interrupt" width 0x0B tree.end endif tree.end tree "SFLASH (Supervisory Flash registers)" base ad:0x0FFFF000 width 35. tree "SFLASH_PROT_ROW" group.byte 0x0++0x00 line.byte 0x00 "SFLASH_PROT_ROW0,Per Page Write Protection 0" group.byte 0x1++0x00 line.byte 0x00 "SFLASH_PROT_ROW1,Per Page Write Protection 1" group.byte 0x2++0x00 line.byte 0x00 "SFLASH_PROT_ROW2,Per Page Write Protection 2" group.byte 0x3++0x00 line.byte 0x00 "SFLASH_PROT_ROW3,Per Page Write Protection 3" group.byte 0x4++0x00 line.byte 0x00 "SFLASH_PROT_ROW4,Per Page Write Protection 4" group.byte 0x5++0x00 line.byte 0x00 "SFLASH_PROT_ROW5,Per Page Write Protection 5" group.byte 0x6++0x00 line.byte 0x00 "SFLASH_PROT_ROW6,Per Page Write Protection 6" group.byte 0x7++0x00 line.byte 0x00 "SFLASH_PROT_ROW7,Per Page Write Protection 7" group.byte 0x8++0x00 line.byte 0x00 "SFLASH_PROT_ROW8,Per Page Write Protection 8" group.byte 0x9++0x00 line.byte 0x00 "SFLASH_PROT_ROW9,Per Page Write Protection 9" group.byte 0xA++0x00 line.byte 0x00 "SFLASH_PROT_ROW10,Per Page Write Protection 10" group.byte 0xB++0x00 line.byte 0x00 "SFLASH_PROT_ROW11,Per Page Write Protection 11" group.byte 0xC++0x00 line.byte 0x00 "SFLASH_PROT_ROW12,Per Page Write Protection 12" group.byte 0xD++0x00 line.byte 0x00 "SFLASH_PROT_ROW13,Per Page Write Protection 13" group.byte 0xE++0x00 line.byte 0x00 "SFLASH_PROT_ROW14,Per Page Write Protection 14" group.byte 0xF++0x00 line.byte 0x00 "SFLASH_PROT_ROW15,Per Page Write Protection 15" group.byte 0x10++0x00 line.byte 0x00 "SFLASH_PROT_ROW16,Per Page Write Protection 16" group.byte 0x11++0x00 line.byte 0x00 "SFLASH_PROT_ROW17,Per Page Write Protection 17" group.byte 0x12++0x00 line.byte 0x00 "SFLASH_PROT_ROW18,Per Page Write Protection 18" group.byte 0x13++0x00 line.byte 0x00 "SFLASH_PROT_ROW19,Per Page Write Protection 19" group.byte 0x14++0x00 line.byte 0x00 "SFLASH_PROT_ROW20,Per Page Write Protection 20" group.byte 0x15++0x00 line.byte 0x00 "SFLASH_PROT_ROW21,Per Page Write Protection 21" group.byte 0x16++0x00 line.byte 0x00 "SFLASH_PROT_ROW22,Per Page Write Protection 22" group.byte 0x17++0x00 line.byte 0x00 "SFLASH_PROT_ROW23,Per Page Write Protection 23" group.byte 0x18++0x00 line.byte 0x00 "SFLASH_PROT_ROW24,Per Page Write Protection 24" group.byte 0x19++0x00 line.byte 0x00 "SFLASH_PROT_ROW25,Per Page Write Protection 25" group.byte 0x1A++0x00 line.byte 0x00 "SFLASH_PROT_ROW26,Per Page Write Protection 26" group.byte 0x1B++0x00 line.byte 0x00 "SFLASH_PROT_ROW27,Per Page Write Protection 27" group.byte 0x1C++0x00 line.byte 0x00 "SFLASH_PROT_ROW28,Per Page Write Protection 28" group.byte 0x1D++0x00 line.byte 0x00 "SFLASH_PROT_ROW29,Per Page Write Protection 29" group.byte 0x1E++0x00 line.byte 0x00 "SFLASH_PROT_ROW30,Per Page Write Protection 30" group.byte 0x1F++0x00 line.byte 0x00 "SFLASH_PROT_ROW31,Per Page Write Protection 31" group.byte 0x20++0x00 line.byte 0x00 "SFLASH_PROT_ROW32,Per Page Write Protection 32" group.byte 0x21++0x00 line.byte 0x00 "SFLASH_PROT_ROW33,Per Page Write Protection 33" group.byte 0x22++0x00 line.byte 0x00 "SFLASH_PROT_ROW34,Per Page Write Protection 34" group.byte 0x23++0x00 line.byte 0x00 "SFLASH_PROT_ROW35,Per Page Write Protection 35" group.byte 0x24++0x00 line.byte 0x00 "SFLASH_PROT_ROW36,Per Page Write Protection 36" group.byte 0x25++0x00 line.byte 0x00 "SFLASH_PROT_ROW37,Per Page Write Protection 37" group.byte 0x26++0x00 line.byte 0x00 "SFLASH_PROT_ROW38,Per Page Write Protection 38" group.byte 0x27++0x00 line.byte 0x00 "SFLASH_PROT_ROW39,Per Page Write Protection 39" group.byte 0x28++0x00 line.byte 0x00 "SFLASH_PROT_ROW40,Per Page Write Protection 40" group.byte 0x29++0x00 line.byte 0x00 "SFLASH_PROT_ROW41,Per Page Write Protection 41" group.byte 0x2A++0x00 line.byte 0x00 "SFLASH_PROT_ROW42,Per Page Write Protection 42" group.byte 0x2B++0x00 line.byte 0x00 "SFLASH_PROT_ROW43,Per Page Write Protection 43" group.byte 0x2C++0x00 line.byte 0x00 "SFLASH_PROT_ROW44,Per Page Write Protection 44" group.byte 0x2D++0x00 line.byte 0x00 "SFLASH_PROT_ROW45,Per Page Write Protection 45" group.byte 0x2E++0x00 line.byte 0x00 "SFLASH_PROT_ROW46,Per Page Write Protection 46" group.byte 0x2F++0x00 line.byte 0x00 "SFLASH_PROT_ROW47,Per Page Write Protection 47" group.byte 0x30++0x00 line.byte 0x00 "SFLASH_PROT_ROW48,Per Page Write Protection 48" group.byte 0x31++0x00 line.byte 0x00 "SFLASH_PROT_ROW49,Per Page Write Protection 49" group.byte 0x32++0x00 line.byte 0x00 "SFLASH_PROT_ROW50,Per Page Write Protection 50" group.byte 0x33++0x00 line.byte 0x00 "SFLASH_PROT_ROW51,Per Page Write Protection 51" group.byte 0x34++0x00 line.byte 0x00 "SFLASH_PROT_ROW52,Per Page Write Protection 52" group.byte 0x35++0x00 line.byte 0x00 "SFLASH_PROT_ROW53,Per Page Write Protection 53" group.byte 0x36++0x00 line.byte 0x00 "SFLASH_PROT_ROW54,Per Page Write Protection 54" group.byte 0x37++0x00 line.byte 0x00 "SFLASH_PROT_ROW55,Per Page Write Protection 55" group.byte 0x38++0x00 line.byte 0x00 "SFLASH_PROT_ROW56,Per Page Write Protection 56" group.byte 0x39++0x00 line.byte 0x00 "SFLASH_PROT_ROW57,Per Page Write Protection 57" group.byte 0x3A++0x00 line.byte 0x00 "SFLASH_PROT_ROW58,Per Page Write Protection 58" group.byte 0x3B++0x00 line.byte 0x00 "SFLASH_PROT_ROW59,Per Page Write Protection 59" group.byte 0x3C++0x00 line.byte 0x00 "SFLASH_PROT_ROW60,Per Page Write Protection 60" group.byte 0x3D++0x00 line.byte 0x00 "SFLASH_PROT_ROW61,Per Page Write Protection 61" group.byte 0x3E++0x00 line.byte 0x00 "SFLASH_PROT_ROW62,Per Page Write Protection 62" group.byte 0x3F++0x00 line.byte 0x00 "SFLASH_PROT_ROW63,Per Page Write Protection 63" tree.end textline " " group.byte 0xFF++0x00 line.byte 0x00 "SFLASH_PROT_PROTECTION,Protection Level" bitfld.byte 0x00 0.--1. " PROT_LEVEL ,Current Protection Mode" "OPEN,VIRGIN,PROTECTED,KILL" tree "SFLASH_AV_PAIRS_8B" group.byte 0x100++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B0,8b Addr/Value pair Section 0" group.byte 0x101++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B1,8b Addr/Value pair Section 1" group.byte 0x102++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B2,8b Addr/Value pair Section 2" group.byte 0x103++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B3,8b Addr/Value pair Section 3" group.byte 0x104++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B4,8b Addr/Value pair Section 4" group.byte 0x105++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B5,8b Addr/Value pair Section 5" group.byte 0x106++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B6,8b Addr/Value pair Section 6" group.byte 0x107++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B7,8b Addr/Value pair Section 7" group.byte 0x108++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B8,8b Addr/Value pair Section 8" group.byte 0x109++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B9,8b Addr/Value pair Section 9" group.byte 0x10A++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B10,8b Addr/Value pair Section 10" group.byte 0x10B++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B11,8b Addr/Value pair Section 11" group.byte 0x10C++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B12,8b Addr/Value pair Section 12" group.byte 0x10D++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B13,8b Addr/Value pair Section 13" group.byte 0x10E++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B14,8b Addr/Value pair Section 14" group.byte 0x10F++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B15,8b Addr/Value pair Section 15" group.byte 0x110++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B16,8b Addr/Value pair Section 16" group.byte 0x111++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B17,8b Addr/Value pair Section 17" group.byte 0x112++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B18,8b Addr/Value pair Section 18" group.byte 0x113++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B19,8b Addr/Value pair Section 19" group.byte 0x114++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B20,8b Addr/Value pair Section 20" group.byte 0x115++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B21,8b Addr/Value pair Section 21" group.byte 0x116++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B22,8b Addr/Value pair Section 22" group.byte 0x117++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B23,8b Addr/Value pair Section 23" group.byte 0x118++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B24,8b Addr/Value pair Section 24" group.byte 0x119++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B25,8b Addr/Value pair Section 25" group.byte 0x11A++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B26,8b Addr/Value pair Section 26" group.byte 0x11B++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B27,8b Addr/Value pair Section 27" group.byte 0x11C++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B28,8b Addr/Value pair Section 28" group.byte 0x11D++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B29,8b Addr/Value pair Section 29" group.byte 0x11E++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B30,8b Addr/Value pair Section 30" group.byte 0x11F++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B31,8b Addr/Value pair Section 31" group.byte 0x120++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B32,8b Addr/Value pair Section 32" group.byte 0x121++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B33,8b Addr/Value pair Section 33" group.byte 0x122++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B34,8b Addr/Value pair Section 34" group.byte 0x123++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B35,8b Addr/Value pair Section 35" group.byte 0x124++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B36,8b Addr/Value pair Section 36" group.byte 0x125++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B37,8b Addr/Value pair Section 37" group.byte 0x126++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B38,8b Addr/Value pair Section 38" group.byte 0x127++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B39,8b Addr/Value pair Section 39" group.byte 0x128++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B40,8b Addr/Value pair Section 40" group.byte 0x129++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B41,8b Addr/Value pair Section 41" group.byte 0x12A++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B42,8b Addr/Value pair Section 42" group.byte 0x12B++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B43,8b Addr/Value pair Section 43" group.byte 0x12C++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B44,8b Addr/Value pair Section 44" group.byte 0x12D++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B45,8b Addr/Value pair Section 45" group.byte 0x12E++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B46,8b Addr/Value pair Section 46" group.byte 0x12F++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B47,8b Addr/Value pair Section 47" group.byte 0x130++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B48,8b Addr/Value pair Section 48" group.byte 0x131++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B49,8b Addr/Value pair Section 49" group.byte 0x132++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B50,8b Addr/Value pair Section 50" group.byte 0x133++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B51,8b Addr/Value pair Section 51" group.byte 0x134++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B52,8b Addr/Value pair Section 52" group.byte 0x135++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B53,8b Addr/Value pair Section 53" group.byte 0x136++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B54,8b Addr/Value pair Section 54" group.byte 0x137++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B55,8b Addr/Value pair Section 55" group.byte 0x138++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B56,8b Addr/Value pair Section 56" group.byte 0x139++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B57,8b Addr/Value pair Section 57" group.byte 0x13A++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B58,8b Addr/Value pair Section 58" group.byte 0x13B++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B59,8b Addr/Value pair Section 59" group.byte 0x13C++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B60,8b Addr/Value pair Section 60" group.byte 0x13D++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B61,8b Addr/Value pair Section 61" group.byte 0x13E++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B62,8b Addr/Value pair Section 62" group.byte 0x13F++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B63,8b Addr/Value pair Section 63" group.byte 0x140++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B64,8b Addr/Value pair Section 64" group.byte 0x141++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B65,8b Addr/Value pair Section 65" group.byte 0x142++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B66,8b Addr/Value pair Section 66" group.byte 0x143++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B67,8b Addr/Value pair Section 67" group.byte 0x144++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B68,8b Addr/Value pair Section 68" group.byte 0x145++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B69,8b Addr/Value pair Section 69" group.byte 0x146++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B70,8b Addr/Value pair Section 70" group.byte 0x147++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B71,8b Addr/Value pair Section 71" group.byte 0x148++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B72,8b Addr/Value pair Section 72" group.byte 0x149++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B73,8b Addr/Value pair Section 73" group.byte 0x14A++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B74,8b Addr/Value pair Section 74" group.byte 0x14B++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B75,8b Addr/Value pair Section 75" group.byte 0x14C++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B76,8b Addr/Value pair Section 76" group.byte 0x14D++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B77,8b Addr/Value pair Section 77" group.byte 0x14E++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B78,8b Addr/Value pair Section 78" group.byte 0x14F++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B79,8b Addr/Value pair Section 79" group.byte 0x150++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B80,8b Addr/Value pair Section 80" group.byte 0x151++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B81,8b Addr/Value pair Section 81" group.byte 0x152++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B82,8b Addr/Value pair Section 82" group.byte 0x153++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B83,8b Addr/Value pair Section 83" group.byte 0x154++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B84,8b Addr/Value pair Section 84" group.byte 0x155++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B85,8b Addr/Value pair Section 85" group.byte 0x156++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B86,8b Addr/Value pair Section 86" group.byte 0x157++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B87,8b Addr/Value pair Section 87" group.byte 0x158++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B88,8b Addr/Value pair Section 88" group.byte 0x159++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B89,8b Addr/Value pair Section 89" group.byte 0x15A++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B90,8b Addr/Value pair Section 90" group.byte 0x15B++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B91,8b Addr/Value pair Section 91" group.byte 0x15C++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B92,8b Addr/Value pair Section 92" group.byte 0x15D++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B93,8b Addr/Value pair Section 93" group.byte 0x15E++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B94,8b Addr/Value pair Section 94" group.byte 0x15F++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B95,8b Addr/Value pair Section 95" group.byte 0x160++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B96,8b Addr/Value pair Section 96" group.byte 0x161++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B97,8b Addr/Value pair Section 97" group.byte 0x162++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B98,8b Addr/Value pair Section 98" group.byte 0x163++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B99,8b Addr/Value pair Section 99" group.byte 0x164++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B100,8b Addr/Value pair Section 100" group.byte 0x165++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B101,8b Addr/Value pair Section 101" group.byte 0x166++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B102,8b Addr/Value pair Section 102" group.byte 0x167++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B103,8b Addr/Value pair Section 103" group.byte 0x168++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B104,8b Addr/Value pair Section 104" group.byte 0x169++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B105,8b Addr/Value pair Section 105" group.byte 0x16A++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B106,8b Addr/Value pair Section 106" group.byte 0x16B++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B107,8b Addr/Value pair Section 107" group.byte 0x16C++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B108,8b Addr/Value pair Section 108" group.byte 0x16D++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B109,8b Addr/Value pair Section 109" group.byte 0x16E++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B110,8b Addr/Value pair Section 110" group.byte 0x16F++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B111,8b Addr/Value pair Section 111" group.byte 0x170++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B112,8b Addr/Value pair Section 112" group.byte 0x171++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B113,8b Addr/Value pair Section 113" group.byte 0x172++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B114,8b Addr/Value pair Section 114" group.byte 0x173++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B115,8b Addr/Value pair Section 115" group.byte 0x174++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B116,8b Addr/Value pair Section 116" group.byte 0x175++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B117,8b Addr/Value pair Section 117" group.byte 0x176++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B118,8b Addr/Value pair Section 118" group.byte 0x177++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B119,8b Addr/Value pair Section 119" group.byte 0x178++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B120,8b Addr/Value pair Section 120" group.byte 0x179++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B121,8b Addr/Value pair Section 121" group.byte 0x17A++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B122,8b Addr/Value pair Section 122" group.byte 0x17B++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B123,8b Addr/Value pair Section 123" group.byte 0x17C++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B124,8b Addr/Value pair Section 124" group.byte 0x17D++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B125,8b Addr/Value pair Section 125" group.byte 0x17E++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B126,8b Addr/Value pair Section 126" group.byte 0x17F++0x00 line.byte 0x00 "SFLASH_AV_PAIRS_8B127,8b Addr/Value pair Section 127" tree.end textline " " tree "SFLASH_AV_PAIRS_32B" group.long 0x200++0x03 line.long 0x00 "SFLASH_AV_PAIRS_32B0,32b Addr/Value pair Section 0" group.long 0x204++0x03 line.long 0x00 "SFLASH_AV_PAIRS_32B1,32b Addr/Value pair Section 1" group.long 0x208++0x03 line.long 0x00 "SFLASH_AV_PAIRS_32B2,32b Addr/Value pair Section 2" group.long 0x20C++0x03 line.long 0x00 "SFLASH_AV_PAIRS_32B3,32b Addr/Value pair Section 3" group.long 0x210++0x03 line.long 0x00 "SFLASH_AV_PAIRS_32B4,32b Addr/Value pair Section 4" group.long 0x214++0x03 line.long 0x00 "SFLASH_AV_PAIRS_32B5,32b Addr/Value pair Section 5" group.long 0x218++0x03 line.long 0x00 "SFLASH_AV_PAIRS_32B6,32b Addr/Value pair Section 6" group.long 0x21C++0x03 line.long 0x00 "SFLASH_AV_PAIRS_32B7,32b Addr/Value pair Section 7" group.long 0x220++0x03 line.long 0x00 "SFLASH_AV_PAIRS_32B8,32b Addr/Value pair Section 8" group.long 0x224++0x03 line.long 0x00 "SFLASH_AV_PAIRS_32B9,32b Addr/Value pair Section 9" group.long 0x228++0x03 line.long 0x00 "SFLASH_AV_PAIRS_32B10,32b Addr/Value pair Section 10" group.long 0x22C++0x03 line.long 0x00 "SFLASH_AV_PAIRS_32B11,32b Addr/Value pair Section 11" group.long 0x230++0x03 line.long 0x00 "SFLASH_AV_PAIRS_32B12,32b Addr/Value pair Section 12" group.long 0x234++0x03 line.long 0x00 "SFLASH_AV_PAIRS_32B13,32b Addr/Value pair Section 13" group.long 0x238++0x03 line.long 0x00 "SFLASH_AV_PAIRS_32B14,32b Addr/Value pair Section 14" group.long 0x23C++0x03 line.long 0x00 "SFLASH_AV_PAIRS_32B15,32b Addr/Value pair Section 15" tree.end sif cpuis("CY8C4*-BL*") group.long 0x240++0x03 line.long 0x00 "SFLASH_CPUSS_WOUNDING,CPUSS Wounding Register" endif group.long 0x244++0x03 line.long 0x00 "SFLASH_SILICON_ID,Silicon ID" hexmask.long.word 0x00 0.--15. 1. " ID ,Silicon ID" group.word 0x248++0x0B line.word 0x00 "SFLASH_CPUSS_PRIV_RAM,RAM Privileged Limit" hexmask.word 0x00 0.--8. 1. " RAM_PROT_LIMIT ,Indicates the limit where the privileged area of SRAM starts in increments of 256 Bytes" line.word 0x02 "SFLASH_CPUSS_PRIV_ROM_BROM,Boot ROM Privileged Limit" hexmask.word.byte 0x02 0.--7. 1. " BROM_PROT_LIMIT ,Indicates the limit where the privileged area of the Boot ROM partition starts in increments of 256 Bytes" line.word 0x04 "SFLASH_CPUSS_PRIV_FLASH,Flash Privileged Limit" hexmask.word 0x04 0.--10. 1. " FLASH_PROT_LIMIT ,Indicates the limit where the privileged area of flash starts in increments of 256 Bytes" line.word 0x06 "SFLASH_CPUSS_PRIV_ROM_SROM,System ROM Privileged Limit" hexmask.word 0x06 0.--9. 1. " SROM_PROT_LIMIT ,Indicates the limit where the privileged area of System ROM partition starts in increments of 256 Bytes" line.word 0x08 "SFLASH_HIB_KEY_DELAY,Hibernate wakeup value for PWR_KEY_DELAY" hexmask.word 0x08 0.--9. 1. " WAKEUP_HOLDOFF ,Delay to wait for references to settle on wakeup from hibernate/deepsleep" line.word 0x0A "SFLASH_DPSLP_KEY_DELAY,DeepSleep wakeup value for PWR_KEY_DELAY" hexmask.word 0x0A 0.--9. 1. " WAKEUP_HOLDOFF ,Delay to wait for references to settle on wakeup from hibernate/deepsleep" group.byte 0x254++0x01 line.byte 0x00 "SFLASH_SWD_CONFIG,SWD pinout selector" bitfld.byte 0x00 0. " SWD_SELECT ,SWD pinout select bit" "Primary,Alternate" line.byte 0x01 "SFLASH_INITIAL_SPCIF_TRIM_M1_DAC0,FLASH IDAC trim used during boot" bitfld.byte 0x01 5.--7. " SLOPE ,See SPCIF_TRIM1" "0,1,2,3,4,5,6,7" bitfld.byte 0x01 0.--4. " IDAC ,See SPCIF_TRIM1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x258++0x07 line.long 0x00 "SFLASH_SWD_LISTEN,Listen Window Length" line.long 0x04 "SFLASH_FLASH_START,Flash Image Start Address" group.byte 0x260++0x03 line.byte 0x00 "SFLASH_CSD_TRIM1_HVIDAC,CSD Trim Data for HVIDAC operation" line.byte 0x01 "SFLASH_CSD_TRIM2_HVIDAC,CSD Trim Data for HVIDAC operation" line.byte 0x02 "SFLASH_CSD_TRIM1_CSD,CSD Trim Data for CSD operation" line.byte 0x03 "SFLASH_CSD_TRIM2_CSD,CSD Trim Data for CSD operation" group.word 0x264++0x03 line.word 0x00 "SFLASH_SAR_TEMP_MULTIPLIER,SAR Temperature Sensor Multiplication Factor" line.word 0x02 "SFLASH_SAR_TEMP_OFFSET,SAR Temperature Sensor Offset" group.byte 0x269++0x14 line.byte 0x00 "SFLASH_SKIP_CHECKSUM,Checksum Skip Option Register" line.byte 0x01 "SFLASH_PROT_VIRGINKEY0,Virgin Protection Mode Key 0" line.byte 0x02 "SFLASH_PROT_VIRGINKEY1,Virgin Protection Mode Key 1" line.byte 0x03 "SFLASH_PROT_VIRGINKEY2,Virgin Protection Mode Key 2" line.byte 0x04 "SFLASH_PROT_VIRGINKEY3,Virgin Protection Mode Key 3" line.byte 0x05 "SFLASH_PROT_VIRGINKEY4,Virgin Protection Mode Key 4" line.byte 0x06 "SFLASH_PROT_VIRGINKEY5,Virgin Protection Mode Key 5" line.byte 0x07 "SFLASH_PROT_VIRGINKEY6,Virgin Protection Mode Key 6" line.byte 0x08 "SFLASH_PROT_VIRGINKEY7,Virgin Protection Mode Key 7" line.byte 0x09 "SFLASH_DIE_LOT0,Lot Number 0" line.byte 0x0A "SFLASH_DIE_LOT1,Lot Number 1" line.byte 0x0B "SFLASH_DIE_LOT2,Lot Number 2" line.byte 0x0C "SFLASH_DIE_WAFER,Wafer Number" line.byte 0x0D "SFLASH_DIE_X,X Position on Wafer, CRI Pass/Fail Bin" line.byte 0x0E "SFLASH_DIE_Y,Y Position on Wafer, CHI Pass/Fail Bin" line.byte 0x0F "SFLASH_DIE_SORT,Sort1/2/3 Pass/Fail Bin" bitfld.byte 0x0F 5. " ENG_PASS ,ENG Pass Bin" "Failed,Passed" bitfld.byte 0x0F 4. " CHI_PASS ,CHI Pass Bin or Fail Bin" "Failed,Passed" bitfld.byte 0x0F 3. " CRI_PASS ,CRI Pass Bin or Fail Bin" "Failed,Passed" bitfld.byte 0x0F 2. " S3_PASS ,SORT3 Pass Bin or Fail Bin" "Failed,Passed" textline " " bitfld.byte 0x0F 1. " S2_PASS ,SORT2 Pass Bin or Fail Bin" "Failed,Passed" bitfld.byte 0x0F 0. " S1_PASS ,SORT1 Pass Bin or Fail Bin" "Failed,Passed" line.byte 0x10 "SFLASH_DIE_MINOR,Minor Revision Number" sif !cpuis("CY8C4*-BL*") line.byte 0x11 "SFLASH_CSD1_TRIM1_HVIDAC,CSD1 Trim Data for HVIDAC operation" line.byte 0x12 "SFLASH_CSD1_TRIM2_HVIDAC,CSD1 Trim Data for HVIDAC operation" line.byte 0x13 "SFLASH_CSD1_TRIM1_CSD,CSD1 Trim Data for (normal) CSD operation" line.byte 0x14 "SFLASH_CSD1_TRIM2_CSD,CSD1 Trim Data for (normal) CSD operation" endif tree "SFLASH_PE_TE_DATA" group.byte 0x300++0x00 line.byte 0x00 "SFLASH_PE_TE_DATA0,PE/TE Data 0" group.byte 0x301++0x00 line.byte 0x00 "SFLASH_PE_TE_DATA1,PE/TE Data 1" group.byte 0x302++0x00 line.byte 0x00 "SFLASH_PE_TE_DATA2,PE/TE Data 2" group.byte 0x303++0x00 line.byte 0x00 "SFLASH_PE_TE_DATA3,PE/TE Data 3" group.byte 0x304++0x00 line.byte 0x00 "SFLASH_PE_TE_DATA4,PE/TE Data 4" group.byte 0x305++0x00 line.byte 0x00 "SFLASH_PE_TE_DATA5,PE/TE Data 5" group.byte 0x306++0x00 line.byte 0x00 "SFLASH_PE_TE_DATA6,PE/TE Data 6" group.byte 0x307++0x00 line.byte 0x00 "SFLASH_PE_TE_DATA7,PE/TE Data 7" group.byte 0x308++0x00 line.byte 0x00 "SFLASH_PE_TE_DATA8,PE/TE Data 8" group.byte 0x309++0x00 line.byte 0x00 "SFLASH_PE_TE_DATA9,PE/TE Data 9" group.byte 0x30A++0x00 line.byte 0x00 "SFLASH_PE_TE_DATA10,PE/TE Data 10" group.byte 0x30B++0x00 line.byte 0x00 "SFLASH_PE_TE_DATA11,PE/TE Data 11" group.byte 0x30C++0x00 line.byte 0x00 "SFLASH_PE_TE_DATA12,PE/TE Data 12" group.byte 0x30D++0x00 line.byte 0x00 "SFLASH_PE_TE_DATA13,PE/TE Data 13" group.byte 0x30E++0x00 line.byte 0x00 "SFLASH_PE_TE_DATA14,PE/TE Data 14" group.byte 0x30F++0x00 line.byte 0x00 "SFLASH_PE_TE_DATA15,PE/TE Data 15" group.byte 0x310++0x00 line.byte 0x00 "SFLASH_PE_TE_DATA16,PE/TE Data 16" group.byte 0x311++0x00 line.byte 0x00 "SFLASH_PE_TE_DATA17,PE/TE Data 17" group.byte 0x312++0x00 line.byte 0x00 "SFLASH_PE_TE_DATA18,PE/TE Data 18" group.byte 0x313++0x00 line.byte 0x00 "SFLASH_PE_TE_DATA19,PE/TE Data 19" group.byte 0x314++0x00 line.byte 0x00 "SFLASH_PE_TE_DATA20,PE/TE Data 20" group.byte 0x315++0x00 line.byte 0x00 "SFLASH_PE_TE_DATA21,PE/TE Data 21" group.byte 0x316++0x00 line.byte 0x00 "SFLASH_PE_TE_DATA22,PE/TE Data 22" group.byte 0x317++0x00 line.byte 0x00 "SFLASH_PE_TE_DATA23,PE/TE Data 23" group.byte 0x318++0x00 line.byte 0x00 "SFLASH_PE_TE_DATA24,PE/TE Data 24" group.byte 0x319++0x00 line.byte 0x00 "SFLASH_PE_TE_DATA25,PE/TE Data 25" group.byte 0x31A++0x00 line.byte 0x00 "SFLASH_PE_TE_DATA26,PE/TE Data 26" group.byte 0x31B++0x00 line.byte 0x00 "SFLASH_PE_TE_DATA27,PE/TE Data 27" group.byte 0x31C++0x00 line.byte 0x00 "SFLASH_PE_TE_DATA28,PE/TE Data 28" group.byte 0x31D++0x00 line.byte 0x00 "SFLASH_PE_TE_DATA29,PE/TE Data 29" group.byte 0x31E++0x00 line.byte 0x00 "SFLASH_PE_TE_DATA30,PE/TE Data 30" group.byte 0x31F++0x00 line.byte 0x00 "SFLASH_PE_TE_DATA31,PE/TE Data 31" tree.end textline " " group.long 0x320++0x1B line.long 0x00 "SFLASH_PP,Preprogram Settings" bitfld.long 0x00 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x00 0.--23. 1. " PERIOD ,Period of timer in clk_spcif_timer ticks" line.long 0x04 "SFLASH_E,Erase Settings" bitfld.long 0x04 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x04 0.--23. 1. " PERIOD ,Period of timer in clk_spcif_timer ticks" line.long 0x08 "SFLASH_P,Program Settings" bitfld.long 0x08 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x08 0.--23. 1. " PERIOD ,Period of timer in clk_spcif_timer ticks" line.long 0x0C "SFLASH_EA_E,Erase All - Erase Settings" bitfld.long 0x0C 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0C 0.--23. 1. " PERIOD ,Period of timer in clk_spcif_timer ticks" line.long 0x10 "SFLASH_EA_P,Erase All - Program Settings" bitfld.long 0x10 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x10 0.--23. 1. " PERIOD ,Period of timer in clk_spcif_timer ticks" line.long 0x14 "SFLASH_ES_E,Erase Sector - Erase Settings" bitfld.long 0x14 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x14 0.--23. 1. " PERIOD ,Period of timer in clk_spcif_timer ticks" line.long 0x18 "SFLASH_ES_P_EO,Erase Sector - Program EO Settings" bitfld.long 0x18 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x18 0.--23. 1. " PERIOD ,Period of timer in clk_spcif_timer ticks" group.byte 0x33C++0x11 line.byte 0x00 "SFLASH_E_VCTAT,Bandgap Trim Register" bitfld.byte 0x00 6. " VCTAT_ENABLE ,Enable VCTAT block" "Disabled,Enabled" bitfld.byte 0x00 4.--5. " VCTAT_VOLTAGE ,Output voltage absolute trim" "0,1,2,3" bitfld.byte 0x00 0.--3. " VCTAT_SLOPE ,Output slope setting controls" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.byte 0x01 "SFLASH_P_VCTAT,Bandgap Trim Register" bitfld.byte 0x01 6. " VCTAT_ENABLE ,Enable VCTAT block" "Disabled,Enabled" bitfld.byte 0x01 4.--5. " VCTAT_VOLTAGE ,Output voltage absolute trim" "0,1,2,3" bitfld.byte 0x01 0.--3. " VCTAT_SLOPE ,Output slope setting controls" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.byte 0x02 "SFLASH_IMO_TRIM_USBMODE_24,USB IMO TRIM 24MHz" line.byte 0x03 "SFLASH_IMO_TRIM_USBMODE_48,USB IMO TRIM 48MHz" line.byte 0x04 "SFLASH_IMO_MAXF0,Max frequency for trim pair" bitfld.byte 0x04 0.--5. " MAXFREQ ,Max frequency at which IMO_ABS/TMPCO3 is valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.byte 0x05 "SFLASH_IMO_ABS0,Value for PWR_BG_TRIM4" bitfld.byte 0x05 0.--5. " ABS_TRIM_IMO ,MO-irefgen output current magnitude trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.byte 0x06 "SFLASH_IMO_TMPCO0,Value for PWR_BG_TRIM5" bitfld.byte 0x06 0.--5. " TMPCO_TRIM_IMO ,IMO-irefgen output current temperature co-efficient trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.byte 0x07 "SFLASH_IMO_MAXF1,Max frequency for trim pair" bitfld.byte 0x07 0.--5. " ABS_TRIM_IMO ,IMO-irefgen output current magnitude trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.byte 0x08 "SFLASH_IMO_ABS1,Value for PWR_BG_TRIM4" bitfld.byte 0x08 0.--5. " ABS_TRIM_IMO ,IMO-irefgen output current magnitude trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.byte 0x09 "SFLASH_IMO_TMPCO1,Value for PWR_BG_TRIM5" bitfld.byte 0x09 0.--5. " TMPCO_TRIM_IMO ,IMO-irefgen output current temperature co-efficient trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.byte 0x0A "SFLASH_IMO_MAXF2,Max frequency for trim pair" bitfld.byte 0x0A 0.--5. " MAXFREQ ,Max frequency at which IMO_ABS/TMPCO3 is valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.byte 0x0B "SFLASH_IMO_ABS2,Value for PWR_BG_TRIM4" bitfld.byte 0x0B 0.--5. " ABS_TRIM_IMO ,IMO-irefgen output current magnitude trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.byte 0x0C "SFLASH_IMO_TMPCO2,Value for PWR_BG_TRIM5" bitfld.byte 0x0C 0.--5. " TMPCO_TRIM_IMO ,IMO-irefgen output current temperature co-efficient trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.byte 0x0D " SFLASH_IMO_MAXF3,Max frequency for trim pair" bitfld.byte 0x0D 0.--5. " MAXFREQ ,Max frequency at which IMO_ABS/TMPCO3 is valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.byte 0x0E "SFLASH_IMO_ABS3,Value for PWR_BG_TRIM4" bitfld.byte 0x0E 0.--5. " ABS_TRIM_IMO ,IMO-irefgen output current magnitude trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.byte 0x0F "SFLASH_IMO_TMPCO3,Value for PWR_BG_TRIM5" bitfld.byte 0x0F 0.--5. " TMPCO_TRIM_IMO ,IMO-irefgen output current temperature co-efficient trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.byte 0x10 "SFLASH_IMO_ABS4,Value for PWR_BG_TRIM4" bitfld.byte 0x10 0.--5. " ABS_TRIM_IMO ,IMO-irefgen output current magnitude trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.byte 0x11 "SFLASH_IMO_TMPCO4,Value for PWR_BG_TRIM5" bitfld.byte 0x11 0.--5. " TMPCO_TRIM_IMO ,IMO-irefgen output current temperature co-efficient trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" tree "SFLASH_IMO_TRIM" group.byte 0x350++0x00 line.byte 0x00 "SFLASH_IMO_TRIM0,IMO Trim Register 0" group.byte 0x351++0x00 line.byte 0x00 "SFLASH_IMO_TRIM1,IMO Trim Register 1" group.byte 0x352++0x00 line.byte 0x00 "SFLASH_IMO_TRIM2,IMO Trim Register 2" group.byte 0x353++0x00 line.byte 0x00 "SFLASH_IMO_TRIM3,IMO Trim Register 3" group.byte 0x354++0x00 line.byte 0x00 "SFLASH_IMO_TRIM4,IMO Trim Register 4" group.byte 0x355++0x00 line.byte 0x00 "SFLASH_IMO_TRIM5,IMO Trim Register 5" group.byte 0x356++0x00 line.byte 0x00 "SFLASH_IMO_TRIM6,IMO Trim Register 6" group.byte 0x357++0x00 line.byte 0x00 "SFLASH_IMO_TRIM7,IMO Trim Register 7" group.byte 0x358++0x00 line.byte 0x00 "SFLASH_IMO_TRIM8,IMO Trim Register 8" group.byte 0x359++0x00 line.byte 0x00 "SFLASH_IMO_TRIM9,IMO Trim Register 9" group.byte 0x35A++0x00 line.byte 0x00 "SFLASH_IMO_TRIM10,IMO Trim Register 10" group.byte 0x35B++0x00 line.byte 0x00 "SFLASH_IMO_TRIM11,IMO Trim Register 11" group.byte 0x35C++0x00 line.byte 0x00 "SFLASH_IMO_TRIM12,IMO Trim Register 12" group.byte 0x35D++0x00 line.byte 0x00 "SFLASH_IMO_TRIM13,IMO Trim Register 13" group.byte 0x35E++0x00 line.byte 0x00 "SFLASH_IMO_TRIM14,IMO Trim Register 14" group.byte 0x35F++0x00 line.byte 0x00 "SFLASH_IMO_TRIM15,IMO Trim Register 15" group.byte 0x360++0x00 line.byte 0x00 "SFLASH_IMO_TRIM16,IMO Trim Register 16" group.byte 0x361++0x00 line.byte 0x00 "SFLASH_IMO_TRIM17,IMO Trim Register 17" group.byte 0x362++0x00 line.byte 0x00 "SFLASH_IMO_TRIM18,IMO Trim Register 18" group.byte 0x363++0x00 line.byte 0x00 "SFLASH_IMO_TRIM19,IMO Trim Register 19" group.byte 0x364++0x00 line.byte 0x00 "SFLASH_IMO_TRIM20,IMO Trim Register 20" group.byte 0x365++0x00 line.byte 0x00 "SFLASH_IMO_TRIM21,IMO Trim Register 21" group.byte 0x366++0x00 line.byte 0x00 "SFLASH_IMO_TRIM22,IMO Trim Register 22" group.byte 0x367++0x00 line.byte 0x00 "SFLASH_IMO_TRIM23,IMO Trim Register 23" group.byte 0x368++0x00 line.byte 0x00 "SFLASH_IMO_TRIM24,IMO Trim Register 24" group.byte 0x369++0x00 line.byte 0x00 "SFLASH_IMO_TRIM25,IMO Trim Register 25" group.byte 0x36A++0x00 line.byte 0x00 "SFLASH_IMO_TRIM26,IMO Trim Register 26" group.byte 0x36B++0x00 line.byte 0x00 "SFLASH_IMO_TRIM27,IMO Trim Register 27" group.byte 0x36C++0x00 line.byte 0x00 "SFLASH_IMO_TRIM28,IMO Trim Register 28" group.byte 0x36D++0x00 line.byte 0x00 "SFLASH_IMO_TRIM29,IMO Trim Register 29" group.byte 0x36E++0x00 line.byte 0x00 "SFLASH_IMO_TRIM30,IMO Trim Register 30" group.byte 0x36F++0x00 line.byte 0x00 "SFLASH_IMO_TRIM31,IMO Trim Register 31" group.byte 0x370++0x00 line.byte 0x00 "SFLASH_IMO_TRIM32,IMO Trim Register 32" group.byte 0x371++0x00 line.byte 0x00 "SFLASH_IMO_TRIM33,IMO Trim Register 33" group.byte 0x372++0x00 line.byte 0x00 "SFLASH_IMO_TRIM34,IMO Trim Register 34" group.byte 0x373++0x00 line.byte 0x00 "SFLASH_IMO_TRIM35,IMO Trim Register 35" group.byte 0x374++0x00 line.byte 0x00 "SFLASH_IMO_TRIM36,IMO Trim Register 36" group.byte 0x375++0x00 line.byte 0x00 "SFLASH_IMO_TRIM37,IMO Trim Register 37" group.byte 0x376++0x00 line.byte 0x00 "SFLASH_IMO_TRIM38,IMO Trim Register 38" group.byte 0x377++0x00 line.byte 0x00 "SFLASH_IMO_TRIM39,IMO Trim Register 39" group.byte 0x378++0x00 line.byte 0x00 "SFLASH_IMO_TRIM40,IMO Trim Register 40" group.byte 0x379++0x00 line.byte 0x00 "SFLASH_IMO_TRIM41,IMO Trim Register 41" group.byte 0x37A++0x00 line.byte 0x00 "SFLASH_IMO_TRIM42,IMO Trim Register 42" group.byte 0x37B++0x00 line.byte 0x00 "SFLASH_IMO_TRIM43,IMO Trim Register 43" group.byte 0x37C++0x00 line.byte 0x00 "SFLASH_IMO_TRIM44,IMO Trim Register 44" group.byte 0x37D++0x00 line.byte 0x00 "SFLASH_IMO_TRIM45,IMO Trim Register 45" tree.end textline " " group.word 0x3FE++0x01 line.word 0x00 "SFLASH_CHECKSUM,Boot Checksum" tree "SFLASH_MACRO_0_FREE_SFLASH" sif cpuis("CY8C4*-BL*") group.byte 0x400++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH0,Uncommitted Supervisorly Flash in Macro 0" group.byte 0x401++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1,Uncommitted Supervisorly Flash in Macro 1" group.byte 0x402++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH2,Uncommitted Supervisorly Flash in Macro 2" group.byte 0x403++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH3,Uncommitted Supervisorly Flash in Macro 3" group.byte 0x404++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH4,Uncommitted Supervisorly Flash in Macro 4" group.byte 0x405++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH5,Uncommitted Supervisorly Flash in Macro 5" group.byte 0x406++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH6,Uncommitted Supervisorly Flash in Macro 6" group.byte 0x407++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH7,Uncommitted Supervisorly Flash in Macro 7" group.byte 0x408++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH8,Uncommitted Supervisorly Flash in Macro 8" group.byte 0x409++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH9,Uncommitted Supervisorly Flash in Macro 9" group.byte 0x40A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH10,Uncommitted Supervisorly Flash in Macro 10" group.byte 0x40B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH11,Uncommitted Supervisorly Flash in Macro 11" group.byte 0x40C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH12,Uncommitted Supervisorly Flash in Macro 12" group.byte 0x40D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH13,Uncommitted Supervisorly Flash in Macro 13" group.byte 0x40E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH14,Uncommitted Supervisorly Flash in Macro 14" group.byte 0x40F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH15,Uncommitted Supervisorly Flash in Macro 15" group.byte 0x410++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH16,Uncommitted Supervisorly Flash in Macro 16" group.byte 0x411++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH17,Uncommitted Supervisorly Flash in Macro 17" group.byte 0x412++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH18,Uncommitted Supervisorly Flash in Macro 18" group.byte 0x413++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH19,Uncommitted Supervisorly Flash in Macro 19" group.byte 0x414++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH20,Uncommitted Supervisorly Flash in Macro 20" group.byte 0x415++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH21,Uncommitted Supervisorly Flash in Macro 21" group.byte 0x416++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH22,Uncommitted Supervisorly Flash in Macro 22" group.byte 0x417++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH23,Uncommitted Supervisorly Flash in Macro 23" group.byte 0x418++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH24,Uncommitted Supervisorly Flash in Macro 24" group.byte 0x419++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH25,Uncommitted Supervisorly Flash in Macro 25" group.byte 0x41A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH26,Uncommitted Supervisorly Flash in Macro 26" group.byte 0x41B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH27,Uncommitted Supervisorly Flash in Macro 27" group.byte 0x41C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH28,Uncommitted Supervisorly Flash in Macro 28" group.byte 0x41D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH29,Uncommitted Supervisorly Flash in Macro 29" group.byte 0x41E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH30,Uncommitted Supervisorly Flash in Macro 30" group.byte 0x41F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH31,Uncommitted Supervisorly Flash in Macro 31" group.byte 0x420++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH32,Uncommitted Supervisorly Flash in Macro 32" group.byte 0x421++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH33,Uncommitted Supervisorly Flash in Macro 33" group.byte 0x422++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH34,Uncommitted Supervisorly Flash in Macro 34" group.byte 0x423++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH35,Uncommitted Supervisorly Flash in Macro 35" group.byte 0x424++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH36,Uncommitted Supervisorly Flash in Macro 36" group.byte 0x425++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH37,Uncommitted Supervisorly Flash in Macro 37" group.byte 0x426++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH38,Uncommitted Supervisorly Flash in Macro 38" group.byte 0x427++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH39,Uncommitted Supervisorly Flash in Macro 39" group.byte 0x428++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH40,Uncommitted Supervisorly Flash in Macro 40" group.byte 0x429++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH41,Uncommitted Supervisorly Flash in Macro 41" group.byte 0x42A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH42,Uncommitted Supervisorly Flash in Macro 42" group.byte 0x42B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH43,Uncommitted Supervisorly Flash in Macro 43" group.byte 0x42C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH44,Uncommitted Supervisorly Flash in Macro 44" group.byte 0x42D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH45,Uncommitted Supervisorly Flash in Macro 45" group.byte 0x42E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH46,Uncommitted Supervisorly Flash in Macro 46" group.byte 0x42F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH47,Uncommitted Supervisorly Flash in Macro 47" group.byte 0x430++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH48,Uncommitted Supervisorly Flash in Macro 48" group.byte 0x431++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH49,Uncommitted Supervisorly Flash in Macro 49" group.byte 0x432++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH50,Uncommitted Supervisorly Flash in Macro 50" group.byte 0x433++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH51,Uncommitted Supervisorly Flash in Macro 51" group.byte 0x434++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH52,Uncommitted Supervisorly Flash in Macro 52" group.byte 0x435++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH53,Uncommitted Supervisorly Flash in Macro 53" group.byte 0x436++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH54,Uncommitted Supervisorly Flash in Macro 54" group.byte 0x437++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH55,Uncommitted Supervisorly Flash in Macro 55" group.byte 0x438++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH56,Uncommitted Supervisorly Flash in Macro 56" group.byte 0x439++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH57,Uncommitted Supervisorly Flash in Macro 57" group.byte 0x43A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH58,Uncommitted Supervisorly Flash in Macro 58" group.byte 0x43B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH59,Uncommitted Supervisorly Flash in Macro 59" group.byte 0x43C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH60,Uncommitted Supervisorly Flash in Macro 60" group.byte 0x43D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH61,Uncommitted Supervisorly Flash in Macro 61" group.byte 0x43E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH62,Uncommitted Supervisorly Flash in Macro 62" group.byte 0x43F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH63,Uncommitted Supervisorly Flash in Macro 63" group.byte 0x440++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH64,Uncommitted Supervisorly Flash in Macro 64" group.byte 0x441++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH65,Uncommitted Supervisorly Flash in Macro 65" group.byte 0x442++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH66,Uncommitted Supervisorly Flash in Macro 66" group.byte 0x443++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH67,Uncommitted Supervisorly Flash in Macro 67" group.byte 0x444++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH68,Uncommitted Supervisorly Flash in Macro 68" group.byte 0x445++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH69,Uncommitted Supervisorly Flash in Macro 69" group.byte 0x446++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH70,Uncommitted Supervisorly Flash in Macro 70" group.byte 0x447++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH71,Uncommitted Supervisorly Flash in Macro 71" group.byte 0x448++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH72,Uncommitted Supervisorly Flash in Macro 72" group.byte 0x449++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH73,Uncommitted Supervisorly Flash in Macro 73" group.byte 0x44A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH74,Uncommitted Supervisorly Flash in Macro 74" group.byte 0x44B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH75,Uncommitted Supervisorly Flash in Macro 75" group.byte 0x44C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH76,Uncommitted Supervisorly Flash in Macro 76" group.byte 0x44D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH77,Uncommitted Supervisorly Flash in Macro 77" group.byte 0x44E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH78,Uncommitted Supervisorly Flash in Macro 78" group.byte 0x44F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH79,Uncommitted Supervisorly Flash in Macro 79" group.byte 0x450++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH80,Uncommitted Supervisorly Flash in Macro 80" group.byte 0x451++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH81,Uncommitted Supervisorly Flash in Macro 81" group.byte 0x452++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH82,Uncommitted Supervisorly Flash in Macro 82" group.byte 0x453++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH83,Uncommitted Supervisorly Flash in Macro 83" group.byte 0x454++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH84,Uncommitted Supervisorly Flash in Macro 84" group.byte 0x455++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH85,Uncommitted Supervisorly Flash in Macro 85" group.byte 0x456++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH86,Uncommitted Supervisorly Flash in Macro 86" group.byte 0x457++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH87,Uncommitted Supervisorly Flash in Macro 87" group.byte 0x458++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH88,Uncommitted Supervisorly Flash in Macro 88" group.byte 0x459++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH89,Uncommitted Supervisorly Flash in Macro 89" group.byte 0x45A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH90,Uncommitted Supervisorly Flash in Macro 90" group.byte 0x45B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH91,Uncommitted Supervisorly Flash in Macro 91" group.byte 0x45C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH92,Uncommitted Supervisorly Flash in Macro 92" group.byte 0x45D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH93,Uncommitted Supervisorly Flash in Macro 93" group.byte 0x45E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH94,Uncommitted Supervisorly Flash in Macro 94" group.byte 0x45F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH95,Uncommitted Supervisorly Flash in Macro 95" group.byte 0x460++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH96,Uncommitted Supervisorly Flash in Macro 96" group.byte 0x461++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH97,Uncommitted Supervisorly Flash in Macro 97" group.byte 0x462++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH98,Uncommitted Supervisorly Flash in Macro 98" group.byte 0x463++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH99,Uncommitted Supervisorly Flash in Macro 99" group.byte 0x464++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH100,Uncommitted Supervisorly Flash in Macro 100" group.byte 0x465++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH101,Uncommitted Supervisorly Flash in Macro 101" group.byte 0x466++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH102,Uncommitted Supervisorly Flash in Macro 102" group.byte 0x467++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH103,Uncommitted Supervisorly Flash in Macro 103" group.byte 0x468++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH104,Uncommitted Supervisorly Flash in Macro 104" group.byte 0x469++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH105,Uncommitted Supervisorly Flash in Macro 105" group.byte 0x46A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH106,Uncommitted Supervisorly Flash in Macro 106" group.byte 0x46B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH107,Uncommitted Supervisorly Flash in Macro 107" group.byte 0x46C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH108,Uncommitted Supervisorly Flash in Macro 108" group.byte 0x46D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH109,Uncommitted Supervisorly Flash in Macro 109" group.byte 0x46E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH110,Uncommitted Supervisorly Flash in Macro 110" group.byte 0x46F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH111,Uncommitted Supervisorly Flash in Macro 111" group.byte 0x470++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH112,Uncommitted Supervisorly Flash in Macro 112" group.byte 0x471++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH113,Uncommitted Supervisorly Flash in Macro 113" group.byte 0x472++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH114,Uncommitted Supervisorly Flash in Macro 114" group.byte 0x473++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH115,Uncommitted Supervisorly Flash in Macro 115" group.byte 0x474++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH116,Uncommitted Supervisorly Flash in Macro 116" group.byte 0x475++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH117,Uncommitted Supervisorly Flash in Macro 117" group.byte 0x476++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH118,Uncommitted Supervisorly Flash in Macro 118" group.byte 0x477++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH119,Uncommitted Supervisorly Flash in Macro 119" group.byte 0x478++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH120,Uncommitted Supervisorly Flash in Macro 120" group.byte 0x479++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH121,Uncommitted Supervisorly Flash in Macro 121" group.byte 0x47A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH122,Uncommitted Supervisorly Flash in Macro 122" group.byte 0x47B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH123,Uncommitted Supervisorly Flash in Macro 123" group.byte 0x47C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH124,Uncommitted Supervisorly Flash in Macro 124" group.byte 0x47D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH125,Uncommitted Supervisorly Flash in Macro 125" group.byte 0x47E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH126,Uncommitted Supervisorly Flash in Macro 126" group.byte 0x47F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH127,Uncommitted Supervisorly Flash in Macro 127" group.byte 0x480++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH128,Uncommitted Supervisorly Flash in Macro 128" group.byte 0x481++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH129,Uncommitted Supervisorly Flash in Macro 129" group.byte 0x482++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH130,Uncommitted Supervisorly Flash in Macro 130" group.byte 0x483++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH131,Uncommitted Supervisorly Flash in Macro 131" group.byte 0x484++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH132,Uncommitted Supervisorly Flash in Macro 132" group.byte 0x485++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH133,Uncommitted Supervisorly Flash in Macro 133" group.byte 0x486++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH134,Uncommitted Supervisorly Flash in Macro 134" group.byte 0x487++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH135,Uncommitted Supervisorly Flash in Macro 135" group.byte 0x488++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH136,Uncommitted Supervisorly Flash in Macro 136" group.byte 0x489++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH137,Uncommitted Supervisorly Flash in Macro 137" group.byte 0x48A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH138,Uncommitted Supervisorly Flash in Macro 138" group.byte 0x48B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH139,Uncommitted Supervisorly Flash in Macro 139" group.byte 0x48C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH140,Uncommitted Supervisorly Flash in Macro 140" group.byte 0x48D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH141,Uncommitted Supervisorly Flash in Macro 141" group.byte 0x48E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH142,Uncommitted Supervisorly Flash in Macro 142" group.byte 0x48F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH143,Uncommitted Supervisorly Flash in Macro 143" group.byte 0x490++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH144,Uncommitted Supervisorly Flash in Macro 144" group.byte 0x491++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH145,Uncommitted Supervisorly Flash in Macro 145" group.byte 0x492++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH146,Uncommitted Supervisorly Flash in Macro 146" group.byte 0x493++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH147,Uncommitted Supervisorly Flash in Macro 147" group.byte 0x494++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH148,Uncommitted Supervisorly Flash in Macro 148" group.byte 0x495++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH149,Uncommitted Supervisorly Flash in Macro 149" group.byte 0x496++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH150,Uncommitted Supervisorly Flash in Macro 150" group.byte 0x497++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH151,Uncommitted Supervisorly Flash in Macro 151" group.byte 0x498++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH152,Uncommitted Supervisorly Flash in Macro 152" group.byte 0x499++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH153,Uncommitted Supervisorly Flash in Macro 153" group.byte 0x49A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH154,Uncommitted Supervisorly Flash in Macro 154" group.byte 0x49B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH155,Uncommitted Supervisorly Flash in Macro 155" group.byte 0x49C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH156,Uncommitted Supervisorly Flash in Macro 156" group.byte 0x49D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH157,Uncommitted Supervisorly Flash in Macro 157" group.byte 0x49E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH158,Uncommitted Supervisorly Flash in Macro 158" group.byte 0x49F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH159,Uncommitted Supervisorly Flash in Macro 159" group.byte 0x4A0++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH160,Uncommitted Supervisorly Flash in Macro 160" group.byte 0x4A1++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH161,Uncommitted Supervisorly Flash in Macro 161" group.byte 0x4A2++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH162,Uncommitted Supervisorly Flash in Macro 162" group.byte 0x4A3++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH163,Uncommitted Supervisorly Flash in Macro 163" group.byte 0x4A4++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH164,Uncommitted Supervisorly Flash in Macro 164" group.byte 0x4A5++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH165,Uncommitted Supervisorly Flash in Macro 165" group.byte 0x4A6++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH166,Uncommitted Supervisorly Flash in Macro 166" group.byte 0x4A7++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH167,Uncommitted Supervisorly Flash in Macro 167" group.byte 0x4A8++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH168,Uncommitted Supervisorly Flash in Macro 168" group.byte 0x4A9++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH169,Uncommitted Supervisorly Flash in Macro 169" group.byte 0x4AA++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH170,Uncommitted Supervisorly Flash in Macro 170" group.byte 0x4AB++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH171,Uncommitted Supervisorly Flash in Macro 171" group.byte 0x4AC++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH172,Uncommitted Supervisorly Flash in Macro 172" group.byte 0x4AD++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH173,Uncommitted Supervisorly Flash in Macro 173" group.byte 0x4AE++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH174,Uncommitted Supervisorly Flash in Macro 174" group.byte 0x4AF++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH175,Uncommitted Supervisorly Flash in Macro 175" group.byte 0x4B0++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH176,Uncommitted Supervisorly Flash in Macro 176" group.byte 0x4B1++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH177,Uncommitted Supervisorly Flash in Macro 177" group.byte 0x4B2++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH178,Uncommitted Supervisorly Flash in Macro 178" group.byte 0x4B3++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH179,Uncommitted Supervisorly Flash in Macro 179" group.byte 0x4B4++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH180,Uncommitted Supervisorly Flash in Macro 180" group.byte 0x4B5++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH181,Uncommitted Supervisorly Flash in Macro 181" group.byte 0x4B6++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH182,Uncommitted Supervisorly Flash in Macro 182" group.byte 0x4B7++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH183,Uncommitted Supervisorly Flash in Macro 183" group.byte 0x4B8++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH184,Uncommitted Supervisorly Flash in Macro 184" group.byte 0x4B9++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH185,Uncommitted Supervisorly Flash in Macro 185" group.byte 0x4BA++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH186,Uncommitted Supervisorly Flash in Macro 186" group.byte 0x4BB++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH187,Uncommitted Supervisorly Flash in Macro 187" group.byte 0x4BC++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH188,Uncommitted Supervisorly Flash in Macro 188" group.byte 0x4BD++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH189,Uncommitted Supervisorly Flash in Macro 189" group.byte 0x4BE++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH190,Uncommitted Supervisorly Flash in Macro 190" group.byte 0x4BF++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH191,Uncommitted Supervisorly Flash in Macro 191" group.byte 0x4C0++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH192,Uncommitted Supervisorly Flash in Macro 192" group.byte 0x4C1++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH193,Uncommitted Supervisorly Flash in Macro 193" group.byte 0x4C2++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH194,Uncommitted Supervisorly Flash in Macro 194" group.byte 0x4C3++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH195,Uncommitted Supervisorly Flash in Macro 195" group.byte 0x4C4++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH196,Uncommitted Supervisorly Flash in Macro 196" group.byte 0x4C5++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH197,Uncommitted Supervisorly Flash in Macro 197" group.byte 0x4C6++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH198,Uncommitted Supervisorly Flash in Macro 198" group.byte 0x4C7++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH199,Uncommitted Supervisorly Flash in Macro 199" group.byte 0x4C8++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH200,Uncommitted Supervisorly Flash in Macro 200" group.byte 0x4C9++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH201,Uncommitted Supervisorly Flash in Macro 201" group.byte 0x4CA++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH202,Uncommitted Supervisorly Flash in Macro 202" group.byte 0x4CB++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH203,Uncommitted Supervisorly Flash in Macro 203" group.byte 0x4CC++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH204,Uncommitted Supervisorly Flash in Macro 204" group.byte 0x4CD++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH205,Uncommitted Supervisorly Flash in Macro 205" group.byte 0x4CE++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH206,Uncommitted Supervisorly Flash in Macro 206" group.byte 0x4CF++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH207,Uncommitted Supervisorly Flash in Macro 207" group.byte 0x4D0++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH208,Uncommitted Supervisorly Flash in Macro 208" group.byte 0x4D1++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH209,Uncommitted Supervisorly Flash in Macro 209" group.byte 0x4D2++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH210,Uncommitted Supervisorly Flash in Macro 210" group.byte 0x4D3++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH211,Uncommitted Supervisorly Flash in Macro 211" group.byte 0x4D4++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH212,Uncommitted Supervisorly Flash in Macro 212" group.byte 0x4D5++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH213,Uncommitted Supervisorly Flash in Macro 213" group.byte 0x4D6++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH214,Uncommitted Supervisorly Flash in Macro 214" group.byte 0x4D7++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH215,Uncommitted Supervisorly Flash in Macro 215" group.byte 0x4D8++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH216,Uncommitted Supervisorly Flash in Macro 216" group.byte 0x4D9++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH217,Uncommitted Supervisorly Flash in Macro 217" group.byte 0x4DA++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH218,Uncommitted Supervisorly Flash in Macro 218" group.byte 0x4DB++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH219,Uncommitted Supervisorly Flash in Macro 219" group.byte 0x4DC++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH220,Uncommitted Supervisorly Flash in Macro 220" group.byte 0x4DD++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH221,Uncommitted Supervisorly Flash in Macro 221" group.byte 0x4DE++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH222,Uncommitted Supervisorly Flash in Macro 222" group.byte 0x4DF++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH223,Uncommitted Supervisorly Flash in Macro 223" group.byte 0x4E0++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH224,Uncommitted Supervisorly Flash in Macro 224" group.byte 0x4E1++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH225,Uncommitted Supervisorly Flash in Macro 225" group.byte 0x4E2++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH226,Uncommitted Supervisorly Flash in Macro 226" group.byte 0x4E3++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH227,Uncommitted Supervisorly Flash in Macro 227" group.byte 0x4E4++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH228,Uncommitted Supervisorly Flash in Macro 228" group.byte 0x4E5++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH229,Uncommitted Supervisorly Flash in Macro 229" group.byte 0x4E6++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH230,Uncommitted Supervisorly Flash in Macro 230" group.byte 0x4E7++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH231,Uncommitted Supervisorly Flash in Macro 231" group.byte 0x4E8++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH232,Uncommitted Supervisorly Flash in Macro 232" group.byte 0x4E9++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH233,Uncommitted Supervisorly Flash in Macro 233" group.byte 0x4EA++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH234,Uncommitted Supervisorly Flash in Macro 234" group.byte 0x4EB++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH235,Uncommitted Supervisorly Flash in Macro 235" group.byte 0x4EC++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH236,Uncommitted Supervisorly Flash in Macro 236" group.byte 0x4ED++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH237,Uncommitted Supervisorly Flash in Macro 237" group.byte 0x4EE++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH238,Uncommitted Supervisorly Flash in Macro 238" group.byte 0x4EF++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH239,Uncommitted Supervisorly Flash in Macro 239" group.byte 0x4F0++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH240,Uncommitted Supervisorly Flash in Macro 240" group.byte 0x4F1++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH241,Uncommitted Supervisorly Flash in Macro 241" group.byte 0x4F2++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH242,Uncommitted Supervisorly Flash in Macro 242" group.byte 0x4F3++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH243,Uncommitted Supervisorly Flash in Macro 243" group.byte 0x4F4++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH244,Uncommitted Supervisorly Flash in Macro 244" group.byte 0x4F5++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH245,Uncommitted Supervisorly Flash in Macro 245" group.byte 0x4F6++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH246,Uncommitted Supervisorly Flash in Macro 246" group.byte 0x4F7++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH247,Uncommitted Supervisorly Flash in Macro 247" group.byte 0x4F8++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH248,Uncommitted Supervisorly Flash in Macro 248" group.byte 0x4F9++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH249,Uncommitted Supervisorly Flash in Macro 249" group.byte 0x4FA++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH250,Uncommitted Supervisorly Flash in Macro 250" group.byte 0x4FB++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH251,Uncommitted Supervisorly Flash in Macro 251" group.byte 0x4FC++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH252,Uncommitted Supervisorly Flash in Macro 252" group.byte 0x4FD++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH253,Uncommitted Supervisorly Flash in Macro 253" group.byte 0x4FE++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH254,Uncommitted Supervisorly Flash in Macro 254" group.byte 0x4FF++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH255,Uncommitted Supervisorly Flash in Macro 255" group.byte 0x500++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH256,Uncommitted Supervisorly Flash in Macro 256" group.byte 0x501++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH257,Uncommitted Supervisorly Flash in Macro 257" group.byte 0x502++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH258,Uncommitted Supervisorly Flash in Macro 258" group.byte 0x503++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH259,Uncommitted Supervisorly Flash in Macro 259" group.byte 0x504++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH260,Uncommitted Supervisorly Flash in Macro 260" group.byte 0x505++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH261,Uncommitted Supervisorly Flash in Macro 261" group.byte 0x506++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH262,Uncommitted Supervisorly Flash in Macro 262" group.byte 0x507++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH263,Uncommitted Supervisorly Flash in Macro 263" group.byte 0x508++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH264,Uncommitted Supervisorly Flash in Macro 264" group.byte 0x509++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH265,Uncommitted Supervisorly Flash in Macro 265" group.byte 0x50A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH266,Uncommitted Supervisorly Flash in Macro 266" group.byte 0x50B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH267,Uncommitted Supervisorly Flash in Macro 267" group.byte 0x50C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH268,Uncommitted Supervisorly Flash in Macro 268" group.byte 0x50D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH269,Uncommitted Supervisorly Flash in Macro 269" group.byte 0x50E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH270,Uncommitted Supervisorly Flash in Macro 270" group.byte 0x50F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH271,Uncommitted Supervisorly Flash in Macro 271" group.byte 0x510++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH272,Uncommitted Supervisorly Flash in Macro 272" group.byte 0x511++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH273,Uncommitted Supervisorly Flash in Macro 273" group.byte 0x512++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH274,Uncommitted Supervisorly Flash in Macro 274" group.byte 0x513++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH275,Uncommitted Supervisorly Flash in Macro 275" group.byte 0x514++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH276,Uncommitted Supervisorly Flash in Macro 276" group.byte 0x515++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH277,Uncommitted Supervisorly Flash in Macro 277" group.byte 0x516++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH278,Uncommitted Supervisorly Flash in Macro 278" group.byte 0x517++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH279,Uncommitted Supervisorly Flash in Macro 279" group.byte 0x518++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH280,Uncommitted Supervisorly Flash in Macro 280" group.byte 0x519++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH281,Uncommitted Supervisorly Flash in Macro 281" group.byte 0x51A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH282,Uncommitted Supervisorly Flash in Macro 282" group.byte 0x51B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH283,Uncommitted Supervisorly Flash in Macro 283" group.byte 0x51C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH284,Uncommitted Supervisorly Flash in Macro 284" group.byte 0x51D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH285,Uncommitted Supervisorly Flash in Macro 285" group.byte 0x51E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH286,Uncommitted Supervisorly Flash in Macro 286" group.byte 0x51F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH287,Uncommitted Supervisorly Flash in Macro 287" group.byte 0x520++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH288,Uncommitted Supervisorly Flash in Macro 288" group.byte 0x521++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH289,Uncommitted Supervisorly Flash in Macro 289" group.byte 0x522++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH290,Uncommitted Supervisorly Flash in Macro 290" group.byte 0x523++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH291,Uncommitted Supervisorly Flash in Macro 291" group.byte 0x524++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH292,Uncommitted Supervisorly Flash in Macro 292" group.byte 0x525++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH293,Uncommitted Supervisorly Flash in Macro 293" group.byte 0x526++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH294,Uncommitted Supervisorly Flash in Macro 294" group.byte 0x527++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH295,Uncommitted Supervisorly Flash in Macro 295" group.byte 0x528++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH296,Uncommitted Supervisorly Flash in Macro 296" group.byte 0x529++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH297,Uncommitted Supervisorly Flash in Macro 297" group.byte 0x52A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH298,Uncommitted Supervisorly Flash in Macro 298" group.byte 0x52B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH299,Uncommitted Supervisorly Flash in Macro 299" group.byte 0x52C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH300,Uncommitted Supervisorly Flash in Macro 300" group.byte 0x52D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH301,Uncommitted Supervisorly Flash in Macro 301" group.byte 0x52E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH302,Uncommitted Supervisorly Flash in Macro 302" group.byte 0x52F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH303,Uncommitted Supervisorly Flash in Macro 303" group.byte 0x530++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH304,Uncommitted Supervisorly Flash in Macro 304" group.byte 0x531++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH305,Uncommitted Supervisorly Flash in Macro 305" group.byte 0x532++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH306,Uncommitted Supervisorly Flash in Macro 306" group.byte 0x533++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH307,Uncommitted Supervisorly Flash in Macro 307" group.byte 0x534++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH308,Uncommitted Supervisorly Flash in Macro 308" group.byte 0x535++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH309,Uncommitted Supervisorly Flash in Macro 309" group.byte 0x536++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH310,Uncommitted Supervisorly Flash in Macro 310" group.byte 0x537++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH311,Uncommitted Supervisorly Flash in Macro 311" group.byte 0x538++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH312,Uncommitted Supervisorly Flash in Macro 312" group.byte 0x539++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH313,Uncommitted Supervisorly Flash in Macro 313" group.byte 0x53A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH314,Uncommitted Supervisorly Flash in Macro 314" group.byte 0x53B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH315,Uncommitted Supervisorly Flash in Macro 315" group.byte 0x53C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH316,Uncommitted Supervisorly Flash in Macro 316" group.byte 0x53D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH317,Uncommitted Supervisorly Flash in Macro 317" group.byte 0x53E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH318,Uncommitted Supervisorly Flash in Macro 318" group.byte 0x53F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH319,Uncommitted Supervisorly Flash in Macro 319" group.byte 0x540++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH320,Uncommitted Supervisorly Flash in Macro 320" group.byte 0x541++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH321,Uncommitted Supervisorly Flash in Macro 321" group.byte 0x542++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH322,Uncommitted Supervisorly Flash in Macro 322" group.byte 0x543++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH323,Uncommitted Supervisorly Flash in Macro 323" group.byte 0x544++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH324,Uncommitted Supervisorly Flash in Macro 324" group.byte 0x545++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH325,Uncommitted Supervisorly Flash in Macro 325" group.byte 0x546++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH326,Uncommitted Supervisorly Flash in Macro 326" group.byte 0x547++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH327,Uncommitted Supervisorly Flash in Macro 327" group.byte 0x548++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH328,Uncommitted Supervisorly Flash in Macro 328" group.byte 0x549++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH329,Uncommitted Supervisorly Flash in Macro 329" group.byte 0x54A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH330,Uncommitted Supervisorly Flash in Macro 330" group.byte 0x54B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH331,Uncommitted Supervisorly Flash in Macro 331" group.byte 0x54C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH332,Uncommitted Supervisorly Flash in Macro 332" group.byte 0x54D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH333,Uncommitted Supervisorly Flash in Macro 333" group.byte 0x54E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH334,Uncommitted Supervisorly Flash in Macro 334" group.byte 0x54F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH335,Uncommitted Supervisorly Flash in Macro 335" group.byte 0x550++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH336,Uncommitted Supervisorly Flash in Macro 336" group.byte 0x551++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH337,Uncommitted Supervisorly Flash in Macro 337" group.byte 0x552++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH338,Uncommitted Supervisorly Flash in Macro 338" group.byte 0x553++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH339,Uncommitted Supervisorly Flash in Macro 339" group.byte 0x554++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH340,Uncommitted Supervisorly Flash in Macro 340" group.byte 0x555++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH341,Uncommitted Supervisorly Flash in Macro 341" group.byte 0x556++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH342,Uncommitted Supervisorly Flash in Macro 342" group.byte 0x557++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH343,Uncommitted Supervisorly Flash in Macro 343" group.byte 0x558++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH344,Uncommitted Supervisorly Flash in Macro 344" group.byte 0x559++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH345,Uncommitted Supervisorly Flash in Macro 345" group.byte 0x55A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH346,Uncommitted Supervisorly Flash in Macro 346" group.byte 0x55B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH347,Uncommitted Supervisorly Flash in Macro 347" group.byte 0x55C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH348,Uncommitted Supervisorly Flash in Macro 348" group.byte 0x55D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH349,Uncommitted Supervisorly Flash in Macro 349" group.byte 0x55E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH350,Uncommitted Supervisorly Flash in Macro 350" group.byte 0x55F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH351,Uncommitted Supervisorly Flash in Macro 351" group.byte 0x560++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH352,Uncommitted Supervisorly Flash in Macro 352" group.byte 0x561++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH353,Uncommitted Supervisorly Flash in Macro 353" group.byte 0x562++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH354,Uncommitted Supervisorly Flash in Macro 354" group.byte 0x563++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH355,Uncommitted Supervisorly Flash in Macro 355" group.byte 0x564++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH356,Uncommitted Supervisorly Flash in Macro 356" group.byte 0x565++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH357,Uncommitted Supervisorly Flash in Macro 357" group.byte 0x566++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH358,Uncommitted Supervisorly Flash in Macro 358" group.byte 0x567++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH359,Uncommitted Supervisorly Flash in Macro 359" group.byte 0x568++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH360,Uncommitted Supervisorly Flash in Macro 360" group.byte 0x569++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH361,Uncommitted Supervisorly Flash in Macro 361" group.byte 0x56A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH362,Uncommitted Supervisorly Flash in Macro 362" group.byte 0x56B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH363,Uncommitted Supervisorly Flash in Macro 363" group.byte 0x56C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH364,Uncommitted Supervisorly Flash in Macro 364" group.byte 0x56D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH365,Uncommitted Supervisorly Flash in Macro 365" group.byte 0x56E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH366,Uncommitted Supervisorly Flash in Macro 366" group.byte 0x56F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH367,Uncommitted Supervisorly Flash in Macro 367" group.byte 0x570++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH368,Uncommitted Supervisorly Flash in Macro 368" group.byte 0x571++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH369,Uncommitted Supervisorly Flash in Macro 369" group.byte 0x572++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH370,Uncommitted Supervisorly Flash in Macro 370" group.byte 0x573++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH371,Uncommitted Supervisorly Flash in Macro 371" group.byte 0x574++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH372,Uncommitted Supervisorly Flash in Macro 372" group.byte 0x575++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH373,Uncommitted Supervisorly Flash in Macro 373" group.byte 0x576++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH374,Uncommitted Supervisorly Flash in Macro 374" group.byte 0x577++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH375,Uncommitted Supervisorly Flash in Macro 375" group.byte 0x578++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH376,Uncommitted Supervisorly Flash in Macro 376" group.byte 0x579++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH377,Uncommitted Supervisorly Flash in Macro 377" group.byte 0x57A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH378,Uncommitted Supervisorly Flash in Macro 378" group.byte 0x57B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH379,Uncommitted Supervisorly Flash in Macro 379" group.byte 0x57C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH380,Uncommitted Supervisorly Flash in Macro 380" group.byte 0x57D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH381,Uncommitted Supervisorly Flash in Macro 381" group.byte 0x57E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH382,Uncommitted Supervisorly Flash in Macro 382" group.byte 0x57F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH383,Uncommitted Supervisorly Flash in Macro 383" group.byte 0x580++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH384,Uncommitted Supervisorly Flash in Macro 384" group.byte 0x581++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH385,Uncommitted Supervisorly Flash in Macro 385" group.byte 0x582++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH386,Uncommitted Supervisorly Flash in Macro 386" group.byte 0x583++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH387,Uncommitted Supervisorly Flash in Macro 387" group.byte 0x584++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH388,Uncommitted Supervisorly Flash in Macro 388" group.byte 0x585++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH389,Uncommitted Supervisorly Flash in Macro 389" group.byte 0x586++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH390,Uncommitted Supervisorly Flash in Macro 390" group.byte 0x587++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH391,Uncommitted Supervisorly Flash in Macro 391" group.byte 0x588++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH392,Uncommitted Supervisorly Flash in Macro 392" group.byte 0x589++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH393,Uncommitted Supervisorly Flash in Macro 393" group.byte 0x58A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH394,Uncommitted Supervisorly Flash in Macro 394" group.byte 0x58B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH395,Uncommitted Supervisorly Flash in Macro 395" group.byte 0x58C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH396,Uncommitted Supervisorly Flash in Macro 396" group.byte 0x58D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH397,Uncommitted Supervisorly Flash in Macro 397" group.byte 0x58E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH398,Uncommitted Supervisorly Flash in Macro 398" group.byte 0x58F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH399,Uncommitted Supervisorly Flash in Macro 399" group.byte 0x590++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH400,Uncommitted Supervisorly Flash in Macro 400" group.byte 0x591++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH401,Uncommitted Supervisorly Flash in Macro 401" group.byte 0x592++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH402,Uncommitted Supervisorly Flash in Macro 402" group.byte 0x593++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH403,Uncommitted Supervisorly Flash in Macro 403" group.byte 0x594++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH404,Uncommitted Supervisorly Flash in Macro 404" group.byte 0x595++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH405,Uncommitted Supervisorly Flash in Macro 405" group.byte 0x596++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH406,Uncommitted Supervisorly Flash in Macro 406" group.byte 0x597++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH407,Uncommitted Supervisorly Flash in Macro 407" group.byte 0x598++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH408,Uncommitted Supervisorly Flash in Macro 408" group.byte 0x599++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH409,Uncommitted Supervisorly Flash in Macro 409" group.byte 0x59A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH410,Uncommitted Supervisorly Flash in Macro 410" group.byte 0x59B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH411,Uncommitted Supervisorly Flash in Macro 411" group.byte 0x59C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH412,Uncommitted Supervisorly Flash in Macro 412" group.byte 0x59D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH413,Uncommitted Supervisorly Flash in Macro 413" group.byte 0x59E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH414,Uncommitted Supervisorly Flash in Macro 414" group.byte 0x59F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH415,Uncommitted Supervisorly Flash in Macro 415" group.byte 0x5A0++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH416,Uncommitted Supervisorly Flash in Macro 416" group.byte 0x5A1++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH417,Uncommitted Supervisorly Flash in Macro 417" group.byte 0x5A2++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH418,Uncommitted Supervisorly Flash in Macro 418" group.byte 0x5A3++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH419,Uncommitted Supervisorly Flash in Macro 419" group.byte 0x5A4++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH420,Uncommitted Supervisorly Flash in Macro 420" group.byte 0x5A5++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH421,Uncommitted Supervisorly Flash in Macro 421" group.byte 0x5A6++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH422,Uncommitted Supervisorly Flash in Macro 422" group.byte 0x5A7++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH423,Uncommitted Supervisorly Flash in Macro 423" group.byte 0x5A8++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH424,Uncommitted Supervisorly Flash in Macro 424" group.byte 0x5A9++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH425,Uncommitted Supervisorly Flash in Macro 425" group.byte 0x5AA++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH426,Uncommitted Supervisorly Flash in Macro 426" group.byte 0x5AB++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH427,Uncommitted Supervisorly Flash in Macro 427" group.byte 0x5AC++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH428,Uncommitted Supervisorly Flash in Macro 428" group.byte 0x5AD++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH429,Uncommitted Supervisorly Flash in Macro 429" group.byte 0x5AE++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH430,Uncommitted Supervisorly Flash in Macro 430" group.byte 0x5AF++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH431,Uncommitted Supervisorly Flash in Macro 431" group.byte 0x5B0++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH432,Uncommitted Supervisorly Flash in Macro 432" group.byte 0x5B1++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH433,Uncommitted Supervisorly Flash in Macro 433" group.byte 0x5B2++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH434,Uncommitted Supervisorly Flash in Macro 434" group.byte 0x5B3++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH435,Uncommitted Supervisorly Flash in Macro 435" group.byte 0x5B4++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH436,Uncommitted Supervisorly Flash in Macro 436" group.byte 0x5B5++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH437,Uncommitted Supervisorly Flash in Macro 437" group.byte 0x5B6++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH438,Uncommitted Supervisorly Flash in Macro 438" group.byte 0x5B7++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH439,Uncommitted Supervisorly Flash in Macro 439" group.byte 0x5B8++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH440,Uncommitted Supervisorly Flash in Macro 440" group.byte 0x5B9++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH441,Uncommitted Supervisorly Flash in Macro 441" group.byte 0x5BA++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH442,Uncommitted Supervisorly Flash in Macro 442" group.byte 0x5BB++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH443,Uncommitted Supervisorly Flash in Macro 443" group.byte 0x5BC++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH444,Uncommitted Supervisorly Flash in Macro 444" group.byte 0x5BD++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH445,Uncommitted Supervisorly Flash in Macro 445" group.byte 0x5BE++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH446,Uncommitted Supervisorly Flash in Macro 446" group.byte 0x5BF++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH447,Uncommitted Supervisorly Flash in Macro 447" group.byte 0x5C0++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH448,Uncommitted Supervisorly Flash in Macro 448" group.byte 0x5C1++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH449,Uncommitted Supervisorly Flash in Macro 449" group.byte 0x5C2++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH450,Uncommitted Supervisorly Flash in Macro 450" group.byte 0x5C3++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH451,Uncommitted Supervisorly Flash in Macro 451" group.byte 0x5C4++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH452,Uncommitted Supervisorly Flash in Macro 452" group.byte 0x5C5++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH453,Uncommitted Supervisorly Flash in Macro 453" group.byte 0x5C6++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH454,Uncommitted Supervisorly Flash in Macro 454" group.byte 0x5C7++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH455,Uncommitted Supervisorly Flash in Macro 455" group.byte 0x5C8++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH456,Uncommitted Supervisorly Flash in Macro 456" group.byte 0x5C9++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH457,Uncommitted Supervisorly Flash in Macro 457" group.byte 0x5CA++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH458,Uncommitted Supervisorly Flash in Macro 458" group.byte 0x5CB++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH459,Uncommitted Supervisorly Flash in Macro 459" group.byte 0x5CC++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH460,Uncommitted Supervisorly Flash in Macro 460" group.byte 0x5CD++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH461,Uncommitted Supervisorly Flash in Macro 461" group.byte 0x5CE++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH462,Uncommitted Supervisorly Flash in Macro 462" group.byte 0x5CF++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH463,Uncommitted Supervisorly Flash in Macro 463" group.byte 0x5D0++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH464,Uncommitted Supervisorly Flash in Macro 464" group.byte 0x5D1++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH465,Uncommitted Supervisorly Flash in Macro 465" group.byte 0x5D2++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH466,Uncommitted Supervisorly Flash in Macro 466" group.byte 0x5D3++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH467,Uncommitted Supervisorly Flash in Macro 467" group.byte 0x5D4++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH468,Uncommitted Supervisorly Flash in Macro 468" group.byte 0x5D5++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH469,Uncommitted Supervisorly Flash in Macro 469" group.byte 0x5D6++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH470,Uncommitted Supervisorly Flash in Macro 470" group.byte 0x5D7++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH471,Uncommitted Supervisorly Flash in Macro 471" group.byte 0x5D8++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH472,Uncommitted Supervisorly Flash in Macro 472" group.byte 0x5D9++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH473,Uncommitted Supervisorly Flash in Macro 473" group.byte 0x5DA++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH474,Uncommitted Supervisorly Flash in Macro 474" group.byte 0x5DB++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH475,Uncommitted Supervisorly Flash in Macro 475" group.byte 0x5DC++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH476,Uncommitted Supervisorly Flash in Macro 476" group.byte 0x5DD++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH477,Uncommitted Supervisorly Flash in Macro 477" group.byte 0x5DE++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH478,Uncommitted Supervisorly Flash in Macro 478" group.byte 0x5DF++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH479,Uncommitted Supervisorly Flash in Macro 479" group.byte 0x5E0++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH480,Uncommitted Supervisorly Flash in Macro 480" group.byte 0x5E1++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH481,Uncommitted Supervisorly Flash in Macro 481" group.byte 0x5E2++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH482,Uncommitted Supervisorly Flash in Macro 482" group.byte 0x5E3++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH483,Uncommitted Supervisorly Flash in Macro 483" group.byte 0x5E4++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH484,Uncommitted Supervisorly Flash in Macro 484" group.byte 0x5E5++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH485,Uncommitted Supervisorly Flash in Macro 485" group.byte 0x5E6++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH486,Uncommitted Supervisorly Flash in Macro 486" group.byte 0x5E7++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH487,Uncommitted Supervisorly Flash in Macro 487" group.byte 0x5E8++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH488,Uncommitted Supervisorly Flash in Macro 488" group.byte 0x5E9++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH489,Uncommitted Supervisorly Flash in Macro 489" group.byte 0x5EA++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH490,Uncommitted Supervisorly Flash in Macro 490" group.byte 0x5EB++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH491,Uncommitted Supervisorly Flash in Macro 491" group.byte 0x5EC++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH492,Uncommitted Supervisorly Flash in Macro 492" group.byte 0x5ED++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH493,Uncommitted Supervisorly Flash in Macro 493" group.byte 0x5EE++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH494,Uncommitted Supervisorly Flash in Macro 494" group.byte 0x5EF++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH495,Uncommitted Supervisorly Flash in Macro 495" group.byte 0x5F0++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH496,Uncommitted Supervisorly Flash in Macro 496" group.byte 0x5F1++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH497,Uncommitted Supervisorly Flash in Macro 497" group.byte 0x5F2++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH498,Uncommitted Supervisorly Flash in Macro 498" group.byte 0x5F3++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH499,Uncommitted Supervisorly Flash in Macro 499" group.byte 0x5F4++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH500,Uncommitted Supervisorly Flash in Macro 500" group.byte 0x5F5++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH501,Uncommitted Supervisorly Flash in Macro 501" group.byte 0x5F6++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH502,Uncommitted Supervisorly Flash in Macro 502" group.byte 0x5F7++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH503,Uncommitted Supervisorly Flash in Macro 503" group.byte 0x5F8++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH504,Uncommitted Supervisorly Flash in Macro 504" group.byte 0x5F9++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH505,Uncommitted Supervisorly Flash in Macro 505" group.byte 0x5FA++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH506,Uncommitted Supervisorly Flash in Macro 506" group.byte 0x5FB++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH507,Uncommitted Supervisorly Flash in Macro 507" group.byte 0x5FC++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH508,Uncommitted Supervisorly Flash in Macro 508" group.byte 0x5FD++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH509,Uncommitted Supervisorly Flash in Macro 509" group.byte 0x5FE++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH510,Uncommitted Supervisorly Flash in Macro 510" group.byte 0x5FF++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH511,Uncommitted Supervisorly Flash in Macro 511" group.byte 0x600++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH512,Uncommitted Supervisorly Flash in Macro 512" group.byte 0x601++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH513,Uncommitted Supervisorly Flash in Macro 513" group.byte 0x602++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH514,Uncommitted Supervisorly Flash in Macro 514" group.byte 0x603++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH515,Uncommitted Supervisorly Flash in Macro 515" group.byte 0x604++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH516,Uncommitted Supervisorly Flash in Macro 516" group.byte 0x605++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH517,Uncommitted Supervisorly Flash in Macro 517" group.byte 0x606++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH518,Uncommitted Supervisorly Flash in Macro 518" group.byte 0x607++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH519,Uncommitted Supervisorly Flash in Macro 519" group.byte 0x608++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH520,Uncommitted Supervisorly Flash in Macro 520" group.byte 0x609++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH521,Uncommitted Supervisorly Flash in Macro 521" group.byte 0x60A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH522,Uncommitted Supervisorly Flash in Macro 522" group.byte 0x60B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH523,Uncommitted Supervisorly Flash in Macro 523" group.byte 0x60C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH524,Uncommitted Supervisorly Flash in Macro 524" group.byte 0x60D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH525,Uncommitted Supervisorly Flash in Macro 525" group.byte 0x60E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH526,Uncommitted Supervisorly Flash in Macro 526" group.byte 0x60F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH527,Uncommitted Supervisorly Flash in Macro 527" group.byte 0x610++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH528,Uncommitted Supervisorly Flash in Macro 528" group.byte 0x611++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH529,Uncommitted Supervisorly Flash in Macro 529" group.byte 0x612++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH530,Uncommitted Supervisorly Flash in Macro 530" group.byte 0x613++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH531,Uncommitted Supervisorly Flash in Macro 531" group.byte 0x614++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH532,Uncommitted Supervisorly Flash in Macro 532" group.byte 0x615++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH533,Uncommitted Supervisorly Flash in Macro 533" group.byte 0x616++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH534,Uncommitted Supervisorly Flash in Macro 534" group.byte 0x617++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH535,Uncommitted Supervisorly Flash in Macro 535" group.byte 0x618++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH536,Uncommitted Supervisorly Flash in Macro 536" group.byte 0x619++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH537,Uncommitted Supervisorly Flash in Macro 537" group.byte 0x61A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH538,Uncommitted Supervisorly Flash in Macro 538" group.byte 0x61B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH539,Uncommitted Supervisorly Flash in Macro 539" group.byte 0x61C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH540,Uncommitted Supervisorly Flash in Macro 540" group.byte 0x61D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH541,Uncommitted Supervisorly Flash in Macro 541" group.byte 0x61E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH542,Uncommitted Supervisorly Flash in Macro 542" group.byte 0x61F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH543,Uncommitted Supervisorly Flash in Macro 543" group.byte 0x620++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH544,Uncommitted Supervisorly Flash in Macro 544" group.byte 0x621++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH545,Uncommitted Supervisorly Flash in Macro 545" group.byte 0x622++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH546,Uncommitted Supervisorly Flash in Macro 546" group.byte 0x623++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH547,Uncommitted Supervisorly Flash in Macro 547" group.byte 0x624++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH548,Uncommitted Supervisorly Flash in Macro 548" group.byte 0x625++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH549,Uncommitted Supervisorly Flash in Macro 549" group.byte 0x626++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH550,Uncommitted Supervisorly Flash in Macro 550" group.byte 0x627++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH551,Uncommitted Supervisorly Flash in Macro 551" group.byte 0x628++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH552,Uncommitted Supervisorly Flash in Macro 552" group.byte 0x629++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH553,Uncommitted Supervisorly Flash in Macro 553" group.byte 0x62A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH554,Uncommitted Supervisorly Flash in Macro 554" group.byte 0x62B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH555,Uncommitted Supervisorly Flash in Macro 555" group.byte 0x62C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH556,Uncommitted Supervisorly Flash in Macro 556" group.byte 0x62D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH557,Uncommitted Supervisorly Flash in Macro 557" group.byte 0x62E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH558,Uncommitted Supervisorly Flash in Macro 558" group.byte 0x62F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH559,Uncommitted Supervisorly Flash in Macro 559" group.byte 0x630++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH560,Uncommitted Supervisorly Flash in Macro 560" group.byte 0x631++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH561,Uncommitted Supervisorly Flash in Macro 561" group.byte 0x632++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH562,Uncommitted Supervisorly Flash in Macro 562" group.byte 0x633++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH563,Uncommitted Supervisorly Flash in Macro 563" group.byte 0x634++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH564,Uncommitted Supervisorly Flash in Macro 564" group.byte 0x635++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH565,Uncommitted Supervisorly Flash in Macro 565" group.byte 0x636++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH566,Uncommitted Supervisorly Flash in Macro 566" group.byte 0x637++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH567,Uncommitted Supervisorly Flash in Macro 567" group.byte 0x638++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH568,Uncommitted Supervisorly Flash in Macro 568" group.byte 0x639++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH569,Uncommitted Supervisorly Flash in Macro 569" group.byte 0x63A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH570,Uncommitted Supervisorly Flash in Macro 570" group.byte 0x63B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH571,Uncommitted Supervisorly Flash in Macro 571" group.byte 0x63C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH572,Uncommitted Supervisorly Flash in Macro 572" group.byte 0x63D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH573,Uncommitted Supervisorly Flash in Macro 573" group.byte 0x63E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH574,Uncommitted Supervisorly Flash in Macro 574" group.byte 0x63F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH575,Uncommitted Supervisorly Flash in Macro 575" group.byte 0x640++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH576,Uncommitted Supervisorly Flash in Macro 576" group.byte 0x641++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH577,Uncommitted Supervisorly Flash in Macro 577" group.byte 0x642++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH578,Uncommitted Supervisorly Flash in Macro 578" group.byte 0x643++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH579,Uncommitted Supervisorly Flash in Macro 579" group.byte 0x644++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH580,Uncommitted Supervisorly Flash in Macro 580" group.byte 0x645++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH581,Uncommitted Supervisorly Flash in Macro 581" group.byte 0x646++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH582,Uncommitted Supervisorly Flash in Macro 582" group.byte 0x647++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH583,Uncommitted Supervisorly Flash in Macro 583" group.byte 0x648++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH584,Uncommitted Supervisorly Flash in Macro 584" group.byte 0x649++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH585,Uncommitted Supervisorly Flash in Macro 585" group.byte 0x64A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH586,Uncommitted Supervisorly Flash in Macro 586" group.byte 0x64B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH587,Uncommitted Supervisorly Flash in Macro 587" group.byte 0x64C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH588,Uncommitted Supervisorly Flash in Macro 588" group.byte 0x64D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH589,Uncommitted Supervisorly Flash in Macro 589" group.byte 0x64E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH590,Uncommitted Supervisorly Flash in Macro 590" group.byte 0x64F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH591,Uncommitted Supervisorly Flash in Macro 591" group.byte 0x650++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH592,Uncommitted Supervisorly Flash in Macro 592" group.byte 0x651++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH593,Uncommitted Supervisorly Flash in Macro 593" group.byte 0x652++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH594,Uncommitted Supervisorly Flash in Macro 594" group.byte 0x653++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH595,Uncommitted Supervisorly Flash in Macro 595" group.byte 0x654++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH596,Uncommitted Supervisorly Flash in Macro 596" group.byte 0x655++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH597,Uncommitted Supervisorly Flash in Macro 597" group.byte 0x656++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH598,Uncommitted Supervisorly Flash in Macro 598" group.byte 0x657++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH599,Uncommitted Supervisorly Flash in Macro 599" group.byte 0x658++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH600,Uncommitted Supervisorly Flash in Macro 600" group.byte 0x659++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH601,Uncommitted Supervisorly Flash in Macro 601" group.byte 0x65A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH602,Uncommitted Supervisorly Flash in Macro 602" group.byte 0x65B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH603,Uncommitted Supervisorly Flash in Macro 603" group.byte 0x65C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH604,Uncommitted Supervisorly Flash in Macro 604" group.byte 0x65D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH605,Uncommitted Supervisorly Flash in Macro 605" group.byte 0x65E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH606,Uncommitted Supervisorly Flash in Macro 606" group.byte 0x65F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH607,Uncommitted Supervisorly Flash in Macro 607" group.byte 0x660++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH608,Uncommitted Supervisorly Flash in Macro 608" group.byte 0x661++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH609,Uncommitted Supervisorly Flash in Macro 609" group.byte 0x662++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH610,Uncommitted Supervisorly Flash in Macro 610" group.byte 0x663++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH611,Uncommitted Supervisorly Flash in Macro 611" group.byte 0x664++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH612,Uncommitted Supervisorly Flash in Macro 612" group.byte 0x665++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH613,Uncommitted Supervisorly Flash in Macro 613" group.byte 0x666++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH614,Uncommitted Supervisorly Flash in Macro 614" group.byte 0x667++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH615,Uncommitted Supervisorly Flash in Macro 615" group.byte 0x668++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH616,Uncommitted Supervisorly Flash in Macro 616" group.byte 0x669++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH617,Uncommitted Supervisorly Flash in Macro 617" group.byte 0x66A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH618,Uncommitted Supervisorly Flash in Macro 618" group.byte 0x66B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH619,Uncommitted Supervisorly Flash in Macro 619" group.byte 0x66C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH620,Uncommitted Supervisorly Flash in Macro 620" group.byte 0x66D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH621,Uncommitted Supervisorly Flash in Macro 621" group.byte 0x66E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH622,Uncommitted Supervisorly Flash in Macro 622" group.byte 0x66F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH623,Uncommitted Supervisorly Flash in Macro 623" group.byte 0x670++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH624,Uncommitted Supervisorly Flash in Macro 624" group.byte 0x671++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH625,Uncommitted Supervisorly Flash in Macro 625" group.byte 0x672++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH626,Uncommitted Supervisorly Flash in Macro 626" group.byte 0x673++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH627,Uncommitted Supervisorly Flash in Macro 627" group.byte 0x674++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH628,Uncommitted Supervisorly Flash in Macro 628" group.byte 0x675++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH629,Uncommitted Supervisorly Flash in Macro 629" group.byte 0x676++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH630,Uncommitted Supervisorly Flash in Macro 630" group.byte 0x677++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH631,Uncommitted Supervisorly Flash in Macro 631" group.byte 0x678++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH632,Uncommitted Supervisorly Flash in Macro 632" group.byte 0x679++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH633,Uncommitted Supervisorly Flash in Macro 633" group.byte 0x67A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH634,Uncommitted Supervisorly Flash in Macro 634" group.byte 0x67B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH635,Uncommitted Supervisorly Flash in Macro 635" group.byte 0x67C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH636,Uncommitted Supervisorly Flash in Macro 636" group.byte 0x67D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH637,Uncommitted Supervisorly Flash in Macro 637" group.byte 0x67E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH638,Uncommitted Supervisorly Flash in Macro 638" group.byte 0x67F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH639,Uncommitted Supervisorly Flash in Macro 639" group.byte 0x680++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH640,Uncommitted Supervisorly Flash in Macro 640" group.byte 0x681++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH641,Uncommitted Supervisorly Flash in Macro 641" group.byte 0x682++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH642,Uncommitted Supervisorly Flash in Macro 642" group.byte 0x683++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH643,Uncommitted Supervisorly Flash in Macro 643" group.byte 0x684++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH644,Uncommitted Supervisorly Flash in Macro 644" group.byte 0x685++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH645,Uncommitted Supervisorly Flash in Macro 645" group.byte 0x686++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH646,Uncommitted Supervisorly Flash in Macro 646" group.byte 0x687++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH647,Uncommitted Supervisorly Flash in Macro 647" group.byte 0x688++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH648,Uncommitted Supervisorly Flash in Macro 648" group.byte 0x689++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH649,Uncommitted Supervisorly Flash in Macro 649" group.byte 0x68A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH650,Uncommitted Supervisorly Flash in Macro 650" group.byte 0x68B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH651,Uncommitted Supervisorly Flash in Macro 651" group.byte 0x68C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH652,Uncommitted Supervisorly Flash in Macro 652" group.byte 0x68D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH653,Uncommitted Supervisorly Flash in Macro 653" group.byte 0x68E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH654,Uncommitted Supervisorly Flash in Macro 654" group.byte 0x68F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH655,Uncommitted Supervisorly Flash in Macro 655" group.byte 0x690++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH656,Uncommitted Supervisorly Flash in Macro 656" group.byte 0x691++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH657,Uncommitted Supervisorly Flash in Macro 657" group.byte 0x692++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH658,Uncommitted Supervisorly Flash in Macro 658" group.byte 0x693++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH659,Uncommitted Supervisorly Flash in Macro 659" group.byte 0x694++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH660,Uncommitted Supervisorly Flash in Macro 660" group.byte 0x695++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH661,Uncommitted Supervisorly Flash in Macro 661" group.byte 0x696++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH662,Uncommitted Supervisorly Flash in Macro 662" group.byte 0x697++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH663,Uncommitted Supervisorly Flash in Macro 663" group.byte 0x698++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH664,Uncommitted Supervisorly Flash in Macro 664" group.byte 0x699++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH665,Uncommitted Supervisorly Flash in Macro 665" group.byte 0x69A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH666,Uncommitted Supervisorly Flash in Macro 666" group.byte 0x69B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH667,Uncommitted Supervisorly Flash in Macro 667" group.byte 0x69C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH668,Uncommitted Supervisorly Flash in Macro 668" group.byte 0x69D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH669,Uncommitted Supervisorly Flash in Macro 669" group.byte 0x69E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH670,Uncommitted Supervisorly Flash in Macro 670" group.byte 0x69F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH671,Uncommitted Supervisorly Flash in Macro 671" group.byte 0x6A0++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH672,Uncommitted Supervisorly Flash in Macro 672" group.byte 0x6A1++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH673,Uncommitted Supervisorly Flash in Macro 673" group.byte 0x6A2++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH674,Uncommitted Supervisorly Flash in Macro 674" group.byte 0x6A3++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH675,Uncommitted Supervisorly Flash in Macro 675" group.byte 0x6A4++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH676,Uncommitted Supervisorly Flash in Macro 676" group.byte 0x6A5++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH677,Uncommitted Supervisorly Flash in Macro 677" group.byte 0x6A6++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH678,Uncommitted Supervisorly Flash in Macro 678" group.byte 0x6A7++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH679,Uncommitted Supervisorly Flash in Macro 679" group.byte 0x6A8++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH680,Uncommitted Supervisorly Flash in Macro 680" group.byte 0x6A9++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH681,Uncommitted Supervisorly Flash in Macro 681" group.byte 0x6AA++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH682,Uncommitted Supervisorly Flash in Macro 682" group.byte 0x6AB++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH683,Uncommitted Supervisorly Flash in Macro 683" group.byte 0x6AC++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH684,Uncommitted Supervisorly Flash in Macro 684" group.byte 0x6AD++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH685,Uncommitted Supervisorly Flash in Macro 685" group.byte 0x6AE++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH686,Uncommitted Supervisorly Flash in Macro 686" group.byte 0x6AF++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH687,Uncommitted Supervisorly Flash in Macro 687" group.byte 0x6B0++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH688,Uncommitted Supervisorly Flash in Macro 688" group.byte 0x6B1++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH689,Uncommitted Supervisorly Flash in Macro 689" group.byte 0x6B2++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH690,Uncommitted Supervisorly Flash in Macro 690" group.byte 0x6B3++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH691,Uncommitted Supervisorly Flash in Macro 691" group.byte 0x6B4++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH692,Uncommitted Supervisorly Flash in Macro 692" group.byte 0x6B5++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH693,Uncommitted Supervisorly Flash in Macro 693" group.byte 0x6B6++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH694,Uncommitted Supervisorly Flash in Macro 694" group.byte 0x6B7++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH695,Uncommitted Supervisorly Flash in Macro 695" group.byte 0x6B8++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH696,Uncommitted Supervisorly Flash in Macro 696" group.byte 0x6B9++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH697,Uncommitted Supervisorly Flash in Macro 697" group.byte 0x6BA++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH698,Uncommitted Supervisorly Flash in Macro 698" group.byte 0x6BB++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH699,Uncommitted Supervisorly Flash in Macro 699" group.byte 0x6BC++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH700,Uncommitted Supervisorly Flash in Macro 700" group.byte 0x6BD++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH701,Uncommitted Supervisorly Flash in Macro 701" group.byte 0x6BE++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH702,Uncommitted Supervisorly Flash in Macro 702" group.byte 0x6BF++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH703,Uncommitted Supervisorly Flash in Macro 703" group.byte 0x6C0++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH704,Uncommitted Supervisorly Flash in Macro 704" group.byte 0x6C1++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH705,Uncommitted Supervisorly Flash in Macro 705" group.byte 0x6C2++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH706,Uncommitted Supervisorly Flash in Macro 706" group.byte 0x6C3++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH707,Uncommitted Supervisorly Flash in Macro 707" group.byte 0x6C4++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH708,Uncommitted Supervisorly Flash in Macro 708" group.byte 0x6C5++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH709,Uncommitted Supervisorly Flash in Macro 709" group.byte 0x6C6++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH710,Uncommitted Supervisorly Flash in Macro 710" group.byte 0x6C7++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH711,Uncommitted Supervisorly Flash in Macro 711" group.byte 0x6C8++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH712,Uncommitted Supervisorly Flash in Macro 712" group.byte 0x6C9++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH713,Uncommitted Supervisorly Flash in Macro 713" group.byte 0x6CA++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH714,Uncommitted Supervisorly Flash in Macro 714" group.byte 0x6CB++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH715,Uncommitted Supervisorly Flash in Macro 715" group.byte 0x6CC++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH716,Uncommitted Supervisorly Flash in Macro 716" group.byte 0x6CD++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH717,Uncommitted Supervisorly Flash in Macro 717" group.byte 0x6CE++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH718,Uncommitted Supervisorly Flash in Macro 718" group.byte 0x6CF++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH719,Uncommitted Supervisorly Flash in Macro 719" group.byte 0x6D0++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH720,Uncommitted Supervisorly Flash in Macro 720" group.byte 0x6D1++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH721,Uncommitted Supervisorly Flash in Macro 721" group.byte 0x6D2++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH722,Uncommitted Supervisorly Flash in Macro 722" group.byte 0x6D3++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH723,Uncommitted Supervisorly Flash in Macro 723" group.byte 0x6D4++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH724,Uncommitted Supervisorly Flash in Macro 724" group.byte 0x6D5++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH725,Uncommitted Supervisorly Flash in Macro 725" group.byte 0x6D6++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH726,Uncommitted Supervisorly Flash in Macro 726" group.byte 0x6D7++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH727,Uncommitted Supervisorly Flash in Macro 727" group.byte 0x6D8++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH728,Uncommitted Supervisorly Flash in Macro 728" group.byte 0x6D9++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH729,Uncommitted Supervisorly Flash in Macro 729" group.byte 0x6DA++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH730,Uncommitted Supervisorly Flash in Macro 730" group.byte 0x6DB++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH731,Uncommitted Supervisorly Flash in Macro 731" group.byte 0x6DC++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH732,Uncommitted Supervisorly Flash in Macro 732" group.byte 0x6DD++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH733,Uncommitted Supervisorly Flash in Macro 733" group.byte 0x6DE++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH734,Uncommitted Supervisorly Flash in Macro 734" group.byte 0x6DF++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH735,Uncommitted Supervisorly Flash in Macro 735" group.byte 0x6E0++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH736,Uncommitted Supervisorly Flash in Macro 736" group.byte 0x6E1++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH737,Uncommitted Supervisorly Flash in Macro 737" group.byte 0x6E2++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH738,Uncommitted Supervisorly Flash in Macro 738" group.byte 0x6E3++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH739,Uncommitted Supervisorly Flash in Macro 739" group.byte 0x6E4++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH740,Uncommitted Supervisorly Flash in Macro 740" group.byte 0x6E5++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH741,Uncommitted Supervisorly Flash in Macro 741" group.byte 0x6E6++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH742,Uncommitted Supervisorly Flash in Macro 742" group.byte 0x6E7++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH743,Uncommitted Supervisorly Flash in Macro 743" group.byte 0x6E8++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH744,Uncommitted Supervisorly Flash in Macro 744" group.byte 0x6E9++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH745,Uncommitted Supervisorly Flash in Macro 745" group.byte 0x6EA++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH746,Uncommitted Supervisorly Flash in Macro 746" group.byte 0x6EB++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH747,Uncommitted Supervisorly Flash in Macro 747" group.byte 0x6EC++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH748,Uncommitted Supervisorly Flash in Macro 748" group.byte 0x6ED++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH749,Uncommitted Supervisorly Flash in Macro 749" group.byte 0x6EE++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH750,Uncommitted Supervisorly Flash in Macro 750" group.byte 0x6EF++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH751,Uncommitted Supervisorly Flash in Macro 751" group.byte 0x6F0++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH752,Uncommitted Supervisorly Flash in Macro 752" group.byte 0x6F1++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH753,Uncommitted Supervisorly Flash in Macro 753" group.byte 0x6F2++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH754,Uncommitted Supervisorly Flash in Macro 754" group.byte 0x6F3++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH755,Uncommitted Supervisorly Flash in Macro 755" group.byte 0x6F4++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH756,Uncommitted Supervisorly Flash in Macro 756" group.byte 0x6F5++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH757,Uncommitted Supervisorly Flash in Macro 757" group.byte 0x6F6++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH758,Uncommitted Supervisorly Flash in Macro 758" group.byte 0x6F7++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH759,Uncommitted Supervisorly Flash in Macro 759" group.byte 0x6F8++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH760,Uncommitted Supervisorly Flash in Macro 760" group.byte 0x6F9++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH761,Uncommitted Supervisorly Flash in Macro 761" group.byte 0x6FA++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH762,Uncommitted Supervisorly Flash in Macro 762" group.byte 0x6FB++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH763,Uncommitted Supervisorly Flash in Macro 763" group.byte 0x6FC++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH764,Uncommitted Supervisorly Flash in Macro 764" group.byte 0x6FD++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH765,Uncommitted Supervisorly Flash in Macro 765" group.byte 0x6FE++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH766,Uncommitted Supervisorly Flash in Macro 766" group.byte 0x6FF++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH767,Uncommitted Supervisorly Flash in Macro 767" group.byte 0x700++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH768,Uncommitted Supervisorly Flash in Macro 768" group.byte 0x701++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH769,Uncommitted Supervisorly Flash in Macro 769" group.byte 0x702++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH770,Uncommitted Supervisorly Flash in Macro 770" group.byte 0x703++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH771,Uncommitted Supervisorly Flash in Macro 771" group.byte 0x704++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH772,Uncommitted Supervisorly Flash in Macro 772" group.byte 0x705++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH773,Uncommitted Supervisorly Flash in Macro 773" group.byte 0x706++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH774,Uncommitted Supervisorly Flash in Macro 774" group.byte 0x707++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH775,Uncommitted Supervisorly Flash in Macro 775" group.byte 0x708++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH776,Uncommitted Supervisorly Flash in Macro 776" group.byte 0x709++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH777,Uncommitted Supervisorly Flash in Macro 777" group.byte 0x70A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH778,Uncommitted Supervisorly Flash in Macro 778" group.byte 0x70B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH779,Uncommitted Supervisorly Flash in Macro 779" group.byte 0x70C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH780,Uncommitted Supervisorly Flash in Macro 780" group.byte 0x70D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH781,Uncommitted Supervisorly Flash in Macro 781" group.byte 0x70E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH782,Uncommitted Supervisorly Flash in Macro 782" group.byte 0x70F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH783,Uncommitted Supervisorly Flash in Macro 783" group.byte 0x710++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH784,Uncommitted Supervisorly Flash in Macro 784" group.byte 0x711++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH785,Uncommitted Supervisorly Flash in Macro 785" group.byte 0x712++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH786,Uncommitted Supervisorly Flash in Macro 786" group.byte 0x713++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH787,Uncommitted Supervisorly Flash in Macro 787" group.byte 0x714++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH788,Uncommitted Supervisorly Flash in Macro 788" group.byte 0x715++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH789,Uncommitted Supervisorly Flash in Macro 789" group.byte 0x716++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH790,Uncommitted Supervisorly Flash in Macro 790" group.byte 0x717++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH791,Uncommitted Supervisorly Flash in Macro 791" group.byte 0x718++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH792,Uncommitted Supervisorly Flash in Macro 792" group.byte 0x719++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH793,Uncommitted Supervisorly Flash in Macro 793" group.byte 0x71A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH794,Uncommitted Supervisorly Flash in Macro 794" group.byte 0x71B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH795,Uncommitted Supervisorly Flash in Macro 795" group.byte 0x71C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH796,Uncommitted Supervisorly Flash in Macro 796" group.byte 0x71D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH797,Uncommitted Supervisorly Flash in Macro 797" group.byte 0x71E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH798,Uncommitted Supervisorly Flash in Macro 798" group.byte 0x71F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH799,Uncommitted Supervisorly Flash in Macro 799" group.byte 0x720++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH800,Uncommitted Supervisorly Flash in Macro 800" group.byte 0x721++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH801,Uncommitted Supervisorly Flash in Macro 801" group.byte 0x722++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH802,Uncommitted Supervisorly Flash in Macro 802" group.byte 0x723++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH803,Uncommitted Supervisorly Flash in Macro 803" group.byte 0x724++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH804,Uncommitted Supervisorly Flash in Macro 804" group.byte 0x725++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH805,Uncommitted Supervisorly Flash in Macro 805" group.byte 0x726++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH806,Uncommitted Supervisorly Flash in Macro 806" group.byte 0x727++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH807,Uncommitted Supervisorly Flash in Macro 807" group.byte 0x728++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH808,Uncommitted Supervisorly Flash in Macro 808" group.byte 0x729++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH809,Uncommitted Supervisorly Flash in Macro 809" group.byte 0x72A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH810,Uncommitted Supervisorly Flash in Macro 810" group.byte 0x72B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH811,Uncommitted Supervisorly Flash in Macro 811" group.byte 0x72C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH812,Uncommitted Supervisorly Flash in Macro 812" group.byte 0x72D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH813,Uncommitted Supervisorly Flash in Macro 813" group.byte 0x72E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH814,Uncommitted Supervisorly Flash in Macro 814" group.byte 0x72F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH815,Uncommitted Supervisorly Flash in Macro 815" group.byte 0x730++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH816,Uncommitted Supervisorly Flash in Macro 816" group.byte 0x731++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH817,Uncommitted Supervisorly Flash in Macro 817" group.byte 0x732++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH818,Uncommitted Supervisorly Flash in Macro 818" group.byte 0x733++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH819,Uncommitted Supervisorly Flash in Macro 819" group.byte 0x734++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH820,Uncommitted Supervisorly Flash in Macro 820" group.byte 0x735++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH821,Uncommitted Supervisorly Flash in Macro 821" group.byte 0x736++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH822,Uncommitted Supervisorly Flash in Macro 822" group.byte 0x737++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH823,Uncommitted Supervisorly Flash in Macro 823" group.byte 0x738++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH824,Uncommitted Supervisorly Flash in Macro 824" group.byte 0x739++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH825,Uncommitted Supervisorly Flash in Macro 825" group.byte 0x73A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH826,Uncommitted Supervisorly Flash in Macro 826" group.byte 0x73B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH827,Uncommitted Supervisorly Flash in Macro 827" group.byte 0x73C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH828,Uncommitted Supervisorly Flash in Macro 828" group.byte 0x73D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH829,Uncommitted Supervisorly Flash in Macro 829" group.byte 0x73E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH830,Uncommitted Supervisorly Flash in Macro 830" group.byte 0x73F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH831,Uncommitted Supervisorly Flash in Macro 831" group.byte 0x740++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH832,Uncommitted Supervisorly Flash in Macro 832" group.byte 0x741++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH833,Uncommitted Supervisorly Flash in Macro 833" group.byte 0x742++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH834,Uncommitted Supervisorly Flash in Macro 834" group.byte 0x743++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH835,Uncommitted Supervisorly Flash in Macro 835" group.byte 0x744++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH836,Uncommitted Supervisorly Flash in Macro 836" group.byte 0x745++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH837,Uncommitted Supervisorly Flash in Macro 837" group.byte 0x746++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH838,Uncommitted Supervisorly Flash in Macro 838" group.byte 0x747++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH839,Uncommitted Supervisorly Flash in Macro 839" group.byte 0x748++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH840,Uncommitted Supervisorly Flash in Macro 840" group.byte 0x749++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH841,Uncommitted Supervisorly Flash in Macro 841" group.byte 0x74A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH842,Uncommitted Supervisorly Flash in Macro 842" group.byte 0x74B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH843,Uncommitted Supervisorly Flash in Macro 843" group.byte 0x74C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH844,Uncommitted Supervisorly Flash in Macro 844" group.byte 0x74D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH845,Uncommitted Supervisorly Flash in Macro 845" group.byte 0x74E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH846,Uncommitted Supervisorly Flash in Macro 846" group.byte 0x74F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH847,Uncommitted Supervisorly Flash in Macro 847" group.byte 0x750++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH848,Uncommitted Supervisorly Flash in Macro 848" group.byte 0x751++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH849,Uncommitted Supervisorly Flash in Macro 849" group.byte 0x752++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH850,Uncommitted Supervisorly Flash in Macro 850" group.byte 0x753++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH851,Uncommitted Supervisorly Flash in Macro 851" group.byte 0x754++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH852,Uncommitted Supervisorly Flash in Macro 852" group.byte 0x755++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH853,Uncommitted Supervisorly Flash in Macro 853" group.byte 0x756++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH854,Uncommitted Supervisorly Flash in Macro 854" group.byte 0x757++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH855,Uncommitted Supervisorly Flash in Macro 855" group.byte 0x758++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH856,Uncommitted Supervisorly Flash in Macro 856" group.byte 0x759++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH857,Uncommitted Supervisorly Flash in Macro 857" group.byte 0x75A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH858,Uncommitted Supervisorly Flash in Macro 858" group.byte 0x75B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH859,Uncommitted Supervisorly Flash in Macro 859" group.byte 0x75C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH860,Uncommitted Supervisorly Flash in Macro 860" group.byte 0x75D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH861,Uncommitted Supervisorly Flash in Macro 861" group.byte 0x75E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH862,Uncommitted Supervisorly Flash in Macro 862" group.byte 0x75F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH863,Uncommitted Supervisorly Flash in Macro 863" group.byte 0x760++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH864,Uncommitted Supervisorly Flash in Macro 864" group.byte 0x761++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH865,Uncommitted Supervisorly Flash in Macro 865" group.byte 0x762++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH866,Uncommitted Supervisorly Flash in Macro 866" group.byte 0x763++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH867,Uncommitted Supervisorly Flash in Macro 867" group.byte 0x764++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH868,Uncommitted Supervisorly Flash in Macro 868" group.byte 0x765++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH869,Uncommitted Supervisorly Flash in Macro 869" group.byte 0x766++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH870,Uncommitted Supervisorly Flash in Macro 870" group.byte 0x767++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH871,Uncommitted Supervisorly Flash in Macro 871" group.byte 0x768++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH872,Uncommitted Supervisorly Flash in Macro 872" group.byte 0x769++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH873,Uncommitted Supervisorly Flash in Macro 873" group.byte 0x76A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH874,Uncommitted Supervisorly Flash in Macro 874" group.byte 0x76B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH875,Uncommitted Supervisorly Flash in Macro 875" group.byte 0x76C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH876,Uncommitted Supervisorly Flash in Macro 876" group.byte 0x76D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH877,Uncommitted Supervisorly Flash in Macro 877" group.byte 0x76E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH878,Uncommitted Supervisorly Flash in Macro 878" group.byte 0x76F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH879,Uncommitted Supervisorly Flash in Macro 879" group.byte 0x770++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH880,Uncommitted Supervisorly Flash in Macro 880" group.byte 0x771++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH881,Uncommitted Supervisorly Flash in Macro 881" group.byte 0x772++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH882,Uncommitted Supervisorly Flash in Macro 882" group.byte 0x773++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH883,Uncommitted Supervisorly Flash in Macro 883" group.byte 0x774++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH884,Uncommitted Supervisorly Flash in Macro 884" group.byte 0x775++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH885,Uncommitted Supervisorly Flash in Macro 885" group.byte 0x776++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH886,Uncommitted Supervisorly Flash in Macro 886" group.byte 0x777++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH887,Uncommitted Supervisorly Flash in Macro 887" group.byte 0x778++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH888,Uncommitted Supervisorly Flash in Macro 888" group.byte 0x779++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH889,Uncommitted Supervisorly Flash in Macro 889" group.byte 0x77A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH890,Uncommitted Supervisorly Flash in Macro 890" group.byte 0x77B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH891,Uncommitted Supervisorly Flash in Macro 891" group.byte 0x77C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH892,Uncommitted Supervisorly Flash in Macro 892" group.byte 0x77D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH893,Uncommitted Supervisorly Flash in Macro 893" group.byte 0x77E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH894,Uncommitted Supervisorly Flash in Macro 894" group.byte 0x77F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH895,Uncommitted Supervisorly Flash in Macro 895" group.byte 0x780++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH896,Uncommitted Supervisorly Flash in Macro 896" group.byte 0x781++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH897,Uncommitted Supervisorly Flash in Macro 897" group.byte 0x782++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH898,Uncommitted Supervisorly Flash in Macro 898" group.byte 0x783++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH899,Uncommitted Supervisorly Flash in Macro 899" group.byte 0x784++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH900,Uncommitted Supervisorly Flash in Macro 900" group.byte 0x785++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH901,Uncommitted Supervisorly Flash in Macro 901" group.byte 0x786++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH902,Uncommitted Supervisorly Flash in Macro 902" group.byte 0x787++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH903,Uncommitted Supervisorly Flash in Macro 903" group.byte 0x788++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH904,Uncommitted Supervisorly Flash in Macro 904" group.byte 0x789++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH905,Uncommitted Supervisorly Flash in Macro 905" group.byte 0x78A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH906,Uncommitted Supervisorly Flash in Macro 906" group.byte 0x78B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH907,Uncommitted Supervisorly Flash in Macro 907" group.byte 0x78C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH908,Uncommitted Supervisorly Flash in Macro 908" group.byte 0x78D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH909,Uncommitted Supervisorly Flash in Macro 909" group.byte 0x78E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH910,Uncommitted Supervisorly Flash in Macro 910" group.byte 0x78F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH911,Uncommitted Supervisorly Flash in Macro 911" group.byte 0x790++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH912,Uncommitted Supervisorly Flash in Macro 912" group.byte 0x791++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH913,Uncommitted Supervisorly Flash in Macro 913" group.byte 0x792++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH914,Uncommitted Supervisorly Flash in Macro 914" group.byte 0x793++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH915,Uncommitted Supervisorly Flash in Macro 915" group.byte 0x794++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH916,Uncommitted Supervisorly Flash in Macro 916" group.byte 0x795++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH917,Uncommitted Supervisorly Flash in Macro 917" group.byte 0x796++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH918,Uncommitted Supervisorly Flash in Macro 918" group.byte 0x797++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH919,Uncommitted Supervisorly Flash in Macro 919" group.byte 0x798++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH920,Uncommitted Supervisorly Flash in Macro 920" group.byte 0x799++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH921,Uncommitted Supervisorly Flash in Macro 921" group.byte 0x79A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH922,Uncommitted Supervisorly Flash in Macro 922" group.byte 0x79B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH923,Uncommitted Supervisorly Flash in Macro 923" group.byte 0x79C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH924,Uncommitted Supervisorly Flash in Macro 924" group.byte 0x79D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH925,Uncommitted Supervisorly Flash in Macro 925" group.byte 0x79E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH926,Uncommitted Supervisorly Flash in Macro 926" group.byte 0x79F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH927,Uncommitted Supervisorly Flash in Macro 927" group.byte 0x7A0++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH928,Uncommitted Supervisorly Flash in Macro 928" group.byte 0x7A1++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH929,Uncommitted Supervisorly Flash in Macro 929" group.byte 0x7A2++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH930,Uncommitted Supervisorly Flash in Macro 930" group.byte 0x7A3++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH931,Uncommitted Supervisorly Flash in Macro 931" group.byte 0x7A4++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH932,Uncommitted Supervisorly Flash in Macro 932" group.byte 0x7A5++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH933,Uncommitted Supervisorly Flash in Macro 933" group.byte 0x7A6++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH934,Uncommitted Supervisorly Flash in Macro 934" group.byte 0x7A7++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH935,Uncommitted Supervisorly Flash in Macro 935" group.byte 0x7A8++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH936,Uncommitted Supervisorly Flash in Macro 936" group.byte 0x7A9++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH937,Uncommitted Supervisorly Flash in Macro 937" group.byte 0x7AA++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH938,Uncommitted Supervisorly Flash in Macro 938" group.byte 0x7AB++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH939,Uncommitted Supervisorly Flash in Macro 939" group.byte 0x7AC++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH940,Uncommitted Supervisorly Flash in Macro 940" group.byte 0x7AD++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH941,Uncommitted Supervisorly Flash in Macro 941" group.byte 0x7AE++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH942,Uncommitted Supervisorly Flash in Macro 942" group.byte 0x7AF++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH943,Uncommitted Supervisorly Flash in Macro 943" group.byte 0x7B0++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH944,Uncommitted Supervisorly Flash in Macro 944" group.byte 0x7B1++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH945,Uncommitted Supervisorly Flash in Macro 945" group.byte 0x7B2++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH946,Uncommitted Supervisorly Flash in Macro 946" group.byte 0x7B3++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH947,Uncommitted Supervisorly Flash in Macro 947" group.byte 0x7B4++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH948,Uncommitted Supervisorly Flash in Macro 948" group.byte 0x7B5++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH949,Uncommitted Supervisorly Flash in Macro 949" group.byte 0x7B6++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH950,Uncommitted Supervisorly Flash in Macro 950" group.byte 0x7B7++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH951,Uncommitted Supervisorly Flash in Macro 951" group.byte 0x7B8++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH952,Uncommitted Supervisorly Flash in Macro 952" group.byte 0x7B9++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH953,Uncommitted Supervisorly Flash in Macro 953" group.byte 0x7BA++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH954,Uncommitted Supervisorly Flash in Macro 954" group.byte 0x7BB++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH955,Uncommitted Supervisorly Flash in Macro 955" group.byte 0x7BC++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH956,Uncommitted Supervisorly Flash in Macro 956" group.byte 0x7BD++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH957,Uncommitted Supervisorly Flash in Macro 957" group.byte 0x7BE++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH958,Uncommitted Supervisorly Flash in Macro 958" group.byte 0x7BF++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH959,Uncommitted Supervisorly Flash in Macro 959" group.byte 0x7C0++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH960,Uncommitted Supervisorly Flash in Macro 960" group.byte 0x7C1++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH961,Uncommitted Supervisorly Flash in Macro 961" group.byte 0x7C2++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH962,Uncommitted Supervisorly Flash in Macro 962" group.byte 0x7C3++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH963,Uncommitted Supervisorly Flash in Macro 963" group.byte 0x7C4++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH964,Uncommitted Supervisorly Flash in Macro 964" group.byte 0x7C5++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH965,Uncommitted Supervisorly Flash in Macro 965" group.byte 0x7C6++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH966,Uncommitted Supervisorly Flash in Macro 966" group.byte 0x7C7++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH967,Uncommitted Supervisorly Flash in Macro 967" group.byte 0x7C8++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH968,Uncommitted Supervisorly Flash in Macro 968" group.byte 0x7C9++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH969,Uncommitted Supervisorly Flash in Macro 969" group.byte 0x7CA++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH970,Uncommitted Supervisorly Flash in Macro 970" group.byte 0x7CB++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH971,Uncommitted Supervisorly Flash in Macro 971" group.byte 0x7CC++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH972,Uncommitted Supervisorly Flash in Macro 972" group.byte 0x7CD++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH973,Uncommitted Supervisorly Flash in Macro 973" group.byte 0x7CE++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH974,Uncommitted Supervisorly Flash in Macro 974" group.byte 0x7CF++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH975,Uncommitted Supervisorly Flash in Macro 975" group.byte 0x7D0++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH976,Uncommitted Supervisorly Flash in Macro 976" group.byte 0x7D1++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH977,Uncommitted Supervisorly Flash in Macro 977" group.byte 0x7D2++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH978,Uncommitted Supervisorly Flash in Macro 978" group.byte 0x7D3++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH979,Uncommitted Supervisorly Flash in Macro 979" group.byte 0x7D4++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH980,Uncommitted Supervisorly Flash in Macro 980" group.byte 0x7D5++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH981,Uncommitted Supervisorly Flash in Macro 981" group.byte 0x7D6++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH982,Uncommitted Supervisorly Flash in Macro 982" group.byte 0x7D7++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH983,Uncommitted Supervisorly Flash in Macro 983" group.byte 0x7D8++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH984,Uncommitted Supervisorly Flash in Macro 984" group.byte 0x7D9++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH985,Uncommitted Supervisorly Flash in Macro 985" group.byte 0x7DA++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH986,Uncommitted Supervisorly Flash in Macro 986" group.byte 0x7DB++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH987,Uncommitted Supervisorly Flash in Macro 987" group.byte 0x7DC++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH988,Uncommitted Supervisorly Flash in Macro 988" group.byte 0x7DD++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH989,Uncommitted Supervisorly Flash in Macro 989" group.byte 0x7DE++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH990,Uncommitted Supervisorly Flash in Macro 990" group.byte 0x7DF++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH991,Uncommitted Supervisorly Flash in Macro 991" group.byte 0x7E0++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH992,Uncommitted Supervisorly Flash in Macro 992" group.byte 0x7E1++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH993,Uncommitted Supervisorly Flash in Macro 993" group.byte 0x7E2++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH994,Uncommitted Supervisorly Flash in Macro 994" group.byte 0x7E3++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH995,Uncommitted Supervisorly Flash in Macro 995" group.byte 0x7E4++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH996,Uncommitted Supervisorly Flash in Macro 996" group.byte 0x7E5++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH997,Uncommitted Supervisorly Flash in Macro 997" group.byte 0x7E6++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH998,Uncommitted Supervisorly Flash in Macro 998" group.byte 0x7E7++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH999,Uncommitted Supervisorly Flash in Macro 999" group.byte 0x7E8++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1000,Uncommitted Supervisorly Flash in Macro 1000" group.byte 0x7E9++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1001,Uncommitted Supervisorly Flash in Macro 1001" group.byte 0x7EA++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1002,Uncommitted Supervisorly Flash in Macro 1002" group.byte 0x7EB++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1003,Uncommitted Supervisorly Flash in Macro 1003" group.byte 0x7EC++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1004,Uncommitted Supervisorly Flash in Macro 1004" group.byte 0x7ED++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1005,Uncommitted Supervisorly Flash in Macro 1005" group.byte 0x7EE++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1006,Uncommitted Supervisorly Flash in Macro 1006" group.byte 0x7EF++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1007,Uncommitted Supervisorly Flash in Macro 1007" group.byte 0x7F0++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1008,Uncommitted Supervisorly Flash in Macro 1008" group.byte 0x7F1++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1009,Uncommitted Supervisorly Flash in Macro 1009" group.byte 0x7F2++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1010,Uncommitted Supervisorly Flash in Macro 1010" group.byte 0x7F3++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1011,Uncommitted Supervisorly Flash in Macro 1011" group.byte 0x7F4++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1012,Uncommitted Supervisorly Flash in Macro 1012" group.byte 0x7F5++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1013,Uncommitted Supervisorly Flash in Macro 1013" group.byte 0x7F6++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1014,Uncommitted Supervisorly Flash in Macro 1014" group.byte 0x7F7++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1015,Uncommitted Supervisorly Flash in Macro 1015" group.byte 0x7F8++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1016,Uncommitted Supervisorly Flash in Macro 1016" group.byte 0x7F9++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1017,Uncommitted Supervisorly Flash in Macro 1017" group.byte 0x7FA++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1018,Uncommitted Supervisorly Flash in Macro 1018" group.byte 0x7FB++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1019,Uncommitted Supervisorly Flash in Macro 1019" group.byte 0x7FC++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1020,Uncommitted Supervisorly Flash in Macro 1020" group.byte 0x7FD++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1021,Uncommitted Supervisorly Flash in Macro 1021" group.byte 0x7FE++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1022,Uncommitted Supervisorly Flash in Macro 1022" group.byte 0x7FF++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1023,Uncommitted Supervisorly Flash in Macro 1023" else group.byte 0x350++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH0,Uncommitted Supervisorly Flash in Macro 0" group.byte 0x351++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1,Uncommitted Supervisorly Flash in Macro 1" group.byte 0x352++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH2,Uncommitted Supervisorly Flash in Macro 2" group.byte 0x353++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH3,Uncommitted Supervisorly Flash in Macro 3" group.byte 0x354++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH4,Uncommitted Supervisorly Flash in Macro 4" group.byte 0x355++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH5,Uncommitted Supervisorly Flash in Macro 5" group.byte 0x356++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH6,Uncommitted Supervisorly Flash in Macro 6" group.byte 0x357++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH7,Uncommitted Supervisorly Flash in Macro 7" group.byte 0x358++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH8,Uncommitted Supervisorly Flash in Macro 8" group.byte 0x359++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH9,Uncommitted Supervisorly Flash in Macro 9" group.byte 0x35A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH10,Uncommitted Supervisorly Flash in Macro 10" group.byte 0x35B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH11,Uncommitted Supervisorly Flash in Macro 11" group.byte 0x35C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH12,Uncommitted Supervisorly Flash in Macro 12" group.byte 0x35D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH13,Uncommitted Supervisorly Flash in Macro 13" group.byte 0x35E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH14,Uncommitted Supervisorly Flash in Macro 14" group.byte 0x35F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH15,Uncommitted Supervisorly Flash in Macro 15" group.byte 0x360++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH16,Uncommitted Supervisorly Flash in Macro 16" group.byte 0x361++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH17,Uncommitted Supervisorly Flash in Macro 17" group.byte 0x362++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH18,Uncommitted Supervisorly Flash in Macro 18" group.byte 0x363++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH19,Uncommitted Supervisorly Flash in Macro 19" group.byte 0x364++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH20,Uncommitted Supervisorly Flash in Macro 20" group.byte 0x365++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH21,Uncommitted Supervisorly Flash in Macro 21" group.byte 0x366++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH22,Uncommitted Supervisorly Flash in Macro 22" group.byte 0x367++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH23,Uncommitted Supervisorly Flash in Macro 23" group.byte 0x368++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH24,Uncommitted Supervisorly Flash in Macro 24" group.byte 0x369++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH25,Uncommitted Supervisorly Flash in Macro 25" group.byte 0x36A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH26,Uncommitted Supervisorly Flash in Macro 26" group.byte 0x36B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH27,Uncommitted Supervisorly Flash in Macro 27" group.byte 0x36C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH28,Uncommitted Supervisorly Flash in Macro 28" group.byte 0x36D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH29,Uncommitted Supervisorly Flash in Macro 29" group.byte 0x36E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH30,Uncommitted Supervisorly Flash in Macro 30" group.byte 0x36F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH31,Uncommitted Supervisorly Flash in Macro 31" group.byte 0x370++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH32,Uncommitted Supervisorly Flash in Macro 32" group.byte 0x371++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH33,Uncommitted Supervisorly Flash in Macro 33" group.byte 0x372++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH34,Uncommitted Supervisorly Flash in Macro 34" group.byte 0x373++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH35,Uncommitted Supervisorly Flash in Macro 35" group.byte 0x374++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH36,Uncommitted Supervisorly Flash in Macro 36" group.byte 0x375++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH37,Uncommitted Supervisorly Flash in Macro 37" group.byte 0x376++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH38,Uncommitted Supervisorly Flash in Macro 38" group.byte 0x377++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH39,Uncommitted Supervisorly Flash in Macro 39" group.byte 0x378++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH40,Uncommitted Supervisorly Flash in Macro 40" group.byte 0x379++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH41,Uncommitted Supervisorly Flash in Macro 41" group.byte 0x37A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH42,Uncommitted Supervisorly Flash in Macro 42" group.byte 0x37B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH43,Uncommitted Supervisorly Flash in Macro 43" group.byte 0x37C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH44,Uncommitted Supervisorly Flash in Macro 44" group.byte 0x37D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH45,Uncommitted Supervisorly Flash in Macro 45" group.byte 0x37E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH46,Uncommitted Supervisorly Flash in Macro 46" group.byte 0x37F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH47,Uncommitted Supervisorly Flash in Macro 47" group.byte 0x380++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH48,Uncommitted Supervisorly Flash in Macro 48" group.byte 0x381++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH49,Uncommitted Supervisorly Flash in Macro 49" group.byte 0x382++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH50,Uncommitted Supervisorly Flash in Macro 50" group.byte 0x383++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH51,Uncommitted Supervisorly Flash in Macro 51" group.byte 0x384++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH52,Uncommitted Supervisorly Flash in Macro 52" group.byte 0x385++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH53,Uncommitted Supervisorly Flash in Macro 53" group.byte 0x386++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH54,Uncommitted Supervisorly Flash in Macro 54" group.byte 0x387++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH55,Uncommitted Supervisorly Flash in Macro 55" group.byte 0x388++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH56,Uncommitted Supervisorly Flash in Macro 56" group.byte 0x389++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH57,Uncommitted Supervisorly Flash in Macro 57" group.byte 0x38A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH58,Uncommitted Supervisorly Flash in Macro 58" group.byte 0x38B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH59,Uncommitted Supervisorly Flash in Macro 59" group.byte 0x38C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH60,Uncommitted Supervisorly Flash in Macro 60" group.byte 0x38D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH61,Uncommitted Supervisorly Flash in Macro 61" group.byte 0x38E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH62,Uncommitted Supervisorly Flash in Macro 62" group.byte 0x38F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH63,Uncommitted Supervisorly Flash in Macro 63" group.byte 0x390++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH64,Uncommitted Supervisorly Flash in Macro 64" group.byte 0x391++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH65,Uncommitted Supervisorly Flash in Macro 65" group.byte 0x392++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH66,Uncommitted Supervisorly Flash in Macro 66" group.byte 0x393++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH67,Uncommitted Supervisorly Flash in Macro 67" group.byte 0x394++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH68,Uncommitted Supervisorly Flash in Macro 68" group.byte 0x395++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH69,Uncommitted Supervisorly Flash in Macro 69" group.byte 0x396++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH70,Uncommitted Supervisorly Flash in Macro 70" group.byte 0x397++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH71,Uncommitted Supervisorly Flash in Macro 71" group.byte 0x398++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH72,Uncommitted Supervisorly Flash in Macro 72" group.byte 0x399++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH73,Uncommitted Supervisorly Flash in Macro 73" group.byte 0x39A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH74,Uncommitted Supervisorly Flash in Macro 74" group.byte 0x39B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH75,Uncommitted Supervisorly Flash in Macro 75" group.byte 0x39C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH76,Uncommitted Supervisorly Flash in Macro 76" group.byte 0x39D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH77,Uncommitted Supervisorly Flash in Macro 77" group.byte 0x39E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH78,Uncommitted Supervisorly Flash in Macro 78" group.byte 0x39F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH79,Uncommitted Supervisorly Flash in Macro 79" group.byte 0x3A0++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH80,Uncommitted Supervisorly Flash in Macro 80" group.byte 0x3A1++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH81,Uncommitted Supervisorly Flash in Macro 81" group.byte 0x3A2++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH82,Uncommitted Supervisorly Flash in Macro 82" group.byte 0x3A3++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH83,Uncommitted Supervisorly Flash in Macro 83" group.byte 0x3A4++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH84,Uncommitted Supervisorly Flash in Macro 84" group.byte 0x3A5++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH85,Uncommitted Supervisorly Flash in Macro 85" group.byte 0x3A6++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH86,Uncommitted Supervisorly Flash in Macro 86" group.byte 0x3A7++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH87,Uncommitted Supervisorly Flash in Macro 87" group.byte 0x3A8++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH88,Uncommitted Supervisorly Flash in Macro 88" group.byte 0x3A9++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH89,Uncommitted Supervisorly Flash in Macro 89" group.byte 0x3AA++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH90,Uncommitted Supervisorly Flash in Macro 90" group.byte 0x3AB++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH91,Uncommitted Supervisorly Flash in Macro 91" group.byte 0x3AC++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH92,Uncommitted Supervisorly Flash in Macro 92" group.byte 0x3AD++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH93,Uncommitted Supervisorly Flash in Macro 93" group.byte 0x3AE++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH94,Uncommitted Supervisorly Flash in Macro 94" group.byte 0x3AF++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH95,Uncommitted Supervisorly Flash in Macro 95" group.byte 0x3B0++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH96,Uncommitted Supervisorly Flash in Macro 96" group.byte 0x3B1++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH97,Uncommitted Supervisorly Flash in Macro 97" group.byte 0x3B2++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH98,Uncommitted Supervisorly Flash in Macro 98" group.byte 0x3B3++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH99,Uncommitted Supervisorly Flash in Macro 99" group.byte 0x3B4++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH100,Uncommitted Supervisorly Flash in Macro 100" group.byte 0x3B5++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH101,Uncommitted Supervisorly Flash in Macro 101" group.byte 0x3B6++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH102,Uncommitted Supervisorly Flash in Macro 102" group.byte 0x3B7++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH103,Uncommitted Supervisorly Flash in Macro 103" group.byte 0x3B8++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH104,Uncommitted Supervisorly Flash in Macro 104" group.byte 0x3B9++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH105,Uncommitted Supervisorly Flash in Macro 105" group.byte 0x3BA++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH106,Uncommitted Supervisorly Flash in Macro 106" group.byte 0x3BB++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH107,Uncommitted Supervisorly Flash in Macro 107" group.byte 0x3BC++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH108,Uncommitted Supervisorly Flash in Macro 108" group.byte 0x3BD++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH109,Uncommitted Supervisorly Flash in Macro 109" group.byte 0x3BE++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH110,Uncommitted Supervisorly Flash in Macro 110" group.byte 0x3BF++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH111,Uncommitted Supervisorly Flash in Macro 111" group.byte 0x3C0++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH112,Uncommitted Supervisorly Flash in Macro 112" group.byte 0x3C1++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH113,Uncommitted Supervisorly Flash in Macro 113" group.byte 0x3C2++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH114,Uncommitted Supervisorly Flash in Macro 114" group.byte 0x3C3++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH115,Uncommitted Supervisorly Flash in Macro 115" group.byte 0x3C4++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH116,Uncommitted Supervisorly Flash in Macro 116" group.byte 0x3C5++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH117,Uncommitted Supervisorly Flash in Macro 117" group.byte 0x3C6++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH118,Uncommitted Supervisorly Flash in Macro 118" group.byte 0x3C7++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH119,Uncommitted Supervisorly Flash in Macro 119" group.byte 0x3C8++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH120,Uncommitted Supervisorly Flash in Macro 120" group.byte 0x3C9++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH121,Uncommitted Supervisorly Flash in Macro 121" group.byte 0x3CA++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH122,Uncommitted Supervisorly Flash in Macro 122" group.byte 0x3CB++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH123,Uncommitted Supervisorly Flash in Macro 123" group.byte 0x3CC++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH124,Uncommitted Supervisorly Flash in Macro 124" group.byte 0x3CD++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH125,Uncommitted Supervisorly Flash in Macro 125" group.byte 0x3CE++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH126,Uncommitted Supervisorly Flash in Macro 126" group.byte 0x3CF++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH127,Uncommitted Supervisorly Flash in Macro 127" group.byte 0x3D0++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH128,Uncommitted Supervisorly Flash in Macro 128" group.byte 0x3D1++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH129,Uncommitted Supervisorly Flash in Macro 129" group.byte 0x3D2++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH130,Uncommitted Supervisorly Flash in Macro 130" group.byte 0x3D3++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH131,Uncommitted Supervisorly Flash in Macro 131" group.byte 0x3D4++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH132,Uncommitted Supervisorly Flash in Macro 132" group.byte 0x3D5++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH133,Uncommitted Supervisorly Flash in Macro 133" group.byte 0x3D6++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH134,Uncommitted Supervisorly Flash in Macro 134" group.byte 0x3D7++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH135,Uncommitted Supervisorly Flash in Macro 135" group.byte 0x3D8++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH136,Uncommitted Supervisorly Flash in Macro 136" group.byte 0x3D9++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH137,Uncommitted Supervisorly Flash in Macro 137" group.byte 0x3DA++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH138,Uncommitted Supervisorly Flash in Macro 138" group.byte 0x3DB++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH139,Uncommitted Supervisorly Flash in Macro 139" group.byte 0x3DC++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH140,Uncommitted Supervisorly Flash in Macro 140" group.byte 0x3DD++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH141,Uncommitted Supervisorly Flash in Macro 141" group.byte 0x3DE++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH142,Uncommitted Supervisorly Flash in Macro 142" group.byte 0x3DF++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH143,Uncommitted Supervisorly Flash in Macro 143" group.byte 0x3E0++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH144,Uncommitted Supervisorly Flash in Macro 144" group.byte 0x3E1++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH145,Uncommitted Supervisorly Flash in Macro 145" group.byte 0x3E2++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH146,Uncommitted Supervisorly Flash in Macro 146" group.byte 0x3E3++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH147,Uncommitted Supervisorly Flash in Macro 147" group.byte 0x3E4++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH148,Uncommitted Supervisorly Flash in Macro 148" group.byte 0x3E5++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH149,Uncommitted Supervisorly Flash in Macro 149" group.byte 0x3E6++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH150,Uncommitted Supervisorly Flash in Macro 150" group.byte 0x3E7++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH151,Uncommitted Supervisorly Flash in Macro 151" group.byte 0x3E8++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH152,Uncommitted Supervisorly Flash in Macro 152" group.byte 0x3E9++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH153,Uncommitted Supervisorly Flash in Macro 153" group.byte 0x3EA++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH154,Uncommitted Supervisorly Flash in Macro 154" group.byte 0x3EB++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH155,Uncommitted Supervisorly Flash in Macro 155" group.byte 0x3EC++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH156,Uncommitted Supervisorly Flash in Macro 156" group.byte 0x3ED++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH157,Uncommitted Supervisorly Flash in Macro 157" group.byte 0x3EE++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH158,Uncommitted Supervisorly Flash in Macro 158" group.byte 0x3EF++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH159,Uncommitted Supervisorly Flash in Macro 159" group.byte 0x3F0++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH160,Uncommitted Supervisorly Flash in Macro 160" group.byte 0x3F1++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH161,Uncommitted Supervisorly Flash in Macro 161" group.byte 0x3F2++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH162,Uncommitted Supervisorly Flash in Macro 162" group.byte 0x3F3++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH163,Uncommitted Supervisorly Flash in Macro 163" group.byte 0x3F4++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH164,Uncommitted Supervisorly Flash in Macro 164" group.byte 0x3F5++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH165,Uncommitted Supervisorly Flash in Macro 165" group.byte 0x3F6++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH166,Uncommitted Supervisorly Flash in Macro 166" group.byte 0x3F7++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH167,Uncommitted Supervisorly Flash in Macro 167" group.byte 0x3F8++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH168,Uncommitted Supervisorly Flash in Macro 168" group.byte 0x3F9++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH169,Uncommitted Supervisorly Flash in Macro 169" group.byte 0x3FA++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH170,Uncommitted Supervisorly Flash in Macro 170" group.byte 0x3FB++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH171,Uncommitted Supervisorly Flash in Macro 171" group.byte 0x3FC++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH172,Uncommitted Supervisorly Flash in Macro 172" group.byte 0x3FD++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH173,Uncommitted Supervisorly Flash in Macro 173" group.byte 0x3FE++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH174,Uncommitted Supervisorly Flash in Macro 174" group.byte 0x3FF++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH175,Uncommitted Supervisorly Flash in Macro 175" group.byte 0x400++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH176,Uncommitted Supervisorly Flash in Macro 176" group.byte 0x401++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH177,Uncommitted Supervisorly Flash in Macro 177" group.byte 0x402++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH178,Uncommitted Supervisorly Flash in Macro 178" group.byte 0x403++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH179,Uncommitted Supervisorly Flash in Macro 179" group.byte 0x404++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH180,Uncommitted Supervisorly Flash in Macro 180" group.byte 0x405++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH181,Uncommitted Supervisorly Flash in Macro 181" group.byte 0x406++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH182,Uncommitted Supervisorly Flash in Macro 182" group.byte 0x407++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH183,Uncommitted Supervisorly Flash in Macro 183" group.byte 0x408++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH184,Uncommitted Supervisorly Flash in Macro 184" group.byte 0x409++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH185,Uncommitted Supervisorly Flash in Macro 185" group.byte 0x40A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH186,Uncommitted Supervisorly Flash in Macro 186" group.byte 0x40B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH187,Uncommitted Supervisorly Flash in Macro 187" group.byte 0x40C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH188,Uncommitted Supervisorly Flash in Macro 188" group.byte 0x40D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH189,Uncommitted Supervisorly Flash in Macro 189" group.byte 0x40E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH190,Uncommitted Supervisorly Flash in Macro 190" group.byte 0x40F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH191,Uncommitted Supervisorly Flash in Macro 191" group.byte 0x410++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH192,Uncommitted Supervisorly Flash in Macro 192" group.byte 0x411++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH193,Uncommitted Supervisorly Flash in Macro 193" group.byte 0x412++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH194,Uncommitted Supervisorly Flash in Macro 194" group.byte 0x413++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH195,Uncommitted Supervisorly Flash in Macro 195" group.byte 0x414++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH196,Uncommitted Supervisorly Flash in Macro 196" group.byte 0x415++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH197,Uncommitted Supervisorly Flash in Macro 197" group.byte 0x416++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH198,Uncommitted Supervisorly Flash in Macro 198" group.byte 0x417++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH199,Uncommitted Supervisorly Flash in Macro 199" group.byte 0x418++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH200,Uncommitted Supervisorly Flash in Macro 200" group.byte 0x419++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH201,Uncommitted Supervisorly Flash in Macro 201" group.byte 0x41A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH202,Uncommitted Supervisorly Flash in Macro 202" group.byte 0x41B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH203,Uncommitted Supervisorly Flash in Macro 203" group.byte 0x41C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH204,Uncommitted Supervisorly Flash in Macro 204" group.byte 0x41D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH205,Uncommitted Supervisorly Flash in Macro 205" group.byte 0x41E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH206,Uncommitted Supervisorly Flash in Macro 206" group.byte 0x41F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH207,Uncommitted Supervisorly Flash in Macro 207" group.byte 0x420++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH208,Uncommitted Supervisorly Flash in Macro 208" group.byte 0x421++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH209,Uncommitted Supervisorly Flash in Macro 209" group.byte 0x422++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH210,Uncommitted Supervisorly Flash in Macro 210" group.byte 0x423++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH211,Uncommitted Supervisorly Flash in Macro 211" group.byte 0x424++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH212,Uncommitted Supervisorly Flash in Macro 212" group.byte 0x425++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH213,Uncommitted Supervisorly Flash in Macro 213" group.byte 0x426++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH214,Uncommitted Supervisorly Flash in Macro 214" group.byte 0x427++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH215,Uncommitted Supervisorly Flash in Macro 215" group.byte 0x428++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH216,Uncommitted Supervisorly Flash in Macro 216" group.byte 0x429++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH217,Uncommitted Supervisorly Flash in Macro 217" group.byte 0x42A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH218,Uncommitted Supervisorly Flash in Macro 218" group.byte 0x42B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH219,Uncommitted Supervisorly Flash in Macro 219" group.byte 0x42C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH220,Uncommitted Supervisorly Flash in Macro 220" group.byte 0x42D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH221,Uncommitted Supervisorly Flash in Macro 221" group.byte 0x42E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH222,Uncommitted Supervisorly Flash in Macro 222" group.byte 0x42F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH223,Uncommitted Supervisorly Flash in Macro 223" group.byte 0x430++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH224,Uncommitted Supervisorly Flash in Macro 224" group.byte 0x431++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH225,Uncommitted Supervisorly Flash in Macro 225" group.byte 0x432++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH226,Uncommitted Supervisorly Flash in Macro 226" group.byte 0x433++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH227,Uncommitted Supervisorly Flash in Macro 227" group.byte 0x434++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH228,Uncommitted Supervisorly Flash in Macro 228" group.byte 0x435++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH229,Uncommitted Supervisorly Flash in Macro 229" group.byte 0x436++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH230,Uncommitted Supervisorly Flash in Macro 230" group.byte 0x437++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH231,Uncommitted Supervisorly Flash in Macro 231" group.byte 0x438++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH232,Uncommitted Supervisorly Flash in Macro 232" group.byte 0x439++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH233,Uncommitted Supervisorly Flash in Macro 233" group.byte 0x43A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH234,Uncommitted Supervisorly Flash in Macro 234" group.byte 0x43B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH235,Uncommitted Supervisorly Flash in Macro 235" group.byte 0x43C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH236,Uncommitted Supervisorly Flash in Macro 236" group.byte 0x43D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH237,Uncommitted Supervisorly Flash in Macro 237" group.byte 0x43E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH238,Uncommitted Supervisorly Flash in Macro 238" group.byte 0x43F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH239,Uncommitted Supervisorly Flash in Macro 239" group.byte 0x440++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH240,Uncommitted Supervisorly Flash in Macro 240" group.byte 0x441++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH241,Uncommitted Supervisorly Flash in Macro 241" group.byte 0x442++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH242,Uncommitted Supervisorly Flash in Macro 242" group.byte 0x443++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH243,Uncommitted Supervisorly Flash in Macro 243" group.byte 0x444++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH244,Uncommitted Supervisorly Flash in Macro 244" group.byte 0x445++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH245,Uncommitted Supervisorly Flash in Macro 245" group.byte 0x446++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH246,Uncommitted Supervisorly Flash in Macro 246" group.byte 0x447++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH247,Uncommitted Supervisorly Flash in Macro 247" group.byte 0x448++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH248,Uncommitted Supervisorly Flash in Macro 248" group.byte 0x449++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH249,Uncommitted Supervisorly Flash in Macro 249" group.byte 0x44A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH250,Uncommitted Supervisorly Flash in Macro 250" group.byte 0x44B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH251,Uncommitted Supervisorly Flash in Macro 251" group.byte 0x44C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH252,Uncommitted Supervisorly Flash in Macro 252" group.byte 0x44D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH253,Uncommitted Supervisorly Flash in Macro 253" group.byte 0x44E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH254,Uncommitted Supervisorly Flash in Macro 254" group.byte 0x44F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH255,Uncommitted Supervisorly Flash in Macro 255" group.byte 0x450++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH256,Uncommitted Supervisorly Flash in Macro 256" group.byte 0x451++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH257,Uncommitted Supervisorly Flash in Macro 257" group.byte 0x452++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH258,Uncommitted Supervisorly Flash in Macro 258" group.byte 0x453++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH259,Uncommitted Supervisorly Flash in Macro 259" group.byte 0x454++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH260,Uncommitted Supervisorly Flash in Macro 260" group.byte 0x455++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH261,Uncommitted Supervisorly Flash in Macro 261" group.byte 0x456++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH262,Uncommitted Supervisorly Flash in Macro 262" group.byte 0x457++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH263,Uncommitted Supervisorly Flash in Macro 263" group.byte 0x458++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH264,Uncommitted Supervisorly Flash in Macro 264" group.byte 0x459++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH265,Uncommitted Supervisorly Flash in Macro 265" group.byte 0x45A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH266,Uncommitted Supervisorly Flash in Macro 266" group.byte 0x45B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH267,Uncommitted Supervisorly Flash in Macro 267" group.byte 0x45C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH268,Uncommitted Supervisorly Flash in Macro 268" group.byte 0x45D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH269,Uncommitted Supervisorly Flash in Macro 269" group.byte 0x45E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH270,Uncommitted Supervisorly Flash in Macro 270" group.byte 0x45F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH271,Uncommitted Supervisorly Flash in Macro 271" group.byte 0x460++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH272,Uncommitted Supervisorly Flash in Macro 272" group.byte 0x461++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH273,Uncommitted Supervisorly Flash in Macro 273" group.byte 0x462++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH274,Uncommitted Supervisorly Flash in Macro 274" group.byte 0x463++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH275,Uncommitted Supervisorly Flash in Macro 275" group.byte 0x464++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH276,Uncommitted Supervisorly Flash in Macro 276" group.byte 0x465++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH277,Uncommitted Supervisorly Flash in Macro 277" group.byte 0x466++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH278,Uncommitted Supervisorly Flash in Macro 278" group.byte 0x467++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH279,Uncommitted Supervisorly Flash in Macro 279" group.byte 0x468++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH280,Uncommitted Supervisorly Flash in Macro 280" group.byte 0x469++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH281,Uncommitted Supervisorly Flash in Macro 281" group.byte 0x46A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH282,Uncommitted Supervisorly Flash in Macro 282" group.byte 0x46B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH283,Uncommitted Supervisorly Flash in Macro 283" group.byte 0x46C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH284,Uncommitted Supervisorly Flash in Macro 284" group.byte 0x46D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH285,Uncommitted Supervisorly Flash in Macro 285" group.byte 0x46E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH286,Uncommitted Supervisorly Flash in Macro 286" group.byte 0x46F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH287,Uncommitted Supervisorly Flash in Macro 287" group.byte 0x470++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH288,Uncommitted Supervisorly Flash in Macro 288" group.byte 0x471++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH289,Uncommitted Supervisorly Flash in Macro 289" group.byte 0x472++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH290,Uncommitted Supervisorly Flash in Macro 290" group.byte 0x473++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH291,Uncommitted Supervisorly Flash in Macro 291" group.byte 0x474++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH292,Uncommitted Supervisorly Flash in Macro 292" group.byte 0x475++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH293,Uncommitted Supervisorly Flash in Macro 293" group.byte 0x476++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH294,Uncommitted Supervisorly Flash in Macro 294" group.byte 0x477++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH295,Uncommitted Supervisorly Flash in Macro 295" group.byte 0x478++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH296,Uncommitted Supervisorly Flash in Macro 296" group.byte 0x479++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH297,Uncommitted Supervisorly Flash in Macro 297" group.byte 0x47A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH298,Uncommitted Supervisorly Flash in Macro 298" group.byte 0x47B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH299,Uncommitted Supervisorly Flash in Macro 299" group.byte 0x47C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH300,Uncommitted Supervisorly Flash in Macro 300" group.byte 0x47D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH301,Uncommitted Supervisorly Flash in Macro 301" group.byte 0x47E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH302,Uncommitted Supervisorly Flash in Macro 302" group.byte 0x47F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH303,Uncommitted Supervisorly Flash in Macro 303" group.byte 0x480++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH304,Uncommitted Supervisorly Flash in Macro 304" group.byte 0x481++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH305,Uncommitted Supervisorly Flash in Macro 305" group.byte 0x482++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH306,Uncommitted Supervisorly Flash in Macro 306" group.byte 0x483++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH307,Uncommitted Supervisorly Flash in Macro 307" group.byte 0x484++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH308,Uncommitted Supervisorly Flash in Macro 308" group.byte 0x485++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH309,Uncommitted Supervisorly Flash in Macro 309" group.byte 0x486++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH310,Uncommitted Supervisorly Flash in Macro 310" group.byte 0x487++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH311,Uncommitted Supervisorly Flash in Macro 311" group.byte 0x488++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH312,Uncommitted Supervisorly Flash in Macro 312" group.byte 0x489++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH313,Uncommitted Supervisorly Flash in Macro 313" group.byte 0x48A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH314,Uncommitted Supervisorly Flash in Macro 314" group.byte 0x48B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH315,Uncommitted Supervisorly Flash in Macro 315" group.byte 0x48C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH316,Uncommitted Supervisorly Flash in Macro 316" group.byte 0x48D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH317,Uncommitted Supervisorly Flash in Macro 317" group.byte 0x48E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH318,Uncommitted Supervisorly Flash in Macro 318" group.byte 0x48F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH319,Uncommitted Supervisorly Flash in Macro 319" group.byte 0x490++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH320,Uncommitted Supervisorly Flash in Macro 320" group.byte 0x491++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH321,Uncommitted Supervisorly Flash in Macro 321" group.byte 0x492++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH322,Uncommitted Supervisorly Flash in Macro 322" group.byte 0x493++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH323,Uncommitted Supervisorly Flash in Macro 323" group.byte 0x494++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH324,Uncommitted Supervisorly Flash in Macro 324" group.byte 0x495++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH325,Uncommitted Supervisorly Flash in Macro 325" group.byte 0x496++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH326,Uncommitted Supervisorly Flash in Macro 326" group.byte 0x497++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH327,Uncommitted Supervisorly Flash in Macro 327" group.byte 0x498++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH328,Uncommitted Supervisorly Flash in Macro 328" group.byte 0x499++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH329,Uncommitted Supervisorly Flash in Macro 329" group.byte 0x49A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH330,Uncommitted Supervisorly Flash in Macro 330" group.byte 0x49B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH331,Uncommitted Supervisorly Flash in Macro 331" group.byte 0x49C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH332,Uncommitted Supervisorly Flash in Macro 332" group.byte 0x49D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH333,Uncommitted Supervisorly Flash in Macro 333" group.byte 0x49E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH334,Uncommitted Supervisorly Flash in Macro 334" group.byte 0x49F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH335,Uncommitted Supervisorly Flash in Macro 335" group.byte 0x4A0++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH336,Uncommitted Supervisorly Flash in Macro 336" group.byte 0x4A1++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH337,Uncommitted Supervisorly Flash in Macro 337" group.byte 0x4A2++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH338,Uncommitted Supervisorly Flash in Macro 338" group.byte 0x4A3++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH339,Uncommitted Supervisorly Flash in Macro 339" group.byte 0x4A4++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH340,Uncommitted Supervisorly Flash in Macro 340" group.byte 0x4A5++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH341,Uncommitted Supervisorly Flash in Macro 341" group.byte 0x4A6++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH342,Uncommitted Supervisorly Flash in Macro 342" group.byte 0x4A7++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH343,Uncommitted Supervisorly Flash in Macro 343" group.byte 0x4A8++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH344,Uncommitted Supervisorly Flash in Macro 344" group.byte 0x4A9++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH345,Uncommitted Supervisorly Flash in Macro 345" group.byte 0x4AA++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH346,Uncommitted Supervisorly Flash in Macro 346" group.byte 0x4AB++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH347,Uncommitted Supervisorly Flash in Macro 347" group.byte 0x4AC++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH348,Uncommitted Supervisorly Flash in Macro 348" group.byte 0x4AD++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH349,Uncommitted Supervisorly Flash in Macro 349" group.byte 0x4AE++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH350,Uncommitted Supervisorly Flash in Macro 350" group.byte 0x4AF++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH351,Uncommitted Supervisorly Flash in Macro 351" group.byte 0x4B0++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH352,Uncommitted Supervisorly Flash in Macro 352" group.byte 0x4B1++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH353,Uncommitted Supervisorly Flash in Macro 353" group.byte 0x4B2++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH354,Uncommitted Supervisorly Flash in Macro 354" group.byte 0x4B3++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH355,Uncommitted Supervisorly Flash in Macro 355" group.byte 0x4B4++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH356,Uncommitted Supervisorly Flash in Macro 356" group.byte 0x4B5++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH357,Uncommitted Supervisorly Flash in Macro 357" group.byte 0x4B6++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH358,Uncommitted Supervisorly Flash in Macro 358" group.byte 0x4B7++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH359,Uncommitted Supervisorly Flash in Macro 359" group.byte 0x4B8++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH360,Uncommitted Supervisorly Flash in Macro 360" group.byte 0x4B9++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH361,Uncommitted Supervisorly Flash in Macro 361" group.byte 0x4BA++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH362,Uncommitted Supervisorly Flash in Macro 362" group.byte 0x4BB++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH363,Uncommitted Supervisorly Flash in Macro 363" group.byte 0x4BC++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH364,Uncommitted Supervisorly Flash in Macro 364" group.byte 0x4BD++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH365,Uncommitted Supervisorly Flash in Macro 365" group.byte 0x4BE++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH366,Uncommitted Supervisorly Flash in Macro 366" group.byte 0x4BF++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH367,Uncommitted Supervisorly Flash in Macro 367" group.byte 0x4C0++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH368,Uncommitted Supervisorly Flash in Macro 368" group.byte 0x4C1++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH369,Uncommitted Supervisorly Flash in Macro 369" group.byte 0x4C2++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH370,Uncommitted Supervisorly Flash in Macro 370" group.byte 0x4C3++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH371,Uncommitted Supervisorly Flash in Macro 371" group.byte 0x4C4++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH372,Uncommitted Supervisorly Flash in Macro 372" group.byte 0x4C5++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH373,Uncommitted Supervisorly Flash in Macro 373" group.byte 0x4C6++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH374,Uncommitted Supervisorly Flash in Macro 374" group.byte 0x4C7++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH375,Uncommitted Supervisorly Flash in Macro 375" group.byte 0x4C8++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH376,Uncommitted Supervisorly Flash in Macro 376" group.byte 0x4C9++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH377,Uncommitted Supervisorly Flash in Macro 377" group.byte 0x4CA++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH378,Uncommitted Supervisorly Flash in Macro 378" group.byte 0x4CB++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH379,Uncommitted Supervisorly Flash in Macro 379" group.byte 0x4CC++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH380,Uncommitted Supervisorly Flash in Macro 380" group.byte 0x4CD++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH381,Uncommitted Supervisorly Flash in Macro 381" group.byte 0x4CE++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH382,Uncommitted Supervisorly Flash in Macro 382" group.byte 0x4CF++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH383,Uncommitted Supervisorly Flash in Macro 383" group.byte 0x4D0++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH384,Uncommitted Supervisorly Flash in Macro 384" group.byte 0x4D1++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH385,Uncommitted Supervisorly Flash in Macro 385" group.byte 0x4D2++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH386,Uncommitted Supervisorly Flash in Macro 386" group.byte 0x4D3++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH387,Uncommitted Supervisorly Flash in Macro 387" group.byte 0x4D4++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH388,Uncommitted Supervisorly Flash in Macro 388" group.byte 0x4D5++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH389,Uncommitted Supervisorly Flash in Macro 389" group.byte 0x4D6++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH390,Uncommitted Supervisorly Flash in Macro 390" group.byte 0x4D7++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH391,Uncommitted Supervisorly Flash in Macro 391" group.byte 0x4D8++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH392,Uncommitted Supervisorly Flash in Macro 392" group.byte 0x4D9++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH393,Uncommitted Supervisorly Flash in Macro 393" group.byte 0x4DA++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH394,Uncommitted Supervisorly Flash in Macro 394" group.byte 0x4DB++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH395,Uncommitted Supervisorly Flash in Macro 395" group.byte 0x4DC++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH396,Uncommitted Supervisorly Flash in Macro 396" group.byte 0x4DD++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH397,Uncommitted Supervisorly Flash in Macro 397" group.byte 0x4DE++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH398,Uncommitted Supervisorly Flash in Macro 398" group.byte 0x4DF++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH399,Uncommitted Supervisorly Flash in Macro 399" group.byte 0x4E0++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH400,Uncommitted Supervisorly Flash in Macro 400" group.byte 0x4E1++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH401,Uncommitted Supervisorly Flash in Macro 401" group.byte 0x4E2++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH402,Uncommitted Supervisorly Flash in Macro 402" group.byte 0x4E3++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH403,Uncommitted Supervisorly Flash in Macro 403" group.byte 0x4E4++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH404,Uncommitted Supervisorly Flash in Macro 404" group.byte 0x4E5++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH405,Uncommitted Supervisorly Flash in Macro 405" group.byte 0x4E6++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH406,Uncommitted Supervisorly Flash in Macro 406" group.byte 0x4E7++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH407,Uncommitted Supervisorly Flash in Macro 407" group.byte 0x4E8++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH408,Uncommitted Supervisorly Flash in Macro 408" group.byte 0x4E9++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH409,Uncommitted Supervisorly Flash in Macro 409" group.byte 0x4EA++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH410,Uncommitted Supervisorly Flash in Macro 410" group.byte 0x4EB++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH411,Uncommitted Supervisorly Flash in Macro 411" group.byte 0x4EC++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH412,Uncommitted Supervisorly Flash in Macro 412" group.byte 0x4ED++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH413,Uncommitted Supervisorly Flash in Macro 413" group.byte 0x4EE++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH414,Uncommitted Supervisorly Flash in Macro 414" group.byte 0x4EF++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH415,Uncommitted Supervisorly Flash in Macro 415" group.byte 0x4F0++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH416,Uncommitted Supervisorly Flash in Macro 416" group.byte 0x4F1++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH417,Uncommitted Supervisorly Flash in Macro 417" group.byte 0x4F2++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH418,Uncommitted Supervisorly Flash in Macro 418" group.byte 0x4F3++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH419,Uncommitted Supervisorly Flash in Macro 419" group.byte 0x4F4++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH420,Uncommitted Supervisorly Flash in Macro 420" group.byte 0x4F5++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH421,Uncommitted Supervisorly Flash in Macro 421" group.byte 0x4F6++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH422,Uncommitted Supervisorly Flash in Macro 422" group.byte 0x4F7++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH423,Uncommitted Supervisorly Flash in Macro 423" group.byte 0x4F8++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH424,Uncommitted Supervisorly Flash in Macro 424" group.byte 0x4F9++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH425,Uncommitted Supervisorly Flash in Macro 425" group.byte 0x4FA++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH426,Uncommitted Supervisorly Flash in Macro 426" group.byte 0x4FB++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH427,Uncommitted Supervisorly Flash in Macro 427" group.byte 0x4FC++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH428,Uncommitted Supervisorly Flash in Macro 428" group.byte 0x4FD++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH429,Uncommitted Supervisorly Flash in Macro 429" group.byte 0x4FE++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH430,Uncommitted Supervisorly Flash in Macro 430" group.byte 0x4FF++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH431,Uncommitted Supervisorly Flash in Macro 431" group.byte 0x500++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH432,Uncommitted Supervisorly Flash in Macro 432" group.byte 0x501++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH433,Uncommitted Supervisorly Flash in Macro 433" group.byte 0x502++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH434,Uncommitted Supervisorly Flash in Macro 434" group.byte 0x503++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH435,Uncommitted Supervisorly Flash in Macro 435" group.byte 0x504++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH436,Uncommitted Supervisorly Flash in Macro 436" group.byte 0x505++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH437,Uncommitted Supervisorly Flash in Macro 437" group.byte 0x506++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH438,Uncommitted Supervisorly Flash in Macro 438" group.byte 0x507++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH439,Uncommitted Supervisorly Flash in Macro 439" group.byte 0x508++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH440,Uncommitted Supervisorly Flash in Macro 440" group.byte 0x509++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH441,Uncommitted Supervisorly Flash in Macro 441" group.byte 0x50A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH442,Uncommitted Supervisorly Flash in Macro 442" group.byte 0x50B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH443,Uncommitted Supervisorly Flash in Macro 443" group.byte 0x50C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH444,Uncommitted Supervisorly Flash in Macro 444" group.byte 0x50D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH445,Uncommitted Supervisorly Flash in Macro 445" group.byte 0x50E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH446,Uncommitted Supervisorly Flash in Macro 446" group.byte 0x50F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH447,Uncommitted Supervisorly Flash in Macro 447" group.byte 0x510++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH448,Uncommitted Supervisorly Flash in Macro 448" group.byte 0x511++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH449,Uncommitted Supervisorly Flash in Macro 449" group.byte 0x512++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH450,Uncommitted Supervisorly Flash in Macro 450" group.byte 0x513++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH451,Uncommitted Supervisorly Flash in Macro 451" group.byte 0x514++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH452,Uncommitted Supervisorly Flash in Macro 452" group.byte 0x515++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH453,Uncommitted Supervisorly Flash in Macro 453" group.byte 0x516++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH454,Uncommitted Supervisorly Flash in Macro 454" group.byte 0x517++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH455,Uncommitted Supervisorly Flash in Macro 455" group.byte 0x518++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH456,Uncommitted Supervisorly Flash in Macro 456" group.byte 0x519++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH457,Uncommitted Supervisorly Flash in Macro 457" group.byte 0x51A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH458,Uncommitted Supervisorly Flash in Macro 458" group.byte 0x51B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH459,Uncommitted Supervisorly Flash in Macro 459" group.byte 0x51C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH460,Uncommitted Supervisorly Flash in Macro 460" group.byte 0x51D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH461,Uncommitted Supervisorly Flash in Macro 461" group.byte 0x51E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH462,Uncommitted Supervisorly Flash in Macro 462" group.byte 0x51F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH463,Uncommitted Supervisorly Flash in Macro 463" group.byte 0x520++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH464,Uncommitted Supervisorly Flash in Macro 464" group.byte 0x521++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH465,Uncommitted Supervisorly Flash in Macro 465" group.byte 0x522++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH466,Uncommitted Supervisorly Flash in Macro 466" group.byte 0x523++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH467,Uncommitted Supervisorly Flash in Macro 467" group.byte 0x524++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH468,Uncommitted Supervisorly Flash in Macro 468" group.byte 0x525++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH469,Uncommitted Supervisorly Flash in Macro 469" group.byte 0x526++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH470,Uncommitted Supervisorly Flash in Macro 470" group.byte 0x527++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH471,Uncommitted Supervisorly Flash in Macro 471" group.byte 0x528++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH472,Uncommitted Supervisorly Flash in Macro 472" group.byte 0x529++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH473,Uncommitted Supervisorly Flash in Macro 473" group.byte 0x52A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH474,Uncommitted Supervisorly Flash in Macro 474" group.byte 0x52B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH475,Uncommitted Supervisorly Flash in Macro 475" group.byte 0x52C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH476,Uncommitted Supervisorly Flash in Macro 476" group.byte 0x52D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH477,Uncommitted Supervisorly Flash in Macro 477" group.byte 0x52E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH478,Uncommitted Supervisorly Flash in Macro 478" group.byte 0x52F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH479,Uncommitted Supervisorly Flash in Macro 479" group.byte 0x530++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH480,Uncommitted Supervisorly Flash in Macro 480" group.byte 0x531++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH481,Uncommitted Supervisorly Flash in Macro 481" group.byte 0x532++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH482,Uncommitted Supervisorly Flash in Macro 482" group.byte 0x533++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH483,Uncommitted Supervisorly Flash in Macro 483" group.byte 0x534++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH484,Uncommitted Supervisorly Flash in Macro 484" group.byte 0x535++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH485,Uncommitted Supervisorly Flash in Macro 485" group.byte 0x536++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH486,Uncommitted Supervisorly Flash in Macro 486" group.byte 0x537++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH487,Uncommitted Supervisorly Flash in Macro 487" group.byte 0x538++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH488,Uncommitted Supervisorly Flash in Macro 488" group.byte 0x539++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH489,Uncommitted Supervisorly Flash in Macro 489" group.byte 0x53A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH490,Uncommitted Supervisorly Flash in Macro 490" group.byte 0x53B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH491,Uncommitted Supervisorly Flash in Macro 491" group.byte 0x53C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH492,Uncommitted Supervisorly Flash in Macro 492" group.byte 0x53D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH493,Uncommitted Supervisorly Flash in Macro 493" group.byte 0x53E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH494,Uncommitted Supervisorly Flash in Macro 494" group.byte 0x53F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH495,Uncommitted Supervisorly Flash in Macro 495" group.byte 0x540++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH496,Uncommitted Supervisorly Flash in Macro 496" group.byte 0x541++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH497,Uncommitted Supervisorly Flash in Macro 497" group.byte 0x542++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH498,Uncommitted Supervisorly Flash in Macro 498" group.byte 0x543++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH499,Uncommitted Supervisorly Flash in Macro 499" group.byte 0x544++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH500,Uncommitted Supervisorly Flash in Macro 500" group.byte 0x545++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH501,Uncommitted Supervisorly Flash in Macro 501" group.byte 0x546++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH502,Uncommitted Supervisorly Flash in Macro 502" group.byte 0x547++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH503,Uncommitted Supervisorly Flash in Macro 503" group.byte 0x548++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH504,Uncommitted Supervisorly Flash in Macro 504" group.byte 0x549++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH505,Uncommitted Supervisorly Flash in Macro 505" group.byte 0x54A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH506,Uncommitted Supervisorly Flash in Macro 506" group.byte 0x54B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH507,Uncommitted Supervisorly Flash in Macro 507" group.byte 0x54C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH508,Uncommitted Supervisorly Flash in Macro 508" group.byte 0x54D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH509,Uncommitted Supervisorly Flash in Macro 509" group.byte 0x54E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH510,Uncommitted Supervisorly Flash in Macro 510" group.byte 0x54F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH511,Uncommitted Supervisorly Flash in Macro 511" group.byte 0x550++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH512,Uncommitted Supervisorly Flash in Macro 512" group.byte 0x551++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH513,Uncommitted Supervisorly Flash in Macro 513" group.byte 0x552++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH514,Uncommitted Supervisorly Flash in Macro 514" group.byte 0x553++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH515,Uncommitted Supervisorly Flash in Macro 515" group.byte 0x554++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH516,Uncommitted Supervisorly Flash in Macro 516" group.byte 0x555++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH517,Uncommitted Supervisorly Flash in Macro 517" group.byte 0x556++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH518,Uncommitted Supervisorly Flash in Macro 518" group.byte 0x557++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH519,Uncommitted Supervisorly Flash in Macro 519" group.byte 0x558++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH520,Uncommitted Supervisorly Flash in Macro 520" group.byte 0x559++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH521,Uncommitted Supervisorly Flash in Macro 521" group.byte 0x55A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH522,Uncommitted Supervisorly Flash in Macro 522" group.byte 0x55B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH523,Uncommitted Supervisorly Flash in Macro 523" group.byte 0x55C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH524,Uncommitted Supervisorly Flash in Macro 524" group.byte 0x55D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH525,Uncommitted Supervisorly Flash in Macro 525" group.byte 0x55E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH526,Uncommitted Supervisorly Flash in Macro 526" group.byte 0x55F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH527,Uncommitted Supervisorly Flash in Macro 527" group.byte 0x560++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH528,Uncommitted Supervisorly Flash in Macro 528" group.byte 0x561++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH529,Uncommitted Supervisorly Flash in Macro 529" group.byte 0x562++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH530,Uncommitted Supervisorly Flash in Macro 530" group.byte 0x563++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH531,Uncommitted Supervisorly Flash in Macro 531" group.byte 0x564++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH532,Uncommitted Supervisorly Flash in Macro 532" group.byte 0x565++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH533,Uncommitted Supervisorly Flash in Macro 533" group.byte 0x566++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH534,Uncommitted Supervisorly Flash in Macro 534" group.byte 0x567++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH535,Uncommitted Supervisorly Flash in Macro 535" group.byte 0x568++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH536,Uncommitted Supervisorly Flash in Macro 536" group.byte 0x569++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH537,Uncommitted Supervisorly Flash in Macro 537" group.byte 0x56A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH538,Uncommitted Supervisorly Flash in Macro 538" group.byte 0x56B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH539,Uncommitted Supervisorly Flash in Macro 539" group.byte 0x56C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH540,Uncommitted Supervisorly Flash in Macro 540" group.byte 0x56D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH541,Uncommitted Supervisorly Flash in Macro 541" group.byte 0x56E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH542,Uncommitted Supervisorly Flash in Macro 542" group.byte 0x56F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH543,Uncommitted Supervisorly Flash in Macro 543" group.byte 0x570++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH544,Uncommitted Supervisorly Flash in Macro 544" group.byte 0x571++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH545,Uncommitted Supervisorly Flash in Macro 545" group.byte 0x572++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH546,Uncommitted Supervisorly Flash in Macro 546" group.byte 0x573++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH547,Uncommitted Supervisorly Flash in Macro 547" group.byte 0x574++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH548,Uncommitted Supervisorly Flash in Macro 548" group.byte 0x575++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH549,Uncommitted Supervisorly Flash in Macro 549" group.byte 0x576++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH550,Uncommitted Supervisorly Flash in Macro 550" group.byte 0x577++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH551,Uncommitted Supervisorly Flash in Macro 551" group.byte 0x578++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH552,Uncommitted Supervisorly Flash in Macro 552" group.byte 0x579++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH553,Uncommitted Supervisorly Flash in Macro 553" group.byte 0x57A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH554,Uncommitted Supervisorly Flash in Macro 554" group.byte 0x57B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH555,Uncommitted Supervisorly Flash in Macro 555" group.byte 0x57C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH556,Uncommitted Supervisorly Flash in Macro 556" group.byte 0x57D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH557,Uncommitted Supervisorly Flash in Macro 557" group.byte 0x57E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH558,Uncommitted Supervisorly Flash in Macro 558" group.byte 0x57F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH559,Uncommitted Supervisorly Flash in Macro 559" group.byte 0x580++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH560,Uncommitted Supervisorly Flash in Macro 560" group.byte 0x581++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH561,Uncommitted Supervisorly Flash in Macro 561" group.byte 0x582++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH562,Uncommitted Supervisorly Flash in Macro 562" group.byte 0x583++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH563,Uncommitted Supervisorly Flash in Macro 563" group.byte 0x584++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH564,Uncommitted Supervisorly Flash in Macro 564" group.byte 0x585++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH565,Uncommitted Supervisorly Flash in Macro 565" group.byte 0x586++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH566,Uncommitted Supervisorly Flash in Macro 566" group.byte 0x587++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH567,Uncommitted Supervisorly Flash in Macro 567" group.byte 0x588++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH568,Uncommitted Supervisorly Flash in Macro 568" group.byte 0x589++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH569,Uncommitted Supervisorly Flash in Macro 569" group.byte 0x58A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH570,Uncommitted Supervisorly Flash in Macro 570" group.byte 0x58B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH571,Uncommitted Supervisorly Flash in Macro 571" group.byte 0x58C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH572,Uncommitted Supervisorly Flash in Macro 572" group.byte 0x58D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH573,Uncommitted Supervisorly Flash in Macro 573" group.byte 0x58E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH574,Uncommitted Supervisorly Flash in Macro 574" group.byte 0x58F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH575,Uncommitted Supervisorly Flash in Macro 575" group.byte 0x590++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH576,Uncommitted Supervisorly Flash in Macro 576" group.byte 0x591++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH577,Uncommitted Supervisorly Flash in Macro 577" group.byte 0x592++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH578,Uncommitted Supervisorly Flash in Macro 578" group.byte 0x593++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH579,Uncommitted Supervisorly Flash in Macro 579" group.byte 0x594++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH580,Uncommitted Supervisorly Flash in Macro 580" group.byte 0x595++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH581,Uncommitted Supervisorly Flash in Macro 581" group.byte 0x596++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH582,Uncommitted Supervisorly Flash in Macro 582" group.byte 0x597++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH583,Uncommitted Supervisorly Flash in Macro 583" group.byte 0x598++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH584,Uncommitted Supervisorly Flash in Macro 584" group.byte 0x599++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH585,Uncommitted Supervisorly Flash in Macro 585" group.byte 0x59A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH586,Uncommitted Supervisorly Flash in Macro 586" group.byte 0x59B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH587,Uncommitted Supervisorly Flash in Macro 587" group.byte 0x59C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH588,Uncommitted Supervisorly Flash in Macro 588" group.byte 0x59D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH589,Uncommitted Supervisorly Flash in Macro 589" group.byte 0x59E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH590,Uncommitted Supervisorly Flash in Macro 590" group.byte 0x59F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH591,Uncommitted Supervisorly Flash in Macro 591" group.byte 0x5A0++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH592,Uncommitted Supervisorly Flash in Macro 592" group.byte 0x5A1++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH593,Uncommitted Supervisorly Flash in Macro 593" group.byte 0x5A2++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH594,Uncommitted Supervisorly Flash in Macro 594" group.byte 0x5A3++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH595,Uncommitted Supervisorly Flash in Macro 595" group.byte 0x5A4++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH596,Uncommitted Supervisorly Flash in Macro 596" group.byte 0x5A5++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH597,Uncommitted Supervisorly Flash in Macro 597" group.byte 0x5A6++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH598,Uncommitted Supervisorly Flash in Macro 598" group.byte 0x5A7++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH599,Uncommitted Supervisorly Flash in Macro 599" group.byte 0x5A8++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH600,Uncommitted Supervisorly Flash in Macro 600" group.byte 0x5A9++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH601,Uncommitted Supervisorly Flash in Macro 601" group.byte 0x5AA++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH602,Uncommitted Supervisorly Flash in Macro 602" group.byte 0x5AB++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH603,Uncommitted Supervisorly Flash in Macro 603" group.byte 0x5AC++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH604,Uncommitted Supervisorly Flash in Macro 604" group.byte 0x5AD++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH605,Uncommitted Supervisorly Flash in Macro 605" group.byte 0x5AE++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH606,Uncommitted Supervisorly Flash in Macro 606" group.byte 0x5AF++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH607,Uncommitted Supervisorly Flash in Macro 607" group.byte 0x5B0++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH608,Uncommitted Supervisorly Flash in Macro 608" group.byte 0x5B1++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH609,Uncommitted Supervisorly Flash in Macro 609" group.byte 0x5B2++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH610,Uncommitted Supervisorly Flash in Macro 610" group.byte 0x5B3++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH611,Uncommitted Supervisorly Flash in Macro 611" group.byte 0x5B4++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH612,Uncommitted Supervisorly Flash in Macro 612" group.byte 0x5B5++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH613,Uncommitted Supervisorly Flash in Macro 613" group.byte 0x5B6++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH614,Uncommitted Supervisorly Flash in Macro 614" group.byte 0x5B7++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH615,Uncommitted Supervisorly Flash in Macro 615" group.byte 0x5B8++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH616,Uncommitted Supervisorly Flash in Macro 616" group.byte 0x5B9++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH617,Uncommitted Supervisorly Flash in Macro 617" group.byte 0x5BA++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH618,Uncommitted Supervisorly Flash in Macro 618" group.byte 0x5BB++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH619,Uncommitted Supervisorly Flash in Macro 619" group.byte 0x5BC++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH620,Uncommitted Supervisorly Flash in Macro 620" group.byte 0x5BD++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH621,Uncommitted Supervisorly Flash in Macro 621" group.byte 0x5BE++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH622,Uncommitted Supervisorly Flash in Macro 622" group.byte 0x5BF++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH623,Uncommitted Supervisorly Flash in Macro 623" group.byte 0x5C0++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH624,Uncommitted Supervisorly Flash in Macro 624" group.byte 0x5C1++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH625,Uncommitted Supervisorly Flash in Macro 625" group.byte 0x5C2++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH626,Uncommitted Supervisorly Flash in Macro 626" group.byte 0x5C3++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH627,Uncommitted Supervisorly Flash in Macro 627" group.byte 0x5C4++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH628,Uncommitted Supervisorly Flash in Macro 628" group.byte 0x5C5++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH629,Uncommitted Supervisorly Flash in Macro 629" group.byte 0x5C6++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH630,Uncommitted Supervisorly Flash in Macro 630" group.byte 0x5C7++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH631,Uncommitted Supervisorly Flash in Macro 631" group.byte 0x5C8++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH632,Uncommitted Supervisorly Flash in Macro 632" group.byte 0x5C9++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH633,Uncommitted Supervisorly Flash in Macro 633" group.byte 0x5CA++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH634,Uncommitted Supervisorly Flash in Macro 634" group.byte 0x5CB++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH635,Uncommitted Supervisorly Flash in Macro 635" group.byte 0x5CC++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH636,Uncommitted Supervisorly Flash in Macro 636" group.byte 0x5CD++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH637,Uncommitted Supervisorly Flash in Macro 637" group.byte 0x5CE++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH638,Uncommitted Supervisorly Flash in Macro 638" group.byte 0x5CF++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH639,Uncommitted Supervisorly Flash in Macro 639" group.byte 0x5D0++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH640,Uncommitted Supervisorly Flash in Macro 640" group.byte 0x5D1++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH641,Uncommitted Supervisorly Flash in Macro 641" group.byte 0x5D2++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH642,Uncommitted Supervisorly Flash in Macro 642" group.byte 0x5D3++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH643,Uncommitted Supervisorly Flash in Macro 643" group.byte 0x5D4++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH644,Uncommitted Supervisorly Flash in Macro 644" group.byte 0x5D5++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH645,Uncommitted Supervisorly Flash in Macro 645" group.byte 0x5D6++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH646,Uncommitted Supervisorly Flash in Macro 646" group.byte 0x5D7++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH647,Uncommitted Supervisorly Flash in Macro 647" group.byte 0x5D8++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH648,Uncommitted Supervisorly Flash in Macro 648" group.byte 0x5D9++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH649,Uncommitted Supervisorly Flash in Macro 649" group.byte 0x5DA++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH650,Uncommitted Supervisorly Flash in Macro 650" group.byte 0x5DB++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH651,Uncommitted Supervisorly Flash in Macro 651" group.byte 0x5DC++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH652,Uncommitted Supervisorly Flash in Macro 652" group.byte 0x5DD++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH653,Uncommitted Supervisorly Flash in Macro 653" group.byte 0x5DE++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH654,Uncommitted Supervisorly Flash in Macro 654" group.byte 0x5DF++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH655,Uncommitted Supervisorly Flash in Macro 655" group.byte 0x5E0++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH656,Uncommitted Supervisorly Flash in Macro 656" group.byte 0x5E1++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH657,Uncommitted Supervisorly Flash in Macro 657" group.byte 0x5E2++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH658,Uncommitted Supervisorly Flash in Macro 658" group.byte 0x5E3++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH659,Uncommitted Supervisorly Flash in Macro 659" group.byte 0x5E4++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH660,Uncommitted Supervisorly Flash in Macro 660" group.byte 0x5E5++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH661,Uncommitted Supervisorly Flash in Macro 661" group.byte 0x5E6++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH662,Uncommitted Supervisorly Flash in Macro 662" group.byte 0x5E7++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH663,Uncommitted Supervisorly Flash in Macro 663" group.byte 0x5E8++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH664,Uncommitted Supervisorly Flash in Macro 664" group.byte 0x5E9++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH665,Uncommitted Supervisorly Flash in Macro 665" group.byte 0x5EA++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH666,Uncommitted Supervisorly Flash in Macro 666" group.byte 0x5EB++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH667,Uncommitted Supervisorly Flash in Macro 667" group.byte 0x5EC++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH668,Uncommitted Supervisorly Flash in Macro 668" group.byte 0x5ED++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH669,Uncommitted Supervisorly Flash in Macro 669" group.byte 0x5EE++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH670,Uncommitted Supervisorly Flash in Macro 670" group.byte 0x5EF++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH671,Uncommitted Supervisorly Flash in Macro 671" group.byte 0x5F0++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH672,Uncommitted Supervisorly Flash in Macro 672" group.byte 0x5F1++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH673,Uncommitted Supervisorly Flash in Macro 673" group.byte 0x5F2++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH674,Uncommitted Supervisorly Flash in Macro 674" group.byte 0x5F3++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH675,Uncommitted Supervisorly Flash in Macro 675" group.byte 0x5F4++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH676,Uncommitted Supervisorly Flash in Macro 676" group.byte 0x5F5++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH677,Uncommitted Supervisorly Flash in Macro 677" group.byte 0x5F6++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH678,Uncommitted Supervisorly Flash in Macro 678" group.byte 0x5F7++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH679,Uncommitted Supervisorly Flash in Macro 679" group.byte 0x5F8++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH680,Uncommitted Supervisorly Flash in Macro 680" group.byte 0x5F9++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH681,Uncommitted Supervisorly Flash in Macro 681" group.byte 0x5FA++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH682,Uncommitted Supervisorly Flash in Macro 682" group.byte 0x5FB++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH683,Uncommitted Supervisorly Flash in Macro 683" group.byte 0x5FC++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH684,Uncommitted Supervisorly Flash in Macro 684" group.byte 0x5FD++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH685,Uncommitted Supervisorly Flash in Macro 685" group.byte 0x5FE++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH686,Uncommitted Supervisorly Flash in Macro 686" group.byte 0x5FF++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH687,Uncommitted Supervisorly Flash in Macro 687" group.byte 0x600++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH688,Uncommitted Supervisorly Flash in Macro 688" group.byte 0x601++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH689,Uncommitted Supervisorly Flash in Macro 689" group.byte 0x602++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH690,Uncommitted Supervisorly Flash in Macro 690" group.byte 0x603++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH691,Uncommitted Supervisorly Flash in Macro 691" group.byte 0x604++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH692,Uncommitted Supervisorly Flash in Macro 692" group.byte 0x605++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH693,Uncommitted Supervisorly Flash in Macro 693" group.byte 0x606++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH694,Uncommitted Supervisorly Flash in Macro 694" group.byte 0x607++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH695,Uncommitted Supervisorly Flash in Macro 695" group.byte 0x608++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH696,Uncommitted Supervisorly Flash in Macro 696" group.byte 0x609++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH697,Uncommitted Supervisorly Flash in Macro 697" group.byte 0x60A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH698,Uncommitted Supervisorly Flash in Macro 698" group.byte 0x60B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH699,Uncommitted Supervisorly Flash in Macro 699" group.byte 0x60C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH700,Uncommitted Supervisorly Flash in Macro 700" group.byte 0x60D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH701,Uncommitted Supervisorly Flash in Macro 701" group.byte 0x60E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH702,Uncommitted Supervisorly Flash in Macro 702" group.byte 0x60F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH703,Uncommitted Supervisorly Flash in Macro 703" group.byte 0x610++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH704,Uncommitted Supervisorly Flash in Macro 704" group.byte 0x611++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH705,Uncommitted Supervisorly Flash in Macro 705" group.byte 0x612++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH706,Uncommitted Supervisorly Flash in Macro 706" group.byte 0x613++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH707,Uncommitted Supervisorly Flash in Macro 707" group.byte 0x614++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH708,Uncommitted Supervisorly Flash in Macro 708" group.byte 0x615++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH709,Uncommitted Supervisorly Flash in Macro 709" group.byte 0x616++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH710,Uncommitted Supervisorly Flash in Macro 710" group.byte 0x617++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH711,Uncommitted Supervisorly Flash in Macro 711" group.byte 0x618++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH712,Uncommitted Supervisorly Flash in Macro 712" group.byte 0x619++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH713,Uncommitted Supervisorly Flash in Macro 713" group.byte 0x61A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH714,Uncommitted Supervisorly Flash in Macro 714" group.byte 0x61B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH715,Uncommitted Supervisorly Flash in Macro 715" group.byte 0x61C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH716,Uncommitted Supervisorly Flash in Macro 716" group.byte 0x61D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH717,Uncommitted Supervisorly Flash in Macro 717" group.byte 0x61E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH718,Uncommitted Supervisorly Flash in Macro 718" group.byte 0x61F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH719,Uncommitted Supervisorly Flash in Macro 719" group.byte 0x620++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH720,Uncommitted Supervisorly Flash in Macro 720" group.byte 0x621++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH721,Uncommitted Supervisorly Flash in Macro 721" group.byte 0x622++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH722,Uncommitted Supervisorly Flash in Macro 722" group.byte 0x623++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH723,Uncommitted Supervisorly Flash in Macro 723" group.byte 0x624++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH724,Uncommitted Supervisorly Flash in Macro 724" group.byte 0x625++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH725,Uncommitted Supervisorly Flash in Macro 725" group.byte 0x626++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH726,Uncommitted Supervisorly Flash in Macro 726" group.byte 0x627++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH727,Uncommitted Supervisorly Flash in Macro 727" group.byte 0x628++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH728,Uncommitted Supervisorly Flash in Macro 728" group.byte 0x629++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH729,Uncommitted Supervisorly Flash in Macro 729" group.byte 0x62A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH730,Uncommitted Supervisorly Flash in Macro 730" group.byte 0x62B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH731,Uncommitted Supervisorly Flash in Macro 731" group.byte 0x62C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH732,Uncommitted Supervisorly Flash in Macro 732" group.byte 0x62D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH733,Uncommitted Supervisorly Flash in Macro 733" group.byte 0x62E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH734,Uncommitted Supervisorly Flash in Macro 734" group.byte 0x62F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH735,Uncommitted Supervisorly Flash in Macro 735" group.byte 0x630++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH736,Uncommitted Supervisorly Flash in Macro 736" group.byte 0x631++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH737,Uncommitted Supervisorly Flash in Macro 737" group.byte 0x632++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH738,Uncommitted Supervisorly Flash in Macro 738" group.byte 0x633++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH739,Uncommitted Supervisorly Flash in Macro 739" group.byte 0x634++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH740,Uncommitted Supervisorly Flash in Macro 740" group.byte 0x635++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH741,Uncommitted Supervisorly Flash in Macro 741" group.byte 0x636++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH742,Uncommitted Supervisorly Flash in Macro 742" group.byte 0x637++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH743,Uncommitted Supervisorly Flash in Macro 743" group.byte 0x638++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH744,Uncommitted Supervisorly Flash in Macro 744" group.byte 0x639++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH745,Uncommitted Supervisorly Flash in Macro 745" group.byte 0x63A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH746,Uncommitted Supervisorly Flash in Macro 746" group.byte 0x63B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH747,Uncommitted Supervisorly Flash in Macro 747" group.byte 0x63C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH748,Uncommitted Supervisorly Flash in Macro 748" group.byte 0x63D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH749,Uncommitted Supervisorly Flash in Macro 749" group.byte 0x63E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH750,Uncommitted Supervisorly Flash in Macro 750" group.byte 0x63F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH751,Uncommitted Supervisorly Flash in Macro 751" group.byte 0x640++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH752,Uncommitted Supervisorly Flash in Macro 752" group.byte 0x641++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH753,Uncommitted Supervisorly Flash in Macro 753" group.byte 0x642++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH754,Uncommitted Supervisorly Flash in Macro 754" group.byte 0x643++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH755,Uncommitted Supervisorly Flash in Macro 755" group.byte 0x644++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH756,Uncommitted Supervisorly Flash in Macro 756" group.byte 0x645++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH757,Uncommitted Supervisorly Flash in Macro 757" group.byte 0x646++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH758,Uncommitted Supervisorly Flash in Macro 758" group.byte 0x647++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH759,Uncommitted Supervisorly Flash in Macro 759" group.byte 0x648++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH760,Uncommitted Supervisorly Flash in Macro 760" group.byte 0x649++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH761,Uncommitted Supervisorly Flash in Macro 761" group.byte 0x64A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH762,Uncommitted Supervisorly Flash in Macro 762" group.byte 0x64B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH763,Uncommitted Supervisorly Flash in Macro 763" group.byte 0x64C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH764,Uncommitted Supervisorly Flash in Macro 764" group.byte 0x64D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH765,Uncommitted Supervisorly Flash in Macro 765" group.byte 0x64E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH766,Uncommitted Supervisorly Flash in Macro 766" group.byte 0x64F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH767,Uncommitted Supervisorly Flash in Macro 767" group.byte 0x650++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH768,Uncommitted Supervisorly Flash in Macro 768" group.byte 0x651++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH769,Uncommitted Supervisorly Flash in Macro 769" group.byte 0x652++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH770,Uncommitted Supervisorly Flash in Macro 770" group.byte 0x653++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH771,Uncommitted Supervisorly Flash in Macro 771" group.byte 0x654++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH772,Uncommitted Supervisorly Flash in Macro 772" group.byte 0x655++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH773,Uncommitted Supervisorly Flash in Macro 773" group.byte 0x656++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH774,Uncommitted Supervisorly Flash in Macro 774" group.byte 0x657++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH775,Uncommitted Supervisorly Flash in Macro 775" group.byte 0x658++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH776,Uncommitted Supervisorly Flash in Macro 776" group.byte 0x659++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH777,Uncommitted Supervisorly Flash in Macro 777" group.byte 0x65A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH778,Uncommitted Supervisorly Flash in Macro 778" group.byte 0x65B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH779,Uncommitted Supervisorly Flash in Macro 779" group.byte 0x65C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH780,Uncommitted Supervisorly Flash in Macro 780" group.byte 0x65D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH781,Uncommitted Supervisorly Flash in Macro 781" group.byte 0x65E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH782,Uncommitted Supervisorly Flash in Macro 782" group.byte 0x65F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH783,Uncommitted Supervisorly Flash in Macro 783" group.byte 0x660++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH784,Uncommitted Supervisorly Flash in Macro 784" group.byte 0x661++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH785,Uncommitted Supervisorly Flash in Macro 785" group.byte 0x662++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH786,Uncommitted Supervisorly Flash in Macro 786" group.byte 0x663++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH787,Uncommitted Supervisorly Flash in Macro 787" group.byte 0x664++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH788,Uncommitted Supervisorly Flash in Macro 788" group.byte 0x665++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH789,Uncommitted Supervisorly Flash in Macro 789" group.byte 0x666++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH790,Uncommitted Supervisorly Flash in Macro 790" group.byte 0x667++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH791,Uncommitted Supervisorly Flash in Macro 791" group.byte 0x668++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH792,Uncommitted Supervisorly Flash in Macro 792" group.byte 0x669++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH793,Uncommitted Supervisorly Flash in Macro 793" group.byte 0x66A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH794,Uncommitted Supervisorly Flash in Macro 794" group.byte 0x66B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH795,Uncommitted Supervisorly Flash in Macro 795" group.byte 0x66C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH796,Uncommitted Supervisorly Flash in Macro 796" group.byte 0x66D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH797,Uncommitted Supervisorly Flash in Macro 797" group.byte 0x66E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH798,Uncommitted Supervisorly Flash in Macro 798" group.byte 0x66F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH799,Uncommitted Supervisorly Flash in Macro 799" group.byte 0x670++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH800,Uncommitted Supervisorly Flash in Macro 800" group.byte 0x671++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH801,Uncommitted Supervisorly Flash in Macro 801" group.byte 0x672++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH802,Uncommitted Supervisorly Flash in Macro 802" group.byte 0x673++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH803,Uncommitted Supervisorly Flash in Macro 803" group.byte 0x674++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH804,Uncommitted Supervisorly Flash in Macro 804" group.byte 0x675++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH805,Uncommitted Supervisorly Flash in Macro 805" group.byte 0x676++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH806,Uncommitted Supervisorly Flash in Macro 806" group.byte 0x677++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH807,Uncommitted Supervisorly Flash in Macro 807" group.byte 0x678++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH808,Uncommitted Supervisorly Flash in Macro 808" group.byte 0x679++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH809,Uncommitted Supervisorly Flash in Macro 809" group.byte 0x67A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH810,Uncommitted Supervisorly Flash in Macro 810" group.byte 0x67B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH811,Uncommitted Supervisorly Flash in Macro 811" group.byte 0x67C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH812,Uncommitted Supervisorly Flash in Macro 812" group.byte 0x67D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH813,Uncommitted Supervisorly Flash in Macro 813" group.byte 0x67E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH814,Uncommitted Supervisorly Flash in Macro 814" group.byte 0x67F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH815,Uncommitted Supervisorly Flash in Macro 815" group.byte 0x680++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH816,Uncommitted Supervisorly Flash in Macro 816" group.byte 0x681++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH817,Uncommitted Supervisorly Flash in Macro 817" group.byte 0x682++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH818,Uncommitted Supervisorly Flash in Macro 818" group.byte 0x683++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH819,Uncommitted Supervisorly Flash in Macro 819" group.byte 0x684++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH820,Uncommitted Supervisorly Flash in Macro 820" group.byte 0x685++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH821,Uncommitted Supervisorly Flash in Macro 821" group.byte 0x686++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH822,Uncommitted Supervisorly Flash in Macro 822" group.byte 0x687++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH823,Uncommitted Supervisorly Flash in Macro 823" group.byte 0x688++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH824,Uncommitted Supervisorly Flash in Macro 824" group.byte 0x689++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH825,Uncommitted Supervisorly Flash in Macro 825" group.byte 0x68A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH826,Uncommitted Supervisorly Flash in Macro 826" group.byte 0x68B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH827,Uncommitted Supervisorly Flash in Macro 827" group.byte 0x68C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH828,Uncommitted Supervisorly Flash in Macro 828" group.byte 0x68D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH829,Uncommitted Supervisorly Flash in Macro 829" group.byte 0x68E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH830,Uncommitted Supervisorly Flash in Macro 830" group.byte 0x68F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH831,Uncommitted Supervisorly Flash in Macro 831" group.byte 0x690++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH832,Uncommitted Supervisorly Flash in Macro 832" group.byte 0x691++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH833,Uncommitted Supervisorly Flash in Macro 833" group.byte 0x692++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH834,Uncommitted Supervisorly Flash in Macro 834" group.byte 0x693++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH835,Uncommitted Supervisorly Flash in Macro 835" group.byte 0x694++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH836,Uncommitted Supervisorly Flash in Macro 836" group.byte 0x695++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH837,Uncommitted Supervisorly Flash in Macro 837" group.byte 0x696++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH838,Uncommitted Supervisorly Flash in Macro 838" group.byte 0x697++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH839,Uncommitted Supervisorly Flash in Macro 839" group.byte 0x698++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH840,Uncommitted Supervisorly Flash in Macro 840" group.byte 0x699++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH841,Uncommitted Supervisorly Flash in Macro 841" group.byte 0x69A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH842,Uncommitted Supervisorly Flash in Macro 842" group.byte 0x69B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH843,Uncommitted Supervisorly Flash in Macro 843" group.byte 0x69C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH844,Uncommitted Supervisorly Flash in Macro 844" group.byte 0x69D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH845,Uncommitted Supervisorly Flash in Macro 845" group.byte 0x69E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH846,Uncommitted Supervisorly Flash in Macro 846" group.byte 0x69F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH847,Uncommitted Supervisorly Flash in Macro 847" group.byte 0x6A0++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH848,Uncommitted Supervisorly Flash in Macro 848" group.byte 0x6A1++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH849,Uncommitted Supervisorly Flash in Macro 849" group.byte 0x6A2++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH850,Uncommitted Supervisorly Flash in Macro 850" group.byte 0x6A3++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH851,Uncommitted Supervisorly Flash in Macro 851" group.byte 0x6A4++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH852,Uncommitted Supervisorly Flash in Macro 852" group.byte 0x6A5++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH853,Uncommitted Supervisorly Flash in Macro 853" group.byte 0x6A6++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH854,Uncommitted Supervisorly Flash in Macro 854" group.byte 0x6A7++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH855,Uncommitted Supervisorly Flash in Macro 855" group.byte 0x6A8++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH856,Uncommitted Supervisorly Flash in Macro 856" group.byte 0x6A9++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH857,Uncommitted Supervisorly Flash in Macro 857" group.byte 0x6AA++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH858,Uncommitted Supervisorly Flash in Macro 858" group.byte 0x6AB++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH859,Uncommitted Supervisorly Flash in Macro 859" group.byte 0x6AC++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH860,Uncommitted Supervisorly Flash in Macro 860" group.byte 0x6AD++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH861,Uncommitted Supervisorly Flash in Macro 861" group.byte 0x6AE++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH862,Uncommitted Supervisorly Flash in Macro 862" group.byte 0x6AF++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH863,Uncommitted Supervisorly Flash in Macro 863" group.byte 0x6B0++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH864,Uncommitted Supervisorly Flash in Macro 864" group.byte 0x6B1++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH865,Uncommitted Supervisorly Flash in Macro 865" group.byte 0x6B2++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH866,Uncommitted Supervisorly Flash in Macro 866" group.byte 0x6B3++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH867,Uncommitted Supervisorly Flash in Macro 867" group.byte 0x6B4++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH868,Uncommitted Supervisorly Flash in Macro 868" group.byte 0x6B5++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH869,Uncommitted Supervisorly Flash in Macro 869" group.byte 0x6B6++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH870,Uncommitted Supervisorly Flash in Macro 870" group.byte 0x6B7++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH871,Uncommitted Supervisorly Flash in Macro 871" group.byte 0x6B8++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH872,Uncommitted Supervisorly Flash in Macro 872" group.byte 0x6B9++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH873,Uncommitted Supervisorly Flash in Macro 873" group.byte 0x6BA++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH874,Uncommitted Supervisorly Flash in Macro 874" group.byte 0x6BB++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH875,Uncommitted Supervisorly Flash in Macro 875" group.byte 0x6BC++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH876,Uncommitted Supervisorly Flash in Macro 876" group.byte 0x6BD++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH877,Uncommitted Supervisorly Flash in Macro 877" group.byte 0x6BE++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH878,Uncommitted Supervisorly Flash in Macro 878" group.byte 0x6BF++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH879,Uncommitted Supervisorly Flash in Macro 879" group.byte 0x6C0++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH880,Uncommitted Supervisorly Flash in Macro 880" group.byte 0x6C1++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH881,Uncommitted Supervisorly Flash in Macro 881" group.byte 0x6C2++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH882,Uncommitted Supervisorly Flash in Macro 882" group.byte 0x6C3++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH883,Uncommitted Supervisorly Flash in Macro 883" group.byte 0x6C4++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH884,Uncommitted Supervisorly Flash in Macro 884" group.byte 0x6C5++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH885,Uncommitted Supervisorly Flash in Macro 885" group.byte 0x6C6++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH886,Uncommitted Supervisorly Flash in Macro 886" group.byte 0x6C7++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH887,Uncommitted Supervisorly Flash in Macro 887" group.byte 0x6C8++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH888,Uncommitted Supervisorly Flash in Macro 888" group.byte 0x6C9++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH889,Uncommitted Supervisorly Flash in Macro 889" group.byte 0x6CA++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH890,Uncommitted Supervisorly Flash in Macro 890" group.byte 0x6CB++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH891,Uncommitted Supervisorly Flash in Macro 891" group.byte 0x6CC++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH892,Uncommitted Supervisorly Flash in Macro 892" group.byte 0x6CD++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH893,Uncommitted Supervisorly Flash in Macro 893" group.byte 0x6CE++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH894,Uncommitted Supervisorly Flash in Macro 894" group.byte 0x6CF++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH895,Uncommitted Supervisorly Flash in Macro 895" group.byte 0x6D0++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH896,Uncommitted Supervisorly Flash in Macro 896" group.byte 0x6D1++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH897,Uncommitted Supervisorly Flash in Macro 897" group.byte 0x6D2++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH898,Uncommitted Supervisorly Flash in Macro 898" group.byte 0x6D3++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH899,Uncommitted Supervisorly Flash in Macro 899" group.byte 0x6D4++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH900,Uncommitted Supervisorly Flash in Macro 900" group.byte 0x6D5++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH901,Uncommitted Supervisorly Flash in Macro 901" group.byte 0x6D6++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH902,Uncommitted Supervisorly Flash in Macro 902" group.byte 0x6D7++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH903,Uncommitted Supervisorly Flash in Macro 903" group.byte 0x6D8++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH904,Uncommitted Supervisorly Flash in Macro 904" group.byte 0x6D9++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH905,Uncommitted Supervisorly Flash in Macro 905" group.byte 0x6DA++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH906,Uncommitted Supervisorly Flash in Macro 906" group.byte 0x6DB++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH907,Uncommitted Supervisorly Flash in Macro 907" group.byte 0x6DC++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH908,Uncommitted Supervisorly Flash in Macro 908" group.byte 0x6DD++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH909,Uncommitted Supervisorly Flash in Macro 909" group.byte 0x6DE++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH910,Uncommitted Supervisorly Flash in Macro 910" group.byte 0x6DF++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH911,Uncommitted Supervisorly Flash in Macro 911" group.byte 0x6E0++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH912,Uncommitted Supervisorly Flash in Macro 912" group.byte 0x6E1++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH913,Uncommitted Supervisorly Flash in Macro 913" group.byte 0x6E2++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH914,Uncommitted Supervisorly Flash in Macro 914" group.byte 0x6E3++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH915,Uncommitted Supervisorly Flash in Macro 915" group.byte 0x6E4++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH916,Uncommitted Supervisorly Flash in Macro 916" group.byte 0x6E5++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH917,Uncommitted Supervisorly Flash in Macro 917" group.byte 0x6E6++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH918,Uncommitted Supervisorly Flash in Macro 918" group.byte 0x6E7++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH919,Uncommitted Supervisorly Flash in Macro 919" group.byte 0x6E8++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH920,Uncommitted Supervisorly Flash in Macro 920" group.byte 0x6E9++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH921,Uncommitted Supervisorly Flash in Macro 921" group.byte 0x6EA++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH922,Uncommitted Supervisorly Flash in Macro 922" group.byte 0x6EB++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH923,Uncommitted Supervisorly Flash in Macro 923" group.byte 0x6EC++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH924,Uncommitted Supervisorly Flash in Macro 924" group.byte 0x6ED++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH925,Uncommitted Supervisorly Flash in Macro 925" group.byte 0x6EE++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH926,Uncommitted Supervisorly Flash in Macro 926" group.byte 0x6EF++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH927,Uncommitted Supervisorly Flash in Macro 927" group.byte 0x6F0++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH928,Uncommitted Supervisorly Flash in Macro 928" group.byte 0x6F1++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH929,Uncommitted Supervisorly Flash in Macro 929" group.byte 0x6F2++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH930,Uncommitted Supervisorly Flash in Macro 930" group.byte 0x6F3++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH931,Uncommitted Supervisorly Flash in Macro 931" group.byte 0x6F4++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH932,Uncommitted Supervisorly Flash in Macro 932" group.byte 0x6F5++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH933,Uncommitted Supervisorly Flash in Macro 933" group.byte 0x6F6++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH934,Uncommitted Supervisorly Flash in Macro 934" group.byte 0x6F7++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH935,Uncommitted Supervisorly Flash in Macro 935" group.byte 0x6F8++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH936,Uncommitted Supervisorly Flash in Macro 936" group.byte 0x6F9++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH937,Uncommitted Supervisorly Flash in Macro 937" group.byte 0x6FA++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH938,Uncommitted Supervisorly Flash in Macro 938" group.byte 0x6FB++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH939,Uncommitted Supervisorly Flash in Macro 939" group.byte 0x6FC++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH940,Uncommitted Supervisorly Flash in Macro 940" group.byte 0x6FD++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH941,Uncommitted Supervisorly Flash in Macro 941" group.byte 0x6FE++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH942,Uncommitted Supervisorly Flash in Macro 942" group.byte 0x6FF++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH943,Uncommitted Supervisorly Flash in Macro 943" group.byte 0x700++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH944,Uncommitted Supervisorly Flash in Macro 944" group.byte 0x701++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH945,Uncommitted Supervisorly Flash in Macro 945" group.byte 0x702++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH946,Uncommitted Supervisorly Flash in Macro 946" group.byte 0x703++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH947,Uncommitted Supervisorly Flash in Macro 947" group.byte 0x704++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH948,Uncommitted Supervisorly Flash in Macro 948" group.byte 0x705++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH949,Uncommitted Supervisorly Flash in Macro 949" group.byte 0x706++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH950,Uncommitted Supervisorly Flash in Macro 950" group.byte 0x707++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH951,Uncommitted Supervisorly Flash in Macro 951" group.byte 0x708++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH952,Uncommitted Supervisorly Flash in Macro 952" group.byte 0x709++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH953,Uncommitted Supervisorly Flash in Macro 953" group.byte 0x70A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH954,Uncommitted Supervisorly Flash in Macro 954" group.byte 0x70B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH955,Uncommitted Supervisorly Flash in Macro 955" group.byte 0x70C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH956,Uncommitted Supervisorly Flash in Macro 956" group.byte 0x70D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH957,Uncommitted Supervisorly Flash in Macro 957" group.byte 0x70E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH958,Uncommitted Supervisorly Flash in Macro 958" group.byte 0x70F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH959,Uncommitted Supervisorly Flash in Macro 959" group.byte 0x710++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH960,Uncommitted Supervisorly Flash in Macro 960" group.byte 0x711++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH961,Uncommitted Supervisorly Flash in Macro 961" group.byte 0x712++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH962,Uncommitted Supervisorly Flash in Macro 962" group.byte 0x713++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH963,Uncommitted Supervisorly Flash in Macro 963" group.byte 0x714++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH964,Uncommitted Supervisorly Flash in Macro 964" group.byte 0x715++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH965,Uncommitted Supervisorly Flash in Macro 965" group.byte 0x716++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH966,Uncommitted Supervisorly Flash in Macro 966" group.byte 0x717++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH967,Uncommitted Supervisorly Flash in Macro 967" group.byte 0x718++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH968,Uncommitted Supervisorly Flash in Macro 968" group.byte 0x719++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH969,Uncommitted Supervisorly Flash in Macro 969" group.byte 0x71A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH970,Uncommitted Supervisorly Flash in Macro 970" group.byte 0x71B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH971,Uncommitted Supervisorly Flash in Macro 971" group.byte 0x71C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH972,Uncommitted Supervisorly Flash in Macro 972" group.byte 0x71D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH973,Uncommitted Supervisorly Flash in Macro 973" group.byte 0x71E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH974,Uncommitted Supervisorly Flash in Macro 974" group.byte 0x71F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH975,Uncommitted Supervisorly Flash in Macro 975" group.byte 0x720++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH976,Uncommitted Supervisorly Flash in Macro 976" group.byte 0x721++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH977,Uncommitted Supervisorly Flash in Macro 977" group.byte 0x722++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH978,Uncommitted Supervisorly Flash in Macro 978" group.byte 0x723++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH979,Uncommitted Supervisorly Flash in Macro 979" group.byte 0x724++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH980,Uncommitted Supervisorly Flash in Macro 980" group.byte 0x725++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH981,Uncommitted Supervisorly Flash in Macro 981" group.byte 0x726++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH982,Uncommitted Supervisorly Flash in Macro 982" group.byte 0x727++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH983,Uncommitted Supervisorly Flash in Macro 983" group.byte 0x728++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH984,Uncommitted Supervisorly Flash in Macro 984" group.byte 0x729++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH985,Uncommitted Supervisorly Flash in Macro 985" group.byte 0x72A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH986,Uncommitted Supervisorly Flash in Macro 986" group.byte 0x72B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH987,Uncommitted Supervisorly Flash in Macro 987" group.byte 0x72C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH988,Uncommitted Supervisorly Flash in Macro 988" group.byte 0x72D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH989,Uncommitted Supervisorly Flash in Macro 989" group.byte 0x72E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH990,Uncommitted Supervisorly Flash in Macro 990" group.byte 0x72F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH991,Uncommitted Supervisorly Flash in Macro 991" group.byte 0x730++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH992,Uncommitted Supervisorly Flash in Macro 992" group.byte 0x731++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH993,Uncommitted Supervisorly Flash in Macro 993" group.byte 0x732++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH994,Uncommitted Supervisorly Flash in Macro 994" group.byte 0x733++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH995,Uncommitted Supervisorly Flash in Macro 995" group.byte 0x734++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH996,Uncommitted Supervisorly Flash in Macro 996" group.byte 0x735++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH997,Uncommitted Supervisorly Flash in Macro 997" group.byte 0x736++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH998,Uncommitted Supervisorly Flash in Macro 998" group.byte 0x737++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH999,Uncommitted Supervisorly Flash in Macro 999" group.byte 0x738++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1000,Uncommitted Supervisorly Flash in Macro 1000" group.byte 0x739++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1001,Uncommitted Supervisorly Flash in Macro 1001" group.byte 0x73A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1002,Uncommitted Supervisorly Flash in Macro 1002" group.byte 0x73B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1003,Uncommitted Supervisorly Flash in Macro 1003" group.byte 0x73C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1004,Uncommitted Supervisorly Flash in Macro 1004" group.byte 0x73D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1005,Uncommitted Supervisorly Flash in Macro 1005" group.byte 0x73E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1006,Uncommitted Supervisorly Flash in Macro 1006" group.byte 0x73F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1007,Uncommitted Supervisorly Flash in Macro 1007" group.byte 0x740++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1008,Uncommitted Supervisorly Flash in Macro 1008" group.byte 0x741++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1009,Uncommitted Supervisorly Flash in Macro 1009" group.byte 0x742++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1010,Uncommitted Supervisorly Flash in Macro 1010" group.byte 0x743++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1011,Uncommitted Supervisorly Flash in Macro 1011" group.byte 0x744++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1012,Uncommitted Supervisorly Flash in Macro 1012" group.byte 0x745++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1013,Uncommitted Supervisorly Flash in Macro 1013" group.byte 0x746++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1014,Uncommitted Supervisorly Flash in Macro 1014" group.byte 0x747++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1015,Uncommitted Supervisorly Flash in Macro 1015" group.byte 0x748++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1016,Uncommitted Supervisorly Flash in Macro 1016" group.byte 0x749++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1017,Uncommitted Supervisorly Flash in Macro 1017" group.byte 0x74A++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1018,Uncommitted Supervisorly Flash in Macro 1018" group.byte 0x74B++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1019,Uncommitted Supervisorly Flash in Macro 1019" group.byte 0x74C++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1020,Uncommitted Supervisorly Flash in Macro 1020" group.byte 0x74D++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1021,Uncommitted Supervisorly Flash in Macro 1021" group.byte 0x74E++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1022,Uncommitted Supervisorly Flash in Macro 1022" group.byte 0x74F++0x00 line.byte 0x00 "SFLASH_MACRO_0_FREE_SFLASH1023,Uncommitted Supervisorly Flash in Macro 1023" endif tree.end textline " " tree "SFLASH_ALT_PROT_ROW" group.byte 0x800++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW0,Per Page Write Protection 0" group.byte 0x801++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW1,Per Page Write Protection 1" group.byte 0x802++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW2,Per Page Write Protection 2" group.byte 0x803++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW3,Per Page Write Protection 3" group.byte 0x804++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW4,Per Page Write Protection 4" group.byte 0x805++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW5,Per Page Write Protection 5" group.byte 0x806++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW6,Per Page Write Protection 6" group.byte 0x807++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW7,Per Page Write Protection 7" group.byte 0x808++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW8,Per Page Write Protection 8" group.byte 0x809++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW9,Per Page Write Protection 9" group.byte 0x80A++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW10,Per Page Write Protection 10" group.byte 0x80B++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW11,Per Page Write Protection 11" group.byte 0x80C++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW12,Per Page Write Protection 12" group.byte 0x80D++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW13,Per Page Write Protection 13" group.byte 0x80E++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW14,Per Page Write Protection 14" group.byte 0x80F++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW15,Per Page Write Protection 15" group.byte 0x810++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW16,Per Page Write Protection 16" group.byte 0x811++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW17,Per Page Write Protection 17" group.byte 0x812++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW18,Per Page Write Protection 18" group.byte 0x813++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW19,Per Page Write Protection 19" group.byte 0x814++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW20,Per Page Write Protection 20" group.byte 0x815++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW21,Per Page Write Protection 21" group.byte 0x816++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW22,Per Page Write Protection 22" group.byte 0x817++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW23,Per Page Write Protection 23" group.byte 0x818++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW24,Per Page Write Protection 24" group.byte 0x819++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW25,Per Page Write Protection 25" group.byte 0x81A++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW26,Per Page Write Protection 26" group.byte 0x81B++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW27,Per Page Write Protection 27" group.byte 0x81C++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW28,Per Page Write Protection 28" group.byte 0x81D++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW29,Per Page Write Protection 29" group.byte 0x81E++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW30,Per Page Write Protection 30" group.byte 0x81F++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW31,Per Page Write Protection 31" group.byte 0x820++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW32,Per Page Write Protection 32" group.byte 0x821++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW33,Per Page Write Protection 33" group.byte 0x822++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW34,Per Page Write Protection 34" group.byte 0x823++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW35,Per Page Write Protection 35" group.byte 0x824++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW36,Per Page Write Protection 36" group.byte 0x825++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW37,Per Page Write Protection 37" group.byte 0x826++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW38,Per Page Write Protection 38" group.byte 0x827++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW39,Per Page Write Protection 39" group.byte 0x828++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW40,Per Page Write Protection 40" group.byte 0x829++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW41,Per Page Write Protection 41" group.byte 0x82A++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW42,Per Page Write Protection 42" group.byte 0x82B++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW43,Per Page Write Protection 43" group.byte 0x82C++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW44,Per Page Write Protection 44" group.byte 0x82D++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW45,Per Page Write Protection 45" group.byte 0x82E++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW46,Per Page Write Protection 46" group.byte 0x82F++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW47,Per Page Write Protection 47" group.byte 0x830++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW48,Per Page Write Protection 48" group.byte 0x831++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW49,Per Page Write Protection 49" group.byte 0x832++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW50,Per Page Write Protection 50" group.byte 0x833++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW51,Per Page Write Protection 51" group.byte 0x834++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW52,Per Page Write Protection 52" group.byte 0x835++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW53,Per Page Write Protection 53" group.byte 0x836++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW54,Per Page Write Protection 54" group.byte 0x837++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW55,Per Page Write Protection 55" group.byte 0x838++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW56,Per Page Write Protection 56" group.byte 0x839++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW57,Per Page Write Protection 57" group.byte 0x83A++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW58,Per Page Write Protection 58" group.byte 0x83B++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW59,Per Page Write Protection 59" group.byte 0x83C++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW60,Per Page Write Protection 60" group.byte 0x83D++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW61,Per Page Write Protection 61" group.byte 0x83E++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW62,Per Page Write Protection 62" group.byte 0x83F++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW63,Per Page Write Protection 63" group.byte 0x840++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW64,Per Page Write Protection 64" group.byte 0x841++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW65,Per Page Write Protection 65" group.byte 0x842++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW66,Per Page Write Protection 66" group.byte 0x843++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW67,Per Page Write Protection 67" group.byte 0x844++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW68,Per Page Write Protection 68" group.byte 0x845++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW69,Per Page Write Protection 69" group.byte 0x846++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW70,Per Page Write Protection 70" group.byte 0x847++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW71,Per Page Write Protection 71" group.byte 0x848++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW72,Per Page Write Protection 72" group.byte 0x849++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW73,Per Page Write Protection 73" group.byte 0x84A++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW74,Per Page Write Protection 74" group.byte 0x84B++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW75,Per Page Write Protection 75" group.byte 0x84C++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW76,Per Page Write Protection 76" group.byte 0x84D++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW77,Per Page Write Protection 77" group.byte 0x84E++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW78,Per Page Write Protection 78" group.byte 0x84F++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW79,Per Page Write Protection 79" group.byte 0x850++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW80,Per Page Write Protection 80" group.byte 0x851++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW81,Per Page Write Protection 81" group.byte 0x852++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW82,Per Page Write Protection 82" group.byte 0x853++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW83,Per Page Write Protection 83" group.byte 0x854++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW84,Per Page Write Protection 84" group.byte 0x855++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW85,Per Page Write Protection 85" group.byte 0x856++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW86,Per Page Write Protection 86" group.byte 0x857++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW87,Per Page Write Protection 87" group.byte 0x858++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW88,Per Page Write Protection 88" group.byte 0x859++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW89,Per Page Write Protection 89" group.byte 0x85A++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW90,Per Page Write Protection 90" group.byte 0x85B++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW91,Per Page Write Protection 91" group.byte 0x85C++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW92,Per Page Write Protection 92" group.byte 0x85D++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW93,Per Page Write Protection 93" group.byte 0x85E++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW94,Per Page Write Protection 94" group.byte 0x85F++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW95,Per Page Write Protection 95" group.byte 0x860++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW96,Per Page Write Protection 96" group.byte 0x861++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW97,Per Page Write Protection 97" group.byte 0x862++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW98,Per Page Write Protection 98" group.byte 0x863++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW99,Per Page Write Protection 99" group.byte 0x864++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW100,Per Page Write Protection 100" group.byte 0x865++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW101,Per Page Write Protection 101" group.byte 0x866++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW102,Per Page Write Protection 102" group.byte 0x867++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW103,Per Page Write Protection 103" group.byte 0x868++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW104,Per Page Write Protection 104" group.byte 0x869++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW105,Per Page Write Protection 105" group.byte 0x86A++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW106,Per Page Write Protection 106" group.byte 0x86B++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW107,Per Page Write Protection 107" group.byte 0x86C++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW108,Per Page Write Protection 108" group.byte 0x86D++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW109,Per Page Write Protection 109" group.byte 0x86E++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW110,Per Page Write Protection 110" group.byte 0x86F++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW111,Per Page Write Protection 111" group.byte 0x870++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW112,Per Page Write Protection 112" group.byte 0x871++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW113,Per Page Write Protection 113" group.byte 0x872++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW114,Per Page Write Protection 114" group.byte 0x873++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW115,Per Page Write Protection 115" group.byte 0x874++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW116,Per Page Write Protection 116" group.byte 0x875++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW117,Per Page Write Protection 117" group.byte 0x876++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW118,Per Page Write Protection 118" group.byte 0x877++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW119,Per Page Write Protection 119" group.byte 0x878++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW120,Per Page Write Protection 120" group.byte 0x879++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW121,Per Page Write Protection 121" group.byte 0x87A++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW122,Per Page Write Protection 122" group.byte 0x87B++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW123,Per Page Write Protection 123" group.byte 0x87C++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW124,Per Page Write Protection 124" group.byte 0x87D++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW125,Per Page Write Protection 125" group.byte 0x87E++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW126,Per Page Write Protection 126" group.byte 0x87F++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW127,Per Page Write Protection 127" group.byte 0x880++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW128,Per Page Write Protection 128" group.byte 0x881++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW129,Per Page Write Protection 129" group.byte 0x882++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW130,Per Page Write Protection 130" group.byte 0x883++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW131,Per Page Write Protection 131" group.byte 0x884++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW132,Per Page Write Protection 132" group.byte 0x885++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW133,Per Page Write Protection 133" group.byte 0x886++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW134,Per Page Write Protection 134" group.byte 0x887++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW135,Per Page Write Protection 135" group.byte 0x888++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW136,Per Page Write Protection 136" group.byte 0x889++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW137,Per Page Write Protection 137" group.byte 0x88A++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW138,Per Page Write Protection 138" group.byte 0x88B++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW139,Per Page Write Protection 139" group.byte 0x88C++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW140,Per Page Write Protection 140" group.byte 0x88D++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW141,Per Page Write Protection 141" group.byte 0x88E++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW142,Per Page Write Protection 142" group.byte 0x88F++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW143,Per Page Write Protection 143" group.byte 0x890++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW144,Per Page Write Protection 144" group.byte 0x891++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW145,Per Page Write Protection 145" group.byte 0x892++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW146,Per Page Write Protection 146" group.byte 0x893++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW147,Per Page Write Protection 147" group.byte 0x894++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW148,Per Page Write Protection 148" group.byte 0x895++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW149,Per Page Write Protection 149" group.byte 0x896++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW150,Per Page Write Protection 150" group.byte 0x897++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW151,Per Page Write Protection 151" group.byte 0x898++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW152,Per Page Write Protection 152" group.byte 0x899++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW153,Per Page Write Protection 153" group.byte 0x89A++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW154,Per Page Write Protection 154" group.byte 0x89B++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW155,Per Page Write Protection 155" group.byte 0x89C++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW156,Per Page Write Protection 156" group.byte 0x89D++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW157,Per Page Write Protection 157" group.byte 0x89E++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW158,Per Page Write Protection 158" group.byte 0x89F++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW159,Per Page Write Protection 159" group.byte 0x8A0++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW160,Per Page Write Protection 160" group.byte 0x8A1++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW161,Per Page Write Protection 161" group.byte 0x8A2++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW162,Per Page Write Protection 162" group.byte 0x8A3++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW163,Per Page Write Protection 163" group.byte 0x8A4++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW164,Per Page Write Protection 164" group.byte 0x8A5++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW165,Per Page Write Protection 165" group.byte 0x8A6++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW166,Per Page Write Protection 166" group.byte 0x8A7++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW167,Per Page Write Protection 167" group.byte 0x8A8++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW168,Per Page Write Protection 168" group.byte 0x8A9++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW169,Per Page Write Protection 169" group.byte 0x8AA++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW170,Per Page Write Protection 170" group.byte 0x8AB++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW171,Per Page Write Protection 171" group.byte 0x8AC++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW172,Per Page Write Protection 172" group.byte 0x8AD++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW173,Per Page Write Protection 173" group.byte 0x8AE++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW174,Per Page Write Protection 174" group.byte 0x8AF++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW175,Per Page Write Protection 175" group.byte 0x8B0++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW176,Per Page Write Protection 176" group.byte 0x8B1++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW177,Per Page Write Protection 177" group.byte 0x8B2++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW178,Per Page Write Protection 178" group.byte 0x8B3++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW179,Per Page Write Protection 179" group.byte 0x8B4++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW180,Per Page Write Protection 180" group.byte 0x8B5++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW181,Per Page Write Protection 181" group.byte 0x8B6++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW182,Per Page Write Protection 182" group.byte 0x8B7++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW183,Per Page Write Protection 183" group.byte 0x8B8++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW184,Per Page Write Protection 184" group.byte 0x8B9++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW185,Per Page Write Protection 185" group.byte 0x8BA++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW186,Per Page Write Protection 186" group.byte 0x8BB++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW187,Per Page Write Protection 187" group.byte 0x8BC++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW188,Per Page Write Protection 188" group.byte 0x8BD++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW189,Per Page Write Protection 189" group.byte 0x8BE++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW190,Per Page Write Protection 190" group.byte 0x8BF++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW191,Per Page Write Protection 191" group.byte 0x8C0++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW192,Per Page Write Protection 192" group.byte 0x8C1++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW193,Per Page Write Protection 193" group.byte 0x8C2++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW194,Per Page Write Protection 194" group.byte 0x8C3++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW195,Per Page Write Protection 195" group.byte 0x8C4++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW196,Per Page Write Protection 196" group.byte 0x8C5++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW197,Per Page Write Protection 197" group.byte 0x8C6++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW198,Per Page Write Protection 198" group.byte 0x8C7++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW199,Per Page Write Protection 199" group.byte 0x8C8++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW200,Per Page Write Protection 200" group.byte 0x8C9++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW201,Per Page Write Protection 201" group.byte 0x8CA++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW202,Per Page Write Protection 202" group.byte 0x8CB++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW203,Per Page Write Protection 203" group.byte 0x8CC++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW204,Per Page Write Protection 204" group.byte 0x8CD++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW205,Per Page Write Protection 205" group.byte 0x8CE++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW206,Per Page Write Protection 206" group.byte 0x8CF++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW207,Per Page Write Protection 207" group.byte 0x8D0++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW208,Per Page Write Protection 208" group.byte 0x8D1++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW209,Per Page Write Protection 209" group.byte 0x8D2++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW210,Per Page Write Protection 210" group.byte 0x8D3++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW211,Per Page Write Protection 211" group.byte 0x8D4++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW212,Per Page Write Protection 212" group.byte 0x8D5++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW213,Per Page Write Protection 213" group.byte 0x8D6++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW214,Per Page Write Protection 214" group.byte 0x8D7++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW215,Per Page Write Protection 215" group.byte 0x8D8++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW216,Per Page Write Protection 216" group.byte 0x8D9++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW217,Per Page Write Protection 217" group.byte 0x8DA++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW218,Per Page Write Protection 218" group.byte 0x8DB++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW219,Per Page Write Protection 219" group.byte 0x8DC++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW220,Per Page Write Protection 220" group.byte 0x8DD++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW221,Per Page Write Protection 221" group.byte 0x8DE++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW222,Per Page Write Protection 222" group.byte 0x8DF++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW223,Per Page Write Protection 223" group.byte 0x8E0++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW224,Per Page Write Protection 224" group.byte 0x8E1++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW225,Per Page Write Protection 225" group.byte 0x8E2++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW226,Per Page Write Protection 226" group.byte 0x8E3++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW227,Per Page Write Protection 227" group.byte 0x8E4++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW228,Per Page Write Protection 228" group.byte 0x8E5++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW229,Per Page Write Protection 229" group.byte 0x8E6++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW230,Per Page Write Protection 230" group.byte 0x8E7++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW231,Per Page Write Protection 231" group.byte 0x8E8++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW232,Per Page Write Protection 232" group.byte 0x8E9++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW233,Per Page Write Protection 233" group.byte 0x8EA++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW234,Per Page Write Protection 234" group.byte 0x8EB++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW235,Per Page Write Protection 235" group.byte 0x8EC++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW236,Per Page Write Protection 236" group.byte 0x8ED++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW237,Per Page Write Protection 237" group.byte 0x8EE++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW238,Per Page Write Protection 238" group.byte 0x8EF++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW239,Per Page Write Protection 239" group.byte 0x8F0++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW240,Per Page Write Protection 240" group.byte 0x8F1++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW241,Per Page Write Protection 241" group.byte 0x8F2++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW242,Per Page Write Protection 242" group.byte 0x8F3++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW243,Per Page Write Protection 243" group.byte 0x8F4++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW244,Per Page Write Protection 244" group.byte 0x8F5++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW245,Per Page Write Protection 245" group.byte 0x8F6++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW246,Per Page Write Protection 246" group.byte 0x8F7++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW247,Per Page Write Protection 247" group.byte 0x8F8++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW248,Per Page Write Protection 248" group.byte 0x8F9++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW249,Per Page Write Protection 249" group.byte 0x8FA++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW250,Per Page Write Protection 250" group.byte 0x8FB++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW251,Per Page Write Protection 251" group.byte 0x8FC++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW252,Per Page Write Protection 252" group.byte 0x8FD++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW253,Per Page Write Protection 253" group.byte 0x8FE++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW254,Per Page Write Protection 254" group.byte 0x8FF++0x00 line.byte 0x00 "SFLASH_ALT_PROT_ROW255,Per Page Write Protection 255" tree.end textline " " group.long 0xB20++0x1B line.long 0x00 "SFLASH_ALT_PP,Preprogram Settings" bitfld.long 0x00 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x00 0.--23. 1. " PERIOD ,Period of timer in clk_spcif_timer ticks" line.long 0x04 "SFLASH_ALT_E,Erase Settings" bitfld.long 0x04 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x04 0.--23. 1. " PERIOD ,Period of timer in clk_spcif_timer ticks" line.long 0x08 "SFLASH_ALT_P,Program Settings" bitfld.long 0x08 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x08 0.--23. 1. " PERIOD ,Period of timer in clk_spcif_timer ticks" line.long 0x0C "SFLASH_ALT_EA_E,Erase All - Erase Settings" bitfld.long 0x0C 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0C 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x0C 0.--23. 1. " PERIOD ,Period of timer in clk_spcif_timer ticks" line.long 0x10 "SFLASH_ALT_EA_P,Erase All - Program Settings" bitfld.long 0x10 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x10 0.--23. 1. " PERIOD ,Period of timer in clk_spcif_timer ticks" line.long 0x14 "SFLASH_ALT_ES_E,Erase Sector - Erase Settings" bitfld.long 0x14 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x14 0.--23. 1. " PERIOD ,Period of timer in clk_spcif_timer ticks" line.long 0x18 "SFLASH_ALT_ES_P_EO,Erase Sector - Program EO Settings" bitfld.long 0x18 28.--31. " NDAC ,NDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 24.--27. " PDAC ,PDAC input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.tbyte 0x18 0.--23. 1. " PERIOD ,Period of timer in clk_spcif_timer ticks" group.byte 0xB3C++0x01 line.byte 0x00 "SFLASH_ALT_E_VCTAT,Bandgap Trim Register" bitfld.byte 0x00 6. " VCTAT_ENABLE ,Enable VCTAT block" "Disabled,Enabled" bitfld.byte 0x00 4.--5. " VCTAT_VOLTAGE ,Output voltage absolute trim" "0,1,2,3" bitfld.byte 0x00 0.--3. " VCTAT_SLOPE ,Output slope setting controls" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.byte 0x01 "SFLASH_ALT_P_VCTAT,Bandgap Trim Register" bitfld.byte 0x01 6. " VCTAT_ENABLE ,Enable VCTAT block" "Disabled,Enabled" bitfld.byte 0x01 4.--5. " VCTAT_VOLTAGE ,Output voltage absolute trim" "0,1,2,3" bitfld.byte 0x01 0.--3. " VCTAT_SLOPE ,Output slope setting controls" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree "SPCIF (SPC Interface registers)" base ad:0x40110000 width 19. group.long 0x00++0x03 line.long 0x00 "SPCIF_GEOMETRY,Flash/NVL Geometry Information" bitfld.long 0x00 31. " DE_CPD_LP ,Busy wait loop to SRAM" "Not occurred,Occurred" hexmask.long.byte 0x00 24.--30. 1. " NVL ,NVLatch size in Byte multiples" rbitfld.long 0x00 22.--23. " FLASH_ROW ,Page size in 64 Byte multiples" "64,128,192,256" rbitfld.long 0x00 20.--21. " NUM_FLASH ,Number of flash macros" "1,2,3,4" textline " " rbitfld.long 0x00 16.--19. " SFLASH ,Supervisory flash capacity in 256 Byte multiples" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.word 0x00 0.--15. 1. " FLASH ,Regular flash capacity in 256 Byte multiples" group.long 0x7F0++0x0F line.long 0x00 "SPCIF_INTR,SPCIF Interrupt Request Register" eventfld.long 0x00 0. " TIMER ,Timer counter value reaches 0" "No interrupt,Interrupt" line.long 0x04 "SPCIF_INTR_SET,SPCIF interrupt set request register" bitfld.long 0x04 0. " TIMER ,Write INTR_SET field with 1 to set corresponding INTR field" "No interrupt,Interrupt" line.long 0x08 "SPCIF_INTR_MASK,SPCIF interrupt mask register" bitfld.long 0x08 0. " TIMER ,Mask for corresponding field in INTR register" "No interrupt,Interrupt" line.long 0x0C "SPCIF_INTR_MASKED,SPCIF interrupt masked request register" rbitfld.long 0x0C 0. " TIMER ,Mask for corresponding field in INTR register" "No interrupt,Interrupt" width 0x0B tree.end tree "SRSS (System Resources Sub-System registers)" base ad:0x400B0000 width 17. if (((per.l(ad:0x400B0000))&0x10000000)==0x10000000) group.long 0x00++0x03 line.long 0x00 "PWR_CONTROL,Power Mode Control" rbitfld.long 0x00 31. " HIBERNATE ,HIBERNATE/DEEPSLEEP modes" "DEEP_SLEEP,HIBERNATE" bitfld.long 0x00 29. " LFCLK_SHORT ,Short Vcclfclk and Vccdpslp power rails in DeepSleep power mode" "No short domain,Short domain" bitfld.long 0x00 28. " HIBERNATE_DISABLE ,Hibernat mode disable" "No,Yes" bitfld.long 0x00 27. " FIMO_DISABLE ,This bit is asserted during the boot process" "12MHz,Normal" textline " " bitfld.long 0x00 25. " HVMON_RELOAD ,Reload HV State in hibernate shadow copy" "Not reloaded,Reloaded" bitfld.long 0x00 24. " HVMON_ENABLE ,HV State Monitoring enable" "Disabled,Enabled" bitfld.long 0x00 23. " EXT_VCCD ,Turns off the active regulator and will lead to system reset (PBOD) unless both Vddd and Vccd pins are supplied externally" "On,Off" rbitfld.long 0x00 5. " LPM_READY ,Indicates whether the low power mode regulators are ready to enter DEEPSLEEP or HIBER-NATE mode" "SLEEP mode,Normal operation" textline " " rbitfld.long 0x00 4. " DEBUG_SESSION ,Indicates whether a debug session is active" "NO_SESSION,SESSION_ACTIVE" rbitfld.long 0x00 0.--3. " POWER_MODE ,Current power mode of the device" "RESET,ACTIVE,SLEEP,DEEP_SLEEP,HIBERNATE,?..." else group.long 0x00++0x03 line.long 0x00 "PWR_CONTROL,Power Mode Control" bitfld.long 0x00 31. " HIBERNATE ,HIBERNATE/DEEPSLEEP modes" "DEEP_SLEEP,HIBERNATE" bitfld.long 0x00 29. " LFCLK_SHORT ,Short Vcclfclk and Vccdpslp power rails in DeepSleep power mode" "No short domain,Short domain" bitfld.long 0x00 28. " HIBERNATE_DISABLE ,Hibernat mode disable" "No,Yes" bitfld.long 0x00 27. " FIMO_DISABLE ,This bit is asserted during the boot process" "12MHz,Normal" textline " " bitfld.long 0x00 25. " HVMON_RELOAD ,Reload HV State in hibernate shadow copy" "Not reloaded,Reloaded" bitfld.long 0x00 24. " HVMON_ENABLE ,HV State Monitoring enable" "Disabled,Enabled" bitfld.long 0x00 23. " EXT_VCCD ,Turns off the active regulator and will lead to system reset (PBOD) unless both Vddd and Vccd pins are supplied externally" "On,Off" rbitfld.long 0x00 5. " LPM_READY ,Indicates whether the low power mode regulators are ready to enter DEEPSLEEP or HIBER-NATE mode" "SLEEP mode,Normal operation" textline " " rbitfld.long 0x00 4. " DEBUG_SESSION ,Indicates whether a debug session is active" "NO_SESSION,SESSION_ACTIVE" rbitfld.long 0x00 0.--3. " POWER_MODE ,Current power mode of the device" "RESET,ACTIVE,SLEEP,DEEP_SLEEP,HIBERNATE,?..." endif group.long 0x04++0x0B line.long 0x00 "PWR_INTR,Power System Interrupt Register" eventfld.long 0x00 1. " LVD ,Indicates an Low Voltage Detect interrupt" "No interrupt,Interrupt" line.long 0x04 "PWR_INTR_MASK,Power System Interrupt Mask Register" bitfld.long 0x04 1. " LVD ,Indicates an Low Voltage Detect interrup" "No interrupt,Interrupt" line.long 0x08 "PWR_KEY_DELAY,Power System Key Register" hexmask.long.word 0x08 0.--9. 1. " WAKEUP_HOLDOFF ,Delay to wait for references to settle on wakeup from hibernate/deepsleep" group.long 0x14++0x07 line.long 0x00 "PWR_BG_CONFIG,Bandgap Trim and Configuration" bitfld.long 0x00 18. " VREF_EN[0] ,Reference voltage enable 0" "Disabled,Enabled" bitfld.long 0x00 17. " VREF_EN[1] ,Reference voltage enable 1" "Disabled,Enabled" bitfld.long 0x00 16. " VREF_EN[2] ,Reference voltage enable 2" "Disabled,Enabled" line.long 0x04 "PWR_VMON_CONFIG,Voltage Monitoring Trim and Configuration" bitfld.long 0x04 1.--4. " LVD_SEL ,Threshold selection for Low Voltage Detect circuit" "1.75V,1.8V,1.9V,2V,2.1V,2.2V,2.3V,2.4V,2.5V,2.6V,2.7V,2.8V,2.9V,3V,3.2V,4.5V" bitfld.long 0x04 0. " LVD_EN ,Enable Low Voltage Detect circuit" "Disabled,Enabled" group.long 0x28++0x07 line.long 0x00 "PWR_BOD_KEY,BOD Detection Key" hexmask.long.word 0x00 0.--15. 1. " KEY16 ,Detect brown-outs KEY16" line.long 0x04 "PWR_STOP,STOP Mode Register" bitfld.long 0x04 31. " STOP ,STOP mode" "Disabled,Enabled" bitfld.long 0x04 17. " FREEZE ,Freeze the configuration, mode and state of all GPIOs and SIOs in the system" "Not stopped,Stopped" bitfld.long 0x04 16. " POLARITY ,Polarity bit" "WAKEUP 0,WAKEUP 1" hexmask.long.byte 0x04 8.--15. 1. " UNLOCK ,operate FREEZE or STOP field" textline " " hexmask.long.byte 0x04 0.--7. 1. " TOKEN , 8-bit token" group.long 0x100++0x0B line.long 0x00 "CLK_SELECT,Clock Select Register" bitfld.long 0x00 19.--21. " SYSCLK_DIV ,SYSCLK Pre-Scaler Value" "/1,/2,/4,/8,/16,/32,/64,/128" bitfld.long 0x00 18. " HALF_EN ,Access FLASH enable bit" "0 wait-state,1 wait-state" bitfld.long 0x00 16.--17. " HFCLK_SEL ,Selects the source for HFCLK" "DIRECT_SEL,DBL,PLL," bitfld.long 0x00 14.--15. " WDT_LOCK ,Prohibits writing to WDT_* registers and CLK_ILO register when not equal 0" "NO_CHG,CLR0,CLR1,SET01" textline " " bitfld.long 0x00 12.--13. " DPLLREF_SEL ,Selects a source for the reference (tracking) input of DPLL" "DSI0,DSI1,DSI2,DSI3" bitfld.long 0x00 9.--11. " DPLLIN_SEL ,Selects a source for the input of DPLL" "IMO,EXTCLK,ECO,DSI0,DSI1,DSI2,DSI3,?..." bitfld.long 0x00 6.--8. " PLL_SEL ,Selects a source the input of EXCO PLL0" "IMO,EXTCLK,ECO,DPLL,DSI0,DSI1,DSI2,DSI3" bitfld.long 0x00 3.--5. " DBL_SEL ,Selects a source the input of EXCO PLL1" "IMO,EXTCLK,ECO,DSI0,DSI1,DSI2,DSI3,?..." textline " " bitfld.long 0x00 0.--2. " DIRECT_SEL ,Selects a source for HFCLK" "IMO,EXTCLK,ECO,DSI0,DSI1,DSI2,DSI3,?..." line.long 0x04 "CLK_ILO_CONFIG,ILO Configuration" bitfld.long 0x04 31. " ENABLE ,Master enable for ILO oscillator" "Disabled,Enabled" bitfld.long 0x04 2. " SATBIAS ,PFET bias" "SATURATED,SUBTHRESHOLD" bitfld.long 0x04 1. " TURBO ,Turbo mode for faster startup from coma power down" "Disabled,Enabled" rbitfld.long 0x04 0. " PD_MODE ,Power down mode" "SLEEP,?..." line.long 0x08 "CLK_IMO_CONFIG,IMO Configuration" bitfld.long 0x08 31. " ENABLE ,Master enable for IMO oscillator" "Disabled,Enabled" bitfld.long 0x08 29. " EN_CLK36 ,Enables 36MHz secondary oscillator that can be used for Pump or Flash Pump" "Disabled,Enabled" bitfld.long 0x08 25.--27. " PUMP_SEL ,Selects operating source for Pump clock" "GND,IMO,DBL,CLK36,FF1,?..." bitfld.long 0x08 22. " FLASHPUMP_SEL ,Selects operating source for SPCIF Timer/Flash Pump clock" "GND,CLK36" if (((per.l(ad:0x400B0000+0x10C))&0xC0000000)==0x40000000) group.long 0x10C++0x03 line.long 0x00 "CLK_IMO_SPREAD,IMO Spread Spectrum Configuration" bitfld.long 0x00 30.--31. " SS_MODE ,Spread Spectrum Mode" "Off,TRIANGLE,LFSR,DSI" bitfld.long 0x00 28.--29. " SS_RANGE ,Spread spectrum range" "M1,M2,M4,?..." bitfld.long 0x00 8.--12. " SS_MAX ,Maximum counter value for spread spectrum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 0.--4. " SS_VALUE ,Current offset value for spread spectrum modulation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" elif (((per.l(ad:0x400B0000+0x10C))&0xC0000000)==0x00) group.long 0x10C++0x03 line.long 0x00 "CLK_IMO_SPREAD,IMO Spread Spectrum Configuration" bitfld.long 0x00 30.--31. " SS_MODE ,Spread Spectrum Mode" "Off,TRIANGLE,LFSR,DSI" rbitfld.long 0x00 28.--29. " SS_RANGE ,Spread spectrum range" "M1,M2,M4,?..." bitfld.long 0x00 8.--12. " SS_MAX ,Maximum counter value for spread spectrum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 0.--4. " SS_VALUE ,Current offset value for spread spectrum modulation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" else group.long 0x10C++0x03 line.long 0x00 "CLK_IMO_SPREAD,IMO Spread Spectrum Configuration" bitfld.long 0x00 30.--31. " SS_MODE ,Spread Spectrum Mode" "Off,TRIANGLE,LFSR,DSI" rbitfld.long 0x00 28.--29. " SS_RANGE ,Spread spectrum range" "M1,M2,M4,?..." bitfld.long 0x00 8.--12. " SS_MAX ,Maximum counter value for spread spectrum" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 0.--4. " SS_VALUE ,Current offset value for spread spectrum modulation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" endif rgroup.long 0x200++0x07 line.long 0x00 "WDT_CTRLOW,Watchdog Counters 0/1" hexmask.long.word 0x00 16.--31. 1. " WDT_CTR1 ,Current value of WDT Counter 1" hexmask.long.word 0x00 0.--15. 1. " WDT_CTR0 ,Current value of WDT Counter 0" line.long 0x04 "WDT_CTRHIGH,Watchdog Counter 2" group.long 0x208++0x0B line.long 0x00 "WDT_MATCH,Watchdog counter match values" hexmask.long.word 0x00 16.--31. 1. " WDT_MATCH1 ,Match value for Watchdog Counter 1" hexmask.long.word 0x00 0.--15. 1. " WDT_MATCH0 ,Match value for Watchdog Counter 0" line.long 0x04 "WDT_CONFIG,Watchdog Counters Configuration" bitfld.long 0x04 30.--31. " LFCLK_SEL ,Select source for LFCLK" "ILO,WCO,?..." bitfld.long 0x04 24.--28. " WDT_BITS2 ,Bit to observe for WDT_INT2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 16. " WDT_MODE2 ,Watchdog Counter 2 Mode" "NOTHING,INT" bitfld.long 0x04 11. " WDT_CASCADE1_2 ,Cascade Watchdog Counters 1,2" "Independent,Cascaded" textline " " bitfld.long 0x04 10. " WDT_CLEAR1 ,Clear Watchdog Counter when WDT_CTR1=WDT_MATCH1" "Free running counter,Clear on match" bitfld.long 0x04 8.--9. " WDT_MODE1 ,Watchdog Counter Action on Match (WDT_CTR1=WDT_MATCH1)" "NOTHING,INT,RESET,INT_THEN_RESET" bitfld.long 0x04 3. " WDT_CASCADE0_1 ,Cascade Watchdog Counters 0,1" "Independent,Cascaded" bitfld.long 0x04 2. " WDT_CLEAR0 ,Clear Watchdog Counter when WDT_CTR0=WDT_MATCH0" "Free running counter,Clear on match" textline " " bitfld.long 0x04 0.--1. " WDT_MODE0 ,Watchdog Counter Action on Match (WDT_CTR0=WDT_MATCH0)" "NOTHING,INT,RESET,INT_THEN_RESET" line.long 0x08 "WDT_CONTROL,Watchdog Counters Control" bitfld.long 0x08 19. " WDT_RESET2 ,Resets counter 2" "No reset,Reset" eventfld.long 0x08 18. " WDT_INT2 ,WDT Interrupt Request" "No interrupt,Interrupt" rbitfld.long 0x08 17. " WDT_ENABLED2 ,Indicates actual state of counter 2" "Disabled,Enabled" bitfld.long 0x08 16. " WDT_ENABLE2 ,Enable Counter 2" "Disabled,Enabled" textline " " bitfld.long 0x08 11. " WDT_RESET1 ,Resets counter 1" "No reset,Reset" eventfld.long 0x08 10. " WDT_INT1 ,WDT Interrupt Request" "No interrupt,Interrupt" rbitfld.long 0x08 9. " WDT_ENABLED1 ,Indicates actual state of counter 1" "Disabled,Enabled" bitfld.long 0x08 8. " WDT_ENABLE1 ,Enable Counter 1" "Disabled,Enabled" textline " " bitfld.long 0x08 3. " WDT_RESET0 ,Resets counter 0" "No reset,Reset" eventfld.long 0x08 2. " WDT_INT0 ,WDT Interrupt Request" "No interrupt,Interrupt" rbitfld.long 0x08 1. " WDT_ENABLED0 ,Indicates actual state of counter 0" "Disabled,Enabled" bitfld.long 0x08 0. " WDT_ENABLE0 ,Enable Counter 0" "Disabled,Enabled" group.long 0x300++0x03 line.long 0x00 "RES_CAUSE,Reset Cause Observation Registe" eventfld.long 0x00 7. " RESET_XRES ,RESET_XRES bit" "No reset,Reset" eventfld.long 0x00 6. " RESET_PBOD ,RESET_PBOD bit" "No reset,Reset" eventfld.long 0x00 5. " RESET_HVBOD ,RESET_HVBOD bit" "No reset,Reset" eventfld.long 0x00 4. " RESET_SOFT ,Cortex-M0 requested a system reset through it's SYSRESETREQ" "No reset,Reset" textline " " eventfld.long 0x00 3. " RESET_PROT_FAULT ,A protection violation occurred that requires a RESET" "No reset,Reset" eventfld.long 0x00 2. " RESET_LOCKUP ,Cortex-M0 LOCKUP is no longer a reset source" "No reset,Reset" eventfld.long 0x00 1. " RESET_DSBOD ,RESET_DSBOD bit" "No reset,Reset" eventfld.long 0x00 0. " RESET_WDT ,A WatchDog Timer reset has occurred since last power cycle" "No reset,Reset" group.long 0xFF18++0x17 line.long 0x00 "PWR_BG_TRIM3,Bandgap Trim Register" bitfld.long 0x00 3.--6. " INL_CROSS_IMO ,IMO Irefgen INL cross-over point control for centering curve at 30C" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--2. " INL_TRIM_IMO ,IMO Irefgen nonlinear current trim for curvature correction" "0,1,2,3,4,5,6,7" line.long 0x04 "PWR_BG_TRIM4,Bandgap Trim Register" bitfld.long 0x04 0.--5. " ABS_TRIM_IMO ,IMO-irefgen output current magnitude trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "PWR_BG_TRIM5,Bandgap Trim Register" bitfld.long 0x08 0.--5. " TMPCO_TRIM_IMO ,IMO-irefgen output current temperature co-efficient trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "CLK_ILO_TRIM,ILO Trim Register" bitfld.long 0x0C 7. " COARSE_TRIM_BIT3 ,Adjusts the bias in the event of high current after fab bit 3" "Normal Mode,Low Current Mode" bitfld.long 0x0C 6. " COARSE_TRIM_BIT2 ,Adjusts the bias in the event of high current after fab bit 2" "Normal Mode,Short R/4" bitfld.long 0x0C 5. " COARSE_TRIM_BIT1 ,Adjusts the bias in the event of high current after fab bit 1" "Unshort R/2,Short R/2" bitfld.long 0x0C 4. " COARSE_TRIM_BIT0 ,Adjusts the bias in the event of high current after fab bit 0" "Unshort R/4,Short 3R/4" textline " " bitfld.long 0x0C 0.--3. " TRIM ,Trim bits to control frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "CLK_IMO_TRIM1,IMO Trim Register" hexmask.long.byte 0x10 0.--7. 1. " OFFSET ,Frequency trim bits" line.long 0x14 "CLK_IMO_TRIM2,IMO Trim Register" bitfld.long 0x14 0.--5. " FREQ ,Frequency to be selected" ",,,,3MHz,4MHz,5MHz,6MHz,7MHz,8MHz,9MHz,10MHz,11MHz,12MHz,,13MHz,14MHz,15MHz,16MHz,17MHz,18MHz,19MHz,20MHz,21MHz,22MHz,23MHz,24MHz,,25MHz,26MHz,27MHz,28MHz,29MHz,30MHz,31MHz,32MHz,33MHz,,34MHz,35MHz,36MHz,37MHz,38MHz,39MHz,40MHz,,,41MHz,42MHz,43MHz,44MHz,45MHz,46MHz,47MHz,48MHz,?..." group.long 0xFF34++0x03 line.long 0x00 "CLK_IMO_TRIM4,IMO Trim Register" bitfld.long 0x00 5.--7. " FSOFFSET ,Fine Scale offset" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--4. " GAIN ,Gain for IMO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" width 0x0B tree.end tree "SRSS External Clock registers" base ad:0x400C0008 width 17. group.long 0x00++0x07 line.long 0x00 "CLK_ECO_CONFIG,ECO Configuration Register" bitfld.long 0x00 31. " ENABLE ,Master enable for ECO oscillator" "Disabled,Enabled" bitfld.long 0x00 1. " AGC_EN ,Automatic Gain Control (AGC) enable" "Disabled,Enabled" bitfld.long 0x00 0. " CLK_EN ,Clock Enable" "Disabled,Enabled" line.long 0x04 "CLK_ECO_STATUS,ECO Status Register" rbitfld.long 0x04 0. " WATCHDOG_ERROR , Watchdog error condition" "No error,Error" if (((per.l(ad:0x400C0008+0x0C))&0x30000)==0x30000) group.long 0x0C++0x03 line.long 0x00 "CLK_PLL0_CONFIG,PLL #0 Configuration Register" bitfld.long 0x00 31. " ENABLE ,Master enable for PLL power gate" "Off,On" rbitfld.long 0x00 30. " ISOLATE_N ,Isolation control of PLL outputs" "Isolated,Not isolated" bitfld.long 0x00 20.--21. " BYPASS_SEL ,Source of the system PLL0 clock" "AUTO,AUTO1,PLL_REF,PLL_OUT" rbitfld.long 0x00 16.--18. " ICP_SEL ,Programmable charge pump current" "0uA,1uA,2uA,3uA,4uA,5uA,6uA,7uA" textline " " rbitfld.long 0x00 14.--15. " OUTPUT_DIV ,Control bits for Output divider" "PASS,DIV2,DIV4,DIV8" rbitfld.long 0x00 8.--13. " REFERENCE_DIV ,Control bits for reference divider" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" hexmask.long.byte 0x00 0.--7. 1. " FEEDBACK_DIV ,Control bits for feedback divider" else group.long 0x0C++0x03 line.long 0x00 "CLK_PLL0_CONFIG,PLL #0 Configuration Register" bitfld.long 0x00 31. " ENABLE ,Master enable for PLL power gate" "Off,On" bitfld.long 0x00 30. " ISOLATE_N ,Isolation control of PLL outputs" "Isolated,Not isolated" bitfld.long 0x00 20.--21. " BYPASS_SEL ,Source of the system PLL0 clock" "AUTO,AUTO1,PLL_REF,PLL_OUT" bitfld.long 0x00 16.--18. " ICP_SEL ,Programmable charge pump current" "0uA,1uA,2uA,3uA,4uA,5uA,6uA,7uA" textline " " bitfld.long 0x00 14.--15. " OUTPUT_DIV ,Control bits for Output divider" "PASS,DIV2,DIV4,DIV8" bitfld.long 0x00 8.--13. " REFERENCE_DIV ,Control bits for reference divider" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" hexmask.long.byte 0x00 0.--7. 1. " FEEDBACK_DIV ,Control bits for feedback divider" endif group.long 0x10++0x07 line.long 0x00 "CLK_PLL0_STATUS,PLL #0 Status Register" rbitfld.long 0x00 0. " LOCKED ,PLL Lock Indicator" "Not locked,Locked" line.long 0x04 "CLK_PLL0_TEST,PLL #0 Test Register" eventfld.long 0x04 4. " UNLOCK_OCCURRED ,Diagnostic bit used for char and validation" "Not occurred,Occurred" bitfld.long 0x04 3. " FAST_LOCK_EN ,Fast Lock Enable" "Disabled,Enabled" bitfld.long 0x04 0.--2. " TEST_MODE ,Test Mode" "NORMAL,TEST_VC_LKG,TEST_CP_DN,TEST_CP_UP,USER_EXT_FL,TEST_CTR_PQ,TEST_LD_DLY,TEST_CTR_ALT" if (((per.l(ad:0x400C0008+0x18))&0x30000)==0x30000) group.long 0x18++0x0B line.long 0x00 "CLK_PLL1_CONFIG,PLL #1 Configuration Register" bitfld.long 0x00 31. " ENABLE ,Master enable for PLL power gate" "Off,On" rbitfld.long 0x00 30. " ISOLATE_N ,Isolation control of PLL outputs" "Isolated,Not isolated" bitfld.long 0x00 20.--21. " BYPASS_SEL ,Source of the system PLL1 clock" "AUTO,AUTO1,PLL_REF,PLL_OUT" rbitfld.long 0x00 16.--18. " ICP_SEL ,Programmable charge pump current" "0uA,1uA,2uA,3uA,4uA,5uA,6uA,7uA" textline " " rbitfld.long 0x00 14.--15. " OUTPUT_DIV ,Control bits for Output divider" "PASS,DIV2,DIV4,DIV8" rbitfld.long 0x00 8.--13. " REFERENCE_DIV ,Control bits for reference divider" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" hexmask.long.byte 0x00 0.--7. 1. " FEEDBACK_DIV ,Control bits for feedback divider" else group.long 0x18++0x0B line.long 0x00 "CLK_PLL1_CONFIG,PLL #1 Configuration Register" bitfld.long 0x00 31. " ENABLE ,Master enable for PLL power gate" "Off,On" bitfld.long 0x00 30. " ISOLATE_N ,Isolation control of PLL outputs" "Isolated,Not isolated" bitfld.long 0x00 20.--21. " BYPASS_SEL ,Source of the system PLL1 clock" "AUTO,AUTO1,PLL_REF,PLL_OUT" bitfld.long 0x00 16.--18. " ICP_SEL ,Programmable charge pump current" "0uA,1uA,2uA,3uA,4uA,5uA,6uA,7uA" textline " " bitfld.long 0x00 14.--15. " OUTPUT_DIV ,Control bits for Output divider" "PASS,DIV2,DIV4,DIV8" bitfld.long 0x00 8.--13. " REFERENCE_DIV ,Control bits for reference divider" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" hexmask.long.byte 0x00 0.--7. 1. " FEEDBACK_DIV ,Control bits for feedback divider" endif rgroup.long 0x1C++0x03 line.long 0x00 "CLK_PLL1_STATUS,PLL #1 Status Register" rbitfld.long 0x00 0. " LOCKED ,PLL Lock Indicator" "Not locked,Locked" group.long 0x20++0x03 line.long 0x00 "CLK_PLL1_TEST,PLL #1 Test Register" eventfld.long 0x00 4. " UNLOCK_OCCURRED ,Diagnostic bit used for char and validation" "Not occurred,Occurred" bitfld.long 0x00 3. " FAST_LOCK_EN ,Fast Lock Enable" "Disabled,Enabled" bitfld.long 0x00 0.--2. " TEST_MODE ,Test Mode" "NORMAL,TEST_VC_LKG,TEST_CP_DN,TEST_CP_UP,USER_EXT_FL,TEST_CTR_PQ,TEST_LD_DLY,TEST_CTR_ALT" group.long 0x48++0x03 line.long 0x00 "CLK_OSCINTF_CTL,Oscillator Interface Control" bitfld.long 0x00 0. " PORT_SEL ,Oscillator Interface Port Select" "USB,WCO" group.long 0xFEFC++0x07 line.long 0x00 "CLK_PLL0_TRIM,PLL #0 Trim Register" bitfld.long 0x00 4.--5. " LOCK_DELAY ,Selects the number of PLL phase frequency detector cycles that the phase error must be in range before declaring lock" "16,32,48,64" bitfld.long 0x00 2.--3. " LOCK_WINDOW ,Selects the allowed phase error before declaring the PLL Unlocked" "25NS,50NS,75NS,100NS" bitfld.long 0x00 0.--1. " VCO_GAIN ,Programmable VCO frequency characteristic at high freq" "0,1,2,3" line.long 0x04 "CLK_PLL1_TRIM,PLL #1 Trim Register" bitfld.long 0x04 4.--5. " LOCK_DELAY ,Selects the number of PLL phase frequency detector cycles that the phase error must be in range before declaring lock" "16,32,48,64" bitfld.long 0x04 2.--3. " LOCK_WINDOW ,Selects the allowed phase error before declaring the PLL Unlocked" "25NS,50NS,75NS,100NS" bitfld.long 0x04 0.--1. " VCO_GAIN ,Programmable VCO frequency characteristic at high freq" "0,1,2,3" if (((per.l(ad:0x400C0008))&0x02)==0x02) group.long 0xFF04++0x03 line.long 0x00 "CLK_ECO_TRIM0,ECO Trim0 Register" bitfld.long 0x00 2.--4. " ATRIM ,Amplitude trim to set the crystal drive level" "0.3Vpp,0.4Vpp,0.5Vpp,0.6Vpp,0.7Vpp,0.8Vpp,0.9Vpp,1Vpp" bitfld.long 0x00 0.--1. " WDTRIM ,Watch Dog Trim" "0.05V,0.1V,0.15V,0.2V" else group.long 0xFF04++0x03 line.long 0x00 "CLK_ECO_TRIM0,ECO Trim0 Register" rbitfld.long 0x00 2.--4. " ATRIM ,Amplitude trim to set the crystal drive level" "0.3Vpp,0.4Vpp,0.5Vpp,0.6Vpp,0.7Vpp,0.8Vpp,0.9Vpp,1Vpp" bitfld.long 0x00 0.--1. " WDTRIM ,Watch Dog Trim" "0.05V,0.1V,0.15V,0.2V" endif group.long 0xFF08++0x03 line.long 0x00 "CLK_ECO_TRIM1,ECO Trim1 Register" bitfld.long 0x00 4.--5. " GTRIM ,Gain Trim - Startup time" "0,1,2,3" bitfld.long 0x00 2.--3. " RTRIM ,Feedback resistor Trim" "0,1,2,3" bitfld.long 0x00 0.--1. " FTRIM ,Filter Trim - 3rd harmonic oscillation" "0,1,2,3" width 0x0B tree.end tree "SRSS Peripheral Clock registers" base ad:0x40010000 width 20. group.long 0x00++0x03 line.long 0x00 "PERI_DIV_CMD,Divider command register" bitfld.long 0x00 31. " ENABLE ,Clock divider enable command" "Disabled,Enabled" bitfld.long 0x00 30. " DISABLE ,Clock divider disable command" "Disabled,Enabled" bitfld.long 0x00 14.--15. " PA_SEL_TYPE ,Divider type of the divider to which phase alignment is performed" "8,16,16.5,24.5" bitfld.long 0x00 8.--13. " PA_SEL_DIV ,Phase alignment for clock enable command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" textline " " bitfld.long 0x00 6.--7. " SEL_TYPE ,Divider type of the divider on which the command is performed" "8,16,16.5,24.5" bitfld.long 0x00 0.--5. " SEL_DIV ,Divider on which the command is per-formed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x100++0x03 line.long 0x00 "PERI_PCLK_CTL0,Programmable clock control register 0" bitfld.long 0x00 6.--7. " SEL_TYPE ,Divider type" "8,16,16.5,24.5" bitfld.long 0x00 0.--3. " SEL_DIV ,One of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x104++0x03 line.long 0x00 "PERI_PCLK_CTL1,Programmable clock control register 1" bitfld.long 0x00 6.--7. " SEL_TYPE ,Divider type" "8,16,16.5,24.5" bitfld.long 0x00 0.--3. " SEL_DIV ,One of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x108++0x03 line.long 0x00 "PERI_PCLK_CTL2,Programmable clock control register 2" bitfld.long 0x00 6.--7. " SEL_TYPE ,Divider type" "8,16,16.5,24.5" bitfld.long 0x00 0.--3. " SEL_DIV ,One of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x10C++0x03 line.long 0x00 "PERI_PCLK_CTL3,Programmable clock control register 3" bitfld.long 0x00 6.--7. " SEL_TYPE ,Divider type" "8,16,16.5,24.5" bitfld.long 0x00 0.--3. " SEL_DIV ,One of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x110++0x03 line.long 0x00 "PERI_PCLK_CTL4,Programmable clock control register 4" bitfld.long 0x00 6.--7. " SEL_TYPE ,Divider type" "8,16,16.5,24.5" bitfld.long 0x00 0.--3. " SEL_DIV ,One of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x114++0x03 line.long 0x00 "PERI_PCLK_CTL5,Programmable clock control register 5" bitfld.long 0x00 6.--7. " SEL_TYPE ,Divider type" "8,16,16.5,24.5" bitfld.long 0x00 0.--3. " SEL_DIV ,One of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x118++0x03 line.long 0x00 "PERI_PCLK_CTL6,Programmable clock control register 6" bitfld.long 0x00 6.--7. " SEL_TYPE ,Divider type" "8,16,16.5,24.5" bitfld.long 0x00 0.--3. " SEL_DIV ,One of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x11C++0x03 line.long 0x00 "PERI_PCLK_CTL7,Programmable clock control register 7" bitfld.long 0x00 6.--7. " SEL_TYPE ,Divider type" "8,16,16.5,24.5" bitfld.long 0x00 0.--3. " SEL_DIV ,One of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x120++0x03 line.long 0x00 "PERI_PCLK_CTL8,Programmable clock control register 8" bitfld.long 0x00 6.--7. " SEL_TYPE ,Divider type" "8,16,16.5,24.5" bitfld.long 0x00 0.--3. " SEL_DIV ,One of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x124++0x03 line.long 0x00 "PERI_PCLK_CTL9,Programmable clock control register 9" bitfld.long 0x00 6.--7. " SEL_TYPE ,Divider type" "8,16,16.5,24.5" bitfld.long 0x00 0.--3. " SEL_DIV ,One of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x128++0x03 line.long 0x00 "PERI_PCLK_CTL10,Programmable clock control register 10" bitfld.long 0x00 6.--7. " SEL_TYPE ,Divider type" "8,16,16.5,24.5" bitfld.long 0x00 0.--3. " SEL_DIV ,One of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x12C++0x03 line.long 0x00 "PERI_PCLK_CTL11,Programmable clock control register 11" bitfld.long 0x00 6.--7. " SEL_TYPE ,Divider type" "8,16,16.5,24.5" bitfld.long 0x00 0.--3. " SEL_DIV ,One of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x130++0x03 line.long 0x00 "PERI_PCLK_CTL12,Programmable clock control register 12" bitfld.long 0x00 6.--7. " SEL_TYPE ,Divider type" "8,16,16.5,24.5" bitfld.long 0x00 0.--3. " SEL_DIV ,One of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x134++0x03 line.long 0x00 "PERI_PCLK_CTL13,Programmable clock control register 13" bitfld.long 0x00 6.--7. " SEL_TYPE ,Divider type" "8,16,16.5,24.5" bitfld.long 0x00 0.--3. " SEL_DIV ,One of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x138++0x03 line.long 0x00 "PERI_PCLK_CTL14,Programmable clock control register 14" bitfld.long 0x00 6.--7. " SEL_TYPE ,Divider type" "8,16,16.5,24.5" bitfld.long 0x00 0.--3. " SEL_DIV ,One of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x13C++0x03 line.long 0x00 "PERI_PCLK_CTL15,Programmable clock control register 15" bitfld.long 0x00 6.--7. " SEL_TYPE ,Divider type" "8,16,16.5,24.5" bitfld.long 0x00 0.--3. " SEL_DIV ,One of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x140++0x03 line.long 0x00 "PERI_PCLK_CTL16,Programmable clock control register 16" bitfld.long 0x00 6.--7. " SEL_TYPE ,Divider type" "8,16,16.5,24.5" bitfld.long 0x00 0.--3. " SEL_DIV ,One of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x144++0x03 line.long 0x00 "PERI_PCLK_CTL17,Programmable clock control register 17" bitfld.long 0x00 6.--7. " SEL_TYPE ,Divider type" "8,16,16.5,24.5" bitfld.long 0x00 0.--3. " SEL_DIV ,One of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x148++0x03 line.long 0x00 "PERI_PCLK_CTL18,Programmable clock control register 18" bitfld.long 0x00 6.--7. " SEL_TYPE ,Divider type" "8,16,16.5,24.5" bitfld.long 0x00 0.--3. " SEL_DIV ,One of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x14C++0x03 line.long 0x00 "PERI_PCLK_CTL19,Programmable clock control register 19" bitfld.long 0x00 6.--7. " SEL_TYPE ,Divider type" "8,16,16.5,24.5" bitfld.long 0x00 0.--3. " SEL_DIV ,One of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x150++0x03 line.long 0x00 "PERI_PCLK_CTL20,Programmable clock control register 20" bitfld.long 0x00 6.--7. " SEL_TYPE ,Divider type" "8,16,16.5,24.5" bitfld.long 0x00 0.--3. " SEL_DIV ,One of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x154++0x03 line.long 0x00 "PERI_PCLK_CTL21,Programmable clock control register 21" bitfld.long 0x00 6.--7. " SEL_TYPE ,Divider type" "8,16,16.5,24.5" bitfld.long 0x00 0.--3. " SEL_DIV ,One of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x158++0x03 line.long 0x00 "PERI_PCLK_CTL22,Programmable clock control register 22" bitfld.long 0x00 6.--7. " SEL_TYPE ,Divider type" "8,16,16.5,24.5" bitfld.long 0x00 0.--3. " SEL_DIV ,One of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x15C++0x03 line.long 0x00 "PERI_PCLK_CTL23,Programmable clock control register 23" bitfld.long 0x00 6.--7. " SEL_TYPE ,Divider type" "8,16,16.5,24.5" bitfld.long 0x00 0.--3. " SEL_DIV ,One of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x160++0x03 line.long 0x00 "PERI_PCLK_CTL24,Programmable clock control register 24" bitfld.long 0x00 6.--7. " SEL_TYPE ,Divider type" "8,16,16.5,24.5" bitfld.long 0x00 0.--3. " SEL_DIV ,One of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x300++0x03 line.long 0x00 "PERI_DIV_16_CTL0,Divider control register (for 16.0 divider) 0" hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,Integer division by (1+INT16_DIV)" rbitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled" group.long 0x304++0x03 line.long 0x00 "PERI_DIV_16_CTL1,Divider control register (for 16.0 divider) 1" hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,Integer division by (1+INT16_DIV)" rbitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled" group.long 0x308++0x03 line.long 0x00 "PERI_DIV_16_CTL2,Divider control register (for 16.0 divider) 2" hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,Integer division by (1+INT16_DIV)" rbitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled" group.long 0x30C++0x03 line.long 0x00 "PERI_DIV_16_CTL3,Divider control register (for 16.0 divider) 3" hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,Integer division by (1+INT16_DIV)" rbitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled" group.long 0x310++0x03 line.long 0x00 "PERI_DIV_16_CTL4,Divider control register (for 16.0 divider) 4" hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,Integer division by (1+INT16_DIV)" rbitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled" group.long 0x314++0x03 line.long 0x00 "PERI_DIV_16_CTL5,Divider control register (for 16.0 divider) 5" hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,Integer division by (1+INT16_DIV)" rbitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled" group.long 0x318++0x03 line.long 0x00 "PERI_DIV_16_CTL6,Divider control register (for 16.0 divider) 6" hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,Integer division by (1+INT16_DIV)" rbitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled" group.long 0x31C++0x03 line.long 0x00 "PERI_DIV_16_CTL7,Divider control register (for 16.0 divider) 7" hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,Integer division by (1+INT16_DIV)" rbitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled" group.long 0x320++0x03 line.long 0x00 "PERI_DIV_16_CTL8,Divider control register (for 16.0 divider) 8" hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,Integer division by (1+INT16_DIV)" rbitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled" group.long 0x324++0x03 line.long 0x00 "PERI_DIV_16_CTL9,Divider control register (for 16.0 divider) 9" hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,Integer division by (1+INT16_DIV)" rbitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled" group.long 0x328++0x03 line.long 0x00 "PERI_DIV_16_CTL10,Divider control register (for 16.0 divider) 10" hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,Integer division by (1+INT16_DIV)" rbitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled" group.long 0x32C++0x03 line.long 0x00 "PERI_DIV_16_CTL11,Divider control register (for 16.0 divider) 11" hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,Integer division by (1+INT16_DIV)" rbitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled" group.long 0x330++0x03 line.long 0x00 "PERI_DIV_16_CTL12,Divider control register (for 16.0 divider) 12" hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,Integer division by (1+INT16_DIV)" rbitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled" group.long 0x334++0x03 line.long 0x00 "PERI_DIV_16_CTL13,Divider control register (for 16.0 divider) 13" hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,Integer division by (1+INT16_DIV)" rbitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled" group.long 0x338++0x03 line.long 0x00 "PERI_DIV_16_CTL14,Divider control register (for 16.0 divider) 14" hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,Integer division by (1+INT16_DIV)" rbitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled" group.long 0x400++0x03 line.long 0x00 "PERI_DIV_16_5_CTL0,Divider control register (for 16.5 divider) 0" hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,Integer division by (1+INT16_DIV)" bitfld.long 0x00 3.--7. " FRAC5_DIV ,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled" group.long 0x404++0x03 line.long 0x00 "PERI_DIV_16_5_CTL1,Divider control register (for 16.5 divider) 1" hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,Integer division by (1+INT16_DIV)" bitfld.long 0x00 3.--7. " FRAC5_DIV ,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled" group.long 0x408++0x03 line.long 0x00 "PERI_DIV_16_5_CTL2,Divider control register (for 16.5 divider) 2" hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,Integer division by (1+INT16_DIV)" bitfld.long 0x00 3.--7. " FRAC5_DIV ,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled" group.long 0x40C++0x03 line.long 0x00 "PERI_DIV_16_5_CTL3,Divider control register (for 16.5 divider) 3" hexmask.long.word 0x00 8.--23. 1. " INT16_DIV ,Integer division by (1+INT16_DIV)" bitfld.long 0x00 3.--7. " FRAC5_DIV ,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled" group.long 0x500++0x03 line.long 0x00 "PERI_DIV_24_5_CTL,Divider control register for 24.5 divider" hexmask.long.tbyte 0x00 8.--31. 1. " INT24_DIV ,Integer division by 1+INT24_DIV" bitfld.long 0x00 3.--7. " FRAC5_DIV ,Fractional division by FRAC5_DIV/32" rbitfld.long 0x00 0. " EN ,Divider enabled" "Disabled,Enabled" group.long 0x600++0x03 line.long 0x00 "PERI_TR_CTL,Trigger control register" bitfld.long 0x00 31. " TR_ACT ,Trigger activation" "Not activated,Activated" bitfld.long 0x00 30. " TR_OUT ,Specifies whether trigger activation is for a specific input or ouput trigger of the trigger multiplex-er" "Input,Output" hexmask.long.byte 0x00 16.--23. 1. " TR_COUNT ,Amount of cycles a specific trigger is activated" bitfld.long 0x00 8.--11. " TR_GROUP ,Trigger group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x00 0.--6. 1. " TR_SEL ,Specifies the activated trigger when TR_ACT is 1" width 0x0B tree.end tree "SRSS Watch Crystal Oscillator registers" base ad:0x40220000 width 12. if (((per.l(ad:0x40220000))&0x01)==0x01) group.long 0x00++0x03 line.long 0x00 "WCO_CONFIG,WCO Configuration Register" bitfld.long 0x00 31. " IP_ENABLE ,Master enable for IP" "Disabled,Enabled" bitfld.long 0x00 30. " DPLL_ENABLE ,Enable DPLL operation" "Disabled,Enabled" bitfld.long 0x00 22. " ENBUS[6] ,Beta multipliers enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " [3] ,Load resistor control" "0,1" bitfld.long 0x00 18. " [2] ,Load resistor control" "0,1" bitfld.long 0x00 17. " [1] ,Load resistor control" "0,1" bitfld.long 0x00 16. " [0] ,Load resistor control" "0,1" textline " " bitfld.long 0x00 2. " EXT_INPUT_EN ,Disables the load resistor and allows external clock input for pad_xin" "Disabled,Enabled" rbitfld.long 0x00 1. " LPM_AUTO ,Automatically control low power mode" "Disabled,Enabled" bitfld.long 0x00 0. " LPM_EN ,Force block into Low Power Mode" "Disabled,Enabled" else group.long 0x00++0x03 line.long 0x00 "WCO_CONFIG,WCO Configuration Register" bitfld.long 0x00 31. " IP_ENABLE ,Master enable for IP" "Disabled,Enabled" bitfld.long 0x00 30. " DPLL_ENABLE ,Enable DPLL operation" "Disabled,Enabled" bitfld.long 0x00 22. " ENBUS[6] ,Beta multipliers enable" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " [3] ,Load resistor control" "0,1" bitfld.long 0x00 18. " [2] ,Load resistor control" "0,1" bitfld.long 0x00 17. " [1] ,Load resistor control" "0,1" bitfld.long 0x00 16. " [0] ,Load resistor control" "0,1" textline " " bitfld.long 0x00 2. " EXT_INPUT_EN ,Disables the load resistor and allows external clock input for pad_xin" "Disabled,Enabled" bitfld.long 0x00 1. " LPM_AUTO ,Automatically control low power mode" "Disabled,Enabled" bitfld.long 0x00 0. " LPM_EN ,Force block into Low Power Mode" "Disabled,Enabled" endif group.long 0x04++0x07 line.long 0x00 "WCO_STATUS,WCO Status Register" rbitfld.long 0x00 0. " OUT_BLNK_A ,Indicates that output has transitioned" "0,1" line.long 0x04 "WCO_DPLL,WCO DPLL Register" hexmask.long.byte 0x04 22.--29. 1. " DPLL_LF_LIMIT ,Maximum IMO offset allowed" bitfld.long 0x04 19.--21. " DPLL_LF_PGAIN ,DPLL Loop Filter Proportional Gain Setting" "1/16,1/8,1/4,1/2,1,2,4,8" bitfld.long 0x04 16.--18. " DPLL_LF_IGAIN ,DPLL Loop Filter Integral Gain Setting" "1/16,1/8,1/4,1/2,1,2,4,8" hexmask.long.word 0x04 0.--10. 1. " DPLL_MULT ,Multiplier to determine IMO frequency in multiples of the WCO frequency" if (((per.l(ad:0x40220000))&0x02)==0x02) group.long 0xF00++0x03 line.long 0x00 "WCO_TRIM,WCO Trim Register" bitfld.long 0x00 12.--13. " LPM_GM_FOR_LPM_AUTO ,GM setting for LPM" "0,1,2,3" bitfld.long 0x00 8.--10. " XGM_FOR_LPM_AUTO ,Amplifier GM setting" "3370 nA,2620 nA,2250 nA,1500 nA,1870 nA,1120 nA,750 nA,0 nA" bitfld.long 0x00 4.--5. " LPM_GM ,GM setting for LPM" "0,1,2,3" bitfld.long 0x00 0.--2. " XGM ,Amplifier GM setting" "3370 nA,2620 nA,2250 nA,1500 nA,1870 nA,1120 nA,750 nA,0 nA" else group.long 0xF00++0x03 line.long 0x00 "WCO_TRIM,WCO Trim Register" rbitfld.long 0x00 12.--13. " LPM_GM_FOR_LPM_AUTO ,GM setting for LPM" "0,1,2,3" rbitfld.long 0x00 8.--10. " XGM_FOR_LPM_AUTO ,Amplifier GM setting" "3370 nA,2620 nA,2250 nA,1500 nA,1870 nA,1120 nA,750 nA,0 nA" bitfld.long 0x00 4.--5. " LPM_GM ,GM setting for LPM" "0,1,2,3" bitfld.long 0x00 0.--2. " XGM ,Amplifier GM setting" "3370 nA,2620 nA,2250 nA,1500 nA,1870 nA,1120 nA,750 nA,0 nA" endif width 0x0B tree.end tree "TCPWM Control and Status registers" base ad:0x40200000 width 18. group.long 0x00++0x03 line.long 0x00 "TCPWM_CTRL,TCPWM Control Register 0" bitfld.long 0x00 7. " COUNTER_ENABLED[7] ,Counter 7 enable" "Disabled,Enabled" bitfld.long 0x00 6. " [6] ,Counter 6 enable" "Disabled,Enabled" bitfld.long 0x00 5. " [5] ,Counter 5 enable" "Disabled,Enabled" bitfld.long 0x00 4. " [4] ,Counter 4 enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " [3] ,Counter 3 enable" "Disabled,Enabled" bitfld.long 0x00 2. " [2] ,Counter 2 enable" "Disabled,Enabled" bitfld.long 0x00 1. " [1] ,Counter 1 enable" "Disabled,Enabled" bitfld.long 0x00 0. " [0] ,Counter 0 enable" "Disabled,Enabled" group.long 0x08++0x03 line.long 0x00 "TCPWM_CMD,TCPWM Command Register" bitfld.long 0x00 31. " COUNTER_START[7] ,Counter 7 start trigger" "No effect,Started" bitfld.long 0x00 30. " [6] ,Counter 6 start trigger" "No effect,Started" bitfld.long 0x00 29. " [5] ,Counter 5 start trigger" "No effect,Started" bitfld.long 0x00 28. " [4] ,Counter 4 start trigger" "No effect,Started" textline " " bitfld.long 0x00 27. " [3] ,Counter 3 start trigger" "No effect,Started" bitfld.long 0x00 26. " [2] ,Counter 2 start trigger" "No effect,Started" bitfld.long 0x00 25. " [1] ,Counter 1 start trigger" "No effect,Started" bitfld.long 0x00 24. " [0] ,Counter 0 start trigger" "No effect,Started" textline " " bitfld.long 0x00 23. " COUNTER_STOP[7] ,Counter 7 stop trigger" "No effect,Stopped" bitfld.long 0x00 22. " [6] ,Counter 6 stop trigger" "No effect,Stopped" bitfld.long 0x00 21. " [5] ,Counter 5 stop trigger" "No effect,Stopped" bitfld.long 0x00 20. " [4] ,Counter 4 stop trigger" "No effect,Stopped" textline " " bitfld.long 0x00 19. " [3] ,Counter 3 stop trigger" "No effect,Stopped" bitfld.long 0x00 18. " [2] ,Counter 2 stop trigger" "No effect,Stopped" bitfld.long 0x00 17. " [1] ,Counter 1 stop trigger" "No effect,Stopped" bitfld.long 0x00 16. " [0] ,Counter 0 stop trigger" "No effect,Stopped" textline " " bitfld.long 0x00 15. " COUNTER_RELOAD[7] ,Counter 7 reload trigger" "No effect,Reloaded" bitfld.long 0x00 14. " [6] ,Counter 6 reload trigger" "No effect,Reloaded" bitfld.long 0x00 13. " [5] ,Counter 5 reload trigger" "No effect,Reloaded" bitfld.long 0x00 12. " [4] ,Counter 4 reload trigger" "No effect,Reloaded" textline " " bitfld.long 0x00 11. " [3] ,Counter 3 reload trigger" "No effect,Reloaded" bitfld.long 0x00 10. " [2] ,Counter 2 reload trigger" "No effect,Reloaded" bitfld.long 0x00 9. " [1] ,Counter 1 reload trigger" "No effect,Reloaded" bitfld.long 0x00 8. " [0] ,Counter 0 reload trigger" "No effect,Reloaded" textline " " bitfld.long 0x00 7. " COUNTER_CAPTURE[7] ,Counter 7 capture trigger" "No effect,Captured" bitfld.long 0x00 6. " [6] ,Counter 6 capture trigger" "No effect,Captured" bitfld.long 0x00 5. " [5] ,Counter 5 capture trigger" "No effect,Captured" bitfld.long 0x00 4. " [4] ,Counter 4 capture trigger" "No effect,Captured" textline " " bitfld.long 0x00 3. " [3] ,Counter 3 capture trigger" "No effect,Captured" bitfld.long 0x00 2. " [2] ,Counter 2 capture trigger" "No effect,Captured" bitfld.long 0x00 1. " [1] ,Counter 1 capture trigger" "No effect,Captured" bitfld.long 0x00 0. " [0] ,Counter 0 capture trigger" "No effect,Captured" rgroup.long 0x0C++0x03 line.long 0x00 "TCPWM_INTR_CAUSE,TCPWM Counter Interrupt Cause Register" bitfld.long 0x00 7. " COUNTER_INT[7] ,Counter 7 interrupt signal active" "Not active,Active" bitfld.long 0x00 6. " [6] ,Counter 6 interrupt signal active" "Not active,Active" bitfld.long 0x00 5. " [5] ,Counter 5 interrupt signal active" "Not active,Active" bitfld.long 0x00 4. " [4] ,Counter 4 interrupt signal active" "Not active,Active" textline " " bitfld.long 0x00 3. " [3] ,Counter 3 interrupt signal active" "Not active,Active" bitfld.long 0x00 2. " [2] ,Counter 2 interrupt signal active" "Not active,Active" bitfld.long 0x00 1. " [1] ,Counter 1 interrupt signal active" "Not active,Active" bitfld.long 0x00 0. " [0] ,Counter 0 interrupt signal active" "Not active,Active" width 0x0B tree.end tree "TCPWM Counter registers" tree "TCPWM_CNT0" base ad:0x40200100 width 13. if (((per.l(ad:0x40200100))&0x7000000)==0x3000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Counter Control Register" bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..." bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature encoding mode" "X1,X2,X4,?..." bitfld.long 0x00 18. " ONE_SHOT ,Counter ONE_SHOT" "Continuous,Off" textline " " bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit control field" elif (((per.l(ad:0x40200100))&0x7000000)==(0x4000000||0x5000000)) if (((per.l(ad:0x40200100))&0x08)==0x08) group.long 0x00++0x03 line.long 0x00 "CTRL,Counter Control Register" bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..." bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature encoding mode" ",INV_OUT,INV_COMPL_OUT,?..." bitfld.long 0x00 18. " ONE_SHOT ,Counter ONE_SHOT" "Continuous,Off" textline " " bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit control field" bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,Specifies whether the counter stops on a kill event" "Not stopped,Stopped" textline " " rbitfld.long 0x00 2. " PWM_SYNC_KILL ,Asynchronous/synchronous kill behaviour" "Asynchronous,Synchronous" bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Switching period values" "Not switched,Switched" textline " " bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Switching CC values" "Not switched,Switched_terminal_count" else group.long 0x00++0x03 line.long 0x00 "CTRL,Counter Control Register" bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..." bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature encoding mode" ",INV_OUT,INV_COMPL_OUT,?..." bitfld.long 0x00 18. " ONE_SHOT ,Counter ONE_SHOT" "Continuous,Off" textline " " bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit control field" bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,Specifies whether the counter stops on a kill event" "Not stopped,Stopped" textline " " bitfld.long 0x00 2. " PWM_SYNC_KILL ,Asynchronous/synchronous kill behaviour" "Asynchronous,Synchronous" bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Switching period values" "Not switched,Switched" textline " " bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Switching CC values" "Not switched,Switched_terminal_count" endif elif (((per.l(ad:0x40200100))&0x7000000)==0x6000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Counter Control Register" bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..." bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature encoding mode" ",INV_OUT,INV_COMPL_OUT,?..." bitfld.long 0x00 18. " ONE_SHOT ,Counter ONE_SHOT" "Continuous,Off" textline " " bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit control field" bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,Specifies whether the counter stops on a kill event" "Not stopped,Stopped" textline " " bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Switching period values" "Not switched,Switched" bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Switching CC values" "Not switched,Switched_terminal_count" elif (((per.l(ad:0x40200100))&0x7000000)==0x00) group.long 0x00++0x03 line.long 0x00 "CTRL,Counter Control Register" bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..." bitfld.long 0x00 18. " ONE_SHOT ,Counter ONE_SHOT" "Continuous,Off" bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit control field" textline " " bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Switching CC values" "Not switched,Switched_compare_match" else group.long 0x00++0x03 line.long 0x00 "CTRL,Counter Control Register" bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..." bitfld.long 0x00 18. " ONE_SHOT ,Counter ONE_SHOT" "Continuous,Off" bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit control field" endif textline " " rgroup.long 0x04++0x03 line.long 0x00 "STATUS,Counter Status Register" bitfld.long 0x00 31. " RUNNING ,Counter on/off" "Off,On" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit counter field" bitfld.long 0x00 0. " DOWN ,Counter couting up/down" "Up,Down" group.long 0x08++0x13 line.long 0x00 "COUNTER,Counter Count Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,16-bit counter value" line.long 0x04 "CC,Counter Compare/capture" hexmask.long.word 0x04 0.--15. 1. " CC ,Counter compare/capture value" line.long 0x08 "CC_BUFF,Counter Buffered Compare/capture Register" hexmask.long.word 0x08 0.--15. 1. " CC ,Additional buffer for counter CC register" line.long 0x0C "PERIOD,Counter Period Register" hexmask.long.word 0x0C 0.--15. 1. " PERIOD ,Period value: upper value of the counter" line.long 0x10 "PERIOD_BUFF,Counter Buffered Period Register" hexmask.long.word 0x10 0.--15. 1. " PERIOD ,Additional buffer for counter PERIOD register" group.long 0x20++0x0B line.long 0x00 "TR_CTRL0,Counter Trigger Control Register 0" bitfld.long 0x00 16.--19. " START_SEL ,Input triggers/phi B as a start trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " STOP_SEL ,Triggers as a stop/kill trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " RELOAD_SEL ,Reload trigger/revolution pulse" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " COUNT_SEL ,Count trigger/phi A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " CAPTURE_SEL ,Capture trigger/switch the values[period registers-buffer counterparts]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "TR_CTRL1,Counter Trigger Control Register 1" bitfld.long 0x04 8.--9. " START_EDGE ,Start the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET" bitfld.long 0x04 6.--7. " STOP_EDGE ,Stop the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET" bitfld.long 0x04 4.--5. " RELOAD_EDGE ,Initialize the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET" bitfld.long 0x04 2.--3. " COUNT_EDGE ,Increase or decrease the counter by one" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET" textline " " bitfld.long 0x04 0.--1. " CAPTURE_EDGE ,Copy the counter value into the CC register" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET" line.long 0x08 "TR_CTRL2,Counter Trigger Control Register 2" bitfld.long 0x08 4.--5. " UNDERFLOW_MODE ,Counter underflow Event(Counter=0)" "SET,CLEAR,INVERT,NO_CHANGE" bitfld.long 0x08 2.--3. " OVERFLOW_MODE ,Counter overflow event (Counter=period)" "SET,CLEAR,INVERT,NO_CHANGE" bitfld.long 0x08 0.--1. " CC_MATCH_MODE ,Compare match event" "SET,CLEAR,INVERT,NO_CHANGE" group.long 0x30++0x0F line.long 0x00 "INTR,Interrupt Request Register" eventfld.long 0x00 1. " CC_MATCH ,Counter matches CC register event" "Cleared,Event_detected" eventfld.long 0x00 0. " TC ,Terminal count event" "Cleared,Event_detected" line.long 0x04 "INTR_SET,Interrupt Set Request Register" bitfld.long 0x04 1. " CC_MATCH ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt" bitfld.long 0x04 0. " TC ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt" line.long 0x08 "INTR_MASK,Interrupt Mask Register" bitfld.long 0x08 1. " CC_MATCH ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked" bitfld.long 0x08 0. " TC ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked" line.long 0x0C "INTR_MASKED,Interrupt Masked Request Register" rbitfld.long 0x0C 1. " CC_MATCH ,Logical AND of corresponding request and mask bits" "Not masked,Masked" rbitfld.long 0x0C 0. " TC ,Logical AND of corresponding request and mask bits" "Not masked,Masked" width 0x0B tree.end tree "TCPWM_CNT1" base ad:0x40200140 width 13. if (((per.l(ad:0x40200140))&0x7000000)==0x3000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Counter Control Register" bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..." bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature encoding mode" "X1,X2,X4,?..." bitfld.long 0x00 18. " ONE_SHOT ,Counter ONE_SHOT" "Continuous,Off" textline " " bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit control field" elif (((per.l(ad:0x40200140))&0x7000000)==(0x4000000||0x5000000)) if (((per.l(ad:0x40200140))&0x08)==0x08) group.long 0x00++0x03 line.long 0x00 "CTRL,Counter Control Register" bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..." bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature encoding mode" ",INV_OUT,INV_COMPL_OUT,?..." bitfld.long 0x00 18. " ONE_SHOT ,Counter ONE_SHOT" "Continuous,Off" textline " " bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit control field" bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,Specifies whether the counter stops on a kill event" "Not stopped,Stopped" textline " " rbitfld.long 0x00 2. " PWM_SYNC_KILL ,Asynchronous/synchronous kill behaviour" "Asynchronous,Synchronous" bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Switching period values" "Not switched,Switched" textline " " bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Switching CC values" "Not switched,Switched_terminal_count" else group.long 0x00++0x03 line.long 0x00 "CTRL,Counter Control Register" bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..." bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature encoding mode" ",INV_OUT,INV_COMPL_OUT,?..." bitfld.long 0x00 18. " ONE_SHOT ,Counter ONE_SHOT" "Continuous,Off" textline " " bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit control field" bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,Specifies whether the counter stops on a kill event" "Not stopped,Stopped" textline " " bitfld.long 0x00 2. " PWM_SYNC_KILL ,Asynchronous/synchronous kill behaviour" "Asynchronous,Synchronous" bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Switching period values" "Not switched,Switched" textline " " bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Switching CC values" "Not switched,Switched_terminal_count" endif elif (((per.l(ad:0x40200140))&0x7000000)==0x6000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Counter Control Register" bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..." bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature encoding mode" ",INV_OUT,INV_COMPL_OUT,?..." bitfld.long 0x00 18. " ONE_SHOT ,Counter ONE_SHOT" "Continuous,Off" textline " " bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit control field" bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,Specifies whether the counter stops on a kill event" "Not stopped,Stopped" textline " " bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Switching period values" "Not switched,Switched" bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Switching CC values" "Not switched,Switched_terminal_count" elif (((per.l(ad:0x40200140))&0x7000000)==0x00) group.long 0x00++0x03 line.long 0x00 "CTRL,Counter Control Register" bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..." bitfld.long 0x00 18. " ONE_SHOT ,Counter ONE_SHOT" "Continuous,Off" bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit control field" textline " " bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Switching CC values" "Not switched,Switched_compare_match" else group.long 0x00++0x03 line.long 0x00 "CTRL,Counter Control Register" bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..." bitfld.long 0x00 18. " ONE_SHOT ,Counter ONE_SHOT" "Continuous,Off" bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit control field" endif textline " " rgroup.long 0x04++0x03 line.long 0x00 "STATUS,Counter Status Register" bitfld.long 0x00 31. " RUNNING ,Counter on/off" "Off,On" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit counter field" bitfld.long 0x00 0. " DOWN ,Counter couting up/down" "Up,Down" group.long 0x08++0x13 line.long 0x00 "COUNTER,Counter Count Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,16-bit counter value" line.long 0x04 "CC,Counter Compare/capture" hexmask.long.word 0x04 0.--15. 1. " CC ,Counter compare/capture value" line.long 0x08 "CC_BUFF,Counter Buffered Compare/capture Register" hexmask.long.word 0x08 0.--15. 1. " CC ,Additional buffer for counter CC register" line.long 0x0C "PERIOD,Counter Period Register" hexmask.long.word 0x0C 0.--15. 1. " PERIOD ,Period value: upper value of the counter" line.long 0x10 "PERIOD_BUFF,Counter Buffered Period Register" hexmask.long.word 0x10 0.--15. 1. " PERIOD ,Additional buffer for counter PERIOD register" group.long 0x20++0x0B line.long 0x00 "TR_CTRL0,Counter Trigger Control Register 0" bitfld.long 0x00 16.--19. " START_SEL ,Input triggers/phi B as a start trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " STOP_SEL ,Triggers as a stop/kill trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " RELOAD_SEL ,Reload trigger/revolution pulse" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " COUNT_SEL ,Count trigger/phi A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " CAPTURE_SEL ,Capture trigger/switch the values[period registers-buffer counterparts]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "TR_CTRL1,Counter Trigger Control Register 1" bitfld.long 0x04 8.--9. " START_EDGE ,Start the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET" bitfld.long 0x04 6.--7. " STOP_EDGE ,Stop the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET" bitfld.long 0x04 4.--5. " RELOAD_EDGE ,Initialize the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET" bitfld.long 0x04 2.--3. " COUNT_EDGE ,Increase or decrease the counter by one" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET" textline " " bitfld.long 0x04 0.--1. " CAPTURE_EDGE ,Copy the counter value into the CC register" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET" line.long 0x08 "TR_CTRL2,Counter Trigger Control Register 2" bitfld.long 0x08 4.--5. " UNDERFLOW_MODE ,Counter underflow Event(Counter=0)" "SET,CLEAR,INVERT,NO_CHANGE" bitfld.long 0x08 2.--3. " OVERFLOW_MODE ,Counter overflow event (Counter=period)" "SET,CLEAR,INVERT,NO_CHANGE" bitfld.long 0x08 0.--1. " CC_MATCH_MODE ,Compare match event" "SET,CLEAR,INVERT,NO_CHANGE" group.long 0x30++0x0F line.long 0x00 "INTR,Interrupt Request Register" eventfld.long 0x00 1. " CC_MATCH ,Counter matches CC register event" "Cleared,Event_detected" eventfld.long 0x00 0. " TC ,Terminal count event" "Cleared,Event_detected" line.long 0x04 "INTR_SET,Interrupt Set Request Register" bitfld.long 0x04 1. " CC_MATCH ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt" bitfld.long 0x04 0. " TC ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt" line.long 0x08 "INTR_MASK,Interrupt Mask Register" bitfld.long 0x08 1. " CC_MATCH ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked" bitfld.long 0x08 0. " TC ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked" line.long 0x0C "INTR_MASKED,Interrupt Masked Request Register" rbitfld.long 0x0C 1. " CC_MATCH ,Logical AND of corresponding request and mask bits" "Not masked,Masked" rbitfld.long 0x0C 0. " TC ,Logical AND of corresponding request and mask bits" "Not masked,Masked" width 0x0B tree.end tree "TCPWM_CNT2" base ad:0x40200180 width 13. if (((per.l(ad:0x40200180))&0x7000000)==0x3000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Counter Control Register" bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..." bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature encoding mode" "X1,X2,X4,?..." bitfld.long 0x00 18. " ONE_SHOT ,Counter ONE_SHOT" "Continuous,Off" textline " " bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit control field" elif (((per.l(ad:0x40200180))&0x7000000)==(0x4000000||0x5000000)) if (((per.l(ad:0x40200180))&0x08)==0x08) group.long 0x00++0x03 line.long 0x00 "CTRL,Counter Control Register" bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..." bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature encoding mode" ",INV_OUT,INV_COMPL_OUT,?..." bitfld.long 0x00 18. " ONE_SHOT ,Counter ONE_SHOT" "Continuous,Off" textline " " bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit control field" bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,Specifies whether the counter stops on a kill event" "Not stopped,Stopped" textline " " rbitfld.long 0x00 2. " PWM_SYNC_KILL ,Asynchronous/synchronous kill behaviour" "Asynchronous,Synchronous" bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Switching period values" "Not switched,Switched" textline " " bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Switching CC values" "Not switched,Switched_terminal_count" else group.long 0x00++0x03 line.long 0x00 "CTRL,Counter Control Register" bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..." bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature encoding mode" ",INV_OUT,INV_COMPL_OUT,?..." bitfld.long 0x00 18. " ONE_SHOT ,Counter ONE_SHOT" "Continuous,Off" textline " " bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit control field" bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,Specifies whether the counter stops on a kill event" "Not stopped,Stopped" textline " " bitfld.long 0x00 2. " PWM_SYNC_KILL ,Asynchronous/synchronous kill behaviour" "Asynchronous,Synchronous" bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Switching period values" "Not switched,Switched" textline " " bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Switching CC values" "Not switched,Switched_terminal_count" endif elif (((per.l(ad:0x40200180))&0x7000000)==0x6000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Counter Control Register" bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..." bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature encoding mode" ",INV_OUT,INV_COMPL_OUT,?..." bitfld.long 0x00 18. " ONE_SHOT ,Counter ONE_SHOT" "Continuous,Off" textline " " bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit control field" bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,Specifies whether the counter stops on a kill event" "Not stopped,Stopped" textline " " bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Switching period values" "Not switched,Switched" bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Switching CC values" "Not switched,Switched_terminal_count" elif (((per.l(ad:0x40200180))&0x7000000)==0x00) group.long 0x00++0x03 line.long 0x00 "CTRL,Counter Control Register" bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..." bitfld.long 0x00 18. " ONE_SHOT ,Counter ONE_SHOT" "Continuous,Off" bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit control field" textline " " bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Switching CC values" "Not switched,Switched_compare_match" else group.long 0x00++0x03 line.long 0x00 "CTRL,Counter Control Register" bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..." bitfld.long 0x00 18. " ONE_SHOT ,Counter ONE_SHOT" "Continuous,Off" bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit control field" endif textline " " rgroup.long 0x04++0x03 line.long 0x00 "STATUS,Counter Status Register" bitfld.long 0x00 31. " RUNNING ,Counter on/off" "Off,On" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit counter field" bitfld.long 0x00 0. " DOWN ,Counter couting up/down" "Up,Down" group.long 0x08++0x13 line.long 0x00 "COUNTER,Counter Count Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,16-bit counter value" line.long 0x04 "CC,Counter Compare/capture" hexmask.long.word 0x04 0.--15. 1. " CC ,Counter compare/capture value" line.long 0x08 "CC_BUFF,Counter Buffered Compare/capture Register" hexmask.long.word 0x08 0.--15. 1. " CC ,Additional buffer for counter CC register" line.long 0x0C "PERIOD,Counter Period Register" hexmask.long.word 0x0C 0.--15. 1. " PERIOD ,Period value: upper value of the counter" line.long 0x10 "PERIOD_BUFF,Counter Buffered Period Register" hexmask.long.word 0x10 0.--15. 1. " PERIOD ,Additional buffer for counter PERIOD register" group.long 0x20++0x0B line.long 0x00 "TR_CTRL0,Counter Trigger Control Register 0" bitfld.long 0x00 16.--19. " START_SEL ,Input triggers/phi B as a start trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " STOP_SEL ,Triggers as a stop/kill trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " RELOAD_SEL ,Reload trigger/revolution pulse" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " COUNT_SEL ,Count trigger/phi A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " CAPTURE_SEL ,Capture trigger/switch the values[period registers-buffer counterparts]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "TR_CTRL1,Counter Trigger Control Register 1" bitfld.long 0x04 8.--9. " START_EDGE ,Start the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET" bitfld.long 0x04 6.--7. " STOP_EDGE ,Stop the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET" bitfld.long 0x04 4.--5. " RELOAD_EDGE ,Initialize the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET" bitfld.long 0x04 2.--3. " COUNT_EDGE ,Increase or decrease the counter by one" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET" textline " " bitfld.long 0x04 0.--1. " CAPTURE_EDGE ,Copy the counter value into the CC register" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET" line.long 0x08 "TR_CTRL2,Counter Trigger Control Register 2" bitfld.long 0x08 4.--5. " UNDERFLOW_MODE ,Counter underflow Event(Counter=0)" "SET,CLEAR,INVERT,NO_CHANGE" bitfld.long 0x08 2.--3. " OVERFLOW_MODE ,Counter overflow event (Counter=period)" "SET,CLEAR,INVERT,NO_CHANGE" bitfld.long 0x08 0.--1. " CC_MATCH_MODE ,Compare match event" "SET,CLEAR,INVERT,NO_CHANGE" group.long 0x30++0x0F line.long 0x00 "INTR,Interrupt Request Register" eventfld.long 0x00 1. " CC_MATCH ,Counter matches CC register event" "Cleared,Event_detected" eventfld.long 0x00 0. " TC ,Terminal count event" "Cleared,Event_detected" line.long 0x04 "INTR_SET,Interrupt Set Request Register" bitfld.long 0x04 1. " CC_MATCH ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt" bitfld.long 0x04 0. " TC ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt" line.long 0x08 "INTR_MASK,Interrupt Mask Register" bitfld.long 0x08 1. " CC_MATCH ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked" bitfld.long 0x08 0. " TC ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked" line.long 0x0C "INTR_MASKED,Interrupt Masked Request Register" rbitfld.long 0x0C 1. " CC_MATCH ,Logical AND of corresponding request and mask bits" "Not masked,Masked" rbitfld.long 0x0C 0. " TC ,Logical AND of corresponding request and mask bits" "Not masked,Masked" width 0x0B tree.end tree "TCPWM_CNT3" base ad:0x402001C0 width 13. if (((per.l(ad:0x402001C0))&0x7000000)==0x3000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Counter Control Register" bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..." bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature encoding mode" "X1,X2,X4,?..." bitfld.long 0x00 18. " ONE_SHOT ,Counter ONE_SHOT" "Continuous,Off" textline " " bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit control field" elif (((per.l(ad:0x402001C0))&0x7000000)==(0x4000000||0x5000000)) if (((per.l(ad:0x402001C0))&0x08)==0x08) group.long 0x00++0x03 line.long 0x00 "CTRL,Counter Control Register" bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..." bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature encoding mode" ",INV_OUT,INV_COMPL_OUT,?..." bitfld.long 0x00 18. " ONE_SHOT ,Counter ONE_SHOT" "Continuous,Off" textline " " bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit control field" bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,Specifies whether the counter stops on a kill event" "Not stopped,Stopped" textline " " rbitfld.long 0x00 2. " PWM_SYNC_KILL ,Asynchronous/synchronous kill behaviour" "Asynchronous,Synchronous" bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Switching period values" "Not switched,Switched" textline " " bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Switching CC values" "Not switched,Switched_terminal_count" else group.long 0x00++0x03 line.long 0x00 "CTRL,Counter Control Register" bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..." bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature encoding mode" ",INV_OUT,INV_COMPL_OUT,?..." bitfld.long 0x00 18. " ONE_SHOT ,Counter ONE_SHOT" "Continuous,Off" textline " " bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit control field" bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,Specifies whether the counter stops on a kill event" "Not stopped,Stopped" textline " " bitfld.long 0x00 2. " PWM_SYNC_KILL ,Asynchronous/synchronous kill behaviour" "Asynchronous,Synchronous" bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Switching period values" "Not switched,Switched" textline " " bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Switching CC values" "Not switched,Switched_terminal_count" endif elif (((per.l(ad:0x402001C0))&0x7000000)==0x6000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Counter Control Register" bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..." bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature encoding mode" ",INV_OUT,INV_COMPL_OUT,?..." bitfld.long 0x00 18. " ONE_SHOT ,Counter ONE_SHOT" "Continuous,Off" textline " " bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit control field" bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,Specifies whether the counter stops on a kill event" "Not stopped,Stopped" textline " " bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Switching period values" "Not switched,Switched" bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Switching CC values" "Not switched,Switched_terminal_count" elif (((per.l(ad:0x402001C0))&0x7000000)==0x00) group.long 0x00++0x03 line.long 0x00 "CTRL,Counter Control Register" bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..." bitfld.long 0x00 18. " ONE_SHOT ,Counter ONE_SHOT" "Continuous,Off" bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit control field" textline " " bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Switching CC values" "Not switched,Switched_compare_match" else group.long 0x00++0x03 line.long 0x00 "CTRL,Counter Control Register" bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..." bitfld.long 0x00 18. " ONE_SHOT ,Counter ONE_SHOT" "Continuous,Off" bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit control field" endif textline " " rgroup.long 0x04++0x03 line.long 0x00 "STATUS,Counter Status Register" bitfld.long 0x00 31. " RUNNING ,Counter on/off" "Off,On" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit counter field" bitfld.long 0x00 0. " DOWN ,Counter couting up/down" "Up,Down" group.long 0x08++0x13 line.long 0x00 "COUNTER,Counter Count Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,16-bit counter value" line.long 0x04 "CC,Counter Compare/capture" hexmask.long.word 0x04 0.--15. 1. " CC ,Counter compare/capture value" line.long 0x08 "CC_BUFF,Counter Buffered Compare/capture Register" hexmask.long.word 0x08 0.--15. 1. " CC ,Additional buffer for counter CC register" line.long 0x0C "PERIOD,Counter Period Register" hexmask.long.word 0x0C 0.--15. 1. " PERIOD ,Period value: upper value of the counter" line.long 0x10 "PERIOD_BUFF,Counter Buffered Period Register" hexmask.long.word 0x10 0.--15. 1. " PERIOD ,Additional buffer for counter PERIOD register" group.long 0x20++0x0B line.long 0x00 "TR_CTRL0,Counter Trigger Control Register 0" bitfld.long 0x00 16.--19. " START_SEL ,Input triggers/phi B as a start trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " STOP_SEL ,Triggers as a stop/kill trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " RELOAD_SEL ,Reload trigger/revolution pulse" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " COUNT_SEL ,Count trigger/phi A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " CAPTURE_SEL ,Capture trigger/switch the values[period registers-buffer counterparts]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "TR_CTRL1,Counter Trigger Control Register 1" bitfld.long 0x04 8.--9. " START_EDGE ,Start the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET" bitfld.long 0x04 6.--7. " STOP_EDGE ,Stop the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET" bitfld.long 0x04 4.--5. " RELOAD_EDGE ,Initialize the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET" bitfld.long 0x04 2.--3. " COUNT_EDGE ,Increase or decrease the counter by one" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET" textline " " bitfld.long 0x04 0.--1. " CAPTURE_EDGE ,Copy the counter value into the CC register" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET" line.long 0x08 "TR_CTRL2,Counter Trigger Control Register 2" bitfld.long 0x08 4.--5. " UNDERFLOW_MODE ,Counter underflow Event(Counter=0)" "SET,CLEAR,INVERT,NO_CHANGE" bitfld.long 0x08 2.--3. " OVERFLOW_MODE ,Counter overflow event (Counter=period)" "SET,CLEAR,INVERT,NO_CHANGE" bitfld.long 0x08 0.--1. " CC_MATCH_MODE ,Compare match event" "SET,CLEAR,INVERT,NO_CHANGE" group.long 0x30++0x0F line.long 0x00 "INTR,Interrupt Request Register" eventfld.long 0x00 1. " CC_MATCH ,Counter matches CC register event" "Cleared,Event_detected" eventfld.long 0x00 0. " TC ,Terminal count event" "Cleared,Event_detected" line.long 0x04 "INTR_SET,Interrupt Set Request Register" bitfld.long 0x04 1. " CC_MATCH ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt" bitfld.long 0x04 0. " TC ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt" line.long 0x08 "INTR_MASK,Interrupt Mask Register" bitfld.long 0x08 1. " CC_MATCH ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked" bitfld.long 0x08 0. " TC ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked" line.long 0x0C "INTR_MASKED,Interrupt Masked Request Register" rbitfld.long 0x0C 1. " CC_MATCH ,Logical AND of corresponding request and mask bits" "Not masked,Masked" rbitfld.long 0x0C 0. " TC ,Logical AND of corresponding request and mask bits" "Not masked,Masked" width 0x0B tree.end tree "TCPWM_CNT4" base ad:0x40200200 width 13. if (((per.l(ad:0x40200200))&0x7000000)==0x3000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Counter Control Register" bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..." bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature encoding mode" "X1,X2,X4,?..." bitfld.long 0x00 18. " ONE_SHOT ,Counter ONE_SHOT" "Continuous,Off" textline " " bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit control field" elif (((per.l(ad:0x40200200))&0x7000000)==(0x4000000||0x5000000)) if (((per.l(ad:0x40200200))&0x08)==0x08) group.long 0x00++0x03 line.long 0x00 "CTRL,Counter Control Register" bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..." bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature encoding mode" ",INV_OUT,INV_COMPL_OUT,?..." bitfld.long 0x00 18. " ONE_SHOT ,Counter ONE_SHOT" "Continuous,Off" textline " " bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit control field" bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,Specifies whether the counter stops on a kill event" "Not stopped,Stopped" textline " " rbitfld.long 0x00 2. " PWM_SYNC_KILL ,Asynchronous/synchronous kill behaviour" "Asynchronous,Synchronous" bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Switching period values" "Not switched,Switched" textline " " bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Switching CC values" "Not switched,Switched_terminal_count" else group.long 0x00++0x03 line.long 0x00 "CTRL,Counter Control Register" bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..." bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature encoding mode" ",INV_OUT,INV_COMPL_OUT,?..." bitfld.long 0x00 18. " ONE_SHOT ,Counter ONE_SHOT" "Continuous,Off" textline " " bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit control field" bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,Specifies whether the counter stops on a kill event" "Not stopped,Stopped" textline " " bitfld.long 0x00 2. " PWM_SYNC_KILL ,Asynchronous/synchronous kill behaviour" "Asynchronous,Synchronous" bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Switching period values" "Not switched,Switched" textline " " bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Switching CC values" "Not switched,Switched_terminal_count" endif elif (((per.l(ad:0x40200200))&0x7000000)==0x6000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Counter Control Register" bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..." bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature encoding mode" ",INV_OUT,INV_COMPL_OUT,?..." bitfld.long 0x00 18. " ONE_SHOT ,Counter ONE_SHOT" "Continuous,Off" textline " " bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit control field" bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,Specifies whether the counter stops on a kill event" "Not stopped,Stopped" textline " " bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Switching period values" "Not switched,Switched" bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Switching CC values" "Not switched,Switched_terminal_count" elif (((per.l(ad:0x40200200))&0x7000000)==0x00) group.long 0x00++0x03 line.long 0x00 "CTRL,Counter Control Register" bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..." bitfld.long 0x00 18. " ONE_SHOT ,Counter ONE_SHOT" "Continuous,Off" bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit control field" textline " " bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Switching CC values" "Not switched,Switched_compare_match" else group.long 0x00++0x03 line.long 0x00 "CTRL,Counter Control Register" bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..." bitfld.long 0x00 18. " ONE_SHOT ,Counter ONE_SHOT" "Continuous,Off" bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit control field" endif textline " " rgroup.long 0x04++0x03 line.long 0x00 "STATUS,Counter Status Register" bitfld.long 0x00 31. " RUNNING ,Counter on/off" "Off,On" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit counter field" bitfld.long 0x00 0. " DOWN ,Counter couting up/down" "Up,Down" group.long 0x08++0x13 line.long 0x00 "COUNTER,Counter Count Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,16-bit counter value" line.long 0x04 "CC,Counter Compare/capture" hexmask.long.word 0x04 0.--15. 1. " CC ,Counter compare/capture value" line.long 0x08 "CC_BUFF,Counter Buffered Compare/capture Register" hexmask.long.word 0x08 0.--15. 1. " CC ,Additional buffer for counter CC register" line.long 0x0C "PERIOD,Counter Period Register" hexmask.long.word 0x0C 0.--15. 1. " PERIOD ,Period value: upper value of the counter" line.long 0x10 "PERIOD_BUFF,Counter Buffered Period Register" hexmask.long.word 0x10 0.--15. 1. " PERIOD ,Additional buffer for counter PERIOD register" group.long 0x20++0x0B line.long 0x00 "TR_CTRL0,Counter Trigger Control Register 0" bitfld.long 0x00 16.--19. " START_SEL ,Input triggers/phi B as a start trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " STOP_SEL ,Triggers as a stop/kill trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " RELOAD_SEL ,Reload trigger/revolution pulse" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " COUNT_SEL ,Count trigger/phi A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " CAPTURE_SEL ,Capture trigger/switch the values[period registers-buffer counterparts]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "TR_CTRL1,Counter Trigger Control Register 1" bitfld.long 0x04 8.--9. " START_EDGE ,Start the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET" bitfld.long 0x04 6.--7. " STOP_EDGE ,Stop the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET" bitfld.long 0x04 4.--5. " RELOAD_EDGE ,Initialize the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET" bitfld.long 0x04 2.--3. " COUNT_EDGE ,Increase or decrease the counter by one" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET" textline " " bitfld.long 0x04 0.--1. " CAPTURE_EDGE ,Copy the counter value into the CC register" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET" line.long 0x08 "TR_CTRL2,Counter Trigger Control Register 2" bitfld.long 0x08 4.--5. " UNDERFLOW_MODE ,Counter underflow Event(Counter=0)" "SET,CLEAR,INVERT,NO_CHANGE" bitfld.long 0x08 2.--3. " OVERFLOW_MODE ,Counter overflow event (Counter=period)" "SET,CLEAR,INVERT,NO_CHANGE" bitfld.long 0x08 0.--1. " CC_MATCH_MODE ,Compare match event" "SET,CLEAR,INVERT,NO_CHANGE" group.long 0x30++0x0F line.long 0x00 "INTR,Interrupt Request Register" eventfld.long 0x00 1. " CC_MATCH ,Counter matches CC register event" "Cleared,Event_detected" eventfld.long 0x00 0. " TC ,Terminal count event" "Cleared,Event_detected" line.long 0x04 "INTR_SET,Interrupt Set Request Register" bitfld.long 0x04 1. " CC_MATCH ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt" bitfld.long 0x04 0. " TC ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt" line.long 0x08 "INTR_MASK,Interrupt Mask Register" bitfld.long 0x08 1. " CC_MATCH ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked" bitfld.long 0x08 0. " TC ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked" line.long 0x0C "INTR_MASKED,Interrupt Masked Request Register" rbitfld.long 0x0C 1. " CC_MATCH ,Logical AND of corresponding request and mask bits" "Not masked,Masked" rbitfld.long 0x0C 0. " TC ,Logical AND of corresponding request and mask bits" "Not masked,Masked" width 0x0B tree.end tree "TCPWM_CNT5" base ad:0x40200240 width 13. if (((per.l(ad:0x40200240))&0x7000000)==0x3000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Counter Control Register" bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..." bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature encoding mode" "X1,X2,X4,?..." bitfld.long 0x00 18. " ONE_SHOT ,Counter ONE_SHOT" "Continuous,Off" textline " " bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit control field" elif (((per.l(ad:0x40200240))&0x7000000)==(0x4000000||0x5000000)) if (((per.l(ad:0x40200240))&0x08)==0x08) group.long 0x00++0x03 line.long 0x00 "CTRL,Counter Control Register" bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..." bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature encoding mode" ",INV_OUT,INV_COMPL_OUT,?..." bitfld.long 0x00 18. " ONE_SHOT ,Counter ONE_SHOT" "Continuous,Off" textline " " bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit control field" bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,Specifies whether the counter stops on a kill event" "Not stopped,Stopped" textline " " rbitfld.long 0x00 2. " PWM_SYNC_KILL ,Asynchronous/synchronous kill behaviour" "Asynchronous,Synchronous" bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Switching period values" "Not switched,Switched" textline " " bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Switching CC values" "Not switched,Switched_terminal_count" else group.long 0x00++0x03 line.long 0x00 "CTRL,Counter Control Register" bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..." bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature encoding mode" ",INV_OUT,INV_COMPL_OUT,?..." bitfld.long 0x00 18. " ONE_SHOT ,Counter ONE_SHOT" "Continuous,Off" textline " " bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit control field" bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,Specifies whether the counter stops on a kill event" "Not stopped,Stopped" textline " " bitfld.long 0x00 2. " PWM_SYNC_KILL ,Asynchronous/synchronous kill behaviour" "Asynchronous,Synchronous" bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Switching period values" "Not switched,Switched" textline " " bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Switching CC values" "Not switched,Switched_terminal_count" endif elif (((per.l(ad:0x40200240))&0x7000000)==0x6000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Counter Control Register" bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..." bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature encoding mode" ",INV_OUT,INV_COMPL_OUT,?..." bitfld.long 0x00 18. " ONE_SHOT ,Counter ONE_SHOT" "Continuous,Off" textline " " bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit control field" bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,Specifies whether the counter stops on a kill event" "Not stopped,Stopped" textline " " bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Switching period values" "Not switched,Switched" bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Switching CC values" "Not switched,Switched_terminal_count" elif (((per.l(ad:0x40200240))&0x7000000)==0x00) group.long 0x00++0x03 line.long 0x00 "CTRL,Counter Control Register" bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..." bitfld.long 0x00 18. " ONE_SHOT ,Counter ONE_SHOT" "Continuous,Off" bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit control field" textline " " bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Switching CC values" "Not switched,Switched_compare_match" else group.long 0x00++0x03 line.long 0x00 "CTRL,Counter Control Register" bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..." bitfld.long 0x00 18. " ONE_SHOT ,Counter ONE_SHOT" "Continuous,Off" bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit control field" endif textline " " rgroup.long 0x04++0x03 line.long 0x00 "STATUS,Counter Status Register" bitfld.long 0x00 31. " RUNNING ,Counter on/off" "Off,On" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit counter field" bitfld.long 0x00 0. " DOWN ,Counter couting up/down" "Up,Down" group.long 0x08++0x13 line.long 0x00 "COUNTER,Counter Count Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,16-bit counter value" line.long 0x04 "CC,Counter Compare/capture" hexmask.long.word 0x04 0.--15. 1. " CC ,Counter compare/capture value" line.long 0x08 "CC_BUFF,Counter Buffered Compare/capture Register" hexmask.long.word 0x08 0.--15. 1. " CC ,Additional buffer for counter CC register" line.long 0x0C "PERIOD,Counter Period Register" hexmask.long.word 0x0C 0.--15. 1. " PERIOD ,Period value: upper value of the counter" line.long 0x10 "PERIOD_BUFF,Counter Buffered Period Register" hexmask.long.word 0x10 0.--15. 1. " PERIOD ,Additional buffer for counter PERIOD register" group.long 0x20++0x0B line.long 0x00 "TR_CTRL0,Counter Trigger Control Register 0" bitfld.long 0x00 16.--19. " START_SEL ,Input triggers/phi B as a start trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " STOP_SEL ,Triggers as a stop/kill trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " RELOAD_SEL ,Reload trigger/revolution pulse" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " COUNT_SEL ,Count trigger/phi A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " CAPTURE_SEL ,Capture trigger/switch the values[period registers-buffer counterparts]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "TR_CTRL1,Counter Trigger Control Register 1" bitfld.long 0x04 8.--9. " START_EDGE ,Start the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET" bitfld.long 0x04 6.--7. " STOP_EDGE ,Stop the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET" bitfld.long 0x04 4.--5. " RELOAD_EDGE ,Initialize the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET" bitfld.long 0x04 2.--3. " COUNT_EDGE ,Increase or decrease the counter by one" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET" textline " " bitfld.long 0x04 0.--1. " CAPTURE_EDGE ,Copy the counter value into the CC register" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET" line.long 0x08 "TR_CTRL2,Counter Trigger Control Register 2" bitfld.long 0x08 4.--5. " UNDERFLOW_MODE ,Counter underflow Event(Counter=0)" "SET,CLEAR,INVERT,NO_CHANGE" bitfld.long 0x08 2.--3. " OVERFLOW_MODE ,Counter overflow event (Counter=period)" "SET,CLEAR,INVERT,NO_CHANGE" bitfld.long 0x08 0.--1. " CC_MATCH_MODE ,Compare match event" "SET,CLEAR,INVERT,NO_CHANGE" group.long 0x30++0x0F line.long 0x00 "INTR,Interrupt Request Register" eventfld.long 0x00 1. " CC_MATCH ,Counter matches CC register event" "Cleared,Event_detected" eventfld.long 0x00 0. " TC ,Terminal count event" "Cleared,Event_detected" line.long 0x04 "INTR_SET,Interrupt Set Request Register" bitfld.long 0x04 1. " CC_MATCH ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt" bitfld.long 0x04 0. " TC ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt" line.long 0x08 "INTR_MASK,Interrupt Mask Register" bitfld.long 0x08 1. " CC_MATCH ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked" bitfld.long 0x08 0. " TC ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked" line.long 0x0C "INTR_MASKED,Interrupt Masked Request Register" rbitfld.long 0x0C 1. " CC_MATCH ,Logical AND of corresponding request and mask bits" "Not masked,Masked" rbitfld.long 0x0C 0. " TC ,Logical AND of corresponding request and mask bits" "Not masked,Masked" width 0x0B tree.end tree "TCPWM_CNT6" base ad:0x40200280 width 13. if (((per.l(ad:0x40200280))&0x7000000)==0x3000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Counter Control Register" bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..." bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature encoding mode" "X1,X2,X4,?..." bitfld.long 0x00 18. " ONE_SHOT ,Counter ONE_SHOT" "Continuous,Off" textline " " bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit control field" elif (((per.l(ad:0x40200280))&0x7000000)==(0x4000000||0x5000000)) if (((per.l(ad:0x40200280))&0x08)==0x08) group.long 0x00++0x03 line.long 0x00 "CTRL,Counter Control Register" bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..." bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature encoding mode" ",INV_OUT,INV_COMPL_OUT,?..." bitfld.long 0x00 18. " ONE_SHOT ,Counter ONE_SHOT" "Continuous,Off" textline " " bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit control field" bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,Specifies whether the counter stops on a kill event" "Not stopped,Stopped" textline " " rbitfld.long 0x00 2. " PWM_SYNC_KILL ,Asynchronous/synchronous kill behaviour" "Asynchronous,Synchronous" bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Switching period values" "Not switched,Switched" textline " " bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Switching CC values" "Not switched,Switched_terminal_count" else group.long 0x00++0x03 line.long 0x00 "CTRL,Counter Control Register" bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..." bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature encoding mode" ",INV_OUT,INV_COMPL_OUT,?..." bitfld.long 0x00 18. " ONE_SHOT ,Counter ONE_SHOT" "Continuous,Off" textline " " bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit control field" bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,Specifies whether the counter stops on a kill event" "Not stopped,Stopped" textline " " bitfld.long 0x00 2. " PWM_SYNC_KILL ,Asynchronous/synchronous kill behaviour" "Asynchronous,Synchronous" bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Switching period values" "Not switched,Switched" textline " " bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Switching CC values" "Not switched,Switched_terminal_count" endif elif (((per.l(ad:0x40200280))&0x7000000)==0x6000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Counter Control Register" bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..." bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature encoding mode" ",INV_OUT,INV_COMPL_OUT,?..." bitfld.long 0x00 18. " ONE_SHOT ,Counter ONE_SHOT" "Continuous,Off" textline " " bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit control field" bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,Specifies whether the counter stops on a kill event" "Not stopped,Stopped" textline " " bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Switching period values" "Not switched,Switched" bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Switching CC values" "Not switched,Switched_terminal_count" elif (((per.l(ad:0x40200280))&0x7000000)==0x00) group.long 0x00++0x03 line.long 0x00 "CTRL,Counter Control Register" bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..." bitfld.long 0x00 18. " ONE_SHOT ,Counter ONE_SHOT" "Continuous,Off" bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit control field" textline " " bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Switching CC values" "Not switched,Switched_compare_match" else group.long 0x00++0x03 line.long 0x00 "CTRL,Counter Control Register" bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..." bitfld.long 0x00 18. " ONE_SHOT ,Counter ONE_SHOT" "Continuous,Off" bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit control field" endif textline " " rgroup.long 0x04++0x03 line.long 0x00 "STATUS,Counter Status Register" bitfld.long 0x00 31. " RUNNING ,Counter on/off" "Off,On" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit counter field" bitfld.long 0x00 0. " DOWN ,Counter couting up/down" "Up,Down" group.long 0x08++0x13 line.long 0x00 "COUNTER,Counter Count Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,16-bit counter value" line.long 0x04 "CC,Counter Compare/capture" hexmask.long.word 0x04 0.--15. 1. " CC ,Counter compare/capture value" line.long 0x08 "CC_BUFF,Counter Buffered Compare/capture Register" hexmask.long.word 0x08 0.--15. 1. " CC ,Additional buffer for counter CC register" line.long 0x0C "PERIOD,Counter Period Register" hexmask.long.word 0x0C 0.--15. 1. " PERIOD ,Period value: upper value of the counter" line.long 0x10 "PERIOD_BUFF,Counter Buffered Period Register" hexmask.long.word 0x10 0.--15. 1. " PERIOD ,Additional buffer for counter PERIOD register" group.long 0x20++0x0B line.long 0x00 "TR_CTRL0,Counter Trigger Control Register 0" bitfld.long 0x00 16.--19. " START_SEL ,Input triggers/phi B as a start trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " STOP_SEL ,Triggers as a stop/kill trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " RELOAD_SEL ,Reload trigger/revolution pulse" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " COUNT_SEL ,Count trigger/phi A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " CAPTURE_SEL ,Capture trigger/switch the values[period registers-buffer counterparts]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "TR_CTRL1,Counter Trigger Control Register 1" bitfld.long 0x04 8.--9. " START_EDGE ,Start the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET" bitfld.long 0x04 6.--7. " STOP_EDGE ,Stop the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET" bitfld.long 0x04 4.--5. " RELOAD_EDGE ,Initialize the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET" bitfld.long 0x04 2.--3. " COUNT_EDGE ,Increase or decrease the counter by one" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET" textline " " bitfld.long 0x04 0.--1. " CAPTURE_EDGE ,Copy the counter value into the CC register" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET" line.long 0x08 "TR_CTRL2,Counter Trigger Control Register 2" bitfld.long 0x08 4.--5. " UNDERFLOW_MODE ,Counter underflow Event(Counter=0)" "SET,CLEAR,INVERT,NO_CHANGE" bitfld.long 0x08 2.--3. " OVERFLOW_MODE ,Counter overflow event (Counter=period)" "SET,CLEAR,INVERT,NO_CHANGE" bitfld.long 0x08 0.--1. " CC_MATCH_MODE ,Compare match event" "SET,CLEAR,INVERT,NO_CHANGE" group.long 0x30++0x0F line.long 0x00 "INTR,Interrupt Request Register" eventfld.long 0x00 1. " CC_MATCH ,Counter matches CC register event" "Cleared,Event_detected" eventfld.long 0x00 0. " TC ,Terminal count event" "Cleared,Event_detected" line.long 0x04 "INTR_SET,Interrupt Set Request Register" bitfld.long 0x04 1. " CC_MATCH ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt" bitfld.long 0x04 0. " TC ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt" line.long 0x08 "INTR_MASK,Interrupt Mask Register" bitfld.long 0x08 1. " CC_MATCH ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked" bitfld.long 0x08 0. " TC ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked" line.long 0x0C "INTR_MASKED,Interrupt Masked Request Register" rbitfld.long 0x0C 1. " CC_MATCH ,Logical AND of corresponding request and mask bits" "Not masked,Masked" rbitfld.long 0x0C 0. " TC ,Logical AND of corresponding request and mask bits" "Not masked,Masked" width 0x0B tree.end tree "TCPWM_CNT7" base ad:0x402002C0 width 13. if (((per.l(ad:0x402002C0))&0x7000000)==0x3000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Counter Control Register" bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..." bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature encoding mode" "X1,X2,X4,?..." bitfld.long 0x00 18. " ONE_SHOT ,Counter ONE_SHOT" "Continuous,Off" textline " " bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit control field" elif (((per.l(ad:0x402002C0))&0x7000000)==(0x4000000||0x5000000)) if (((per.l(ad:0x402002C0))&0x08)==0x08) group.long 0x00++0x03 line.long 0x00 "CTRL,Counter Control Register" bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..." bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature encoding mode" ",INV_OUT,INV_COMPL_OUT,?..." bitfld.long 0x00 18. " ONE_SHOT ,Counter ONE_SHOT" "Continuous,Off" textline " " bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit control field" bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,Specifies whether the counter stops on a kill event" "Not stopped,Stopped" textline " " rbitfld.long 0x00 2. " PWM_SYNC_KILL ,Asynchronous/synchronous kill behaviour" "Asynchronous,Synchronous" bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Switching period values" "Not switched,Switched" textline " " bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Switching CC values" "Not switched,Switched_terminal_count" else group.long 0x00++0x03 line.long 0x00 "CTRL,Counter Control Register" bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..." bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature encoding mode" ",INV_OUT,INV_COMPL_OUT,?..." bitfld.long 0x00 18. " ONE_SHOT ,Counter ONE_SHOT" "Continuous,Off" textline " " bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit control field" bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,Specifies whether the counter stops on a kill event" "Not stopped,Stopped" textline " " bitfld.long 0x00 2. " PWM_SYNC_KILL ,Asynchronous/synchronous kill behaviour" "Asynchronous,Synchronous" bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Switching period values" "Not switched,Switched" textline " " bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Switching CC values" "Not switched,Switched_terminal_count" endif elif (((per.l(ad:0x402002C0))&0x7000000)==0x6000000) group.long 0x00++0x03 line.long 0x00 "CTRL,Counter Control Register" bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..." bitfld.long 0x00 20.--21. " QUADRATURE_MODE ,Quadrature encoding mode" ",INV_OUT,INV_COMPL_OUT,?..." bitfld.long 0x00 18. " ONE_SHOT ,Counter ONE_SHOT" "Continuous,Off" textline " " bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit control field" bitfld.long 0x00 3. " PWM_STOP_ON_KILL ,Specifies whether the counter stops on a kill event" "Not stopped,Stopped" textline " " bitfld.long 0x00 1. " AUTO_RELOAD_PERIOD ,Switching period values" "Not switched,Switched" bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Switching CC values" "Not switched,Switched_terminal_count" elif (((per.l(ad:0x402002C0))&0x7000000)==0x00) group.long 0x00++0x03 line.long 0x00 "CTRL,Counter Control Register" bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..." bitfld.long 0x00 18. " ONE_SHOT ,Counter ONE_SHOT" "Continuous,Off" bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit control field" textline " " bitfld.long 0x00 0. " AUTO_RELOAD_CC ,Switching CC values" "Not switched,Switched_compare_match" else group.long 0x00++0x03 line.long 0x00 "CTRL,Counter Control Register" bitfld.long 0x00 24.--26. " MODE ,Counter mode" "TIMER,,CAPTURE,QUAD,PWM,PWM_DT,PWM_PR,?..." bitfld.long 0x00 18. " ONE_SHOT ,Counter ONE_SHOT" "Continuous,Off" bitfld.long 0x00 16.--17. " UP_DOWN_MODE ,Determines counter direction" "COUNT_UP,COUNT_DOWN,COUNT_UPDN1,COUNT_UPDN2" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit control field" endif textline " " rgroup.long 0x04++0x03 line.long 0x00 "STATUS,Counter Status Register" bitfld.long 0x00 31. " RUNNING ,Counter on/off" "Off,On" hexmask.long.byte 0x00 8.--15. 1. " GENERIC ,Generic 8-bit counter field" bitfld.long 0x00 0. " DOWN ,Counter couting up/down" "Up,Down" group.long 0x08++0x13 line.long 0x00 "COUNTER,Counter Count Register" hexmask.long.word 0x00 0.--15. 1. " COUNTER ,16-bit counter value" line.long 0x04 "CC,Counter Compare/capture" hexmask.long.word 0x04 0.--15. 1. " CC ,Counter compare/capture value" line.long 0x08 "CC_BUFF,Counter Buffered Compare/capture Register" hexmask.long.word 0x08 0.--15. 1. " CC ,Additional buffer for counter CC register" line.long 0x0C "PERIOD,Counter Period Register" hexmask.long.word 0x0C 0.--15. 1. " PERIOD ,Period value: upper value of the counter" line.long 0x10 "PERIOD_BUFF,Counter Buffered Period Register" hexmask.long.word 0x10 0.--15. 1. " PERIOD ,Additional buffer for counter PERIOD register" group.long 0x20++0x0B line.long 0x00 "TR_CTRL0,Counter Trigger Control Register 0" bitfld.long 0x00 16.--19. " START_SEL ,Input triggers/phi B as a start trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. " STOP_SEL ,Triggers as a stop/kill trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " RELOAD_SEL ,Reload trigger/revolution pulse" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " COUNT_SEL ,Count trigger/phi A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " CAPTURE_SEL ,Capture trigger/switch the values[period registers-buffer counterparts]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "TR_CTRL1,Counter Trigger Control Register 1" bitfld.long 0x04 8.--9. " START_EDGE ,Start the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET" bitfld.long 0x04 6.--7. " STOP_EDGE ,Stop the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET" bitfld.long 0x04 4.--5. " RELOAD_EDGE ,Initialize the counter" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET" bitfld.long 0x04 2.--3. " COUNT_EDGE ,Increase or decrease the counter by one" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET" textline " " bitfld.long 0x04 0.--1. " CAPTURE_EDGE ,Copy the counter value into the CC register" "RISING_EDGE,FALLING_EDGE,BOTH_EDGES,NO_EDGE_DET" line.long 0x08 "TR_CTRL2,Counter Trigger Control Register 2" bitfld.long 0x08 4.--5. " UNDERFLOW_MODE ,Counter underflow Event(Counter=0)" "SET,CLEAR,INVERT,NO_CHANGE" bitfld.long 0x08 2.--3. " OVERFLOW_MODE ,Counter overflow event (Counter=period)" "SET,CLEAR,INVERT,NO_CHANGE" bitfld.long 0x08 0.--1. " CC_MATCH_MODE ,Compare match event" "SET,CLEAR,INVERT,NO_CHANGE" group.long 0x30++0x0F line.long 0x00 "INTR,Interrupt Request Register" eventfld.long 0x00 1. " CC_MATCH ,Counter matches CC register event" "Cleared,Event_detected" eventfld.long 0x00 0. " TC ,Terminal count event" "Cleared,Event_detected" line.long 0x04 "INTR_SET,Interrupt Set Request Register" bitfld.long 0x04 1. " CC_MATCH ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt" bitfld.long 0x04 0. " TC ,Set corresponding bit in interrupt request register" "No interrupt,Interrupt" line.long 0x08 "INTR_MASK,Interrupt Mask Register" bitfld.long 0x08 1. " CC_MATCH ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked" bitfld.long 0x08 0. " TC ,Mask bit for corresponding bit in interrupt request register" "Not masked,Masked" line.long 0x0C "INTR_MASKED,Interrupt Masked Request Register" rbitfld.long 0x0C 1. " CC_MATCH ,Logical AND of corresponding request and mask bits" "Not masked,Masked" rbitfld.long 0x0C 0. " TC ,Logical AND of corresponding request and mask bits" "Not masked,Masked" width 0x0B tree.end tree.end tree "Peripheral Trigger registers" base ad:0x40012000 width 29. group.long 0x0++0x03 line.long 0x00 "PERI_TR_GROUP0_TR_OUT_CTL0,GROUP 0 Trigger control register 0" bitfld.long 0x00 0.--5. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x4++0x03 line.long 0x00 "PERI_TR_GROUP0_TR_OUT_CTL1,GROUP 0 Trigger control register 1" bitfld.long 0x00 0.--5. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x8++0x03 line.long 0x00 "PERI_TR_GROUP0_TR_OUT_CTL2,GROUP 0 Trigger control register 2" bitfld.long 0x00 0.--5. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xC++0x03 line.long 0x00 "PERI_TR_GROUP0_TR_OUT_CTL3,GROUP 0 Trigger control register 3" bitfld.long 0x00 0.--5. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x10++0x03 line.long 0x00 "PERI_TR_GROUP0_TR_OUT_CTL4,GROUP 0 Trigger control register 4" bitfld.long 0x00 0.--5. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x14++0x03 line.long 0x00 "PERI_TR_GROUP0_TR_OUT_CTL5,GROUP 0 Trigger control register 5" bitfld.long 0x00 0.--5. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x18++0x03 line.long 0x00 "PERI_TR_GROUP0_TR_OUT_CTL6,GROUP 0 Trigger control register 6" bitfld.long 0x00 0.--5. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x1C++0x03 line.long 0x00 "PERI_TR_GROUP0_TR_OUT_CTL7,GROUP 0 Trigger control register 7" bitfld.long 0x00 0.--5. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x200++0x03 line.long 0x00 "PERI_TR_GROUP1_TR_OUT_CTL0,GROUP 1 Trigger Control Register 0" bitfld.long 0x00 0.--4. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x204++0x03 line.long 0x00 "PERI_TR_GROUP1_TR_OUT_CTL1,GROUP 1 Trigger Control Register 1" bitfld.long 0x00 0.--4. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x208++0x03 line.long 0x00 "PERI_TR_GROUP1_TR_OUT_CTL2,GROUP 1 Trigger Control Register 2" bitfld.long 0x00 0.--4. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x20C++0x03 line.long 0x00 "PERI_TR_GROUP1_TR_OUT_CTL3,GROUP 1 Trigger Control Register 3" bitfld.long 0x00 0.--4. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x210++0x03 line.long 0x00 "PERI_TR_GROUP1_TR_OUT_CTL4,GROUP 1 Trigger Control Register 4" bitfld.long 0x00 0.--4. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x214++0x03 line.long 0x00 "PERI_TR_GROUP1_TR_OUT_CTL5,GROUP 1 Trigger Control Register 5" bitfld.long 0x00 0.--4. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x218++0x03 line.long 0x00 "PERI_TR_GROUP1_TR_OUT_CTL6,GROUP 1 Trigger Control Register 6" bitfld.long 0x00 0.--4. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x21C++0x03 line.long 0x00 "PERI_TR_GROUP1_TR_OUT_CTL7,GROUP 1 Trigger Control Register 7" bitfld.long 0x00 0.--4. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x400++0x03 line.long 0x00 "PERI_TR_GROUP2_TR_OUT_CTL0,GROUP 2 Trigger Control Register 0" bitfld.long 0x00 0.--4. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x404++0x03 line.long 0x00 "PERI_TR_GROUP2_TR_OUT_CTL1,GROUP 2 Trigger Control Register 1" bitfld.long 0x00 0.--4. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x408++0x03 line.long 0x00 "PERI_TR_GROUP2_TR_OUT_CTL2,GROUP 2 Trigger Control Register 2" bitfld.long 0x00 0.--4. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x40C++0x03 line.long 0x00 "PERI_TR_GROUP2_TR_OUT_CTL3,GROUP 2 Trigger Control Register 3" bitfld.long 0x00 0.--4. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x410++0x03 line.long 0x00 "PERI_TR_GROUP2_TR_OUT_CTL4,GROUP 2 Trigger Control Register 4" bitfld.long 0x00 0.--4. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x414++0x03 line.long 0x00 "PERI_TR_GROUP2_TR_OUT_CTL5,GROUP 2 Trigger Control Register 5" bitfld.long 0x00 0.--4. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x418++0x03 line.long 0x00 "PERI_TR_GROUP2_TR_OUT_CTL6,GROUP 2 Trigger Control Register 6" bitfld.long 0x00 0.--4. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x41C++0x03 line.long 0x00 "PERI_TR_GROUP2_TR_OUT_CTL7,GROUP 2 Trigger Control Register 7" bitfld.long 0x00 0.--4. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x420++0x03 line.long 0x00 "PERI_TR_GROUP2_TR_OUT_CTL8,GROUP 2 Trigger Control Register 8" bitfld.long 0x00 0.--4. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x424++0x03 line.long 0x00 "PERI_TR_GROUP2_TR_OUT_CTL9,GROUP 2 Trigger Control Register 9" bitfld.long 0x00 0.--4. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x428++0x03 line.long 0x00 "PERI_TR_GROUP2_TR_OUT_CTL10,GROUP 2 Trigger Control Register 10" bitfld.long 0x00 0.--4. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x42C++0x03 line.long 0x00 "PERI_TR_GROUP2_TR_OUT_CTL11,GROUP 2 Trigger Control Register 11" bitfld.long 0x00 0.--4. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x430++0x03 line.long 0x00 "PERI_TR_GROUP2_TR_OUT_CTL12,GROUP 2 Trigger Control Register 12" bitfld.long 0x00 0.--4. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x434++0x03 line.long 0x00 "PERI_TR_GROUP2_TR_OUT_CTL13,GROUP 2 Trigger Control Register 13" bitfld.long 0x00 0.--4. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x438++0x03 line.long 0x00 "PERI_TR_GROUP2_TR_OUT_CTL14,GROUP 2 Trigger Control Register 14" bitfld.long 0x00 0.--4. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x43C++0x03 line.long 0x00 "PERI_TR_GROUP2_TR_OUT_CTL15,GROUP 2 Trigger Control Register 15" bitfld.long 0x00 0.--4. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x600++0x03 line.long 0x00 "PERI_TR_GROUP3_TR_OUT_CTL0,GROUP 3 Trigger Control Register 0" bitfld.long 0x00 0.--3. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x604++0x03 line.long 0x00 "PERI_TR_GROUP3_TR_OUT_CTL1,GROUP 3 Trigger Control Register 1" bitfld.long 0x00 0.--3. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x608++0x03 line.long 0x00 "PERI_TR_GROUP3_TR_OUT_CTL2,GROUP 3 Trigger Control Register 2" bitfld.long 0x00 0.--3. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x60C++0x03 line.long 0x00 "PERI_TR_GROUP3_TR_OUT_CTL3,GROUP 3 Trigger Control Register 3" bitfld.long 0x00 0.--3. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x610++0x03 line.long 0x00 "PERI_TR_GROUP3_TR_OUT_CTL4,GROUP 3 Trigger Control Register 4" bitfld.long 0x00 0.--3. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x614++0x03 line.long 0x00 "PERI_TR_GROUP3_TR_OUT_CTL5,GROUP 3 Trigger Control Register 5" bitfld.long 0x00 0.--3. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x618++0x03 line.long 0x00 "PERI_TR_GROUP3_TR_OUT_CTL6,GROUP 3 Trigger Control Register 6" bitfld.long 0x00 0.--3. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x61C++0x03 line.long 0x00 "PERI_TR_GROUP3_TR_OUT_CTL7,GROUP 3 Trigger Control Register 7" bitfld.long 0x00 0.--3. " SEL ,Specifies input trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree "UDB (Universal Digital Block registers)" base ad:0x400F8000 width 13. group.long 0x00++0x03 line.long 0x00 "UDB_INT_CFG,UDB Subsystem Interrupt Configuration" bitfld.long 0x00 16. " INT_MODE_CFG[16] ,Interrupt 16 mode" "Level,Pulse" bitfld.long 0x00 15. " [15] ,Interrupt 15 mode" "Level,Pulse" bitfld.long 0x00 14. " [14] ,Interrupt 14 mode" "Level,Pulse" bitfld.long 0x00 13. " [13] ,Interrupt 13 mode" "Level,Pulse" textline " " bitfld.long 0x00 12. " [12] ,Interrupt 12 mode" "Level,Pulse" bitfld.long 0x00 11. " [11] ,Interrupt 11 mode" "Level,Pulse" bitfld.long 0x00 10. " [10] ,Interrupt 10 mode" "Level,Pulse" bitfld.long 0x00 9. " [9] ,Interrupt 9 mode" "Level,Pulse" textline " " bitfld.long 0x00 8. " [8] ,Interrupt 8 mode" "Level,Pulse" bitfld.long 0x00 7. " [7] ,Interrupt 7 mode" "Level,Pulse" bitfld.long 0x00 6. " [6] ,Interrupt 6 mode" "Level,Pulse" bitfld.long 0x00 5. " [5] ,Interrupt 5 mode" "Level,Pulse" textline " " bitfld.long 0x00 4. " [4] ,Interrupt 4 mode" "Level,Pulse" bitfld.long 0x00 3. " [3] ,Interrupt 3 mode" "Level,Pulse" bitfld.long 0x00 2. " [2] ,Interrupt 2 mode" "Level,Pulse" bitfld.long 0x00 1. " [1] ,Interrupt 1 mode" "Level,Pulse" textline " " bitfld.long 0x00 0. " [0] ,Interrupt 0 mode" "Level,Pulse" width 0x0B tree.end tree "UDB Array Bank Control registers" base ad:0x400F6000 width 21. group.byte 0x00++0x02 line.byte 0x00 "UDB_BCTL0_DRV,Master Digital Clock Drive Register" line.byte 0x01 "UDB_BCTL0_MDCLK_EN,Master Digital Clock Enable Register" line.byte 0x02 "UDB_BCTL0_MBCLK_EN,Master Bus Clock Enable Register" bitfld.byte 0x02 0. " BCEN ,Bank clock enable control" "Disabled,Enabled" group.byte 0x08++0x03 line.byte 0x00 "UDB_BCTL0_BOTSEL_L,Lower Nibble Bottom Digital Clock Select Register" bitfld.byte 0x00 6.--7. " CLK_SEL3 ,Clock selection control for digital clock 3" "EDGE_ENABLES,PORT_INPUT,DSI_OUTPUT,SYNC_DSI_OUTPUT" bitfld.byte 0x00 4.--5. " CLK_SEL2 ,Clock selection control for digital clock 2" "EDGE_ENABLES,PORT_INPUT,DSI_OUTPUT,SYNC_DSI_OUTPUT" bitfld.byte 0x00 2.--3. " CLK_SEL1 ,Clock selection control for digital clock 1" "EDGE_ENABLES,PORT_INPUT,DSI_OUTPUT,SYNC_DSI_OUTPUT" bitfld.byte 0x00 0.--1. " CLK_SEL0 ,Clock selection control for digital clock 0" "EDGE_ENABLES,PORT_INPUT,DSI_OUTPUT,SYNC_DSI_OUTPUT" line.byte 0x01 "UDB_BCTL0_BOTSEL_U,Upper Nibble Bottom Digital Clock Select Register" bitfld.byte 0x01 6.--7. " CLK_SEL7 ,Clock selection control for digital clock 7" "EDGE_ENABLES,PORT_INPUT,DSI_OUTPUT,SYNC_DSI_OUTPUT" bitfld.byte 0x01 4.--5. " CLK_SEL6 ,Clock selection control for digital clock 6" "EDGE_ENABLES,PORT_INPUT,DSI_OUTPUT,SYNC_DSI_OUTPUT" bitfld.byte 0x01 2.--3. " CLK_SEL5 ,Clock selection control for digital clock 5" "EDGE_ENABLES,PORT_INPUT,DSI_OUTPUT,SYNC_DSI_OUTPUT" bitfld.byte 0x01 0.--1. " CLK_SEL4 ,Clock selection control for digital clock 4" "EDGE_ENABLES,PORT_INPUT,DSI_OUTPUT,SYNC_DSI_OUTPUT" line.byte 0x02 "UDB_BCTL0_TOPSEL_L,Lower Nibble Top Digital Clock Select Register" bitfld.byte 0x02 6.--7. " CLK_SEL3 ,Clock selection control for digital clock 3" "EDGE_ENABLES,PORT_INPUT,DSI_OUTPUT,SYNC_DSI_OUTPUT" bitfld.byte 0x02 4.--5. " CLK_SEL2 ,Clock selection control for digital clock 2" "EDGE_ENABLES,PORT_INPUT,DSI_OUTPUT,SYNC_DSI_OUTPUT" bitfld.byte 0x02 2.--3. " CLK_SEL1 ,Clock selection control for digital clock 1" "EDGE_ENABLES,PORT_INPUT,DSI_OUTPUT,SYNC_DSI_OUTPUT" bitfld.byte 0x02 0.--1. " CLK_SEL0 ,Clock selection control for digital clock 0" "EDGE_ENABLES,PORT_INPUT,DSI_OUTPUT,SYNC_DSI_OUTPUT" line.byte 0x03 "UDB_BCTL0_TOPSEL_U,Upper Nibble Top Digital Clock Select Register" bitfld.byte 0x03 6.--7. " CLK_SEL7 ,Clock selection control for digital clock 7" "EDGE_ENABLES,PORT_INPUT,DSI_OUTPUT,SYNC_DSI_OUTPUT" bitfld.byte 0x03 4.--5. " CLK_SEL6 ,Clock selection control for digital clock 6" "EDGE_ENABLES,PORT_INPUT,DSI_OUTPUT,SYNC_DSI_OUTPUT" bitfld.byte 0x03 2.--3. " CLK_SEL5 ,Clock selection control for digital clock 5" "EDGE_ENABLES,PORT_INPUT,DSI_OUTPUT,SYNC_DSI_OUTPUT" bitfld.byte 0x03 0.--1. " CLK_SEL4 ,Clock selection control for digital clock 4" "EDGE_ENABLES,PORT_INPUT,DSI_OUTPUT,SYNC_DSI_OUTPUT" group.word 0x10++0x01 line.word 0x00 "UDB_BCTL0_QCLK_EN0,Quadrant Digital Clock Enable Registers 0" bitfld.word 0x00 15. " SLEEP_TEST ,Sleep into the UDB array for internal UDB test purposes" "Disabled,Enabled" bitfld.word 0x00 14. " NC0 ,Spare register bit NC0" "0,1" bitfld.word 0x00 13. " WR_CFG_OPT ,Select 1/2 clock cycle or full clock cycle generation for bus_last_strobe" "FULL_CYCLE_STB,HALF_CYCLE_STB" bitfld.word 0x00 12. " GLB_DSI_WR ,Enable global write operation for the DSI routing channels" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " DISABLE_ROUTE ,Routing in the associated quadrant" "Disabled,Enabled" bitfld.word 0x00 10. " GCH_WR_HI ,Enable global write operation for the routing channel with the higher address in the associated quadrant" "Disabled,Enabled" bitfld.word 0x00 9. " GCH_WR_LO ,Enable global write operation for the routing channel with the lower address in the associated quadrant" "Disabled,Enabled" bitfld.word 0x00 8. " BCEN_Q ,Bank Clock Enable Control" "Disabled,Enabled" textline " " hexmask.word.byte 0x00 0.--7. 1. " DCEN_Q ,Digital clock enable for indexed digital clock for the associated quadrant" group.word 0x10++0x01 line.word 0x00 "UDB_BCTL0_QCLK_EN1,Quadrant Digital Clock Enable Registers 1" bitfld.word 0x00 15. " SLEEP_TEST ,Sleep into the UDB array for internal UDB test purposes" "Disabled,Enabled" bitfld.word 0x00 14. " NC0 ,Spare register bit NC0" "0,1" bitfld.word 0x00 13. " WR_CFG_OPT ,Select 1/2 clock cycle or full clock cycle generation for bus_last_strobe" "FULL_CYCLE_STB,HALF_CYCLE_STB" bitfld.word 0x00 12. " GLB_DSI_WR ,Enable global write operation for the DSI routing channels" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " DISABLE_ROUTE ,Routing in the associated quadrant" "Disabled,Enabled" bitfld.word 0x00 10. " GCH_WR_HI ,Enable global write operation for the routing channel with the higher address in the associated quadrant" "Disabled,Enabled" bitfld.word 0x00 9. " GCH_WR_LO ,Enable global write operation for the routing channel with the lower address in the associated quadrant" "Disabled,Enabled" bitfld.word 0x00 8. " BCEN_Q ,Bank Clock Enable Control" "Disabled,Enabled" textline " " hexmask.word.byte 0x00 0.--7. 1. " DCEN_Q ,Digital clock enable for indexed digital clock for the associated quadrant" group.word 0x10++0x01 line.word 0x00 "UDB_BCTL0_QCLK_EN2,Quadrant Digital Clock Enable Registers 2" bitfld.word 0x00 15. " SLEEP_TEST ,Sleep into the UDB array for internal UDB test purposes" "Disabled,Enabled" bitfld.word 0x00 14. " NC0 ,Spare register bit NC0" "0,1" bitfld.word 0x00 13. " WR_CFG_OPT ,Select 1/2 clock cycle or full clock cycle generation for bus_last_strobe" "FULL_CYCLE_STB,HALF_CYCLE_STB" bitfld.word 0x00 12. " GLB_DSI_WR ,Enable global write operation for the DSI routing channels" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " DISABLE_ROUTE ,Routing in the associated quadrant" "Disabled,Enabled" bitfld.word 0x00 10. " GCH_WR_HI ,Enable global write operation for the routing channel with the higher address in the associated quadrant" "Disabled,Enabled" bitfld.word 0x00 9. " GCH_WR_LO ,Enable global write operation for the routing channel with the lower address in the associated quadrant" "Disabled,Enabled" bitfld.word 0x00 8. " BCEN_Q ,Bank Clock Enable Control" "Disabled,Enabled" textline " " hexmask.word.byte 0x00 0.--7. 1. " DCEN_Q ,Digital clock enable for indexed digital clock for the associated quadrant" group.word 0x10++0x01 line.word 0x00 "UDB_BCTL0_QCLK_EN3,Quadrant Digital Clock Enable Registers 3" bitfld.word 0x00 15. " SLEEP_TEST ,Sleep into the UDB array for internal UDB test purposes" "Disabled,Enabled" bitfld.word 0x00 14. " NC0 ,Spare register bit NC0" "0,1" bitfld.word 0x00 13. " WR_CFG_OPT ,Select 1/2 clock cycle or full clock cycle generation for bus_last_strobe" "FULL_CYCLE_STB,HALF_CYCLE_STB" bitfld.word 0x00 12. " GLB_DSI_WR ,Enable global write operation for the DSI routing channels" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " DISABLE_ROUTE ,Routing in the associated quadrant" "Disabled,Enabled" bitfld.word 0x00 10. " GCH_WR_HI ,Enable global write operation for the routing channel with the higher address in the associated quadrant" "Disabled,Enabled" bitfld.word 0x00 9. " GCH_WR_LO ,Enable global write operation for the routing channel with the lower address in the associated quadrant" "Disabled,Enabled" bitfld.word 0x00 8. " BCEN_Q ,Bank Clock Enable Control" "Disabled,Enabled" textline " " hexmask.word.byte 0x00 0.--7. 1. " DCEN_Q ,Digital clock enable for indexed digital clock for the associated quadrant" width 0x0B tree.end tree "UDB Digital System Interconnect registers" tree "UDB_DSI0" base ad:0x400F4000 width 15. group.byte 0x0++0x00 line.byte 0x00 "HC0,DSI HC Tile Configuration 0" group.byte 0x1++0x00 line.byte 0x00 "HC1,DSI HC Tile Configuration 1" group.byte 0x2++0x00 line.byte 0x00 "HC2,DSI HC Tile Configuration 2" group.byte 0x3++0x00 line.byte 0x00 "HC3,DSI HC Tile Configuration 3" group.byte 0x4++0x00 line.byte 0x00 "HC4,DSI HC Tile Configuration 4" group.byte 0x5++0x00 line.byte 0x00 "HC5,DSI HC Tile Configuration 5" group.byte 0x6++0x00 line.byte 0x00 "HC6,DSI HC Tile Configuration 6" group.byte 0x7++0x00 line.byte 0x00 "HC7,DSI HC Tile Configuration 7" group.byte 0x8++0x00 line.byte 0x00 "HC8,DSI HC Tile Configuration 8" group.byte 0x9++0x00 line.byte 0x00 "HC9,DSI HC Tile Configuration 9" group.byte 0xA++0x00 line.byte 0x00 "HC10,DSI HC Tile Configuration 10" group.byte 0xB++0x00 line.byte 0x00 "HC11,DSI HC Tile Configuration 11" group.byte 0xC++0x00 line.byte 0x00 "HC12,DSI HC Tile Configuration 12" group.byte 0xD++0x00 line.byte 0x00 "HC13,DSI HC Tile Configuration 13" group.byte 0xE++0x00 line.byte 0x00 "HC14,DSI HC Tile Configuration 14" group.byte 0xF++0x00 line.byte 0x00 "HC15,DSI HC Tile Configuration 15" group.byte 0x10++0x00 line.byte 0x00 "HC16,DSI HC Tile Configuration 16" group.byte 0x11++0x00 line.byte 0x00 "HC17,DSI HC Tile Configuration 17" group.byte 0x12++0x00 line.byte 0x00 "HC18,DSI HC Tile Configuration 18" group.byte 0x13++0x00 line.byte 0x00 "HC19,DSI HC Tile Configuration 19" group.byte 0x14++0x00 line.byte 0x00 "HC20,DSI HC Tile Configuration 20" group.byte 0x15++0x00 line.byte 0x00 "HC21,DSI HC Tile Configuration 21" group.byte 0x16++0x00 line.byte 0x00 "HC22,DSI HC Tile Configuration 22" group.byte 0x17++0x00 line.byte 0x00 "HC23,DSI HC Tile Configuration 23" group.byte 0x18++0x00 line.byte 0x00 "HC24,DSI HC Tile Configuration 24" group.byte 0x19++0x00 line.byte 0x00 "HC25,DSI HC Tile Configuration 25" group.byte 0x1A++0x00 line.byte 0x00 "HC26,DSI HC Tile Configuration 26" group.byte 0x1B++0x00 line.byte 0x00 "HC27,DSI HC Tile Configuration 27" group.byte 0x1C++0x00 line.byte 0x00 "HC28,DSI HC Tile Configuration 28" group.byte 0x1D++0x00 line.byte 0x00 "HC29,DSI HC Tile Configuration 29" group.byte 0x1E++0x00 line.byte 0x00 "HC30,DSI HC Tile Configuration 30" group.byte 0x1F++0x00 line.byte 0x00 "HC31,DSI HC Tile Configuration 31" group.byte 0x20++0x00 line.byte 0x00 "HC32,DSI HC Tile Configuration 32" group.byte 0x21++0x00 line.byte 0x00 "HC33,DSI HC Tile Configuration 33" group.byte 0x22++0x00 line.byte 0x00 "HC34,DSI HC Tile Configuration 34" group.byte 0x23++0x00 line.byte 0x00 "HC35,DSI HC Tile Configuration 35" group.byte 0x24++0x00 line.byte 0x00 "HC36,DSI HC Tile Configuration 36" group.byte 0x25++0x00 line.byte 0x00 "HC37,DSI HC Tile Configuration 37" group.byte 0x26++0x00 line.byte 0x00 "HC38,DSI HC Tile Configuration 38" group.byte 0x27++0x00 line.byte 0x00 "HC39,DSI HC Tile Configuration 39" group.byte 0x28++0x00 line.byte 0x00 "HC40,DSI HC Tile Configuration 40" group.byte 0x29++0x00 line.byte 0x00 "HC41,DSI HC Tile Configuration 41" group.byte 0x2A++0x00 line.byte 0x00 "HC42,DSI HC Tile Configuration 42" group.byte 0x2B++0x00 line.byte 0x00 "HC43,DSI HC Tile Configuration 43" group.byte 0x2C++0x00 line.byte 0x00 "HC44,DSI HC Tile Configuration 44" group.byte 0x2D++0x00 line.byte 0x00 "HC45,DSI HC Tile Configuration 45" group.byte 0x2E++0x00 line.byte 0x00 "HC46,DSI HC Tile Configuration 46" group.byte 0x2F++0x00 line.byte 0x00 "HC47,DSI HC Tile Configuration 47" group.byte 0x30++0x00 line.byte 0x00 "HC48,DSI HC Tile Configuration 48" group.byte 0x31++0x00 line.byte 0x00 "HC49,DSI HC Tile Configuration 49" group.byte 0x32++0x00 line.byte 0x00 "HC50,DSI HC Tile Configuration 50" group.byte 0x33++0x00 line.byte 0x00 "HC51,DSI HC Tile Configuration 51" group.byte 0x34++0x00 line.byte 0x00 "HC52,DSI HC Tile Configuration 52" group.byte 0x35++0x00 line.byte 0x00 "HC53,DSI HC Tile Configuration 53" group.byte 0x36++0x00 line.byte 0x00 "HC54,DSI HC Tile Configuration 54" group.byte 0x37++0x00 line.byte 0x00 "HC55,DSI HC Tile Configuration 55" group.byte 0x38++0x00 line.byte 0x00 "HC56,DSI HC Tile Configuration 56" group.byte 0x39++0x00 line.byte 0x00 "HC57,DSI HC Tile Configuration 57" group.byte 0x3A++0x00 line.byte 0x00 "HC58,DSI HC Tile Configuration 58" group.byte 0x3B++0x00 line.byte 0x00 "HC59,DSI HC Tile Configuration 59" group.byte 0x3C++0x00 line.byte 0x00 "HC60,DSI HC Tile Configuration 60" group.byte 0x3D++0x00 line.byte 0x00 "HC61,DSI HC Tile Configuration 61" group.byte 0x3E++0x00 line.byte 0x00 "HC62,DSI HC Tile Configuration 62" group.byte 0x3F++0x00 line.byte 0x00 "HC63,DSI HC Tile Configuration 63" group.byte 0x40++0x00 line.byte 0x00 "HC64,DSI HC Tile Configuration 64" group.byte 0x41++0x00 line.byte 0x00 "HC65,DSI HC Tile Configuration 65" group.byte 0x42++0x00 line.byte 0x00 "HC66,DSI HC Tile Configuration 66" group.byte 0x43++0x00 line.byte 0x00 "HC67,DSI HC Tile Configuration 67" group.byte 0x44++0x00 line.byte 0x00 "HC68,DSI HC Tile Configuration 68" group.byte 0x45++0x00 line.byte 0x00 "HC69,DSI HC Tile Configuration 69" group.byte 0x46++0x00 line.byte 0x00 "HC70,DSI HC Tile Configuration 70" group.byte 0x47++0x00 line.byte 0x00 "HC71,DSI HC Tile Configuration 71" group.byte 0x48++0x00 line.byte 0x00 "HC72,DSI HC Tile Configuration 72" group.byte 0x49++0x00 line.byte 0x00 "HC73,DSI HC Tile Configuration 73" group.byte 0x4A++0x00 line.byte 0x00 "HC74,DSI HC Tile Configuration 74" group.byte 0x4B++0x00 line.byte 0x00 "HC75,DSI HC Tile Configuration 75" group.byte 0x4C++0x00 line.byte 0x00 "HC76,DSI HC Tile Configuration 76" group.byte 0x4D++0x00 line.byte 0x00 "HC77,DSI HC Tile Configuration 77" group.byte 0x4E++0x00 line.byte 0x00 "HC78,DSI HC Tile Configuration 78" group.byte 0x4F++0x00 line.byte 0x00 "HC79,DSI HC Tile Configuration 79" group.byte 0x50++0x00 line.byte 0x00 "HC80,DSI HC Tile Configuration 80" group.byte 0x51++0x00 line.byte 0x00 "HC81,DSI HC Tile Configuration 81" group.byte 0x52++0x00 line.byte 0x00 "HC82,DSI HC Tile Configuration 82" group.byte 0x53++0x00 line.byte 0x00 "HC83,DSI HC Tile Configuration 83" group.byte 0x54++0x00 line.byte 0x00 "HC84,DSI HC Tile Configuration 84" group.byte 0x55++0x00 line.byte 0x00 "HC85,DSI HC Tile Configuration 85" group.byte 0x56++0x00 line.byte 0x00 "HC86,DSI HC Tile Configuration 86" group.byte 0x57++0x00 line.byte 0x00 "HC87,DSI HC Tile Configuration 87" group.byte 0x58++0x00 line.byte 0x00 "HC88,DSI HC Tile Configuration 88" group.byte 0x59++0x00 line.byte 0x00 "HC89,DSI HC Tile Configuration 89" group.byte 0x5A++0x00 line.byte 0x00 "HC90,DSI HC Tile Configuration 90" group.byte 0x5B++0x00 line.byte 0x00 "HC91,DSI HC Tile Configuration 91" group.byte 0x5C++0x00 line.byte 0x00 "HC92,DSI HC Tile Configuration 92" group.byte 0x5D++0x00 line.byte 0x00 "HC93,DSI HC Tile Configuration 93" group.byte 0x5E++0x00 line.byte 0x00 "HC94,DSI HC Tile Configuration 94" group.byte 0x5F++0x00 line.byte 0x00 "HC95,DSI HC Tile Configuration 95" group.byte 0x60++0x00 line.byte 0x00 "HC96,DSI HC Tile Configuration 96" group.byte 0x61++0x00 line.byte 0x00 "HC97,DSI HC Tile Configuration 97" group.byte 0x62++0x00 line.byte 0x00 "HC98,DSI HC Tile Configuration 98" group.byte 0x63++0x00 line.byte 0x00 "HC99,DSI HC Tile Configuration 99" group.byte 0x64++0x00 line.byte 0x00 "HC100,DSI HC Tile Configuration 100" group.byte 0x65++0x00 line.byte 0x00 "HC101,DSI HC Tile Configuration 101" group.byte 0x66++0x00 line.byte 0x00 "HC102,DSI HC Tile Configuration 102" group.byte 0x67++0x00 line.byte 0x00 "HC103,DSI HC Tile Configuration 103" group.byte 0x68++0x00 line.byte 0x00 "HC104,DSI HC Tile Configuration 104" group.byte 0x69++0x00 line.byte 0x00 "HC105,DSI HC Tile Configuration 105" group.byte 0x6A++0x00 line.byte 0x00 "HC106,DSI HC Tile Configuration 106" group.byte 0x6B++0x00 line.byte 0x00 "HC107,DSI HC Tile Configuration 107" group.byte 0x6C++0x00 line.byte 0x00 "HC108,DSI HC Tile Configuration 108" group.byte 0x6D++0x00 line.byte 0x00 "HC109,DSI HC Tile Configuration 109" group.byte 0x6E++0x00 line.byte 0x00 "HC110,DSI HC Tile Configuration 110" group.byte 0x6F++0x00 line.byte 0x00 "HC111,DSI HC Tile Configuration 111" group.byte 0x70++0x00 line.byte 0x00 "HC112,DSI HC Tile Configuration 112" group.byte 0x71++0x00 line.byte 0x00 "HC113,DSI HC Tile Configuration 113" group.byte 0x72++0x00 line.byte 0x00 "HC114,DSI HC Tile Configuration 114" group.byte 0x73++0x00 line.byte 0x00 "HC115,DSI HC Tile Configuration 115" group.byte 0x74++0x00 line.byte 0x00 "HC116,DSI HC Tile Configuration 116" group.byte 0x75++0x00 line.byte 0x00 "HC117,DSI HC Tile Configuration 117" group.byte 0x76++0x00 line.byte 0x00 "HC118,DSI HC Tile Configuration 118" group.byte 0x77++0x00 line.byte 0x00 "HC119,DSI HC Tile Configuration 119" group.byte 0x78++0x00 line.byte 0x00 "HC120,DSI HC Tile Configuration 120" group.byte 0x79++0x00 line.byte 0x00 "HC121,DSI HC Tile Configuration 121" group.byte 0x7A++0x00 line.byte 0x00 "HC122,DSI HC Tile Configuration 122" group.byte 0x7B++0x00 line.byte 0x00 "HC123,DSI HC Tile Configuration 123" group.byte 0x7C++0x00 line.byte 0x00 "HC124,DSI HC Tile Configuration 124" group.byte 0x7D++0x00 line.byte 0x00 "HC125,DSI HC Tile Configuration 125" group.byte 0x7E++0x00 line.byte 0x00 "HC126,DSI HC Tile Configuration 126" group.byte 0x7F++0x00 line.byte 0x00 "HC127,DSI HC Tile Configuration 127" group.byte 0x80++0x00 line.byte 0x00 "HV_L0,DSI HV Tile Configuration; Left 0" group.byte 0x81++0x00 line.byte 0x00 "HV_L1,DSI HV Tile Configuration; Left 1" group.byte 0x82++0x00 line.byte 0x00 "HV_L2,DSI HV Tile Configuration; Left 2" group.byte 0x83++0x00 line.byte 0x00 "HV_L3,DSI HV Tile Configuration; Left 3" group.byte 0x84++0x00 line.byte 0x00 "HV_L4,DSI HV Tile Configuration; Left 4" group.byte 0x85++0x00 line.byte 0x00 "HV_L5,DSI HV Tile Configuration; Left 5" group.byte 0x86++0x00 line.byte 0x00 "HV_L6,DSI HV Tile Configuration; Left 6" group.byte 0x87++0x00 line.byte 0x00 "HV_L7,DSI HV Tile Configuration; Left 7" group.byte 0x88++0x00 line.byte 0x00 "HV_L8,DSI HV Tile Configuration; Left 8" group.byte 0x89++0x00 line.byte 0x00 "HV_L9,DSI HV Tile Configuration; Left 9" group.byte 0x8A++0x00 line.byte 0x00 "HV_L10,DSI HV Tile Configuration; Left 10" group.byte 0x8B++0x00 line.byte 0x00 "HV_L11,DSI HV Tile Configuration; Left 11" group.byte 0x8C++0x00 line.byte 0x00 "HV_L12,DSI HV Tile Configuration; Left 12" group.byte 0x8D++0x00 line.byte 0x00 "HV_L13,DSI HV Tile Configuration; Left 13" group.byte 0x8E++0x00 line.byte 0x00 "HV_L14,DSI HV Tile Configuration; Left 14" group.byte 0x8F++0x00 line.byte 0x00 "HV_L15,DSI HV Tile Configuration; Left 15" group.byte 0x90++0x00 line.byte 0x00 "HS0,DSI HS Tile Configuration; Horizontal Segmentation 0" group.byte 0x91++0x00 line.byte 0x00 "HS1,DSI HS Tile Configuration; Horizontal Segmentation 1" group.byte 0x92++0x00 line.byte 0x00 "HS2,DSI HS Tile Configuration; Horizontal Segmentation 2" group.byte 0x93++0x00 line.byte 0x00 "HS3,DSI HS Tile Configuration; Horizontal Segmentation 3" group.byte 0x94++0x00 line.byte 0x00 "HS4,DSI HS Tile Configuration; Horizontal Segmentation 4" group.byte 0x95++0x00 line.byte 0x00 "HS5,DSI HS Tile Configuration; Horizontal Segmentation 5" group.byte 0x96++0x00 line.byte 0x00 "HS6,DSI HS Tile Configuration; Horizontal Segmentation 6" group.byte 0x97++0x00 line.byte 0x00 "HS7,DSI HS Tile Configuration; Horizontal Segmentation 7" group.byte 0x98++0x00 line.byte 0x00 "HS8,DSI HS Tile Configuration; Horizontal Segmentation 8" group.byte 0x99++0x00 line.byte 0x00 "HS9,DSI HS Tile Configuration; Horizontal Segmentation 9" group.byte 0x9A++0x00 line.byte 0x00 "HS10,DSI HS Tile Configuration; Horizontal Segmentation 10" group.byte 0x9B++0x00 line.byte 0x00 "HS11,DSI HS Tile Configuration; Horizontal Segmentation 11" group.byte 0x9C++0x00 line.byte 0x00 "HS12,DSI HS Tile Configuration; Horizontal Segmentation 12" group.byte 0x9D++0x00 line.byte 0x00 "HS13,DSI HS Tile Configuration; Horizontal Segmentation 13" group.byte 0x9E++0x00 line.byte 0x00 "HS14,DSI HS Tile Configuration; Horizontal Segmentation 14" group.byte 0x9F++0x00 line.byte 0x00 "HS15,DSI HS Tile Configuration; Horizontal Segmentation 15" group.byte 0xA0++0x00 line.byte 0x00 "HS16,DSI HS Tile Configuration; Horizontal Segmentation 16" group.byte 0xA1++0x00 line.byte 0x00 "HS17,DSI HS Tile Configuration; Horizontal Segmentation 17" group.byte 0xA2++0x00 line.byte 0x00 "HS18,DSI HS Tile Configuration; Horizontal Segmentation 18" group.byte 0xA3++0x00 line.byte 0x00 "HS19,DSI HS Tile Configuration; Horizontal Segmentation 19" group.byte 0xA4++0x00 line.byte 0x00 "HS20,DSI HS Tile Configuration; Horizontal Segmentation 20" group.byte 0xA5++0x00 line.byte 0x00 "HS21,DSI HS Tile Configuration; Horizontal Segmentation 21" group.byte 0xA6++0x00 line.byte 0x00 "HS22,DSI HS Tile Configuration; Horizontal Segmentation 22" group.byte 0xA7++0x00 line.byte 0x00 "HS23,DSI HS Tile Configuration; Horizontal Segmentation 23" group.byte 0xA8++0x00 line.byte 0x00 "HV_R0,DSI HV Tile Configuration; Right 0" group.byte 0xA9++0x00 line.byte 0x00 "HV_R1,DSI HV Tile Configuration; Right 1" group.byte 0xAA++0x00 line.byte 0x00 "HV_R2,DSI HV Tile Configuration; Right 2" group.byte 0xAB++0x00 line.byte 0x00 "HV_R3,DSI HV Tile Configuration; Right 3" group.byte 0xAC++0x00 line.byte 0x00 "HV_R4,DSI HV Tile Configuration; Right 4" group.byte 0xAD++0x00 line.byte 0x00 "HV_R5,DSI HV Tile Configuration; Right 5" group.byte 0xAE++0x00 line.byte 0x00 "HV_R6,DSI HV Tile Configuration; Right 6" group.byte 0xAF++0x00 line.byte 0x00 "HV_R7,DSI HV Tile Configuration; Right 7" group.byte 0xB0++0x00 line.byte 0x00 "HV_R8,DSI HV Tile Configuration; Right 8" group.byte 0xB1++0x00 line.byte 0x00 "HV_R9,DSI HV Tile Configuration; Right 9" group.byte 0xB2++0x00 line.byte 0x00 "HV_R10,DSI HV Tile Configuration; Right 10" group.byte 0xB3++0x00 line.byte 0x00 "HV_R11,DSI HV Tile Configuration; Right 11" group.byte 0xB4++0x00 line.byte 0x00 "HV_R12,DSI HV Tile Configuration; Right 12" group.byte 0xB5++0x00 line.byte 0x00 "HV_R13,DSI HV Tile Configuration; Right 13" group.byte 0xB6++0x00 line.byte 0x00 "HV_R14,DSI HV Tile Configuration; Right 14" group.byte 0xB7++0x00 line.byte 0x00 "HV_R15,DSI HV Tile Configuration; Right 15" group.word 0xC0++0x01 line.word 0x00 "DSIINP0,DSI PI Tile Configuration For DSI I/O; Input 0" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xC2++0x01 line.word 0x00 "DSIINP1,DSI PI Tile Configuration For DSI I/O; Input 1" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xC4++0x01 line.word 0x00 "DSIINP2,DSI PI Tile Configuration For DSI I/O; Input 2" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xC6++0x01 line.word 0x00 "DSIINP3,DSI PI Tile Configuration For DSI I/O; Input 3" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xC8++0x01 line.word 0x00 "DSIINP4,DSI PI Tile Configuration For DSI I/O; Input 4" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xCA++0x01 line.word 0x00 "DSIINP5,DSI PI Tile Configuration For DSI I/O; Input 5" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xCC++0x01 line.word 0x00 "DSIOUTP0,DSI PI Tile Configuration For DSI I/O; Output Pair 0" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xCE++0x01 line.word 0x00 "DSIOUTP1,DSI PI Tile Configuration For DSI I/O; Output Pair 1" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xD0++0x01 line.word 0x00 "DSIOUTP2,DSI PI Tile Configuration For DSI I/O; Output Pair 2" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xD2++0x01 line.word 0x00 "DSIOUTP3,DSI PI Tile Configuration For DSI I/O; Output Pair 3" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xD4++0x01 line.word 0x00 "DSIOUTT0,DSI PI Tile Configuration For DSI I/O; Output Triplet 0" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xD6++0x01 line.word 0x00 "DSIOUTT1,DSI PI Tile Configuration For DSI I/O; Output Triplet 1" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xD8++0x01 line.word 0x00 "DSIOUTT2,DSI PI Tile Configuration For DSI I/O; Output Triplet 2" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xDA++0x01 line.word 0x00 "DSIOUTT3,DSI PI Tile Configuration For DSI I/O; Output Triplet 3" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xDC++0x01 line.word 0x00 "DSIOUTT4,DSI PI Tile Configuration For DSI I/O; Output Triplet 4" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xDE++0x01 line.word 0x00 "DSIOUTT5,DSI PI Tile Configuration For DSI I/O; Output Triplet 5" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE0++0x01 line.word 0x00 "VS0,DSI VS Tile Configuration; Vertical Segmentation 0" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE2++0x01 line.word 0x00 "VS1,DSI VS Tile Configuration; Vertical Segmentation 1" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE4++0x01 line.word 0x00 "VS2,DSI VS Tile Configuration; Vertical Segmentation 2" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE6++0x01 line.word 0x00 "VS3,DSI VS Tile Configuration; Vertical Segmentation 3" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE8++0x01 line.word 0x00 "VS4,DSI VS Tile Configuration; Vertical Segmentation 4" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xEA++0x01 line.word 0x00 "VS5,DSI VS Tile Configuration; Vertical Segmentation 5" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xEC++0x01 line.word 0x00 "VS6,DSI VS Tile Configuration; Vertical Segmentation 6" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xEE++0x01 line.word 0x00 "VS7,DSI VS Tile Configuration; Vertical Segmentation 7" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree "UDB_DSI1" base ad:0x400F4100 width 15. group.byte 0x0++0x00 line.byte 0x00 "HC0,DSI HC Tile Configuration 0" group.byte 0x1++0x00 line.byte 0x00 "HC1,DSI HC Tile Configuration 1" group.byte 0x2++0x00 line.byte 0x00 "HC2,DSI HC Tile Configuration 2" group.byte 0x3++0x00 line.byte 0x00 "HC3,DSI HC Tile Configuration 3" group.byte 0x4++0x00 line.byte 0x00 "HC4,DSI HC Tile Configuration 4" group.byte 0x5++0x00 line.byte 0x00 "HC5,DSI HC Tile Configuration 5" group.byte 0x6++0x00 line.byte 0x00 "HC6,DSI HC Tile Configuration 6" group.byte 0x7++0x00 line.byte 0x00 "HC7,DSI HC Tile Configuration 7" group.byte 0x8++0x00 line.byte 0x00 "HC8,DSI HC Tile Configuration 8" group.byte 0x9++0x00 line.byte 0x00 "HC9,DSI HC Tile Configuration 9" group.byte 0xA++0x00 line.byte 0x00 "HC10,DSI HC Tile Configuration 10" group.byte 0xB++0x00 line.byte 0x00 "HC11,DSI HC Tile Configuration 11" group.byte 0xC++0x00 line.byte 0x00 "HC12,DSI HC Tile Configuration 12" group.byte 0xD++0x00 line.byte 0x00 "HC13,DSI HC Tile Configuration 13" group.byte 0xE++0x00 line.byte 0x00 "HC14,DSI HC Tile Configuration 14" group.byte 0xF++0x00 line.byte 0x00 "HC15,DSI HC Tile Configuration 15" group.byte 0x10++0x00 line.byte 0x00 "HC16,DSI HC Tile Configuration 16" group.byte 0x11++0x00 line.byte 0x00 "HC17,DSI HC Tile Configuration 17" group.byte 0x12++0x00 line.byte 0x00 "HC18,DSI HC Tile Configuration 18" group.byte 0x13++0x00 line.byte 0x00 "HC19,DSI HC Tile Configuration 19" group.byte 0x14++0x00 line.byte 0x00 "HC20,DSI HC Tile Configuration 20" group.byte 0x15++0x00 line.byte 0x00 "HC21,DSI HC Tile Configuration 21" group.byte 0x16++0x00 line.byte 0x00 "HC22,DSI HC Tile Configuration 22" group.byte 0x17++0x00 line.byte 0x00 "HC23,DSI HC Tile Configuration 23" group.byte 0x18++0x00 line.byte 0x00 "HC24,DSI HC Tile Configuration 24" group.byte 0x19++0x00 line.byte 0x00 "HC25,DSI HC Tile Configuration 25" group.byte 0x1A++0x00 line.byte 0x00 "HC26,DSI HC Tile Configuration 26" group.byte 0x1B++0x00 line.byte 0x00 "HC27,DSI HC Tile Configuration 27" group.byte 0x1C++0x00 line.byte 0x00 "HC28,DSI HC Tile Configuration 28" group.byte 0x1D++0x00 line.byte 0x00 "HC29,DSI HC Tile Configuration 29" group.byte 0x1E++0x00 line.byte 0x00 "HC30,DSI HC Tile Configuration 30" group.byte 0x1F++0x00 line.byte 0x00 "HC31,DSI HC Tile Configuration 31" group.byte 0x20++0x00 line.byte 0x00 "HC32,DSI HC Tile Configuration 32" group.byte 0x21++0x00 line.byte 0x00 "HC33,DSI HC Tile Configuration 33" group.byte 0x22++0x00 line.byte 0x00 "HC34,DSI HC Tile Configuration 34" group.byte 0x23++0x00 line.byte 0x00 "HC35,DSI HC Tile Configuration 35" group.byte 0x24++0x00 line.byte 0x00 "HC36,DSI HC Tile Configuration 36" group.byte 0x25++0x00 line.byte 0x00 "HC37,DSI HC Tile Configuration 37" group.byte 0x26++0x00 line.byte 0x00 "HC38,DSI HC Tile Configuration 38" group.byte 0x27++0x00 line.byte 0x00 "HC39,DSI HC Tile Configuration 39" group.byte 0x28++0x00 line.byte 0x00 "HC40,DSI HC Tile Configuration 40" group.byte 0x29++0x00 line.byte 0x00 "HC41,DSI HC Tile Configuration 41" group.byte 0x2A++0x00 line.byte 0x00 "HC42,DSI HC Tile Configuration 42" group.byte 0x2B++0x00 line.byte 0x00 "HC43,DSI HC Tile Configuration 43" group.byte 0x2C++0x00 line.byte 0x00 "HC44,DSI HC Tile Configuration 44" group.byte 0x2D++0x00 line.byte 0x00 "HC45,DSI HC Tile Configuration 45" group.byte 0x2E++0x00 line.byte 0x00 "HC46,DSI HC Tile Configuration 46" group.byte 0x2F++0x00 line.byte 0x00 "HC47,DSI HC Tile Configuration 47" group.byte 0x30++0x00 line.byte 0x00 "HC48,DSI HC Tile Configuration 48" group.byte 0x31++0x00 line.byte 0x00 "HC49,DSI HC Tile Configuration 49" group.byte 0x32++0x00 line.byte 0x00 "HC50,DSI HC Tile Configuration 50" group.byte 0x33++0x00 line.byte 0x00 "HC51,DSI HC Tile Configuration 51" group.byte 0x34++0x00 line.byte 0x00 "HC52,DSI HC Tile Configuration 52" group.byte 0x35++0x00 line.byte 0x00 "HC53,DSI HC Tile Configuration 53" group.byte 0x36++0x00 line.byte 0x00 "HC54,DSI HC Tile Configuration 54" group.byte 0x37++0x00 line.byte 0x00 "HC55,DSI HC Tile Configuration 55" group.byte 0x38++0x00 line.byte 0x00 "HC56,DSI HC Tile Configuration 56" group.byte 0x39++0x00 line.byte 0x00 "HC57,DSI HC Tile Configuration 57" group.byte 0x3A++0x00 line.byte 0x00 "HC58,DSI HC Tile Configuration 58" group.byte 0x3B++0x00 line.byte 0x00 "HC59,DSI HC Tile Configuration 59" group.byte 0x3C++0x00 line.byte 0x00 "HC60,DSI HC Tile Configuration 60" group.byte 0x3D++0x00 line.byte 0x00 "HC61,DSI HC Tile Configuration 61" group.byte 0x3E++0x00 line.byte 0x00 "HC62,DSI HC Tile Configuration 62" group.byte 0x3F++0x00 line.byte 0x00 "HC63,DSI HC Tile Configuration 63" group.byte 0x40++0x00 line.byte 0x00 "HC64,DSI HC Tile Configuration 64" group.byte 0x41++0x00 line.byte 0x00 "HC65,DSI HC Tile Configuration 65" group.byte 0x42++0x00 line.byte 0x00 "HC66,DSI HC Tile Configuration 66" group.byte 0x43++0x00 line.byte 0x00 "HC67,DSI HC Tile Configuration 67" group.byte 0x44++0x00 line.byte 0x00 "HC68,DSI HC Tile Configuration 68" group.byte 0x45++0x00 line.byte 0x00 "HC69,DSI HC Tile Configuration 69" group.byte 0x46++0x00 line.byte 0x00 "HC70,DSI HC Tile Configuration 70" group.byte 0x47++0x00 line.byte 0x00 "HC71,DSI HC Tile Configuration 71" group.byte 0x48++0x00 line.byte 0x00 "HC72,DSI HC Tile Configuration 72" group.byte 0x49++0x00 line.byte 0x00 "HC73,DSI HC Tile Configuration 73" group.byte 0x4A++0x00 line.byte 0x00 "HC74,DSI HC Tile Configuration 74" group.byte 0x4B++0x00 line.byte 0x00 "HC75,DSI HC Tile Configuration 75" group.byte 0x4C++0x00 line.byte 0x00 "HC76,DSI HC Tile Configuration 76" group.byte 0x4D++0x00 line.byte 0x00 "HC77,DSI HC Tile Configuration 77" group.byte 0x4E++0x00 line.byte 0x00 "HC78,DSI HC Tile Configuration 78" group.byte 0x4F++0x00 line.byte 0x00 "HC79,DSI HC Tile Configuration 79" group.byte 0x50++0x00 line.byte 0x00 "HC80,DSI HC Tile Configuration 80" group.byte 0x51++0x00 line.byte 0x00 "HC81,DSI HC Tile Configuration 81" group.byte 0x52++0x00 line.byte 0x00 "HC82,DSI HC Tile Configuration 82" group.byte 0x53++0x00 line.byte 0x00 "HC83,DSI HC Tile Configuration 83" group.byte 0x54++0x00 line.byte 0x00 "HC84,DSI HC Tile Configuration 84" group.byte 0x55++0x00 line.byte 0x00 "HC85,DSI HC Tile Configuration 85" group.byte 0x56++0x00 line.byte 0x00 "HC86,DSI HC Tile Configuration 86" group.byte 0x57++0x00 line.byte 0x00 "HC87,DSI HC Tile Configuration 87" group.byte 0x58++0x00 line.byte 0x00 "HC88,DSI HC Tile Configuration 88" group.byte 0x59++0x00 line.byte 0x00 "HC89,DSI HC Tile Configuration 89" group.byte 0x5A++0x00 line.byte 0x00 "HC90,DSI HC Tile Configuration 90" group.byte 0x5B++0x00 line.byte 0x00 "HC91,DSI HC Tile Configuration 91" group.byte 0x5C++0x00 line.byte 0x00 "HC92,DSI HC Tile Configuration 92" group.byte 0x5D++0x00 line.byte 0x00 "HC93,DSI HC Tile Configuration 93" group.byte 0x5E++0x00 line.byte 0x00 "HC94,DSI HC Tile Configuration 94" group.byte 0x5F++0x00 line.byte 0x00 "HC95,DSI HC Tile Configuration 95" group.byte 0x60++0x00 line.byte 0x00 "HC96,DSI HC Tile Configuration 96" group.byte 0x61++0x00 line.byte 0x00 "HC97,DSI HC Tile Configuration 97" group.byte 0x62++0x00 line.byte 0x00 "HC98,DSI HC Tile Configuration 98" group.byte 0x63++0x00 line.byte 0x00 "HC99,DSI HC Tile Configuration 99" group.byte 0x64++0x00 line.byte 0x00 "HC100,DSI HC Tile Configuration 100" group.byte 0x65++0x00 line.byte 0x00 "HC101,DSI HC Tile Configuration 101" group.byte 0x66++0x00 line.byte 0x00 "HC102,DSI HC Tile Configuration 102" group.byte 0x67++0x00 line.byte 0x00 "HC103,DSI HC Tile Configuration 103" group.byte 0x68++0x00 line.byte 0x00 "HC104,DSI HC Tile Configuration 104" group.byte 0x69++0x00 line.byte 0x00 "HC105,DSI HC Tile Configuration 105" group.byte 0x6A++0x00 line.byte 0x00 "HC106,DSI HC Tile Configuration 106" group.byte 0x6B++0x00 line.byte 0x00 "HC107,DSI HC Tile Configuration 107" group.byte 0x6C++0x00 line.byte 0x00 "HC108,DSI HC Tile Configuration 108" group.byte 0x6D++0x00 line.byte 0x00 "HC109,DSI HC Tile Configuration 109" group.byte 0x6E++0x00 line.byte 0x00 "HC110,DSI HC Tile Configuration 110" group.byte 0x6F++0x00 line.byte 0x00 "HC111,DSI HC Tile Configuration 111" group.byte 0x70++0x00 line.byte 0x00 "HC112,DSI HC Tile Configuration 112" group.byte 0x71++0x00 line.byte 0x00 "HC113,DSI HC Tile Configuration 113" group.byte 0x72++0x00 line.byte 0x00 "HC114,DSI HC Tile Configuration 114" group.byte 0x73++0x00 line.byte 0x00 "HC115,DSI HC Tile Configuration 115" group.byte 0x74++0x00 line.byte 0x00 "HC116,DSI HC Tile Configuration 116" group.byte 0x75++0x00 line.byte 0x00 "HC117,DSI HC Tile Configuration 117" group.byte 0x76++0x00 line.byte 0x00 "HC118,DSI HC Tile Configuration 118" group.byte 0x77++0x00 line.byte 0x00 "HC119,DSI HC Tile Configuration 119" group.byte 0x78++0x00 line.byte 0x00 "HC120,DSI HC Tile Configuration 120" group.byte 0x79++0x00 line.byte 0x00 "HC121,DSI HC Tile Configuration 121" group.byte 0x7A++0x00 line.byte 0x00 "HC122,DSI HC Tile Configuration 122" group.byte 0x7B++0x00 line.byte 0x00 "HC123,DSI HC Tile Configuration 123" group.byte 0x7C++0x00 line.byte 0x00 "HC124,DSI HC Tile Configuration 124" group.byte 0x7D++0x00 line.byte 0x00 "HC125,DSI HC Tile Configuration 125" group.byte 0x7E++0x00 line.byte 0x00 "HC126,DSI HC Tile Configuration 126" group.byte 0x7F++0x00 line.byte 0x00 "HC127,DSI HC Tile Configuration 127" group.byte 0x80++0x00 line.byte 0x00 "HV_L0,DSI HV Tile Configuration; Left 0" group.byte 0x81++0x00 line.byte 0x00 "HV_L1,DSI HV Tile Configuration; Left 1" group.byte 0x82++0x00 line.byte 0x00 "HV_L2,DSI HV Tile Configuration; Left 2" group.byte 0x83++0x00 line.byte 0x00 "HV_L3,DSI HV Tile Configuration; Left 3" group.byte 0x84++0x00 line.byte 0x00 "HV_L4,DSI HV Tile Configuration; Left 4" group.byte 0x85++0x00 line.byte 0x00 "HV_L5,DSI HV Tile Configuration; Left 5" group.byte 0x86++0x00 line.byte 0x00 "HV_L6,DSI HV Tile Configuration; Left 6" group.byte 0x87++0x00 line.byte 0x00 "HV_L7,DSI HV Tile Configuration; Left 7" group.byte 0x88++0x00 line.byte 0x00 "HV_L8,DSI HV Tile Configuration; Left 8" group.byte 0x89++0x00 line.byte 0x00 "HV_L9,DSI HV Tile Configuration; Left 9" group.byte 0x8A++0x00 line.byte 0x00 "HV_L10,DSI HV Tile Configuration; Left 10" group.byte 0x8B++0x00 line.byte 0x00 "HV_L11,DSI HV Tile Configuration; Left 11" group.byte 0x8C++0x00 line.byte 0x00 "HV_L12,DSI HV Tile Configuration; Left 12" group.byte 0x8D++0x00 line.byte 0x00 "HV_L13,DSI HV Tile Configuration; Left 13" group.byte 0x8E++0x00 line.byte 0x00 "HV_L14,DSI HV Tile Configuration; Left 14" group.byte 0x8F++0x00 line.byte 0x00 "HV_L15,DSI HV Tile Configuration; Left 15" group.byte 0x90++0x00 line.byte 0x00 "HS0,DSI HS Tile Configuration; Horizontal Segmentation 0" group.byte 0x91++0x00 line.byte 0x00 "HS1,DSI HS Tile Configuration; Horizontal Segmentation 1" group.byte 0x92++0x00 line.byte 0x00 "HS2,DSI HS Tile Configuration; Horizontal Segmentation 2" group.byte 0x93++0x00 line.byte 0x00 "HS3,DSI HS Tile Configuration; Horizontal Segmentation 3" group.byte 0x94++0x00 line.byte 0x00 "HS4,DSI HS Tile Configuration; Horizontal Segmentation 4" group.byte 0x95++0x00 line.byte 0x00 "HS5,DSI HS Tile Configuration; Horizontal Segmentation 5" group.byte 0x96++0x00 line.byte 0x00 "HS6,DSI HS Tile Configuration; Horizontal Segmentation 6" group.byte 0x97++0x00 line.byte 0x00 "HS7,DSI HS Tile Configuration; Horizontal Segmentation 7" group.byte 0x98++0x00 line.byte 0x00 "HS8,DSI HS Tile Configuration; Horizontal Segmentation 8" group.byte 0x99++0x00 line.byte 0x00 "HS9,DSI HS Tile Configuration; Horizontal Segmentation 9" group.byte 0x9A++0x00 line.byte 0x00 "HS10,DSI HS Tile Configuration; Horizontal Segmentation 10" group.byte 0x9B++0x00 line.byte 0x00 "HS11,DSI HS Tile Configuration; Horizontal Segmentation 11" group.byte 0x9C++0x00 line.byte 0x00 "HS12,DSI HS Tile Configuration; Horizontal Segmentation 12" group.byte 0x9D++0x00 line.byte 0x00 "HS13,DSI HS Tile Configuration; Horizontal Segmentation 13" group.byte 0x9E++0x00 line.byte 0x00 "HS14,DSI HS Tile Configuration; Horizontal Segmentation 14" group.byte 0x9F++0x00 line.byte 0x00 "HS15,DSI HS Tile Configuration; Horizontal Segmentation 15" group.byte 0xA0++0x00 line.byte 0x00 "HS16,DSI HS Tile Configuration; Horizontal Segmentation 16" group.byte 0xA1++0x00 line.byte 0x00 "HS17,DSI HS Tile Configuration; Horizontal Segmentation 17" group.byte 0xA2++0x00 line.byte 0x00 "HS18,DSI HS Tile Configuration; Horizontal Segmentation 18" group.byte 0xA3++0x00 line.byte 0x00 "HS19,DSI HS Tile Configuration; Horizontal Segmentation 19" group.byte 0xA4++0x00 line.byte 0x00 "HS20,DSI HS Tile Configuration; Horizontal Segmentation 20" group.byte 0xA5++0x00 line.byte 0x00 "HS21,DSI HS Tile Configuration; Horizontal Segmentation 21" group.byte 0xA6++0x00 line.byte 0x00 "HS22,DSI HS Tile Configuration; Horizontal Segmentation 22" group.byte 0xA7++0x00 line.byte 0x00 "HS23,DSI HS Tile Configuration; Horizontal Segmentation 23" group.byte 0xA8++0x00 line.byte 0x00 "HV_R0,DSI HV Tile Configuration; Right 0" group.byte 0xA9++0x00 line.byte 0x00 "HV_R1,DSI HV Tile Configuration; Right 1" group.byte 0xAA++0x00 line.byte 0x00 "HV_R2,DSI HV Tile Configuration; Right 2" group.byte 0xAB++0x00 line.byte 0x00 "HV_R3,DSI HV Tile Configuration; Right 3" group.byte 0xAC++0x00 line.byte 0x00 "HV_R4,DSI HV Tile Configuration; Right 4" group.byte 0xAD++0x00 line.byte 0x00 "HV_R5,DSI HV Tile Configuration; Right 5" group.byte 0xAE++0x00 line.byte 0x00 "HV_R6,DSI HV Tile Configuration; Right 6" group.byte 0xAF++0x00 line.byte 0x00 "HV_R7,DSI HV Tile Configuration; Right 7" group.byte 0xB0++0x00 line.byte 0x00 "HV_R8,DSI HV Tile Configuration; Right 8" group.byte 0xB1++0x00 line.byte 0x00 "HV_R9,DSI HV Tile Configuration; Right 9" group.byte 0xB2++0x00 line.byte 0x00 "HV_R10,DSI HV Tile Configuration; Right 10" group.byte 0xB3++0x00 line.byte 0x00 "HV_R11,DSI HV Tile Configuration; Right 11" group.byte 0xB4++0x00 line.byte 0x00 "HV_R12,DSI HV Tile Configuration; Right 12" group.byte 0xB5++0x00 line.byte 0x00 "HV_R13,DSI HV Tile Configuration; Right 13" group.byte 0xB6++0x00 line.byte 0x00 "HV_R14,DSI HV Tile Configuration; Right 14" group.byte 0xB7++0x00 line.byte 0x00 "HV_R15,DSI HV Tile Configuration; Right 15" group.word 0xC0++0x01 line.word 0x00 "DSIINP0,DSI PI Tile Configuration For DSI I/O; Input 0" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xC2++0x01 line.word 0x00 "DSIINP1,DSI PI Tile Configuration For DSI I/O; Input 1" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xC4++0x01 line.word 0x00 "DSIINP2,DSI PI Tile Configuration For DSI I/O; Input 2" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xC6++0x01 line.word 0x00 "DSIINP3,DSI PI Tile Configuration For DSI I/O; Input 3" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xC8++0x01 line.word 0x00 "DSIINP4,DSI PI Tile Configuration For DSI I/O; Input 4" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xCA++0x01 line.word 0x00 "DSIINP5,DSI PI Tile Configuration For DSI I/O; Input 5" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xCC++0x01 line.word 0x00 "DSIOUTP0,DSI PI Tile Configuration For DSI I/O; Output Pair 0" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xCE++0x01 line.word 0x00 "DSIOUTP1,DSI PI Tile Configuration For DSI I/O; Output Pair 1" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xD0++0x01 line.word 0x00 "DSIOUTP2,DSI PI Tile Configuration For DSI I/O; Output Pair 2" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xD2++0x01 line.word 0x00 "DSIOUTP3,DSI PI Tile Configuration For DSI I/O; Output Pair 3" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xD4++0x01 line.word 0x00 "DSIOUTT0,DSI PI Tile Configuration For DSI I/O; Output Triplet 0" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xD6++0x01 line.word 0x00 "DSIOUTT1,DSI PI Tile Configuration For DSI I/O; Output Triplet 1" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xD8++0x01 line.word 0x00 "DSIOUTT2,DSI PI Tile Configuration For DSI I/O; Output Triplet 2" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xDA++0x01 line.word 0x00 "DSIOUTT3,DSI PI Tile Configuration For DSI I/O; Output Triplet 3" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xDC++0x01 line.word 0x00 "DSIOUTT4,DSI PI Tile Configuration For DSI I/O; Output Triplet 4" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xDE++0x01 line.word 0x00 "DSIOUTT5,DSI PI Tile Configuration For DSI I/O; Output Triplet 5" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE0++0x01 line.word 0x00 "VS0,DSI VS Tile Configuration; Vertical Segmentation 0" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE2++0x01 line.word 0x00 "VS1,DSI VS Tile Configuration; Vertical Segmentation 1" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE4++0x01 line.word 0x00 "VS2,DSI VS Tile Configuration; Vertical Segmentation 2" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE6++0x01 line.word 0x00 "VS3,DSI VS Tile Configuration; Vertical Segmentation 3" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE8++0x01 line.word 0x00 "VS4,DSI VS Tile Configuration; Vertical Segmentation 4" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xEA++0x01 line.word 0x00 "VS5,DSI VS Tile Configuration; Vertical Segmentation 5" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xEC++0x01 line.word 0x00 "VS6,DSI VS Tile Configuration; Vertical Segmentation 6" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xEE++0x01 line.word 0x00 "VS7,DSI VS Tile Configuration; Vertical Segmentation 7" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree "UDB_DSI2" base ad:0x400F4200 width 15. group.byte 0x0++0x00 line.byte 0x00 "HC0,DSI HC Tile Configuration 0" group.byte 0x1++0x00 line.byte 0x00 "HC1,DSI HC Tile Configuration 1" group.byte 0x2++0x00 line.byte 0x00 "HC2,DSI HC Tile Configuration 2" group.byte 0x3++0x00 line.byte 0x00 "HC3,DSI HC Tile Configuration 3" group.byte 0x4++0x00 line.byte 0x00 "HC4,DSI HC Tile Configuration 4" group.byte 0x5++0x00 line.byte 0x00 "HC5,DSI HC Tile Configuration 5" group.byte 0x6++0x00 line.byte 0x00 "HC6,DSI HC Tile Configuration 6" group.byte 0x7++0x00 line.byte 0x00 "HC7,DSI HC Tile Configuration 7" group.byte 0x8++0x00 line.byte 0x00 "HC8,DSI HC Tile Configuration 8" group.byte 0x9++0x00 line.byte 0x00 "HC9,DSI HC Tile Configuration 9" group.byte 0xA++0x00 line.byte 0x00 "HC10,DSI HC Tile Configuration 10" group.byte 0xB++0x00 line.byte 0x00 "HC11,DSI HC Tile Configuration 11" group.byte 0xC++0x00 line.byte 0x00 "HC12,DSI HC Tile Configuration 12" group.byte 0xD++0x00 line.byte 0x00 "HC13,DSI HC Tile Configuration 13" group.byte 0xE++0x00 line.byte 0x00 "HC14,DSI HC Tile Configuration 14" group.byte 0xF++0x00 line.byte 0x00 "HC15,DSI HC Tile Configuration 15" group.byte 0x10++0x00 line.byte 0x00 "HC16,DSI HC Tile Configuration 16" group.byte 0x11++0x00 line.byte 0x00 "HC17,DSI HC Tile Configuration 17" group.byte 0x12++0x00 line.byte 0x00 "HC18,DSI HC Tile Configuration 18" group.byte 0x13++0x00 line.byte 0x00 "HC19,DSI HC Tile Configuration 19" group.byte 0x14++0x00 line.byte 0x00 "HC20,DSI HC Tile Configuration 20" group.byte 0x15++0x00 line.byte 0x00 "HC21,DSI HC Tile Configuration 21" group.byte 0x16++0x00 line.byte 0x00 "HC22,DSI HC Tile Configuration 22" group.byte 0x17++0x00 line.byte 0x00 "HC23,DSI HC Tile Configuration 23" group.byte 0x18++0x00 line.byte 0x00 "HC24,DSI HC Tile Configuration 24" group.byte 0x19++0x00 line.byte 0x00 "HC25,DSI HC Tile Configuration 25" group.byte 0x1A++0x00 line.byte 0x00 "HC26,DSI HC Tile Configuration 26" group.byte 0x1B++0x00 line.byte 0x00 "HC27,DSI HC Tile Configuration 27" group.byte 0x1C++0x00 line.byte 0x00 "HC28,DSI HC Tile Configuration 28" group.byte 0x1D++0x00 line.byte 0x00 "HC29,DSI HC Tile Configuration 29" group.byte 0x1E++0x00 line.byte 0x00 "HC30,DSI HC Tile Configuration 30" group.byte 0x1F++0x00 line.byte 0x00 "HC31,DSI HC Tile Configuration 31" group.byte 0x20++0x00 line.byte 0x00 "HC32,DSI HC Tile Configuration 32" group.byte 0x21++0x00 line.byte 0x00 "HC33,DSI HC Tile Configuration 33" group.byte 0x22++0x00 line.byte 0x00 "HC34,DSI HC Tile Configuration 34" group.byte 0x23++0x00 line.byte 0x00 "HC35,DSI HC Tile Configuration 35" group.byte 0x24++0x00 line.byte 0x00 "HC36,DSI HC Tile Configuration 36" group.byte 0x25++0x00 line.byte 0x00 "HC37,DSI HC Tile Configuration 37" group.byte 0x26++0x00 line.byte 0x00 "HC38,DSI HC Tile Configuration 38" group.byte 0x27++0x00 line.byte 0x00 "HC39,DSI HC Tile Configuration 39" group.byte 0x28++0x00 line.byte 0x00 "HC40,DSI HC Tile Configuration 40" group.byte 0x29++0x00 line.byte 0x00 "HC41,DSI HC Tile Configuration 41" group.byte 0x2A++0x00 line.byte 0x00 "HC42,DSI HC Tile Configuration 42" group.byte 0x2B++0x00 line.byte 0x00 "HC43,DSI HC Tile Configuration 43" group.byte 0x2C++0x00 line.byte 0x00 "HC44,DSI HC Tile Configuration 44" group.byte 0x2D++0x00 line.byte 0x00 "HC45,DSI HC Tile Configuration 45" group.byte 0x2E++0x00 line.byte 0x00 "HC46,DSI HC Tile Configuration 46" group.byte 0x2F++0x00 line.byte 0x00 "HC47,DSI HC Tile Configuration 47" group.byte 0x30++0x00 line.byte 0x00 "HC48,DSI HC Tile Configuration 48" group.byte 0x31++0x00 line.byte 0x00 "HC49,DSI HC Tile Configuration 49" group.byte 0x32++0x00 line.byte 0x00 "HC50,DSI HC Tile Configuration 50" group.byte 0x33++0x00 line.byte 0x00 "HC51,DSI HC Tile Configuration 51" group.byte 0x34++0x00 line.byte 0x00 "HC52,DSI HC Tile Configuration 52" group.byte 0x35++0x00 line.byte 0x00 "HC53,DSI HC Tile Configuration 53" group.byte 0x36++0x00 line.byte 0x00 "HC54,DSI HC Tile Configuration 54" group.byte 0x37++0x00 line.byte 0x00 "HC55,DSI HC Tile Configuration 55" group.byte 0x38++0x00 line.byte 0x00 "HC56,DSI HC Tile Configuration 56" group.byte 0x39++0x00 line.byte 0x00 "HC57,DSI HC Tile Configuration 57" group.byte 0x3A++0x00 line.byte 0x00 "HC58,DSI HC Tile Configuration 58" group.byte 0x3B++0x00 line.byte 0x00 "HC59,DSI HC Tile Configuration 59" group.byte 0x3C++0x00 line.byte 0x00 "HC60,DSI HC Tile Configuration 60" group.byte 0x3D++0x00 line.byte 0x00 "HC61,DSI HC Tile Configuration 61" group.byte 0x3E++0x00 line.byte 0x00 "HC62,DSI HC Tile Configuration 62" group.byte 0x3F++0x00 line.byte 0x00 "HC63,DSI HC Tile Configuration 63" group.byte 0x40++0x00 line.byte 0x00 "HC64,DSI HC Tile Configuration 64" group.byte 0x41++0x00 line.byte 0x00 "HC65,DSI HC Tile Configuration 65" group.byte 0x42++0x00 line.byte 0x00 "HC66,DSI HC Tile Configuration 66" group.byte 0x43++0x00 line.byte 0x00 "HC67,DSI HC Tile Configuration 67" group.byte 0x44++0x00 line.byte 0x00 "HC68,DSI HC Tile Configuration 68" group.byte 0x45++0x00 line.byte 0x00 "HC69,DSI HC Tile Configuration 69" group.byte 0x46++0x00 line.byte 0x00 "HC70,DSI HC Tile Configuration 70" group.byte 0x47++0x00 line.byte 0x00 "HC71,DSI HC Tile Configuration 71" group.byte 0x48++0x00 line.byte 0x00 "HC72,DSI HC Tile Configuration 72" group.byte 0x49++0x00 line.byte 0x00 "HC73,DSI HC Tile Configuration 73" group.byte 0x4A++0x00 line.byte 0x00 "HC74,DSI HC Tile Configuration 74" group.byte 0x4B++0x00 line.byte 0x00 "HC75,DSI HC Tile Configuration 75" group.byte 0x4C++0x00 line.byte 0x00 "HC76,DSI HC Tile Configuration 76" group.byte 0x4D++0x00 line.byte 0x00 "HC77,DSI HC Tile Configuration 77" group.byte 0x4E++0x00 line.byte 0x00 "HC78,DSI HC Tile Configuration 78" group.byte 0x4F++0x00 line.byte 0x00 "HC79,DSI HC Tile Configuration 79" group.byte 0x50++0x00 line.byte 0x00 "HC80,DSI HC Tile Configuration 80" group.byte 0x51++0x00 line.byte 0x00 "HC81,DSI HC Tile Configuration 81" group.byte 0x52++0x00 line.byte 0x00 "HC82,DSI HC Tile Configuration 82" group.byte 0x53++0x00 line.byte 0x00 "HC83,DSI HC Tile Configuration 83" group.byte 0x54++0x00 line.byte 0x00 "HC84,DSI HC Tile Configuration 84" group.byte 0x55++0x00 line.byte 0x00 "HC85,DSI HC Tile Configuration 85" group.byte 0x56++0x00 line.byte 0x00 "HC86,DSI HC Tile Configuration 86" group.byte 0x57++0x00 line.byte 0x00 "HC87,DSI HC Tile Configuration 87" group.byte 0x58++0x00 line.byte 0x00 "HC88,DSI HC Tile Configuration 88" group.byte 0x59++0x00 line.byte 0x00 "HC89,DSI HC Tile Configuration 89" group.byte 0x5A++0x00 line.byte 0x00 "HC90,DSI HC Tile Configuration 90" group.byte 0x5B++0x00 line.byte 0x00 "HC91,DSI HC Tile Configuration 91" group.byte 0x5C++0x00 line.byte 0x00 "HC92,DSI HC Tile Configuration 92" group.byte 0x5D++0x00 line.byte 0x00 "HC93,DSI HC Tile Configuration 93" group.byte 0x5E++0x00 line.byte 0x00 "HC94,DSI HC Tile Configuration 94" group.byte 0x5F++0x00 line.byte 0x00 "HC95,DSI HC Tile Configuration 95" group.byte 0x60++0x00 line.byte 0x00 "HC96,DSI HC Tile Configuration 96" group.byte 0x61++0x00 line.byte 0x00 "HC97,DSI HC Tile Configuration 97" group.byte 0x62++0x00 line.byte 0x00 "HC98,DSI HC Tile Configuration 98" group.byte 0x63++0x00 line.byte 0x00 "HC99,DSI HC Tile Configuration 99" group.byte 0x64++0x00 line.byte 0x00 "HC100,DSI HC Tile Configuration 100" group.byte 0x65++0x00 line.byte 0x00 "HC101,DSI HC Tile Configuration 101" group.byte 0x66++0x00 line.byte 0x00 "HC102,DSI HC Tile Configuration 102" group.byte 0x67++0x00 line.byte 0x00 "HC103,DSI HC Tile Configuration 103" group.byte 0x68++0x00 line.byte 0x00 "HC104,DSI HC Tile Configuration 104" group.byte 0x69++0x00 line.byte 0x00 "HC105,DSI HC Tile Configuration 105" group.byte 0x6A++0x00 line.byte 0x00 "HC106,DSI HC Tile Configuration 106" group.byte 0x6B++0x00 line.byte 0x00 "HC107,DSI HC Tile Configuration 107" group.byte 0x6C++0x00 line.byte 0x00 "HC108,DSI HC Tile Configuration 108" group.byte 0x6D++0x00 line.byte 0x00 "HC109,DSI HC Tile Configuration 109" group.byte 0x6E++0x00 line.byte 0x00 "HC110,DSI HC Tile Configuration 110" group.byte 0x6F++0x00 line.byte 0x00 "HC111,DSI HC Tile Configuration 111" group.byte 0x70++0x00 line.byte 0x00 "HC112,DSI HC Tile Configuration 112" group.byte 0x71++0x00 line.byte 0x00 "HC113,DSI HC Tile Configuration 113" group.byte 0x72++0x00 line.byte 0x00 "HC114,DSI HC Tile Configuration 114" group.byte 0x73++0x00 line.byte 0x00 "HC115,DSI HC Tile Configuration 115" group.byte 0x74++0x00 line.byte 0x00 "HC116,DSI HC Tile Configuration 116" group.byte 0x75++0x00 line.byte 0x00 "HC117,DSI HC Tile Configuration 117" group.byte 0x76++0x00 line.byte 0x00 "HC118,DSI HC Tile Configuration 118" group.byte 0x77++0x00 line.byte 0x00 "HC119,DSI HC Tile Configuration 119" group.byte 0x78++0x00 line.byte 0x00 "HC120,DSI HC Tile Configuration 120" group.byte 0x79++0x00 line.byte 0x00 "HC121,DSI HC Tile Configuration 121" group.byte 0x7A++0x00 line.byte 0x00 "HC122,DSI HC Tile Configuration 122" group.byte 0x7B++0x00 line.byte 0x00 "HC123,DSI HC Tile Configuration 123" group.byte 0x7C++0x00 line.byte 0x00 "HC124,DSI HC Tile Configuration 124" group.byte 0x7D++0x00 line.byte 0x00 "HC125,DSI HC Tile Configuration 125" group.byte 0x7E++0x00 line.byte 0x00 "HC126,DSI HC Tile Configuration 126" group.byte 0x7F++0x00 line.byte 0x00 "HC127,DSI HC Tile Configuration 127" group.byte 0x80++0x00 line.byte 0x00 "HV_L0,DSI HV Tile Configuration; Left 0" group.byte 0x81++0x00 line.byte 0x00 "HV_L1,DSI HV Tile Configuration; Left 1" group.byte 0x82++0x00 line.byte 0x00 "HV_L2,DSI HV Tile Configuration; Left 2" group.byte 0x83++0x00 line.byte 0x00 "HV_L3,DSI HV Tile Configuration; Left 3" group.byte 0x84++0x00 line.byte 0x00 "HV_L4,DSI HV Tile Configuration; Left 4" group.byte 0x85++0x00 line.byte 0x00 "HV_L5,DSI HV Tile Configuration; Left 5" group.byte 0x86++0x00 line.byte 0x00 "HV_L6,DSI HV Tile Configuration; Left 6" group.byte 0x87++0x00 line.byte 0x00 "HV_L7,DSI HV Tile Configuration; Left 7" group.byte 0x88++0x00 line.byte 0x00 "HV_L8,DSI HV Tile Configuration; Left 8" group.byte 0x89++0x00 line.byte 0x00 "HV_L9,DSI HV Tile Configuration; Left 9" group.byte 0x8A++0x00 line.byte 0x00 "HV_L10,DSI HV Tile Configuration; Left 10" group.byte 0x8B++0x00 line.byte 0x00 "HV_L11,DSI HV Tile Configuration; Left 11" group.byte 0x8C++0x00 line.byte 0x00 "HV_L12,DSI HV Tile Configuration; Left 12" group.byte 0x8D++0x00 line.byte 0x00 "HV_L13,DSI HV Tile Configuration; Left 13" group.byte 0x8E++0x00 line.byte 0x00 "HV_L14,DSI HV Tile Configuration; Left 14" group.byte 0x8F++0x00 line.byte 0x00 "HV_L15,DSI HV Tile Configuration; Left 15" group.byte 0x90++0x00 line.byte 0x00 "HS0,DSI HS Tile Configuration; Horizontal Segmentation 0" group.byte 0x91++0x00 line.byte 0x00 "HS1,DSI HS Tile Configuration; Horizontal Segmentation 1" group.byte 0x92++0x00 line.byte 0x00 "HS2,DSI HS Tile Configuration; Horizontal Segmentation 2" group.byte 0x93++0x00 line.byte 0x00 "HS3,DSI HS Tile Configuration; Horizontal Segmentation 3" group.byte 0x94++0x00 line.byte 0x00 "HS4,DSI HS Tile Configuration; Horizontal Segmentation 4" group.byte 0x95++0x00 line.byte 0x00 "HS5,DSI HS Tile Configuration; Horizontal Segmentation 5" group.byte 0x96++0x00 line.byte 0x00 "HS6,DSI HS Tile Configuration; Horizontal Segmentation 6" group.byte 0x97++0x00 line.byte 0x00 "HS7,DSI HS Tile Configuration; Horizontal Segmentation 7" group.byte 0x98++0x00 line.byte 0x00 "HS8,DSI HS Tile Configuration; Horizontal Segmentation 8" group.byte 0x99++0x00 line.byte 0x00 "HS9,DSI HS Tile Configuration; Horizontal Segmentation 9" group.byte 0x9A++0x00 line.byte 0x00 "HS10,DSI HS Tile Configuration; Horizontal Segmentation 10" group.byte 0x9B++0x00 line.byte 0x00 "HS11,DSI HS Tile Configuration; Horizontal Segmentation 11" group.byte 0x9C++0x00 line.byte 0x00 "HS12,DSI HS Tile Configuration; Horizontal Segmentation 12" group.byte 0x9D++0x00 line.byte 0x00 "HS13,DSI HS Tile Configuration; Horizontal Segmentation 13" group.byte 0x9E++0x00 line.byte 0x00 "HS14,DSI HS Tile Configuration; Horizontal Segmentation 14" group.byte 0x9F++0x00 line.byte 0x00 "HS15,DSI HS Tile Configuration; Horizontal Segmentation 15" group.byte 0xA0++0x00 line.byte 0x00 "HS16,DSI HS Tile Configuration; Horizontal Segmentation 16" group.byte 0xA1++0x00 line.byte 0x00 "HS17,DSI HS Tile Configuration; Horizontal Segmentation 17" group.byte 0xA2++0x00 line.byte 0x00 "HS18,DSI HS Tile Configuration; Horizontal Segmentation 18" group.byte 0xA3++0x00 line.byte 0x00 "HS19,DSI HS Tile Configuration; Horizontal Segmentation 19" group.byte 0xA4++0x00 line.byte 0x00 "HS20,DSI HS Tile Configuration; Horizontal Segmentation 20" group.byte 0xA5++0x00 line.byte 0x00 "HS21,DSI HS Tile Configuration; Horizontal Segmentation 21" group.byte 0xA6++0x00 line.byte 0x00 "HS22,DSI HS Tile Configuration; Horizontal Segmentation 22" group.byte 0xA7++0x00 line.byte 0x00 "HS23,DSI HS Tile Configuration; Horizontal Segmentation 23" group.byte 0xA8++0x00 line.byte 0x00 "HV_R0,DSI HV Tile Configuration; Right 0" group.byte 0xA9++0x00 line.byte 0x00 "HV_R1,DSI HV Tile Configuration; Right 1" group.byte 0xAA++0x00 line.byte 0x00 "HV_R2,DSI HV Tile Configuration; Right 2" group.byte 0xAB++0x00 line.byte 0x00 "HV_R3,DSI HV Tile Configuration; Right 3" group.byte 0xAC++0x00 line.byte 0x00 "HV_R4,DSI HV Tile Configuration; Right 4" group.byte 0xAD++0x00 line.byte 0x00 "HV_R5,DSI HV Tile Configuration; Right 5" group.byte 0xAE++0x00 line.byte 0x00 "HV_R6,DSI HV Tile Configuration; Right 6" group.byte 0xAF++0x00 line.byte 0x00 "HV_R7,DSI HV Tile Configuration; Right 7" group.byte 0xB0++0x00 line.byte 0x00 "HV_R8,DSI HV Tile Configuration; Right 8" group.byte 0xB1++0x00 line.byte 0x00 "HV_R9,DSI HV Tile Configuration; Right 9" group.byte 0xB2++0x00 line.byte 0x00 "HV_R10,DSI HV Tile Configuration; Right 10" group.byte 0xB3++0x00 line.byte 0x00 "HV_R11,DSI HV Tile Configuration; Right 11" group.byte 0xB4++0x00 line.byte 0x00 "HV_R12,DSI HV Tile Configuration; Right 12" group.byte 0xB5++0x00 line.byte 0x00 "HV_R13,DSI HV Tile Configuration; Right 13" group.byte 0xB6++0x00 line.byte 0x00 "HV_R14,DSI HV Tile Configuration; Right 14" group.byte 0xB7++0x00 line.byte 0x00 "HV_R15,DSI HV Tile Configuration; Right 15" group.word 0xC0++0x01 line.word 0x00 "DSIINP0,DSI PI Tile Configuration For DSI I/O; Input 0" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xC2++0x01 line.word 0x00 "DSIINP1,DSI PI Tile Configuration For DSI I/O; Input 1" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xC4++0x01 line.word 0x00 "DSIINP2,DSI PI Tile Configuration For DSI I/O; Input 2" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xC6++0x01 line.word 0x00 "DSIINP3,DSI PI Tile Configuration For DSI I/O; Input 3" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xC8++0x01 line.word 0x00 "DSIINP4,DSI PI Tile Configuration For DSI I/O; Input 4" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xCA++0x01 line.word 0x00 "DSIINP5,DSI PI Tile Configuration For DSI I/O; Input 5" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xCC++0x01 line.word 0x00 "DSIOUTP0,DSI PI Tile Configuration For DSI I/O; Output Pair 0" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xCE++0x01 line.word 0x00 "DSIOUTP1,DSI PI Tile Configuration For DSI I/O; Output Pair 1" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xD0++0x01 line.word 0x00 "DSIOUTP2,DSI PI Tile Configuration For DSI I/O; Output Pair 2" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xD2++0x01 line.word 0x00 "DSIOUTP3,DSI PI Tile Configuration For DSI I/O; Output Pair 3" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xD4++0x01 line.word 0x00 "DSIOUTT0,DSI PI Tile Configuration For DSI I/O; Output Triplet 0" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xD6++0x01 line.word 0x00 "DSIOUTT1,DSI PI Tile Configuration For DSI I/O; Output Triplet 1" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xD8++0x01 line.word 0x00 "DSIOUTT2,DSI PI Tile Configuration For DSI I/O; Output Triplet 2" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xDA++0x01 line.word 0x00 "DSIOUTT3,DSI PI Tile Configuration For DSI I/O; Output Triplet 3" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xDC++0x01 line.word 0x00 "DSIOUTT4,DSI PI Tile Configuration For DSI I/O; Output Triplet 4" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xDE++0x01 line.word 0x00 "DSIOUTT5,DSI PI Tile Configuration For DSI I/O; Output Triplet 5" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE0++0x01 line.word 0x00 "VS0,DSI VS Tile Configuration; Vertical Segmentation 0" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE2++0x01 line.word 0x00 "VS1,DSI VS Tile Configuration; Vertical Segmentation 1" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE4++0x01 line.word 0x00 "VS2,DSI VS Tile Configuration; Vertical Segmentation 2" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE6++0x01 line.word 0x00 "VS3,DSI VS Tile Configuration; Vertical Segmentation 3" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE8++0x01 line.word 0x00 "VS4,DSI VS Tile Configuration; Vertical Segmentation 4" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xEA++0x01 line.word 0x00 "VS5,DSI VS Tile Configuration; Vertical Segmentation 5" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xEC++0x01 line.word 0x00 "VS6,DSI VS Tile Configuration; Vertical Segmentation 6" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xEE++0x01 line.word 0x00 "VS7,DSI VS Tile Configuration; Vertical Segmentation 7" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree "UDB_DSI3" base ad:0x400F4300 width 15. group.byte 0x0++0x00 line.byte 0x00 "HC0,DSI HC Tile Configuration 0" group.byte 0x1++0x00 line.byte 0x00 "HC1,DSI HC Tile Configuration 1" group.byte 0x2++0x00 line.byte 0x00 "HC2,DSI HC Tile Configuration 2" group.byte 0x3++0x00 line.byte 0x00 "HC3,DSI HC Tile Configuration 3" group.byte 0x4++0x00 line.byte 0x00 "HC4,DSI HC Tile Configuration 4" group.byte 0x5++0x00 line.byte 0x00 "HC5,DSI HC Tile Configuration 5" group.byte 0x6++0x00 line.byte 0x00 "HC6,DSI HC Tile Configuration 6" group.byte 0x7++0x00 line.byte 0x00 "HC7,DSI HC Tile Configuration 7" group.byte 0x8++0x00 line.byte 0x00 "HC8,DSI HC Tile Configuration 8" group.byte 0x9++0x00 line.byte 0x00 "HC9,DSI HC Tile Configuration 9" group.byte 0xA++0x00 line.byte 0x00 "HC10,DSI HC Tile Configuration 10" group.byte 0xB++0x00 line.byte 0x00 "HC11,DSI HC Tile Configuration 11" group.byte 0xC++0x00 line.byte 0x00 "HC12,DSI HC Tile Configuration 12" group.byte 0xD++0x00 line.byte 0x00 "HC13,DSI HC Tile Configuration 13" group.byte 0xE++0x00 line.byte 0x00 "HC14,DSI HC Tile Configuration 14" group.byte 0xF++0x00 line.byte 0x00 "HC15,DSI HC Tile Configuration 15" group.byte 0x10++0x00 line.byte 0x00 "HC16,DSI HC Tile Configuration 16" group.byte 0x11++0x00 line.byte 0x00 "HC17,DSI HC Tile Configuration 17" group.byte 0x12++0x00 line.byte 0x00 "HC18,DSI HC Tile Configuration 18" group.byte 0x13++0x00 line.byte 0x00 "HC19,DSI HC Tile Configuration 19" group.byte 0x14++0x00 line.byte 0x00 "HC20,DSI HC Tile Configuration 20" group.byte 0x15++0x00 line.byte 0x00 "HC21,DSI HC Tile Configuration 21" group.byte 0x16++0x00 line.byte 0x00 "HC22,DSI HC Tile Configuration 22" group.byte 0x17++0x00 line.byte 0x00 "HC23,DSI HC Tile Configuration 23" group.byte 0x18++0x00 line.byte 0x00 "HC24,DSI HC Tile Configuration 24" group.byte 0x19++0x00 line.byte 0x00 "HC25,DSI HC Tile Configuration 25" group.byte 0x1A++0x00 line.byte 0x00 "HC26,DSI HC Tile Configuration 26" group.byte 0x1B++0x00 line.byte 0x00 "HC27,DSI HC Tile Configuration 27" group.byte 0x1C++0x00 line.byte 0x00 "HC28,DSI HC Tile Configuration 28" group.byte 0x1D++0x00 line.byte 0x00 "HC29,DSI HC Tile Configuration 29" group.byte 0x1E++0x00 line.byte 0x00 "HC30,DSI HC Tile Configuration 30" group.byte 0x1F++0x00 line.byte 0x00 "HC31,DSI HC Tile Configuration 31" group.byte 0x20++0x00 line.byte 0x00 "HC32,DSI HC Tile Configuration 32" group.byte 0x21++0x00 line.byte 0x00 "HC33,DSI HC Tile Configuration 33" group.byte 0x22++0x00 line.byte 0x00 "HC34,DSI HC Tile Configuration 34" group.byte 0x23++0x00 line.byte 0x00 "HC35,DSI HC Tile Configuration 35" group.byte 0x24++0x00 line.byte 0x00 "HC36,DSI HC Tile Configuration 36" group.byte 0x25++0x00 line.byte 0x00 "HC37,DSI HC Tile Configuration 37" group.byte 0x26++0x00 line.byte 0x00 "HC38,DSI HC Tile Configuration 38" group.byte 0x27++0x00 line.byte 0x00 "HC39,DSI HC Tile Configuration 39" group.byte 0x28++0x00 line.byte 0x00 "HC40,DSI HC Tile Configuration 40" group.byte 0x29++0x00 line.byte 0x00 "HC41,DSI HC Tile Configuration 41" group.byte 0x2A++0x00 line.byte 0x00 "HC42,DSI HC Tile Configuration 42" group.byte 0x2B++0x00 line.byte 0x00 "HC43,DSI HC Tile Configuration 43" group.byte 0x2C++0x00 line.byte 0x00 "HC44,DSI HC Tile Configuration 44" group.byte 0x2D++0x00 line.byte 0x00 "HC45,DSI HC Tile Configuration 45" group.byte 0x2E++0x00 line.byte 0x00 "HC46,DSI HC Tile Configuration 46" group.byte 0x2F++0x00 line.byte 0x00 "HC47,DSI HC Tile Configuration 47" group.byte 0x30++0x00 line.byte 0x00 "HC48,DSI HC Tile Configuration 48" group.byte 0x31++0x00 line.byte 0x00 "HC49,DSI HC Tile Configuration 49" group.byte 0x32++0x00 line.byte 0x00 "HC50,DSI HC Tile Configuration 50" group.byte 0x33++0x00 line.byte 0x00 "HC51,DSI HC Tile Configuration 51" group.byte 0x34++0x00 line.byte 0x00 "HC52,DSI HC Tile Configuration 52" group.byte 0x35++0x00 line.byte 0x00 "HC53,DSI HC Tile Configuration 53" group.byte 0x36++0x00 line.byte 0x00 "HC54,DSI HC Tile Configuration 54" group.byte 0x37++0x00 line.byte 0x00 "HC55,DSI HC Tile Configuration 55" group.byte 0x38++0x00 line.byte 0x00 "HC56,DSI HC Tile Configuration 56" group.byte 0x39++0x00 line.byte 0x00 "HC57,DSI HC Tile Configuration 57" group.byte 0x3A++0x00 line.byte 0x00 "HC58,DSI HC Tile Configuration 58" group.byte 0x3B++0x00 line.byte 0x00 "HC59,DSI HC Tile Configuration 59" group.byte 0x3C++0x00 line.byte 0x00 "HC60,DSI HC Tile Configuration 60" group.byte 0x3D++0x00 line.byte 0x00 "HC61,DSI HC Tile Configuration 61" group.byte 0x3E++0x00 line.byte 0x00 "HC62,DSI HC Tile Configuration 62" group.byte 0x3F++0x00 line.byte 0x00 "HC63,DSI HC Tile Configuration 63" group.byte 0x40++0x00 line.byte 0x00 "HC64,DSI HC Tile Configuration 64" group.byte 0x41++0x00 line.byte 0x00 "HC65,DSI HC Tile Configuration 65" group.byte 0x42++0x00 line.byte 0x00 "HC66,DSI HC Tile Configuration 66" group.byte 0x43++0x00 line.byte 0x00 "HC67,DSI HC Tile Configuration 67" group.byte 0x44++0x00 line.byte 0x00 "HC68,DSI HC Tile Configuration 68" group.byte 0x45++0x00 line.byte 0x00 "HC69,DSI HC Tile Configuration 69" group.byte 0x46++0x00 line.byte 0x00 "HC70,DSI HC Tile Configuration 70" group.byte 0x47++0x00 line.byte 0x00 "HC71,DSI HC Tile Configuration 71" group.byte 0x48++0x00 line.byte 0x00 "HC72,DSI HC Tile Configuration 72" group.byte 0x49++0x00 line.byte 0x00 "HC73,DSI HC Tile Configuration 73" group.byte 0x4A++0x00 line.byte 0x00 "HC74,DSI HC Tile Configuration 74" group.byte 0x4B++0x00 line.byte 0x00 "HC75,DSI HC Tile Configuration 75" group.byte 0x4C++0x00 line.byte 0x00 "HC76,DSI HC Tile Configuration 76" group.byte 0x4D++0x00 line.byte 0x00 "HC77,DSI HC Tile Configuration 77" group.byte 0x4E++0x00 line.byte 0x00 "HC78,DSI HC Tile Configuration 78" group.byte 0x4F++0x00 line.byte 0x00 "HC79,DSI HC Tile Configuration 79" group.byte 0x50++0x00 line.byte 0x00 "HC80,DSI HC Tile Configuration 80" group.byte 0x51++0x00 line.byte 0x00 "HC81,DSI HC Tile Configuration 81" group.byte 0x52++0x00 line.byte 0x00 "HC82,DSI HC Tile Configuration 82" group.byte 0x53++0x00 line.byte 0x00 "HC83,DSI HC Tile Configuration 83" group.byte 0x54++0x00 line.byte 0x00 "HC84,DSI HC Tile Configuration 84" group.byte 0x55++0x00 line.byte 0x00 "HC85,DSI HC Tile Configuration 85" group.byte 0x56++0x00 line.byte 0x00 "HC86,DSI HC Tile Configuration 86" group.byte 0x57++0x00 line.byte 0x00 "HC87,DSI HC Tile Configuration 87" group.byte 0x58++0x00 line.byte 0x00 "HC88,DSI HC Tile Configuration 88" group.byte 0x59++0x00 line.byte 0x00 "HC89,DSI HC Tile Configuration 89" group.byte 0x5A++0x00 line.byte 0x00 "HC90,DSI HC Tile Configuration 90" group.byte 0x5B++0x00 line.byte 0x00 "HC91,DSI HC Tile Configuration 91" group.byte 0x5C++0x00 line.byte 0x00 "HC92,DSI HC Tile Configuration 92" group.byte 0x5D++0x00 line.byte 0x00 "HC93,DSI HC Tile Configuration 93" group.byte 0x5E++0x00 line.byte 0x00 "HC94,DSI HC Tile Configuration 94" group.byte 0x5F++0x00 line.byte 0x00 "HC95,DSI HC Tile Configuration 95" group.byte 0x60++0x00 line.byte 0x00 "HC96,DSI HC Tile Configuration 96" group.byte 0x61++0x00 line.byte 0x00 "HC97,DSI HC Tile Configuration 97" group.byte 0x62++0x00 line.byte 0x00 "HC98,DSI HC Tile Configuration 98" group.byte 0x63++0x00 line.byte 0x00 "HC99,DSI HC Tile Configuration 99" group.byte 0x64++0x00 line.byte 0x00 "HC100,DSI HC Tile Configuration 100" group.byte 0x65++0x00 line.byte 0x00 "HC101,DSI HC Tile Configuration 101" group.byte 0x66++0x00 line.byte 0x00 "HC102,DSI HC Tile Configuration 102" group.byte 0x67++0x00 line.byte 0x00 "HC103,DSI HC Tile Configuration 103" group.byte 0x68++0x00 line.byte 0x00 "HC104,DSI HC Tile Configuration 104" group.byte 0x69++0x00 line.byte 0x00 "HC105,DSI HC Tile Configuration 105" group.byte 0x6A++0x00 line.byte 0x00 "HC106,DSI HC Tile Configuration 106" group.byte 0x6B++0x00 line.byte 0x00 "HC107,DSI HC Tile Configuration 107" group.byte 0x6C++0x00 line.byte 0x00 "HC108,DSI HC Tile Configuration 108" group.byte 0x6D++0x00 line.byte 0x00 "HC109,DSI HC Tile Configuration 109" group.byte 0x6E++0x00 line.byte 0x00 "HC110,DSI HC Tile Configuration 110" group.byte 0x6F++0x00 line.byte 0x00 "HC111,DSI HC Tile Configuration 111" group.byte 0x70++0x00 line.byte 0x00 "HC112,DSI HC Tile Configuration 112" group.byte 0x71++0x00 line.byte 0x00 "HC113,DSI HC Tile Configuration 113" group.byte 0x72++0x00 line.byte 0x00 "HC114,DSI HC Tile Configuration 114" group.byte 0x73++0x00 line.byte 0x00 "HC115,DSI HC Tile Configuration 115" group.byte 0x74++0x00 line.byte 0x00 "HC116,DSI HC Tile Configuration 116" group.byte 0x75++0x00 line.byte 0x00 "HC117,DSI HC Tile Configuration 117" group.byte 0x76++0x00 line.byte 0x00 "HC118,DSI HC Tile Configuration 118" group.byte 0x77++0x00 line.byte 0x00 "HC119,DSI HC Tile Configuration 119" group.byte 0x78++0x00 line.byte 0x00 "HC120,DSI HC Tile Configuration 120" group.byte 0x79++0x00 line.byte 0x00 "HC121,DSI HC Tile Configuration 121" group.byte 0x7A++0x00 line.byte 0x00 "HC122,DSI HC Tile Configuration 122" group.byte 0x7B++0x00 line.byte 0x00 "HC123,DSI HC Tile Configuration 123" group.byte 0x7C++0x00 line.byte 0x00 "HC124,DSI HC Tile Configuration 124" group.byte 0x7D++0x00 line.byte 0x00 "HC125,DSI HC Tile Configuration 125" group.byte 0x7E++0x00 line.byte 0x00 "HC126,DSI HC Tile Configuration 126" group.byte 0x7F++0x00 line.byte 0x00 "HC127,DSI HC Tile Configuration 127" group.byte 0x80++0x00 line.byte 0x00 "HV_L0,DSI HV Tile Configuration; Left 0" group.byte 0x81++0x00 line.byte 0x00 "HV_L1,DSI HV Tile Configuration; Left 1" group.byte 0x82++0x00 line.byte 0x00 "HV_L2,DSI HV Tile Configuration; Left 2" group.byte 0x83++0x00 line.byte 0x00 "HV_L3,DSI HV Tile Configuration; Left 3" group.byte 0x84++0x00 line.byte 0x00 "HV_L4,DSI HV Tile Configuration; Left 4" group.byte 0x85++0x00 line.byte 0x00 "HV_L5,DSI HV Tile Configuration; Left 5" group.byte 0x86++0x00 line.byte 0x00 "HV_L6,DSI HV Tile Configuration; Left 6" group.byte 0x87++0x00 line.byte 0x00 "HV_L7,DSI HV Tile Configuration; Left 7" group.byte 0x88++0x00 line.byte 0x00 "HV_L8,DSI HV Tile Configuration; Left 8" group.byte 0x89++0x00 line.byte 0x00 "HV_L9,DSI HV Tile Configuration; Left 9" group.byte 0x8A++0x00 line.byte 0x00 "HV_L10,DSI HV Tile Configuration; Left 10" group.byte 0x8B++0x00 line.byte 0x00 "HV_L11,DSI HV Tile Configuration; Left 11" group.byte 0x8C++0x00 line.byte 0x00 "HV_L12,DSI HV Tile Configuration; Left 12" group.byte 0x8D++0x00 line.byte 0x00 "HV_L13,DSI HV Tile Configuration; Left 13" group.byte 0x8E++0x00 line.byte 0x00 "HV_L14,DSI HV Tile Configuration; Left 14" group.byte 0x8F++0x00 line.byte 0x00 "HV_L15,DSI HV Tile Configuration; Left 15" group.byte 0x90++0x00 line.byte 0x00 "HS0,DSI HS Tile Configuration; Horizontal Segmentation 0" group.byte 0x91++0x00 line.byte 0x00 "HS1,DSI HS Tile Configuration; Horizontal Segmentation 1" group.byte 0x92++0x00 line.byte 0x00 "HS2,DSI HS Tile Configuration; Horizontal Segmentation 2" group.byte 0x93++0x00 line.byte 0x00 "HS3,DSI HS Tile Configuration; Horizontal Segmentation 3" group.byte 0x94++0x00 line.byte 0x00 "HS4,DSI HS Tile Configuration; Horizontal Segmentation 4" group.byte 0x95++0x00 line.byte 0x00 "HS5,DSI HS Tile Configuration; Horizontal Segmentation 5" group.byte 0x96++0x00 line.byte 0x00 "HS6,DSI HS Tile Configuration; Horizontal Segmentation 6" group.byte 0x97++0x00 line.byte 0x00 "HS7,DSI HS Tile Configuration; Horizontal Segmentation 7" group.byte 0x98++0x00 line.byte 0x00 "HS8,DSI HS Tile Configuration; Horizontal Segmentation 8" group.byte 0x99++0x00 line.byte 0x00 "HS9,DSI HS Tile Configuration; Horizontal Segmentation 9" group.byte 0x9A++0x00 line.byte 0x00 "HS10,DSI HS Tile Configuration; Horizontal Segmentation 10" group.byte 0x9B++0x00 line.byte 0x00 "HS11,DSI HS Tile Configuration; Horizontal Segmentation 11" group.byte 0x9C++0x00 line.byte 0x00 "HS12,DSI HS Tile Configuration; Horizontal Segmentation 12" group.byte 0x9D++0x00 line.byte 0x00 "HS13,DSI HS Tile Configuration; Horizontal Segmentation 13" group.byte 0x9E++0x00 line.byte 0x00 "HS14,DSI HS Tile Configuration; Horizontal Segmentation 14" group.byte 0x9F++0x00 line.byte 0x00 "HS15,DSI HS Tile Configuration; Horizontal Segmentation 15" group.byte 0xA0++0x00 line.byte 0x00 "HS16,DSI HS Tile Configuration; Horizontal Segmentation 16" group.byte 0xA1++0x00 line.byte 0x00 "HS17,DSI HS Tile Configuration; Horizontal Segmentation 17" group.byte 0xA2++0x00 line.byte 0x00 "HS18,DSI HS Tile Configuration; Horizontal Segmentation 18" group.byte 0xA3++0x00 line.byte 0x00 "HS19,DSI HS Tile Configuration; Horizontal Segmentation 19" group.byte 0xA4++0x00 line.byte 0x00 "HS20,DSI HS Tile Configuration; Horizontal Segmentation 20" group.byte 0xA5++0x00 line.byte 0x00 "HS21,DSI HS Tile Configuration; Horizontal Segmentation 21" group.byte 0xA6++0x00 line.byte 0x00 "HS22,DSI HS Tile Configuration; Horizontal Segmentation 22" group.byte 0xA7++0x00 line.byte 0x00 "HS23,DSI HS Tile Configuration; Horizontal Segmentation 23" group.byte 0xA8++0x00 line.byte 0x00 "HV_R0,DSI HV Tile Configuration; Right 0" group.byte 0xA9++0x00 line.byte 0x00 "HV_R1,DSI HV Tile Configuration; Right 1" group.byte 0xAA++0x00 line.byte 0x00 "HV_R2,DSI HV Tile Configuration; Right 2" group.byte 0xAB++0x00 line.byte 0x00 "HV_R3,DSI HV Tile Configuration; Right 3" group.byte 0xAC++0x00 line.byte 0x00 "HV_R4,DSI HV Tile Configuration; Right 4" group.byte 0xAD++0x00 line.byte 0x00 "HV_R5,DSI HV Tile Configuration; Right 5" group.byte 0xAE++0x00 line.byte 0x00 "HV_R6,DSI HV Tile Configuration; Right 6" group.byte 0xAF++0x00 line.byte 0x00 "HV_R7,DSI HV Tile Configuration; Right 7" group.byte 0xB0++0x00 line.byte 0x00 "HV_R8,DSI HV Tile Configuration; Right 8" group.byte 0xB1++0x00 line.byte 0x00 "HV_R9,DSI HV Tile Configuration; Right 9" group.byte 0xB2++0x00 line.byte 0x00 "HV_R10,DSI HV Tile Configuration; Right 10" group.byte 0xB3++0x00 line.byte 0x00 "HV_R11,DSI HV Tile Configuration; Right 11" group.byte 0xB4++0x00 line.byte 0x00 "HV_R12,DSI HV Tile Configuration; Right 12" group.byte 0xB5++0x00 line.byte 0x00 "HV_R13,DSI HV Tile Configuration; Right 13" group.byte 0xB6++0x00 line.byte 0x00 "HV_R14,DSI HV Tile Configuration; Right 14" group.byte 0xB7++0x00 line.byte 0x00 "HV_R15,DSI HV Tile Configuration; Right 15" group.word 0xC0++0x01 line.word 0x00 "DSIINP0,DSI PI Tile Configuration For DSI I/O; Input 0" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xC2++0x01 line.word 0x00 "DSIINP1,DSI PI Tile Configuration For DSI I/O; Input 1" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xC4++0x01 line.word 0x00 "DSIINP2,DSI PI Tile Configuration For DSI I/O; Input 2" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xC6++0x01 line.word 0x00 "DSIINP3,DSI PI Tile Configuration For DSI I/O; Input 3" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xC8++0x01 line.word 0x00 "DSIINP4,DSI PI Tile Configuration For DSI I/O; Input 4" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xCA++0x01 line.word 0x00 "DSIINP5,DSI PI Tile Configuration For DSI I/O; Input 5" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xCC++0x01 line.word 0x00 "DSIOUTP0,DSI PI Tile Configuration For DSI I/O; Output Pair 0" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xCE++0x01 line.word 0x00 "DSIOUTP1,DSI PI Tile Configuration For DSI I/O; Output Pair 1" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xD0++0x01 line.word 0x00 "DSIOUTP2,DSI PI Tile Configuration For DSI I/O; Output Pair 2" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xD2++0x01 line.word 0x00 "DSIOUTP3,DSI PI Tile Configuration For DSI I/O; Output Pair 3" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xD4++0x01 line.word 0x00 "DSIOUTT0,DSI PI Tile Configuration For DSI I/O; Output Triplet 0" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xD6++0x01 line.word 0x00 "DSIOUTT1,DSI PI Tile Configuration For DSI I/O; Output Triplet 1" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xD8++0x01 line.word 0x00 "DSIOUTT2,DSI PI Tile Configuration For DSI I/O; Output Triplet 2" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xDA++0x01 line.word 0x00 "DSIOUTT3,DSI PI Tile Configuration For DSI I/O; Output Triplet 3" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xDC++0x01 line.word 0x00 "DSIOUTT4,DSI PI Tile Configuration For DSI I/O; Output Triplet 4" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xDE++0x01 line.word 0x00 "DSIOUTT5,DSI PI Tile Configuration For DSI I/O; Output Triplet 5" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE0++0x01 line.word 0x00 "VS0,DSI VS Tile Configuration; Vertical Segmentation 0" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE2++0x01 line.word 0x00 "VS1,DSI VS Tile Configuration; Vertical Segmentation 1" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE4++0x01 line.word 0x00 "VS2,DSI VS Tile Configuration; Vertical Segmentation 2" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE6++0x01 line.word 0x00 "VS3,DSI VS Tile Configuration; Vertical Segmentation 3" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE8++0x01 line.word 0x00 "VS4,DSI VS Tile Configuration; Vertical Segmentation 4" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xEA++0x01 line.word 0x00 "VS5,DSI VS Tile Configuration; Vertical Segmentation 5" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xEC++0x01 line.word 0x00 "VS6,DSI VS Tile Configuration; Vertical Segmentation 6" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xEE++0x01 line.word 0x00 "VS7,DSI VS Tile Configuration; Vertical Segmentation 7" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree "UDB_DSI4" base ad:0x400F4400 width 15. group.byte 0x0++0x00 line.byte 0x00 "HC0,DSI HC Tile Configuration 0" group.byte 0x1++0x00 line.byte 0x00 "HC1,DSI HC Tile Configuration 1" group.byte 0x2++0x00 line.byte 0x00 "HC2,DSI HC Tile Configuration 2" group.byte 0x3++0x00 line.byte 0x00 "HC3,DSI HC Tile Configuration 3" group.byte 0x4++0x00 line.byte 0x00 "HC4,DSI HC Tile Configuration 4" group.byte 0x5++0x00 line.byte 0x00 "HC5,DSI HC Tile Configuration 5" group.byte 0x6++0x00 line.byte 0x00 "HC6,DSI HC Tile Configuration 6" group.byte 0x7++0x00 line.byte 0x00 "HC7,DSI HC Tile Configuration 7" group.byte 0x8++0x00 line.byte 0x00 "HC8,DSI HC Tile Configuration 8" group.byte 0x9++0x00 line.byte 0x00 "HC9,DSI HC Tile Configuration 9" group.byte 0xA++0x00 line.byte 0x00 "HC10,DSI HC Tile Configuration 10" group.byte 0xB++0x00 line.byte 0x00 "HC11,DSI HC Tile Configuration 11" group.byte 0xC++0x00 line.byte 0x00 "HC12,DSI HC Tile Configuration 12" group.byte 0xD++0x00 line.byte 0x00 "HC13,DSI HC Tile Configuration 13" group.byte 0xE++0x00 line.byte 0x00 "HC14,DSI HC Tile Configuration 14" group.byte 0xF++0x00 line.byte 0x00 "HC15,DSI HC Tile Configuration 15" group.byte 0x10++0x00 line.byte 0x00 "HC16,DSI HC Tile Configuration 16" group.byte 0x11++0x00 line.byte 0x00 "HC17,DSI HC Tile Configuration 17" group.byte 0x12++0x00 line.byte 0x00 "HC18,DSI HC Tile Configuration 18" group.byte 0x13++0x00 line.byte 0x00 "HC19,DSI HC Tile Configuration 19" group.byte 0x14++0x00 line.byte 0x00 "HC20,DSI HC Tile Configuration 20" group.byte 0x15++0x00 line.byte 0x00 "HC21,DSI HC Tile Configuration 21" group.byte 0x16++0x00 line.byte 0x00 "HC22,DSI HC Tile Configuration 22" group.byte 0x17++0x00 line.byte 0x00 "HC23,DSI HC Tile Configuration 23" group.byte 0x18++0x00 line.byte 0x00 "HC24,DSI HC Tile Configuration 24" group.byte 0x19++0x00 line.byte 0x00 "HC25,DSI HC Tile Configuration 25" group.byte 0x1A++0x00 line.byte 0x00 "HC26,DSI HC Tile Configuration 26" group.byte 0x1B++0x00 line.byte 0x00 "HC27,DSI HC Tile Configuration 27" group.byte 0x1C++0x00 line.byte 0x00 "HC28,DSI HC Tile Configuration 28" group.byte 0x1D++0x00 line.byte 0x00 "HC29,DSI HC Tile Configuration 29" group.byte 0x1E++0x00 line.byte 0x00 "HC30,DSI HC Tile Configuration 30" group.byte 0x1F++0x00 line.byte 0x00 "HC31,DSI HC Tile Configuration 31" group.byte 0x20++0x00 line.byte 0x00 "HC32,DSI HC Tile Configuration 32" group.byte 0x21++0x00 line.byte 0x00 "HC33,DSI HC Tile Configuration 33" group.byte 0x22++0x00 line.byte 0x00 "HC34,DSI HC Tile Configuration 34" group.byte 0x23++0x00 line.byte 0x00 "HC35,DSI HC Tile Configuration 35" group.byte 0x24++0x00 line.byte 0x00 "HC36,DSI HC Tile Configuration 36" group.byte 0x25++0x00 line.byte 0x00 "HC37,DSI HC Tile Configuration 37" group.byte 0x26++0x00 line.byte 0x00 "HC38,DSI HC Tile Configuration 38" group.byte 0x27++0x00 line.byte 0x00 "HC39,DSI HC Tile Configuration 39" group.byte 0x28++0x00 line.byte 0x00 "HC40,DSI HC Tile Configuration 40" group.byte 0x29++0x00 line.byte 0x00 "HC41,DSI HC Tile Configuration 41" group.byte 0x2A++0x00 line.byte 0x00 "HC42,DSI HC Tile Configuration 42" group.byte 0x2B++0x00 line.byte 0x00 "HC43,DSI HC Tile Configuration 43" group.byte 0x2C++0x00 line.byte 0x00 "HC44,DSI HC Tile Configuration 44" group.byte 0x2D++0x00 line.byte 0x00 "HC45,DSI HC Tile Configuration 45" group.byte 0x2E++0x00 line.byte 0x00 "HC46,DSI HC Tile Configuration 46" group.byte 0x2F++0x00 line.byte 0x00 "HC47,DSI HC Tile Configuration 47" group.byte 0x30++0x00 line.byte 0x00 "HC48,DSI HC Tile Configuration 48" group.byte 0x31++0x00 line.byte 0x00 "HC49,DSI HC Tile Configuration 49" group.byte 0x32++0x00 line.byte 0x00 "HC50,DSI HC Tile Configuration 50" group.byte 0x33++0x00 line.byte 0x00 "HC51,DSI HC Tile Configuration 51" group.byte 0x34++0x00 line.byte 0x00 "HC52,DSI HC Tile Configuration 52" group.byte 0x35++0x00 line.byte 0x00 "HC53,DSI HC Tile Configuration 53" group.byte 0x36++0x00 line.byte 0x00 "HC54,DSI HC Tile Configuration 54" group.byte 0x37++0x00 line.byte 0x00 "HC55,DSI HC Tile Configuration 55" group.byte 0x38++0x00 line.byte 0x00 "HC56,DSI HC Tile Configuration 56" group.byte 0x39++0x00 line.byte 0x00 "HC57,DSI HC Tile Configuration 57" group.byte 0x3A++0x00 line.byte 0x00 "HC58,DSI HC Tile Configuration 58" group.byte 0x3B++0x00 line.byte 0x00 "HC59,DSI HC Tile Configuration 59" group.byte 0x3C++0x00 line.byte 0x00 "HC60,DSI HC Tile Configuration 60" group.byte 0x3D++0x00 line.byte 0x00 "HC61,DSI HC Tile Configuration 61" group.byte 0x3E++0x00 line.byte 0x00 "HC62,DSI HC Tile Configuration 62" group.byte 0x3F++0x00 line.byte 0x00 "HC63,DSI HC Tile Configuration 63" group.byte 0x40++0x00 line.byte 0x00 "HC64,DSI HC Tile Configuration 64" group.byte 0x41++0x00 line.byte 0x00 "HC65,DSI HC Tile Configuration 65" group.byte 0x42++0x00 line.byte 0x00 "HC66,DSI HC Tile Configuration 66" group.byte 0x43++0x00 line.byte 0x00 "HC67,DSI HC Tile Configuration 67" group.byte 0x44++0x00 line.byte 0x00 "HC68,DSI HC Tile Configuration 68" group.byte 0x45++0x00 line.byte 0x00 "HC69,DSI HC Tile Configuration 69" group.byte 0x46++0x00 line.byte 0x00 "HC70,DSI HC Tile Configuration 70" group.byte 0x47++0x00 line.byte 0x00 "HC71,DSI HC Tile Configuration 71" group.byte 0x48++0x00 line.byte 0x00 "HC72,DSI HC Tile Configuration 72" group.byte 0x49++0x00 line.byte 0x00 "HC73,DSI HC Tile Configuration 73" group.byte 0x4A++0x00 line.byte 0x00 "HC74,DSI HC Tile Configuration 74" group.byte 0x4B++0x00 line.byte 0x00 "HC75,DSI HC Tile Configuration 75" group.byte 0x4C++0x00 line.byte 0x00 "HC76,DSI HC Tile Configuration 76" group.byte 0x4D++0x00 line.byte 0x00 "HC77,DSI HC Tile Configuration 77" group.byte 0x4E++0x00 line.byte 0x00 "HC78,DSI HC Tile Configuration 78" group.byte 0x4F++0x00 line.byte 0x00 "HC79,DSI HC Tile Configuration 79" group.byte 0x50++0x00 line.byte 0x00 "HC80,DSI HC Tile Configuration 80" group.byte 0x51++0x00 line.byte 0x00 "HC81,DSI HC Tile Configuration 81" group.byte 0x52++0x00 line.byte 0x00 "HC82,DSI HC Tile Configuration 82" group.byte 0x53++0x00 line.byte 0x00 "HC83,DSI HC Tile Configuration 83" group.byte 0x54++0x00 line.byte 0x00 "HC84,DSI HC Tile Configuration 84" group.byte 0x55++0x00 line.byte 0x00 "HC85,DSI HC Tile Configuration 85" group.byte 0x56++0x00 line.byte 0x00 "HC86,DSI HC Tile Configuration 86" group.byte 0x57++0x00 line.byte 0x00 "HC87,DSI HC Tile Configuration 87" group.byte 0x58++0x00 line.byte 0x00 "HC88,DSI HC Tile Configuration 88" group.byte 0x59++0x00 line.byte 0x00 "HC89,DSI HC Tile Configuration 89" group.byte 0x5A++0x00 line.byte 0x00 "HC90,DSI HC Tile Configuration 90" group.byte 0x5B++0x00 line.byte 0x00 "HC91,DSI HC Tile Configuration 91" group.byte 0x5C++0x00 line.byte 0x00 "HC92,DSI HC Tile Configuration 92" group.byte 0x5D++0x00 line.byte 0x00 "HC93,DSI HC Tile Configuration 93" group.byte 0x5E++0x00 line.byte 0x00 "HC94,DSI HC Tile Configuration 94" group.byte 0x5F++0x00 line.byte 0x00 "HC95,DSI HC Tile Configuration 95" group.byte 0x60++0x00 line.byte 0x00 "HC96,DSI HC Tile Configuration 96" group.byte 0x61++0x00 line.byte 0x00 "HC97,DSI HC Tile Configuration 97" group.byte 0x62++0x00 line.byte 0x00 "HC98,DSI HC Tile Configuration 98" group.byte 0x63++0x00 line.byte 0x00 "HC99,DSI HC Tile Configuration 99" group.byte 0x64++0x00 line.byte 0x00 "HC100,DSI HC Tile Configuration 100" group.byte 0x65++0x00 line.byte 0x00 "HC101,DSI HC Tile Configuration 101" group.byte 0x66++0x00 line.byte 0x00 "HC102,DSI HC Tile Configuration 102" group.byte 0x67++0x00 line.byte 0x00 "HC103,DSI HC Tile Configuration 103" group.byte 0x68++0x00 line.byte 0x00 "HC104,DSI HC Tile Configuration 104" group.byte 0x69++0x00 line.byte 0x00 "HC105,DSI HC Tile Configuration 105" group.byte 0x6A++0x00 line.byte 0x00 "HC106,DSI HC Tile Configuration 106" group.byte 0x6B++0x00 line.byte 0x00 "HC107,DSI HC Tile Configuration 107" group.byte 0x6C++0x00 line.byte 0x00 "HC108,DSI HC Tile Configuration 108" group.byte 0x6D++0x00 line.byte 0x00 "HC109,DSI HC Tile Configuration 109" group.byte 0x6E++0x00 line.byte 0x00 "HC110,DSI HC Tile Configuration 110" group.byte 0x6F++0x00 line.byte 0x00 "HC111,DSI HC Tile Configuration 111" group.byte 0x70++0x00 line.byte 0x00 "HC112,DSI HC Tile Configuration 112" group.byte 0x71++0x00 line.byte 0x00 "HC113,DSI HC Tile Configuration 113" group.byte 0x72++0x00 line.byte 0x00 "HC114,DSI HC Tile Configuration 114" group.byte 0x73++0x00 line.byte 0x00 "HC115,DSI HC Tile Configuration 115" group.byte 0x74++0x00 line.byte 0x00 "HC116,DSI HC Tile Configuration 116" group.byte 0x75++0x00 line.byte 0x00 "HC117,DSI HC Tile Configuration 117" group.byte 0x76++0x00 line.byte 0x00 "HC118,DSI HC Tile Configuration 118" group.byte 0x77++0x00 line.byte 0x00 "HC119,DSI HC Tile Configuration 119" group.byte 0x78++0x00 line.byte 0x00 "HC120,DSI HC Tile Configuration 120" group.byte 0x79++0x00 line.byte 0x00 "HC121,DSI HC Tile Configuration 121" group.byte 0x7A++0x00 line.byte 0x00 "HC122,DSI HC Tile Configuration 122" group.byte 0x7B++0x00 line.byte 0x00 "HC123,DSI HC Tile Configuration 123" group.byte 0x7C++0x00 line.byte 0x00 "HC124,DSI HC Tile Configuration 124" group.byte 0x7D++0x00 line.byte 0x00 "HC125,DSI HC Tile Configuration 125" group.byte 0x7E++0x00 line.byte 0x00 "HC126,DSI HC Tile Configuration 126" group.byte 0x7F++0x00 line.byte 0x00 "HC127,DSI HC Tile Configuration 127" group.byte 0x80++0x00 line.byte 0x00 "HV_L0,DSI HV Tile Configuration; Left 0" group.byte 0x81++0x00 line.byte 0x00 "HV_L1,DSI HV Tile Configuration; Left 1" group.byte 0x82++0x00 line.byte 0x00 "HV_L2,DSI HV Tile Configuration; Left 2" group.byte 0x83++0x00 line.byte 0x00 "HV_L3,DSI HV Tile Configuration; Left 3" group.byte 0x84++0x00 line.byte 0x00 "HV_L4,DSI HV Tile Configuration; Left 4" group.byte 0x85++0x00 line.byte 0x00 "HV_L5,DSI HV Tile Configuration; Left 5" group.byte 0x86++0x00 line.byte 0x00 "HV_L6,DSI HV Tile Configuration; Left 6" group.byte 0x87++0x00 line.byte 0x00 "HV_L7,DSI HV Tile Configuration; Left 7" group.byte 0x88++0x00 line.byte 0x00 "HV_L8,DSI HV Tile Configuration; Left 8" group.byte 0x89++0x00 line.byte 0x00 "HV_L9,DSI HV Tile Configuration; Left 9" group.byte 0x8A++0x00 line.byte 0x00 "HV_L10,DSI HV Tile Configuration; Left 10" group.byte 0x8B++0x00 line.byte 0x00 "HV_L11,DSI HV Tile Configuration; Left 11" group.byte 0x8C++0x00 line.byte 0x00 "HV_L12,DSI HV Tile Configuration; Left 12" group.byte 0x8D++0x00 line.byte 0x00 "HV_L13,DSI HV Tile Configuration; Left 13" group.byte 0x8E++0x00 line.byte 0x00 "HV_L14,DSI HV Tile Configuration; Left 14" group.byte 0x8F++0x00 line.byte 0x00 "HV_L15,DSI HV Tile Configuration; Left 15" group.byte 0x90++0x00 line.byte 0x00 "HS0,DSI HS Tile Configuration; Horizontal Segmentation 0" group.byte 0x91++0x00 line.byte 0x00 "HS1,DSI HS Tile Configuration; Horizontal Segmentation 1" group.byte 0x92++0x00 line.byte 0x00 "HS2,DSI HS Tile Configuration; Horizontal Segmentation 2" group.byte 0x93++0x00 line.byte 0x00 "HS3,DSI HS Tile Configuration; Horizontal Segmentation 3" group.byte 0x94++0x00 line.byte 0x00 "HS4,DSI HS Tile Configuration; Horizontal Segmentation 4" group.byte 0x95++0x00 line.byte 0x00 "HS5,DSI HS Tile Configuration; Horizontal Segmentation 5" group.byte 0x96++0x00 line.byte 0x00 "HS6,DSI HS Tile Configuration; Horizontal Segmentation 6" group.byte 0x97++0x00 line.byte 0x00 "HS7,DSI HS Tile Configuration; Horizontal Segmentation 7" group.byte 0x98++0x00 line.byte 0x00 "HS8,DSI HS Tile Configuration; Horizontal Segmentation 8" group.byte 0x99++0x00 line.byte 0x00 "HS9,DSI HS Tile Configuration; Horizontal Segmentation 9" group.byte 0x9A++0x00 line.byte 0x00 "HS10,DSI HS Tile Configuration; Horizontal Segmentation 10" group.byte 0x9B++0x00 line.byte 0x00 "HS11,DSI HS Tile Configuration; Horizontal Segmentation 11" group.byte 0x9C++0x00 line.byte 0x00 "HS12,DSI HS Tile Configuration; Horizontal Segmentation 12" group.byte 0x9D++0x00 line.byte 0x00 "HS13,DSI HS Tile Configuration; Horizontal Segmentation 13" group.byte 0x9E++0x00 line.byte 0x00 "HS14,DSI HS Tile Configuration; Horizontal Segmentation 14" group.byte 0x9F++0x00 line.byte 0x00 "HS15,DSI HS Tile Configuration; Horizontal Segmentation 15" group.byte 0xA0++0x00 line.byte 0x00 "HS16,DSI HS Tile Configuration; Horizontal Segmentation 16" group.byte 0xA1++0x00 line.byte 0x00 "HS17,DSI HS Tile Configuration; Horizontal Segmentation 17" group.byte 0xA2++0x00 line.byte 0x00 "HS18,DSI HS Tile Configuration; Horizontal Segmentation 18" group.byte 0xA3++0x00 line.byte 0x00 "HS19,DSI HS Tile Configuration; Horizontal Segmentation 19" group.byte 0xA4++0x00 line.byte 0x00 "HS20,DSI HS Tile Configuration; Horizontal Segmentation 20" group.byte 0xA5++0x00 line.byte 0x00 "HS21,DSI HS Tile Configuration; Horizontal Segmentation 21" group.byte 0xA6++0x00 line.byte 0x00 "HS22,DSI HS Tile Configuration; Horizontal Segmentation 22" group.byte 0xA7++0x00 line.byte 0x00 "HS23,DSI HS Tile Configuration; Horizontal Segmentation 23" group.byte 0xA8++0x00 line.byte 0x00 "HV_R0,DSI HV Tile Configuration; Right 0" group.byte 0xA9++0x00 line.byte 0x00 "HV_R1,DSI HV Tile Configuration; Right 1" group.byte 0xAA++0x00 line.byte 0x00 "HV_R2,DSI HV Tile Configuration; Right 2" group.byte 0xAB++0x00 line.byte 0x00 "HV_R3,DSI HV Tile Configuration; Right 3" group.byte 0xAC++0x00 line.byte 0x00 "HV_R4,DSI HV Tile Configuration; Right 4" group.byte 0xAD++0x00 line.byte 0x00 "HV_R5,DSI HV Tile Configuration; Right 5" group.byte 0xAE++0x00 line.byte 0x00 "HV_R6,DSI HV Tile Configuration; Right 6" group.byte 0xAF++0x00 line.byte 0x00 "HV_R7,DSI HV Tile Configuration; Right 7" group.byte 0xB0++0x00 line.byte 0x00 "HV_R8,DSI HV Tile Configuration; Right 8" group.byte 0xB1++0x00 line.byte 0x00 "HV_R9,DSI HV Tile Configuration; Right 9" group.byte 0xB2++0x00 line.byte 0x00 "HV_R10,DSI HV Tile Configuration; Right 10" group.byte 0xB3++0x00 line.byte 0x00 "HV_R11,DSI HV Tile Configuration; Right 11" group.byte 0xB4++0x00 line.byte 0x00 "HV_R12,DSI HV Tile Configuration; Right 12" group.byte 0xB5++0x00 line.byte 0x00 "HV_R13,DSI HV Tile Configuration; Right 13" group.byte 0xB6++0x00 line.byte 0x00 "HV_R14,DSI HV Tile Configuration; Right 14" group.byte 0xB7++0x00 line.byte 0x00 "HV_R15,DSI HV Tile Configuration; Right 15" group.word 0xC0++0x01 line.word 0x00 "DSIINP0,DSI PI Tile Configuration For DSI I/O; Input 0" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xC2++0x01 line.word 0x00 "DSIINP1,DSI PI Tile Configuration For DSI I/O; Input 1" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xC4++0x01 line.word 0x00 "DSIINP2,DSI PI Tile Configuration For DSI I/O; Input 2" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xC6++0x01 line.word 0x00 "DSIINP3,DSI PI Tile Configuration For DSI I/O; Input 3" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xC8++0x01 line.word 0x00 "DSIINP4,DSI PI Tile Configuration For DSI I/O; Input 4" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xCA++0x01 line.word 0x00 "DSIINP5,DSI PI Tile Configuration For DSI I/O; Input 5" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xCC++0x01 line.word 0x00 "DSIOUTP0,DSI PI Tile Configuration For DSI I/O; Output Pair 0" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xCE++0x01 line.word 0x00 "DSIOUTP1,DSI PI Tile Configuration For DSI I/O; Output Pair 1" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xD0++0x01 line.word 0x00 "DSIOUTP2,DSI PI Tile Configuration For DSI I/O; Output Pair 2" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xD2++0x01 line.word 0x00 "DSIOUTP3,DSI PI Tile Configuration For DSI I/O; Output Pair 3" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xD4++0x01 line.word 0x00 "DSIOUTT0,DSI PI Tile Configuration For DSI I/O; Output Triplet 0" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xD6++0x01 line.word 0x00 "DSIOUTT1,DSI PI Tile Configuration For DSI I/O; Output Triplet 1" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xD8++0x01 line.word 0x00 "DSIOUTT2,DSI PI Tile Configuration For DSI I/O; Output Triplet 2" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xDA++0x01 line.word 0x00 "DSIOUTT3,DSI PI Tile Configuration For DSI I/O; Output Triplet 3" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xDC++0x01 line.word 0x00 "DSIOUTT4,DSI PI Tile Configuration For DSI I/O; Output Triplet 4" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xDE++0x01 line.word 0x00 "DSIOUTT5,DSI PI Tile Configuration For DSI I/O; Output Triplet 5" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE0++0x01 line.word 0x00 "VS0,DSI VS Tile Configuration; Vertical Segmentation 0" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE2++0x01 line.word 0x00 "VS1,DSI VS Tile Configuration; Vertical Segmentation 1" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE4++0x01 line.word 0x00 "VS2,DSI VS Tile Configuration; Vertical Segmentation 2" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE6++0x01 line.word 0x00 "VS3,DSI VS Tile Configuration; Vertical Segmentation 3" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE8++0x01 line.word 0x00 "VS4,DSI VS Tile Configuration; Vertical Segmentation 4" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xEA++0x01 line.word 0x00 "VS5,DSI VS Tile Configuration; Vertical Segmentation 5" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xEC++0x01 line.word 0x00 "VS6,DSI VS Tile Configuration; Vertical Segmentation 6" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xEE++0x01 line.word 0x00 "VS7,DSI VS Tile Configuration; Vertical Segmentation 7" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree "UDB_DSI5" base ad:0x400F4500 width 15. group.byte 0x0++0x00 line.byte 0x00 "HC0,DSI HC Tile Configuration 0" group.byte 0x1++0x00 line.byte 0x00 "HC1,DSI HC Tile Configuration 1" group.byte 0x2++0x00 line.byte 0x00 "HC2,DSI HC Tile Configuration 2" group.byte 0x3++0x00 line.byte 0x00 "HC3,DSI HC Tile Configuration 3" group.byte 0x4++0x00 line.byte 0x00 "HC4,DSI HC Tile Configuration 4" group.byte 0x5++0x00 line.byte 0x00 "HC5,DSI HC Tile Configuration 5" group.byte 0x6++0x00 line.byte 0x00 "HC6,DSI HC Tile Configuration 6" group.byte 0x7++0x00 line.byte 0x00 "HC7,DSI HC Tile Configuration 7" group.byte 0x8++0x00 line.byte 0x00 "HC8,DSI HC Tile Configuration 8" group.byte 0x9++0x00 line.byte 0x00 "HC9,DSI HC Tile Configuration 9" group.byte 0xA++0x00 line.byte 0x00 "HC10,DSI HC Tile Configuration 10" group.byte 0xB++0x00 line.byte 0x00 "HC11,DSI HC Tile Configuration 11" group.byte 0xC++0x00 line.byte 0x00 "HC12,DSI HC Tile Configuration 12" group.byte 0xD++0x00 line.byte 0x00 "HC13,DSI HC Tile Configuration 13" group.byte 0xE++0x00 line.byte 0x00 "HC14,DSI HC Tile Configuration 14" group.byte 0xF++0x00 line.byte 0x00 "HC15,DSI HC Tile Configuration 15" group.byte 0x10++0x00 line.byte 0x00 "HC16,DSI HC Tile Configuration 16" group.byte 0x11++0x00 line.byte 0x00 "HC17,DSI HC Tile Configuration 17" group.byte 0x12++0x00 line.byte 0x00 "HC18,DSI HC Tile Configuration 18" group.byte 0x13++0x00 line.byte 0x00 "HC19,DSI HC Tile Configuration 19" group.byte 0x14++0x00 line.byte 0x00 "HC20,DSI HC Tile Configuration 20" group.byte 0x15++0x00 line.byte 0x00 "HC21,DSI HC Tile Configuration 21" group.byte 0x16++0x00 line.byte 0x00 "HC22,DSI HC Tile Configuration 22" group.byte 0x17++0x00 line.byte 0x00 "HC23,DSI HC Tile Configuration 23" group.byte 0x18++0x00 line.byte 0x00 "HC24,DSI HC Tile Configuration 24" group.byte 0x19++0x00 line.byte 0x00 "HC25,DSI HC Tile Configuration 25" group.byte 0x1A++0x00 line.byte 0x00 "HC26,DSI HC Tile Configuration 26" group.byte 0x1B++0x00 line.byte 0x00 "HC27,DSI HC Tile Configuration 27" group.byte 0x1C++0x00 line.byte 0x00 "HC28,DSI HC Tile Configuration 28" group.byte 0x1D++0x00 line.byte 0x00 "HC29,DSI HC Tile Configuration 29" group.byte 0x1E++0x00 line.byte 0x00 "HC30,DSI HC Tile Configuration 30" group.byte 0x1F++0x00 line.byte 0x00 "HC31,DSI HC Tile Configuration 31" group.byte 0x20++0x00 line.byte 0x00 "HC32,DSI HC Tile Configuration 32" group.byte 0x21++0x00 line.byte 0x00 "HC33,DSI HC Tile Configuration 33" group.byte 0x22++0x00 line.byte 0x00 "HC34,DSI HC Tile Configuration 34" group.byte 0x23++0x00 line.byte 0x00 "HC35,DSI HC Tile Configuration 35" group.byte 0x24++0x00 line.byte 0x00 "HC36,DSI HC Tile Configuration 36" group.byte 0x25++0x00 line.byte 0x00 "HC37,DSI HC Tile Configuration 37" group.byte 0x26++0x00 line.byte 0x00 "HC38,DSI HC Tile Configuration 38" group.byte 0x27++0x00 line.byte 0x00 "HC39,DSI HC Tile Configuration 39" group.byte 0x28++0x00 line.byte 0x00 "HC40,DSI HC Tile Configuration 40" group.byte 0x29++0x00 line.byte 0x00 "HC41,DSI HC Tile Configuration 41" group.byte 0x2A++0x00 line.byte 0x00 "HC42,DSI HC Tile Configuration 42" group.byte 0x2B++0x00 line.byte 0x00 "HC43,DSI HC Tile Configuration 43" group.byte 0x2C++0x00 line.byte 0x00 "HC44,DSI HC Tile Configuration 44" group.byte 0x2D++0x00 line.byte 0x00 "HC45,DSI HC Tile Configuration 45" group.byte 0x2E++0x00 line.byte 0x00 "HC46,DSI HC Tile Configuration 46" group.byte 0x2F++0x00 line.byte 0x00 "HC47,DSI HC Tile Configuration 47" group.byte 0x30++0x00 line.byte 0x00 "HC48,DSI HC Tile Configuration 48" group.byte 0x31++0x00 line.byte 0x00 "HC49,DSI HC Tile Configuration 49" group.byte 0x32++0x00 line.byte 0x00 "HC50,DSI HC Tile Configuration 50" group.byte 0x33++0x00 line.byte 0x00 "HC51,DSI HC Tile Configuration 51" group.byte 0x34++0x00 line.byte 0x00 "HC52,DSI HC Tile Configuration 52" group.byte 0x35++0x00 line.byte 0x00 "HC53,DSI HC Tile Configuration 53" group.byte 0x36++0x00 line.byte 0x00 "HC54,DSI HC Tile Configuration 54" group.byte 0x37++0x00 line.byte 0x00 "HC55,DSI HC Tile Configuration 55" group.byte 0x38++0x00 line.byte 0x00 "HC56,DSI HC Tile Configuration 56" group.byte 0x39++0x00 line.byte 0x00 "HC57,DSI HC Tile Configuration 57" group.byte 0x3A++0x00 line.byte 0x00 "HC58,DSI HC Tile Configuration 58" group.byte 0x3B++0x00 line.byte 0x00 "HC59,DSI HC Tile Configuration 59" group.byte 0x3C++0x00 line.byte 0x00 "HC60,DSI HC Tile Configuration 60" group.byte 0x3D++0x00 line.byte 0x00 "HC61,DSI HC Tile Configuration 61" group.byte 0x3E++0x00 line.byte 0x00 "HC62,DSI HC Tile Configuration 62" group.byte 0x3F++0x00 line.byte 0x00 "HC63,DSI HC Tile Configuration 63" group.byte 0x40++0x00 line.byte 0x00 "HC64,DSI HC Tile Configuration 64" group.byte 0x41++0x00 line.byte 0x00 "HC65,DSI HC Tile Configuration 65" group.byte 0x42++0x00 line.byte 0x00 "HC66,DSI HC Tile Configuration 66" group.byte 0x43++0x00 line.byte 0x00 "HC67,DSI HC Tile Configuration 67" group.byte 0x44++0x00 line.byte 0x00 "HC68,DSI HC Tile Configuration 68" group.byte 0x45++0x00 line.byte 0x00 "HC69,DSI HC Tile Configuration 69" group.byte 0x46++0x00 line.byte 0x00 "HC70,DSI HC Tile Configuration 70" group.byte 0x47++0x00 line.byte 0x00 "HC71,DSI HC Tile Configuration 71" group.byte 0x48++0x00 line.byte 0x00 "HC72,DSI HC Tile Configuration 72" group.byte 0x49++0x00 line.byte 0x00 "HC73,DSI HC Tile Configuration 73" group.byte 0x4A++0x00 line.byte 0x00 "HC74,DSI HC Tile Configuration 74" group.byte 0x4B++0x00 line.byte 0x00 "HC75,DSI HC Tile Configuration 75" group.byte 0x4C++0x00 line.byte 0x00 "HC76,DSI HC Tile Configuration 76" group.byte 0x4D++0x00 line.byte 0x00 "HC77,DSI HC Tile Configuration 77" group.byte 0x4E++0x00 line.byte 0x00 "HC78,DSI HC Tile Configuration 78" group.byte 0x4F++0x00 line.byte 0x00 "HC79,DSI HC Tile Configuration 79" group.byte 0x50++0x00 line.byte 0x00 "HC80,DSI HC Tile Configuration 80" group.byte 0x51++0x00 line.byte 0x00 "HC81,DSI HC Tile Configuration 81" group.byte 0x52++0x00 line.byte 0x00 "HC82,DSI HC Tile Configuration 82" group.byte 0x53++0x00 line.byte 0x00 "HC83,DSI HC Tile Configuration 83" group.byte 0x54++0x00 line.byte 0x00 "HC84,DSI HC Tile Configuration 84" group.byte 0x55++0x00 line.byte 0x00 "HC85,DSI HC Tile Configuration 85" group.byte 0x56++0x00 line.byte 0x00 "HC86,DSI HC Tile Configuration 86" group.byte 0x57++0x00 line.byte 0x00 "HC87,DSI HC Tile Configuration 87" group.byte 0x58++0x00 line.byte 0x00 "HC88,DSI HC Tile Configuration 88" group.byte 0x59++0x00 line.byte 0x00 "HC89,DSI HC Tile Configuration 89" group.byte 0x5A++0x00 line.byte 0x00 "HC90,DSI HC Tile Configuration 90" group.byte 0x5B++0x00 line.byte 0x00 "HC91,DSI HC Tile Configuration 91" group.byte 0x5C++0x00 line.byte 0x00 "HC92,DSI HC Tile Configuration 92" group.byte 0x5D++0x00 line.byte 0x00 "HC93,DSI HC Tile Configuration 93" group.byte 0x5E++0x00 line.byte 0x00 "HC94,DSI HC Tile Configuration 94" group.byte 0x5F++0x00 line.byte 0x00 "HC95,DSI HC Tile Configuration 95" group.byte 0x60++0x00 line.byte 0x00 "HC96,DSI HC Tile Configuration 96" group.byte 0x61++0x00 line.byte 0x00 "HC97,DSI HC Tile Configuration 97" group.byte 0x62++0x00 line.byte 0x00 "HC98,DSI HC Tile Configuration 98" group.byte 0x63++0x00 line.byte 0x00 "HC99,DSI HC Tile Configuration 99" group.byte 0x64++0x00 line.byte 0x00 "HC100,DSI HC Tile Configuration 100" group.byte 0x65++0x00 line.byte 0x00 "HC101,DSI HC Tile Configuration 101" group.byte 0x66++0x00 line.byte 0x00 "HC102,DSI HC Tile Configuration 102" group.byte 0x67++0x00 line.byte 0x00 "HC103,DSI HC Tile Configuration 103" group.byte 0x68++0x00 line.byte 0x00 "HC104,DSI HC Tile Configuration 104" group.byte 0x69++0x00 line.byte 0x00 "HC105,DSI HC Tile Configuration 105" group.byte 0x6A++0x00 line.byte 0x00 "HC106,DSI HC Tile Configuration 106" group.byte 0x6B++0x00 line.byte 0x00 "HC107,DSI HC Tile Configuration 107" group.byte 0x6C++0x00 line.byte 0x00 "HC108,DSI HC Tile Configuration 108" group.byte 0x6D++0x00 line.byte 0x00 "HC109,DSI HC Tile Configuration 109" group.byte 0x6E++0x00 line.byte 0x00 "HC110,DSI HC Tile Configuration 110" group.byte 0x6F++0x00 line.byte 0x00 "HC111,DSI HC Tile Configuration 111" group.byte 0x70++0x00 line.byte 0x00 "HC112,DSI HC Tile Configuration 112" group.byte 0x71++0x00 line.byte 0x00 "HC113,DSI HC Tile Configuration 113" group.byte 0x72++0x00 line.byte 0x00 "HC114,DSI HC Tile Configuration 114" group.byte 0x73++0x00 line.byte 0x00 "HC115,DSI HC Tile Configuration 115" group.byte 0x74++0x00 line.byte 0x00 "HC116,DSI HC Tile Configuration 116" group.byte 0x75++0x00 line.byte 0x00 "HC117,DSI HC Tile Configuration 117" group.byte 0x76++0x00 line.byte 0x00 "HC118,DSI HC Tile Configuration 118" group.byte 0x77++0x00 line.byte 0x00 "HC119,DSI HC Tile Configuration 119" group.byte 0x78++0x00 line.byte 0x00 "HC120,DSI HC Tile Configuration 120" group.byte 0x79++0x00 line.byte 0x00 "HC121,DSI HC Tile Configuration 121" group.byte 0x7A++0x00 line.byte 0x00 "HC122,DSI HC Tile Configuration 122" group.byte 0x7B++0x00 line.byte 0x00 "HC123,DSI HC Tile Configuration 123" group.byte 0x7C++0x00 line.byte 0x00 "HC124,DSI HC Tile Configuration 124" group.byte 0x7D++0x00 line.byte 0x00 "HC125,DSI HC Tile Configuration 125" group.byte 0x7E++0x00 line.byte 0x00 "HC126,DSI HC Tile Configuration 126" group.byte 0x7F++0x00 line.byte 0x00 "HC127,DSI HC Tile Configuration 127" group.byte 0x80++0x00 line.byte 0x00 "HV_L0,DSI HV Tile Configuration; Left 0" group.byte 0x81++0x00 line.byte 0x00 "HV_L1,DSI HV Tile Configuration; Left 1" group.byte 0x82++0x00 line.byte 0x00 "HV_L2,DSI HV Tile Configuration; Left 2" group.byte 0x83++0x00 line.byte 0x00 "HV_L3,DSI HV Tile Configuration; Left 3" group.byte 0x84++0x00 line.byte 0x00 "HV_L4,DSI HV Tile Configuration; Left 4" group.byte 0x85++0x00 line.byte 0x00 "HV_L5,DSI HV Tile Configuration; Left 5" group.byte 0x86++0x00 line.byte 0x00 "HV_L6,DSI HV Tile Configuration; Left 6" group.byte 0x87++0x00 line.byte 0x00 "HV_L7,DSI HV Tile Configuration; Left 7" group.byte 0x88++0x00 line.byte 0x00 "HV_L8,DSI HV Tile Configuration; Left 8" group.byte 0x89++0x00 line.byte 0x00 "HV_L9,DSI HV Tile Configuration; Left 9" group.byte 0x8A++0x00 line.byte 0x00 "HV_L10,DSI HV Tile Configuration; Left 10" group.byte 0x8B++0x00 line.byte 0x00 "HV_L11,DSI HV Tile Configuration; Left 11" group.byte 0x8C++0x00 line.byte 0x00 "HV_L12,DSI HV Tile Configuration; Left 12" group.byte 0x8D++0x00 line.byte 0x00 "HV_L13,DSI HV Tile Configuration; Left 13" group.byte 0x8E++0x00 line.byte 0x00 "HV_L14,DSI HV Tile Configuration; Left 14" group.byte 0x8F++0x00 line.byte 0x00 "HV_L15,DSI HV Tile Configuration; Left 15" group.byte 0x90++0x00 line.byte 0x00 "HS0,DSI HS Tile Configuration; Horizontal Segmentation 0" group.byte 0x91++0x00 line.byte 0x00 "HS1,DSI HS Tile Configuration; Horizontal Segmentation 1" group.byte 0x92++0x00 line.byte 0x00 "HS2,DSI HS Tile Configuration; Horizontal Segmentation 2" group.byte 0x93++0x00 line.byte 0x00 "HS3,DSI HS Tile Configuration; Horizontal Segmentation 3" group.byte 0x94++0x00 line.byte 0x00 "HS4,DSI HS Tile Configuration; Horizontal Segmentation 4" group.byte 0x95++0x00 line.byte 0x00 "HS5,DSI HS Tile Configuration; Horizontal Segmentation 5" group.byte 0x96++0x00 line.byte 0x00 "HS6,DSI HS Tile Configuration; Horizontal Segmentation 6" group.byte 0x97++0x00 line.byte 0x00 "HS7,DSI HS Tile Configuration; Horizontal Segmentation 7" group.byte 0x98++0x00 line.byte 0x00 "HS8,DSI HS Tile Configuration; Horizontal Segmentation 8" group.byte 0x99++0x00 line.byte 0x00 "HS9,DSI HS Tile Configuration; Horizontal Segmentation 9" group.byte 0x9A++0x00 line.byte 0x00 "HS10,DSI HS Tile Configuration; Horizontal Segmentation 10" group.byte 0x9B++0x00 line.byte 0x00 "HS11,DSI HS Tile Configuration; Horizontal Segmentation 11" group.byte 0x9C++0x00 line.byte 0x00 "HS12,DSI HS Tile Configuration; Horizontal Segmentation 12" group.byte 0x9D++0x00 line.byte 0x00 "HS13,DSI HS Tile Configuration; Horizontal Segmentation 13" group.byte 0x9E++0x00 line.byte 0x00 "HS14,DSI HS Tile Configuration; Horizontal Segmentation 14" group.byte 0x9F++0x00 line.byte 0x00 "HS15,DSI HS Tile Configuration; Horizontal Segmentation 15" group.byte 0xA0++0x00 line.byte 0x00 "HS16,DSI HS Tile Configuration; Horizontal Segmentation 16" group.byte 0xA1++0x00 line.byte 0x00 "HS17,DSI HS Tile Configuration; Horizontal Segmentation 17" group.byte 0xA2++0x00 line.byte 0x00 "HS18,DSI HS Tile Configuration; Horizontal Segmentation 18" group.byte 0xA3++0x00 line.byte 0x00 "HS19,DSI HS Tile Configuration; Horizontal Segmentation 19" group.byte 0xA4++0x00 line.byte 0x00 "HS20,DSI HS Tile Configuration; Horizontal Segmentation 20" group.byte 0xA5++0x00 line.byte 0x00 "HS21,DSI HS Tile Configuration; Horizontal Segmentation 21" group.byte 0xA6++0x00 line.byte 0x00 "HS22,DSI HS Tile Configuration; Horizontal Segmentation 22" group.byte 0xA7++0x00 line.byte 0x00 "HS23,DSI HS Tile Configuration; Horizontal Segmentation 23" group.byte 0xA8++0x00 line.byte 0x00 "HV_R0,DSI HV Tile Configuration; Right 0" group.byte 0xA9++0x00 line.byte 0x00 "HV_R1,DSI HV Tile Configuration; Right 1" group.byte 0xAA++0x00 line.byte 0x00 "HV_R2,DSI HV Tile Configuration; Right 2" group.byte 0xAB++0x00 line.byte 0x00 "HV_R3,DSI HV Tile Configuration; Right 3" group.byte 0xAC++0x00 line.byte 0x00 "HV_R4,DSI HV Tile Configuration; Right 4" group.byte 0xAD++0x00 line.byte 0x00 "HV_R5,DSI HV Tile Configuration; Right 5" group.byte 0xAE++0x00 line.byte 0x00 "HV_R6,DSI HV Tile Configuration; Right 6" group.byte 0xAF++0x00 line.byte 0x00 "HV_R7,DSI HV Tile Configuration; Right 7" group.byte 0xB0++0x00 line.byte 0x00 "HV_R8,DSI HV Tile Configuration; Right 8" group.byte 0xB1++0x00 line.byte 0x00 "HV_R9,DSI HV Tile Configuration; Right 9" group.byte 0xB2++0x00 line.byte 0x00 "HV_R10,DSI HV Tile Configuration; Right 10" group.byte 0xB3++0x00 line.byte 0x00 "HV_R11,DSI HV Tile Configuration; Right 11" group.byte 0xB4++0x00 line.byte 0x00 "HV_R12,DSI HV Tile Configuration; Right 12" group.byte 0xB5++0x00 line.byte 0x00 "HV_R13,DSI HV Tile Configuration; Right 13" group.byte 0xB6++0x00 line.byte 0x00 "HV_R14,DSI HV Tile Configuration; Right 14" group.byte 0xB7++0x00 line.byte 0x00 "HV_R15,DSI HV Tile Configuration; Right 15" group.word 0xC0++0x01 line.word 0x00 "DSIINP0,DSI PI Tile Configuration For DSI I/O; Input 0" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xC2++0x01 line.word 0x00 "DSIINP1,DSI PI Tile Configuration For DSI I/O; Input 1" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xC4++0x01 line.word 0x00 "DSIINP2,DSI PI Tile Configuration For DSI I/O; Input 2" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xC6++0x01 line.word 0x00 "DSIINP3,DSI PI Tile Configuration For DSI I/O; Input 3" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xC8++0x01 line.word 0x00 "DSIINP4,DSI PI Tile Configuration For DSI I/O; Input 4" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xCA++0x01 line.word 0x00 "DSIINP5,DSI PI Tile Configuration For DSI I/O; Input 5" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xCC++0x01 line.word 0x00 "DSIOUTP0,DSI PI Tile Configuration For DSI I/O; Output Pair 0" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xCE++0x01 line.word 0x00 "DSIOUTP1,DSI PI Tile Configuration For DSI I/O; Output Pair 1" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xD0++0x01 line.word 0x00 "DSIOUTP2,DSI PI Tile Configuration For DSI I/O; Output Pair 2" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xD2++0x01 line.word 0x00 "DSIOUTP3,DSI PI Tile Configuration For DSI I/O; Output Pair 3" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xD4++0x01 line.word 0x00 "DSIOUTT0,DSI PI Tile Configuration For DSI I/O; Output Triplet 0" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xD6++0x01 line.word 0x00 "DSIOUTT1,DSI PI Tile Configuration For DSI I/O; Output Triplet 1" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xD8++0x01 line.word 0x00 "DSIOUTT2,DSI PI Tile Configuration For DSI I/O; Output Triplet 2" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xDA++0x01 line.word 0x00 "DSIOUTT3,DSI PI Tile Configuration For DSI I/O; Output Triplet 3" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xDC++0x01 line.word 0x00 "DSIOUTT4,DSI PI Tile Configuration For DSI I/O; Output Triplet 4" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xDE++0x01 line.word 0x00 "DSIOUTT5,DSI PI Tile Configuration For DSI I/O; Output Triplet 5" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE0++0x01 line.word 0x00 "VS0,DSI VS Tile Configuration; Vertical Segmentation 0" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE2++0x01 line.word 0x00 "VS1,DSI VS Tile Configuration; Vertical Segmentation 1" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE4++0x01 line.word 0x00 "VS2,DSI VS Tile Configuration; Vertical Segmentation 2" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE6++0x01 line.word 0x00 "VS3,DSI VS Tile Configuration; Vertical Segmentation 3" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE8++0x01 line.word 0x00 "VS4,DSI VS Tile Configuration; Vertical Segmentation 4" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xEA++0x01 line.word 0x00 "VS5,DSI VS Tile Configuration; Vertical Segmentation 5" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xEC++0x01 line.word 0x00 "VS6,DSI VS Tile Configuration; Vertical Segmentation 6" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xEE++0x01 line.word 0x00 "VS7,DSI VS Tile Configuration; Vertical Segmentation 7" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree "UDB_DSI6" base ad:0x400F4600 width 15. group.byte 0x0++0x00 line.byte 0x00 "HC0,DSI HC Tile Configuration 0" group.byte 0x1++0x00 line.byte 0x00 "HC1,DSI HC Tile Configuration 1" group.byte 0x2++0x00 line.byte 0x00 "HC2,DSI HC Tile Configuration 2" group.byte 0x3++0x00 line.byte 0x00 "HC3,DSI HC Tile Configuration 3" group.byte 0x4++0x00 line.byte 0x00 "HC4,DSI HC Tile Configuration 4" group.byte 0x5++0x00 line.byte 0x00 "HC5,DSI HC Tile Configuration 5" group.byte 0x6++0x00 line.byte 0x00 "HC6,DSI HC Tile Configuration 6" group.byte 0x7++0x00 line.byte 0x00 "HC7,DSI HC Tile Configuration 7" group.byte 0x8++0x00 line.byte 0x00 "HC8,DSI HC Tile Configuration 8" group.byte 0x9++0x00 line.byte 0x00 "HC9,DSI HC Tile Configuration 9" group.byte 0xA++0x00 line.byte 0x00 "HC10,DSI HC Tile Configuration 10" group.byte 0xB++0x00 line.byte 0x00 "HC11,DSI HC Tile Configuration 11" group.byte 0xC++0x00 line.byte 0x00 "HC12,DSI HC Tile Configuration 12" group.byte 0xD++0x00 line.byte 0x00 "HC13,DSI HC Tile Configuration 13" group.byte 0xE++0x00 line.byte 0x00 "HC14,DSI HC Tile Configuration 14" group.byte 0xF++0x00 line.byte 0x00 "HC15,DSI HC Tile Configuration 15" group.byte 0x10++0x00 line.byte 0x00 "HC16,DSI HC Tile Configuration 16" group.byte 0x11++0x00 line.byte 0x00 "HC17,DSI HC Tile Configuration 17" group.byte 0x12++0x00 line.byte 0x00 "HC18,DSI HC Tile Configuration 18" group.byte 0x13++0x00 line.byte 0x00 "HC19,DSI HC Tile Configuration 19" group.byte 0x14++0x00 line.byte 0x00 "HC20,DSI HC Tile Configuration 20" group.byte 0x15++0x00 line.byte 0x00 "HC21,DSI HC Tile Configuration 21" group.byte 0x16++0x00 line.byte 0x00 "HC22,DSI HC Tile Configuration 22" group.byte 0x17++0x00 line.byte 0x00 "HC23,DSI HC Tile Configuration 23" group.byte 0x18++0x00 line.byte 0x00 "HC24,DSI HC Tile Configuration 24" group.byte 0x19++0x00 line.byte 0x00 "HC25,DSI HC Tile Configuration 25" group.byte 0x1A++0x00 line.byte 0x00 "HC26,DSI HC Tile Configuration 26" group.byte 0x1B++0x00 line.byte 0x00 "HC27,DSI HC Tile Configuration 27" group.byte 0x1C++0x00 line.byte 0x00 "HC28,DSI HC Tile Configuration 28" group.byte 0x1D++0x00 line.byte 0x00 "HC29,DSI HC Tile Configuration 29" group.byte 0x1E++0x00 line.byte 0x00 "HC30,DSI HC Tile Configuration 30" group.byte 0x1F++0x00 line.byte 0x00 "HC31,DSI HC Tile Configuration 31" group.byte 0x20++0x00 line.byte 0x00 "HC32,DSI HC Tile Configuration 32" group.byte 0x21++0x00 line.byte 0x00 "HC33,DSI HC Tile Configuration 33" group.byte 0x22++0x00 line.byte 0x00 "HC34,DSI HC Tile Configuration 34" group.byte 0x23++0x00 line.byte 0x00 "HC35,DSI HC Tile Configuration 35" group.byte 0x24++0x00 line.byte 0x00 "HC36,DSI HC Tile Configuration 36" group.byte 0x25++0x00 line.byte 0x00 "HC37,DSI HC Tile Configuration 37" group.byte 0x26++0x00 line.byte 0x00 "HC38,DSI HC Tile Configuration 38" group.byte 0x27++0x00 line.byte 0x00 "HC39,DSI HC Tile Configuration 39" group.byte 0x28++0x00 line.byte 0x00 "HC40,DSI HC Tile Configuration 40" group.byte 0x29++0x00 line.byte 0x00 "HC41,DSI HC Tile Configuration 41" group.byte 0x2A++0x00 line.byte 0x00 "HC42,DSI HC Tile Configuration 42" group.byte 0x2B++0x00 line.byte 0x00 "HC43,DSI HC Tile Configuration 43" group.byte 0x2C++0x00 line.byte 0x00 "HC44,DSI HC Tile Configuration 44" group.byte 0x2D++0x00 line.byte 0x00 "HC45,DSI HC Tile Configuration 45" group.byte 0x2E++0x00 line.byte 0x00 "HC46,DSI HC Tile Configuration 46" group.byte 0x2F++0x00 line.byte 0x00 "HC47,DSI HC Tile Configuration 47" group.byte 0x30++0x00 line.byte 0x00 "HC48,DSI HC Tile Configuration 48" group.byte 0x31++0x00 line.byte 0x00 "HC49,DSI HC Tile Configuration 49" group.byte 0x32++0x00 line.byte 0x00 "HC50,DSI HC Tile Configuration 50" group.byte 0x33++0x00 line.byte 0x00 "HC51,DSI HC Tile Configuration 51" group.byte 0x34++0x00 line.byte 0x00 "HC52,DSI HC Tile Configuration 52" group.byte 0x35++0x00 line.byte 0x00 "HC53,DSI HC Tile Configuration 53" group.byte 0x36++0x00 line.byte 0x00 "HC54,DSI HC Tile Configuration 54" group.byte 0x37++0x00 line.byte 0x00 "HC55,DSI HC Tile Configuration 55" group.byte 0x38++0x00 line.byte 0x00 "HC56,DSI HC Tile Configuration 56" group.byte 0x39++0x00 line.byte 0x00 "HC57,DSI HC Tile Configuration 57" group.byte 0x3A++0x00 line.byte 0x00 "HC58,DSI HC Tile Configuration 58" group.byte 0x3B++0x00 line.byte 0x00 "HC59,DSI HC Tile Configuration 59" group.byte 0x3C++0x00 line.byte 0x00 "HC60,DSI HC Tile Configuration 60" group.byte 0x3D++0x00 line.byte 0x00 "HC61,DSI HC Tile Configuration 61" group.byte 0x3E++0x00 line.byte 0x00 "HC62,DSI HC Tile Configuration 62" group.byte 0x3F++0x00 line.byte 0x00 "HC63,DSI HC Tile Configuration 63" group.byte 0x40++0x00 line.byte 0x00 "HC64,DSI HC Tile Configuration 64" group.byte 0x41++0x00 line.byte 0x00 "HC65,DSI HC Tile Configuration 65" group.byte 0x42++0x00 line.byte 0x00 "HC66,DSI HC Tile Configuration 66" group.byte 0x43++0x00 line.byte 0x00 "HC67,DSI HC Tile Configuration 67" group.byte 0x44++0x00 line.byte 0x00 "HC68,DSI HC Tile Configuration 68" group.byte 0x45++0x00 line.byte 0x00 "HC69,DSI HC Tile Configuration 69" group.byte 0x46++0x00 line.byte 0x00 "HC70,DSI HC Tile Configuration 70" group.byte 0x47++0x00 line.byte 0x00 "HC71,DSI HC Tile Configuration 71" group.byte 0x48++0x00 line.byte 0x00 "HC72,DSI HC Tile Configuration 72" group.byte 0x49++0x00 line.byte 0x00 "HC73,DSI HC Tile Configuration 73" group.byte 0x4A++0x00 line.byte 0x00 "HC74,DSI HC Tile Configuration 74" group.byte 0x4B++0x00 line.byte 0x00 "HC75,DSI HC Tile Configuration 75" group.byte 0x4C++0x00 line.byte 0x00 "HC76,DSI HC Tile Configuration 76" group.byte 0x4D++0x00 line.byte 0x00 "HC77,DSI HC Tile Configuration 77" group.byte 0x4E++0x00 line.byte 0x00 "HC78,DSI HC Tile Configuration 78" group.byte 0x4F++0x00 line.byte 0x00 "HC79,DSI HC Tile Configuration 79" group.byte 0x50++0x00 line.byte 0x00 "HC80,DSI HC Tile Configuration 80" group.byte 0x51++0x00 line.byte 0x00 "HC81,DSI HC Tile Configuration 81" group.byte 0x52++0x00 line.byte 0x00 "HC82,DSI HC Tile Configuration 82" group.byte 0x53++0x00 line.byte 0x00 "HC83,DSI HC Tile Configuration 83" group.byte 0x54++0x00 line.byte 0x00 "HC84,DSI HC Tile Configuration 84" group.byte 0x55++0x00 line.byte 0x00 "HC85,DSI HC Tile Configuration 85" group.byte 0x56++0x00 line.byte 0x00 "HC86,DSI HC Tile Configuration 86" group.byte 0x57++0x00 line.byte 0x00 "HC87,DSI HC Tile Configuration 87" group.byte 0x58++0x00 line.byte 0x00 "HC88,DSI HC Tile Configuration 88" group.byte 0x59++0x00 line.byte 0x00 "HC89,DSI HC Tile Configuration 89" group.byte 0x5A++0x00 line.byte 0x00 "HC90,DSI HC Tile Configuration 90" group.byte 0x5B++0x00 line.byte 0x00 "HC91,DSI HC Tile Configuration 91" group.byte 0x5C++0x00 line.byte 0x00 "HC92,DSI HC Tile Configuration 92" group.byte 0x5D++0x00 line.byte 0x00 "HC93,DSI HC Tile Configuration 93" group.byte 0x5E++0x00 line.byte 0x00 "HC94,DSI HC Tile Configuration 94" group.byte 0x5F++0x00 line.byte 0x00 "HC95,DSI HC Tile Configuration 95" group.byte 0x60++0x00 line.byte 0x00 "HC96,DSI HC Tile Configuration 96" group.byte 0x61++0x00 line.byte 0x00 "HC97,DSI HC Tile Configuration 97" group.byte 0x62++0x00 line.byte 0x00 "HC98,DSI HC Tile Configuration 98" group.byte 0x63++0x00 line.byte 0x00 "HC99,DSI HC Tile Configuration 99" group.byte 0x64++0x00 line.byte 0x00 "HC100,DSI HC Tile Configuration 100" group.byte 0x65++0x00 line.byte 0x00 "HC101,DSI HC Tile Configuration 101" group.byte 0x66++0x00 line.byte 0x00 "HC102,DSI HC Tile Configuration 102" group.byte 0x67++0x00 line.byte 0x00 "HC103,DSI HC Tile Configuration 103" group.byte 0x68++0x00 line.byte 0x00 "HC104,DSI HC Tile Configuration 104" group.byte 0x69++0x00 line.byte 0x00 "HC105,DSI HC Tile Configuration 105" group.byte 0x6A++0x00 line.byte 0x00 "HC106,DSI HC Tile Configuration 106" group.byte 0x6B++0x00 line.byte 0x00 "HC107,DSI HC Tile Configuration 107" group.byte 0x6C++0x00 line.byte 0x00 "HC108,DSI HC Tile Configuration 108" group.byte 0x6D++0x00 line.byte 0x00 "HC109,DSI HC Tile Configuration 109" group.byte 0x6E++0x00 line.byte 0x00 "HC110,DSI HC Tile Configuration 110" group.byte 0x6F++0x00 line.byte 0x00 "HC111,DSI HC Tile Configuration 111" group.byte 0x70++0x00 line.byte 0x00 "HC112,DSI HC Tile Configuration 112" group.byte 0x71++0x00 line.byte 0x00 "HC113,DSI HC Tile Configuration 113" group.byte 0x72++0x00 line.byte 0x00 "HC114,DSI HC Tile Configuration 114" group.byte 0x73++0x00 line.byte 0x00 "HC115,DSI HC Tile Configuration 115" group.byte 0x74++0x00 line.byte 0x00 "HC116,DSI HC Tile Configuration 116" group.byte 0x75++0x00 line.byte 0x00 "HC117,DSI HC Tile Configuration 117" group.byte 0x76++0x00 line.byte 0x00 "HC118,DSI HC Tile Configuration 118" group.byte 0x77++0x00 line.byte 0x00 "HC119,DSI HC Tile Configuration 119" group.byte 0x78++0x00 line.byte 0x00 "HC120,DSI HC Tile Configuration 120" group.byte 0x79++0x00 line.byte 0x00 "HC121,DSI HC Tile Configuration 121" group.byte 0x7A++0x00 line.byte 0x00 "HC122,DSI HC Tile Configuration 122" group.byte 0x7B++0x00 line.byte 0x00 "HC123,DSI HC Tile Configuration 123" group.byte 0x7C++0x00 line.byte 0x00 "HC124,DSI HC Tile Configuration 124" group.byte 0x7D++0x00 line.byte 0x00 "HC125,DSI HC Tile Configuration 125" group.byte 0x7E++0x00 line.byte 0x00 "HC126,DSI HC Tile Configuration 126" group.byte 0x7F++0x00 line.byte 0x00 "HC127,DSI HC Tile Configuration 127" group.byte 0x80++0x00 line.byte 0x00 "HV_L0,DSI HV Tile Configuration; Left 0" group.byte 0x81++0x00 line.byte 0x00 "HV_L1,DSI HV Tile Configuration; Left 1" group.byte 0x82++0x00 line.byte 0x00 "HV_L2,DSI HV Tile Configuration; Left 2" group.byte 0x83++0x00 line.byte 0x00 "HV_L3,DSI HV Tile Configuration; Left 3" group.byte 0x84++0x00 line.byte 0x00 "HV_L4,DSI HV Tile Configuration; Left 4" group.byte 0x85++0x00 line.byte 0x00 "HV_L5,DSI HV Tile Configuration; Left 5" group.byte 0x86++0x00 line.byte 0x00 "HV_L6,DSI HV Tile Configuration; Left 6" group.byte 0x87++0x00 line.byte 0x00 "HV_L7,DSI HV Tile Configuration; Left 7" group.byte 0x88++0x00 line.byte 0x00 "HV_L8,DSI HV Tile Configuration; Left 8" group.byte 0x89++0x00 line.byte 0x00 "HV_L9,DSI HV Tile Configuration; Left 9" group.byte 0x8A++0x00 line.byte 0x00 "HV_L10,DSI HV Tile Configuration; Left 10" group.byte 0x8B++0x00 line.byte 0x00 "HV_L11,DSI HV Tile Configuration; Left 11" group.byte 0x8C++0x00 line.byte 0x00 "HV_L12,DSI HV Tile Configuration; Left 12" group.byte 0x8D++0x00 line.byte 0x00 "HV_L13,DSI HV Tile Configuration; Left 13" group.byte 0x8E++0x00 line.byte 0x00 "HV_L14,DSI HV Tile Configuration; Left 14" group.byte 0x8F++0x00 line.byte 0x00 "HV_L15,DSI HV Tile Configuration; Left 15" group.byte 0x90++0x00 line.byte 0x00 "HS0,DSI HS Tile Configuration; Horizontal Segmentation 0" group.byte 0x91++0x00 line.byte 0x00 "HS1,DSI HS Tile Configuration; Horizontal Segmentation 1" group.byte 0x92++0x00 line.byte 0x00 "HS2,DSI HS Tile Configuration; Horizontal Segmentation 2" group.byte 0x93++0x00 line.byte 0x00 "HS3,DSI HS Tile Configuration; Horizontal Segmentation 3" group.byte 0x94++0x00 line.byte 0x00 "HS4,DSI HS Tile Configuration; Horizontal Segmentation 4" group.byte 0x95++0x00 line.byte 0x00 "HS5,DSI HS Tile Configuration; Horizontal Segmentation 5" group.byte 0x96++0x00 line.byte 0x00 "HS6,DSI HS Tile Configuration; Horizontal Segmentation 6" group.byte 0x97++0x00 line.byte 0x00 "HS7,DSI HS Tile Configuration; Horizontal Segmentation 7" group.byte 0x98++0x00 line.byte 0x00 "HS8,DSI HS Tile Configuration; Horizontal Segmentation 8" group.byte 0x99++0x00 line.byte 0x00 "HS9,DSI HS Tile Configuration; Horizontal Segmentation 9" group.byte 0x9A++0x00 line.byte 0x00 "HS10,DSI HS Tile Configuration; Horizontal Segmentation 10" group.byte 0x9B++0x00 line.byte 0x00 "HS11,DSI HS Tile Configuration; Horizontal Segmentation 11" group.byte 0x9C++0x00 line.byte 0x00 "HS12,DSI HS Tile Configuration; Horizontal Segmentation 12" group.byte 0x9D++0x00 line.byte 0x00 "HS13,DSI HS Tile Configuration; Horizontal Segmentation 13" group.byte 0x9E++0x00 line.byte 0x00 "HS14,DSI HS Tile Configuration; Horizontal Segmentation 14" group.byte 0x9F++0x00 line.byte 0x00 "HS15,DSI HS Tile Configuration; Horizontal Segmentation 15" group.byte 0xA0++0x00 line.byte 0x00 "HS16,DSI HS Tile Configuration; Horizontal Segmentation 16" group.byte 0xA1++0x00 line.byte 0x00 "HS17,DSI HS Tile Configuration; Horizontal Segmentation 17" group.byte 0xA2++0x00 line.byte 0x00 "HS18,DSI HS Tile Configuration; Horizontal Segmentation 18" group.byte 0xA3++0x00 line.byte 0x00 "HS19,DSI HS Tile Configuration; Horizontal Segmentation 19" group.byte 0xA4++0x00 line.byte 0x00 "HS20,DSI HS Tile Configuration; Horizontal Segmentation 20" group.byte 0xA5++0x00 line.byte 0x00 "HS21,DSI HS Tile Configuration; Horizontal Segmentation 21" group.byte 0xA6++0x00 line.byte 0x00 "HS22,DSI HS Tile Configuration; Horizontal Segmentation 22" group.byte 0xA7++0x00 line.byte 0x00 "HS23,DSI HS Tile Configuration; Horizontal Segmentation 23" group.byte 0xA8++0x00 line.byte 0x00 "HV_R0,DSI HV Tile Configuration; Right 0" group.byte 0xA9++0x00 line.byte 0x00 "HV_R1,DSI HV Tile Configuration; Right 1" group.byte 0xAA++0x00 line.byte 0x00 "HV_R2,DSI HV Tile Configuration; Right 2" group.byte 0xAB++0x00 line.byte 0x00 "HV_R3,DSI HV Tile Configuration; Right 3" group.byte 0xAC++0x00 line.byte 0x00 "HV_R4,DSI HV Tile Configuration; Right 4" group.byte 0xAD++0x00 line.byte 0x00 "HV_R5,DSI HV Tile Configuration; Right 5" group.byte 0xAE++0x00 line.byte 0x00 "HV_R6,DSI HV Tile Configuration; Right 6" group.byte 0xAF++0x00 line.byte 0x00 "HV_R7,DSI HV Tile Configuration; Right 7" group.byte 0xB0++0x00 line.byte 0x00 "HV_R8,DSI HV Tile Configuration; Right 8" group.byte 0xB1++0x00 line.byte 0x00 "HV_R9,DSI HV Tile Configuration; Right 9" group.byte 0xB2++0x00 line.byte 0x00 "HV_R10,DSI HV Tile Configuration; Right 10" group.byte 0xB3++0x00 line.byte 0x00 "HV_R11,DSI HV Tile Configuration; Right 11" group.byte 0xB4++0x00 line.byte 0x00 "HV_R12,DSI HV Tile Configuration; Right 12" group.byte 0xB5++0x00 line.byte 0x00 "HV_R13,DSI HV Tile Configuration; Right 13" group.byte 0xB6++0x00 line.byte 0x00 "HV_R14,DSI HV Tile Configuration; Right 14" group.byte 0xB7++0x00 line.byte 0x00 "HV_R15,DSI HV Tile Configuration; Right 15" group.word 0xC0++0x01 line.word 0x00 "DSIINP0,DSI PI Tile Configuration For DSI I/O; Input 0" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xC2++0x01 line.word 0x00 "DSIINP1,DSI PI Tile Configuration For DSI I/O; Input 1" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xC4++0x01 line.word 0x00 "DSIINP2,DSI PI Tile Configuration For DSI I/O; Input 2" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xC6++0x01 line.word 0x00 "DSIINP3,DSI PI Tile Configuration For DSI I/O; Input 3" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xC8++0x01 line.word 0x00 "DSIINP4,DSI PI Tile Configuration For DSI I/O; Input 4" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xCA++0x01 line.word 0x00 "DSIINP5,DSI PI Tile Configuration For DSI I/O; Input 5" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xCC++0x01 line.word 0x00 "DSIOUTP0,DSI PI Tile Configuration For DSI I/O; Output Pair 0" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xCE++0x01 line.word 0x00 "DSIOUTP1,DSI PI Tile Configuration For DSI I/O; Output Pair 1" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xD0++0x01 line.word 0x00 "DSIOUTP2,DSI PI Tile Configuration For DSI I/O; Output Pair 2" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xD2++0x01 line.word 0x00 "DSIOUTP3,DSI PI Tile Configuration For DSI I/O; Output Pair 3" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xD4++0x01 line.word 0x00 "DSIOUTT0,DSI PI Tile Configuration For DSI I/O; Output Triplet 0" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xD6++0x01 line.word 0x00 "DSIOUTT1,DSI PI Tile Configuration For DSI I/O; Output Triplet 1" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xD8++0x01 line.word 0x00 "DSIOUTT2,DSI PI Tile Configuration For DSI I/O; Output Triplet 2" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xDA++0x01 line.word 0x00 "DSIOUTT3,DSI PI Tile Configuration For DSI I/O; Output Triplet 3" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xDC++0x01 line.word 0x00 "DSIOUTT4,DSI PI Tile Configuration For DSI I/O; Output Triplet 4" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xDE++0x01 line.word 0x00 "DSIOUTT5,DSI PI Tile Configuration For DSI I/O; Output Triplet 5" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE0++0x01 line.word 0x00 "VS0,DSI VS Tile Configuration; Vertical Segmentation 0" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE2++0x01 line.word 0x00 "VS1,DSI VS Tile Configuration; Vertical Segmentation 1" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE4++0x01 line.word 0x00 "VS2,DSI VS Tile Configuration; Vertical Segmentation 2" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE6++0x01 line.word 0x00 "VS3,DSI VS Tile Configuration; Vertical Segmentation 3" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE8++0x01 line.word 0x00 "VS4,DSI VS Tile Configuration; Vertical Segmentation 4" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xEA++0x01 line.word 0x00 "VS5,DSI VS Tile Configuration; Vertical Segmentation 5" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xEC++0x01 line.word 0x00 "VS6,DSI VS Tile Configuration; Vertical Segmentation 6" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xEE++0x01 line.word 0x00 "VS7,DSI VS Tile Configuration; Vertical Segmentation 7" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree "UDB_DSI7" base ad:0x400F4700 width 15. group.byte 0x0++0x00 line.byte 0x00 "HC0,DSI HC Tile Configuration 0" group.byte 0x1++0x00 line.byte 0x00 "HC1,DSI HC Tile Configuration 1" group.byte 0x2++0x00 line.byte 0x00 "HC2,DSI HC Tile Configuration 2" group.byte 0x3++0x00 line.byte 0x00 "HC3,DSI HC Tile Configuration 3" group.byte 0x4++0x00 line.byte 0x00 "HC4,DSI HC Tile Configuration 4" group.byte 0x5++0x00 line.byte 0x00 "HC5,DSI HC Tile Configuration 5" group.byte 0x6++0x00 line.byte 0x00 "HC6,DSI HC Tile Configuration 6" group.byte 0x7++0x00 line.byte 0x00 "HC7,DSI HC Tile Configuration 7" group.byte 0x8++0x00 line.byte 0x00 "HC8,DSI HC Tile Configuration 8" group.byte 0x9++0x00 line.byte 0x00 "HC9,DSI HC Tile Configuration 9" group.byte 0xA++0x00 line.byte 0x00 "HC10,DSI HC Tile Configuration 10" group.byte 0xB++0x00 line.byte 0x00 "HC11,DSI HC Tile Configuration 11" group.byte 0xC++0x00 line.byte 0x00 "HC12,DSI HC Tile Configuration 12" group.byte 0xD++0x00 line.byte 0x00 "HC13,DSI HC Tile Configuration 13" group.byte 0xE++0x00 line.byte 0x00 "HC14,DSI HC Tile Configuration 14" group.byte 0xF++0x00 line.byte 0x00 "HC15,DSI HC Tile Configuration 15" group.byte 0x10++0x00 line.byte 0x00 "HC16,DSI HC Tile Configuration 16" group.byte 0x11++0x00 line.byte 0x00 "HC17,DSI HC Tile Configuration 17" group.byte 0x12++0x00 line.byte 0x00 "HC18,DSI HC Tile Configuration 18" group.byte 0x13++0x00 line.byte 0x00 "HC19,DSI HC Tile Configuration 19" group.byte 0x14++0x00 line.byte 0x00 "HC20,DSI HC Tile Configuration 20" group.byte 0x15++0x00 line.byte 0x00 "HC21,DSI HC Tile Configuration 21" group.byte 0x16++0x00 line.byte 0x00 "HC22,DSI HC Tile Configuration 22" group.byte 0x17++0x00 line.byte 0x00 "HC23,DSI HC Tile Configuration 23" group.byte 0x18++0x00 line.byte 0x00 "HC24,DSI HC Tile Configuration 24" group.byte 0x19++0x00 line.byte 0x00 "HC25,DSI HC Tile Configuration 25" group.byte 0x1A++0x00 line.byte 0x00 "HC26,DSI HC Tile Configuration 26" group.byte 0x1B++0x00 line.byte 0x00 "HC27,DSI HC Tile Configuration 27" group.byte 0x1C++0x00 line.byte 0x00 "HC28,DSI HC Tile Configuration 28" group.byte 0x1D++0x00 line.byte 0x00 "HC29,DSI HC Tile Configuration 29" group.byte 0x1E++0x00 line.byte 0x00 "HC30,DSI HC Tile Configuration 30" group.byte 0x1F++0x00 line.byte 0x00 "HC31,DSI HC Tile Configuration 31" group.byte 0x20++0x00 line.byte 0x00 "HC32,DSI HC Tile Configuration 32" group.byte 0x21++0x00 line.byte 0x00 "HC33,DSI HC Tile Configuration 33" group.byte 0x22++0x00 line.byte 0x00 "HC34,DSI HC Tile Configuration 34" group.byte 0x23++0x00 line.byte 0x00 "HC35,DSI HC Tile Configuration 35" group.byte 0x24++0x00 line.byte 0x00 "HC36,DSI HC Tile Configuration 36" group.byte 0x25++0x00 line.byte 0x00 "HC37,DSI HC Tile Configuration 37" group.byte 0x26++0x00 line.byte 0x00 "HC38,DSI HC Tile Configuration 38" group.byte 0x27++0x00 line.byte 0x00 "HC39,DSI HC Tile Configuration 39" group.byte 0x28++0x00 line.byte 0x00 "HC40,DSI HC Tile Configuration 40" group.byte 0x29++0x00 line.byte 0x00 "HC41,DSI HC Tile Configuration 41" group.byte 0x2A++0x00 line.byte 0x00 "HC42,DSI HC Tile Configuration 42" group.byte 0x2B++0x00 line.byte 0x00 "HC43,DSI HC Tile Configuration 43" group.byte 0x2C++0x00 line.byte 0x00 "HC44,DSI HC Tile Configuration 44" group.byte 0x2D++0x00 line.byte 0x00 "HC45,DSI HC Tile Configuration 45" group.byte 0x2E++0x00 line.byte 0x00 "HC46,DSI HC Tile Configuration 46" group.byte 0x2F++0x00 line.byte 0x00 "HC47,DSI HC Tile Configuration 47" group.byte 0x30++0x00 line.byte 0x00 "HC48,DSI HC Tile Configuration 48" group.byte 0x31++0x00 line.byte 0x00 "HC49,DSI HC Tile Configuration 49" group.byte 0x32++0x00 line.byte 0x00 "HC50,DSI HC Tile Configuration 50" group.byte 0x33++0x00 line.byte 0x00 "HC51,DSI HC Tile Configuration 51" group.byte 0x34++0x00 line.byte 0x00 "HC52,DSI HC Tile Configuration 52" group.byte 0x35++0x00 line.byte 0x00 "HC53,DSI HC Tile Configuration 53" group.byte 0x36++0x00 line.byte 0x00 "HC54,DSI HC Tile Configuration 54" group.byte 0x37++0x00 line.byte 0x00 "HC55,DSI HC Tile Configuration 55" group.byte 0x38++0x00 line.byte 0x00 "HC56,DSI HC Tile Configuration 56" group.byte 0x39++0x00 line.byte 0x00 "HC57,DSI HC Tile Configuration 57" group.byte 0x3A++0x00 line.byte 0x00 "HC58,DSI HC Tile Configuration 58" group.byte 0x3B++0x00 line.byte 0x00 "HC59,DSI HC Tile Configuration 59" group.byte 0x3C++0x00 line.byte 0x00 "HC60,DSI HC Tile Configuration 60" group.byte 0x3D++0x00 line.byte 0x00 "HC61,DSI HC Tile Configuration 61" group.byte 0x3E++0x00 line.byte 0x00 "HC62,DSI HC Tile Configuration 62" group.byte 0x3F++0x00 line.byte 0x00 "HC63,DSI HC Tile Configuration 63" group.byte 0x40++0x00 line.byte 0x00 "HC64,DSI HC Tile Configuration 64" group.byte 0x41++0x00 line.byte 0x00 "HC65,DSI HC Tile Configuration 65" group.byte 0x42++0x00 line.byte 0x00 "HC66,DSI HC Tile Configuration 66" group.byte 0x43++0x00 line.byte 0x00 "HC67,DSI HC Tile Configuration 67" group.byte 0x44++0x00 line.byte 0x00 "HC68,DSI HC Tile Configuration 68" group.byte 0x45++0x00 line.byte 0x00 "HC69,DSI HC Tile Configuration 69" group.byte 0x46++0x00 line.byte 0x00 "HC70,DSI HC Tile Configuration 70" group.byte 0x47++0x00 line.byte 0x00 "HC71,DSI HC Tile Configuration 71" group.byte 0x48++0x00 line.byte 0x00 "HC72,DSI HC Tile Configuration 72" group.byte 0x49++0x00 line.byte 0x00 "HC73,DSI HC Tile Configuration 73" group.byte 0x4A++0x00 line.byte 0x00 "HC74,DSI HC Tile Configuration 74" group.byte 0x4B++0x00 line.byte 0x00 "HC75,DSI HC Tile Configuration 75" group.byte 0x4C++0x00 line.byte 0x00 "HC76,DSI HC Tile Configuration 76" group.byte 0x4D++0x00 line.byte 0x00 "HC77,DSI HC Tile Configuration 77" group.byte 0x4E++0x00 line.byte 0x00 "HC78,DSI HC Tile Configuration 78" group.byte 0x4F++0x00 line.byte 0x00 "HC79,DSI HC Tile Configuration 79" group.byte 0x50++0x00 line.byte 0x00 "HC80,DSI HC Tile Configuration 80" group.byte 0x51++0x00 line.byte 0x00 "HC81,DSI HC Tile Configuration 81" group.byte 0x52++0x00 line.byte 0x00 "HC82,DSI HC Tile Configuration 82" group.byte 0x53++0x00 line.byte 0x00 "HC83,DSI HC Tile Configuration 83" group.byte 0x54++0x00 line.byte 0x00 "HC84,DSI HC Tile Configuration 84" group.byte 0x55++0x00 line.byte 0x00 "HC85,DSI HC Tile Configuration 85" group.byte 0x56++0x00 line.byte 0x00 "HC86,DSI HC Tile Configuration 86" group.byte 0x57++0x00 line.byte 0x00 "HC87,DSI HC Tile Configuration 87" group.byte 0x58++0x00 line.byte 0x00 "HC88,DSI HC Tile Configuration 88" group.byte 0x59++0x00 line.byte 0x00 "HC89,DSI HC Tile Configuration 89" group.byte 0x5A++0x00 line.byte 0x00 "HC90,DSI HC Tile Configuration 90" group.byte 0x5B++0x00 line.byte 0x00 "HC91,DSI HC Tile Configuration 91" group.byte 0x5C++0x00 line.byte 0x00 "HC92,DSI HC Tile Configuration 92" group.byte 0x5D++0x00 line.byte 0x00 "HC93,DSI HC Tile Configuration 93" group.byte 0x5E++0x00 line.byte 0x00 "HC94,DSI HC Tile Configuration 94" group.byte 0x5F++0x00 line.byte 0x00 "HC95,DSI HC Tile Configuration 95" group.byte 0x60++0x00 line.byte 0x00 "HC96,DSI HC Tile Configuration 96" group.byte 0x61++0x00 line.byte 0x00 "HC97,DSI HC Tile Configuration 97" group.byte 0x62++0x00 line.byte 0x00 "HC98,DSI HC Tile Configuration 98" group.byte 0x63++0x00 line.byte 0x00 "HC99,DSI HC Tile Configuration 99" group.byte 0x64++0x00 line.byte 0x00 "HC100,DSI HC Tile Configuration 100" group.byte 0x65++0x00 line.byte 0x00 "HC101,DSI HC Tile Configuration 101" group.byte 0x66++0x00 line.byte 0x00 "HC102,DSI HC Tile Configuration 102" group.byte 0x67++0x00 line.byte 0x00 "HC103,DSI HC Tile Configuration 103" group.byte 0x68++0x00 line.byte 0x00 "HC104,DSI HC Tile Configuration 104" group.byte 0x69++0x00 line.byte 0x00 "HC105,DSI HC Tile Configuration 105" group.byte 0x6A++0x00 line.byte 0x00 "HC106,DSI HC Tile Configuration 106" group.byte 0x6B++0x00 line.byte 0x00 "HC107,DSI HC Tile Configuration 107" group.byte 0x6C++0x00 line.byte 0x00 "HC108,DSI HC Tile Configuration 108" group.byte 0x6D++0x00 line.byte 0x00 "HC109,DSI HC Tile Configuration 109" group.byte 0x6E++0x00 line.byte 0x00 "HC110,DSI HC Tile Configuration 110" group.byte 0x6F++0x00 line.byte 0x00 "HC111,DSI HC Tile Configuration 111" group.byte 0x70++0x00 line.byte 0x00 "HC112,DSI HC Tile Configuration 112" group.byte 0x71++0x00 line.byte 0x00 "HC113,DSI HC Tile Configuration 113" group.byte 0x72++0x00 line.byte 0x00 "HC114,DSI HC Tile Configuration 114" group.byte 0x73++0x00 line.byte 0x00 "HC115,DSI HC Tile Configuration 115" group.byte 0x74++0x00 line.byte 0x00 "HC116,DSI HC Tile Configuration 116" group.byte 0x75++0x00 line.byte 0x00 "HC117,DSI HC Tile Configuration 117" group.byte 0x76++0x00 line.byte 0x00 "HC118,DSI HC Tile Configuration 118" group.byte 0x77++0x00 line.byte 0x00 "HC119,DSI HC Tile Configuration 119" group.byte 0x78++0x00 line.byte 0x00 "HC120,DSI HC Tile Configuration 120" group.byte 0x79++0x00 line.byte 0x00 "HC121,DSI HC Tile Configuration 121" group.byte 0x7A++0x00 line.byte 0x00 "HC122,DSI HC Tile Configuration 122" group.byte 0x7B++0x00 line.byte 0x00 "HC123,DSI HC Tile Configuration 123" group.byte 0x7C++0x00 line.byte 0x00 "HC124,DSI HC Tile Configuration 124" group.byte 0x7D++0x00 line.byte 0x00 "HC125,DSI HC Tile Configuration 125" group.byte 0x7E++0x00 line.byte 0x00 "HC126,DSI HC Tile Configuration 126" group.byte 0x7F++0x00 line.byte 0x00 "HC127,DSI HC Tile Configuration 127" group.byte 0x80++0x00 line.byte 0x00 "HV_L0,DSI HV Tile Configuration; Left 0" group.byte 0x81++0x00 line.byte 0x00 "HV_L1,DSI HV Tile Configuration; Left 1" group.byte 0x82++0x00 line.byte 0x00 "HV_L2,DSI HV Tile Configuration; Left 2" group.byte 0x83++0x00 line.byte 0x00 "HV_L3,DSI HV Tile Configuration; Left 3" group.byte 0x84++0x00 line.byte 0x00 "HV_L4,DSI HV Tile Configuration; Left 4" group.byte 0x85++0x00 line.byte 0x00 "HV_L5,DSI HV Tile Configuration; Left 5" group.byte 0x86++0x00 line.byte 0x00 "HV_L6,DSI HV Tile Configuration; Left 6" group.byte 0x87++0x00 line.byte 0x00 "HV_L7,DSI HV Tile Configuration; Left 7" group.byte 0x88++0x00 line.byte 0x00 "HV_L8,DSI HV Tile Configuration; Left 8" group.byte 0x89++0x00 line.byte 0x00 "HV_L9,DSI HV Tile Configuration; Left 9" group.byte 0x8A++0x00 line.byte 0x00 "HV_L10,DSI HV Tile Configuration; Left 10" group.byte 0x8B++0x00 line.byte 0x00 "HV_L11,DSI HV Tile Configuration; Left 11" group.byte 0x8C++0x00 line.byte 0x00 "HV_L12,DSI HV Tile Configuration; Left 12" group.byte 0x8D++0x00 line.byte 0x00 "HV_L13,DSI HV Tile Configuration; Left 13" group.byte 0x8E++0x00 line.byte 0x00 "HV_L14,DSI HV Tile Configuration; Left 14" group.byte 0x8F++0x00 line.byte 0x00 "HV_L15,DSI HV Tile Configuration; Left 15" group.byte 0x90++0x00 line.byte 0x00 "HS0,DSI HS Tile Configuration; Horizontal Segmentation 0" group.byte 0x91++0x00 line.byte 0x00 "HS1,DSI HS Tile Configuration; Horizontal Segmentation 1" group.byte 0x92++0x00 line.byte 0x00 "HS2,DSI HS Tile Configuration; Horizontal Segmentation 2" group.byte 0x93++0x00 line.byte 0x00 "HS3,DSI HS Tile Configuration; Horizontal Segmentation 3" group.byte 0x94++0x00 line.byte 0x00 "HS4,DSI HS Tile Configuration; Horizontal Segmentation 4" group.byte 0x95++0x00 line.byte 0x00 "HS5,DSI HS Tile Configuration; Horizontal Segmentation 5" group.byte 0x96++0x00 line.byte 0x00 "HS6,DSI HS Tile Configuration; Horizontal Segmentation 6" group.byte 0x97++0x00 line.byte 0x00 "HS7,DSI HS Tile Configuration; Horizontal Segmentation 7" group.byte 0x98++0x00 line.byte 0x00 "HS8,DSI HS Tile Configuration; Horizontal Segmentation 8" group.byte 0x99++0x00 line.byte 0x00 "HS9,DSI HS Tile Configuration; Horizontal Segmentation 9" group.byte 0x9A++0x00 line.byte 0x00 "HS10,DSI HS Tile Configuration; Horizontal Segmentation 10" group.byte 0x9B++0x00 line.byte 0x00 "HS11,DSI HS Tile Configuration; Horizontal Segmentation 11" group.byte 0x9C++0x00 line.byte 0x00 "HS12,DSI HS Tile Configuration; Horizontal Segmentation 12" group.byte 0x9D++0x00 line.byte 0x00 "HS13,DSI HS Tile Configuration; Horizontal Segmentation 13" group.byte 0x9E++0x00 line.byte 0x00 "HS14,DSI HS Tile Configuration; Horizontal Segmentation 14" group.byte 0x9F++0x00 line.byte 0x00 "HS15,DSI HS Tile Configuration; Horizontal Segmentation 15" group.byte 0xA0++0x00 line.byte 0x00 "HS16,DSI HS Tile Configuration; Horizontal Segmentation 16" group.byte 0xA1++0x00 line.byte 0x00 "HS17,DSI HS Tile Configuration; Horizontal Segmentation 17" group.byte 0xA2++0x00 line.byte 0x00 "HS18,DSI HS Tile Configuration; Horizontal Segmentation 18" group.byte 0xA3++0x00 line.byte 0x00 "HS19,DSI HS Tile Configuration; Horizontal Segmentation 19" group.byte 0xA4++0x00 line.byte 0x00 "HS20,DSI HS Tile Configuration; Horizontal Segmentation 20" group.byte 0xA5++0x00 line.byte 0x00 "HS21,DSI HS Tile Configuration; Horizontal Segmentation 21" group.byte 0xA6++0x00 line.byte 0x00 "HS22,DSI HS Tile Configuration; Horizontal Segmentation 22" group.byte 0xA7++0x00 line.byte 0x00 "HS23,DSI HS Tile Configuration; Horizontal Segmentation 23" group.byte 0xA8++0x00 line.byte 0x00 "HV_R0,DSI HV Tile Configuration; Right 0" group.byte 0xA9++0x00 line.byte 0x00 "HV_R1,DSI HV Tile Configuration; Right 1" group.byte 0xAA++0x00 line.byte 0x00 "HV_R2,DSI HV Tile Configuration; Right 2" group.byte 0xAB++0x00 line.byte 0x00 "HV_R3,DSI HV Tile Configuration; Right 3" group.byte 0xAC++0x00 line.byte 0x00 "HV_R4,DSI HV Tile Configuration; Right 4" group.byte 0xAD++0x00 line.byte 0x00 "HV_R5,DSI HV Tile Configuration; Right 5" group.byte 0xAE++0x00 line.byte 0x00 "HV_R6,DSI HV Tile Configuration; Right 6" group.byte 0xAF++0x00 line.byte 0x00 "HV_R7,DSI HV Tile Configuration; Right 7" group.byte 0xB0++0x00 line.byte 0x00 "HV_R8,DSI HV Tile Configuration; Right 8" group.byte 0xB1++0x00 line.byte 0x00 "HV_R9,DSI HV Tile Configuration; Right 9" group.byte 0xB2++0x00 line.byte 0x00 "HV_R10,DSI HV Tile Configuration; Right 10" group.byte 0xB3++0x00 line.byte 0x00 "HV_R11,DSI HV Tile Configuration; Right 11" group.byte 0xB4++0x00 line.byte 0x00 "HV_R12,DSI HV Tile Configuration; Right 12" group.byte 0xB5++0x00 line.byte 0x00 "HV_R13,DSI HV Tile Configuration; Right 13" group.byte 0xB6++0x00 line.byte 0x00 "HV_R14,DSI HV Tile Configuration; Right 14" group.byte 0xB7++0x00 line.byte 0x00 "HV_R15,DSI HV Tile Configuration; Right 15" group.word 0xC0++0x01 line.word 0x00 "DSIINP0,DSI PI Tile Configuration For DSI I/O; Input 0" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xC2++0x01 line.word 0x00 "DSIINP1,DSI PI Tile Configuration For DSI I/O; Input 1" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xC4++0x01 line.word 0x00 "DSIINP2,DSI PI Tile Configuration For DSI I/O; Input 2" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xC6++0x01 line.word 0x00 "DSIINP3,DSI PI Tile Configuration For DSI I/O; Input 3" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xC8++0x01 line.word 0x00 "DSIINP4,DSI PI Tile Configuration For DSI I/O; Input 4" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xCA++0x01 line.word 0x00 "DSIINP5,DSI PI Tile Configuration For DSI I/O; Input 5" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xCC++0x01 line.word 0x00 "DSIOUTP0,DSI PI Tile Configuration For DSI I/O; Output Pair 0" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xCE++0x01 line.word 0x00 "DSIOUTP1,DSI PI Tile Configuration For DSI I/O; Output Pair 1" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xD0++0x01 line.word 0x00 "DSIOUTP2,DSI PI Tile Configuration For DSI I/O; Output Pair 2" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xD2++0x01 line.word 0x00 "DSIOUTP3,DSI PI Tile Configuration For DSI I/O; Output Pair 3" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xD4++0x01 line.word 0x00 "DSIOUTT0,DSI PI Tile Configuration For DSI I/O; Output Triplet 0" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xD6++0x01 line.word 0x00 "DSIOUTT1,DSI PI Tile Configuration For DSI I/O; Output Triplet 1" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xD8++0x01 line.word 0x00 "DSIOUTT2,DSI PI Tile Configuration For DSI I/O; Output Triplet 2" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xDA++0x01 line.word 0x00 "DSIOUTT3,DSI PI Tile Configuration For DSI I/O; Output Triplet 3" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xDC++0x01 line.word 0x00 "DSIOUTT4,DSI PI Tile Configuration For DSI I/O; Output Triplet 4" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xDE++0x01 line.word 0x00 "DSIOUTT5,DSI PI Tile Configuration For DSI I/O; Output Triplet 5" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration for BOTTOM DSI port interface, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration for TOP DSI port interface, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE0++0x01 line.word 0x00 "VS0,DSI VS Tile Configuration; Vertical Segmentation 0" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE2++0x01 line.word 0x00 "VS1,DSI VS Tile Configuration; Vertical Segmentation 1" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE4++0x01 line.word 0x00 "VS2,DSI VS Tile Configuration; Vertical Segmentation 2" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE6++0x01 line.word 0x00 "VS3,DSI VS Tile Configuration; Vertical Segmentation 3" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE8++0x01 line.word 0x00 "VS4,DSI VS Tile Configuration; Vertical Segmentation 4" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xEA++0x01 line.word 0x00 "VS5,DSI VS Tile Configuration; Vertical Segmentation 5" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xEC++0x01 line.word 0x00 "VS6,DSI VS Tile Configuration; Vertical Segmentation 6" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xEE++0x01 line.word 0x00 "VS7,DSI VS Tile Configuration; Vertical Segmentation 7" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration for BOTTOM DSI vertical segmentation, not implemented in TOP DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration for TOP DSI vertical segmentation, not implemented in BOTTOM DSI blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree.end tree "UDB Port Adapter registers" tree "UDB_P0" base ad:0x400F5000 width 7. group.byte 0x00++0x0E line.byte 0x00 "CFG0,PA Data In Clock Control Register" bitfld.byte 0x00 6.--7. " NC ,Spare register bits NC" "0,1,2,3" bitfld.byte 0x00 5. " CLKIN_INV ,Determines whether the selected clock is inverted or not" "Not inverted,Inverted" bitfld.byte 0x00 4. " CLKIN_EN_INV ,Determines whether the selected enable is inverted or not" "Not inverted,Inverted" bitfld.byte 0x00 2.--3. " CLKIN_EN_MODE ,Select one of four operating modes" "Off,On,Posedge,Level" textline " " bitfld.byte 0x00 0.--1. " CLKIN_EN_SEL ,Select one of four choices for clock enable" "PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2" line.byte 0x01 "CFG1,PA Data Out Clock Control Register" bitfld.byte 0x01 6.--7. " NC ,Spare register bits NC" "0,1,2,3" bitfld.byte 0x01 5. " CLKOUT_INV ,Determines whether the selected clock is inverted or not" "Not inverted,Inverted" bitfld.byte 0x01 4. " CLKOUT_EN_INV ,Determines whether the selected enable is inverted or not" "Not inverted,Inverted" bitfld.byte 0x01 2.--3. " CLKOUT_EN_MODE ,Select one of four operating modes" "Off,On,Posedge,Level" textline " " bitfld.byte 0x01 0.--1. " CLKOUT_EN_SEL ,Select one of four choices for clock enable" "PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2" line.byte 0x02 "CFG2,PA Clock Select Register" bitfld.byte 0x02 4.--7. " CLKOUT_SEL ,Select one of four choices for clock enable" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,,BUS_CLK_APP,,,PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2" bitfld.byte 0x02 0.--3. " CLKIN_SEL ,Select one of four choices for clock enable" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,,BUS_CLK_APP,,,PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2" line.byte 0x03 "CFG3,PA Reset Select Register" bitfld.byte 0x03 7. " NC7 ,Spare register bit NC7" "0,1" bitfld.byte 0x03 6. " RES_OUT_INV ,Select the polarity of the reset control" "Not inverted,Inverted" bitfld.byte 0x03 4.--5. " RES_OUT_SEL ,Select one of four inputs to serve as the reset control to the block" "PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2" bitfld.byte 0x03 3. " NC0 ,Spare register bit NC0" "0,1" textline " " bitfld.byte 0x03 2. " RES_IN_INV ,Select the polarity of the reset control" "Not inverted,Inverted" bitfld.byte 0x03 0.--1. " RES_IN_SEL ,Select one of four inputs to serve as the reset control to the block" "PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2" line.byte 0x04 "CFG4,PA Reset Enable Register" bitfld.byte 0x04 3.--7. " NC7654 ,Spare register bits NC7654" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.byte 0x04 2. " RES_OE_EN ,Enable the selected reset" "Disabled,Enabled" bitfld.byte 0x04 1. " RES_OUT_EN ,Enable the selected reset" "Disabled,Enabled" bitfld.byte 0x04 0. " RES_IN_EN ,Enable the selected reset" "Disabled,Enabled" line.byte 0x05 "CFG5,PA Reset Pin Select Register" bitfld.byte 0x05 3.--7. " NC7654 ,Spare register bits NC7654" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.byte 0x05 0. " PIN_SEL ,Select port input to route to reset multiplexer" "No reset,Reset" line.byte 0x06 "CFG6,PA Input Data Sync Control Register - Low" bitfld.byte 0x06 6.--7. " IN_SYNC3 ,Synchronization selection for PA input 3" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." bitfld.byte 0x06 4.--5. " IN_SYNC2 ,Synchronization selection for PA input 2" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." bitfld.byte 0x06 2.--3. " IN_SYNC1 ,Synchronization selection for PA input 1" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." bitfld.byte 0x06 0.--1. " IN_SYNC0 ,Synchronization selection for PA input 0" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." line.byte 0x07 "CFG7,PA Input Data Sync Control Register - High" bitfld.byte 0x07 6.--7. " IN_SYNC7 ,Synchronization selection for PA input 7" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." bitfld.byte 0x07 4.--5. " IN_SYNC6 ,Synchronization selection for PA input 6" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." bitfld.byte 0x07 2.--3. " IN_SYNC5 ,Synchronization selection for PA input 5" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." bitfld.byte 0x07 0.--1. " IN_SYNC4 ,Synchronization selection for PA input 4" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." line.byte 0x08 "CFG8,PA Output Data Sync Control Register - Low" bitfld.byte 0x08 6.--7. " OUT_SYNC3 ,Synchronization selection for PA output 3" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" bitfld.byte 0x08 4.--5. " OUT_SYNC2 ,Synchronization selection for PA output 2" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" bitfld.byte 0x08 2.--3. " OUT_SYNC1 ,Synchronization selection for PA output 1" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" bitfld.byte 0x08 0.--1. " OUT_SYNC0 ,Synchronization selection for PA output 0" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" line.byte 0x09 "CFG9,PA Output Data Sync Control Register - High" bitfld.byte 0x09 6.--7. " OUT_SYNC7 ,Synchronization selection for PA output 7" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" bitfld.byte 0x09 4.--5. " OUT_SYNC6 ,Synchronization selection for PA output 6" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" bitfld.byte 0x09 2.--3. " OUT_SYNC5 ,Synchronization selection for PA output 5" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" bitfld.byte 0x09 0.--1. " OUT_SYNC4 ,Synchronization selection for PA output 4" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" line.byte 0x0A "CFG10,PA Output Data Select Register - Low" bitfld.byte 0x0A 6.--7. " DATA_SEL3 ,Data selection for PA output 3" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" bitfld.byte 0x0A 4.--5. " DATA_SEL2 ,Data selection for PA output 2" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" bitfld.byte 0x0A 2.--3. " DATA_SEL1 ,Data selection for PA output 1" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" bitfld.byte 0x0A 0.--1. " DATA_SEL0 ,Data selection for PA output 0" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" line.byte 0x0B "CFG11,PA Output Data Select Register - High" bitfld.byte 0x0B 6.--7. " DATA_SEL7 ,Data selection for PA output 7" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" bitfld.byte 0x0B 4.--5. " DATA_SEL6 ,Data selection for PA output 6" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" bitfld.byte 0x0B 2.--3. " DATA_SEL5 ,Data selection for PA output 5" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" bitfld.byte 0x0B 0.--1. " DATA_SEL4 ,Data selection for PA output 4" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" line.byte 0x0C "CFG12,PA OE Select Register - Low" bitfld.byte 0x0C 6.--7. " OE_SEL3 ,Data selection for PA oe 3" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" bitfld.byte 0x0C 4.--5. " OE_SEL2 ,Data selection for PA oe 2" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" bitfld.byte 0x0C 2.--3. " OE_SEL1 ,Data selection for PA oe 1" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" bitfld.byte 0x0C 0.--1. " OE_SEL0 ,Data selection for PA oe 0" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" line.byte 0x0D "CFG13,PA OE Select Register - High" bitfld.byte 0x0D 6.--7. " OE_SEL7 ,Data selection for PA oe 7" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" bitfld.byte 0x0D 4.--5. " OE_SEL6 ,Data selection for PA oe 6" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" bitfld.byte 0x0D 2.--3. " OE_SEL5 ,Data selection for PA oe 5" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" bitfld.byte 0x0D 0.--1. " OE_SEL4 ,Data selection for PA oe 4" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" line.byte 0x0E "CFG14,PA OE Sync Register" bitfld.byte 0x0E 6.--7. " OE_SYNC3 ,Synchronization options for dsi_to_oe[3]" "TRANSPARENT,SINGLESYNC,CONSTANT1,CONSTANT0" bitfld.byte 0x0E 4.--5. " OE_SYNC2 ,Synchronization options for dsi_to_oe[2]" "TRANSPARENT,SINGLESYNC,CONSTANT1,CONSTANT0" bitfld.byte 0x0E 2.--3. " OE_SYNC1 ,Synchronization options for dsi_to_oe[1]" "TRANSPARENT,SINGLESYNC,CONSTANT1,CONSTANT0" bitfld.byte 0x0E 0.--1. " OE_SYNC0 ,Synchronization options for dsi_to_oe[0]" "TRANSPARENT,SINGLESYNC,CONSTANT1,CONSTANT0" width 0x0B tree.end tree "UDB_P1" base ad:0x400F5010 width 7. group.byte 0x00++0x0E line.byte 0x00 "CFG0,PA Data In Clock Control Register" bitfld.byte 0x00 6.--7. " NC ,Spare register bits NC" "0,1,2,3" bitfld.byte 0x00 5. " CLKIN_INV ,Determines whether the selected clock is inverted or not" "Not inverted,Inverted" bitfld.byte 0x00 4. " CLKIN_EN_INV ,Determines whether the selected enable is inverted or not" "Not inverted,Inverted" bitfld.byte 0x00 2.--3. " CLKIN_EN_MODE ,Select one of four operating modes" "Off,On,Posedge,Level" textline " " bitfld.byte 0x00 0.--1. " CLKIN_EN_SEL ,Select one of four choices for clock enable" "PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2" line.byte 0x01 "CFG1,PA Data Out Clock Control Register" bitfld.byte 0x01 6.--7. " NC ,Spare register bits NC" "0,1,2,3" bitfld.byte 0x01 5. " CLKOUT_INV ,Determines whether the selected clock is inverted or not" "Not inverted,Inverted" bitfld.byte 0x01 4. " CLKOUT_EN_INV ,Determines whether the selected enable is inverted or not" "Not inverted,Inverted" bitfld.byte 0x01 2.--3. " CLKOUT_EN_MODE ,Select one of four operating modes" "Off,On,Posedge,Level" textline " " bitfld.byte 0x01 0.--1. " CLKOUT_EN_SEL ,Select one of four choices for clock enable" "PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2" line.byte 0x02 "CFG2,PA Clock Select Register" bitfld.byte 0x02 4.--7. " CLKOUT_SEL ,Select one of four choices for clock enable" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,,BUS_CLK_APP,,,PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2" bitfld.byte 0x02 0.--3. " CLKIN_SEL ,Select one of four choices for clock enable" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,,BUS_CLK_APP,,,PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2" line.byte 0x03 "CFG3,PA Reset Select Register" bitfld.byte 0x03 7. " NC7 ,Spare register bit NC7" "0,1" bitfld.byte 0x03 6. " RES_OUT_INV ,Select the polarity of the reset control" "Not inverted,Inverted" bitfld.byte 0x03 4.--5. " RES_OUT_SEL ,Select one of four inputs to serve as the reset control to the block" "PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2" bitfld.byte 0x03 3. " NC0 ,Spare register bit NC0" "0,1" textline " " bitfld.byte 0x03 2. " RES_IN_INV ,Select the polarity of the reset control" "Not inverted,Inverted" bitfld.byte 0x03 0.--1. " RES_IN_SEL ,Select one of four inputs to serve as the reset control to the block" "PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2" line.byte 0x04 "CFG4,PA Reset Enable Register" bitfld.byte 0x04 3.--7. " NC7654 ,Spare register bits NC7654" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.byte 0x04 2. " RES_OE_EN ,Enable the selected reset" "Disabled,Enabled" bitfld.byte 0x04 1. " RES_OUT_EN ,Enable the selected reset" "Disabled,Enabled" bitfld.byte 0x04 0. " RES_IN_EN ,Enable the selected reset" "Disabled,Enabled" line.byte 0x05 "CFG5,PA Reset Pin Select Register" bitfld.byte 0x05 3.--7. " NC7654 ,Spare register bits NC7654" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.byte 0x05 0. " PIN_SEL ,Select port input to route to reset multiplexer" "No reset,Reset" line.byte 0x06 "CFG6,PA Input Data Sync Control Register - Low" bitfld.byte 0x06 6.--7. " IN_SYNC3 ,Synchronization selection for PA input 3" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." bitfld.byte 0x06 4.--5. " IN_SYNC2 ,Synchronization selection for PA input 2" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." bitfld.byte 0x06 2.--3. " IN_SYNC1 ,Synchronization selection for PA input 1" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." bitfld.byte 0x06 0.--1. " IN_SYNC0 ,Synchronization selection for PA input 0" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." line.byte 0x07 "CFG7,PA Input Data Sync Control Register - High" bitfld.byte 0x07 6.--7. " IN_SYNC7 ,Synchronization selection for PA input 7" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." bitfld.byte 0x07 4.--5. " IN_SYNC6 ,Synchronization selection for PA input 6" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." bitfld.byte 0x07 2.--3. " IN_SYNC5 ,Synchronization selection for PA input 5" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." bitfld.byte 0x07 0.--1. " IN_SYNC4 ,Synchronization selection for PA input 4" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." line.byte 0x08 "CFG8,PA Output Data Sync Control Register - Low" bitfld.byte 0x08 6.--7. " OUT_SYNC3 ,Synchronization selection for PA output 3" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" bitfld.byte 0x08 4.--5. " OUT_SYNC2 ,Synchronization selection for PA output 2" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" bitfld.byte 0x08 2.--3. " OUT_SYNC1 ,Synchronization selection for PA output 1" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" bitfld.byte 0x08 0.--1. " OUT_SYNC0 ,Synchronization selection for PA output 0" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" line.byte 0x09 "CFG9,PA Output Data Sync Control Register - High" bitfld.byte 0x09 6.--7. " OUT_SYNC7 ,Synchronization selection for PA output 7" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" bitfld.byte 0x09 4.--5. " OUT_SYNC6 ,Synchronization selection for PA output 6" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" bitfld.byte 0x09 2.--3. " OUT_SYNC5 ,Synchronization selection for PA output 5" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" bitfld.byte 0x09 0.--1. " OUT_SYNC4 ,Synchronization selection for PA output 4" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" line.byte 0x0A "CFG10,PA Output Data Select Register - Low" bitfld.byte 0x0A 6.--7. " DATA_SEL3 ,Data selection for PA output 3" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" bitfld.byte 0x0A 4.--5. " DATA_SEL2 ,Data selection for PA output 2" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" bitfld.byte 0x0A 2.--3. " DATA_SEL1 ,Data selection for PA output 1" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" bitfld.byte 0x0A 0.--1. " DATA_SEL0 ,Data selection for PA output 0" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" line.byte 0x0B "CFG11,PA Output Data Select Register - High" bitfld.byte 0x0B 6.--7. " DATA_SEL7 ,Data selection for PA output 7" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" bitfld.byte 0x0B 4.--5. " DATA_SEL6 ,Data selection for PA output 6" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" bitfld.byte 0x0B 2.--3. " DATA_SEL5 ,Data selection for PA output 5" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" bitfld.byte 0x0B 0.--1. " DATA_SEL4 ,Data selection for PA output 4" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" line.byte 0x0C "CFG12,PA OE Select Register - Low" bitfld.byte 0x0C 6.--7. " OE_SEL3 ,Data selection for PA oe 3" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" bitfld.byte 0x0C 4.--5. " OE_SEL2 ,Data selection for PA oe 2" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" bitfld.byte 0x0C 2.--3. " OE_SEL1 ,Data selection for PA oe 1" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" bitfld.byte 0x0C 0.--1. " OE_SEL0 ,Data selection for PA oe 0" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" line.byte 0x0D "CFG13,PA OE Select Register - High" bitfld.byte 0x0D 6.--7. " OE_SEL7 ,Data selection for PA oe 7" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" bitfld.byte 0x0D 4.--5. " OE_SEL6 ,Data selection for PA oe 6" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" bitfld.byte 0x0D 2.--3. " OE_SEL5 ,Data selection for PA oe 5" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" bitfld.byte 0x0D 0.--1. " OE_SEL4 ,Data selection for PA oe 4" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" line.byte 0x0E "CFG14,PA OE Sync Register" bitfld.byte 0x0E 6.--7. " OE_SYNC3 ,Synchronization options for dsi_to_oe[3]" "TRANSPARENT,SINGLESYNC,CONSTANT1,CONSTANT0" bitfld.byte 0x0E 4.--5. " OE_SYNC2 ,Synchronization options for dsi_to_oe[2]" "TRANSPARENT,SINGLESYNC,CONSTANT1,CONSTANT0" bitfld.byte 0x0E 2.--3. " OE_SYNC1 ,Synchronization options for dsi_to_oe[1]" "TRANSPARENT,SINGLESYNC,CONSTANT1,CONSTANT0" bitfld.byte 0x0E 0.--1. " OE_SYNC0 ,Synchronization options for dsi_to_oe[0]" "TRANSPARENT,SINGLESYNC,CONSTANT1,CONSTANT0" width 0x0B tree.end tree "UDB_P2" base ad:0x400F5020 width 7. group.byte 0x00++0x0E line.byte 0x00 "CFG0,PA Data In Clock Control Register" bitfld.byte 0x00 6.--7. " NC ,Spare register bits NC" "0,1,2,3" bitfld.byte 0x00 5. " CLKIN_INV ,Determines whether the selected clock is inverted or not" "Not inverted,Inverted" bitfld.byte 0x00 4. " CLKIN_EN_INV ,Determines whether the selected enable is inverted or not" "Not inverted,Inverted" bitfld.byte 0x00 2.--3. " CLKIN_EN_MODE ,Select one of four operating modes" "Off,On,Posedge,Level" textline " " bitfld.byte 0x00 0.--1. " CLKIN_EN_SEL ,Select one of four choices for clock enable" "PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2" line.byte 0x01 "CFG1,PA Data Out Clock Control Register" bitfld.byte 0x01 6.--7. " NC ,Spare register bits NC" "0,1,2,3" bitfld.byte 0x01 5. " CLKOUT_INV ,Determines whether the selected clock is inverted or not" "Not inverted,Inverted" bitfld.byte 0x01 4. " CLKOUT_EN_INV ,Determines whether the selected enable is inverted or not" "Not inverted,Inverted" bitfld.byte 0x01 2.--3. " CLKOUT_EN_MODE ,Select one of four operating modes" "Off,On,Posedge,Level" textline " " bitfld.byte 0x01 0.--1. " CLKOUT_EN_SEL ,Select one of four choices for clock enable" "PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2" line.byte 0x02 "CFG2,PA Clock Select Register" bitfld.byte 0x02 4.--7. " CLKOUT_SEL ,Select one of four choices for clock enable" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,,BUS_CLK_APP,,,PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2" bitfld.byte 0x02 0.--3. " CLKIN_SEL ,Select one of four choices for clock enable" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,,BUS_CLK_APP,,,PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2" line.byte 0x03 "CFG3,PA Reset Select Register" bitfld.byte 0x03 7. " NC7 ,Spare register bit NC7" "0,1" bitfld.byte 0x03 6. " RES_OUT_INV ,Select the polarity of the reset control" "Not inverted,Inverted" bitfld.byte 0x03 4.--5. " RES_OUT_SEL ,Select one of four inputs to serve as the reset control to the block" "PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2" bitfld.byte 0x03 3. " NC0 ,Spare register bit NC0" "0,1" textline " " bitfld.byte 0x03 2. " RES_IN_INV ,Select the polarity of the reset control" "Not inverted,Inverted" bitfld.byte 0x03 0.--1. " RES_IN_SEL ,Select one of four inputs to serve as the reset control to the block" "PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2" line.byte 0x04 "CFG4,PA Reset Enable Register" bitfld.byte 0x04 3.--7. " NC7654 ,Spare register bits NC7654" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.byte 0x04 2. " RES_OE_EN ,Enable the selected reset" "Disabled,Enabled" bitfld.byte 0x04 1. " RES_OUT_EN ,Enable the selected reset" "Disabled,Enabled" bitfld.byte 0x04 0. " RES_IN_EN ,Enable the selected reset" "Disabled,Enabled" line.byte 0x05 "CFG5,PA Reset Pin Select Register" bitfld.byte 0x05 3.--7. " NC7654 ,Spare register bits NC7654" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.byte 0x05 0. " PIN_SEL ,Select port input to route to reset multiplexer" "No reset,Reset" line.byte 0x06 "CFG6,PA Input Data Sync Control Register - Low" bitfld.byte 0x06 6.--7. " IN_SYNC3 ,Synchronization selection for PA input 3" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." bitfld.byte 0x06 4.--5. " IN_SYNC2 ,Synchronization selection for PA input 2" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." bitfld.byte 0x06 2.--3. " IN_SYNC1 ,Synchronization selection for PA input 1" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." bitfld.byte 0x06 0.--1. " IN_SYNC0 ,Synchronization selection for PA input 0" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." line.byte 0x07 "CFG7,PA Input Data Sync Control Register - High" bitfld.byte 0x07 6.--7. " IN_SYNC7 ,Synchronization selection for PA input 7" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." bitfld.byte 0x07 4.--5. " IN_SYNC6 ,Synchronization selection for PA input 6" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." bitfld.byte 0x07 2.--3. " IN_SYNC5 ,Synchronization selection for PA input 5" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." bitfld.byte 0x07 0.--1. " IN_SYNC4 ,Synchronization selection for PA input 4" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." line.byte 0x08 "CFG8,PA Output Data Sync Control Register - Low" bitfld.byte 0x08 6.--7. " OUT_SYNC3 ,Synchronization selection for PA output 3" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" bitfld.byte 0x08 4.--5. " OUT_SYNC2 ,Synchronization selection for PA output 2" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" bitfld.byte 0x08 2.--3. " OUT_SYNC1 ,Synchronization selection for PA output 1" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" bitfld.byte 0x08 0.--1. " OUT_SYNC0 ,Synchronization selection for PA output 0" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" line.byte 0x09 "CFG9,PA Output Data Sync Control Register - High" bitfld.byte 0x09 6.--7. " OUT_SYNC7 ,Synchronization selection for PA output 7" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" bitfld.byte 0x09 4.--5. " OUT_SYNC6 ,Synchronization selection for PA output 6" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" bitfld.byte 0x09 2.--3. " OUT_SYNC5 ,Synchronization selection for PA output 5" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" bitfld.byte 0x09 0.--1. " OUT_SYNC4 ,Synchronization selection for PA output 4" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" line.byte 0x0A "CFG10,PA Output Data Select Register - Low" bitfld.byte 0x0A 6.--7. " DATA_SEL3 ,Data selection for PA output 3" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" bitfld.byte 0x0A 4.--5. " DATA_SEL2 ,Data selection for PA output 2" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" bitfld.byte 0x0A 2.--3. " DATA_SEL1 ,Data selection for PA output 1" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" bitfld.byte 0x0A 0.--1. " DATA_SEL0 ,Data selection for PA output 0" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" line.byte 0x0B "CFG11,PA Output Data Select Register - High" bitfld.byte 0x0B 6.--7. " DATA_SEL7 ,Data selection for PA output 7" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" bitfld.byte 0x0B 4.--5. " DATA_SEL6 ,Data selection for PA output 6" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" bitfld.byte 0x0B 2.--3. " DATA_SEL5 ,Data selection for PA output 5" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" bitfld.byte 0x0B 0.--1. " DATA_SEL4 ,Data selection for PA output 4" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" line.byte 0x0C "CFG12,PA OE Select Register - Low" bitfld.byte 0x0C 6.--7. " OE_SEL3 ,Data selection for PA oe 3" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" bitfld.byte 0x0C 4.--5. " OE_SEL2 ,Data selection for PA oe 2" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" bitfld.byte 0x0C 2.--3. " OE_SEL1 ,Data selection for PA oe 1" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" bitfld.byte 0x0C 0.--1. " OE_SEL0 ,Data selection for PA oe 0" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" line.byte 0x0D "CFG13,PA OE Select Register - High" bitfld.byte 0x0D 6.--7. " OE_SEL7 ,Data selection for PA oe 7" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" bitfld.byte 0x0D 4.--5. " OE_SEL6 ,Data selection for PA oe 6" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" bitfld.byte 0x0D 2.--3. " OE_SEL5 ,Data selection for PA oe 5" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" bitfld.byte 0x0D 0.--1. " OE_SEL4 ,Data selection for PA oe 4" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" line.byte 0x0E "CFG14,PA OE Sync Register" bitfld.byte 0x0E 6.--7. " OE_SYNC3 ,Synchronization options for dsi_to_oe[3]" "TRANSPARENT,SINGLESYNC,CONSTANT1,CONSTANT0" bitfld.byte 0x0E 4.--5. " OE_SYNC2 ,Synchronization options for dsi_to_oe[2]" "TRANSPARENT,SINGLESYNC,CONSTANT1,CONSTANT0" bitfld.byte 0x0E 2.--3. " OE_SYNC1 ,Synchronization options for dsi_to_oe[1]" "TRANSPARENT,SINGLESYNC,CONSTANT1,CONSTANT0" bitfld.byte 0x0E 0.--1. " OE_SYNC0 ,Synchronization options for dsi_to_oe[0]" "TRANSPARENT,SINGLESYNC,CONSTANT1,CONSTANT0" width 0x0B tree.end tree "UDB_P3" base ad:0x400F5030 width 7. group.byte 0x00++0x0E line.byte 0x00 "CFG0,PA Data In Clock Control Register" bitfld.byte 0x00 6.--7. " NC ,Spare register bits NC" "0,1,2,3" bitfld.byte 0x00 5. " CLKIN_INV ,Determines whether the selected clock is inverted or not" "Not inverted,Inverted" bitfld.byte 0x00 4. " CLKIN_EN_INV ,Determines whether the selected enable is inverted or not" "Not inverted,Inverted" bitfld.byte 0x00 2.--3. " CLKIN_EN_MODE ,Select one of four operating modes" "Off,On,Posedge,Level" textline " " bitfld.byte 0x00 0.--1. " CLKIN_EN_SEL ,Select one of four choices for clock enable" "PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2" line.byte 0x01 "CFG1,PA Data Out Clock Control Register" bitfld.byte 0x01 6.--7. " NC ,Spare register bits NC" "0,1,2,3" bitfld.byte 0x01 5. " CLKOUT_INV ,Determines whether the selected clock is inverted or not" "Not inverted,Inverted" bitfld.byte 0x01 4. " CLKOUT_EN_INV ,Determines whether the selected enable is inverted or not" "Not inverted,Inverted" bitfld.byte 0x01 2.--3. " CLKOUT_EN_MODE ,Select one of four operating modes" "Off,On,Posedge,Level" textline " " bitfld.byte 0x01 0.--1. " CLKOUT_EN_SEL ,Select one of four choices for clock enable" "PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2" line.byte 0x02 "CFG2,PA Clock Select Register" bitfld.byte 0x02 4.--7. " CLKOUT_SEL ,Select one of four choices for clock enable" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,,BUS_CLK_APP,,,PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2" bitfld.byte 0x02 0.--3. " CLKIN_SEL ,Select one of four choices for clock enable" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,,BUS_CLK_APP,,,PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2" line.byte 0x03 "CFG3,PA Reset Select Register" bitfld.byte 0x03 7. " NC7 ,Spare register bit NC7" "0,1" bitfld.byte 0x03 6. " RES_OUT_INV ,Select the polarity of the reset control" "Not inverted,Inverted" bitfld.byte 0x03 4.--5. " RES_OUT_SEL ,Select one of four inputs to serve as the reset control to the block" "PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2" bitfld.byte 0x03 3. " NC0 ,Spare register bit NC0" "0,1" textline " " bitfld.byte 0x03 2. " RES_IN_INV ,Select the polarity of the reset control" "Not inverted,Inverted" bitfld.byte 0x03 0.--1. " RES_IN_SEL ,Select one of four inputs to serve as the reset control to the block" "PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2" line.byte 0x04 "CFG4,PA Reset Enable Register" bitfld.byte 0x04 3.--7. " NC7654 ,Spare register bits NC7654" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.byte 0x04 2. " RES_OE_EN ,Enable the selected reset" "Disabled,Enabled" bitfld.byte 0x04 1. " RES_OUT_EN ,Enable the selected reset" "Disabled,Enabled" bitfld.byte 0x04 0. " RES_IN_EN ,Enable the selected reset" "Disabled,Enabled" line.byte 0x05 "CFG5,PA Reset Pin Select Register" bitfld.byte 0x05 3.--7. " NC7654 ,Spare register bits NC7654" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.byte 0x05 0. " PIN_SEL ,Select port input to route to reset multiplexer" "No reset,Reset" line.byte 0x06 "CFG6,PA Input Data Sync Control Register - Low" bitfld.byte 0x06 6.--7. " IN_SYNC3 ,Synchronization selection for PA input 3" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." bitfld.byte 0x06 4.--5. " IN_SYNC2 ,Synchronization selection for PA input 2" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." bitfld.byte 0x06 2.--3. " IN_SYNC1 ,Synchronization selection for PA input 1" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." bitfld.byte 0x06 0.--1. " IN_SYNC0 ,Synchronization selection for PA input 0" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." line.byte 0x07 "CFG7,PA Input Data Sync Control Register - High" bitfld.byte 0x07 6.--7. " IN_SYNC7 ,Synchronization selection for PA input 7" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." bitfld.byte 0x07 4.--5. " IN_SYNC6 ,Synchronization selection for PA input 6" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." bitfld.byte 0x07 2.--3. " IN_SYNC5 ,Synchronization selection for PA input 5" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." bitfld.byte 0x07 0.--1. " IN_SYNC4 ,Synchronization selection for PA input 4" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." line.byte 0x08 "CFG8,PA Output Data Sync Control Register - Low" bitfld.byte 0x08 6.--7. " OUT_SYNC3 ,Synchronization selection for PA output 3" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" bitfld.byte 0x08 4.--5. " OUT_SYNC2 ,Synchronization selection for PA output 2" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" bitfld.byte 0x08 2.--3. " OUT_SYNC1 ,Synchronization selection for PA output 1" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" bitfld.byte 0x08 0.--1. " OUT_SYNC0 ,Synchronization selection for PA output 0" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" line.byte 0x09 "CFG9,PA Output Data Sync Control Register - High" bitfld.byte 0x09 6.--7. " OUT_SYNC7 ,Synchronization selection for PA output 7" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" bitfld.byte 0x09 4.--5. " OUT_SYNC6 ,Synchronization selection for PA output 6" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" bitfld.byte 0x09 2.--3. " OUT_SYNC5 ,Synchronization selection for PA output 5" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" bitfld.byte 0x09 0.--1. " OUT_SYNC4 ,Synchronization selection for PA output 4" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" line.byte 0x0A "CFG10,PA Output Data Select Register - Low" bitfld.byte 0x0A 6.--7. " DATA_SEL3 ,Data selection for PA output 3" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" bitfld.byte 0x0A 4.--5. " DATA_SEL2 ,Data selection for PA output 2" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" bitfld.byte 0x0A 2.--3. " DATA_SEL1 ,Data selection for PA output 1" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" bitfld.byte 0x0A 0.--1. " DATA_SEL0 ,Data selection for PA output 0" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" line.byte 0x0B "CFG11,PA Output Data Select Register - High" bitfld.byte 0x0B 6.--7. " DATA_SEL7 ,Data selection for PA output 7" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" bitfld.byte 0x0B 4.--5. " DATA_SEL6 ,Data selection for PA output 6" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" bitfld.byte 0x0B 2.--3. " DATA_SEL5 ,Data selection for PA output 5" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" bitfld.byte 0x0B 0.--1. " DATA_SEL4 ,Data selection for PA output 4" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" line.byte 0x0C "CFG12,PA OE Select Register - Low" bitfld.byte 0x0C 6.--7. " OE_SEL3 ,Data selection for PA oe 3" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" bitfld.byte 0x0C 4.--5. " OE_SEL2 ,Data selection for PA oe 2" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" bitfld.byte 0x0C 2.--3. " OE_SEL1 ,Data selection for PA oe 1" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" bitfld.byte 0x0C 0.--1. " OE_SEL0 ,Data selection for PA oe 0" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" line.byte 0x0D "CFG13,PA OE Select Register - High" bitfld.byte 0x0D 6.--7. " OE_SEL7 ,Data selection for PA oe 7" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" bitfld.byte 0x0D 4.--5. " OE_SEL6 ,Data selection for PA oe 6" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" bitfld.byte 0x0D 2.--3. " OE_SEL5 ,Data selection for PA oe 5" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" bitfld.byte 0x0D 0.--1. " OE_SEL4 ,Data selection for PA oe 4" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" line.byte 0x0E "CFG14,PA OE Sync Register" bitfld.byte 0x0E 6.--7. " OE_SYNC3 ,Synchronization options for dsi_to_oe[3]" "TRANSPARENT,SINGLESYNC,CONSTANT1,CONSTANT0" bitfld.byte 0x0E 4.--5. " OE_SYNC2 ,Synchronization options for dsi_to_oe[2]" "TRANSPARENT,SINGLESYNC,CONSTANT1,CONSTANT0" bitfld.byte 0x0E 2.--3. " OE_SYNC1 ,Synchronization options for dsi_to_oe[1]" "TRANSPARENT,SINGLESYNC,CONSTANT1,CONSTANT0" bitfld.byte 0x0E 0.--1. " OE_SYNC0 ,Synchronization options for dsi_to_oe[0]" "TRANSPARENT,SINGLESYNC,CONSTANT1,CONSTANT0" width 0x0B tree.end tree "UDB_P4" base ad:0x400F5040 width 7. group.byte 0x00++0x0E line.byte 0x00 "CFG0,PA Data In Clock Control Register" bitfld.byte 0x00 6.--7. " NC ,Spare register bits NC" "0,1,2,3" bitfld.byte 0x00 5. " CLKIN_INV ,Determines whether the selected clock is inverted or not" "Not inverted,Inverted" bitfld.byte 0x00 4. " CLKIN_EN_INV ,Determines whether the selected enable is inverted or not" "Not inverted,Inverted" bitfld.byte 0x00 2.--3. " CLKIN_EN_MODE ,Select one of four operating modes" "Off,On,Posedge,Level" textline " " bitfld.byte 0x00 0.--1. " CLKIN_EN_SEL ,Select one of four choices for clock enable" "PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2" line.byte 0x01 "CFG1,PA Data Out Clock Control Register" bitfld.byte 0x01 6.--7. " NC ,Spare register bits NC" "0,1,2,3" bitfld.byte 0x01 5. " CLKOUT_INV ,Determines whether the selected clock is inverted or not" "Not inverted,Inverted" bitfld.byte 0x01 4. " CLKOUT_EN_INV ,Determines whether the selected enable is inverted or not" "Not inverted,Inverted" bitfld.byte 0x01 2.--3. " CLKOUT_EN_MODE ,Select one of four operating modes" "Off,On,Posedge,Level" textline " " bitfld.byte 0x01 0.--1. " CLKOUT_EN_SEL ,Select one of four choices for clock enable" "PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2" line.byte 0x02 "CFG2,PA Clock Select Register" bitfld.byte 0x02 4.--7. " CLKOUT_SEL ,Select one of four choices for clock enable" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,,BUS_CLK_APP,,,PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2" bitfld.byte 0x02 0.--3. " CLKIN_SEL ,Select one of four choices for clock enable" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,,BUS_CLK_APP,,,PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2" line.byte 0x03 "CFG3,PA Reset Select Register" bitfld.byte 0x03 7. " NC7 ,Spare register bit NC7" "0,1" bitfld.byte 0x03 6. " RES_OUT_INV ,Select the polarity of the reset control" "Not inverted,Inverted" bitfld.byte 0x03 4.--5. " RES_OUT_SEL ,Select one of four inputs to serve as the reset control to the block" "PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2" bitfld.byte 0x03 3. " NC0 ,Spare register bit NC0" "0,1" textline " " bitfld.byte 0x03 2. " RES_IN_INV ,Select the polarity of the reset control" "Not inverted,Inverted" bitfld.byte 0x03 0.--1. " RES_IN_SEL ,Select one of four inputs to serve as the reset control to the block" "PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2" line.byte 0x04 "CFG4,PA Reset Enable Register" bitfld.byte 0x04 3.--7. " NC7654 ,Spare register bits NC7654" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.byte 0x04 2. " RES_OE_EN ,Enable the selected reset" "Disabled,Enabled" bitfld.byte 0x04 1. " RES_OUT_EN ,Enable the selected reset" "Disabled,Enabled" bitfld.byte 0x04 0. " RES_IN_EN ,Enable the selected reset" "Disabled,Enabled" line.byte 0x05 "CFG5,PA Reset Pin Select Register" bitfld.byte 0x05 3.--7. " NC7654 ,Spare register bits NC7654" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.byte 0x05 0. " PIN_SEL ,Select port input to route to reset multiplexer" "No reset,Reset" line.byte 0x06 "CFG6,PA Input Data Sync Control Register - Low" bitfld.byte 0x06 6.--7. " IN_SYNC3 ,Synchronization selection for PA input 3" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." bitfld.byte 0x06 4.--5. " IN_SYNC2 ,Synchronization selection for PA input 2" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." bitfld.byte 0x06 2.--3. " IN_SYNC1 ,Synchronization selection for PA input 1" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." bitfld.byte 0x06 0.--1. " IN_SYNC0 ,Synchronization selection for PA input 0" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." line.byte 0x07 "CFG7,PA Input Data Sync Control Register - High" bitfld.byte 0x07 6.--7. " IN_SYNC7 ,Synchronization selection for PA input 7" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." bitfld.byte 0x07 4.--5. " IN_SYNC6 ,Synchronization selection for PA input 6" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." bitfld.byte 0x07 2.--3. " IN_SYNC5 ,Synchronization selection for PA input 5" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." bitfld.byte 0x07 0.--1. " IN_SYNC4 ,Synchronization selection for PA input 4" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." line.byte 0x08 "CFG8,PA Output Data Sync Control Register - Low" bitfld.byte 0x08 6.--7. " OUT_SYNC3 ,Synchronization selection for PA output 3" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" bitfld.byte 0x08 4.--5. " OUT_SYNC2 ,Synchronization selection for PA output 2" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" bitfld.byte 0x08 2.--3. " OUT_SYNC1 ,Synchronization selection for PA output 1" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" bitfld.byte 0x08 0.--1. " OUT_SYNC0 ,Synchronization selection for PA output 0" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" line.byte 0x09 "CFG9,PA Output Data Sync Control Register - High" bitfld.byte 0x09 6.--7. " OUT_SYNC7 ,Synchronization selection for PA output 7" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" bitfld.byte 0x09 4.--5. " OUT_SYNC6 ,Synchronization selection for PA output 6" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" bitfld.byte 0x09 2.--3. " OUT_SYNC5 ,Synchronization selection for PA output 5" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" bitfld.byte 0x09 0.--1. " OUT_SYNC4 ,Synchronization selection for PA output 4" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" line.byte 0x0A "CFG10,PA Output Data Select Register - Low" bitfld.byte 0x0A 6.--7. " DATA_SEL3 ,Data selection for PA output 3" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" bitfld.byte 0x0A 4.--5. " DATA_SEL2 ,Data selection for PA output 2" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" bitfld.byte 0x0A 2.--3. " DATA_SEL1 ,Data selection for PA output 1" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" bitfld.byte 0x0A 0.--1. " DATA_SEL0 ,Data selection for PA output 0" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" line.byte 0x0B "CFG11,PA Output Data Select Register - High" bitfld.byte 0x0B 6.--7. " DATA_SEL7 ,Data selection for PA output 7" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" bitfld.byte 0x0B 4.--5. " DATA_SEL6 ,Data selection for PA output 6" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" bitfld.byte 0x0B 2.--3. " DATA_SEL5 ,Data selection for PA output 5" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" bitfld.byte 0x0B 0.--1. " DATA_SEL4 ,Data selection for PA output 4" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" line.byte 0x0C "CFG12,PA OE Select Register - Low" bitfld.byte 0x0C 6.--7. " OE_SEL3 ,Data selection for PA oe 3" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" bitfld.byte 0x0C 4.--5. " OE_SEL2 ,Data selection for PA oe 2" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" bitfld.byte 0x0C 2.--3. " OE_SEL1 ,Data selection for PA oe 1" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" bitfld.byte 0x0C 0.--1. " OE_SEL0 ,Data selection for PA oe 0" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" line.byte 0x0D "CFG13,PA OE Select Register - High" bitfld.byte 0x0D 6.--7. " OE_SEL7 ,Data selection for PA oe 7" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" bitfld.byte 0x0D 4.--5. " OE_SEL6 ,Data selection for PA oe 6" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" bitfld.byte 0x0D 2.--3. " OE_SEL5 ,Data selection for PA oe 5" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" bitfld.byte 0x0D 0.--1. " OE_SEL4 ,Data selection for PA oe 4" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" line.byte 0x0E "CFG14,PA OE Sync Register" bitfld.byte 0x0E 6.--7. " OE_SYNC3 ,Synchronization options for dsi_to_oe[3]" "TRANSPARENT,SINGLESYNC,CONSTANT1,CONSTANT0" bitfld.byte 0x0E 4.--5. " OE_SYNC2 ,Synchronization options for dsi_to_oe[2]" "TRANSPARENT,SINGLESYNC,CONSTANT1,CONSTANT0" bitfld.byte 0x0E 2.--3. " OE_SYNC1 ,Synchronization options for dsi_to_oe[1]" "TRANSPARENT,SINGLESYNC,CONSTANT1,CONSTANT0" bitfld.byte 0x0E 0.--1. " OE_SYNC0 ,Synchronization options for dsi_to_oe[0]" "TRANSPARENT,SINGLESYNC,CONSTANT1,CONSTANT0" width 0x0B tree.end tree "UDB_P5" base ad:0x400F5050 width 7. group.byte 0x00++0x0E line.byte 0x00 "CFG0,PA Data In Clock Control Register" bitfld.byte 0x00 6.--7. " NC ,Spare register bits NC" "0,1,2,3" bitfld.byte 0x00 5. " CLKIN_INV ,Determines whether the selected clock is inverted or not" "Not inverted,Inverted" bitfld.byte 0x00 4. " CLKIN_EN_INV ,Determines whether the selected enable is inverted or not" "Not inverted,Inverted" bitfld.byte 0x00 2.--3. " CLKIN_EN_MODE ,Select one of four operating modes" "Off,On,Posedge,Level" textline " " bitfld.byte 0x00 0.--1. " CLKIN_EN_SEL ,Select one of four choices for clock enable" "PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2" line.byte 0x01 "CFG1,PA Data Out Clock Control Register" bitfld.byte 0x01 6.--7. " NC ,Spare register bits NC" "0,1,2,3" bitfld.byte 0x01 5. " CLKOUT_INV ,Determines whether the selected clock is inverted or not" "Not inverted,Inverted" bitfld.byte 0x01 4. " CLKOUT_EN_INV ,Determines whether the selected enable is inverted or not" "Not inverted,Inverted" bitfld.byte 0x01 2.--3. " CLKOUT_EN_MODE ,Select one of four operating modes" "Off,On,Posedge,Level" textline " " bitfld.byte 0x01 0.--1. " CLKOUT_EN_SEL ,Select one of four choices for clock enable" "PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2" line.byte 0x02 "CFG2,PA Clock Select Register" bitfld.byte 0x02 4.--7. " CLKOUT_SEL ,Select one of four choices for clock enable" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,,BUS_CLK_APP,,,PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2" bitfld.byte 0x02 0.--3. " CLKIN_SEL ,Select one of four choices for clock enable" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,,BUS_CLK_APP,,,PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2" line.byte 0x03 "CFG3,PA Reset Select Register" bitfld.byte 0x03 7. " NC7 ,Spare register bit NC7" "0,1" bitfld.byte 0x03 6. " RES_OUT_INV ,Select the polarity of the reset control" "Not inverted,Inverted" bitfld.byte 0x03 4.--5. " RES_OUT_SEL ,Select one of four inputs to serve as the reset control to the block" "PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2" bitfld.byte 0x03 3. " NC0 ,Spare register bit NC0" "0,1" textline " " bitfld.byte 0x03 2. " RES_IN_INV ,Select the polarity of the reset control" "Not inverted,Inverted" bitfld.byte 0x03 0.--1. " RES_IN_SEL ,Select one of four inputs to serve as the reset control to the block" "PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2" line.byte 0x04 "CFG4,PA Reset Enable Register" bitfld.byte 0x04 3.--7. " NC7654 ,Spare register bits NC7654" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.byte 0x04 2. " RES_OE_EN ,Enable the selected reset" "Disabled,Enabled" bitfld.byte 0x04 1. " RES_OUT_EN ,Enable the selected reset" "Disabled,Enabled" bitfld.byte 0x04 0. " RES_IN_EN ,Enable the selected reset" "Disabled,Enabled" line.byte 0x05 "CFG5,PA Reset Pin Select Register" bitfld.byte 0x05 3.--7. " NC7654 ,Spare register bits NC7654" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.byte 0x05 0. " PIN_SEL ,Select port input to route to reset multiplexer" "No reset,Reset" line.byte 0x06 "CFG6,PA Input Data Sync Control Register - Low" bitfld.byte 0x06 6.--7. " IN_SYNC3 ,Synchronization selection for PA input 3" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." bitfld.byte 0x06 4.--5. " IN_SYNC2 ,Synchronization selection for PA input 2" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." bitfld.byte 0x06 2.--3. " IN_SYNC1 ,Synchronization selection for PA input 1" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." bitfld.byte 0x06 0.--1. " IN_SYNC0 ,Synchronization selection for PA input 0" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." line.byte 0x07 "CFG7,PA Input Data Sync Control Register - High" bitfld.byte 0x07 6.--7. " IN_SYNC7 ,Synchronization selection for PA input 7" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." bitfld.byte 0x07 4.--5. " IN_SYNC6 ,Synchronization selection for PA input 6" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." bitfld.byte 0x07 2.--3. " IN_SYNC5 ,Synchronization selection for PA input 5" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." bitfld.byte 0x07 0.--1. " IN_SYNC4 ,Synchronization selection for PA input 4" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." line.byte 0x08 "CFG8,PA Output Data Sync Control Register - Low" bitfld.byte 0x08 6.--7. " OUT_SYNC3 ,Synchronization selection for PA output 3" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" bitfld.byte 0x08 4.--5. " OUT_SYNC2 ,Synchronization selection for PA output 2" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" bitfld.byte 0x08 2.--3. " OUT_SYNC1 ,Synchronization selection for PA output 1" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" bitfld.byte 0x08 0.--1. " OUT_SYNC0 ,Synchronization selection for PA output 0" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" line.byte 0x09 "CFG9,PA Output Data Sync Control Register - High" bitfld.byte 0x09 6.--7. " OUT_SYNC7 ,Synchronization selection for PA output 7" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" bitfld.byte 0x09 4.--5. " OUT_SYNC6 ,Synchronization selection for PA output 6" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" bitfld.byte 0x09 2.--3. " OUT_SYNC5 ,Synchronization selection for PA output 5" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" bitfld.byte 0x09 0.--1. " OUT_SYNC4 ,Synchronization selection for PA output 4" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" line.byte 0x0A "CFG10,PA Output Data Select Register - Low" bitfld.byte 0x0A 6.--7. " DATA_SEL3 ,Data selection for PA output 3" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" bitfld.byte 0x0A 4.--5. " DATA_SEL2 ,Data selection for PA output 2" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" bitfld.byte 0x0A 2.--3. " DATA_SEL1 ,Data selection for PA output 1" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" bitfld.byte 0x0A 0.--1. " DATA_SEL0 ,Data selection for PA output 0" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" line.byte 0x0B "CFG11,PA Output Data Select Register - High" bitfld.byte 0x0B 6.--7. " DATA_SEL7 ,Data selection for PA output 7" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" bitfld.byte 0x0B 4.--5. " DATA_SEL6 ,Data selection for PA output 6" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" bitfld.byte 0x0B 2.--3. " DATA_SEL5 ,Data selection for PA output 5" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" bitfld.byte 0x0B 0.--1. " DATA_SEL4 ,Data selection for PA output 4" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" line.byte 0x0C "CFG12,PA OE Select Register - Low" bitfld.byte 0x0C 6.--7. " OE_SEL3 ,Data selection for PA oe 3" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" bitfld.byte 0x0C 4.--5. " OE_SEL2 ,Data selection for PA oe 2" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" bitfld.byte 0x0C 2.--3. " OE_SEL1 ,Data selection for PA oe 1" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" bitfld.byte 0x0C 0.--1. " OE_SEL0 ,Data selection for PA oe 0" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" line.byte 0x0D "CFG13,PA OE Select Register - High" bitfld.byte 0x0D 6.--7. " OE_SEL7 ,Data selection for PA oe 7" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" bitfld.byte 0x0D 4.--5. " OE_SEL6 ,Data selection for PA oe 6" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" bitfld.byte 0x0D 2.--3. " OE_SEL5 ,Data selection for PA oe 5" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" bitfld.byte 0x0D 0.--1. " OE_SEL4 ,Data selection for PA oe 4" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" line.byte 0x0E "CFG14,PA OE Sync Register" bitfld.byte 0x0E 6.--7. " OE_SYNC3 ,Synchronization options for dsi_to_oe[3]" "TRANSPARENT,SINGLESYNC,CONSTANT1,CONSTANT0" bitfld.byte 0x0E 4.--5. " OE_SYNC2 ,Synchronization options for dsi_to_oe[2]" "TRANSPARENT,SINGLESYNC,CONSTANT1,CONSTANT0" bitfld.byte 0x0E 2.--3. " OE_SYNC1 ,Synchronization options for dsi_to_oe[1]" "TRANSPARENT,SINGLESYNC,CONSTANT1,CONSTANT0" bitfld.byte 0x0E 0.--1. " OE_SYNC0 ,Synchronization options for dsi_to_oe[0]" "TRANSPARENT,SINGLESYNC,CONSTANT1,CONSTANT0" width 0x0B tree.end tree "UDB_P6" base ad:0x400F5060 width 7. group.byte 0x00++0x0E line.byte 0x00 "CFG0,PA Data In Clock Control Register" bitfld.byte 0x00 6.--7. " NC ,Spare register bits NC" "0,1,2,3" bitfld.byte 0x00 5. " CLKIN_INV ,Determines whether the selected clock is inverted or not" "Not inverted,Inverted" bitfld.byte 0x00 4. " CLKIN_EN_INV ,Determines whether the selected enable is inverted or not" "Not inverted,Inverted" bitfld.byte 0x00 2.--3. " CLKIN_EN_MODE ,Select one of four operating modes" "Off,On,Posedge,Level" textline " " bitfld.byte 0x00 0.--1. " CLKIN_EN_SEL ,Select one of four choices for clock enable" "PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2" line.byte 0x01 "CFG1,PA Data Out Clock Control Register" bitfld.byte 0x01 6.--7. " NC ,Spare register bits NC" "0,1,2,3" bitfld.byte 0x01 5. " CLKOUT_INV ,Determines whether the selected clock is inverted or not" "Not inverted,Inverted" bitfld.byte 0x01 4. " CLKOUT_EN_INV ,Determines whether the selected enable is inverted or not" "Not inverted,Inverted" bitfld.byte 0x01 2.--3. " CLKOUT_EN_MODE ,Select one of four operating modes" "Off,On,Posedge,Level" textline " " bitfld.byte 0x01 0.--1. " CLKOUT_EN_SEL ,Select one of four choices for clock enable" "PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2" line.byte 0x02 "CFG2,PA Clock Select Register" bitfld.byte 0x02 4.--7. " CLKOUT_SEL ,Select one of four choices for clock enable" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,,BUS_CLK_APP,,,PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2" bitfld.byte 0x02 0.--3. " CLKIN_SEL ,Select one of four choices for clock enable" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,,BUS_CLK_APP,,,PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2" line.byte 0x03 "CFG3,PA Reset Select Register" bitfld.byte 0x03 7. " NC7 ,Spare register bit NC7" "0,1" bitfld.byte 0x03 6. " RES_OUT_INV ,Select the polarity of the reset control" "Not inverted,Inverted" bitfld.byte 0x03 4.--5. " RES_OUT_SEL ,Select one of four inputs to serve as the reset control to the block" "PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2" bitfld.byte 0x03 3. " NC0 ,Spare register bit NC0" "0,1" textline " " bitfld.byte 0x03 2. " RES_IN_INV ,Select the polarity of the reset control" "Not inverted,Inverted" bitfld.byte 0x03 0.--1. " RES_IN_SEL ,Select one of four inputs to serve as the reset control to the block" "PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2" line.byte 0x04 "CFG4,PA Reset Enable Register" bitfld.byte 0x04 3.--7. " NC7654 ,Spare register bits NC7654" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.byte 0x04 2. " RES_OE_EN ,Enable the selected reset" "Disabled,Enabled" bitfld.byte 0x04 1. " RES_OUT_EN ,Enable the selected reset" "Disabled,Enabled" bitfld.byte 0x04 0. " RES_IN_EN ,Enable the selected reset" "Disabled,Enabled" line.byte 0x05 "CFG5,PA Reset Pin Select Register" bitfld.byte 0x05 3.--7. " NC7654 ,Spare register bits NC7654" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.byte 0x05 0. " PIN_SEL ,Select port input to route to reset multiplexer" "No reset,Reset" line.byte 0x06 "CFG6,PA Input Data Sync Control Register - Low" bitfld.byte 0x06 6.--7. " IN_SYNC3 ,Synchronization selection for PA input 3" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." bitfld.byte 0x06 4.--5. " IN_SYNC2 ,Synchronization selection for PA input 2" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." bitfld.byte 0x06 2.--3. " IN_SYNC1 ,Synchronization selection for PA input 1" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." bitfld.byte 0x06 0.--1. " IN_SYNC0 ,Synchronization selection for PA input 0" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." line.byte 0x07 "CFG7,PA Input Data Sync Control Register - High" bitfld.byte 0x07 6.--7. " IN_SYNC7 ,Synchronization selection for PA input 7" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." bitfld.byte 0x07 4.--5. " IN_SYNC6 ,Synchronization selection for PA input 6" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." bitfld.byte 0x07 2.--3. " IN_SYNC5 ,Synchronization selection for PA input 5" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." bitfld.byte 0x07 0.--1. " IN_SYNC4 ,Synchronization selection for PA input 4" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." line.byte 0x08 "CFG8,PA Output Data Sync Control Register - Low" bitfld.byte 0x08 6.--7. " OUT_SYNC3 ,Synchronization selection for PA output 3" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" bitfld.byte 0x08 4.--5. " OUT_SYNC2 ,Synchronization selection for PA output 2" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" bitfld.byte 0x08 2.--3. " OUT_SYNC1 ,Synchronization selection for PA output 1" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" bitfld.byte 0x08 0.--1. " OUT_SYNC0 ,Synchronization selection for PA output 0" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" line.byte 0x09 "CFG9,PA Output Data Sync Control Register - High" bitfld.byte 0x09 6.--7. " OUT_SYNC7 ,Synchronization selection for PA output 7" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" bitfld.byte 0x09 4.--5. " OUT_SYNC6 ,Synchronization selection for PA output 6" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" bitfld.byte 0x09 2.--3. " OUT_SYNC5 ,Synchronization selection for PA output 5" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" bitfld.byte 0x09 0.--1. " OUT_SYNC4 ,Synchronization selection for PA output 4" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" line.byte 0x0A "CFG10,PA Output Data Select Register - Low" bitfld.byte 0x0A 6.--7. " DATA_SEL3 ,Data selection for PA output 3" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" bitfld.byte 0x0A 4.--5. " DATA_SEL2 ,Data selection for PA output 2" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" bitfld.byte 0x0A 2.--3. " DATA_SEL1 ,Data selection for PA output 1" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" bitfld.byte 0x0A 0.--1. " DATA_SEL0 ,Data selection for PA output 0" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" line.byte 0x0B "CFG11,PA Output Data Select Register - High" bitfld.byte 0x0B 6.--7. " DATA_SEL7 ,Data selection for PA output 7" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" bitfld.byte 0x0B 4.--5. " DATA_SEL6 ,Data selection for PA output 6" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" bitfld.byte 0x0B 2.--3. " DATA_SEL5 ,Data selection for PA output 5" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" bitfld.byte 0x0B 0.--1. " DATA_SEL4 ,Data selection for PA output 4" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" line.byte 0x0C "CFG12,PA OE Select Register - Low" bitfld.byte 0x0C 6.--7. " OE_SEL3 ,Data selection for PA oe 3" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" bitfld.byte 0x0C 4.--5. " OE_SEL2 ,Data selection for PA oe 2" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" bitfld.byte 0x0C 2.--3. " OE_SEL1 ,Data selection for PA oe 1" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" bitfld.byte 0x0C 0.--1. " OE_SEL0 ,Data selection for PA oe 0" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" line.byte 0x0D "CFG13,PA OE Select Register - High" bitfld.byte 0x0D 6.--7. " OE_SEL7 ,Data selection for PA oe 7" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" bitfld.byte 0x0D 4.--5. " OE_SEL6 ,Data selection for PA oe 6" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" bitfld.byte 0x0D 2.--3. " OE_SEL5 ,Data selection for PA oe 5" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" bitfld.byte 0x0D 0.--1. " OE_SEL4 ,Data selection for PA oe 4" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" line.byte 0x0E "CFG14,PA OE Sync Register" bitfld.byte 0x0E 6.--7. " OE_SYNC3 ,Synchronization options for dsi_to_oe[3]" "TRANSPARENT,SINGLESYNC,CONSTANT1,CONSTANT0" bitfld.byte 0x0E 4.--5. " OE_SYNC2 ,Synchronization options for dsi_to_oe[2]" "TRANSPARENT,SINGLESYNC,CONSTANT1,CONSTANT0" bitfld.byte 0x0E 2.--3. " OE_SYNC1 ,Synchronization options for dsi_to_oe[1]" "TRANSPARENT,SINGLESYNC,CONSTANT1,CONSTANT0" bitfld.byte 0x0E 0.--1. " OE_SYNC0 ,Synchronization options for dsi_to_oe[0]" "TRANSPARENT,SINGLESYNC,CONSTANT1,CONSTANT0" width 0x0B tree.end tree "UDB_P7" base ad:0x400F5070 width 7. group.byte 0x00++0x0E line.byte 0x00 "CFG0,PA Data In Clock Control Register" bitfld.byte 0x00 6.--7. " NC ,Spare register bits NC" "0,1,2,3" bitfld.byte 0x00 5. " CLKIN_INV ,Determines whether the selected clock is inverted or not" "Not inverted,Inverted" bitfld.byte 0x00 4. " CLKIN_EN_INV ,Determines whether the selected enable is inverted or not" "Not inverted,Inverted" bitfld.byte 0x00 2.--3. " CLKIN_EN_MODE ,Select one of four operating modes" "Off,On,Posedge,Level" textline " " bitfld.byte 0x00 0.--1. " CLKIN_EN_SEL ,Select one of four choices for clock enable" "PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2" line.byte 0x01 "CFG1,PA Data Out Clock Control Register" bitfld.byte 0x01 6.--7. " NC ,Spare register bits NC" "0,1,2,3" bitfld.byte 0x01 5. " CLKOUT_INV ,Determines whether the selected clock is inverted or not" "Not inverted,Inverted" bitfld.byte 0x01 4. " CLKOUT_EN_INV ,Determines whether the selected enable is inverted or not" "Not inverted,Inverted" bitfld.byte 0x01 2.--3. " CLKOUT_EN_MODE ,Select one of four operating modes" "Off,On,Posedge,Level" textline " " bitfld.byte 0x01 0.--1. " CLKOUT_EN_SEL ,Select one of four choices for clock enable" "PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2" line.byte 0x02 "CFG2,PA Clock Select Register" bitfld.byte 0x02 4.--7. " CLKOUT_SEL ,Select one of four choices for clock enable" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,,BUS_CLK_APP,,,PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2" bitfld.byte 0x02 0.--3. " CLKIN_SEL ,Select one of four choices for clock enable" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,,BUS_CLK_APP,,,PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2" line.byte 0x03 "CFG3,PA Reset Select Register" bitfld.byte 0x03 7. " NC7 ,Spare register bit NC7" "0,1" bitfld.byte 0x03 6. " RES_OUT_INV ,Select the polarity of the reset control" "Not inverted,Inverted" bitfld.byte 0x03 4.--5. " RES_OUT_SEL ,Select one of four inputs to serve as the reset control to the block" "PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2" bitfld.byte 0x03 3. " NC0 ,Spare register bit NC0" "0,1" textline " " bitfld.byte 0x03 2. " RES_IN_INV ,Select the polarity of the reset control" "Not inverted,Inverted" bitfld.byte 0x03 0.--1. " RES_IN_SEL ,Select one of four inputs to serve as the reset control to the block" "PIN_RC,DSI_RC_0,DSI_RC_1,DSI_RC_2" line.byte 0x04 "CFG4,PA Reset Enable Register" bitfld.byte 0x04 3.--7. " NC7654 ,Spare register bits NC7654" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.byte 0x04 2. " RES_OE_EN ,Enable the selected reset" "Disabled,Enabled" bitfld.byte 0x04 1. " RES_OUT_EN ,Enable the selected reset" "Disabled,Enabled" bitfld.byte 0x04 0. " RES_IN_EN ,Enable the selected reset" "Disabled,Enabled" line.byte 0x05 "CFG5,PA Reset Pin Select Register" bitfld.byte 0x05 3.--7. " NC7654 ,Spare register bits NC7654" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.byte 0x05 0. " PIN_SEL ,Select port input to route to reset multiplexer" "No reset,Reset" line.byte 0x06 "CFG6,PA Input Data Sync Control Register - Low" bitfld.byte 0x06 6.--7. " IN_SYNC3 ,Synchronization selection for PA input 3" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." bitfld.byte 0x06 4.--5. " IN_SYNC2 ,Synchronization selection for PA input 2" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." bitfld.byte 0x06 2.--3. " IN_SYNC1 ,Synchronization selection for PA input 1" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." bitfld.byte 0x06 0.--1. " IN_SYNC0 ,Synchronization selection for PA input 0" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." line.byte 0x07 "CFG7,PA Input Data Sync Control Register - High" bitfld.byte 0x07 6.--7. " IN_SYNC7 ,Synchronization selection for PA input 7" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." bitfld.byte 0x07 4.--5. " IN_SYNC6 ,Synchronization selection for PA input 6" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." bitfld.byte 0x07 2.--3. " IN_SYNC5 ,Synchronization selection for PA input 5" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." bitfld.byte 0x07 0.--1. " IN_SYNC4 ,Synchronization selection for PA input 4" "TRANSPARENT,SINGLESYNC,DOUBLESYNC,?..." line.byte 0x08 "CFG8,PA Output Data Sync Control Register - Low" bitfld.byte 0x08 6.--7. " OUT_SYNC3 ,Synchronization selection for PA output 3" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" bitfld.byte 0x08 4.--5. " OUT_SYNC2 ,Synchronization selection for PA output 2" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" bitfld.byte 0x08 2.--3. " OUT_SYNC1 ,Synchronization selection for PA output 1" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" bitfld.byte 0x08 0.--1. " OUT_SYNC0 ,Synchronization selection for PA output 0" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" line.byte 0x09 "CFG9,PA Output Data Sync Control Register - High" bitfld.byte 0x09 6.--7. " OUT_SYNC7 ,Synchronization selection for PA output 7" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" bitfld.byte 0x09 4.--5. " OUT_SYNC6 ,Synchronization selection for PA output 6" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" bitfld.byte 0x09 2.--3. " OUT_SYNC5 ,Synchronization selection for PA output 5" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" bitfld.byte 0x09 0.--1. " OUT_SYNC4 ,Synchronization selection for PA output 4" "TRANSPARENT,SINGLESYNC,CLOCK,CLOCKINV" line.byte 0x0A "CFG10,PA Output Data Select Register - Low" bitfld.byte 0x0A 6.--7. " DATA_SEL3 ,Data selection for PA output 3" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" bitfld.byte 0x0A 4.--5. " DATA_SEL2 ,Data selection for PA output 2" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" bitfld.byte 0x0A 2.--3. " DATA_SEL1 ,Data selection for PA output 1" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" bitfld.byte 0x0A 0.--1. " DATA_SEL0 ,Data selection for PA output 0" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" line.byte 0x0B "CFG11,PA Output Data Select Register - High" bitfld.byte 0x0B 6.--7. " DATA_SEL7 ,Data selection for PA output 7" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" bitfld.byte 0x0B 4.--5. " DATA_SEL6 ,Data selection for PA output 6" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" bitfld.byte 0x0B 2.--3. " DATA_SEL5 ,Data selection for PA output 5" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" bitfld.byte 0x0B 0.--1. " DATA_SEL4 ,Data selection for PA output 4" "DSI_OUTPUT0,DSI_OUTPUT1,DSI_OUTPUT2,DSI_OUTPUT3" line.byte 0x0C "CFG12,PA OE Select Register - Low" bitfld.byte 0x0C 6.--7. " OE_SEL3 ,Data selection for PA oe 3" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" bitfld.byte 0x0C 4.--5. " OE_SEL2 ,Data selection for PA oe 2" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" bitfld.byte 0x0C 2.--3. " OE_SEL1 ,Data selection for PA oe 1" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" bitfld.byte 0x0C 0.--1. " OE_SEL0 ,Data selection for PA oe 0" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" line.byte 0x0D "CFG13,PA OE Select Register - High" bitfld.byte 0x0D 6.--7. " OE_SEL7 ,Data selection for PA oe 7" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" bitfld.byte 0x0D 4.--5. " OE_SEL6 ,Data selection for PA oe 6" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" bitfld.byte 0x0D 2.--3. " OE_SEL5 ,Data selection for PA oe 5" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" bitfld.byte 0x0D 0.--1. " OE_SEL4 ,Data selection for PA oe 4" "DSI_OE_OUT0,DSI_OE_OUT1,DSI_OE_OUT2,DSI_OE_OUT3" line.byte 0x0E "CFG14,PA OE Sync Register" bitfld.byte 0x0E 6.--7. " OE_SYNC3 ,Synchronization options for dsi_to_oe[3]" "TRANSPARENT,SINGLESYNC,CONSTANT1,CONSTANT0" bitfld.byte 0x0E 4.--5. " OE_SYNC2 ,Synchronization options for dsi_to_oe[2]" "TRANSPARENT,SINGLESYNC,CONSTANT1,CONSTANT0" bitfld.byte 0x0E 2.--3. " OE_SYNC1 ,Synchronization options for dsi_to_oe[1]" "TRANSPARENT,SINGLESYNC,CONSTANT1,CONSTANT0" bitfld.byte 0x0E 0.--1. " OE_SYNC0 ,Synchronization options for dsi_to_oe[0]" "TRANSPARENT,SINGLESYNC,CONSTANT1,CONSTANT0" width 0x0B tree.end tree.end tree "UDB Routing registers" tree "UDB_P0" base ad:0x400F3100 width 16. group.byte 0x0++0x00 line.byte 0x00 "ROUTE_HC0,UDB Channel HC Tile Configuration; Horizontal Channel 0" group.byte 0x1++0x00 line.byte 0x00 "ROUTE_HC1,UDB Channel HC Tile Configuration; Horizontal Channel 1" group.byte 0x2++0x00 line.byte 0x00 "ROUTE_HC2,UDB Channel HC Tile Configuration; Horizontal Channel 2" group.byte 0x3++0x00 line.byte 0x00 "ROUTE_HC3,UDB Channel HC Tile Configuration; Horizontal Channel 3" group.byte 0x4++0x00 line.byte 0x00 "ROUTE_HC4,UDB Channel HC Tile Configuration; Horizontal Channel 4" group.byte 0x5++0x00 line.byte 0x00 "ROUTE_HC5,UDB Channel HC Tile Configuration; Horizontal Channel 5" group.byte 0x6++0x00 line.byte 0x00 "ROUTE_HC6,UDB Channel HC Tile Configuration; Horizontal Channel 6" group.byte 0x7++0x00 line.byte 0x00 "ROUTE_HC7,UDB Channel HC Tile Configuration; Horizontal Channel 7" group.byte 0x8++0x00 line.byte 0x00 "ROUTE_HC8,UDB Channel HC Tile Configuration; Horizontal Channel 8" group.byte 0x9++0x00 line.byte 0x00 "ROUTE_HC9,UDB Channel HC Tile Configuration; Horizontal Channel 9" group.byte 0xA++0x00 line.byte 0x00 "ROUTE_HC10,UDB Channel HC Tile Configuration; Horizontal Channel 10" group.byte 0xB++0x00 line.byte 0x00 "ROUTE_HC11,UDB Channel HC Tile Configuration; Horizontal Channel 11" group.byte 0xC++0x00 line.byte 0x00 "ROUTE_HC12,UDB Channel HC Tile Configuration; Horizontal Channel 12" group.byte 0xD++0x00 line.byte 0x00 "ROUTE_HC13,UDB Channel HC Tile Configuration; Horizontal Channel 13" group.byte 0xE++0x00 line.byte 0x00 "ROUTE_HC14,UDB Channel HC Tile Configuration; Horizontal Channel 14" group.byte 0xF++0x00 line.byte 0x00 "ROUTE_HC15,UDB Channel HC Tile Configuration; Horizontal Channel 15" group.byte 0x10++0x00 line.byte 0x00 "ROUTE_HC16,UDB Channel HC Tile Configuration; Horizontal Channel 16" group.byte 0x11++0x00 line.byte 0x00 "ROUTE_HC17,UDB Channel HC Tile Configuration; Horizontal Channel 17" group.byte 0x12++0x00 line.byte 0x00 "ROUTE_HC18,UDB Channel HC Tile Configuration; Horizontal Channel 18" group.byte 0x13++0x00 line.byte 0x00 "ROUTE_HC19,UDB Channel HC Tile Configuration; Horizontal Channel 19" group.byte 0x14++0x00 line.byte 0x00 "ROUTE_HC20,UDB Channel HC Tile Configuration; Horizontal Channel 20" group.byte 0x15++0x00 line.byte 0x00 "ROUTE_HC21,UDB Channel HC Tile Configuration; Horizontal Channel 21" group.byte 0x16++0x00 line.byte 0x00 "ROUTE_HC22,UDB Channel HC Tile Configuration; Horizontal Channel 22" group.byte 0x17++0x00 line.byte 0x00 "ROUTE_HC23,UDB Channel HC Tile Configuration; Horizontal Channel 23" group.byte 0x18++0x00 line.byte 0x00 "ROUTE_HC24,UDB Channel HC Tile Configuration; Horizontal Channel 24" group.byte 0x19++0x00 line.byte 0x00 "ROUTE_HC25,UDB Channel HC Tile Configuration; Horizontal Channel 25" group.byte 0x1A++0x00 line.byte 0x00 "ROUTE_HC26,UDB Channel HC Tile Configuration; Horizontal Channel 26" group.byte 0x1B++0x00 line.byte 0x00 "ROUTE_HC27,UDB Channel HC Tile Configuration; Horizontal Channel 27" group.byte 0x1C++0x00 line.byte 0x00 "ROUTE_HC28,UDB Channel HC Tile Configuration; Horizontal Channel 28" group.byte 0x1D++0x00 line.byte 0x00 "ROUTE_HC29,UDB Channel HC Tile Configuration; Horizontal Channel 29" group.byte 0x1E++0x00 line.byte 0x00 "ROUTE_HC30,UDB Channel HC Tile Configuration; Horizontal Channel 30" group.byte 0x1F++0x00 line.byte 0x00 "ROUTE_HC31,UDB Channel HC Tile Configuration; Horizontal Channel 31" group.byte 0x20++0x00 line.byte 0x00 "ROUTE_HC32,UDB Channel HC Tile Configuration; Horizontal Channel 32" group.byte 0x21++0x00 line.byte 0x00 "ROUTE_HC33,UDB Channel HC Tile Configuration; Horizontal Channel 33" group.byte 0x22++0x00 line.byte 0x00 "ROUTE_HC34,UDB Channel HC Tile Configuration; Horizontal Channel 34" group.byte 0x23++0x00 line.byte 0x00 "ROUTE_HC35,UDB Channel HC Tile Configuration; Horizontal Channel 35" group.byte 0x24++0x00 line.byte 0x00 "ROUTE_HC36,UDB Channel HC Tile Configuration; Horizontal Channel 36" group.byte 0x25++0x00 line.byte 0x00 "ROUTE_HC37,UDB Channel HC Tile Configuration; Horizontal Channel 37" group.byte 0x26++0x00 line.byte 0x00 "ROUTE_HC38,UDB Channel HC Tile Configuration; Horizontal Channel 38" group.byte 0x27++0x00 line.byte 0x00 "ROUTE_HC39,UDB Channel HC Tile Configuration; Horizontal Channel 39" group.byte 0x28++0x00 line.byte 0x00 "ROUTE_HC40,UDB Channel HC Tile Configuration; Horizontal Channel 40" group.byte 0x29++0x00 line.byte 0x00 "ROUTE_HC41,UDB Channel HC Tile Configuration; Horizontal Channel 41" group.byte 0x2A++0x00 line.byte 0x00 "ROUTE_HC42,UDB Channel HC Tile Configuration; Horizontal Channel 42" group.byte 0x2B++0x00 line.byte 0x00 "ROUTE_HC43,UDB Channel HC Tile Configuration; Horizontal Channel 43" group.byte 0x2C++0x00 line.byte 0x00 "ROUTE_HC44,UDB Channel HC Tile Configuration; Horizontal Channel 44" group.byte 0x2D++0x00 line.byte 0x00 "ROUTE_HC45,UDB Channel HC Tile Configuration; Horizontal Channel 45" group.byte 0x2E++0x00 line.byte 0x00 "ROUTE_HC46,UDB Channel HC Tile Configuration; Horizontal Channel 46" group.byte 0x2F++0x00 line.byte 0x00 "ROUTE_HC47,UDB Channel HC Tile Configuration; Horizontal Channel 47" group.byte 0x30++0x00 line.byte 0x00 "ROUTE_HC48,UDB Channel HC Tile Configuration; Horizontal Channel 48" group.byte 0x31++0x00 line.byte 0x00 "ROUTE_HC49,UDB Channel HC Tile Configuration; Horizontal Channel 49" group.byte 0x32++0x00 line.byte 0x00 "ROUTE_HC50,UDB Channel HC Tile Configuration; Horizontal Channel 50" group.byte 0x33++0x00 line.byte 0x00 "ROUTE_HC51,UDB Channel HC Tile Configuration; Horizontal Channel 51" group.byte 0x34++0x00 line.byte 0x00 "ROUTE_HC52,UDB Channel HC Tile Configuration; Horizontal Channel 52" group.byte 0x35++0x00 line.byte 0x00 "ROUTE_HC53,UDB Channel HC Tile Configuration; Horizontal Channel 53" group.byte 0x36++0x00 line.byte 0x00 "ROUTE_HC54,UDB Channel HC Tile Configuration; Horizontal Channel 54" group.byte 0x37++0x00 line.byte 0x00 "ROUTE_HC55,UDB Channel HC Tile Configuration; Horizontal Channel 55" group.byte 0x38++0x00 line.byte 0x00 "ROUTE_HC56,UDB Channel HC Tile Configuration; Horizontal Channel 56" group.byte 0x39++0x00 line.byte 0x00 "ROUTE_HC57,UDB Channel HC Tile Configuration; Horizontal Channel 57" group.byte 0x3A++0x00 line.byte 0x00 "ROUTE_HC58,UDB Channel HC Tile Configuration; Horizontal Channel 58" group.byte 0x3B++0x00 line.byte 0x00 "ROUTE_HC59,UDB Channel HC Tile Configuration; Horizontal Channel 59" group.byte 0x3C++0x00 line.byte 0x00 "ROUTE_HC60,UDB Channel HC Tile Configuration; Horizontal Channel 60" group.byte 0x3D++0x00 line.byte 0x00 "ROUTE_HC61,UDB Channel HC Tile Configuration; Horizontal Channel 61" group.byte 0x3E++0x00 line.byte 0x00 "ROUTE_HC62,UDB Channel HC Tile Configuration; Horizontal Channel 62" group.byte 0x3F++0x00 line.byte 0x00 "ROUTE_HC63,UDB Channel HC Tile Configuration; Horizontal Channel 63" group.byte 0x40++0x00 line.byte 0x00 "ROUTE_HC64,UDB Channel HC Tile Configuration; Horizontal Channel 64" group.byte 0x41++0x00 line.byte 0x00 "ROUTE_HC65,UDB Channel HC Tile Configuration; Horizontal Channel 65" group.byte 0x42++0x00 line.byte 0x00 "ROUTE_HC66,UDB Channel HC Tile Configuration; Horizontal Channel 66" group.byte 0x43++0x00 line.byte 0x00 "ROUTE_HC67,UDB Channel HC Tile Configuration; Horizontal Channel 67" group.byte 0x44++0x00 line.byte 0x00 "ROUTE_HC68,UDB Channel HC Tile Configuration; Horizontal Channel 68" group.byte 0x45++0x00 line.byte 0x00 "ROUTE_HC69,UDB Channel HC Tile Configuration; Horizontal Channel 69" group.byte 0x46++0x00 line.byte 0x00 "ROUTE_HC70,UDB Channel HC Tile Configuration; Horizontal Channel 70" group.byte 0x47++0x00 line.byte 0x00 "ROUTE_HC71,UDB Channel HC Tile Configuration; Horizontal Channel 71" group.byte 0x48++0x00 line.byte 0x00 "ROUTE_HC72,UDB Channel HC Tile Configuration; Horizontal Channel 72" group.byte 0x49++0x00 line.byte 0x00 "ROUTE_HC73,UDB Channel HC Tile Configuration; Horizontal Channel 73" group.byte 0x4A++0x00 line.byte 0x00 "ROUTE_HC74,UDB Channel HC Tile Configuration; Horizontal Channel 74" group.byte 0x4B++0x00 line.byte 0x00 "ROUTE_HC75,UDB Channel HC Tile Configuration; Horizontal Channel 75" group.byte 0x4C++0x00 line.byte 0x00 "ROUTE_HC76,UDB Channel HC Tile Configuration; Horizontal Channel 76" group.byte 0x4D++0x00 line.byte 0x00 "ROUTE_HC77,UDB Channel HC Tile Configuration; Horizontal Channel 77" group.byte 0x4E++0x00 line.byte 0x00 "ROUTE_HC78,UDB Channel HC Tile Configuration; Horizontal Channel 78" group.byte 0x4F++0x00 line.byte 0x00 "ROUTE_HC79,UDB Channel HC Tile Configuration; Horizontal Channel 79" group.byte 0x50++0x00 line.byte 0x00 "ROUTE_HC80,UDB Channel HC Tile Configuration; Horizontal Channel 80" group.byte 0x51++0x00 line.byte 0x00 "ROUTE_HC81,UDB Channel HC Tile Configuration; Horizontal Channel 81" group.byte 0x52++0x00 line.byte 0x00 "ROUTE_HC82,UDB Channel HC Tile Configuration; Horizontal Channel 82" group.byte 0x53++0x00 line.byte 0x00 "ROUTE_HC83,UDB Channel HC Tile Configuration; Horizontal Channel 83" group.byte 0x54++0x00 line.byte 0x00 "ROUTE_HC84,UDB Channel HC Tile Configuration; Horizontal Channel 84" group.byte 0x55++0x00 line.byte 0x00 "ROUTE_HC85,UDB Channel HC Tile Configuration; Horizontal Channel 85" group.byte 0x56++0x00 line.byte 0x00 "ROUTE_HC86,UDB Channel HC Tile Configuration; Horizontal Channel 86" group.byte 0x57++0x00 line.byte 0x00 "ROUTE_HC87,UDB Channel HC Tile Configuration; Horizontal Channel 87" group.byte 0x58++0x00 line.byte 0x00 "ROUTE_HC88,UDB Channel HC Tile Configuration; Horizontal Channel 88" group.byte 0x59++0x00 line.byte 0x00 "ROUTE_HC89,UDB Channel HC Tile Configuration; Horizontal Channel 89" group.byte 0x5A++0x00 line.byte 0x00 "ROUTE_HC90,UDB Channel HC Tile Configuration; Horizontal Channel 90" group.byte 0x5B++0x00 line.byte 0x00 "ROUTE_HC91,UDB Channel HC Tile Configuration; Horizontal Channel 91" group.byte 0x5C++0x00 line.byte 0x00 "ROUTE_HC92,UDB Channel HC Tile Configuration; Horizontal Channel 92" group.byte 0x5D++0x00 line.byte 0x00 "ROUTE_HC93,UDB Channel HC Tile Configuration; Horizontal Channel 93" group.byte 0x5E++0x00 line.byte 0x00 "ROUTE_HC94,UDB Channel HC Tile Configuration; Horizontal Channel 94" group.byte 0x5F++0x00 line.byte 0x00 "ROUTE_HC95,UDB Channel HC Tile Configuration; Horizontal Channel 95" group.byte 0x60++0x00 line.byte 0x00 "ROUTE_HC96,UDB Channel HC Tile Configuration; Horizontal Channel 96" group.byte 0x61++0x00 line.byte 0x00 "ROUTE_HC97,UDB Channel HC Tile Configuration; Horizontal Channel 97" group.byte 0x62++0x00 line.byte 0x00 "ROUTE_HC98,UDB Channel HC Tile Configuration; Horizontal Channel 98" group.byte 0x63++0x00 line.byte 0x00 "ROUTE_HC99,UDB Channel HC Tile Configuration; Horizontal Channel 99" group.byte 0x64++0x00 line.byte 0x00 "ROUTE_HC100,UDB Channel HC Tile Configuration; Horizontal Channel 100" group.byte 0x65++0x00 line.byte 0x00 "ROUTE_HC101,UDB Channel HC Tile Configuration; Horizontal Channel 101" group.byte 0x66++0x00 line.byte 0x00 "ROUTE_HC102,UDB Channel HC Tile Configuration; Horizontal Channel 102" group.byte 0x67++0x00 line.byte 0x00 "ROUTE_HC103,UDB Channel HC Tile Configuration; Horizontal Channel 103" group.byte 0x68++0x00 line.byte 0x00 "ROUTE_HC104,UDB Channel HC Tile Configuration; Horizontal Channel 104" group.byte 0x69++0x00 line.byte 0x00 "ROUTE_HC105,UDB Channel HC Tile Configuration; Horizontal Channel 105" group.byte 0x6A++0x00 line.byte 0x00 "ROUTE_HC106,UDB Channel HC Tile Configuration; Horizontal Channel 106" group.byte 0x6B++0x00 line.byte 0x00 "ROUTE_HC107,UDB Channel HC Tile Configuration; Horizontal Channel 107" group.byte 0x6C++0x00 line.byte 0x00 "ROUTE_HC108,UDB Channel HC Tile Configuration; Horizontal Channel 108" group.byte 0x6D++0x00 line.byte 0x00 "ROUTE_HC109,UDB Channel HC Tile Configuration; Horizontal Channel 109" group.byte 0x6E++0x00 line.byte 0x00 "ROUTE_HC110,UDB Channel HC Tile Configuration; Horizontal Channel 110" group.byte 0x6F++0x00 line.byte 0x00 "ROUTE_HC111,UDB Channel HC Tile Configuration; Horizontal Channel 111" group.byte 0x70++0x00 line.byte 0x00 "ROUTE_HC112,UDB Channel HC Tile Configuration; Horizontal Channel 112" group.byte 0x71++0x00 line.byte 0x00 "ROUTE_HC113,UDB Channel HC Tile Configuration; Horizontal Channel 113" group.byte 0x72++0x00 line.byte 0x00 "ROUTE_HC114,UDB Channel HC Tile Configuration; Horizontal Channel 114" group.byte 0x73++0x00 line.byte 0x00 "ROUTE_HC115,UDB Channel HC Tile Configuration; Horizontal Channel 115" group.byte 0x74++0x00 line.byte 0x00 "ROUTE_HC116,UDB Channel HC Tile Configuration; Horizontal Channel 116" group.byte 0x75++0x00 line.byte 0x00 "ROUTE_HC117,UDB Channel HC Tile Configuration; Horizontal Channel 117" group.byte 0x76++0x00 line.byte 0x00 "ROUTE_HC118,UDB Channel HC Tile Configuration; Horizontal Channel 118" group.byte 0x77++0x00 line.byte 0x00 "ROUTE_HC119,UDB Channel HC Tile Configuration; Horizontal Channel 119" group.byte 0x78++0x00 line.byte 0x00 "ROUTE_HC120,UDB Channel HC Tile Configuration; Horizontal Channel 120" group.byte 0x79++0x00 line.byte 0x00 "ROUTE_HC121,UDB Channel HC Tile Configuration; Horizontal Channel 121" group.byte 0x7A++0x00 line.byte 0x00 "ROUTE_HC122,UDB Channel HC Tile Configuration; Horizontal Channel 122" group.byte 0x7B++0x00 line.byte 0x00 "ROUTE_HC123,UDB Channel HC Tile Configuration; Horizontal Channel 123" group.byte 0x7C++0x00 line.byte 0x00 "ROUTE_HC124,UDB Channel HC Tile Configuration; Horizontal Channel 124" group.byte 0x7D++0x00 line.byte 0x00 "ROUTE_HC125,UDB Channel HC Tile Configuration; Horizontal Channel 125" group.byte 0x7E++0x00 line.byte 0x00 "ROUTE_HC126,UDB Channel HC Tile Configuration; Horizontal Channel 126" group.byte 0x7F++0x00 line.byte 0x00 "ROUTE_HC127,UDB Channel HC Tile Configuration; Horizontal Channel 127" group.byte 0x80++0x00 line.byte 0x00 "ROUTE_HV_L0,UDB Channel HV Tile Configuration; Left 0" group.byte 0x81++0x00 line.byte 0x00 "ROUTE_HV_L1,UDB Channel HV Tile Configuration; Left 1" group.byte 0x82++0x00 line.byte 0x00 "ROUTE_HV_L2,UDB Channel HV Tile Configuration; Left 2" group.byte 0x83++0x00 line.byte 0x00 "ROUTE_HV_L3,UDB Channel HV Tile Configuration; Left 3" group.byte 0x84++0x00 line.byte 0x00 "ROUTE_HV_L4,UDB Channel HV Tile Configuration; Left 4" group.byte 0x85++0x00 line.byte 0x00 "ROUTE_HV_L5,UDB Channel HV Tile Configuration; Left 5" group.byte 0x86++0x00 line.byte 0x00 "ROUTE_HV_L6,UDB Channel HV Tile Configuration; Left 6" group.byte 0x87++0x00 line.byte 0x00 "ROUTE_HV_L7,UDB Channel HV Tile Configuration; Left 7" group.byte 0x88++0x00 line.byte 0x00 "ROUTE_HV_L8,UDB Channel HV Tile Configuration; Left 8" group.byte 0x89++0x00 line.byte 0x00 "ROUTE_HV_L9,UDB Channel HV Tile Configuration; Left 9" group.byte 0x8A++0x00 line.byte 0x00 "ROUTE_HV_L10,UDB Channel HV Tile Configuration; Left 10" group.byte 0x8B++0x00 line.byte 0x00 "ROUTE_HV_L11,UDB Channel HV Tile Configuration; Left 11" group.byte 0x8C++0x00 line.byte 0x00 "ROUTE_HV_L12,UDB Channel HV Tile Configuration; Left 12" group.byte 0x8D++0x00 line.byte 0x00 "ROUTE_HV_L13,UDB Channel HV Tile Configuration; Left 13" group.byte 0x8E++0x00 line.byte 0x00 "ROUTE_HV_L14,UDB Channel HV Tile Configuration; Left 14" group.byte 0x8F++0x00 line.byte 0x00 "ROUTE_HV_L15,UDB Channel HV Tile Configuration; Left 15" group.byte 0x90++0x00 line.byte 0x00 "ROUTE_HS0,UDB Channel HS Tile Configuration; Horizontal Segmentation 0" group.byte 0x91++0x00 line.byte 0x00 "ROUTE_HS1,UDB Channel HS Tile Configuration; Horizontal Segmentation 1" group.byte 0x92++0x00 line.byte 0x00 "ROUTE_HS2,UDB Channel HS Tile Configuration; Horizontal Segmentation 2" group.byte 0x93++0x00 line.byte 0x00 "ROUTE_HS3,UDB Channel HS Tile Configuration; Horizontal Segmentation 3" group.byte 0x94++0x00 line.byte 0x00 "ROUTE_HS4,UDB Channel HS Tile Configuration; Horizontal Segmentation 4" group.byte 0x95++0x00 line.byte 0x00 "ROUTE_HS5,UDB Channel HS Tile Configuration; Horizontal Segmentation 5" group.byte 0x96++0x00 line.byte 0x00 "ROUTE_HS6,UDB Channel HS Tile Configuration; Horizontal Segmentation 6" group.byte 0x97++0x00 line.byte 0x00 "ROUTE_HS7,UDB Channel HS Tile Configuration; Horizontal Segmentation 7" group.byte 0x98++0x00 line.byte 0x00 "ROUTE_HS8,UDB Channel HS Tile Configuration; Horizontal Segmentation 8" group.byte 0x99++0x00 line.byte 0x00 "ROUTE_HS9,UDB Channel HS Tile Configuration; Horizontal Segmentation 9" group.byte 0x9A++0x00 line.byte 0x00 "ROUTE_HS10,UDB Channel HS Tile Configuration; Horizontal Segmentation 10" group.byte 0x9B++0x00 line.byte 0x00 "ROUTE_HS11,UDB Channel HS Tile Configuration; Horizontal Segmentation 11" group.byte 0x9C++0x00 line.byte 0x00 "ROUTE_HS12,UDB Channel HS Tile Configuration; Horizontal Segmentation 12" group.byte 0x9D++0x00 line.byte 0x00 "ROUTE_HS13,UDB Channel HS Tile Configuration; Horizontal Segmentation 13" group.byte 0x9E++0x00 line.byte 0x00 "ROUTE_HS14,UDB Channel HS Tile Configuration; Horizontal Segmentation 14" group.byte 0x9F++0x00 line.byte 0x00 "ROUTE_HS15,UDB Channel HS Tile Configuration; Horizontal Segmentation 15" group.byte 0xA0++0x00 line.byte 0x00 "ROUTE_HS16,UDB Channel HS Tile Configuration; Horizontal Segmentation 16" group.byte 0xA1++0x00 line.byte 0x00 "ROUTE_HS17,UDB Channel HS Tile Configuration; Horizontal Segmentation 17" group.byte 0xA2++0x00 line.byte 0x00 "ROUTE_HS18,UDB Channel HS Tile Configuration; Horizontal Segmentation 18" group.byte 0xA3++0x00 line.byte 0x00 "ROUTE_HS19,UDB Channel HS Tile Configuration; Horizontal Segmentation 19" group.byte 0xA4++0x00 line.byte 0x00 "ROUTE_HS20,UDB Channel HS Tile Configuration; Horizontal Segmentation 20" group.byte 0xA5++0x00 line.byte 0x00 "ROUTE_HS21,UDB Channel HS Tile Configuration; Horizontal Segmentation 21" group.byte 0xA6++0x00 line.byte 0x00 "ROUTE_HS22,UDB Channel HS Tile Configuration; Horizontal Segmentation 22" group.byte 0xA7++0x00 line.byte 0x00 "ROUTE_HS23,UDB Channel HS Tile Configuration; Horizontal Segmentation 23" group.byte 0xA8++0x00 line.byte 0x00 "ROUTE_HV_R0,UDB Channel HV Tile Configuration; Right 0" group.byte 0xA9++0x00 line.byte 0x00 "ROUTE_HV_R1,UDB Channel HV Tile Configuration; Right 1" group.byte 0xAA++0x00 line.byte 0x00 "ROUTE_HV_R2,UDB Channel HV Tile Configuration; Right 2" group.byte 0xAB++0x00 line.byte 0x00 "ROUTE_HV_R3,UDB Channel HV Tile Configuration; Right 3" group.byte 0xAC++0x00 line.byte 0x00 "ROUTE_HV_R4,UDB Channel HV Tile Configuration; Right 4" group.byte 0xAD++0x00 line.byte 0x00 "ROUTE_HV_R5,UDB Channel HV Tile Configuration; Right 5" group.byte 0xAE++0x00 line.byte 0x00 "ROUTE_HV_R6,UDB Channel HV Tile Configuration; Right 6" group.byte 0xAF++0x00 line.byte 0x00 "ROUTE_HV_R7,UDB Channel HV Tile Configuration; Right 7" group.byte 0xB0++0x00 line.byte 0x00 "ROUTE_HV_R8,UDB Channel HV Tile Configuration; Right 8" group.byte 0xB1++0x00 line.byte 0x00 "ROUTE_HV_R9,UDB Channel HV Tile Configuration; Right 9" group.byte 0xB2++0x00 line.byte 0x00 "ROUTE_HV_R10,UDB Channel HV Tile Configuration; Right 10" group.byte 0xB3++0x00 line.byte 0x00 "ROUTE_HV_R11,UDB Channel HV Tile Configuration; Right 11" group.byte 0xB4++0x00 line.byte 0x00 "ROUTE_HV_R12,UDB Channel HV Tile Configuration; Right 12" group.byte 0xB5++0x00 line.byte 0x00 "ROUTE_HV_R13,UDB Channel HV Tile Configuration; Right 13" group.byte 0xB6++0x00 line.byte 0x00 "ROUTE_HV_R14,UDB Channel HV Tile Configuration; Right 14" group.byte 0xB7++0x00 line.byte 0x00 "ROUTE_HV_R15,UDB Channel HV Tile Configuration; Right 15" group.word 0xC0++0x01 line.word 0x00 "ROUTE_PLD0IN0,UDB Channel PI Tile Configuration; PLD Input 0" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xC2++0x01 line.word 0x00 "ROUTE_PLD0IN1,UDB Channel PI Tile Configuration; PLD Input 1" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xC4++0x01 line.word 0x00 "ROUTE_PLD0IN2,UDB Channel PI Tile Configuration; PLD Input 2" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xCA++0x01 line.word 0x00 "ROUTE_PLD1IN0,UDB Channel PI Tile Configuration; PLD Input 0" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xCC++0x01 line.word 0x00 "ROUTE_PLD1IN1,UDB Channel PI Tile Configuration; PLD Input 1" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xCE++0x01 line.word 0x00 "ROUTE_PLD1IN2,UDB Channel PI Tile Configuration; PLD Input 2" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xD0++0x00 line.byte 0x00 "ROUTE_DPIN0,UDB Channel PI Tile Configuration; Datapath Input 0" bitfld.byte 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xD2++0x00 line.byte 0x00 "ROUTE_DPIN1,UDB Channel PI Tile Configuration; Datapath Input 1" bitfld.byte 0x00 4.--5. " PI_BOT2 ,RAM configuration bits (2) for BOTTOM UDB port interface configuration" "0,1,2,3" bitfld.byte 0x00 2.--3. " PI_TOP2 ,RAM configuration bits (2) for TOP UDB port interface configuration" "0,1,2,3" group.byte 0xD6++0x00 line.byte 0x00 "ROUTE_SCIN,UDB Channel PI Tile Configuration; Status / Control Blocks Input Control" bitfld.byte 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xD8++0x00 line.byte 0x00 "ROUTE_SCIOIN,UDB Channel PI Tile Configuration; Status / Control Blocks Input / Output Control" bitfld.byte 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xDE++0x00 line.byte 0x00 "ROUTE_RCIN,UDB Channel PI Tile Configuration; Reset And Clock Blocks Input Control" bitfld.byte 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE0++0x01 line.word 0x00 "ROUTE_VS0,UDB Channel VS Tile Configuration; Vertical Segmentation 0" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration nibble for BOTTOM UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration nibble for TOP UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE2++0x01 line.word 0x00 "ROUTE_VS1,UDB Channel VS Tile Configuration; Vertical Segmentation 1" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration nibble for BOTTOM UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration nibble for TOP UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE4++0x01 line.word 0x00 "ROUTE_VS2,UDB Channel VS Tile Configuration; Vertical Segmentation 2" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration nibble for BOTTOM UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration nibble for TOP UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE6++0x01 line.word 0x00 "ROUTE_VS3,UDB Channel VS Tile Configuration; Vertical Segmentation 3" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration nibble for BOTTOM UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration nibble for TOP UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE8++0x01 line.word 0x00 "ROUTE_VS4,UDB Channel VS Tile Configuration; Vertical Segmentation 4" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration nibble for BOTTOM UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration nibble for TOP UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xEA++0x01 line.word 0x00 "ROUTE_VS5,UDB Channel VS Tile Configuration; Vertical Segmentation 5" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration nibble for BOTTOM UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration nibble for TOP UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xEC++0x01 line.word 0x00 "ROUTE_VS6,UDB Channel VS Tile Configuration; Vertical Segmentation 6" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration nibble for BOTTOM UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration nibble for TOP UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xEE++0x01 line.word 0x00 "ROUTE_VS7,UDB Channel VS Tile Configuration; Vertical Segmentation 7" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration nibble for BOTTOM UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration nibble for TOP UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree "UDB_P1" base ad:0x400F3300 width 16. group.byte 0x0++0x00 line.byte 0x00 "ROUTE_HC0,UDB Channel HC Tile Configuration; Horizontal Channel 0" group.byte 0x1++0x00 line.byte 0x00 "ROUTE_HC1,UDB Channel HC Tile Configuration; Horizontal Channel 1" group.byte 0x2++0x00 line.byte 0x00 "ROUTE_HC2,UDB Channel HC Tile Configuration; Horizontal Channel 2" group.byte 0x3++0x00 line.byte 0x00 "ROUTE_HC3,UDB Channel HC Tile Configuration; Horizontal Channel 3" group.byte 0x4++0x00 line.byte 0x00 "ROUTE_HC4,UDB Channel HC Tile Configuration; Horizontal Channel 4" group.byte 0x5++0x00 line.byte 0x00 "ROUTE_HC5,UDB Channel HC Tile Configuration; Horizontal Channel 5" group.byte 0x6++0x00 line.byte 0x00 "ROUTE_HC6,UDB Channel HC Tile Configuration; Horizontal Channel 6" group.byte 0x7++0x00 line.byte 0x00 "ROUTE_HC7,UDB Channel HC Tile Configuration; Horizontal Channel 7" group.byte 0x8++0x00 line.byte 0x00 "ROUTE_HC8,UDB Channel HC Tile Configuration; Horizontal Channel 8" group.byte 0x9++0x00 line.byte 0x00 "ROUTE_HC9,UDB Channel HC Tile Configuration; Horizontal Channel 9" group.byte 0xA++0x00 line.byte 0x00 "ROUTE_HC10,UDB Channel HC Tile Configuration; Horizontal Channel 10" group.byte 0xB++0x00 line.byte 0x00 "ROUTE_HC11,UDB Channel HC Tile Configuration; Horizontal Channel 11" group.byte 0xC++0x00 line.byte 0x00 "ROUTE_HC12,UDB Channel HC Tile Configuration; Horizontal Channel 12" group.byte 0xD++0x00 line.byte 0x00 "ROUTE_HC13,UDB Channel HC Tile Configuration; Horizontal Channel 13" group.byte 0xE++0x00 line.byte 0x00 "ROUTE_HC14,UDB Channel HC Tile Configuration; Horizontal Channel 14" group.byte 0xF++0x00 line.byte 0x00 "ROUTE_HC15,UDB Channel HC Tile Configuration; Horizontal Channel 15" group.byte 0x10++0x00 line.byte 0x00 "ROUTE_HC16,UDB Channel HC Tile Configuration; Horizontal Channel 16" group.byte 0x11++0x00 line.byte 0x00 "ROUTE_HC17,UDB Channel HC Tile Configuration; Horizontal Channel 17" group.byte 0x12++0x00 line.byte 0x00 "ROUTE_HC18,UDB Channel HC Tile Configuration; Horizontal Channel 18" group.byte 0x13++0x00 line.byte 0x00 "ROUTE_HC19,UDB Channel HC Tile Configuration; Horizontal Channel 19" group.byte 0x14++0x00 line.byte 0x00 "ROUTE_HC20,UDB Channel HC Tile Configuration; Horizontal Channel 20" group.byte 0x15++0x00 line.byte 0x00 "ROUTE_HC21,UDB Channel HC Tile Configuration; Horizontal Channel 21" group.byte 0x16++0x00 line.byte 0x00 "ROUTE_HC22,UDB Channel HC Tile Configuration; Horizontal Channel 22" group.byte 0x17++0x00 line.byte 0x00 "ROUTE_HC23,UDB Channel HC Tile Configuration; Horizontal Channel 23" group.byte 0x18++0x00 line.byte 0x00 "ROUTE_HC24,UDB Channel HC Tile Configuration; Horizontal Channel 24" group.byte 0x19++0x00 line.byte 0x00 "ROUTE_HC25,UDB Channel HC Tile Configuration; Horizontal Channel 25" group.byte 0x1A++0x00 line.byte 0x00 "ROUTE_HC26,UDB Channel HC Tile Configuration; Horizontal Channel 26" group.byte 0x1B++0x00 line.byte 0x00 "ROUTE_HC27,UDB Channel HC Tile Configuration; Horizontal Channel 27" group.byte 0x1C++0x00 line.byte 0x00 "ROUTE_HC28,UDB Channel HC Tile Configuration; Horizontal Channel 28" group.byte 0x1D++0x00 line.byte 0x00 "ROUTE_HC29,UDB Channel HC Tile Configuration; Horizontal Channel 29" group.byte 0x1E++0x00 line.byte 0x00 "ROUTE_HC30,UDB Channel HC Tile Configuration; Horizontal Channel 30" group.byte 0x1F++0x00 line.byte 0x00 "ROUTE_HC31,UDB Channel HC Tile Configuration; Horizontal Channel 31" group.byte 0x20++0x00 line.byte 0x00 "ROUTE_HC32,UDB Channel HC Tile Configuration; Horizontal Channel 32" group.byte 0x21++0x00 line.byte 0x00 "ROUTE_HC33,UDB Channel HC Tile Configuration; Horizontal Channel 33" group.byte 0x22++0x00 line.byte 0x00 "ROUTE_HC34,UDB Channel HC Tile Configuration; Horizontal Channel 34" group.byte 0x23++0x00 line.byte 0x00 "ROUTE_HC35,UDB Channel HC Tile Configuration; Horizontal Channel 35" group.byte 0x24++0x00 line.byte 0x00 "ROUTE_HC36,UDB Channel HC Tile Configuration; Horizontal Channel 36" group.byte 0x25++0x00 line.byte 0x00 "ROUTE_HC37,UDB Channel HC Tile Configuration; Horizontal Channel 37" group.byte 0x26++0x00 line.byte 0x00 "ROUTE_HC38,UDB Channel HC Tile Configuration; Horizontal Channel 38" group.byte 0x27++0x00 line.byte 0x00 "ROUTE_HC39,UDB Channel HC Tile Configuration; Horizontal Channel 39" group.byte 0x28++0x00 line.byte 0x00 "ROUTE_HC40,UDB Channel HC Tile Configuration; Horizontal Channel 40" group.byte 0x29++0x00 line.byte 0x00 "ROUTE_HC41,UDB Channel HC Tile Configuration; Horizontal Channel 41" group.byte 0x2A++0x00 line.byte 0x00 "ROUTE_HC42,UDB Channel HC Tile Configuration; Horizontal Channel 42" group.byte 0x2B++0x00 line.byte 0x00 "ROUTE_HC43,UDB Channel HC Tile Configuration; Horizontal Channel 43" group.byte 0x2C++0x00 line.byte 0x00 "ROUTE_HC44,UDB Channel HC Tile Configuration; Horizontal Channel 44" group.byte 0x2D++0x00 line.byte 0x00 "ROUTE_HC45,UDB Channel HC Tile Configuration; Horizontal Channel 45" group.byte 0x2E++0x00 line.byte 0x00 "ROUTE_HC46,UDB Channel HC Tile Configuration; Horizontal Channel 46" group.byte 0x2F++0x00 line.byte 0x00 "ROUTE_HC47,UDB Channel HC Tile Configuration; Horizontal Channel 47" group.byte 0x30++0x00 line.byte 0x00 "ROUTE_HC48,UDB Channel HC Tile Configuration; Horizontal Channel 48" group.byte 0x31++0x00 line.byte 0x00 "ROUTE_HC49,UDB Channel HC Tile Configuration; Horizontal Channel 49" group.byte 0x32++0x00 line.byte 0x00 "ROUTE_HC50,UDB Channel HC Tile Configuration; Horizontal Channel 50" group.byte 0x33++0x00 line.byte 0x00 "ROUTE_HC51,UDB Channel HC Tile Configuration; Horizontal Channel 51" group.byte 0x34++0x00 line.byte 0x00 "ROUTE_HC52,UDB Channel HC Tile Configuration; Horizontal Channel 52" group.byte 0x35++0x00 line.byte 0x00 "ROUTE_HC53,UDB Channel HC Tile Configuration; Horizontal Channel 53" group.byte 0x36++0x00 line.byte 0x00 "ROUTE_HC54,UDB Channel HC Tile Configuration; Horizontal Channel 54" group.byte 0x37++0x00 line.byte 0x00 "ROUTE_HC55,UDB Channel HC Tile Configuration; Horizontal Channel 55" group.byte 0x38++0x00 line.byte 0x00 "ROUTE_HC56,UDB Channel HC Tile Configuration; Horizontal Channel 56" group.byte 0x39++0x00 line.byte 0x00 "ROUTE_HC57,UDB Channel HC Tile Configuration; Horizontal Channel 57" group.byte 0x3A++0x00 line.byte 0x00 "ROUTE_HC58,UDB Channel HC Tile Configuration; Horizontal Channel 58" group.byte 0x3B++0x00 line.byte 0x00 "ROUTE_HC59,UDB Channel HC Tile Configuration; Horizontal Channel 59" group.byte 0x3C++0x00 line.byte 0x00 "ROUTE_HC60,UDB Channel HC Tile Configuration; Horizontal Channel 60" group.byte 0x3D++0x00 line.byte 0x00 "ROUTE_HC61,UDB Channel HC Tile Configuration; Horizontal Channel 61" group.byte 0x3E++0x00 line.byte 0x00 "ROUTE_HC62,UDB Channel HC Tile Configuration; Horizontal Channel 62" group.byte 0x3F++0x00 line.byte 0x00 "ROUTE_HC63,UDB Channel HC Tile Configuration; Horizontal Channel 63" group.byte 0x40++0x00 line.byte 0x00 "ROUTE_HC64,UDB Channel HC Tile Configuration; Horizontal Channel 64" group.byte 0x41++0x00 line.byte 0x00 "ROUTE_HC65,UDB Channel HC Tile Configuration; Horizontal Channel 65" group.byte 0x42++0x00 line.byte 0x00 "ROUTE_HC66,UDB Channel HC Tile Configuration; Horizontal Channel 66" group.byte 0x43++0x00 line.byte 0x00 "ROUTE_HC67,UDB Channel HC Tile Configuration; Horizontal Channel 67" group.byte 0x44++0x00 line.byte 0x00 "ROUTE_HC68,UDB Channel HC Tile Configuration; Horizontal Channel 68" group.byte 0x45++0x00 line.byte 0x00 "ROUTE_HC69,UDB Channel HC Tile Configuration; Horizontal Channel 69" group.byte 0x46++0x00 line.byte 0x00 "ROUTE_HC70,UDB Channel HC Tile Configuration; Horizontal Channel 70" group.byte 0x47++0x00 line.byte 0x00 "ROUTE_HC71,UDB Channel HC Tile Configuration; Horizontal Channel 71" group.byte 0x48++0x00 line.byte 0x00 "ROUTE_HC72,UDB Channel HC Tile Configuration; Horizontal Channel 72" group.byte 0x49++0x00 line.byte 0x00 "ROUTE_HC73,UDB Channel HC Tile Configuration; Horizontal Channel 73" group.byte 0x4A++0x00 line.byte 0x00 "ROUTE_HC74,UDB Channel HC Tile Configuration; Horizontal Channel 74" group.byte 0x4B++0x00 line.byte 0x00 "ROUTE_HC75,UDB Channel HC Tile Configuration; Horizontal Channel 75" group.byte 0x4C++0x00 line.byte 0x00 "ROUTE_HC76,UDB Channel HC Tile Configuration; Horizontal Channel 76" group.byte 0x4D++0x00 line.byte 0x00 "ROUTE_HC77,UDB Channel HC Tile Configuration; Horizontal Channel 77" group.byte 0x4E++0x00 line.byte 0x00 "ROUTE_HC78,UDB Channel HC Tile Configuration; Horizontal Channel 78" group.byte 0x4F++0x00 line.byte 0x00 "ROUTE_HC79,UDB Channel HC Tile Configuration; Horizontal Channel 79" group.byte 0x50++0x00 line.byte 0x00 "ROUTE_HC80,UDB Channel HC Tile Configuration; Horizontal Channel 80" group.byte 0x51++0x00 line.byte 0x00 "ROUTE_HC81,UDB Channel HC Tile Configuration; Horizontal Channel 81" group.byte 0x52++0x00 line.byte 0x00 "ROUTE_HC82,UDB Channel HC Tile Configuration; Horizontal Channel 82" group.byte 0x53++0x00 line.byte 0x00 "ROUTE_HC83,UDB Channel HC Tile Configuration; Horizontal Channel 83" group.byte 0x54++0x00 line.byte 0x00 "ROUTE_HC84,UDB Channel HC Tile Configuration; Horizontal Channel 84" group.byte 0x55++0x00 line.byte 0x00 "ROUTE_HC85,UDB Channel HC Tile Configuration; Horizontal Channel 85" group.byte 0x56++0x00 line.byte 0x00 "ROUTE_HC86,UDB Channel HC Tile Configuration; Horizontal Channel 86" group.byte 0x57++0x00 line.byte 0x00 "ROUTE_HC87,UDB Channel HC Tile Configuration; Horizontal Channel 87" group.byte 0x58++0x00 line.byte 0x00 "ROUTE_HC88,UDB Channel HC Tile Configuration; Horizontal Channel 88" group.byte 0x59++0x00 line.byte 0x00 "ROUTE_HC89,UDB Channel HC Tile Configuration; Horizontal Channel 89" group.byte 0x5A++0x00 line.byte 0x00 "ROUTE_HC90,UDB Channel HC Tile Configuration; Horizontal Channel 90" group.byte 0x5B++0x00 line.byte 0x00 "ROUTE_HC91,UDB Channel HC Tile Configuration; Horizontal Channel 91" group.byte 0x5C++0x00 line.byte 0x00 "ROUTE_HC92,UDB Channel HC Tile Configuration; Horizontal Channel 92" group.byte 0x5D++0x00 line.byte 0x00 "ROUTE_HC93,UDB Channel HC Tile Configuration; Horizontal Channel 93" group.byte 0x5E++0x00 line.byte 0x00 "ROUTE_HC94,UDB Channel HC Tile Configuration; Horizontal Channel 94" group.byte 0x5F++0x00 line.byte 0x00 "ROUTE_HC95,UDB Channel HC Tile Configuration; Horizontal Channel 95" group.byte 0x60++0x00 line.byte 0x00 "ROUTE_HC96,UDB Channel HC Tile Configuration; Horizontal Channel 96" group.byte 0x61++0x00 line.byte 0x00 "ROUTE_HC97,UDB Channel HC Tile Configuration; Horizontal Channel 97" group.byte 0x62++0x00 line.byte 0x00 "ROUTE_HC98,UDB Channel HC Tile Configuration; Horizontal Channel 98" group.byte 0x63++0x00 line.byte 0x00 "ROUTE_HC99,UDB Channel HC Tile Configuration; Horizontal Channel 99" group.byte 0x64++0x00 line.byte 0x00 "ROUTE_HC100,UDB Channel HC Tile Configuration; Horizontal Channel 100" group.byte 0x65++0x00 line.byte 0x00 "ROUTE_HC101,UDB Channel HC Tile Configuration; Horizontal Channel 101" group.byte 0x66++0x00 line.byte 0x00 "ROUTE_HC102,UDB Channel HC Tile Configuration; Horizontal Channel 102" group.byte 0x67++0x00 line.byte 0x00 "ROUTE_HC103,UDB Channel HC Tile Configuration; Horizontal Channel 103" group.byte 0x68++0x00 line.byte 0x00 "ROUTE_HC104,UDB Channel HC Tile Configuration; Horizontal Channel 104" group.byte 0x69++0x00 line.byte 0x00 "ROUTE_HC105,UDB Channel HC Tile Configuration; Horizontal Channel 105" group.byte 0x6A++0x00 line.byte 0x00 "ROUTE_HC106,UDB Channel HC Tile Configuration; Horizontal Channel 106" group.byte 0x6B++0x00 line.byte 0x00 "ROUTE_HC107,UDB Channel HC Tile Configuration; Horizontal Channel 107" group.byte 0x6C++0x00 line.byte 0x00 "ROUTE_HC108,UDB Channel HC Tile Configuration; Horizontal Channel 108" group.byte 0x6D++0x00 line.byte 0x00 "ROUTE_HC109,UDB Channel HC Tile Configuration; Horizontal Channel 109" group.byte 0x6E++0x00 line.byte 0x00 "ROUTE_HC110,UDB Channel HC Tile Configuration; Horizontal Channel 110" group.byte 0x6F++0x00 line.byte 0x00 "ROUTE_HC111,UDB Channel HC Tile Configuration; Horizontal Channel 111" group.byte 0x70++0x00 line.byte 0x00 "ROUTE_HC112,UDB Channel HC Tile Configuration; Horizontal Channel 112" group.byte 0x71++0x00 line.byte 0x00 "ROUTE_HC113,UDB Channel HC Tile Configuration; Horizontal Channel 113" group.byte 0x72++0x00 line.byte 0x00 "ROUTE_HC114,UDB Channel HC Tile Configuration; Horizontal Channel 114" group.byte 0x73++0x00 line.byte 0x00 "ROUTE_HC115,UDB Channel HC Tile Configuration; Horizontal Channel 115" group.byte 0x74++0x00 line.byte 0x00 "ROUTE_HC116,UDB Channel HC Tile Configuration; Horizontal Channel 116" group.byte 0x75++0x00 line.byte 0x00 "ROUTE_HC117,UDB Channel HC Tile Configuration; Horizontal Channel 117" group.byte 0x76++0x00 line.byte 0x00 "ROUTE_HC118,UDB Channel HC Tile Configuration; Horizontal Channel 118" group.byte 0x77++0x00 line.byte 0x00 "ROUTE_HC119,UDB Channel HC Tile Configuration; Horizontal Channel 119" group.byte 0x78++0x00 line.byte 0x00 "ROUTE_HC120,UDB Channel HC Tile Configuration; Horizontal Channel 120" group.byte 0x79++0x00 line.byte 0x00 "ROUTE_HC121,UDB Channel HC Tile Configuration; Horizontal Channel 121" group.byte 0x7A++0x00 line.byte 0x00 "ROUTE_HC122,UDB Channel HC Tile Configuration; Horizontal Channel 122" group.byte 0x7B++0x00 line.byte 0x00 "ROUTE_HC123,UDB Channel HC Tile Configuration; Horizontal Channel 123" group.byte 0x7C++0x00 line.byte 0x00 "ROUTE_HC124,UDB Channel HC Tile Configuration; Horizontal Channel 124" group.byte 0x7D++0x00 line.byte 0x00 "ROUTE_HC125,UDB Channel HC Tile Configuration; Horizontal Channel 125" group.byte 0x7E++0x00 line.byte 0x00 "ROUTE_HC126,UDB Channel HC Tile Configuration; Horizontal Channel 126" group.byte 0x7F++0x00 line.byte 0x00 "ROUTE_HC127,UDB Channel HC Tile Configuration; Horizontal Channel 127" group.byte 0x80++0x00 line.byte 0x00 "ROUTE_HV_L0,UDB Channel HV Tile Configuration; Left 0" group.byte 0x81++0x00 line.byte 0x00 "ROUTE_HV_L1,UDB Channel HV Tile Configuration; Left 1" group.byte 0x82++0x00 line.byte 0x00 "ROUTE_HV_L2,UDB Channel HV Tile Configuration; Left 2" group.byte 0x83++0x00 line.byte 0x00 "ROUTE_HV_L3,UDB Channel HV Tile Configuration; Left 3" group.byte 0x84++0x00 line.byte 0x00 "ROUTE_HV_L4,UDB Channel HV Tile Configuration; Left 4" group.byte 0x85++0x00 line.byte 0x00 "ROUTE_HV_L5,UDB Channel HV Tile Configuration; Left 5" group.byte 0x86++0x00 line.byte 0x00 "ROUTE_HV_L6,UDB Channel HV Tile Configuration; Left 6" group.byte 0x87++0x00 line.byte 0x00 "ROUTE_HV_L7,UDB Channel HV Tile Configuration; Left 7" group.byte 0x88++0x00 line.byte 0x00 "ROUTE_HV_L8,UDB Channel HV Tile Configuration; Left 8" group.byte 0x89++0x00 line.byte 0x00 "ROUTE_HV_L9,UDB Channel HV Tile Configuration; Left 9" group.byte 0x8A++0x00 line.byte 0x00 "ROUTE_HV_L10,UDB Channel HV Tile Configuration; Left 10" group.byte 0x8B++0x00 line.byte 0x00 "ROUTE_HV_L11,UDB Channel HV Tile Configuration; Left 11" group.byte 0x8C++0x00 line.byte 0x00 "ROUTE_HV_L12,UDB Channel HV Tile Configuration; Left 12" group.byte 0x8D++0x00 line.byte 0x00 "ROUTE_HV_L13,UDB Channel HV Tile Configuration; Left 13" group.byte 0x8E++0x00 line.byte 0x00 "ROUTE_HV_L14,UDB Channel HV Tile Configuration; Left 14" group.byte 0x8F++0x00 line.byte 0x00 "ROUTE_HV_L15,UDB Channel HV Tile Configuration; Left 15" group.byte 0x90++0x00 line.byte 0x00 "ROUTE_HS0,UDB Channel HS Tile Configuration; Horizontal Segmentation 0" group.byte 0x91++0x00 line.byte 0x00 "ROUTE_HS1,UDB Channel HS Tile Configuration; Horizontal Segmentation 1" group.byte 0x92++0x00 line.byte 0x00 "ROUTE_HS2,UDB Channel HS Tile Configuration; Horizontal Segmentation 2" group.byte 0x93++0x00 line.byte 0x00 "ROUTE_HS3,UDB Channel HS Tile Configuration; Horizontal Segmentation 3" group.byte 0x94++0x00 line.byte 0x00 "ROUTE_HS4,UDB Channel HS Tile Configuration; Horizontal Segmentation 4" group.byte 0x95++0x00 line.byte 0x00 "ROUTE_HS5,UDB Channel HS Tile Configuration; Horizontal Segmentation 5" group.byte 0x96++0x00 line.byte 0x00 "ROUTE_HS6,UDB Channel HS Tile Configuration; Horizontal Segmentation 6" group.byte 0x97++0x00 line.byte 0x00 "ROUTE_HS7,UDB Channel HS Tile Configuration; Horizontal Segmentation 7" group.byte 0x98++0x00 line.byte 0x00 "ROUTE_HS8,UDB Channel HS Tile Configuration; Horizontal Segmentation 8" group.byte 0x99++0x00 line.byte 0x00 "ROUTE_HS9,UDB Channel HS Tile Configuration; Horizontal Segmentation 9" group.byte 0x9A++0x00 line.byte 0x00 "ROUTE_HS10,UDB Channel HS Tile Configuration; Horizontal Segmentation 10" group.byte 0x9B++0x00 line.byte 0x00 "ROUTE_HS11,UDB Channel HS Tile Configuration; Horizontal Segmentation 11" group.byte 0x9C++0x00 line.byte 0x00 "ROUTE_HS12,UDB Channel HS Tile Configuration; Horizontal Segmentation 12" group.byte 0x9D++0x00 line.byte 0x00 "ROUTE_HS13,UDB Channel HS Tile Configuration; Horizontal Segmentation 13" group.byte 0x9E++0x00 line.byte 0x00 "ROUTE_HS14,UDB Channel HS Tile Configuration; Horizontal Segmentation 14" group.byte 0x9F++0x00 line.byte 0x00 "ROUTE_HS15,UDB Channel HS Tile Configuration; Horizontal Segmentation 15" group.byte 0xA0++0x00 line.byte 0x00 "ROUTE_HS16,UDB Channel HS Tile Configuration; Horizontal Segmentation 16" group.byte 0xA1++0x00 line.byte 0x00 "ROUTE_HS17,UDB Channel HS Tile Configuration; Horizontal Segmentation 17" group.byte 0xA2++0x00 line.byte 0x00 "ROUTE_HS18,UDB Channel HS Tile Configuration; Horizontal Segmentation 18" group.byte 0xA3++0x00 line.byte 0x00 "ROUTE_HS19,UDB Channel HS Tile Configuration; Horizontal Segmentation 19" group.byte 0xA4++0x00 line.byte 0x00 "ROUTE_HS20,UDB Channel HS Tile Configuration; Horizontal Segmentation 20" group.byte 0xA5++0x00 line.byte 0x00 "ROUTE_HS21,UDB Channel HS Tile Configuration; Horizontal Segmentation 21" group.byte 0xA6++0x00 line.byte 0x00 "ROUTE_HS22,UDB Channel HS Tile Configuration; Horizontal Segmentation 22" group.byte 0xA7++0x00 line.byte 0x00 "ROUTE_HS23,UDB Channel HS Tile Configuration; Horizontal Segmentation 23" group.byte 0xA8++0x00 line.byte 0x00 "ROUTE_HV_R0,UDB Channel HV Tile Configuration; Right 0" group.byte 0xA9++0x00 line.byte 0x00 "ROUTE_HV_R1,UDB Channel HV Tile Configuration; Right 1" group.byte 0xAA++0x00 line.byte 0x00 "ROUTE_HV_R2,UDB Channel HV Tile Configuration; Right 2" group.byte 0xAB++0x00 line.byte 0x00 "ROUTE_HV_R3,UDB Channel HV Tile Configuration; Right 3" group.byte 0xAC++0x00 line.byte 0x00 "ROUTE_HV_R4,UDB Channel HV Tile Configuration; Right 4" group.byte 0xAD++0x00 line.byte 0x00 "ROUTE_HV_R5,UDB Channel HV Tile Configuration; Right 5" group.byte 0xAE++0x00 line.byte 0x00 "ROUTE_HV_R6,UDB Channel HV Tile Configuration; Right 6" group.byte 0xAF++0x00 line.byte 0x00 "ROUTE_HV_R7,UDB Channel HV Tile Configuration; Right 7" group.byte 0xB0++0x00 line.byte 0x00 "ROUTE_HV_R8,UDB Channel HV Tile Configuration; Right 8" group.byte 0xB1++0x00 line.byte 0x00 "ROUTE_HV_R9,UDB Channel HV Tile Configuration; Right 9" group.byte 0xB2++0x00 line.byte 0x00 "ROUTE_HV_R10,UDB Channel HV Tile Configuration; Right 10" group.byte 0xB3++0x00 line.byte 0x00 "ROUTE_HV_R11,UDB Channel HV Tile Configuration; Right 11" group.byte 0xB4++0x00 line.byte 0x00 "ROUTE_HV_R12,UDB Channel HV Tile Configuration; Right 12" group.byte 0xB5++0x00 line.byte 0x00 "ROUTE_HV_R13,UDB Channel HV Tile Configuration; Right 13" group.byte 0xB6++0x00 line.byte 0x00 "ROUTE_HV_R14,UDB Channel HV Tile Configuration; Right 14" group.byte 0xB7++0x00 line.byte 0x00 "ROUTE_HV_R15,UDB Channel HV Tile Configuration; Right 15" group.word 0xC0++0x01 line.word 0x00 "ROUTE_PLD0IN0,UDB Channel PI Tile Configuration; PLD Input 0" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xC2++0x01 line.word 0x00 "ROUTE_PLD0IN1,UDB Channel PI Tile Configuration; PLD Input 1" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xC4++0x01 line.word 0x00 "ROUTE_PLD0IN2,UDB Channel PI Tile Configuration; PLD Input 2" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xCA++0x01 line.word 0x00 "ROUTE_PLD1IN0,UDB Channel PI Tile Configuration; PLD Input 0" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xCC++0x01 line.word 0x00 "ROUTE_PLD1IN1,UDB Channel PI Tile Configuration; PLD Input 1" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xCE++0x01 line.word 0x00 "ROUTE_PLD1IN2,UDB Channel PI Tile Configuration; PLD Input 2" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xD0++0x00 line.byte 0x00 "ROUTE_DPIN0,UDB Channel PI Tile Configuration; Datapath Input 0" bitfld.byte 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xD2++0x00 line.byte 0x00 "ROUTE_DPIN1,UDB Channel PI Tile Configuration; Datapath Input 1" bitfld.byte 0x00 4.--5. " PI_BOT2 ,RAM configuration bits (2) for BOTTOM UDB port interface configuration" "0,1,2,3" bitfld.byte 0x00 2.--3. " PI_TOP2 ,RAM configuration bits (2) for TOP UDB port interface configuration" "0,1,2,3" group.byte 0xD6++0x00 line.byte 0x00 "ROUTE_SCIN,UDB Channel PI Tile Configuration; Status / Control Blocks Input Control" bitfld.byte 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xD8++0x00 line.byte 0x00 "ROUTE_SCIOIN,UDB Channel PI Tile Configuration; Status / Control Blocks Input / Output Control" bitfld.byte 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xDE++0x00 line.byte 0x00 "ROUTE_RCIN,UDB Channel PI Tile Configuration; Reset And Clock Blocks Input Control" bitfld.byte 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE0++0x01 line.word 0x00 "ROUTE_VS0,UDB Channel VS Tile Configuration; Vertical Segmentation 0" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration nibble for BOTTOM UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration nibble for TOP UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE2++0x01 line.word 0x00 "ROUTE_VS1,UDB Channel VS Tile Configuration; Vertical Segmentation 1" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration nibble for BOTTOM UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration nibble for TOP UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE4++0x01 line.word 0x00 "ROUTE_VS2,UDB Channel VS Tile Configuration; Vertical Segmentation 2" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration nibble for BOTTOM UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration nibble for TOP UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE6++0x01 line.word 0x00 "ROUTE_VS3,UDB Channel VS Tile Configuration; Vertical Segmentation 3" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration nibble for BOTTOM UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration nibble for TOP UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE8++0x01 line.word 0x00 "ROUTE_VS4,UDB Channel VS Tile Configuration; Vertical Segmentation 4" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration nibble for BOTTOM UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration nibble for TOP UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xEA++0x01 line.word 0x00 "ROUTE_VS5,UDB Channel VS Tile Configuration; Vertical Segmentation 5" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration nibble for BOTTOM UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration nibble for TOP UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xEC++0x01 line.word 0x00 "ROUTE_VS6,UDB Channel VS Tile Configuration; Vertical Segmentation 6" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration nibble for BOTTOM UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration nibble for TOP UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xEE++0x01 line.word 0x00 "ROUTE_VS7,UDB Channel VS Tile Configuration; Vertical Segmentation 7" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration nibble for BOTTOM UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration nibble for TOP UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree "UDB_P2" base ad:0x400F3500 width 16. group.byte 0x0++0x00 line.byte 0x00 "ROUTE_HC0,UDB Channel HC Tile Configuration; Horizontal Channel 0" group.byte 0x1++0x00 line.byte 0x00 "ROUTE_HC1,UDB Channel HC Tile Configuration; Horizontal Channel 1" group.byte 0x2++0x00 line.byte 0x00 "ROUTE_HC2,UDB Channel HC Tile Configuration; Horizontal Channel 2" group.byte 0x3++0x00 line.byte 0x00 "ROUTE_HC3,UDB Channel HC Tile Configuration; Horizontal Channel 3" group.byte 0x4++0x00 line.byte 0x00 "ROUTE_HC4,UDB Channel HC Tile Configuration; Horizontal Channel 4" group.byte 0x5++0x00 line.byte 0x00 "ROUTE_HC5,UDB Channel HC Tile Configuration; Horizontal Channel 5" group.byte 0x6++0x00 line.byte 0x00 "ROUTE_HC6,UDB Channel HC Tile Configuration; Horizontal Channel 6" group.byte 0x7++0x00 line.byte 0x00 "ROUTE_HC7,UDB Channel HC Tile Configuration; Horizontal Channel 7" group.byte 0x8++0x00 line.byte 0x00 "ROUTE_HC8,UDB Channel HC Tile Configuration; Horizontal Channel 8" group.byte 0x9++0x00 line.byte 0x00 "ROUTE_HC9,UDB Channel HC Tile Configuration; Horizontal Channel 9" group.byte 0xA++0x00 line.byte 0x00 "ROUTE_HC10,UDB Channel HC Tile Configuration; Horizontal Channel 10" group.byte 0xB++0x00 line.byte 0x00 "ROUTE_HC11,UDB Channel HC Tile Configuration; Horizontal Channel 11" group.byte 0xC++0x00 line.byte 0x00 "ROUTE_HC12,UDB Channel HC Tile Configuration; Horizontal Channel 12" group.byte 0xD++0x00 line.byte 0x00 "ROUTE_HC13,UDB Channel HC Tile Configuration; Horizontal Channel 13" group.byte 0xE++0x00 line.byte 0x00 "ROUTE_HC14,UDB Channel HC Tile Configuration; Horizontal Channel 14" group.byte 0xF++0x00 line.byte 0x00 "ROUTE_HC15,UDB Channel HC Tile Configuration; Horizontal Channel 15" group.byte 0x10++0x00 line.byte 0x00 "ROUTE_HC16,UDB Channel HC Tile Configuration; Horizontal Channel 16" group.byte 0x11++0x00 line.byte 0x00 "ROUTE_HC17,UDB Channel HC Tile Configuration; Horizontal Channel 17" group.byte 0x12++0x00 line.byte 0x00 "ROUTE_HC18,UDB Channel HC Tile Configuration; Horizontal Channel 18" group.byte 0x13++0x00 line.byte 0x00 "ROUTE_HC19,UDB Channel HC Tile Configuration; Horizontal Channel 19" group.byte 0x14++0x00 line.byte 0x00 "ROUTE_HC20,UDB Channel HC Tile Configuration; Horizontal Channel 20" group.byte 0x15++0x00 line.byte 0x00 "ROUTE_HC21,UDB Channel HC Tile Configuration; Horizontal Channel 21" group.byte 0x16++0x00 line.byte 0x00 "ROUTE_HC22,UDB Channel HC Tile Configuration; Horizontal Channel 22" group.byte 0x17++0x00 line.byte 0x00 "ROUTE_HC23,UDB Channel HC Tile Configuration; Horizontal Channel 23" group.byte 0x18++0x00 line.byte 0x00 "ROUTE_HC24,UDB Channel HC Tile Configuration; Horizontal Channel 24" group.byte 0x19++0x00 line.byte 0x00 "ROUTE_HC25,UDB Channel HC Tile Configuration; Horizontal Channel 25" group.byte 0x1A++0x00 line.byte 0x00 "ROUTE_HC26,UDB Channel HC Tile Configuration; Horizontal Channel 26" group.byte 0x1B++0x00 line.byte 0x00 "ROUTE_HC27,UDB Channel HC Tile Configuration; Horizontal Channel 27" group.byte 0x1C++0x00 line.byte 0x00 "ROUTE_HC28,UDB Channel HC Tile Configuration; Horizontal Channel 28" group.byte 0x1D++0x00 line.byte 0x00 "ROUTE_HC29,UDB Channel HC Tile Configuration; Horizontal Channel 29" group.byte 0x1E++0x00 line.byte 0x00 "ROUTE_HC30,UDB Channel HC Tile Configuration; Horizontal Channel 30" group.byte 0x1F++0x00 line.byte 0x00 "ROUTE_HC31,UDB Channel HC Tile Configuration; Horizontal Channel 31" group.byte 0x20++0x00 line.byte 0x00 "ROUTE_HC32,UDB Channel HC Tile Configuration; Horizontal Channel 32" group.byte 0x21++0x00 line.byte 0x00 "ROUTE_HC33,UDB Channel HC Tile Configuration; Horizontal Channel 33" group.byte 0x22++0x00 line.byte 0x00 "ROUTE_HC34,UDB Channel HC Tile Configuration; Horizontal Channel 34" group.byte 0x23++0x00 line.byte 0x00 "ROUTE_HC35,UDB Channel HC Tile Configuration; Horizontal Channel 35" group.byte 0x24++0x00 line.byte 0x00 "ROUTE_HC36,UDB Channel HC Tile Configuration; Horizontal Channel 36" group.byte 0x25++0x00 line.byte 0x00 "ROUTE_HC37,UDB Channel HC Tile Configuration; Horizontal Channel 37" group.byte 0x26++0x00 line.byte 0x00 "ROUTE_HC38,UDB Channel HC Tile Configuration; Horizontal Channel 38" group.byte 0x27++0x00 line.byte 0x00 "ROUTE_HC39,UDB Channel HC Tile Configuration; Horizontal Channel 39" group.byte 0x28++0x00 line.byte 0x00 "ROUTE_HC40,UDB Channel HC Tile Configuration; Horizontal Channel 40" group.byte 0x29++0x00 line.byte 0x00 "ROUTE_HC41,UDB Channel HC Tile Configuration; Horizontal Channel 41" group.byte 0x2A++0x00 line.byte 0x00 "ROUTE_HC42,UDB Channel HC Tile Configuration; Horizontal Channel 42" group.byte 0x2B++0x00 line.byte 0x00 "ROUTE_HC43,UDB Channel HC Tile Configuration; Horizontal Channel 43" group.byte 0x2C++0x00 line.byte 0x00 "ROUTE_HC44,UDB Channel HC Tile Configuration; Horizontal Channel 44" group.byte 0x2D++0x00 line.byte 0x00 "ROUTE_HC45,UDB Channel HC Tile Configuration; Horizontal Channel 45" group.byte 0x2E++0x00 line.byte 0x00 "ROUTE_HC46,UDB Channel HC Tile Configuration; Horizontal Channel 46" group.byte 0x2F++0x00 line.byte 0x00 "ROUTE_HC47,UDB Channel HC Tile Configuration; Horizontal Channel 47" group.byte 0x30++0x00 line.byte 0x00 "ROUTE_HC48,UDB Channel HC Tile Configuration; Horizontal Channel 48" group.byte 0x31++0x00 line.byte 0x00 "ROUTE_HC49,UDB Channel HC Tile Configuration; Horizontal Channel 49" group.byte 0x32++0x00 line.byte 0x00 "ROUTE_HC50,UDB Channel HC Tile Configuration; Horizontal Channel 50" group.byte 0x33++0x00 line.byte 0x00 "ROUTE_HC51,UDB Channel HC Tile Configuration; Horizontal Channel 51" group.byte 0x34++0x00 line.byte 0x00 "ROUTE_HC52,UDB Channel HC Tile Configuration; Horizontal Channel 52" group.byte 0x35++0x00 line.byte 0x00 "ROUTE_HC53,UDB Channel HC Tile Configuration; Horizontal Channel 53" group.byte 0x36++0x00 line.byte 0x00 "ROUTE_HC54,UDB Channel HC Tile Configuration; Horizontal Channel 54" group.byte 0x37++0x00 line.byte 0x00 "ROUTE_HC55,UDB Channel HC Tile Configuration; Horizontal Channel 55" group.byte 0x38++0x00 line.byte 0x00 "ROUTE_HC56,UDB Channel HC Tile Configuration; Horizontal Channel 56" group.byte 0x39++0x00 line.byte 0x00 "ROUTE_HC57,UDB Channel HC Tile Configuration; Horizontal Channel 57" group.byte 0x3A++0x00 line.byte 0x00 "ROUTE_HC58,UDB Channel HC Tile Configuration; Horizontal Channel 58" group.byte 0x3B++0x00 line.byte 0x00 "ROUTE_HC59,UDB Channel HC Tile Configuration; Horizontal Channel 59" group.byte 0x3C++0x00 line.byte 0x00 "ROUTE_HC60,UDB Channel HC Tile Configuration; Horizontal Channel 60" group.byte 0x3D++0x00 line.byte 0x00 "ROUTE_HC61,UDB Channel HC Tile Configuration; Horizontal Channel 61" group.byte 0x3E++0x00 line.byte 0x00 "ROUTE_HC62,UDB Channel HC Tile Configuration; Horizontal Channel 62" group.byte 0x3F++0x00 line.byte 0x00 "ROUTE_HC63,UDB Channel HC Tile Configuration; Horizontal Channel 63" group.byte 0x40++0x00 line.byte 0x00 "ROUTE_HC64,UDB Channel HC Tile Configuration; Horizontal Channel 64" group.byte 0x41++0x00 line.byte 0x00 "ROUTE_HC65,UDB Channel HC Tile Configuration; Horizontal Channel 65" group.byte 0x42++0x00 line.byte 0x00 "ROUTE_HC66,UDB Channel HC Tile Configuration; Horizontal Channel 66" group.byte 0x43++0x00 line.byte 0x00 "ROUTE_HC67,UDB Channel HC Tile Configuration; Horizontal Channel 67" group.byte 0x44++0x00 line.byte 0x00 "ROUTE_HC68,UDB Channel HC Tile Configuration; Horizontal Channel 68" group.byte 0x45++0x00 line.byte 0x00 "ROUTE_HC69,UDB Channel HC Tile Configuration; Horizontal Channel 69" group.byte 0x46++0x00 line.byte 0x00 "ROUTE_HC70,UDB Channel HC Tile Configuration; Horizontal Channel 70" group.byte 0x47++0x00 line.byte 0x00 "ROUTE_HC71,UDB Channel HC Tile Configuration; Horizontal Channel 71" group.byte 0x48++0x00 line.byte 0x00 "ROUTE_HC72,UDB Channel HC Tile Configuration; Horizontal Channel 72" group.byte 0x49++0x00 line.byte 0x00 "ROUTE_HC73,UDB Channel HC Tile Configuration; Horizontal Channel 73" group.byte 0x4A++0x00 line.byte 0x00 "ROUTE_HC74,UDB Channel HC Tile Configuration; Horizontal Channel 74" group.byte 0x4B++0x00 line.byte 0x00 "ROUTE_HC75,UDB Channel HC Tile Configuration; Horizontal Channel 75" group.byte 0x4C++0x00 line.byte 0x00 "ROUTE_HC76,UDB Channel HC Tile Configuration; Horizontal Channel 76" group.byte 0x4D++0x00 line.byte 0x00 "ROUTE_HC77,UDB Channel HC Tile Configuration; Horizontal Channel 77" group.byte 0x4E++0x00 line.byte 0x00 "ROUTE_HC78,UDB Channel HC Tile Configuration; Horizontal Channel 78" group.byte 0x4F++0x00 line.byte 0x00 "ROUTE_HC79,UDB Channel HC Tile Configuration; Horizontal Channel 79" group.byte 0x50++0x00 line.byte 0x00 "ROUTE_HC80,UDB Channel HC Tile Configuration; Horizontal Channel 80" group.byte 0x51++0x00 line.byte 0x00 "ROUTE_HC81,UDB Channel HC Tile Configuration; Horizontal Channel 81" group.byte 0x52++0x00 line.byte 0x00 "ROUTE_HC82,UDB Channel HC Tile Configuration; Horizontal Channel 82" group.byte 0x53++0x00 line.byte 0x00 "ROUTE_HC83,UDB Channel HC Tile Configuration; Horizontal Channel 83" group.byte 0x54++0x00 line.byte 0x00 "ROUTE_HC84,UDB Channel HC Tile Configuration; Horizontal Channel 84" group.byte 0x55++0x00 line.byte 0x00 "ROUTE_HC85,UDB Channel HC Tile Configuration; Horizontal Channel 85" group.byte 0x56++0x00 line.byte 0x00 "ROUTE_HC86,UDB Channel HC Tile Configuration; Horizontal Channel 86" group.byte 0x57++0x00 line.byte 0x00 "ROUTE_HC87,UDB Channel HC Tile Configuration; Horizontal Channel 87" group.byte 0x58++0x00 line.byte 0x00 "ROUTE_HC88,UDB Channel HC Tile Configuration; Horizontal Channel 88" group.byte 0x59++0x00 line.byte 0x00 "ROUTE_HC89,UDB Channel HC Tile Configuration; Horizontal Channel 89" group.byte 0x5A++0x00 line.byte 0x00 "ROUTE_HC90,UDB Channel HC Tile Configuration; Horizontal Channel 90" group.byte 0x5B++0x00 line.byte 0x00 "ROUTE_HC91,UDB Channel HC Tile Configuration; Horizontal Channel 91" group.byte 0x5C++0x00 line.byte 0x00 "ROUTE_HC92,UDB Channel HC Tile Configuration; Horizontal Channel 92" group.byte 0x5D++0x00 line.byte 0x00 "ROUTE_HC93,UDB Channel HC Tile Configuration; Horizontal Channel 93" group.byte 0x5E++0x00 line.byte 0x00 "ROUTE_HC94,UDB Channel HC Tile Configuration; Horizontal Channel 94" group.byte 0x5F++0x00 line.byte 0x00 "ROUTE_HC95,UDB Channel HC Tile Configuration; Horizontal Channel 95" group.byte 0x60++0x00 line.byte 0x00 "ROUTE_HC96,UDB Channel HC Tile Configuration; Horizontal Channel 96" group.byte 0x61++0x00 line.byte 0x00 "ROUTE_HC97,UDB Channel HC Tile Configuration; Horizontal Channel 97" group.byte 0x62++0x00 line.byte 0x00 "ROUTE_HC98,UDB Channel HC Tile Configuration; Horizontal Channel 98" group.byte 0x63++0x00 line.byte 0x00 "ROUTE_HC99,UDB Channel HC Tile Configuration; Horizontal Channel 99" group.byte 0x64++0x00 line.byte 0x00 "ROUTE_HC100,UDB Channel HC Tile Configuration; Horizontal Channel 100" group.byte 0x65++0x00 line.byte 0x00 "ROUTE_HC101,UDB Channel HC Tile Configuration; Horizontal Channel 101" group.byte 0x66++0x00 line.byte 0x00 "ROUTE_HC102,UDB Channel HC Tile Configuration; Horizontal Channel 102" group.byte 0x67++0x00 line.byte 0x00 "ROUTE_HC103,UDB Channel HC Tile Configuration; Horizontal Channel 103" group.byte 0x68++0x00 line.byte 0x00 "ROUTE_HC104,UDB Channel HC Tile Configuration; Horizontal Channel 104" group.byte 0x69++0x00 line.byte 0x00 "ROUTE_HC105,UDB Channel HC Tile Configuration; Horizontal Channel 105" group.byte 0x6A++0x00 line.byte 0x00 "ROUTE_HC106,UDB Channel HC Tile Configuration; Horizontal Channel 106" group.byte 0x6B++0x00 line.byte 0x00 "ROUTE_HC107,UDB Channel HC Tile Configuration; Horizontal Channel 107" group.byte 0x6C++0x00 line.byte 0x00 "ROUTE_HC108,UDB Channel HC Tile Configuration; Horizontal Channel 108" group.byte 0x6D++0x00 line.byte 0x00 "ROUTE_HC109,UDB Channel HC Tile Configuration; Horizontal Channel 109" group.byte 0x6E++0x00 line.byte 0x00 "ROUTE_HC110,UDB Channel HC Tile Configuration; Horizontal Channel 110" group.byte 0x6F++0x00 line.byte 0x00 "ROUTE_HC111,UDB Channel HC Tile Configuration; Horizontal Channel 111" group.byte 0x70++0x00 line.byte 0x00 "ROUTE_HC112,UDB Channel HC Tile Configuration; Horizontal Channel 112" group.byte 0x71++0x00 line.byte 0x00 "ROUTE_HC113,UDB Channel HC Tile Configuration; Horizontal Channel 113" group.byte 0x72++0x00 line.byte 0x00 "ROUTE_HC114,UDB Channel HC Tile Configuration; Horizontal Channel 114" group.byte 0x73++0x00 line.byte 0x00 "ROUTE_HC115,UDB Channel HC Tile Configuration; Horizontal Channel 115" group.byte 0x74++0x00 line.byte 0x00 "ROUTE_HC116,UDB Channel HC Tile Configuration; Horizontal Channel 116" group.byte 0x75++0x00 line.byte 0x00 "ROUTE_HC117,UDB Channel HC Tile Configuration; Horizontal Channel 117" group.byte 0x76++0x00 line.byte 0x00 "ROUTE_HC118,UDB Channel HC Tile Configuration; Horizontal Channel 118" group.byte 0x77++0x00 line.byte 0x00 "ROUTE_HC119,UDB Channel HC Tile Configuration; Horizontal Channel 119" group.byte 0x78++0x00 line.byte 0x00 "ROUTE_HC120,UDB Channel HC Tile Configuration; Horizontal Channel 120" group.byte 0x79++0x00 line.byte 0x00 "ROUTE_HC121,UDB Channel HC Tile Configuration; Horizontal Channel 121" group.byte 0x7A++0x00 line.byte 0x00 "ROUTE_HC122,UDB Channel HC Tile Configuration; Horizontal Channel 122" group.byte 0x7B++0x00 line.byte 0x00 "ROUTE_HC123,UDB Channel HC Tile Configuration; Horizontal Channel 123" group.byte 0x7C++0x00 line.byte 0x00 "ROUTE_HC124,UDB Channel HC Tile Configuration; Horizontal Channel 124" group.byte 0x7D++0x00 line.byte 0x00 "ROUTE_HC125,UDB Channel HC Tile Configuration; Horizontal Channel 125" group.byte 0x7E++0x00 line.byte 0x00 "ROUTE_HC126,UDB Channel HC Tile Configuration; Horizontal Channel 126" group.byte 0x7F++0x00 line.byte 0x00 "ROUTE_HC127,UDB Channel HC Tile Configuration; Horizontal Channel 127" group.byte 0x80++0x00 line.byte 0x00 "ROUTE_HV_L0,UDB Channel HV Tile Configuration; Left 0" group.byte 0x81++0x00 line.byte 0x00 "ROUTE_HV_L1,UDB Channel HV Tile Configuration; Left 1" group.byte 0x82++0x00 line.byte 0x00 "ROUTE_HV_L2,UDB Channel HV Tile Configuration; Left 2" group.byte 0x83++0x00 line.byte 0x00 "ROUTE_HV_L3,UDB Channel HV Tile Configuration; Left 3" group.byte 0x84++0x00 line.byte 0x00 "ROUTE_HV_L4,UDB Channel HV Tile Configuration; Left 4" group.byte 0x85++0x00 line.byte 0x00 "ROUTE_HV_L5,UDB Channel HV Tile Configuration; Left 5" group.byte 0x86++0x00 line.byte 0x00 "ROUTE_HV_L6,UDB Channel HV Tile Configuration; Left 6" group.byte 0x87++0x00 line.byte 0x00 "ROUTE_HV_L7,UDB Channel HV Tile Configuration; Left 7" group.byte 0x88++0x00 line.byte 0x00 "ROUTE_HV_L8,UDB Channel HV Tile Configuration; Left 8" group.byte 0x89++0x00 line.byte 0x00 "ROUTE_HV_L9,UDB Channel HV Tile Configuration; Left 9" group.byte 0x8A++0x00 line.byte 0x00 "ROUTE_HV_L10,UDB Channel HV Tile Configuration; Left 10" group.byte 0x8B++0x00 line.byte 0x00 "ROUTE_HV_L11,UDB Channel HV Tile Configuration; Left 11" group.byte 0x8C++0x00 line.byte 0x00 "ROUTE_HV_L12,UDB Channel HV Tile Configuration; Left 12" group.byte 0x8D++0x00 line.byte 0x00 "ROUTE_HV_L13,UDB Channel HV Tile Configuration; Left 13" group.byte 0x8E++0x00 line.byte 0x00 "ROUTE_HV_L14,UDB Channel HV Tile Configuration; Left 14" group.byte 0x8F++0x00 line.byte 0x00 "ROUTE_HV_L15,UDB Channel HV Tile Configuration; Left 15" group.byte 0x90++0x00 line.byte 0x00 "ROUTE_HS0,UDB Channel HS Tile Configuration; Horizontal Segmentation 0" group.byte 0x91++0x00 line.byte 0x00 "ROUTE_HS1,UDB Channel HS Tile Configuration; Horizontal Segmentation 1" group.byte 0x92++0x00 line.byte 0x00 "ROUTE_HS2,UDB Channel HS Tile Configuration; Horizontal Segmentation 2" group.byte 0x93++0x00 line.byte 0x00 "ROUTE_HS3,UDB Channel HS Tile Configuration; Horizontal Segmentation 3" group.byte 0x94++0x00 line.byte 0x00 "ROUTE_HS4,UDB Channel HS Tile Configuration; Horizontal Segmentation 4" group.byte 0x95++0x00 line.byte 0x00 "ROUTE_HS5,UDB Channel HS Tile Configuration; Horizontal Segmentation 5" group.byte 0x96++0x00 line.byte 0x00 "ROUTE_HS6,UDB Channel HS Tile Configuration; Horizontal Segmentation 6" group.byte 0x97++0x00 line.byte 0x00 "ROUTE_HS7,UDB Channel HS Tile Configuration; Horizontal Segmentation 7" group.byte 0x98++0x00 line.byte 0x00 "ROUTE_HS8,UDB Channel HS Tile Configuration; Horizontal Segmentation 8" group.byte 0x99++0x00 line.byte 0x00 "ROUTE_HS9,UDB Channel HS Tile Configuration; Horizontal Segmentation 9" group.byte 0x9A++0x00 line.byte 0x00 "ROUTE_HS10,UDB Channel HS Tile Configuration; Horizontal Segmentation 10" group.byte 0x9B++0x00 line.byte 0x00 "ROUTE_HS11,UDB Channel HS Tile Configuration; Horizontal Segmentation 11" group.byte 0x9C++0x00 line.byte 0x00 "ROUTE_HS12,UDB Channel HS Tile Configuration; Horizontal Segmentation 12" group.byte 0x9D++0x00 line.byte 0x00 "ROUTE_HS13,UDB Channel HS Tile Configuration; Horizontal Segmentation 13" group.byte 0x9E++0x00 line.byte 0x00 "ROUTE_HS14,UDB Channel HS Tile Configuration; Horizontal Segmentation 14" group.byte 0x9F++0x00 line.byte 0x00 "ROUTE_HS15,UDB Channel HS Tile Configuration; Horizontal Segmentation 15" group.byte 0xA0++0x00 line.byte 0x00 "ROUTE_HS16,UDB Channel HS Tile Configuration; Horizontal Segmentation 16" group.byte 0xA1++0x00 line.byte 0x00 "ROUTE_HS17,UDB Channel HS Tile Configuration; Horizontal Segmentation 17" group.byte 0xA2++0x00 line.byte 0x00 "ROUTE_HS18,UDB Channel HS Tile Configuration; Horizontal Segmentation 18" group.byte 0xA3++0x00 line.byte 0x00 "ROUTE_HS19,UDB Channel HS Tile Configuration; Horizontal Segmentation 19" group.byte 0xA4++0x00 line.byte 0x00 "ROUTE_HS20,UDB Channel HS Tile Configuration; Horizontal Segmentation 20" group.byte 0xA5++0x00 line.byte 0x00 "ROUTE_HS21,UDB Channel HS Tile Configuration; Horizontal Segmentation 21" group.byte 0xA6++0x00 line.byte 0x00 "ROUTE_HS22,UDB Channel HS Tile Configuration; Horizontal Segmentation 22" group.byte 0xA7++0x00 line.byte 0x00 "ROUTE_HS23,UDB Channel HS Tile Configuration; Horizontal Segmentation 23" group.byte 0xA8++0x00 line.byte 0x00 "ROUTE_HV_R0,UDB Channel HV Tile Configuration; Right 0" group.byte 0xA9++0x00 line.byte 0x00 "ROUTE_HV_R1,UDB Channel HV Tile Configuration; Right 1" group.byte 0xAA++0x00 line.byte 0x00 "ROUTE_HV_R2,UDB Channel HV Tile Configuration; Right 2" group.byte 0xAB++0x00 line.byte 0x00 "ROUTE_HV_R3,UDB Channel HV Tile Configuration; Right 3" group.byte 0xAC++0x00 line.byte 0x00 "ROUTE_HV_R4,UDB Channel HV Tile Configuration; Right 4" group.byte 0xAD++0x00 line.byte 0x00 "ROUTE_HV_R5,UDB Channel HV Tile Configuration; Right 5" group.byte 0xAE++0x00 line.byte 0x00 "ROUTE_HV_R6,UDB Channel HV Tile Configuration; Right 6" group.byte 0xAF++0x00 line.byte 0x00 "ROUTE_HV_R7,UDB Channel HV Tile Configuration; Right 7" group.byte 0xB0++0x00 line.byte 0x00 "ROUTE_HV_R8,UDB Channel HV Tile Configuration; Right 8" group.byte 0xB1++0x00 line.byte 0x00 "ROUTE_HV_R9,UDB Channel HV Tile Configuration; Right 9" group.byte 0xB2++0x00 line.byte 0x00 "ROUTE_HV_R10,UDB Channel HV Tile Configuration; Right 10" group.byte 0xB3++0x00 line.byte 0x00 "ROUTE_HV_R11,UDB Channel HV Tile Configuration; Right 11" group.byte 0xB4++0x00 line.byte 0x00 "ROUTE_HV_R12,UDB Channel HV Tile Configuration; Right 12" group.byte 0xB5++0x00 line.byte 0x00 "ROUTE_HV_R13,UDB Channel HV Tile Configuration; Right 13" group.byte 0xB6++0x00 line.byte 0x00 "ROUTE_HV_R14,UDB Channel HV Tile Configuration; Right 14" group.byte 0xB7++0x00 line.byte 0x00 "ROUTE_HV_R15,UDB Channel HV Tile Configuration; Right 15" group.word 0xC0++0x01 line.word 0x00 "ROUTE_PLD0IN0,UDB Channel PI Tile Configuration; PLD Input 0" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xC2++0x01 line.word 0x00 "ROUTE_PLD0IN1,UDB Channel PI Tile Configuration; PLD Input 1" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xC4++0x01 line.word 0x00 "ROUTE_PLD0IN2,UDB Channel PI Tile Configuration; PLD Input 2" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xCA++0x01 line.word 0x00 "ROUTE_PLD1IN0,UDB Channel PI Tile Configuration; PLD Input 0" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xCC++0x01 line.word 0x00 "ROUTE_PLD1IN1,UDB Channel PI Tile Configuration; PLD Input 1" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xCE++0x01 line.word 0x00 "ROUTE_PLD1IN2,UDB Channel PI Tile Configuration; PLD Input 2" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xD0++0x00 line.byte 0x00 "ROUTE_DPIN0,UDB Channel PI Tile Configuration; Datapath Input 0" bitfld.byte 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xD2++0x00 line.byte 0x00 "ROUTE_DPIN1,UDB Channel PI Tile Configuration; Datapath Input 1" bitfld.byte 0x00 4.--5. " PI_BOT2 ,RAM configuration bits (2) for BOTTOM UDB port interface configuration" "0,1,2,3" bitfld.byte 0x00 2.--3. " PI_TOP2 ,RAM configuration bits (2) for TOP UDB port interface configuration" "0,1,2,3" group.byte 0xD6++0x00 line.byte 0x00 "ROUTE_SCIN,UDB Channel PI Tile Configuration; Status / Control Blocks Input Control" bitfld.byte 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xD8++0x00 line.byte 0x00 "ROUTE_SCIOIN,UDB Channel PI Tile Configuration; Status / Control Blocks Input / Output Control" bitfld.byte 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xDE++0x00 line.byte 0x00 "ROUTE_RCIN,UDB Channel PI Tile Configuration; Reset And Clock Blocks Input Control" bitfld.byte 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE0++0x01 line.word 0x00 "ROUTE_VS0,UDB Channel VS Tile Configuration; Vertical Segmentation 0" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration nibble for BOTTOM UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration nibble for TOP UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE2++0x01 line.word 0x00 "ROUTE_VS1,UDB Channel VS Tile Configuration; Vertical Segmentation 1" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration nibble for BOTTOM UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration nibble for TOP UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE4++0x01 line.word 0x00 "ROUTE_VS2,UDB Channel VS Tile Configuration; Vertical Segmentation 2" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration nibble for BOTTOM UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration nibble for TOP UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE6++0x01 line.word 0x00 "ROUTE_VS3,UDB Channel VS Tile Configuration; Vertical Segmentation 3" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration nibble for BOTTOM UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration nibble for TOP UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE8++0x01 line.word 0x00 "ROUTE_VS4,UDB Channel VS Tile Configuration; Vertical Segmentation 4" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration nibble for BOTTOM UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration nibble for TOP UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xEA++0x01 line.word 0x00 "ROUTE_VS5,UDB Channel VS Tile Configuration; Vertical Segmentation 5" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration nibble for BOTTOM UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration nibble for TOP UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xEC++0x01 line.word 0x00 "ROUTE_VS6,UDB Channel VS Tile Configuration; Vertical Segmentation 6" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration nibble for BOTTOM UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration nibble for TOP UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xEE++0x01 line.word 0x00 "ROUTE_VS7,UDB Channel VS Tile Configuration; Vertical Segmentation 7" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration nibble for BOTTOM UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration nibble for TOP UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree "UDB_P3" base ad:0x400F3700 width 16. group.byte 0x0++0x00 line.byte 0x00 "ROUTE_HC0,UDB Channel HC Tile Configuration; Horizontal Channel 0" group.byte 0x1++0x00 line.byte 0x00 "ROUTE_HC1,UDB Channel HC Tile Configuration; Horizontal Channel 1" group.byte 0x2++0x00 line.byte 0x00 "ROUTE_HC2,UDB Channel HC Tile Configuration; Horizontal Channel 2" group.byte 0x3++0x00 line.byte 0x00 "ROUTE_HC3,UDB Channel HC Tile Configuration; Horizontal Channel 3" group.byte 0x4++0x00 line.byte 0x00 "ROUTE_HC4,UDB Channel HC Tile Configuration; Horizontal Channel 4" group.byte 0x5++0x00 line.byte 0x00 "ROUTE_HC5,UDB Channel HC Tile Configuration; Horizontal Channel 5" group.byte 0x6++0x00 line.byte 0x00 "ROUTE_HC6,UDB Channel HC Tile Configuration; Horizontal Channel 6" group.byte 0x7++0x00 line.byte 0x00 "ROUTE_HC7,UDB Channel HC Tile Configuration; Horizontal Channel 7" group.byte 0x8++0x00 line.byte 0x00 "ROUTE_HC8,UDB Channel HC Tile Configuration; Horizontal Channel 8" group.byte 0x9++0x00 line.byte 0x00 "ROUTE_HC9,UDB Channel HC Tile Configuration; Horizontal Channel 9" group.byte 0xA++0x00 line.byte 0x00 "ROUTE_HC10,UDB Channel HC Tile Configuration; Horizontal Channel 10" group.byte 0xB++0x00 line.byte 0x00 "ROUTE_HC11,UDB Channel HC Tile Configuration; Horizontal Channel 11" group.byte 0xC++0x00 line.byte 0x00 "ROUTE_HC12,UDB Channel HC Tile Configuration; Horizontal Channel 12" group.byte 0xD++0x00 line.byte 0x00 "ROUTE_HC13,UDB Channel HC Tile Configuration; Horizontal Channel 13" group.byte 0xE++0x00 line.byte 0x00 "ROUTE_HC14,UDB Channel HC Tile Configuration; Horizontal Channel 14" group.byte 0xF++0x00 line.byte 0x00 "ROUTE_HC15,UDB Channel HC Tile Configuration; Horizontal Channel 15" group.byte 0x10++0x00 line.byte 0x00 "ROUTE_HC16,UDB Channel HC Tile Configuration; Horizontal Channel 16" group.byte 0x11++0x00 line.byte 0x00 "ROUTE_HC17,UDB Channel HC Tile Configuration; Horizontal Channel 17" group.byte 0x12++0x00 line.byte 0x00 "ROUTE_HC18,UDB Channel HC Tile Configuration; Horizontal Channel 18" group.byte 0x13++0x00 line.byte 0x00 "ROUTE_HC19,UDB Channel HC Tile Configuration; Horizontal Channel 19" group.byte 0x14++0x00 line.byte 0x00 "ROUTE_HC20,UDB Channel HC Tile Configuration; Horizontal Channel 20" group.byte 0x15++0x00 line.byte 0x00 "ROUTE_HC21,UDB Channel HC Tile Configuration; Horizontal Channel 21" group.byte 0x16++0x00 line.byte 0x00 "ROUTE_HC22,UDB Channel HC Tile Configuration; Horizontal Channel 22" group.byte 0x17++0x00 line.byte 0x00 "ROUTE_HC23,UDB Channel HC Tile Configuration; Horizontal Channel 23" group.byte 0x18++0x00 line.byte 0x00 "ROUTE_HC24,UDB Channel HC Tile Configuration; Horizontal Channel 24" group.byte 0x19++0x00 line.byte 0x00 "ROUTE_HC25,UDB Channel HC Tile Configuration; Horizontal Channel 25" group.byte 0x1A++0x00 line.byte 0x00 "ROUTE_HC26,UDB Channel HC Tile Configuration; Horizontal Channel 26" group.byte 0x1B++0x00 line.byte 0x00 "ROUTE_HC27,UDB Channel HC Tile Configuration; Horizontal Channel 27" group.byte 0x1C++0x00 line.byte 0x00 "ROUTE_HC28,UDB Channel HC Tile Configuration; Horizontal Channel 28" group.byte 0x1D++0x00 line.byte 0x00 "ROUTE_HC29,UDB Channel HC Tile Configuration; Horizontal Channel 29" group.byte 0x1E++0x00 line.byte 0x00 "ROUTE_HC30,UDB Channel HC Tile Configuration; Horizontal Channel 30" group.byte 0x1F++0x00 line.byte 0x00 "ROUTE_HC31,UDB Channel HC Tile Configuration; Horizontal Channel 31" group.byte 0x20++0x00 line.byte 0x00 "ROUTE_HC32,UDB Channel HC Tile Configuration; Horizontal Channel 32" group.byte 0x21++0x00 line.byte 0x00 "ROUTE_HC33,UDB Channel HC Tile Configuration; Horizontal Channel 33" group.byte 0x22++0x00 line.byte 0x00 "ROUTE_HC34,UDB Channel HC Tile Configuration; Horizontal Channel 34" group.byte 0x23++0x00 line.byte 0x00 "ROUTE_HC35,UDB Channel HC Tile Configuration; Horizontal Channel 35" group.byte 0x24++0x00 line.byte 0x00 "ROUTE_HC36,UDB Channel HC Tile Configuration; Horizontal Channel 36" group.byte 0x25++0x00 line.byte 0x00 "ROUTE_HC37,UDB Channel HC Tile Configuration; Horizontal Channel 37" group.byte 0x26++0x00 line.byte 0x00 "ROUTE_HC38,UDB Channel HC Tile Configuration; Horizontal Channel 38" group.byte 0x27++0x00 line.byte 0x00 "ROUTE_HC39,UDB Channel HC Tile Configuration; Horizontal Channel 39" group.byte 0x28++0x00 line.byte 0x00 "ROUTE_HC40,UDB Channel HC Tile Configuration; Horizontal Channel 40" group.byte 0x29++0x00 line.byte 0x00 "ROUTE_HC41,UDB Channel HC Tile Configuration; Horizontal Channel 41" group.byte 0x2A++0x00 line.byte 0x00 "ROUTE_HC42,UDB Channel HC Tile Configuration; Horizontal Channel 42" group.byte 0x2B++0x00 line.byte 0x00 "ROUTE_HC43,UDB Channel HC Tile Configuration; Horizontal Channel 43" group.byte 0x2C++0x00 line.byte 0x00 "ROUTE_HC44,UDB Channel HC Tile Configuration; Horizontal Channel 44" group.byte 0x2D++0x00 line.byte 0x00 "ROUTE_HC45,UDB Channel HC Tile Configuration; Horizontal Channel 45" group.byte 0x2E++0x00 line.byte 0x00 "ROUTE_HC46,UDB Channel HC Tile Configuration; Horizontal Channel 46" group.byte 0x2F++0x00 line.byte 0x00 "ROUTE_HC47,UDB Channel HC Tile Configuration; Horizontal Channel 47" group.byte 0x30++0x00 line.byte 0x00 "ROUTE_HC48,UDB Channel HC Tile Configuration; Horizontal Channel 48" group.byte 0x31++0x00 line.byte 0x00 "ROUTE_HC49,UDB Channel HC Tile Configuration; Horizontal Channel 49" group.byte 0x32++0x00 line.byte 0x00 "ROUTE_HC50,UDB Channel HC Tile Configuration; Horizontal Channel 50" group.byte 0x33++0x00 line.byte 0x00 "ROUTE_HC51,UDB Channel HC Tile Configuration; Horizontal Channel 51" group.byte 0x34++0x00 line.byte 0x00 "ROUTE_HC52,UDB Channel HC Tile Configuration; Horizontal Channel 52" group.byte 0x35++0x00 line.byte 0x00 "ROUTE_HC53,UDB Channel HC Tile Configuration; Horizontal Channel 53" group.byte 0x36++0x00 line.byte 0x00 "ROUTE_HC54,UDB Channel HC Tile Configuration; Horizontal Channel 54" group.byte 0x37++0x00 line.byte 0x00 "ROUTE_HC55,UDB Channel HC Tile Configuration; Horizontal Channel 55" group.byte 0x38++0x00 line.byte 0x00 "ROUTE_HC56,UDB Channel HC Tile Configuration; Horizontal Channel 56" group.byte 0x39++0x00 line.byte 0x00 "ROUTE_HC57,UDB Channel HC Tile Configuration; Horizontal Channel 57" group.byte 0x3A++0x00 line.byte 0x00 "ROUTE_HC58,UDB Channel HC Tile Configuration; Horizontal Channel 58" group.byte 0x3B++0x00 line.byte 0x00 "ROUTE_HC59,UDB Channel HC Tile Configuration; Horizontal Channel 59" group.byte 0x3C++0x00 line.byte 0x00 "ROUTE_HC60,UDB Channel HC Tile Configuration; Horizontal Channel 60" group.byte 0x3D++0x00 line.byte 0x00 "ROUTE_HC61,UDB Channel HC Tile Configuration; Horizontal Channel 61" group.byte 0x3E++0x00 line.byte 0x00 "ROUTE_HC62,UDB Channel HC Tile Configuration; Horizontal Channel 62" group.byte 0x3F++0x00 line.byte 0x00 "ROUTE_HC63,UDB Channel HC Tile Configuration; Horizontal Channel 63" group.byte 0x40++0x00 line.byte 0x00 "ROUTE_HC64,UDB Channel HC Tile Configuration; Horizontal Channel 64" group.byte 0x41++0x00 line.byte 0x00 "ROUTE_HC65,UDB Channel HC Tile Configuration; Horizontal Channel 65" group.byte 0x42++0x00 line.byte 0x00 "ROUTE_HC66,UDB Channel HC Tile Configuration; Horizontal Channel 66" group.byte 0x43++0x00 line.byte 0x00 "ROUTE_HC67,UDB Channel HC Tile Configuration; Horizontal Channel 67" group.byte 0x44++0x00 line.byte 0x00 "ROUTE_HC68,UDB Channel HC Tile Configuration; Horizontal Channel 68" group.byte 0x45++0x00 line.byte 0x00 "ROUTE_HC69,UDB Channel HC Tile Configuration; Horizontal Channel 69" group.byte 0x46++0x00 line.byte 0x00 "ROUTE_HC70,UDB Channel HC Tile Configuration; Horizontal Channel 70" group.byte 0x47++0x00 line.byte 0x00 "ROUTE_HC71,UDB Channel HC Tile Configuration; Horizontal Channel 71" group.byte 0x48++0x00 line.byte 0x00 "ROUTE_HC72,UDB Channel HC Tile Configuration; Horizontal Channel 72" group.byte 0x49++0x00 line.byte 0x00 "ROUTE_HC73,UDB Channel HC Tile Configuration; Horizontal Channel 73" group.byte 0x4A++0x00 line.byte 0x00 "ROUTE_HC74,UDB Channel HC Tile Configuration; Horizontal Channel 74" group.byte 0x4B++0x00 line.byte 0x00 "ROUTE_HC75,UDB Channel HC Tile Configuration; Horizontal Channel 75" group.byte 0x4C++0x00 line.byte 0x00 "ROUTE_HC76,UDB Channel HC Tile Configuration; Horizontal Channel 76" group.byte 0x4D++0x00 line.byte 0x00 "ROUTE_HC77,UDB Channel HC Tile Configuration; Horizontal Channel 77" group.byte 0x4E++0x00 line.byte 0x00 "ROUTE_HC78,UDB Channel HC Tile Configuration; Horizontal Channel 78" group.byte 0x4F++0x00 line.byte 0x00 "ROUTE_HC79,UDB Channel HC Tile Configuration; Horizontal Channel 79" group.byte 0x50++0x00 line.byte 0x00 "ROUTE_HC80,UDB Channel HC Tile Configuration; Horizontal Channel 80" group.byte 0x51++0x00 line.byte 0x00 "ROUTE_HC81,UDB Channel HC Tile Configuration; Horizontal Channel 81" group.byte 0x52++0x00 line.byte 0x00 "ROUTE_HC82,UDB Channel HC Tile Configuration; Horizontal Channel 82" group.byte 0x53++0x00 line.byte 0x00 "ROUTE_HC83,UDB Channel HC Tile Configuration; Horizontal Channel 83" group.byte 0x54++0x00 line.byte 0x00 "ROUTE_HC84,UDB Channel HC Tile Configuration; Horizontal Channel 84" group.byte 0x55++0x00 line.byte 0x00 "ROUTE_HC85,UDB Channel HC Tile Configuration; Horizontal Channel 85" group.byte 0x56++0x00 line.byte 0x00 "ROUTE_HC86,UDB Channel HC Tile Configuration; Horizontal Channel 86" group.byte 0x57++0x00 line.byte 0x00 "ROUTE_HC87,UDB Channel HC Tile Configuration; Horizontal Channel 87" group.byte 0x58++0x00 line.byte 0x00 "ROUTE_HC88,UDB Channel HC Tile Configuration; Horizontal Channel 88" group.byte 0x59++0x00 line.byte 0x00 "ROUTE_HC89,UDB Channel HC Tile Configuration; Horizontal Channel 89" group.byte 0x5A++0x00 line.byte 0x00 "ROUTE_HC90,UDB Channel HC Tile Configuration; Horizontal Channel 90" group.byte 0x5B++0x00 line.byte 0x00 "ROUTE_HC91,UDB Channel HC Tile Configuration; Horizontal Channel 91" group.byte 0x5C++0x00 line.byte 0x00 "ROUTE_HC92,UDB Channel HC Tile Configuration; Horizontal Channel 92" group.byte 0x5D++0x00 line.byte 0x00 "ROUTE_HC93,UDB Channel HC Tile Configuration; Horizontal Channel 93" group.byte 0x5E++0x00 line.byte 0x00 "ROUTE_HC94,UDB Channel HC Tile Configuration; Horizontal Channel 94" group.byte 0x5F++0x00 line.byte 0x00 "ROUTE_HC95,UDB Channel HC Tile Configuration; Horizontal Channel 95" group.byte 0x60++0x00 line.byte 0x00 "ROUTE_HC96,UDB Channel HC Tile Configuration; Horizontal Channel 96" group.byte 0x61++0x00 line.byte 0x00 "ROUTE_HC97,UDB Channel HC Tile Configuration; Horizontal Channel 97" group.byte 0x62++0x00 line.byte 0x00 "ROUTE_HC98,UDB Channel HC Tile Configuration; Horizontal Channel 98" group.byte 0x63++0x00 line.byte 0x00 "ROUTE_HC99,UDB Channel HC Tile Configuration; Horizontal Channel 99" group.byte 0x64++0x00 line.byte 0x00 "ROUTE_HC100,UDB Channel HC Tile Configuration; Horizontal Channel 100" group.byte 0x65++0x00 line.byte 0x00 "ROUTE_HC101,UDB Channel HC Tile Configuration; Horizontal Channel 101" group.byte 0x66++0x00 line.byte 0x00 "ROUTE_HC102,UDB Channel HC Tile Configuration; Horizontal Channel 102" group.byte 0x67++0x00 line.byte 0x00 "ROUTE_HC103,UDB Channel HC Tile Configuration; Horizontal Channel 103" group.byte 0x68++0x00 line.byte 0x00 "ROUTE_HC104,UDB Channel HC Tile Configuration; Horizontal Channel 104" group.byte 0x69++0x00 line.byte 0x00 "ROUTE_HC105,UDB Channel HC Tile Configuration; Horizontal Channel 105" group.byte 0x6A++0x00 line.byte 0x00 "ROUTE_HC106,UDB Channel HC Tile Configuration; Horizontal Channel 106" group.byte 0x6B++0x00 line.byte 0x00 "ROUTE_HC107,UDB Channel HC Tile Configuration; Horizontal Channel 107" group.byte 0x6C++0x00 line.byte 0x00 "ROUTE_HC108,UDB Channel HC Tile Configuration; Horizontal Channel 108" group.byte 0x6D++0x00 line.byte 0x00 "ROUTE_HC109,UDB Channel HC Tile Configuration; Horizontal Channel 109" group.byte 0x6E++0x00 line.byte 0x00 "ROUTE_HC110,UDB Channel HC Tile Configuration; Horizontal Channel 110" group.byte 0x6F++0x00 line.byte 0x00 "ROUTE_HC111,UDB Channel HC Tile Configuration; Horizontal Channel 111" group.byte 0x70++0x00 line.byte 0x00 "ROUTE_HC112,UDB Channel HC Tile Configuration; Horizontal Channel 112" group.byte 0x71++0x00 line.byte 0x00 "ROUTE_HC113,UDB Channel HC Tile Configuration; Horizontal Channel 113" group.byte 0x72++0x00 line.byte 0x00 "ROUTE_HC114,UDB Channel HC Tile Configuration; Horizontal Channel 114" group.byte 0x73++0x00 line.byte 0x00 "ROUTE_HC115,UDB Channel HC Tile Configuration; Horizontal Channel 115" group.byte 0x74++0x00 line.byte 0x00 "ROUTE_HC116,UDB Channel HC Tile Configuration; Horizontal Channel 116" group.byte 0x75++0x00 line.byte 0x00 "ROUTE_HC117,UDB Channel HC Tile Configuration; Horizontal Channel 117" group.byte 0x76++0x00 line.byte 0x00 "ROUTE_HC118,UDB Channel HC Tile Configuration; Horizontal Channel 118" group.byte 0x77++0x00 line.byte 0x00 "ROUTE_HC119,UDB Channel HC Tile Configuration; Horizontal Channel 119" group.byte 0x78++0x00 line.byte 0x00 "ROUTE_HC120,UDB Channel HC Tile Configuration; Horizontal Channel 120" group.byte 0x79++0x00 line.byte 0x00 "ROUTE_HC121,UDB Channel HC Tile Configuration; Horizontal Channel 121" group.byte 0x7A++0x00 line.byte 0x00 "ROUTE_HC122,UDB Channel HC Tile Configuration; Horizontal Channel 122" group.byte 0x7B++0x00 line.byte 0x00 "ROUTE_HC123,UDB Channel HC Tile Configuration; Horizontal Channel 123" group.byte 0x7C++0x00 line.byte 0x00 "ROUTE_HC124,UDB Channel HC Tile Configuration; Horizontal Channel 124" group.byte 0x7D++0x00 line.byte 0x00 "ROUTE_HC125,UDB Channel HC Tile Configuration; Horizontal Channel 125" group.byte 0x7E++0x00 line.byte 0x00 "ROUTE_HC126,UDB Channel HC Tile Configuration; Horizontal Channel 126" group.byte 0x7F++0x00 line.byte 0x00 "ROUTE_HC127,UDB Channel HC Tile Configuration; Horizontal Channel 127" group.byte 0x80++0x00 line.byte 0x00 "ROUTE_HV_L0,UDB Channel HV Tile Configuration; Left 0" group.byte 0x81++0x00 line.byte 0x00 "ROUTE_HV_L1,UDB Channel HV Tile Configuration; Left 1" group.byte 0x82++0x00 line.byte 0x00 "ROUTE_HV_L2,UDB Channel HV Tile Configuration; Left 2" group.byte 0x83++0x00 line.byte 0x00 "ROUTE_HV_L3,UDB Channel HV Tile Configuration; Left 3" group.byte 0x84++0x00 line.byte 0x00 "ROUTE_HV_L4,UDB Channel HV Tile Configuration; Left 4" group.byte 0x85++0x00 line.byte 0x00 "ROUTE_HV_L5,UDB Channel HV Tile Configuration; Left 5" group.byte 0x86++0x00 line.byte 0x00 "ROUTE_HV_L6,UDB Channel HV Tile Configuration; Left 6" group.byte 0x87++0x00 line.byte 0x00 "ROUTE_HV_L7,UDB Channel HV Tile Configuration; Left 7" group.byte 0x88++0x00 line.byte 0x00 "ROUTE_HV_L8,UDB Channel HV Tile Configuration; Left 8" group.byte 0x89++0x00 line.byte 0x00 "ROUTE_HV_L9,UDB Channel HV Tile Configuration; Left 9" group.byte 0x8A++0x00 line.byte 0x00 "ROUTE_HV_L10,UDB Channel HV Tile Configuration; Left 10" group.byte 0x8B++0x00 line.byte 0x00 "ROUTE_HV_L11,UDB Channel HV Tile Configuration; Left 11" group.byte 0x8C++0x00 line.byte 0x00 "ROUTE_HV_L12,UDB Channel HV Tile Configuration; Left 12" group.byte 0x8D++0x00 line.byte 0x00 "ROUTE_HV_L13,UDB Channel HV Tile Configuration; Left 13" group.byte 0x8E++0x00 line.byte 0x00 "ROUTE_HV_L14,UDB Channel HV Tile Configuration; Left 14" group.byte 0x8F++0x00 line.byte 0x00 "ROUTE_HV_L15,UDB Channel HV Tile Configuration; Left 15" group.byte 0x90++0x00 line.byte 0x00 "ROUTE_HS0,UDB Channel HS Tile Configuration; Horizontal Segmentation 0" group.byte 0x91++0x00 line.byte 0x00 "ROUTE_HS1,UDB Channel HS Tile Configuration; Horizontal Segmentation 1" group.byte 0x92++0x00 line.byte 0x00 "ROUTE_HS2,UDB Channel HS Tile Configuration; Horizontal Segmentation 2" group.byte 0x93++0x00 line.byte 0x00 "ROUTE_HS3,UDB Channel HS Tile Configuration; Horizontal Segmentation 3" group.byte 0x94++0x00 line.byte 0x00 "ROUTE_HS4,UDB Channel HS Tile Configuration; Horizontal Segmentation 4" group.byte 0x95++0x00 line.byte 0x00 "ROUTE_HS5,UDB Channel HS Tile Configuration; Horizontal Segmentation 5" group.byte 0x96++0x00 line.byte 0x00 "ROUTE_HS6,UDB Channel HS Tile Configuration; Horizontal Segmentation 6" group.byte 0x97++0x00 line.byte 0x00 "ROUTE_HS7,UDB Channel HS Tile Configuration; Horizontal Segmentation 7" group.byte 0x98++0x00 line.byte 0x00 "ROUTE_HS8,UDB Channel HS Tile Configuration; Horizontal Segmentation 8" group.byte 0x99++0x00 line.byte 0x00 "ROUTE_HS9,UDB Channel HS Tile Configuration; Horizontal Segmentation 9" group.byte 0x9A++0x00 line.byte 0x00 "ROUTE_HS10,UDB Channel HS Tile Configuration; Horizontal Segmentation 10" group.byte 0x9B++0x00 line.byte 0x00 "ROUTE_HS11,UDB Channel HS Tile Configuration; Horizontal Segmentation 11" group.byte 0x9C++0x00 line.byte 0x00 "ROUTE_HS12,UDB Channel HS Tile Configuration; Horizontal Segmentation 12" group.byte 0x9D++0x00 line.byte 0x00 "ROUTE_HS13,UDB Channel HS Tile Configuration; Horizontal Segmentation 13" group.byte 0x9E++0x00 line.byte 0x00 "ROUTE_HS14,UDB Channel HS Tile Configuration; Horizontal Segmentation 14" group.byte 0x9F++0x00 line.byte 0x00 "ROUTE_HS15,UDB Channel HS Tile Configuration; Horizontal Segmentation 15" group.byte 0xA0++0x00 line.byte 0x00 "ROUTE_HS16,UDB Channel HS Tile Configuration; Horizontal Segmentation 16" group.byte 0xA1++0x00 line.byte 0x00 "ROUTE_HS17,UDB Channel HS Tile Configuration; Horizontal Segmentation 17" group.byte 0xA2++0x00 line.byte 0x00 "ROUTE_HS18,UDB Channel HS Tile Configuration; Horizontal Segmentation 18" group.byte 0xA3++0x00 line.byte 0x00 "ROUTE_HS19,UDB Channel HS Tile Configuration; Horizontal Segmentation 19" group.byte 0xA4++0x00 line.byte 0x00 "ROUTE_HS20,UDB Channel HS Tile Configuration; Horizontal Segmentation 20" group.byte 0xA5++0x00 line.byte 0x00 "ROUTE_HS21,UDB Channel HS Tile Configuration; Horizontal Segmentation 21" group.byte 0xA6++0x00 line.byte 0x00 "ROUTE_HS22,UDB Channel HS Tile Configuration; Horizontal Segmentation 22" group.byte 0xA7++0x00 line.byte 0x00 "ROUTE_HS23,UDB Channel HS Tile Configuration; Horizontal Segmentation 23" group.byte 0xA8++0x00 line.byte 0x00 "ROUTE_HV_R0,UDB Channel HV Tile Configuration; Right 0" group.byte 0xA9++0x00 line.byte 0x00 "ROUTE_HV_R1,UDB Channel HV Tile Configuration; Right 1" group.byte 0xAA++0x00 line.byte 0x00 "ROUTE_HV_R2,UDB Channel HV Tile Configuration; Right 2" group.byte 0xAB++0x00 line.byte 0x00 "ROUTE_HV_R3,UDB Channel HV Tile Configuration; Right 3" group.byte 0xAC++0x00 line.byte 0x00 "ROUTE_HV_R4,UDB Channel HV Tile Configuration; Right 4" group.byte 0xAD++0x00 line.byte 0x00 "ROUTE_HV_R5,UDB Channel HV Tile Configuration; Right 5" group.byte 0xAE++0x00 line.byte 0x00 "ROUTE_HV_R6,UDB Channel HV Tile Configuration; Right 6" group.byte 0xAF++0x00 line.byte 0x00 "ROUTE_HV_R7,UDB Channel HV Tile Configuration; Right 7" group.byte 0xB0++0x00 line.byte 0x00 "ROUTE_HV_R8,UDB Channel HV Tile Configuration; Right 8" group.byte 0xB1++0x00 line.byte 0x00 "ROUTE_HV_R9,UDB Channel HV Tile Configuration; Right 9" group.byte 0xB2++0x00 line.byte 0x00 "ROUTE_HV_R10,UDB Channel HV Tile Configuration; Right 10" group.byte 0xB3++0x00 line.byte 0x00 "ROUTE_HV_R11,UDB Channel HV Tile Configuration; Right 11" group.byte 0xB4++0x00 line.byte 0x00 "ROUTE_HV_R12,UDB Channel HV Tile Configuration; Right 12" group.byte 0xB5++0x00 line.byte 0x00 "ROUTE_HV_R13,UDB Channel HV Tile Configuration; Right 13" group.byte 0xB6++0x00 line.byte 0x00 "ROUTE_HV_R14,UDB Channel HV Tile Configuration; Right 14" group.byte 0xB7++0x00 line.byte 0x00 "ROUTE_HV_R15,UDB Channel HV Tile Configuration; Right 15" group.word 0xC0++0x01 line.word 0x00 "ROUTE_PLD0IN0,UDB Channel PI Tile Configuration; PLD Input 0" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xC2++0x01 line.word 0x00 "ROUTE_PLD0IN1,UDB Channel PI Tile Configuration; PLD Input 1" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xC4++0x01 line.word 0x00 "ROUTE_PLD0IN2,UDB Channel PI Tile Configuration; PLD Input 2" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xCA++0x01 line.word 0x00 "ROUTE_PLD1IN0,UDB Channel PI Tile Configuration; PLD Input 0" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xCC++0x01 line.word 0x00 "ROUTE_PLD1IN1,UDB Channel PI Tile Configuration; PLD Input 1" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xCE++0x01 line.word 0x00 "ROUTE_PLD1IN2,UDB Channel PI Tile Configuration; PLD Input 2" bitfld.word 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xD0++0x00 line.byte 0x00 "ROUTE_DPIN0,UDB Channel PI Tile Configuration; Datapath Input 0" bitfld.byte 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xD2++0x00 line.byte 0x00 "ROUTE_DPIN1,UDB Channel PI Tile Configuration; Datapath Input 1" bitfld.byte 0x00 4.--5. " PI_BOT2 ,RAM configuration bits (2) for BOTTOM UDB port interface configuration" "0,1,2,3" bitfld.byte 0x00 2.--3. " PI_TOP2 ,RAM configuration bits (2) for TOP UDB port interface configuration" "0,1,2,3" group.byte 0xD6++0x00 line.byte 0x00 "ROUTE_SCIN,UDB Channel PI Tile Configuration; Status / Control Blocks Input Control" bitfld.byte 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xD8++0x00 line.byte 0x00 "ROUTE_SCIOIN,UDB Channel PI Tile Configuration; Status / Control Blocks Input / Output Control" bitfld.byte 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.byte 0xDE++0x00 line.byte 0x00 "ROUTE_RCIN,UDB Channel PI Tile Configuration; Reset And Clock Blocks Input Control" bitfld.byte 0x00 4.--7. " PI_BOT ,RAM configuration nibble for BOTTOM UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " PI_TOP ,RAM configuration nibble for TOP UDB port interface configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE0++0x01 line.word 0x00 "ROUTE_VS0,UDB Channel VS Tile Configuration; Vertical Segmentation 0" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration nibble for BOTTOM UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration nibble for TOP UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE2++0x01 line.word 0x00 "ROUTE_VS1,UDB Channel VS Tile Configuration; Vertical Segmentation 1" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration nibble for BOTTOM UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration nibble for TOP UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE4++0x01 line.word 0x00 "ROUTE_VS2,UDB Channel VS Tile Configuration; Vertical Segmentation 2" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration nibble for BOTTOM UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration nibble for TOP UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE6++0x01 line.word 0x00 "ROUTE_VS3,UDB Channel VS Tile Configuration; Vertical Segmentation 3" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration nibble for BOTTOM UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration nibble for TOP UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xE8++0x01 line.word 0x00 "ROUTE_VS4,UDB Channel VS Tile Configuration; Vertical Segmentation 4" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration nibble for BOTTOM UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration nibble for TOP UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xEA++0x01 line.word 0x00 "ROUTE_VS5,UDB Channel VS Tile Configuration; Vertical Segmentation 5" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration nibble for BOTTOM UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration nibble for TOP UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xEC++0x01 line.word 0x00 "ROUTE_VS6,UDB Channel VS Tile Configuration; Vertical Segmentation 6" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration nibble for BOTTOM UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration nibble for TOP UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.word 0xEE++0x01 line.word 0x00 "ROUTE_VS7,UDB Channel VS Tile Configuration; Vertical Segmentation 7" bitfld.word 0x00 4.--7. " VS_BOT ,RAM configuration nibble for BOTTOM UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " VS_TOP ,RAM configuration nibble for TOP UDB vertical segmentation configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree.end tree "UDB 8-bit Working registers" base ad:0x400F0000 width 15. group.byte 0x0++0x00 line.byte 0x00 "UDB_W8_A00,Accumulator 0" group.byte 0x1++0x00 line.byte 0x00 "UDB_W8_A01,Accumulator 0" group.byte 0x2++0x00 line.byte 0x00 "UDB_W8_A02,Accumulator 0" group.byte 0x3++0x00 line.byte 0x00 "UDB_W8_A03,Accumulator 0" group.byte 0x4++0x00 line.byte 0x00 "UDB_W8_A04,Accumulator 0" group.byte 0x5++0x00 line.byte 0x00 "UDB_W8_A05,Accumulator 0" group.byte 0x6++0x00 line.byte 0x00 "UDB_W8_A06,Accumulator 0" group.byte 0x7++0x00 line.byte 0x00 "UDB_W8_A07,Accumulator 0" group.byte 0x10++0x00 line.byte 0x00 "UDB_W8_A10,Accumulator 1" group.byte 0x11++0x00 line.byte 0x00 "UDB_W8_A11,Accumulator 1" group.byte 0x12++0x00 line.byte 0x00 "UDB_W8_A12,Accumulator 1" group.byte 0x13++0x00 line.byte 0x00 "UDB_W8_A13,Accumulator 1" group.byte 0x14++0x00 line.byte 0x00 "UDB_W8_A14,Accumulator 1" group.byte 0x15++0x00 line.byte 0x00 "UDB_W8_A15,Accumulator 1" group.byte 0x16++0x00 line.byte 0x00 "UDB_W8_A16,Accumulator 1" group.byte 0x17++0x00 line.byte 0x00 "UDB_W8_A17,Accumulator 1" group.byte 0x20++0x00 line.byte 0x00 "UDB_W8_D00,Data 0" group.byte 0x21++0x00 line.byte 0x00 "UDB_W8_D01,Data 0" group.byte 0x22++0x00 line.byte 0x00 "UDB_W8_D02,Data 0" group.byte 0x23++0x00 line.byte 0x00 "UDB_W8_D03,Data 0" group.byte 0x24++0x00 line.byte 0x00 "UDB_W8_D04,Data 0" group.byte 0x25++0x00 line.byte 0x00 "UDB_W8_D05,Data 0" group.byte 0x26++0x00 line.byte 0x00 "UDB_W8_D06,Data 0" group.byte 0x27++0x00 line.byte 0x00 "UDB_W8_D07,Data 0" group.byte 0x30++0x00 line.byte 0x00 "UDB_W8_D10,Data 1" group.byte 0x31++0x00 line.byte 0x00 "UDB_W8_D11,Data 1" group.byte 0x32++0x00 line.byte 0x00 "UDB_W8_D12,Data 1" group.byte 0x33++0x00 line.byte 0x00 "UDB_W8_D13,Data 1" group.byte 0x34++0x00 line.byte 0x00 "UDB_W8_D14,Data 1" group.byte 0x35++0x00 line.byte 0x00 "UDB_W8_D15,Data 1" group.byte 0x36++0x00 line.byte 0x00 "UDB_W8_D16,Data 1" group.byte 0x37++0x00 line.byte 0x00 "UDB_W8_D17,Data 1" group.byte 0x40++0x00 line.byte 0x00 "UDB_W8_F00,Fifo 0" group.byte 0x41++0x00 line.byte 0x00 "UDB_W8_F01,Fifo 0" group.byte 0x42++0x00 line.byte 0x00 "UDB_W8_F02,Fifo 0" group.byte 0x43++0x00 line.byte 0x00 "UDB_W8_F03,Fifo 0" group.byte 0x44++0x00 line.byte 0x00 "UDB_W8_F04,Fifo 0" group.byte 0x45++0x00 line.byte 0x00 "UDB_W8_F05,Fifo 0" group.byte 0x46++0x00 line.byte 0x00 "UDB_W8_F06,Fifo 0" group.byte 0x47++0x00 line.byte 0x00 "UDB_W8_F07,Fifo 0" group.byte 0x50++0x00 line.byte 0x00 "UDB_W8_F10,Fifo 1" group.byte 0x51++0x00 line.byte 0x00 "UDB_W8_F11,Fifo 1" group.byte 0x52++0x00 line.byte 0x00 "UDB_W8_F12,Fifo 1" group.byte 0x53++0x00 line.byte 0x00 "UDB_W8_F13,Fifo 1" group.byte 0x54++0x00 line.byte 0x00 "UDB_W8_F14,Fifo 1" group.byte 0x55++0x00 line.byte 0x00 "UDB_W8_F15,Fifo 1" group.byte 0x56++0x00 line.byte 0x00 "UDB_W8_F16,Fifo 1" group.byte 0x57++0x00 line.byte 0x00 "UDB_W8_F17,Fifo 1" rgroup.byte 0x60++0x00 line.byte 0x00 "UDB_W8_ST0,Status Register 0" rgroup.byte 0x61++0x00 line.byte 0x00 "UDB_W8_ST1,Status Register 1" rgroup.byte 0x62++0x00 line.byte 0x00 "UDB_W8_ST2,Status Register 2" rgroup.byte 0x63++0x00 line.byte 0x00 "UDB_W8_ST3,Status Register 3" rgroup.byte 0x64++0x00 line.byte 0x00 "UDB_W8_ST4,Status Register 4" rgroup.byte 0x65++0x00 line.byte 0x00 "UDB_W8_ST5,Status Register 5" rgroup.byte 0x66++0x00 line.byte 0x00 "UDB_W8_ST6,Status Register 6" rgroup.byte 0x67++0x00 line.byte 0x00 "UDB_W8_ST7,Status Register 7" group.byte 0x70++0x00 line.byte 0x00 "UDB_W8_CTL0,Control Register 0" group.byte 0x71++0x00 line.byte 0x00 "UDB_W8_CTL1,Control Register 1" group.byte 0x72++0x00 line.byte 0x00 "UDB_W8_CTL2,Control Register 2" group.byte 0x73++0x00 line.byte 0x00 "UDB_W8_CTL3,Control Register 3" group.byte 0x74++0x00 line.byte 0x00 "UDB_W8_CTL4,Control Register 4" group.byte 0x75++0x00 line.byte 0x00 "UDB_W8_CTL5,Control Register 5" group.byte 0x76++0x00 line.byte 0x00 "UDB_W8_CTL6,Control Register 6" group.byte 0x77++0x00 line.byte 0x00 "UDB_W8_CTL7,Control Register 7" group.byte 0x80++0x00 line.byte 0x00 "UDB_W8_MSK0,Interrupt Mask 0" group.byte 0x81++0x00 line.byte 0x00 "UDB_W8_MSK1,Interrupt Mask 1" group.byte 0x82++0x00 line.byte 0x00 "UDB_W8_MSK2,Interrupt Mask 2" group.byte 0x83++0x00 line.byte 0x00 "UDB_W8_MSK3,Interrupt Mask 3" group.byte 0x84++0x00 line.byte 0x00 "UDB_W8_MSK4,Interrupt Mask 4" group.byte 0x85++0x00 line.byte 0x00 "UDB_W8_MSK5,Interrupt Mask 5" group.byte 0x86++0x00 line.byte 0x00 "UDB_W8_MSK6,Interrupt Mask 6" group.byte 0x87++0x00 line.byte 0x00 "UDB_W8_MSK7,Interrupt Mask 7" group.byte 0x90++0x00 line.byte 0x00 "UDB_W8_ACTL0,Auxiliary Control 0" bitfld.byte 0x00 5. " CNT_START ,Control register counter enable" "Disabled,Enabled" bitfld.byte 0x00 4. " INT_EN ,Enable interrupt" "Disabled,Enabled" bitfld.byte 0x00 3. " FIFO1_LVL ,FIFO 1 fill status level control" "Normal,Mid" bitfld.byte 0x00 2. " FIFO0_LVL ,FIFO 0 fill status level control" "Normal,Mid" textline " " bitfld.byte 0x00 1. " FIFO1_CLR ,FIFO 1 clear" "Normal,Clear" bitfld.byte 0x00 0. " FIFO0_CLR ,FIFO 0 clear" "Normal,Clear" group.byte 0x91++0x00 line.byte 0x00 "UDB_W8_ACTL1,Auxiliary Control 1" bitfld.byte 0x00 5. " CNT_START ,Control register counter enable" "Disabled,Enabled" bitfld.byte 0x00 4. " INT_EN ,Enable interrupt" "Disabled,Enabled" bitfld.byte 0x00 3. " FIFO1_LVL ,FIFO 1 fill status level control" "Normal,Mid" bitfld.byte 0x00 2. " FIFO0_LVL ,FIFO 0 fill status level control" "Normal,Mid" textline " " bitfld.byte 0x00 1. " FIFO1_CLR ,FIFO 1 clear" "Normal,Clear" bitfld.byte 0x00 0. " FIFO0_CLR ,FIFO 0 clear" "Normal,Clear" group.byte 0x92++0x00 line.byte 0x00 "UDB_W8_ACTL2,Auxiliary Control 2" bitfld.byte 0x00 5. " CNT_START ,Control register counter enable" "Disabled,Enabled" bitfld.byte 0x00 4. " INT_EN ,Enable interrupt" "Disabled,Enabled" bitfld.byte 0x00 3. " FIFO1_LVL ,FIFO 1 fill status level control" "Normal,Mid" bitfld.byte 0x00 2. " FIFO0_LVL ,FIFO 0 fill status level control" "Normal,Mid" textline " " bitfld.byte 0x00 1. " FIFO1_CLR ,FIFO 1 clear" "Normal,Clear" bitfld.byte 0x00 0. " FIFO0_CLR ,FIFO 0 clear" "Normal,Clear" group.byte 0x93++0x00 line.byte 0x00 "UDB_W8_ACTL3,Auxiliary Control 3" bitfld.byte 0x00 5. " CNT_START ,Control register counter enable" "Disabled,Enabled" bitfld.byte 0x00 4. " INT_EN ,Enable interrupt" "Disabled,Enabled" bitfld.byte 0x00 3. " FIFO1_LVL ,FIFO 1 fill status level control" "Normal,Mid" bitfld.byte 0x00 2. " FIFO0_LVL ,FIFO 0 fill status level control" "Normal,Mid" textline " " bitfld.byte 0x00 1. " FIFO1_CLR ,FIFO 1 clear" "Normal,Clear" bitfld.byte 0x00 0. " FIFO0_CLR ,FIFO 0 clear" "Normal,Clear" group.byte 0x94++0x00 line.byte 0x00 "UDB_W8_ACTL4,Auxiliary Control 4" bitfld.byte 0x00 5. " CNT_START ,Control register counter enable" "Disabled,Enabled" bitfld.byte 0x00 4. " INT_EN ,Enable interrupt" "Disabled,Enabled" bitfld.byte 0x00 3. " FIFO1_LVL ,FIFO 1 fill status level control" "Normal,Mid" bitfld.byte 0x00 2. " FIFO0_LVL ,FIFO 0 fill status level control" "Normal,Mid" textline " " bitfld.byte 0x00 1. " FIFO1_CLR ,FIFO 1 clear" "Normal,Clear" bitfld.byte 0x00 0. " FIFO0_CLR ,FIFO 0 clear" "Normal,Clear" group.byte 0x95++0x00 line.byte 0x00 "UDB_W8_ACTL5,Auxiliary Control 5" bitfld.byte 0x00 5. " CNT_START ,Control register counter enable" "Disabled,Enabled" bitfld.byte 0x00 4. " INT_EN ,Enable interrupt" "Disabled,Enabled" bitfld.byte 0x00 3. " FIFO1_LVL ,FIFO 1 fill status level control" "Normal,Mid" bitfld.byte 0x00 2. " FIFO0_LVL ,FIFO 0 fill status level control" "Normal,Mid" textline " " bitfld.byte 0x00 1. " FIFO1_CLR ,FIFO 1 clear" "Normal,Clear" bitfld.byte 0x00 0. " FIFO0_CLR ,FIFO 0 clear" "Normal,Clear" group.byte 0x96++0x00 line.byte 0x00 "UDB_W8_ACTL6,Auxiliary Control 6" bitfld.byte 0x00 5. " CNT_START ,Control register counter enable" "Disabled,Enabled" bitfld.byte 0x00 4. " INT_EN ,Enable interrupt" "Disabled,Enabled" bitfld.byte 0x00 3. " FIFO1_LVL ,FIFO 1 fill status level control" "Normal,Mid" bitfld.byte 0x00 2. " FIFO0_LVL ,FIFO 0 fill status level control" "Normal,Mid" textline " " bitfld.byte 0x00 1. " FIFO1_CLR ,FIFO 1 clear" "Normal,Clear" bitfld.byte 0x00 0. " FIFO0_CLR ,FIFO 0 clear" "Normal,Clear" group.byte 0x97++0x00 line.byte 0x00 "UDB_W8_ACTL7,Auxiliary Control 7" bitfld.byte 0x00 5. " CNT_START ,Control register counter enable" "Disabled,Enabled" bitfld.byte 0x00 4. " INT_EN ,Enable interrupt" "Disabled,Enabled" bitfld.byte 0x00 3. " FIFO1_LVL ,FIFO 1 fill status level control" "Normal,Mid" bitfld.byte 0x00 2. " FIFO0_LVL ,FIFO 0 fill status level control" "Normal,Mid" textline " " bitfld.byte 0x00 1. " FIFO1_CLR ,FIFO 1 clear" "Normal,Clear" bitfld.byte 0x00 0. " FIFO0_CLR ,FIFO 0 clear" "Normal,Clear" rgroup.byte 0xA0++0x00 line.byte 0x00 "UDB_W8_MC0,PLD Macrocell Reading 0" bitfld.byte 0x00 4.--7. " PLD1_MC ,Read macrocell 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " PLD0_MC ,Read macrocell 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.byte 0xA1++0x00 line.byte 0x00 "UDB_W8_MC1,PLD Macrocell Reading 1" bitfld.byte 0x00 4.--7. " PLD1_MC ,Read macrocell 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " PLD0_MC ,Read macrocell 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.byte 0xA2++0x00 line.byte 0x00 "UDB_W8_MC2,PLD Macrocell Reading 2" bitfld.byte 0x00 4.--7. " PLD1_MC ,Read macrocell 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " PLD0_MC ,Read macrocell 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.byte 0xA3++0x00 line.byte 0x00 "UDB_W8_MC3,PLD Macrocell Reading 3" bitfld.byte 0x00 4.--7. " PLD1_MC ,Read macrocell 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " PLD0_MC ,Read macrocell 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.byte 0xA4++0x00 line.byte 0x00 "UDB_W8_MC4,PLD Macrocell Reading 4" bitfld.byte 0x00 4.--7. " PLD1_MC ,Read macrocell 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " PLD0_MC ,Read macrocell 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.byte 0xA5++0x00 line.byte 0x00 "UDB_W8_MC5,PLD Macrocell Reading 5" bitfld.byte 0x00 4.--7. " PLD1_MC ,Read macrocell 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " PLD0_MC ,Read macrocell 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.byte 0xA6++0x00 line.byte 0x00 "UDB_W8_MC6,PLD Macrocell Reading 6" bitfld.byte 0x00 4.--7. " PLD1_MC ,Read macrocell 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " PLD0_MC ,Read macrocell 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.byte 0xA7++0x00 line.byte 0x00 "UDB_W8_MC7,PLD Macrocell Reading 7" bitfld.byte 0x00 4.--7. " PLD1_MC ,Read macrocell 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " PLD0_MC ,Read macrocell 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree "UDB 16-bit Concatenated Working registers" base ad:0x400F1000 width 22. group.word 0x0++0x01 line.word 0x00 "UDB_CAT16_A0,Accumulator Registers (A1,A0)" hexmask.word.byte 0x00 8.--15. 1. " A1 ,Accumulator 1 register" hexmask.word.byte 0x00 0.--7. 1. " A0 ,Accumulator 0 register" group.word 0x2++0x01 line.word 0x00 "UDB_CAT16_A1,Accumulator Registers (A1,A0)" hexmask.word.byte 0x00 8.--15. 1. " A1 ,Accumulator 1 register" hexmask.word.byte 0x00 0.--7. 1. " A0 ,Accumulator 0 register" group.word 0x4++0x01 line.word 0x00 "UDB_CAT16_A2,Accumulator Registers (A1,A0)" hexmask.word.byte 0x00 8.--15. 1. " A1 ,Accumulator 1 register" hexmask.word.byte 0x00 0.--7. 1. " A0 ,Accumulator 0 register" group.word 0x6++0x01 line.word 0x00 "UDB_CAT16_A3,Accumulator Registers (A1,A0)" hexmask.word.byte 0x00 8.--15. 1. " A1 ,Accumulator 1 register" hexmask.word.byte 0x00 0.--7. 1. " A0 ,Accumulator 0 register" group.word 0x8++0x01 line.word 0x00 "UDB_CAT16_A4,Accumulator Registers (A1,A0)" hexmask.word.byte 0x00 8.--15. 1. " A1 ,Accumulator 1 register" hexmask.word.byte 0x00 0.--7. 1. " A0 ,Accumulator 0 register" group.word 0xA++0x01 line.word 0x00 "UDB_CAT16_A5,Accumulator Registers (A1,A0)" hexmask.word.byte 0x00 8.--15. 1. " A1 ,Accumulator 1 register" hexmask.word.byte 0x00 0.--7. 1. " A0 ,Accumulator 0 register" group.word 0xC++0x01 line.word 0x00 "UDB_CAT16_A6,Accumulator Registers (A1,A0)" hexmask.word.byte 0x00 8.--15. 1. " A1 ,Accumulator 1 register" hexmask.word.byte 0x00 0.--7. 1. " A0 ,Accumulator 0 register" group.word 0xE++0x01 line.word 0x00 "UDB_CAT16_A7,Accumulator Registers (A1,A0)" hexmask.word.byte 0x00 8.--15. 1. " A1 ,Accumulator 1 register" hexmask.word.byte 0x00 0.--7. 1. " A0 ,Accumulator 0 register" group.word 0x40++0x01 line.word 0x00 "UDB_CAT16_D0,Data Registers (D1,D0)" hexmask.word.byte 0x00 8.--15. 1. " D1 ,Data 1 register" hexmask.word.byte 0x00 0.--7. 1. " D0 ,Data 0 register" group.word 0x42++0x01 line.word 0x00 "UDB_CAT16_D1,Data Registers (D1,D0)" hexmask.word.byte 0x00 8.--15. 1. " D1 ,Data 1 register" hexmask.word.byte 0x00 0.--7. 1. " D0 ,Data 0 register" group.word 0x44++0x01 line.word 0x00 "UDB_CAT16_D2,Data Registers (D1,D0)" hexmask.word.byte 0x00 8.--15. 1. " D1 ,Data 1 register" hexmask.word.byte 0x00 0.--7. 1. " D0 ,Data 0 register" group.word 0x46++0x01 line.word 0x00 "UDB_CAT16_D3,Data Registers (D1,D0)" hexmask.word.byte 0x00 8.--15. 1. " D1 ,Data 1 register" hexmask.word.byte 0x00 0.--7. 1. " D0 ,Data 0 register" group.word 0x48++0x01 line.word 0x00 "UDB_CAT16_D4,Data Registers (D1,D0)" hexmask.word.byte 0x00 8.--15. 1. " D1 ,Data 1 register" hexmask.word.byte 0x00 0.--7. 1. " D0 ,Data 0 register" group.word 0x4A++0x01 line.word 0x00 "UDB_CAT16_D5,Data Registers (D1,D0)" hexmask.word.byte 0x00 8.--15. 1. " D1 ,Data 1 register" hexmask.word.byte 0x00 0.--7. 1. " D0 ,Data 0 register" group.word 0x4C++0x01 line.word 0x00 "UDB_CAT16_D6,Data Registers (D1,D0)" hexmask.word.byte 0x00 8.--15. 1. " D1 ,Data 1 register" hexmask.word.byte 0x00 0.--7. 1. " D0 ,Data 0 register" group.word 0x4E++0x01 line.word 0x00 "UDB_CAT16_D7,Data Registers (D1,D0)" hexmask.word.byte 0x00 8.--15. 1. " D1 ,Data 1 register" hexmask.word.byte 0x00 0.--7. 1. " D0 ,Data 0 register" group.word 0x80++0x01 line.word 0x00 "UDB_CAT16_F0,Fifos (F1,F0)" hexmask.word.byte 0x00 8.--15. 1. " F1 ,FIFO 1" hexmask.word.byte 0x00 0.--7. 1. " F0 ,FIFO 0" group.word 0x82++0x01 line.word 0x00 "UDB_CAT16_F1,Fifos (F1,F0)" hexmask.word.byte 0x00 8.--15. 1. " F1 ,FIFO 1" hexmask.word.byte 0x00 0.--7. 1. " F0 ,FIFO 0" group.word 0x84++0x01 line.word 0x00 "UDB_CAT16_F2,Fifos (F1,F0)" hexmask.word.byte 0x00 8.--15. 1. " F1 ,FIFO 1" hexmask.word.byte 0x00 0.--7. 1. " F0 ,FIFO 0" group.word 0x86++0x01 line.word 0x00 "UDB_CAT16_F3,Fifos (F1,F0)" hexmask.word.byte 0x00 8.--15. 1. " F1 ,FIFO 1" hexmask.word.byte 0x00 0.--7. 1. " F0 ,FIFO 0" group.word 0x88++0x01 line.word 0x00 "UDB_CAT16_F4,Fifos (F1,F0)" hexmask.word.byte 0x00 8.--15. 1. " F1 ,FIFO 1" hexmask.word.byte 0x00 0.--7. 1. " F0 ,FIFO 0" group.word 0x8A++0x01 line.word 0x00 "UDB_CAT16_F5,Fifos (F1,F0)" hexmask.word.byte 0x00 8.--15. 1. " F1 ,FIFO 1" hexmask.word.byte 0x00 0.--7. 1. " F0 ,FIFO 0" group.word 0x8C++0x01 line.word 0x00 "UDB_CAT16_F6,Fifos (F1,F0)" hexmask.word.byte 0x00 8.--15. 1. " F1 ,FIFO 1" hexmask.word.byte 0x00 0.--7. 1. " F0 ,FIFO 0" group.word 0x8E++0x01 line.word 0x00 "UDB_CAT16_F7,Fifos (F1,F0)" hexmask.word.byte 0x00 8.--15. 1. " F1 ,FIFO 1" hexmask.word.byte 0x00 0.--7. 1. " F0 ,FIFO 0" rgroup.word 0xC0++0x01 line.word 0x00 "UDB_CAT16_CTL_ST0,Status And Control Registers (CTL,ST)" hexmask.word.byte 0x00 8.--15. 1. " CTL ,Control register" hexmask.word.byte 0x00 0.--7. 1. " ST ,Status register" rgroup.word 0xC2++0x01 line.word 0x00 "UDB_CAT16_CTL_ST1,Status And Control Registers (CTL,ST)" hexmask.word.byte 0x00 8.--15. 1. " CTL ,Control register" hexmask.word.byte 0x00 0.--7. 1. " ST ,Status register" rgroup.word 0xC4++0x01 line.word 0x00 "UDB_CAT16_CTL_ST2,Status And Control Registers (CTL,ST)" hexmask.word.byte 0x00 8.--15. 1. " CTL ,Control register" hexmask.word.byte 0x00 0.--7. 1. " ST ,Status register" rgroup.word 0xC6++0x01 line.word 0x00 "UDB_CAT16_CTL_ST3,Status And Control Registers (CTL,ST)" hexmask.word.byte 0x00 8.--15. 1. " CTL ,Control register" hexmask.word.byte 0x00 0.--7. 1. " ST ,Status register" rgroup.word 0xC8++0x01 line.word 0x00 "UDB_CAT16_CTL_ST4,Status And Control Registers (CTL,ST)" hexmask.word.byte 0x00 8.--15. 1. " CTL ,Control register" hexmask.word.byte 0x00 0.--7. 1. " ST ,Status register" rgroup.word 0xCA++0x01 line.word 0x00 "UDB_CAT16_CTL_ST5,Status And Control Registers (CTL,ST)" hexmask.word.byte 0x00 8.--15. 1. " CTL ,Control register" hexmask.word.byte 0x00 0.--7. 1. " ST ,Status register" rgroup.word 0xCC++0x01 line.word 0x00 "UDB_CAT16_CTL_ST6,Status And Control Registers (CTL,ST)" hexmask.word.byte 0x00 8.--15. 1. " CTL ,Control register" hexmask.word.byte 0x00 0.--7. 1. " ST ,Status register" rgroup.word 0xCE++0x01 line.word 0x00 "UDB_CAT16_CTL_ST7,Status And Control Registers (CTL,ST)" hexmask.word.byte 0x00 8.--15. 1. " CTL ,Control register" hexmask.word.byte 0x00 0.--7. 1. " ST ,Status register" group.word 0x100++0x01 line.word 0x00 "UDB_CAT16_ACTL_MSK0,Mask And Auxiliary Control Registers (ACTL,MSK)" bitfld.word 0x00 13. " CNT_START ,Control register counter enable" "Disabled,Enabled" bitfld.word 0x00 12. " INT_EN ,Enable interrupt" "Disabled,Enabled" bitfld.word 0x00 11. " FIFO1_LVL ,FIFO 1 fill status level control" "Normal,Mid" bitfld.word 0x00 10. " FIFO0_LVL ,FIFO 0 fill status level control" "Normal,Mid" textline " " bitfld.word 0x00 9. " FIFO1_CLR ,FIFO 1 clear" "Normal,Clear" bitfld.word 0x00 8. " FIFO0_CLR ,FIFO 0 clear" "Normal,Clear" hexmask.word.byte 0x00 0.--7. 1. " MSK ,Interrupt mask register" group.word 0x102++0x01 line.word 0x00 "UDB_CAT16_ACTL_MSK1,Mask And Auxiliary Control Registers (ACTL,MSK)" bitfld.word 0x00 13. " CNT_START ,Control register counter enable" "Disabled,Enabled" bitfld.word 0x00 12. " INT_EN ,Enable interrupt" "Disabled,Enabled" bitfld.word 0x00 11. " FIFO1_LVL ,FIFO 1 fill status level control" "Normal,Mid" bitfld.word 0x00 10. " FIFO0_LVL ,FIFO 0 fill status level control" "Normal,Mid" textline " " bitfld.word 0x00 9. " FIFO1_CLR ,FIFO 1 clear" "Normal,Clear" bitfld.word 0x00 8. " FIFO0_CLR ,FIFO 0 clear" "Normal,Clear" hexmask.word.byte 0x00 0.--7. 1. " MSK ,Interrupt mask register" group.word 0x104++0x01 line.word 0x00 "UDB_CAT16_ACTL_MSK2,Mask And Auxiliary Control Registers (ACTL,MSK)" bitfld.word 0x00 13. " CNT_START ,Control register counter enable" "Disabled,Enabled" bitfld.word 0x00 12. " INT_EN ,Enable interrupt" "Disabled,Enabled" bitfld.word 0x00 11. " FIFO1_LVL ,FIFO 1 fill status level control" "Normal,Mid" bitfld.word 0x00 10. " FIFO0_LVL ,FIFO 0 fill status level control" "Normal,Mid" textline " " bitfld.word 0x00 9. " FIFO1_CLR ,FIFO 1 clear" "Normal,Clear" bitfld.word 0x00 8. " FIFO0_CLR ,FIFO 0 clear" "Normal,Clear" hexmask.word.byte 0x00 0.--7. 1. " MSK ,Interrupt mask register" group.word 0x106++0x01 line.word 0x00 "UDB_CAT16_ACTL_MSK3,Mask And Auxiliary Control Registers (ACTL,MSK)" bitfld.word 0x00 13. " CNT_START ,Control register counter enable" "Disabled,Enabled" bitfld.word 0x00 12. " INT_EN ,Enable interrupt" "Disabled,Enabled" bitfld.word 0x00 11. " FIFO1_LVL ,FIFO 1 fill status level control" "Normal,Mid" bitfld.word 0x00 10. " FIFO0_LVL ,FIFO 0 fill status level control" "Normal,Mid" textline " " bitfld.word 0x00 9. " FIFO1_CLR ,FIFO 1 clear" "Normal,Clear" bitfld.word 0x00 8. " FIFO0_CLR ,FIFO 0 clear" "Normal,Clear" hexmask.word.byte 0x00 0.--7. 1. " MSK ,Interrupt mask register" group.word 0x108++0x01 line.word 0x00 "UDB_CAT16_ACTL_MSK4,Mask And Auxiliary Control Registers (ACTL,MSK)" bitfld.word 0x00 13. " CNT_START ,Control register counter enable" "Disabled,Enabled" bitfld.word 0x00 12. " INT_EN ,Enable interrupt" "Disabled,Enabled" bitfld.word 0x00 11. " FIFO1_LVL ,FIFO 1 fill status level control" "Normal,Mid" bitfld.word 0x00 10. " FIFO0_LVL ,FIFO 0 fill status level control" "Normal,Mid" textline " " bitfld.word 0x00 9. " FIFO1_CLR ,FIFO 1 clear" "Normal,Clear" bitfld.word 0x00 8. " FIFO0_CLR ,FIFO 0 clear" "Normal,Clear" hexmask.word.byte 0x00 0.--7. 1. " MSK ,Interrupt mask register" group.word 0x10A++0x01 line.word 0x00 "UDB_CAT16_ACTL_MSK5,Mask And Auxiliary Control Registers (ACTL,MSK)" bitfld.word 0x00 13. " CNT_START ,Control register counter enable" "Disabled,Enabled" bitfld.word 0x00 12. " INT_EN ,Enable interrupt" "Disabled,Enabled" bitfld.word 0x00 11. " FIFO1_LVL ,FIFO 1 fill status level control" "Normal,Mid" bitfld.word 0x00 10. " FIFO0_LVL ,FIFO 0 fill status level control" "Normal,Mid" textline " " bitfld.word 0x00 9. " FIFO1_CLR ,FIFO 1 clear" "Normal,Clear" bitfld.word 0x00 8. " FIFO0_CLR ,FIFO 0 clear" "Normal,Clear" hexmask.word.byte 0x00 0.--7. 1. " MSK ,Interrupt mask register" group.word 0x10C++0x01 line.word 0x00 "UDB_CAT16_ACTL_MSK6,Mask And Auxiliary Control Registers (ACTL,MSK)" bitfld.word 0x00 13. " CNT_START ,Control register counter enable" "Disabled,Enabled" bitfld.word 0x00 12. " INT_EN ,Enable interrupt" "Disabled,Enabled" bitfld.word 0x00 11. " FIFO1_LVL ,FIFO 1 fill status level control" "Normal,Mid" bitfld.word 0x00 10. " FIFO0_LVL ,FIFO 0 fill status level control" "Normal,Mid" textline " " bitfld.word 0x00 9. " FIFO1_CLR ,FIFO 1 clear" "Normal,Clear" bitfld.word 0x00 8. " FIFO0_CLR ,FIFO 0 clear" "Normal,Clear" hexmask.word.byte 0x00 0.--7. 1. " MSK ,Interrupt mask register" group.word 0x10E++0x01 line.word 0x00 "UDB_CAT16_ACTL_MSK7,Mask And Auxiliary Control Registers (ACTL,MSK)" bitfld.word 0x00 13. " CNT_START ,Control register counter enable" "Disabled,Enabled" bitfld.word 0x00 12. " INT_EN ,Enable interrupt" "Disabled,Enabled" bitfld.word 0x00 11. " FIFO1_LVL ,FIFO 1 fill status level control" "Normal,Mid" bitfld.word 0x00 10. " FIFO0_LVL ,FIFO 0 fill status level control" "Normal,Mid" textline " " bitfld.word 0x00 9. " FIFO1_CLR ,FIFO 1 clear" "Normal,Clear" bitfld.word 0x00 8. " FIFO0_CLR ,FIFO 0 clear" "Normal,Clear" hexmask.word.byte 0x00 0.--7. 1. " MSK ,Interrupt mask register" rgroup.word 0x140++0x01 line.word 0x00 "UDB_CAT16_MC0,PLD Macrocell Read Registers (00,MC)" bitfld.word 0x00 4.--7. " PLD1_MC ,PLD1 macrocell read register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PLD0_MC ,PLD0 macrocell read register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0x142++0x01 line.word 0x00 "UDB_CAT16_MC1,PLD Macrocell Read Registers (00,MC)" bitfld.word 0x00 4.--7. " PLD1_MC ,PLD1 macrocell read register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PLD0_MC ,PLD0 macrocell read register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0x144++0x01 line.word 0x00 "UDB_CAT16_MC2,PLD Macrocell Read Registers (00,MC)" bitfld.word 0x00 4.--7. " PLD1_MC ,PLD1 macrocell read register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PLD0_MC ,PLD0 macrocell read register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0x146++0x01 line.word 0x00 "UDB_CAT16_MC3,PLD Macrocell Read Registers (00,MC)" bitfld.word 0x00 4.--7. " PLD1_MC ,PLD1 macrocell read register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PLD0_MC ,PLD0 macrocell read register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0x148++0x01 line.word 0x00 "UDB_CAT16_MC4,PLD Macrocell Read Registers (00,MC)" bitfld.word 0x00 4.--7. " PLD1_MC ,PLD1 macrocell read register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PLD0_MC ,PLD0 macrocell read register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0x14A++0x01 line.word 0x00 "UDB_CAT16_MC5,PLD Macrocell Read Registers (00,MC)" bitfld.word 0x00 4.--7. " PLD1_MC ,PLD1 macrocell read register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PLD0_MC ,PLD0 macrocell read register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0x14C++0x01 line.word 0x00 "UDB_CAT16_MC6,PLD Macrocell Read Registers (00,MC)" bitfld.word 0x00 4.--7. " PLD1_MC ,PLD1 macrocell read register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PLD0_MC ,PLD0 macrocell read register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0x14E++0x01 line.word 0x00 "UDB_CAT16_MC7,PLD Macrocell Read Registers (00,MC)" bitfld.word 0x00 4.--7. " PLD1_MC ,PLD1 macrocell read register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PLD0_MC ,PLD0 macrocell read register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree "UDB 16-bit Working registers" base ad:0x400F1000 width 16. group.word 0x0++0x01 line.word 0x00 "UDB_W16_A00,Accumulator 0" hexmask.word.byte 0x00 8.--15. 1. " A0_MS ,Accumulator 0 for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " A0_LS ,Accumulator 0 for UDB[n]" group.word 0x2++0x01 line.word 0x00 "UDB_W16_A01,Accumulator 0" hexmask.word.byte 0x00 8.--15. 1. " A0_MS ,Accumulator 0 for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " A0_LS ,Accumulator 0 for UDB[n]" group.word 0x4++0x01 line.word 0x00 "UDB_W16_A02,Accumulator 0" hexmask.word.byte 0x00 8.--15. 1. " A0_MS ,Accumulator 0 for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " A0_LS ,Accumulator 0 for UDB[n]" group.word 0x6++0x01 line.word 0x00 "UDB_W16_A03,Accumulator 0" hexmask.word.byte 0x00 8.--15. 1. " A0_MS ,Accumulator 0 for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " A0_LS ,Accumulator 0 for UDB[n]" group.word 0x8++0x01 line.word 0x00 "UDB_W16_A04,Accumulator 0" hexmask.word.byte 0x00 8.--15. 1. " A0_MS ,Accumulator 0 for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " A0_LS ,Accumulator 0 for UDB[n]" group.word 0xA++0x01 line.word 0x00 "UDB_W16_A05,Accumulator 0" hexmask.word.byte 0x00 8.--15. 1. " A0_MS ,Accumulator 0 for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " A0_LS ,Accumulator 0 for UDB[n]" group.word 0xC++0x01 line.word 0x00 "UDB_W16_A06,Accumulator 0" hexmask.word.byte 0x00 8.--15. 1. " A0_MS ,Accumulator 0 for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " A0_LS ,Accumulator 0 for UDB[n]" group.word 0x20++0x01 line.word 0x00 "UDB_W16_A10,Accumulator 1" hexmask.word.byte 0x00 8.--15. 1. " A1_MS ,Accumulator 1 for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " A1_LS ,Accumulator 1 for UDB[n]" group.word 0x22++0x01 line.word 0x00 "UDB_W16_A11,Accumulator 1" hexmask.word.byte 0x00 8.--15. 1. " A1_MS ,Accumulator 1 for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " A1_LS ,Accumulator 1 for UDB[n]" group.word 0x24++0x01 line.word 0x00 "UDB_W16_A12,Accumulator 1" hexmask.word.byte 0x00 8.--15. 1. " A1_MS ,Accumulator 1 for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " A1_LS ,Accumulator 1 for UDB[n]" group.word 0x26++0x01 line.word 0x00 "UDB_W16_A13,Accumulator 1" hexmask.word.byte 0x00 8.--15. 1. " A1_MS ,Accumulator 1 for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " A1_LS ,Accumulator 1 for UDB[n]" group.word 0x28++0x01 line.word 0x00 "UDB_W16_A14,Accumulator 1" hexmask.word.byte 0x00 8.--15. 1. " A1_MS ,Accumulator 1 for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " A1_LS ,Accumulator 1 for UDB[n]" group.word 0x2A++0x01 line.word 0x00 "UDB_W16_A15,Accumulator 1" hexmask.word.byte 0x00 8.--15. 1. " A1_MS ,Accumulator 1 for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " A1_LS ,Accumulator 1 for UDB[n]" group.word 0x2C++0x01 line.word 0x00 "UDB_W16_A16,Accumulator 1" hexmask.word.byte 0x00 8.--15. 1. " A1_MS ,Accumulator 1 for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " A1_LS ,Accumulator 1 for UDB[n]" group.word 0x40++0x01 line.word 0x00 "UDB_W16_D00,Data 0" hexmask.word.byte 0x00 8.--15. 1. " D0_MS ,Data 0 for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " D0_LS ,Data 0 for UDB[n]" group.word 0x42++0x01 line.word 0x00 "UDB_W16_D01,Data 0" hexmask.word.byte 0x00 8.--15. 1. " D0_MS ,Data 0 for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " D0_LS ,Data 0 for UDB[n]" group.word 0x44++0x01 line.word 0x00 "UDB_W16_D02,Data 0" hexmask.word.byte 0x00 8.--15. 1. " D0_MS ,Data 0 for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " D0_LS ,Data 0 for UDB[n]" group.word 0x46++0x01 line.word 0x00 "UDB_W16_D03,Data 0" hexmask.word.byte 0x00 8.--15. 1. " D0_MS ,Data 0 for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " D0_LS ,Data 0 for UDB[n]" group.word 0x48++0x01 line.word 0x00 "UDB_W16_D04,Data 0" hexmask.word.byte 0x00 8.--15. 1. " D0_MS ,Data 0 for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " D0_LS ,Data 0 for UDB[n]" group.word 0x4A++0x01 line.word 0x00 "UDB_W16_D05,Data 0" hexmask.word.byte 0x00 8.--15. 1. " D0_MS ,Data 0 for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " D0_LS ,Data 0 for UDB[n]" group.word 0x4C++0x01 line.word 0x00 "UDB_W16_D06,Data 0" hexmask.word.byte 0x00 8.--15. 1. " D0_MS ,Data 0 for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " D0_LS ,Data 0 for UDB[n]" group.word 0x60++0x01 line.word 0x00 "UDB_W16_D10,Data 1" hexmask.word.byte 0x00 8.--15. 1. " D1_MS ,Data 1 for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " D1_LS ,Data 1 for UDB[n]" group.word 0x62++0x01 line.word 0x00 "UDB_W16_D11,Data 1" hexmask.word.byte 0x00 8.--15. 1. " D1_MS ,Data 1 for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " D1_LS ,Data 1 for UDB[n]" group.word 0x64++0x01 line.word 0x00 "UDB_W16_D12,Data 1" hexmask.word.byte 0x00 8.--15. 1. " D1_MS ,Data 1 for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " D1_LS ,Data 1 for UDB[n]" group.word 0x66++0x01 line.word 0x00 "UDB_W16_D13,Data 1" hexmask.word.byte 0x00 8.--15. 1. " D1_MS ,Data 1 for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " D1_LS ,Data 1 for UDB[n]" group.word 0x68++0x01 line.word 0x00 "UDB_W16_D14,Data 1" hexmask.word.byte 0x00 8.--15. 1. " D1_MS ,Data 1 for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " D1_LS ,Data 1 for UDB[n]" group.word 0x6A++0x01 line.word 0x00 "UDB_W16_D15,Data 1" hexmask.word.byte 0x00 8.--15. 1. " D1_MS ,Data 1 for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " D1_LS ,Data 1 for UDB[n]" group.word 0x6C++0x01 line.word 0x00 "UDB_W16_D16,Data 1" hexmask.word.byte 0x00 8.--15. 1. " D1_MS ,Data 1 for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " D1_LS ,Data 1 for UDB[n]" group.word 0x80++0x01 line.word 0x00 "UDB_W16_F00,FIFO 0" hexmask.word.byte 0x00 8.--15. 1. " F0_MS ,Fifo 0 for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " F0_LS ,Fifo 0 for UDB[n]" group.word 0x82++0x01 line.word 0x00 "UDB_W16_F01,FIFO 0" hexmask.word.byte 0x00 8.--15. 1. " F0_MS ,Fifo 0 for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " F0_LS ,Fifo 0 for UDB[n]" group.word 0x84++0x01 line.word 0x00 "UDB_W16_F02,FIFO 0" hexmask.word.byte 0x00 8.--15. 1. " F0_MS ,Fifo 0 for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " F0_LS ,Fifo 0 for UDB[n]" group.word 0x86++0x01 line.word 0x00 "UDB_W16_F03,FIFO 0" hexmask.word.byte 0x00 8.--15. 1. " F0_MS ,Fifo 0 for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " F0_LS ,Fifo 0 for UDB[n]" group.word 0x88++0x01 line.word 0x00 "UDB_W16_F04,FIFO 0" hexmask.word.byte 0x00 8.--15. 1. " F0_MS ,Fifo 0 for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " F0_LS ,Fifo 0 for UDB[n]" group.word 0x8A++0x01 line.word 0x00 "UDB_W16_F05,FIFO 0" hexmask.word.byte 0x00 8.--15. 1. " F0_MS ,Fifo 0 for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " F0_LS ,Fifo 0 for UDB[n]" group.word 0x8C++0x01 line.word 0x00 "UDB_W16_F06,FIFO 0" hexmask.word.byte 0x00 8.--15. 1. " F0_MS ,Fifo 0 for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " F0_LS ,Fifo 0 for UDB[n]" group.word 0xA0++0x01 line.word 0x00 "UDB_W16_F10,FIFO 1" hexmask.word.byte 0x00 8.--15. 1. " F1_MS ,Fifo 1 for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " F1_LS ,Fifo 1 for UDB[n]" group.word 0xA2++0x01 line.word 0x00 "UDB_W16_F11,FIFO 1" hexmask.word.byte 0x00 8.--15. 1. " F1_MS ,Fifo 1 for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " F1_LS ,Fifo 1 for UDB[n]" group.word 0xA4++0x01 line.word 0x00 "UDB_W16_F12,FIFO 1" hexmask.word.byte 0x00 8.--15. 1. " F1_MS ,Fifo 1 for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " F1_LS ,Fifo 1 for UDB[n]" group.word 0xA6++0x01 line.word 0x00 "UDB_W16_F13,FIFO 1" hexmask.word.byte 0x00 8.--15. 1. " F1_MS ,Fifo 1 for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " F1_LS ,Fifo 1 for UDB[n]" group.word 0xA8++0x01 line.word 0x00 "UDB_W16_F14,FIFO 1" hexmask.word.byte 0x00 8.--15. 1. " F1_MS ,Fifo 1 for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " F1_LS ,Fifo 1 for UDB[n]" group.word 0xAA++0x01 line.word 0x00 "UDB_W16_F15,FIFO 1" hexmask.word.byte 0x00 8.--15. 1. " F1_MS ,Fifo 1 for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " F1_LS ,Fifo 1 for UDB[n]" group.word 0xAC++0x01 line.word 0x00 "UDB_W16_F16,FIFO 1" hexmask.word.byte 0x00 8.--15. 1. " F1_MS ,Fifo 1 for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " F1_LS ,Fifo 1 for UDB[n]" rgroup.word 0xC0++0x01 line.word 0x00 "UDB_W16_ST0,Status Register 0" hexmask.word.byte 0x00 8.--15. 1. " ST_MS ,Status register for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " ST_LS ,Status register for UDB[n]" rgroup.word 0xC2++0x01 line.word 0x00 "UDB_W16_ST1,Status Register 1" hexmask.word.byte 0x00 8.--15. 1. " ST_MS ,Status register for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " ST_LS ,Status register for UDB[n]" rgroup.word 0xC4++0x01 line.word 0x00 "UDB_W16_ST2,Status Register 2" hexmask.word.byte 0x00 8.--15. 1. " ST_MS ,Status register for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " ST_LS ,Status register for UDB[n]" rgroup.word 0xC6++0x01 line.word 0x00 "UDB_W16_ST3,Status Register 3" hexmask.word.byte 0x00 8.--15. 1. " ST_MS ,Status register for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " ST_LS ,Status register for UDB[n]" rgroup.word 0xC8++0x01 line.word 0x00 "UDB_W16_ST4,Status Register 4" hexmask.word.byte 0x00 8.--15. 1. " ST_MS ,Status register for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " ST_LS ,Status register for UDB[n]" rgroup.word 0xCA++0x01 line.word 0x00 "UDB_W16_ST5,Status Register 5" hexmask.word.byte 0x00 8.--15. 1. " ST_MS ,Status register for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " ST_LS ,Status register for UDB[n]" rgroup.word 0xCC++0x01 line.word 0x00 "UDB_W16_ST6,Status Register 6" hexmask.word.byte 0x00 8.--15. 1. " ST_MS ,Status register for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " ST_LS ,Status register for UDB[n]" group.word 0xE0++0x01 line.word 0x00 "UDB_W16_CTL0,Control Register 0" hexmask.word.byte 0x00 8.--15. 1. " CTL_MS ,Control register for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " CTL_LS ,Control register for UDB[n]" group.word 0xE2++0x01 line.word 0x00 "UDB_W16_CTL1,Control Register 1" hexmask.word.byte 0x00 8.--15. 1. " CTL_MS ,Control register for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " CTL_LS ,Control register for UDB[n]" group.word 0xE4++0x01 line.word 0x00 "UDB_W16_CTL2,Control Register 2" hexmask.word.byte 0x00 8.--15. 1. " CTL_MS ,Control register for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " CTL_LS ,Control register for UDB[n]" group.word 0xE6++0x01 line.word 0x00 "UDB_W16_CTL3,Control Register 3" hexmask.word.byte 0x00 8.--15. 1. " CTL_MS ,Control register for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " CTL_LS ,Control register for UDB[n]" group.word 0xE8++0x01 line.word 0x00 "UDB_W16_CTL4,Control Register 4" hexmask.word.byte 0x00 8.--15. 1. " CTL_MS ,Control register for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " CTL_LS ,Control register for UDB[n]" group.word 0xEA++0x01 line.word 0x00 "UDB_W16_CTL5,Control Register 5" hexmask.word.byte 0x00 8.--15. 1. " CTL_MS ,Control register for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " CTL_LS ,Control register for UDB[n]" group.word 0xEC++0x01 line.word 0x00 "UDB_W16_CTL6,Control Register 6" hexmask.word.byte 0x00 8.--15. 1. " CTL_MS ,Control register for UDB[n+1]" hexmask.word.byte 0x00 0.--7. 1. " CTL_LS ,Control register for UDB[n]" group.word 0x100++0x01 line.word 0x00 "UDB_W16_MSK0,Interrupt Mask 0" hexmask.word.byte 0x00 8.--14. 1. " MSK_MS ,Interrupt mask register for UDB[n+1]" hexmask.word.byte 0x00 0.--6. 1. " MSK_LS ,Interrupt mask register for UDB[n]" group.word 0x102++0x01 line.word 0x00 "UDB_W16_MSK1,Interrupt Mask 1" hexmask.word.byte 0x00 8.--14. 1. " MSK_MS ,Interrupt mask register for UDB[n+1]" hexmask.word.byte 0x00 0.--6. 1. " MSK_LS ,Interrupt mask register for UDB[n]" group.word 0x104++0x01 line.word 0x00 "UDB_W16_MSK2,Interrupt Mask 2" hexmask.word.byte 0x00 8.--14. 1. " MSK_MS ,Interrupt mask register for UDB[n+1]" hexmask.word.byte 0x00 0.--6. 1. " MSK_LS ,Interrupt mask register for UDB[n]" group.word 0x106++0x01 line.word 0x00 "UDB_W16_MSK3,Interrupt Mask 3" hexmask.word.byte 0x00 8.--14. 1. " MSK_MS ,Interrupt mask register for UDB[n+1]" hexmask.word.byte 0x00 0.--6. 1. " MSK_LS ,Interrupt mask register for UDB[n]" group.word 0x108++0x01 line.word 0x00 "UDB_W16_MSK4,Interrupt Mask 4" hexmask.word.byte 0x00 8.--14. 1. " MSK_MS ,Interrupt mask register for UDB[n+1]" hexmask.word.byte 0x00 0.--6. 1. " MSK_LS ,Interrupt mask register for UDB[n]" group.word 0x10A++0x01 line.word 0x00 "UDB_W16_MSK5,Interrupt Mask 5" hexmask.word.byte 0x00 8.--14. 1. " MSK_MS ,Interrupt mask register for UDB[n+1]" hexmask.word.byte 0x00 0.--6. 1. " MSK_LS ,Interrupt mask register for UDB[n]" group.word 0x10C++0x01 line.word 0x00 "UDB_W16_MSK6,Interrupt Mask 6" hexmask.word.byte 0x00 8.--14. 1. " MSK_MS ,Interrupt mask register for UDB[n+1]" hexmask.word.byte 0x00 0.--6. 1. " MSK_LS ,Interrupt mask register for UDB[n]" group.word 0x120++0x01 line.word 0x00 "UDB_W16_ACTL0,Auxiliary Control 0" bitfld.word 0x00 13. " CNT_START_MS ,Control register counter MS enable" "Disabled,Enabled" bitfld.word 0x00 12. " INT_EN_MS ,Enable interrupt MS" "Disabled,Enabled" bitfld.word 0x00 11. " FIFO1_LVL_MS ,FIFO 1 fill status level MS control" "Normal,Mid" bitfld.word 0x00 10. " FIFO0_LVL_MS ,FIFO 0 fill status level MS control" "Normal,Mid" textline " " bitfld.word 0x00 9. " FIFO1_CLR_MS ,FIFO 1 clear MS" "Normal,Clear" bitfld.word 0x00 8. " FIFO0_CLR_MS ,FIFO 0 clear MS" "Normal,Clear" bitfld.word 0x00 5. " CNT_START_LS ,Control register counter LS enable" "Disabled,Enabled" bitfld.word 0x00 4. " INT_EN_LS ,Enable interrupt LS" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " FIFO1_LVL_LS ,FIFO 1 fill status level LS control" "Normal,Mid" bitfld.word 0x00 2. " FIFO0_LVL_LS ,FIFO fill status level control" "Normal,Mid" bitfld.word 0x00 1. " FIFO1_CLR_LS ,FIFO 1 clear LS" "Normal,Clear" bitfld.word 0x00 0. " FIFO0_CLR_LS ,FIFO 0 clear LS" "Normal,Clear" group.word 0x122++0x01 line.word 0x00 "UDB_W16_ACTL1,Auxiliary Control 1" bitfld.word 0x00 13. " CNT_START_MS ,Control register counter MS enable" "Disabled,Enabled" bitfld.word 0x00 12. " INT_EN_MS ,Enable interrupt MS" "Disabled,Enabled" bitfld.word 0x00 11. " FIFO1_LVL_MS ,FIFO 1 fill status level MS control" "Normal,Mid" bitfld.word 0x00 10. " FIFO0_LVL_MS ,FIFO 0 fill status level MS control" "Normal,Mid" textline " " bitfld.word 0x00 9. " FIFO1_CLR_MS ,FIFO 1 clear MS" "Normal,Clear" bitfld.word 0x00 8. " FIFO0_CLR_MS ,FIFO 0 clear MS" "Normal,Clear" bitfld.word 0x00 5. " CNT_START_LS ,Control register counter LS enable" "Disabled,Enabled" bitfld.word 0x00 4. " INT_EN_LS ,Enable interrupt LS" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " FIFO1_LVL_LS ,FIFO 1 fill status level LS control" "Normal,Mid" bitfld.word 0x00 2. " FIFO0_LVL_LS ,FIFO fill status level control" "Normal,Mid" bitfld.word 0x00 1. " FIFO1_CLR_LS ,FIFO 1 clear LS" "Normal,Clear" bitfld.word 0x00 0. " FIFO0_CLR_LS ,FIFO 0 clear LS" "Normal,Clear" group.word 0x124++0x01 line.word 0x00 "UDB_W16_ACTL2,Auxiliary Control 2" bitfld.word 0x00 13. " CNT_START_MS ,Control register counter MS enable" "Disabled,Enabled" bitfld.word 0x00 12. " INT_EN_MS ,Enable interrupt MS" "Disabled,Enabled" bitfld.word 0x00 11. " FIFO1_LVL_MS ,FIFO 1 fill status level MS control" "Normal,Mid" bitfld.word 0x00 10. " FIFO0_LVL_MS ,FIFO 0 fill status level MS control" "Normal,Mid" textline " " bitfld.word 0x00 9. " FIFO1_CLR_MS ,FIFO 1 clear MS" "Normal,Clear" bitfld.word 0x00 8. " FIFO0_CLR_MS ,FIFO 0 clear MS" "Normal,Clear" bitfld.word 0x00 5. " CNT_START_LS ,Control register counter LS enable" "Disabled,Enabled" bitfld.word 0x00 4. " INT_EN_LS ,Enable interrupt LS" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " FIFO1_LVL_LS ,FIFO 1 fill status level LS control" "Normal,Mid" bitfld.word 0x00 2. " FIFO0_LVL_LS ,FIFO fill status level control" "Normal,Mid" bitfld.word 0x00 1. " FIFO1_CLR_LS ,FIFO 1 clear LS" "Normal,Clear" bitfld.word 0x00 0. " FIFO0_CLR_LS ,FIFO 0 clear LS" "Normal,Clear" group.word 0x126++0x01 line.word 0x00 "UDB_W16_ACTL3,Auxiliary Control 3" bitfld.word 0x00 13. " CNT_START_MS ,Control register counter MS enable" "Disabled,Enabled" bitfld.word 0x00 12. " INT_EN_MS ,Enable interrupt MS" "Disabled,Enabled" bitfld.word 0x00 11. " FIFO1_LVL_MS ,FIFO 1 fill status level MS control" "Normal,Mid" bitfld.word 0x00 10. " FIFO0_LVL_MS ,FIFO 0 fill status level MS control" "Normal,Mid" textline " " bitfld.word 0x00 9. " FIFO1_CLR_MS ,FIFO 1 clear MS" "Normal,Clear" bitfld.word 0x00 8. " FIFO0_CLR_MS ,FIFO 0 clear MS" "Normal,Clear" bitfld.word 0x00 5. " CNT_START_LS ,Control register counter LS enable" "Disabled,Enabled" bitfld.word 0x00 4. " INT_EN_LS ,Enable interrupt LS" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " FIFO1_LVL_LS ,FIFO 1 fill status level LS control" "Normal,Mid" bitfld.word 0x00 2. " FIFO0_LVL_LS ,FIFO fill status level control" "Normal,Mid" bitfld.word 0x00 1. " FIFO1_CLR_LS ,FIFO 1 clear LS" "Normal,Clear" bitfld.word 0x00 0. " FIFO0_CLR_LS ,FIFO 0 clear LS" "Normal,Clear" group.word 0x128++0x01 line.word 0x00 "UDB_W16_ACTL4,Auxiliary Control 4" bitfld.word 0x00 13. " CNT_START_MS ,Control register counter MS enable" "Disabled,Enabled" bitfld.word 0x00 12. " INT_EN_MS ,Enable interrupt MS" "Disabled,Enabled" bitfld.word 0x00 11. " FIFO1_LVL_MS ,FIFO 1 fill status level MS control" "Normal,Mid" bitfld.word 0x00 10. " FIFO0_LVL_MS ,FIFO 0 fill status level MS control" "Normal,Mid" textline " " bitfld.word 0x00 9. " FIFO1_CLR_MS ,FIFO 1 clear MS" "Normal,Clear" bitfld.word 0x00 8. " FIFO0_CLR_MS ,FIFO 0 clear MS" "Normal,Clear" bitfld.word 0x00 5. " CNT_START_LS ,Control register counter LS enable" "Disabled,Enabled" bitfld.word 0x00 4. " INT_EN_LS ,Enable interrupt LS" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " FIFO1_LVL_LS ,FIFO 1 fill status level LS control" "Normal,Mid" bitfld.word 0x00 2. " FIFO0_LVL_LS ,FIFO fill status level control" "Normal,Mid" bitfld.word 0x00 1. " FIFO1_CLR_LS ,FIFO 1 clear LS" "Normal,Clear" bitfld.word 0x00 0. " FIFO0_CLR_LS ,FIFO 0 clear LS" "Normal,Clear" group.word 0x12A++0x01 line.word 0x00 "UDB_W16_ACTL5,Auxiliary Control 5" bitfld.word 0x00 13. " CNT_START_MS ,Control register counter MS enable" "Disabled,Enabled" bitfld.word 0x00 12. " INT_EN_MS ,Enable interrupt MS" "Disabled,Enabled" bitfld.word 0x00 11. " FIFO1_LVL_MS ,FIFO 1 fill status level MS control" "Normal,Mid" bitfld.word 0x00 10. " FIFO0_LVL_MS ,FIFO 0 fill status level MS control" "Normal,Mid" textline " " bitfld.word 0x00 9. " FIFO1_CLR_MS ,FIFO 1 clear MS" "Normal,Clear" bitfld.word 0x00 8. " FIFO0_CLR_MS ,FIFO 0 clear MS" "Normal,Clear" bitfld.word 0x00 5. " CNT_START_LS ,Control register counter LS enable" "Disabled,Enabled" bitfld.word 0x00 4. " INT_EN_LS ,Enable interrupt LS" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " FIFO1_LVL_LS ,FIFO 1 fill status level LS control" "Normal,Mid" bitfld.word 0x00 2. " FIFO0_LVL_LS ,FIFO fill status level control" "Normal,Mid" bitfld.word 0x00 1. " FIFO1_CLR_LS ,FIFO 1 clear LS" "Normal,Clear" bitfld.word 0x00 0. " FIFO0_CLR_LS ,FIFO 0 clear LS" "Normal,Clear" group.word 0x12C++0x01 line.word 0x00 "UDB_W16_ACTL6,Auxiliary Control 6" bitfld.word 0x00 13. " CNT_START_MS ,Control register counter MS enable" "Disabled,Enabled" bitfld.word 0x00 12. " INT_EN_MS ,Enable interrupt MS" "Disabled,Enabled" bitfld.word 0x00 11. " FIFO1_LVL_MS ,FIFO 1 fill status level MS control" "Normal,Mid" bitfld.word 0x00 10. " FIFO0_LVL_MS ,FIFO 0 fill status level MS control" "Normal,Mid" textline " " bitfld.word 0x00 9. " FIFO1_CLR_MS ,FIFO 1 clear MS" "Normal,Clear" bitfld.word 0x00 8. " FIFO0_CLR_MS ,FIFO 0 clear MS" "Normal,Clear" bitfld.word 0x00 5. " CNT_START_LS ,Control register counter LS enable" "Disabled,Enabled" bitfld.word 0x00 4. " INT_EN_LS ,Enable interrupt LS" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " FIFO1_LVL_LS ,FIFO 1 fill status level LS control" "Normal,Mid" bitfld.word 0x00 2. " FIFO0_LVL_LS ,FIFO fill status level control" "Normal,Mid" bitfld.word 0x00 1. " FIFO1_CLR_LS ,FIFO 1 clear LS" "Normal,Clear" bitfld.word 0x00 0. " FIFO0_CLR_LS ,FIFO 0 clear LS" "Normal,Clear" rgroup.word 0x140++0x01 line.word 0x00 "UDB_W16_MC0,PLD Macrocell Reading 0" bitfld.word 0x00 12.--15. " PLD1_MC_MS ,Read macrocell 1 for UDB[n+1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 8.--11. " PLD0_MC_MS ,Read macrocell 0 for UDB[n+1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 4.--7. " PLD1_MC_LS ,Read macrocell 1 for UDB[n]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PLD0_MC_LS ,Read macrocell 0 for UDB[n]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0x142++0x01 line.word 0x00 "UDB_W16_MC1,PLD Macrocell Reading 1" bitfld.word 0x00 12.--15. " PLD1_MC_MS ,Read macrocell 1 for UDB[n+1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 8.--11. " PLD0_MC_MS ,Read macrocell 0 for UDB[n+1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 4.--7. " PLD1_MC_LS ,Read macrocell 1 for UDB[n]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PLD0_MC_LS ,Read macrocell 0 for UDB[n]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0x144++0x01 line.word 0x00 "UDB_W16_MC2,PLD Macrocell Reading 2" bitfld.word 0x00 12.--15. " PLD1_MC_MS ,Read macrocell 1 for UDB[n+1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 8.--11. " PLD0_MC_MS ,Read macrocell 0 for UDB[n+1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 4.--7. " PLD1_MC_LS ,Read macrocell 1 for UDB[n]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PLD0_MC_LS ,Read macrocell 0 for UDB[n]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0x146++0x01 line.word 0x00 "UDB_W16_MC3,PLD Macrocell Reading 3" bitfld.word 0x00 12.--15. " PLD1_MC_MS ,Read macrocell 1 for UDB[n+1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 8.--11. " PLD0_MC_MS ,Read macrocell 0 for UDB[n+1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 4.--7. " PLD1_MC_LS ,Read macrocell 1 for UDB[n]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PLD0_MC_LS ,Read macrocell 0 for UDB[n]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0x148++0x01 line.word 0x00 "UDB_W16_MC4,PLD Macrocell Reading 4" bitfld.word 0x00 12.--15. " PLD1_MC_MS ,Read macrocell 1 for UDB[n+1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 8.--11. " PLD0_MC_MS ,Read macrocell 0 for UDB[n+1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 4.--7. " PLD1_MC_LS ,Read macrocell 1 for UDB[n]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PLD0_MC_LS ,Read macrocell 0 for UDB[n]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0x14A++0x01 line.word 0x00 "UDB_W16_MC5,PLD Macrocell Reading 5" bitfld.word 0x00 12.--15. " PLD1_MC_MS ,Read macrocell 1 for UDB[n+1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 8.--11. " PLD0_MC_MS ,Read macrocell 0 for UDB[n+1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 4.--7. " PLD1_MC_LS ,Read macrocell 1 for UDB[n]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PLD0_MC_LS ,Read macrocell 0 for UDB[n]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.word 0x14C++0x01 line.word 0x00 "UDB_W16_MC6,PLD Macrocell Reading 6" bitfld.word 0x00 12.--15. " PLD1_MC_MS ,Read macrocell 1 for UDB[n+1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 8.--11. " PLD0_MC_MS ,Read macrocell 0 for UDB[n+1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 4.--7. " PLD1_MC_LS ,Read macrocell 1 for UDB[n]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.word 0x00 0.--3. " PLD0_MC_LS ,Read macrocell 0 for UDB[n]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree "UDB 32-bit Working registers" base ad:0x400F2000 width 16. group.long 0x0++0x03 line.long 0x00 "UDB_W32_A00,Accumulator 0" hexmask.long.byte 0x00 24.--31. 1. " A0_3 ,Accumulator 0 for UDB[n+3]" hexmask.long.byte 0x00 16.--23. 1. " A0_2 ,Accumulator 0 for UDB[n+2]" hexmask.long.byte 0x00 8.--15. 1. " A0_1 ,Accumulator 0 for UDB[n+1]" hexmask.long.byte 0x00 0.--7. 1. " A0_0 ,Accumulator 0 for UDB[n]" group.long 0x4++0x03 line.long 0x00 "UDB_W32_A01,Accumulator 0" hexmask.long.byte 0x00 24.--31. 1. " A0_3 ,Accumulator 0 for UDB[n+3]" hexmask.long.byte 0x00 16.--23. 1. " A0_2 ,Accumulator 0 for UDB[n+2]" hexmask.long.byte 0x00 8.--15. 1. " A0_1 ,Accumulator 0 for UDB[n+1]" hexmask.long.byte 0x00 0.--7. 1. " A0_0 ,Accumulator 0 for UDB[n]" group.long 0x8++0x03 line.long 0x00 "UDB_W32_A02,Accumulator 0" hexmask.long.byte 0x00 24.--31. 1. " A0_3 ,Accumulator 0 for UDB[n+3]" hexmask.long.byte 0x00 16.--23. 1. " A0_2 ,Accumulator 0 for UDB[n+2]" hexmask.long.byte 0x00 8.--15. 1. " A0_1 ,Accumulator 0 for UDB[n+1]" hexmask.long.byte 0x00 0.--7. 1. " A0_0 ,Accumulator 0 for UDB[n]" group.long 0xC++0x03 line.long 0x00 "UDB_W32_A03,Accumulator 0" hexmask.long.byte 0x00 24.--31. 1. " A0_3 ,Accumulator 0 for UDB[n+3]" hexmask.long.byte 0x00 16.--23. 1. " A0_2 ,Accumulator 0 for UDB[n+2]" hexmask.long.byte 0x00 8.--15. 1. " A0_1 ,Accumulator 0 for UDB[n+1]" hexmask.long.byte 0x00 0.--7. 1. " A0_0 ,Accumulator 0 for UDB[n]" group.long 0x10++0x03 line.long 0x00 "UDB_W32_A04,Accumulator 0" hexmask.long.byte 0x00 24.--31. 1. " A0_3 ,Accumulator 0 for UDB[n+3]" hexmask.long.byte 0x00 16.--23. 1. " A0_2 ,Accumulator 0 for UDB[n+2]" hexmask.long.byte 0x00 8.--15. 1. " A0_1 ,Accumulator 0 for UDB[n+1]" hexmask.long.byte 0x00 0.--7. 1. " A0_0 ,Accumulator 0 for UDB[n]" group.long 0x40++0x03 line.long 0x00 "UDB_W32_A10,Accumulator 1" hexmask.long.byte 0x00 24.--31. 1. " A1_3 ,Accumulator 1 for UDB[n+3]" hexmask.long.byte 0x00 16.--23. 1. " A1_2 ,Accumulator 1 for UDB[n+2]" hexmask.long.byte 0x00 8.--15. 1. " A1_1 ,Accumulator 1 for UDB[n+1]" hexmask.long.byte 0x00 0.--7. 1. " A1_0 ,Accumulator 1 for UDB[n]" group.long 0x44++0x03 line.long 0x00 "UDB_W32_A11,Accumulator 1" hexmask.long.byte 0x00 24.--31. 1. " A1_3 ,Accumulator 1 for UDB[n+3]" hexmask.long.byte 0x00 16.--23. 1. " A1_2 ,Accumulator 1 for UDB[n+2]" hexmask.long.byte 0x00 8.--15. 1. " A1_1 ,Accumulator 1 for UDB[n+1]" hexmask.long.byte 0x00 0.--7. 1. " A1_0 ,Accumulator 1 for UDB[n]" group.long 0x48++0x03 line.long 0x00 "UDB_W32_A12,Accumulator 1" hexmask.long.byte 0x00 24.--31. 1. " A1_3 ,Accumulator 1 for UDB[n+3]" hexmask.long.byte 0x00 16.--23. 1. " A1_2 ,Accumulator 1 for UDB[n+2]" hexmask.long.byte 0x00 8.--15. 1. " A1_1 ,Accumulator 1 for UDB[n+1]" hexmask.long.byte 0x00 0.--7. 1. " A1_0 ,Accumulator 1 for UDB[n]" group.long 0x4C++0x03 line.long 0x00 "UDB_W32_A13,Accumulator 1" hexmask.long.byte 0x00 24.--31. 1. " A1_3 ,Accumulator 1 for UDB[n+3]" hexmask.long.byte 0x00 16.--23. 1. " A1_2 ,Accumulator 1 for UDB[n+2]" hexmask.long.byte 0x00 8.--15. 1. " A1_1 ,Accumulator 1 for UDB[n+1]" hexmask.long.byte 0x00 0.--7. 1. " A1_0 ,Accumulator 1 for UDB[n]" group.long 0x50++0x03 line.long 0x00 "UDB_W32_A14,Accumulator 1" hexmask.long.byte 0x00 24.--31. 1. " A1_3 ,Accumulator 1 for UDB[n+3]" hexmask.long.byte 0x00 16.--23. 1. " A1_2 ,Accumulator 1 for UDB[n+2]" hexmask.long.byte 0x00 8.--15. 1. " A1_1 ,Accumulator 1 for UDB[n+1]" hexmask.long.byte 0x00 0.--7. 1. " A1_0 ,Accumulator 1 for UDB[n]" group.long 0x80++0x03 line.long 0x00 "UDB_W32_D00,Data 0" hexmask.long.byte 0x00 24.--31. 1. " D0_3 ,Data 0 for UDB[n+3]" hexmask.long.byte 0x00 16.--23. 1. " D0_2 ,Data 0 for UDB[n+2]" hexmask.long.byte 0x00 8.--15. 1. " D0_1 ,Data 0 for UDB[n+1" hexmask.long.byte 0x00 0.--7. 1. " D0_0 ,Data 0 for UDB[n]" group.long 0x84++0x03 line.long 0x00 "UDB_W32_D01,Data 0" hexmask.long.byte 0x00 24.--31. 1. " D0_3 ,Data 0 for UDB[n+3]" hexmask.long.byte 0x00 16.--23. 1. " D0_2 ,Data 0 for UDB[n+2]" hexmask.long.byte 0x00 8.--15. 1. " D0_1 ,Data 0 for UDB[n+1" hexmask.long.byte 0x00 0.--7. 1. " D0_0 ,Data 0 for UDB[n]" group.long 0x88++0x03 line.long 0x00 "UDB_W32_D02,Data 0" hexmask.long.byte 0x00 24.--31. 1. " D0_3 ,Data 0 for UDB[n+3]" hexmask.long.byte 0x00 16.--23. 1. " D0_2 ,Data 0 for UDB[n+2]" hexmask.long.byte 0x00 8.--15. 1. " D0_1 ,Data 0 for UDB[n+1" hexmask.long.byte 0x00 0.--7. 1. " D0_0 ,Data 0 for UDB[n]" group.long 0x8C++0x03 line.long 0x00 "UDB_W32_D03,Data 0" hexmask.long.byte 0x00 24.--31. 1. " D0_3 ,Data 0 for UDB[n+3]" hexmask.long.byte 0x00 16.--23. 1. " D0_2 ,Data 0 for UDB[n+2]" hexmask.long.byte 0x00 8.--15. 1. " D0_1 ,Data 0 for UDB[n+1" hexmask.long.byte 0x00 0.--7. 1. " D0_0 ,Data 0 for UDB[n]" group.long 0x90++0x03 line.long 0x00 "UDB_W32_D04,Data 0" hexmask.long.byte 0x00 24.--31. 1. " D0_3 ,Data 0 for UDB[n+3]" hexmask.long.byte 0x00 16.--23. 1. " D0_2 ,Data 0 for UDB[n+2]" hexmask.long.byte 0x00 8.--15. 1. " D0_1 ,Data 0 for UDB[n+1" hexmask.long.byte 0x00 0.--7. 1. " D0_0 ,Data 0 for UDB[n]" group.long 0xC0++0x03 line.long 0x00 "UDB_W32_D10,Data 1" hexmask.long.byte 0x00 24.--31. 1. " D1_3 ,Data 1 for UDB[n+3]" hexmask.long.byte 0x00 16.--23. 1. " D1_2 ,Data 1 for UDB[n+2]" hexmask.long.byte 0x00 8.--15. 1. " D1_1 ,Data 1 for UDB[n+1]" hexmask.long.byte 0x00 0.--7. 1. " D1_0 ,Data 1 for UDB[n]" group.long 0xC4++0x03 line.long 0x00 "UDB_W32_D11,Data 1" hexmask.long.byte 0x00 24.--31. 1. " D1_3 ,Data 1 for UDB[n+3]" hexmask.long.byte 0x00 16.--23. 1. " D1_2 ,Data 1 for UDB[n+2]" hexmask.long.byte 0x00 8.--15. 1. " D1_1 ,Data 1 for UDB[n+1]" hexmask.long.byte 0x00 0.--7. 1. " D1_0 ,Data 1 for UDB[n]" group.long 0xC8++0x03 line.long 0x00 "UDB_W32_D12,Data 1" hexmask.long.byte 0x00 24.--31. 1. " D1_3 ,Data 1 for UDB[n+3]" hexmask.long.byte 0x00 16.--23. 1. " D1_2 ,Data 1 for UDB[n+2]" hexmask.long.byte 0x00 8.--15. 1. " D1_1 ,Data 1 for UDB[n+1]" hexmask.long.byte 0x00 0.--7. 1. " D1_0 ,Data 1 for UDB[n]" group.long 0xCC++0x03 line.long 0x00 "UDB_W32_D13,Data 1" hexmask.long.byte 0x00 24.--31. 1. " D1_3 ,Data 1 for UDB[n+3]" hexmask.long.byte 0x00 16.--23. 1. " D1_2 ,Data 1 for UDB[n+2]" hexmask.long.byte 0x00 8.--15. 1. " D1_1 ,Data 1 for UDB[n+1]" hexmask.long.byte 0x00 0.--7. 1. " D1_0 ,Data 1 for UDB[n]" group.long 0xD0++0x03 line.long 0x00 "UDB_W32_D14,Data 1" hexmask.long.byte 0x00 24.--31. 1. " D1_3 ,Data 1 for UDB[n+3]" hexmask.long.byte 0x00 16.--23. 1. " D1_2 ,Data 1 for UDB[n+2]" hexmask.long.byte 0x00 8.--15. 1. " D1_1 ,Data 1 for UDB[n+1]" hexmask.long.byte 0x00 0.--7. 1. " D1_0 ,Data 1 for UDB[n]" group.long 0x100++0x03 line.long 0x00 "UDB_W32_F00,FIFO 0" hexmask.long.byte 0x00 24.--31. 1. " F0_3 ,Fifo 0 for UDB[n+3]" hexmask.long.byte 0x00 16.--23. 1. " F0_2 ,Fifo 0 for UDB[n+2]" hexmask.long.byte 0x00 8.--15. 1. " F0_1 ,Fifo 0 for UDB[n+1]" hexmask.long.byte 0x00 0.--7. 1. " F0_0 ,Fifo 0 for UDB[n]" group.long 0x104++0x03 line.long 0x00 "UDB_W32_F01,FIFO 0" hexmask.long.byte 0x00 24.--31. 1. " F0_3 ,Fifo 0 for UDB[n+3]" hexmask.long.byte 0x00 16.--23. 1. " F0_2 ,Fifo 0 for UDB[n+2]" hexmask.long.byte 0x00 8.--15. 1. " F0_1 ,Fifo 0 for UDB[n+1]" hexmask.long.byte 0x00 0.--7. 1. " F0_0 ,Fifo 0 for UDB[n]" group.long 0x108++0x03 line.long 0x00 "UDB_W32_F02,FIFO 0" hexmask.long.byte 0x00 24.--31. 1. " F0_3 ,Fifo 0 for UDB[n+3]" hexmask.long.byte 0x00 16.--23. 1. " F0_2 ,Fifo 0 for UDB[n+2]" hexmask.long.byte 0x00 8.--15. 1. " F0_1 ,Fifo 0 for UDB[n+1]" hexmask.long.byte 0x00 0.--7. 1. " F0_0 ,Fifo 0 for UDB[n]" group.long 0x10C++0x03 line.long 0x00 "UDB_W32_F03,FIFO 0" hexmask.long.byte 0x00 24.--31. 1. " F0_3 ,Fifo 0 for UDB[n+3]" hexmask.long.byte 0x00 16.--23. 1. " F0_2 ,Fifo 0 for UDB[n+2]" hexmask.long.byte 0x00 8.--15. 1. " F0_1 ,Fifo 0 for UDB[n+1]" hexmask.long.byte 0x00 0.--7. 1. " F0_0 ,Fifo 0 for UDB[n]" group.long 0x110++0x03 line.long 0x00 "UDB_W32_F04,FIFO 0" hexmask.long.byte 0x00 24.--31. 1. " F0_3 ,Fifo 0 for UDB[n+3]" hexmask.long.byte 0x00 16.--23. 1. " F0_2 ,Fifo 0 for UDB[n+2]" hexmask.long.byte 0x00 8.--15. 1. " F0_1 ,Fifo 0 for UDB[n+1]" hexmask.long.byte 0x00 0.--7. 1. " F0_0 ,Fifo 0 for UDB[n]" group.long 0x140++0x03 line.long 0x00 "UDB_W32_F10,FIFO 1" hexmask.long.byte 0x00 24.--31. 1. " F1_3 ,Fifo 1 for UDB[n+3]" hexmask.long.byte 0x00 16.--23. 1. " F1_2 ,Fifo 1 for UDB[n+2]" hexmask.long.byte 0x00 8.--15. 1. " F1_1 ,Fifo 1 for UDB[n+1]" hexmask.long.byte 0x00 0.--7. 1. " F1_0 ,Fifo 1 for UDB[n]" group.long 0x144++0x03 line.long 0x00 "UDB_W32_F11,FIFO 1" hexmask.long.byte 0x00 24.--31. 1. " F1_3 ,Fifo 1 for UDB[n+3]" hexmask.long.byte 0x00 16.--23. 1. " F1_2 ,Fifo 1 for UDB[n+2]" hexmask.long.byte 0x00 8.--15. 1. " F1_1 ,Fifo 1 for UDB[n+1]" hexmask.long.byte 0x00 0.--7. 1. " F1_0 ,Fifo 1 for UDB[n]" group.long 0x148++0x03 line.long 0x00 "UDB_W32_F12,FIFO 1" hexmask.long.byte 0x00 24.--31. 1. " F1_3 ,Fifo 1 for UDB[n+3]" hexmask.long.byte 0x00 16.--23. 1. " F1_2 ,Fifo 1 for UDB[n+2]" hexmask.long.byte 0x00 8.--15. 1. " F1_1 ,Fifo 1 for UDB[n+1]" hexmask.long.byte 0x00 0.--7. 1. " F1_0 ,Fifo 1 for UDB[n]" group.long 0x14C++0x03 line.long 0x00 "UDB_W32_F13,FIFO 1" hexmask.long.byte 0x00 24.--31. 1. " F1_3 ,Fifo 1 for UDB[n+3]" hexmask.long.byte 0x00 16.--23. 1. " F1_2 ,Fifo 1 for UDB[n+2]" hexmask.long.byte 0x00 8.--15. 1. " F1_1 ,Fifo 1 for UDB[n+1]" hexmask.long.byte 0x00 0.--7. 1. " F1_0 ,Fifo 1 for UDB[n]" group.long 0x150++0x03 line.long 0x00 "UDB_W32_F14,FIFO 1" hexmask.long.byte 0x00 24.--31. 1. " F1_3 ,Fifo 1 for UDB[n+3]" hexmask.long.byte 0x00 16.--23. 1. " F1_2 ,Fifo 1 for UDB[n+2]" hexmask.long.byte 0x00 8.--15. 1. " F1_1 ,Fifo 1 for UDB[n+1]" hexmask.long.byte 0x00 0.--7. 1. " F1_0 ,Fifo 1 for UDB[n]" rgroup.long 0x180++0x03 line.long 0x00 "UDB_W32_ST0,Status Register 0" hexmask.long.byte 0x00 24.--31. 1. " ST_3 ,Status register for UDB[n+3]" hexmask.long.byte 0x00 16.--23. 1. " ST_2 ,Status register for UDB[n+2]" hexmask.long.byte 0x00 8.--15. 1. " ST_1 ,Status register for UDB[n+1]" hexmask.long.byte 0x00 0.--7. 1. " ST_0 ,Status register for UDB[n]" rgroup.long 0x184++0x03 line.long 0x00 "UDB_W32_ST1,Status Register 1" hexmask.long.byte 0x00 24.--31. 1. " ST_3 ,Status register for UDB[n+3]" hexmask.long.byte 0x00 16.--23. 1. " ST_2 ,Status register for UDB[n+2]" hexmask.long.byte 0x00 8.--15. 1. " ST_1 ,Status register for UDB[n+1]" hexmask.long.byte 0x00 0.--7. 1. " ST_0 ,Status register for UDB[n]" rgroup.long 0x188++0x03 line.long 0x00 "UDB_W32_ST2,Status Register 2" hexmask.long.byte 0x00 24.--31. 1. " ST_3 ,Status register for UDB[n+3]" hexmask.long.byte 0x00 16.--23. 1. " ST_2 ,Status register for UDB[n+2]" hexmask.long.byte 0x00 8.--15. 1. " ST_1 ,Status register for UDB[n+1]" hexmask.long.byte 0x00 0.--7. 1. " ST_0 ,Status register for UDB[n]" rgroup.long 0x18C++0x03 line.long 0x00 "UDB_W32_ST3,Status Register 3" hexmask.long.byte 0x00 24.--31. 1. " ST_3 ,Status register for UDB[n+3]" hexmask.long.byte 0x00 16.--23. 1. " ST_2 ,Status register for UDB[n+2]" hexmask.long.byte 0x00 8.--15. 1. " ST_1 ,Status register for UDB[n+1]" hexmask.long.byte 0x00 0.--7. 1. " ST_0 ,Status register for UDB[n]" rgroup.long 0x190++0x03 line.long 0x00 "UDB_W32_ST4,Status Register 4" hexmask.long.byte 0x00 24.--31. 1. " ST_3 ,Status register for UDB[n+3]" hexmask.long.byte 0x00 16.--23. 1. " ST_2 ,Status register for UDB[n+2]" hexmask.long.byte 0x00 8.--15. 1. " ST_1 ,Status register for UDB[n+1]" hexmask.long.byte 0x00 0.--7. 1. " ST_0 ,Status register for UDB[n]" group.long 0x1C0++0x03 line.long 0x00 "UDB_W32_CTL0,Status Control Register 0" hexmask.long.byte 0x00 24.--31. 1. " CTL_3 ,Control register for UDB[n+3]" hexmask.long.byte 0x00 16.--23. 1. " CTL_2 ,Control register for UDB[n+2]" hexmask.long.byte 0x00 8.--15. 1. " CTL_1 ,Control register for UDB[n+1]" hexmask.long.byte 0x00 0.--7. 1. " CTL_0 ,Control register for UDB[n]" group.long 0x1C4++0x03 line.long 0x00 "UDB_W32_CTL1,Status Control Register 1" hexmask.long.byte 0x00 24.--31. 1. " CTL_3 ,Control register for UDB[n+3]" hexmask.long.byte 0x00 16.--23. 1. " CTL_2 ,Control register for UDB[n+2]" hexmask.long.byte 0x00 8.--15. 1. " CTL_1 ,Control register for UDB[n+1]" hexmask.long.byte 0x00 0.--7. 1. " CTL_0 ,Control register for UDB[n]" group.long 0x1C8++0x03 line.long 0x00 "UDB_W32_CTL2,Status Control Register 2" hexmask.long.byte 0x00 24.--31. 1. " CTL_3 ,Control register for UDB[n+3]" hexmask.long.byte 0x00 16.--23. 1. " CTL_2 ,Control register for UDB[n+2]" hexmask.long.byte 0x00 8.--15. 1. " CTL_1 ,Control register for UDB[n+1]" hexmask.long.byte 0x00 0.--7. 1. " CTL_0 ,Control register for UDB[n]" group.long 0x1CC++0x03 line.long 0x00 "UDB_W32_CTL3,Status Control Register 3" hexmask.long.byte 0x00 24.--31. 1. " CTL_3 ,Control register for UDB[n+3]" hexmask.long.byte 0x00 16.--23. 1. " CTL_2 ,Control register for UDB[n+2]" hexmask.long.byte 0x00 8.--15. 1. " CTL_1 ,Control register for UDB[n+1]" hexmask.long.byte 0x00 0.--7. 1. " CTL_0 ,Control register for UDB[n]" group.long 0x1D0++0x03 line.long 0x00 "UDB_W32_CTL4,Status Control Register 4" hexmask.long.byte 0x00 24.--31. 1. " CTL_3 ,Control register for UDB[n+3]" hexmask.long.byte 0x00 16.--23. 1. " CTL_2 ,Control register for UDB[n+2]" hexmask.long.byte 0x00 8.--15. 1. " CTL_1 ,Control register for UDB[n+1]" hexmask.long.byte 0x00 0.--7. 1. " CTL_0 ,Control register for UDB[n]" group.long 0x200++0x03 line.long 0x00 "UDB_W32_MSK0,Interrupt Mask 0" hexmask.long.byte 0x00 24.--31. 1. " MSK_3 ,Interrupt mask register 3" hexmask.long.byte 0x00 16.--23. 1. " MSK_2 ,Interrupt mask register 2" hexmask.long.byte 0x00 8.--15. 1. " MSK_1 ,Interrupt mask register 1" hexmask.long.byte 0x00 0.--7. 1. " MSK_0 ,Interrupt mask register 0" group.long 0x204++0x03 line.long 0x00 "UDB_W32_MSK1,Interrupt Mask 1" hexmask.long.byte 0x00 24.--31. 1. " MSK_3 ,Interrupt mask register 3" hexmask.long.byte 0x00 16.--23. 1. " MSK_2 ,Interrupt mask register 2" hexmask.long.byte 0x00 8.--15. 1. " MSK_1 ,Interrupt mask register 1" hexmask.long.byte 0x00 0.--7. 1. " MSK_0 ,Interrupt mask register 0" group.long 0x208++0x03 line.long 0x00 "UDB_W32_MSK2,Interrupt Mask 2" hexmask.long.byte 0x00 24.--31. 1. " MSK_3 ,Interrupt mask register 3" hexmask.long.byte 0x00 16.--23. 1. " MSK_2 ,Interrupt mask register 2" hexmask.long.byte 0x00 8.--15. 1. " MSK_1 ,Interrupt mask register 1" hexmask.long.byte 0x00 0.--7. 1. " MSK_0 ,Interrupt mask register 0" group.long 0x20C++0x03 line.long 0x00 "UDB_W32_MSK3,Interrupt Mask 3" hexmask.long.byte 0x00 24.--31. 1. " MSK_3 ,Interrupt mask register 3" hexmask.long.byte 0x00 16.--23. 1. " MSK_2 ,Interrupt mask register 2" hexmask.long.byte 0x00 8.--15. 1. " MSK_1 ,Interrupt mask register 1" hexmask.long.byte 0x00 0.--7. 1. " MSK_0 ,Interrupt mask register 0" group.long 0x210++0x03 line.long 0x00 "UDB_W32_MSK4,Interrupt Mask 4" hexmask.long.byte 0x00 24.--31. 1. " MSK_3 ,Interrupt mask register 3" hexmask.long.byte 0x00 16.--23. 1. " MSK_2 ,Interrupt mask register 2" hexmask.long.byte 0x00 8.--15. 1. " MSK_1 ,Interrupt mask register 1" hexmask.long.byte 0x00 0.--7. 1. " MSK_0 ,Interrupt mask register 0" group.long 0x240++0x03 line.long 0x00 "UDB_W32_ACTL0,Auxiliary Control 0" bitfld.long 0x00 29. " CNT_START_3 ,Control register counter 3 enable" "Disabled,Enabled" bitfld.long 0x00 28. " INT_EN_3 ,Enable interrupt 3" "Disabled,Enabled" bitfld.long 0x00 27. " FIFO1_LVL_3 ,FIFO 1 fill status level 3 control" "Normal,Mid" bitfld.long 0x00 26. " FIFO0_LVL_3 ,FIFO 0 fill status level 3 control" "Normal,Mid" textline " " bitfld.long 0x00 25. " FIFO1_CLR_3 ,FIFO 1 clear" "Normal,Clear" bitfld.long 0x00 24. " FIFO0_CLR_3 ,FIFO 0 clear" "Normal,Clear" bitfld.long 0x00 21. " CNT_START_2 ,Control register counter 2 enable" "Disabled,Enabled" bitfld.long 0x00 20. " INT_EN_2 ,Enable interrupt 2" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " FIFO1_LVL_2 ,FIFO 1 fill status level 2 control" "Normal,Mid" bitfld.long 0x00 18. " FIFO0_LVL_2 ,FIFO 0 fill status level 2 control" "Normal,Mid" bitfld.long 0x00 17. " FIFO1_CLR_2 ,FIFO 1 clear 2" "Normal,Clear" bitfld.long 0x00 16. " FIFO0_CLR_2 ,FIFO 0 clear 2" "Normal,Clear" textline " " bitfld.long 0x00 13. " CNT_START_1 ,Control register counter 1 enable" "Disabled,Enabled" bitfld.long 0x00 12. " INT_EN_1 ,Enable interrupt 1" "Disabled,Enabled" bitfld.long 0x00 11. " FIFO1_LVL_1 ,FIFO fill status level control" "Normal,Mid" bitfld.long 0x00 10. " FIFO0_LVL_1 ,FIFO fill status level 1 control" "Normal,Mid" textline " " bitfld.long 0x00 9. " FIFO1_CLR_1 ,FIFO 1 clear 1" "Normal,Clear" bitfld.long 0x00 8. " FIFO0_CLR_1 ,FIFO 0 clear 1" "Normal,Clear" bitfld.long 0x00 5. " CNT_START_0 ,Control register counter 0 enable" "Disabled,Enabled" bitfld.long 0x00 4. " INT_EN_0 ,Enable interrupt 0" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " FIFO1_LVL_0 ,FIFO 1 fill status level 0 control" "Normal,Mid" bitfld.long 0x00 2. " FIFO0_LVL_0 ,FIFO 0 fill status level 0 control" "Normal,Mid" bitfld.long 0x00 1. " FIFO1_CLR_0 ,FIFO 1 clear 0" "Normal,Clear" bitfld.long 0x00 0. " FIFO0_CLR_0 ,FIFO 0 clear 0" "Normal,Clear" group.long 0x244++0x03 line.long 0x00 "UDB_W32_ACTL1,Auxiliary Control 1" bitfld.long 0x00 29. " CNT_START_3 ,Control register counter 3 enable" "Disabled,Enabled" bitfld.long 0x00 28. " INT_EN_3 ,Enable interrupt 3" "Disabled,Enabled" bitfld.long 0x00 27. " FIFO1_LVL_3 ,FIFO 1 fill status level 3 control" "Normal,Mid" bitfld.long 0x00 26. " FIFO0_LVL_3 ,FIFO 0 fill status level 3 control" "Normal,Mid" textline " " bitfld.long 0x00 25. " FIFO1_CLR_3 ,FIFO 1 clear" "Normal,Clear" bitfld.long 0x00 24. " FIFO0_CLR_3 ,FIFO 0 clear" "Normal,Clear" bitfld.long 0x00 21. " CNT_START_2 ,Control register counter 2 enable" "Disabled,Enabled" bitfld.long 0x00 20. " INT_EN_2 ,Enable interrupt 2" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " FIFO1_LVL_2 ,FIFO 1 fill status level 2 control" "Normal,Mid" bitfld.long 0x00 18. " FIFO0_LVL_2 ,FIFO 0 fill status level 2 control" "Normal,Mid" bitfld.long 0x00 17. " FIFO1_CLR_2 ,FIFO 1 clear 2" "Normal,Clear" bitfld.long 0x00 16. " FIFO0_CLR_2 ,FIFO 0 clear 2" "Normal,Clear" textline " " bitfld.long 0x00 13. " CNT_START_1 ,Control register counter 1 enable" "Disabled,Enabled" bitfld.long 0x00 12. " INT_EN_1 ,Enable interrupt 1" "Disabled,Enabled" bitfld.long 0x00 11. " FIFO1_LVL_1 ,FIFO fill status level control" "Normal,Mid" bitfld.long 0x00 10. " FIFO0_LVL_1 ,FIFO fill status level 1 control" "Normal,Mid" textline " " bitfld.long 0x00 9. " FIFO1_CLR_1 ,FIFO 1 clear 1" "Normal,Clear" bitfld.long 0x00 8. " FIFO0_CLR_1 ,FIFO 0 clear 1" "Normal,Clear" bitfld.long 0x00 5. " CNT_START_0 ,Control register counter 0 enable" "Disabled,Enabled" bitfld.long 0x00 4. " INT_EN_0 ,Enable interrupt 0" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " FIFO1_LVL_0 ,FIFO 1 fill status level 0 control" "Normal,Mid" bitfld.long 0x00 2. " FIFO0_LVL_0 ,FIFO 0 fill status level 0 control" "Normal,Mid" bitfld.long 0x00 1. " FIFO1_CLR_0 ,FIFO 1 clear 0" "Normal,Clear" bitfld.long 0x00 0. " FIFO0_CLR_0 ,FIFO 0 clear 0" "Normal,Clear" group.long 0x248++0x03 line.long 0x00 "UDB_W32_ACTL2,Auxiliary Control 2" bitfld.long 0x00 29. " CNT_START_3 ,Control register counter 3 enable" "Disabled,Enabled" bitfld.long 0x00 28. " INT_EN_3 ,Enable interrupt 3" "Disabled,Enabled" bitfld.long 0x00 27. " FIFO1_LVL_3 ,FIFO 1 fill status level 3 control" "Normal,Mid" bitfld.long 0x00 26. " FIFO0_LVL_3 ,FIFO 0 fill status level 3 control" "Normal,Mid" textline " " bitfld.long 0x00 25. " FIFO1_CLR_3 ,FIFO 1 clear" "Normal,Clear" bitfld.long 0x00 24. " FIFO0_CLR_3 ,FIFO 0 clear" "Normal,Clear" bitfld.long 0x00 21. " CNT_START_2 ,Control register counter 2 enable" "Disabled,Enabled" bitfld.long 0x00 20. " INT_EN_2 ,Enable interrupt 2" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " FIFO1_LVL_2 ,FIFO 1 fill status level 2 control" "Normal,Mid" bitfld.long 0x00 18. " FIFO0_LVL_2 ,FIFO 0 fill status level 2 control" "Normal,Mid" bitfld.long 0x00 17. " FIFO1_CLR_2 ,FIFO 1 clear 2" "Normal,Clear" bitfld.long 0x00 16. " FIFO0_CLR_2 ,FIFO 0 clear 2" "Normal,Clear" textline " " bitfld.long 0x00 13. " CNT_START_1 ,Control register counter 1 enable" "Disabled,Enabled" bitfld.long 0x00 12. " INT_EN_1 ,Enable interrupt 1" "Disabled,Enabled" bitfld.long 0x00 11. " FIFO1_LVL_1 ,FIFO fill status level control" "Normal,Mid" bitfld.long 0x00 10. " FIFO0_LVL_1 ,FIFO fill status level 1 control" "Normal,Mid" textline " " bitfld.long 0x00 9. " FIFO1_CLR_1 ,FIFO 1 clear 1" "Normal,Clear" bitfld.long 0x00 8. " FIFO0_CLR_1 ,FIFO 0 clear 1" "Normal,Clear" bitfld.long 0x00 5. " CNT_START_0 ,Control register counter 0 enable" "Disabled,Enabled" bitfld.long 0x00 4. " INT_EN_0 ,Enable interrupt 0" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " FIFO1_LVL_0 ,FIFO 1 fill status level 0 control" "Normal,Mid" bitfld.long 0x00 2. " FIFO0_LVL_0 ,FIFO 0 fill status level 0 control" "Normal,Mid" bitfld.long 0x00 1. " FIFO1_CLR_0 ,FIFO 1 clear 0" "Normal,Clear" bitfld.long 0x00 0. " FIFO0_CLR_0 ,FIFO 0 clear 0" "Normal,Clear" group.long 0x24C++0x03 line.long 0x00 "UDB_W32_ACTL3,Auxiliary Control 3" bitfld.long 0x00 29. " CNT_START_3 ,Control register counter 3 enable" "Disabled,Enabled" bitfld.long 0x00 28. " INT_EN_3 ,Enable interrupt 3" "Disabled,Enabled" bitfld.long 0x00 27. " FIFO1_LVL_3 ,FIFO 1 fill status level 3 control" "Normal,Mid" bitfld.long 0x00 26. " FIFO0_LVL_3 ,FIFO 0 fill status level 3 control" "Normal,Mid" textline " " bitfld.long 0x00 25. " FIFO1_CLR_3 ,FIFO 1 clear" "Normal,Clear" bitfld.long 0x00 24. " FIFO0_CLR_3 ,FIFO 0 clear" "Normal,Clear" bitfld.long 0x00 21. " CNT_START_2 ,Control register counter 2 enable" "Disabled,Enabled" bitfld.long 0x00 20. " INT_EN_2 ,Enable interrupt 2" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " FIFO1_LVL_2 ,FIFO 1 fill status level 2 control" "Normal,Mid" bitfld.long 0x00 18. " FIFO0_LVL_2 ,FIFO 0 fill status level 2 control" "Normal,Mid" bitfld.long 0x00 17. " FIFO1_CLR_2 ,FIFO 1 clear 2" "Normal,Clear" bitfld.long 0x00 16. " FIFO0_CLR_2 ,FIFO 0 clear 2" "Normal,Clear" textline " " bitfld.long 0x00 13. " CNT_START_1 ,Control register counter 1 enable" "Disabled,Enabled" bitfld.long 0x00 12. " INT_EN_1 ,Enable interrupt 1" "Disabled,Enabled" bitfld.long 0x00 11. " FIFO1_LVL_1 ,FIFO fill status level control" "Normal,Mid" bitfld.long 0x00 10. " FIFO0_LVL_1 ,FIFO fill status level 1 control" "Normal,Mid" textline " " bitfld.long 0x00 9. " FIFO1_CLR_1 ,FIFO 1 clear 1" "Normal,Clear" bitfld.long 0x00 8. " FIFO0_CLR_1 ,FIFO 0 clear 1" "Normal,Clear" bitfld.long 0x00 5. " CNT_START_0 ,Control register counter 0 enable" "Disabled,Enabled" bitfld.long 0x00 4. " INT_EN_0 ,Enable interrupt 0" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " FIFO1_LVL_0 ,FIFO 1 fill status level 0 control" "Normal,Mid" bitfld.long 0x00 2. " FIFO0_LVL_0 ,FIFO 0 fill status level 0 control" "Normal,Mid" bitfld.long 0x00 1. " FIFO1_CLR_0 ,FIFO 1 clear 0" "Normal,Clear" bitfld.long 0x00 0. " FIFO0_CLR_0 ,FIFO 0 clear 0" "Normal,Clear" group.long 0x250++0x03 line.long 0x00 "UDB_W32_ACTL4,Auxiliary Control 4" bitfld.long 0x00 29. " CNT_START_3 ,Control register counter 3 enable" "Disabled,Enabled" bitfld.long 0x00 28. " INT_EN_3 ,Enable interrupt 3" "Disabled,Enabled" bitfld.long 0x00 27. " FIFO1_LVL_3 ,FIFO 1 fill status level 3 control" "Normal,Mid" bitfld.long 0x00 26. " FIFO0_LVL_3 ,FIFO 0 fill status level 3 control" "Normal,Mid" textline " " bitfld.long 0x00 25. " FIFO1_CLR_3 ,FIFO 1 clear" "Normal,Clear" bitfld.long 0x00 24. " FIFO0_CLR_3 ,FIFO 0 clear" "Normal,Clear" bitfld.long 0x00 21. " CNT_START_2 ,Control register counter 2 enable" "Disabled,Enabled" bitfld.long 0x00 20. " INT_EN_2 ,Enable interrupt 2" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " FIFO1_LVL_2 ,FIFO 1 fill status level 2 control" "Normal,Mid" bitfld.long 0x00 18. " FIFO0_LVL_2 ,FIFO 0 fill status level 2 control" "Normal,Mid" bitfld.long 0x00 17. " FIFO1_CLR_2 ,FIFO 1 clear 2" "Normal,Clear" bitfld.long 0x00 16. " FIFO0_CLR_2 ,FIFO 0 clear 2" "Normal,Clear" textline " " bitfld.long 0x00 13. " CNT_START_1 ,Control register counter 1 enable" "Disabled,Enabled" bitfld.long 0x00 12. " INT_EN_1 ,Enable interrupt 1" "Disabled,Enabled" bitfld.long 0x00 11. " FIFO1_LVL_1 ,FIFO fill status level control" "Normal,Mid" bitfld.long 0x00 10. " FIFO0_LVL_1 ,FIFO fill status level 1 control" "Normal,Mid" textline " " bitfld.long 0x00 9. " FIFO1_CLR_1 ,FIFO 1 clear 1" "Normal,Clear" bitfld.long 0x00 8. " FIFO0_CLR_1 ,FIFO 0 clear 1" "Normal,Clear" bitfld.long 0x00 5. " CNT_START_0 ,Control register counter 0 enable" "Disabled,Enabled" bitfld.long 0x00 4. " INT_EN_0 ,Enable interrupt 0" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " FIFO1_LVL_0 ,FIFO 1 fill status level 0 control" "Normal,Mid" bitfld.long 0x00 2. " FIFO0_LVL_0 ,FIFO 0 fill status level 0 control" "Normal,Mid" bitfld.long 0x00 1. " FIFO1_CLR_0 ,FIFO 1 clear 0" "Normal,Clear" bitfld.long 0x00 0. " FIFO0_CLR_0 ,FIFO 0 clear 0" "Normal,Clear" rgroup.long 0x280++0x03 line.long 0x00 "UDB_W32_MC0,PLD Macrocell Reading 0" bitfld.long 0x00 28.--31. " PLD1_MC_3 ,Read macrocell 1 for UDB[n+3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " PLD0_MC_3 ,Read macrocell 0 for UDB[n+3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " PLD1_MC_2 ,Read macrocell 1 for UDB[n+2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " PLD0_MC_2 ,Read macrocell 0 for UDB[n+2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--15. " PLD1_MC_1 ,Read macrocell 1 for UDB[n+1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " PLD0_MC_1 ,Read macrocell 0 for UDB[n+1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " PLD1_MC_0 ,Read macrocell 1 for UDB[n]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " PLD0_MC_0 ,Read macrocell 0 for UDB[n]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x284++0x03 line.long 0x00 "UDB_W32_MC1,PLD Macrocell Reading 1" bitfld.long 0x00 28.--31. " PLD1_MC_3 ,Read macrocell 1 for UDB[n+3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " PLD0_MC_3 ,Read macrocell 0 for UDB[n+3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " PLD1_MC_2 ,Read macrocell 1 for UDB[n+2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " PLD0_MC_2 ,Read macrocell 0 for UDB[n+2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--15. " PLD1_MC_1 ,Read macrocell 1 for UDB[n+1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " PLD0_MC_1 ,Read macrocell 0 for UDB[n+1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " PLD1_MC_0 ,Read macrocell 1 for UDB[n]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " PLD0_MC_0 ,Read macrocell 0 for UDB[n]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x288++0x03 line.long 0x00 "UDB_W32_MC2,PLD Macrocell Reading 2" bitfld.long 0x00 28.--31. " PLD1_MC_3 ,Read macrocell 1 for UDB[n+3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " PLD0_MC_3 ,Read macrocell 0 for UDB[n+3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " PLD1_MC_2 ,Read macrocell 1 for UDB[n+2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " PLD0_MC_2 ,Read macrocell 0 for UDB[n+2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--15. " PLD1_MC_1 ,Read macrocell 1 for UDB[n+1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " PLD0_MC_1 ,Read macrocell 0 for UDB[n+1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " PLD1_MC_0 ,Read macrocell 1 for UDB[n]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " PLD0_MC_0 ,Read macrocell 0 for UDB[n]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x28C++0x03 line.long 0x00 "UDB_W32_MC3,PLD Macrocell Reading 3" bitfld.long 0x00 28.--31. " PLD1_MC_3 ,Read macrocell 1 for UDB[n+3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " PLD0_MC_3 ,Read macrocell 0 for UDB[n+3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " PLD1_MC_2 ,Read macrocell 1 for UDB[n+2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " PLD0_MC_2 ,Read macrocell 0 for UDB[n+2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--15. " PLD1_MC_1 ,Read macrocell 1 for UDB[n+1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " PLD0_MC_1 ,Read macrocell 0 for UDB[n+1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " PLD1_MC_0 ,Read macrocell 1 for UDB[n]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " PLD0_MC_0 ,Read macrocell 0 for UDB[n]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x290++0x03 line.long 0x00 "UDB_W32_MC4,PLD Macrocell Reading 4" bitfld.long 0x00 28.--31. " PLD1_MC_3 ,Read macrocell 1 for UDB[n+3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. " PLD0_MC_3 ,Read macrocell 0 for UDB[n+3]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. " PLD1_MC_2 ,Read macrocell 1 for UDB[n+2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. " PLD0_MC_2 ,Read macrocell 0 for UDB[n+2]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--15. " PLD1_MC_1 ,Read macrocell 1 for UDB[n+1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. " PLD0_MC_1 ,Read macrocell 0 for UDB[n+1]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. " PLD1_MC_0 ,Read macrocell 1 for UDB[n]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " PLD0_MC_0 ,Read macrocell 0 for UDB[n]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0x0B tree.end tree "UDB Interface registers" base ad:0x400F7000 width 21. group.byte 0x00++0x01 line.byte 0x00 "UDB_UDB_BANK_CTL,Bank Control" bitfld.byte 0x00 7. " GLBL_WR ,UDB array global writing option" "Disabled,Enabled" bitfld.byte 0x00 4. " PIPE ,Pipelining control" "BYPASS,PIPELINED" bitfld.byte 0x00 2. " BANK_EN ,Enable bank" "Disabled,Enabled" bitfld.byte 0x00 1. " ROUTE_EN ,Enable routing" "Disabled,Enabled" textline " " bitfld.byte 0x00 0. " DIS_COR ,Selection of Clear-On-Read" "NORMAL,DISABLED" line.byte 0x01 "UDB_UDB_WAIT_CFG,Wait States Configuration" bitfld.byte 0x01 6.--7. " WR_WRK_WAIT ,Write work wait states" "2 waits,3 waits,4 waits,Illegal" bitfld.byte 0x01 4.--5. " RD_WRK_WAIT ,Read work wait states" "2 waits,3 waits,4 waits,Illegal" bitfld.byte 0x01 2.--3. " WR_CFG_WAIT ,Write configuration wait states" "2 waits,3 waits,4 waits,Illegal" bitfld.byte 0x01 0.--1. " RD_CFG_WAIT ,Read configuration wait states" "6 waits,5 waits,4 waits,2 waits" group.byte 0x1C++0x00 line.byte 0x00 "UDB_UDB_INT_CLK_CTL,Interrupt Synchronizer Clock Control" bitfld.byte 0x00 0. " INT_CLK_ENABLE ,Interrupt synchronizer in the UDB interface" "Disabled,Enabled" group.byte 0x20++0x00 line.byte 0x00 "UDB_UDB_TR_CLK_CTL,Trigger Clock Control" bitfld.byte 0x00 0. " TR_CLOCK_ENABLE ,Enable clock and reset of the DMA request logic" "Disabled,Enabled" group.long 0x100++0x03 line.long 0x00 "UDB_UDB_TR_CFG,Trigger Configuration" width 0x0B tree.end tree "UDBSNG Registers" tree "UDB P0 U0" base ad:0x400F3000 width 22. group.long 0x0++0x03 line.long 0x00 "PLD_IT0,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT0T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT0T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT0T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT0T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT0T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT0T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT0T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT0T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT0T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT0T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT0T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT0T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT0T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT0T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT0T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT0T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT0C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT0C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT0C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT0C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT0C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT0C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT0C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT0C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT0C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT0C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT0C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT0C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT0C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT0C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT0C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT0C_0 ,PLD0 complement input term 0" "0,1" group.long 0x4++0x03 line.long 0x00 "PLD_IT1,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT1T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT1T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT1T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT1T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT1T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT1T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT1T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT1T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT1T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT1T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT1T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT1T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT1T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT1T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT1T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT1T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT1C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT1C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT1C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT1C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT1C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT1C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT1C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT1C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT1C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT1C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT1C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT1C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT1C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT1C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT1C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT1C_0 ,PLD0 complement input term 0" "0,1" group.long 0x8++0x03 line.long 0x00 "PLD_IT2,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT2T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT2T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT2T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT2T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT2T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT2T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT2T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT2T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT2T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT2T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT2T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT2T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT2T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT2T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT2T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT2T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT2C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT2C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT2C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT2C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT2C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT2C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT2C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT2C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT2C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT2C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT2C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT2C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT2C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT2C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT2C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT2C_0 ,PLD0 complement input term 0" "0,1" group.long 0xC++0x03 line.long 0x00 "PLD_IT3,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT3T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT3T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT3T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT3T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT3T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT3T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT3T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT3T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT3T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT3T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT3T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT3T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT3T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT3T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT3T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT3T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT3C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT3C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT3C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT3C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT3C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT3C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT3C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT3C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT3C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT3C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT3C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT3C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT3C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT3C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT3C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT3C_0 ,PLD0 complement input term 0" "0,1" group.long 0x10++0x03 line.long 0x00 "PLD_IT4,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT4T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT4T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT4T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT4T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT4T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT4T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT4T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT4T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT4T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT4T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT4T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT4T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT4T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT4T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT4T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT4T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT4C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT4C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT4C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT4C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT4C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT4C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT4C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT4C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT4C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT4C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT4C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT4C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT4C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT4C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT4C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT4C_0 ,PLD0 complement input term 0" "0,1" group.long 0x14++0x03 line.long 0x00 "PLD_IT5,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT5T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT5T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT5T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT5T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT5T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT5T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT5T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT5T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT5T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT5T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT5T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT5T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT5T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT5T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT5T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT5T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT5C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT5C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT5C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT5C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT5C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT5C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT5C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT5C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT5C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT5C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT5C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT5C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT5C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT5C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT5C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT5C_0 ,PLD0 complement input term 0" "0,1" group.long 0x18++0x03 line.long 0x00 "PLD_IT6,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT6T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT6T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT6T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT6T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT6T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT6T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT6T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT6T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT6T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT6T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT6T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT6T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT6T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT6T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT6T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT6T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT6C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT6C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT6C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT6C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT6C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT6C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT6C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT6C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT6C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT6C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT6C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT6C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT6C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT6C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT6C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT6C_0 ,PLD0 complement input term 0" "0,1" group.long 0x1C++0x03 line.long 0x00 "PLD_IT7,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT7T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT7T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT7T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT7T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT7T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT7T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT7T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT7T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT7T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT7T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT7T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT7T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT7T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT7T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT7T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT7T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT7C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT7C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT7C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT7C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT7C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT7C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT7C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT7C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT7C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT7C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT7C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT7C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT7C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT7C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT7C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT7C_0 ,PLD0 complement input term 0" "0,1" group.long 0x20++0x03 line.long 0x00 "PLD_IT8,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT8T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT8T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT8T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT8T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT8T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT8T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT8T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT8T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT8T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT8T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT8T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT8T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT8T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT8T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT8T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT8T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT8C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT8C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT8C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT8C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT8C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT8C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT8C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT8C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT8C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT8C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT8C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT8C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT8C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT8C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT8C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT8C_0 ,PLD0 complement input term 0" "0,1" group.long 0x24++0x03 line.long 0x00 "PLD_IT9,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT9T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT9T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT9T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT9T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT9T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT9T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT9T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT9T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT9T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT9T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT9T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT9T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT9T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT9T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT9T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT9T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT9C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT9C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT9C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT9C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT9C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT9C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT9C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT9C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT9C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT9C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT9C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT9C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT9C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT9C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT9C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT9C_0 ,PLD0 complement input term 0" "0,1" group.long 0x28++0x03 line.long 0x00 "PLD_IT10,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT10T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT10T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT10T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT10T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT10T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT10T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT10T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT10T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT10T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT10T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT10T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT10T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT10T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT10T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT10T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT10T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT10C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT10C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT10C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT10C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT10C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT10C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT10C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT10C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT10C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT10C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT10C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT10C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT10C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT10C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT10C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT10C_0 ,PLD0 complement input term 0" "0,1" group.long 0x2C++0x03 line.long 0x00 "PLD_IT11,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT11T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT11T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT11T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT11T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT11T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT11T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT11T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT11T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT11T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT11T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT11T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT11T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT11T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT11T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT11T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT11T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT11C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT11C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT11C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT11C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT11C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT11C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT11C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT11C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT11C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT11C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT11C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT11C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT11C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT11C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT11C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT11C_0 ,PLD0 complement input term 0" "0,1" group.word 0x30++0x01 line.word 0x00 "PLD_ORT0,PLD OR Terms" bitfld.word 0x00 15. " PLD1_ORT_PT0_7 ,PLD1 OR term 7" "0,1" bitfld.word 0x00 14. " PLD1_ORT_PT0_6 ,PLD1 OR term 6" "0,1" bitfld.word 0x00 13. " PLD1_ORT_PT0_5 ,PLD1 OR term 5" "0,1" bitfld.word 0x00 12. " PLD1_ORT_PT0_4 ,PLD1 OR term 4" "0,1" textline " " bitfld.word 0x00 11. " PLD1_ORT_PT0_3 ,PLD1 OR term 3" "0,1" bitfld.word 0x00 10. " PLD1_ORT_PT0_2 ,PLD1 OR term 2" "0,1" bitfld.word 0x00 9. " PLD1_ORT_PT0_1 ,PLD1 OR term 1" "0,1" bitfld.word 0x00 8. " PLD1_ORT_PT0_0 ,PLD1 OR term 0" "0,1" textline " " bitfld.word 0x00 7. " PLD0_ORT_PT0_7 ,PLD0 OR term 7" "0,1" bitfld.word 0x00 6. " PLD0_ORT_PT0_6 ,PLD0 OR term 6" "0,1" bitfld.word 0x00 5. " PLD0_ORT_PT0_5 ,PLD0 OR term 5" "0,1" bitfld.word 0x00 4. " PLD0_ORT_PT0_4 ,PLD0 OR term 4" "0,1" textline " " bitfld.word 0x00 3. " PLD0_ORT_PT0_3 ,PLD0 OR term 3" "0,1" bitfld.word 0x00 2. " PLD0_ORT_PT0_2 ,PLD0 OR term 2" "0,1" bitfld.word 0x00 1. " PLD0_ORT_PT0_1 ,PLD0 OR term 1" "0,1" bitfld.word 0x00 0. " PLD0_ORT_PT0_0 ,PLD0 OR term 0" "0,1" group.word 0x32++0x01 line.word 0x00 "PLD_ORT1,PLD OR Terms" bitfld.word 0x00 15. " PLD1_ORT_PT1_7 ,PLD1 OR term 7" "0,1" bitfld.word 0x00 14. " PLD1_ORT_PT1_6 ,PLD1 OR term 6" "0,1" bitfld.word 0x00 13. " PLD1_ORT_PT1_5 ,PLD1 OR term 5" "0,1" bitfld.word 0x00 12. " PLD1_ORT_PT1_4 ,PLD1 OR term 4" "0,1" textline " " bitfld.word 0x00 11. " PLD1_ORT_PT1_3 ,PLD1 OR term 3" "0,1" bitfld.word 0x00 10. " PLD1_ORT_PT1_2 ,PLD1 OR term 2" "0,1" bitfld.word 0x00 9. " PLD1_ORT_PT1_1 ,PLD1 OR term 1" "0,1" bitfld.word 0x00 8. " PLD1_ORT_PT1_0 ,PLD1 OR term 0" "0,1" textline " " bitfld.word 0x00 7. " PLD0_ORT_PT1_7 ,PLD0 OR term 7" "0,1" bitfld.word 0x00 6. " PLD0_ORT_PT1_6 ,PLD0 OR term 6" "0,1" bitfld.word 0x00 5. " PLD0_ORT_PT1_5 ,PLD0 OR term 5" "0,1" bitfld.word 0x00 4. " PLD0_ORT_PT1_4 ,PLD0 OR term 4" "0,1" textline " " bitfld.word 0x00 3. " PLD0_ORT_PT1_3 ,PLD0 OR term 3" "0,1" bitfld.word 0x00 2. " PLD0_ORT_PT1_2 ,PLD0 OR term 2" "0,1" bitfld.word 0x00 1. " PLD0_ORT_PT1_1 ,PLD0 OR term 1" "0,1" bitfld.word 0x00 0. " PLD0_ORT_PT1_0 ,PLD0 OR term 0" "0,1" group.word 0x34++0x01 line.word 0x00 "PLD_ORT2,PLD OR Terms" bitfld.word 0x00 15. " PLD1_ORT_PT2_7 ,PLD1 OR term 7" "0,1" bitfld.word 0x00 14. " PLD1_ORT_PT2_6 ,PLD1 OR term 6" "0,1" bitfld.word 0x00 13. " PLD1_ORT_PT2_5 ,PLD1 OR term 5" "0,1" bitfld.word 0x00 12. " PLD1_ORT_PT2_4 ,PLD1 OR term 4" "0,1" textline " " bitfld.word 0x00 11. " PLD1_ORT_PT2_3 ,PLD1 OR term 3" "0,1" bitfld.word 0x00 10. " PLD1_ORT_PT2_2 ,PLD1 OR term 2" "0,1" bitfld.word 0x00 9. " PLD1_ORT_PT2_1 ,PLD1 OR term 1" "0,1" bitfld.word 0x00 8. " PLD1_ORT_PT2_0 ,PLD1 OR term 0" "0,1" textline " " bitfld.word 0x00 7. " PLD0_ORT_PT2_7 ,PLD0 OR term 7" "0,1" bitfld.word 0x00 6. " PLD0_ORT_PT2_6 ,PLD0 OR term 6" "0,1" bitfld.word 0x00 5. " PLD0_ORT_PT2_5 ,PLD0 OR term 5" "0,1" bitfld.word 0x00 4. " PLD0_ORT_PT2_4 ,PLD0 OR term 4" "0,1" textline " " bitfld.word 0x00 3. " PLD0_ORT_PT2_3 ,PLD0 OR term 3" "0,1" bitfld.word 0x00 2. " PLD0_ORT_PT2_2 ,PLD0 OR term 2" "0,1" bitfld.word 0x00 1. " PLD0_ORT_PT2_1 ,PLD0 OR term 1" "0,1" bitfld.word 0x00 0. " PLD0_ORT_PT2_0 ,PLD0 OR term 0" "0,1" group.word 0x36++0x01 line.word 0x00 "PLD_ORT3,PLD OR Terms" bitfld.word 0x00 15. " PLD1_ORT_PT3_7 ,PLD1 OR term 7" "0,1" bitfld.word 0x00 14. " PLD1_ORT_PT3_6 ,PLD1 OR term 6" "0,1" bitfld.word 0x00 13. " PLD1_ORT_PT3_5 ,PLD1 OR term 5" "0,1" bitfld.word 0x00 12. " PLD1_ORT_PT3_4 ,PLD1 OR term 4" "0,1" textline " " bitfld.word 0x00 11. " PLD1_ORT_PT3_3 ,PLD1 OR term 3" "0,1" bitfld.word 0x00 10. " PLD1_ORT_PT3_2 ,PLD1 OR term 2" "0,1" bitfld.word 0x00 9. " PLD1_ORT_PT3_1 ,PLD1 OR term 1" "0,1" bitfld.word 0x00 8. " PLD1_ORT_PT3_0 ,PLD1 OR term 0" "0,1" textline " " bitfld.word 0x00 7. " PLD0_ORT_PT3_7 ,PLD0 OR term 7" "0,1" bitfld.word 0x00 6. " PLD0_ORT_PT3_6 ,PLD0 OR term 6" "0,1" bitfld.word 0x00 5. " PLD0_ORT_PT3_5 ,PLD0 OR term 5" "0,1" bitfld.word 0x00 4. " PLD0_ORT_PT3_4 ,PLD0 OR term 4" "0,1" textline " " bitfld.word 0x00 3. " PLD0_ORT_PT3_3 ,PLD0 OR term 3" "0,1" bitfld.word 0x00 2. " PLD0_ORT_PT3_2 ,PLD0 OR term 2" "0,1" bitfld.word 0x00 1. " PLD0_ORT_PT3_1 ,PLD0 OR term 1" "0,1" bitfld.word 0x00 0. " PLD0_ORT_PT3_0 ,PLD0 OR term 0" "0,1" group.word 0x38++0x07 line.word 0x00 "PLD_MC_CFG_CEN_CONST,Macrocell Configuration For Carry Enable And Constant" bitfld.word 0x00 15. " PLD1_MC3_DFF_C ,PLD1 MC3 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 14. " PLD1_MC3_CEN ,PLD1 MC3 carry enable" "Disabled,Enabled" bitfld.word 0x00 13. " PLD1_MC2_DFF_C ,PLD1 MC2 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 12. " PLD1_MC2_CEN ,PLD1 MC2 carry enable" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " PLD1_MC1_DFF_C ,PLD1 MC1 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 10. " PLD1_MC1_CEN ,PLD1 MC1 carry enable" "Disabled,Enabled" bitfld.word 0x00 9. " PLD1_MC0_DFF_C ,PLD1 MC0 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 8. " PLD1_MC0_CEN ,PLD1 MC0 carry enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " PLD0_MC3_DFF_C ,PLD0 MC3 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 6. " PLD0_MC3_CEN ,PLD0 MC3 carry enable" "Disabled,Enabled" bitfld.word 0x00 5. " PLD0_MC2_DFF_C ,PLD0 MC2 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 4. " PLD0_MC2_CEN ,PLD0 MC2 carry enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " PLD0_MC1_DFF_C ,PLD0 MC1 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 2. " PLD0_MC1_CEN ,PLD0 MC1 carry enable" "Disabled,Enabled" bitfld.word 0x00 1. " PLD0_MC0_DFF_C ,PLD0 MC0 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 0. " PLD0_MC0_CEN ,PLD0_MC0 carry enable" "Disabled,Enabled" line.word 0x02 "PLD_MC_CFG_XORFB,PLD Macro Cell XOR Feedback" bitfld.word 0x02 14.--15. " PLD1_MC3_XORFB ,PLD1 MC3 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" bitfld.word 0x02 12.--13. " PLD1_MC2_XORFB ,PLD1 MC2 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" bitfld.word 0x02 10.--11. " PLD1_MC1_XORFB ,PLD1 MC1 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" bitfld.word 0x02 8.--9. " PLD1_MC0_XORFB ,PLD1 MC0 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" textline " " bitfld.word 0x02 6.--7. " PLD0_MC3_XORFB ,PLD0 MC3 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" bitfld.word 0x02 4.--5. " PLD0_MC2_XORFB ,PLD0 MC2 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" bitfld.word 0x02 2.--3. " PLD0_MC1_XORFB ,PLD0 MC1 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" bitfld.word 0x02 0.--1. " PLD0_MC0_XORFB ,PLD0 MC0 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" line.word 0x04 "PLD_MC_SET_RESET,PLD Macro Cell Set Reset Selection" bitfld.word 0x04 15. " PLD1_MC3_RESET_SEL ,PLD1 MC3 reset select enable" "Disabled,Enabled" bitfld.word 0x04 14. " PLD1_MC3_SET_SEL ,PLD1 MC3 set select enable" "Disabled,Enabled" bitfld.word 0x04 13. " PLD1_MC2_RESET_SEL ,PLD1 MC2 reset select enable" "Disabled,Enabled" bitfld.word 0x04 12. " PLD1_MC2_SET_SEL ,PLD1 MC2 set select enable" "Disabled,Enabled" textline " " bitfld.word 0x04 11. " PLD1_MC1_RESET_SEL ,PLD1 MC1 reset select enable" "Disabled,Enabled" bitfld.word 0x04 10. " PLD1_MC1_SET_SEL ,PLD1 MC0 set select enable" "Disabled,Enabled" bitfld.word 0x04 9. " PLD1_MC0_RESET_SEL ,PLD1 MC0 reset select enable" "Disabled,Enabled" bitfld.word 0x04 8. " PLD1_MC0_SET_SEL ,PLD1 MC0 set select enable" "Disabled,Enabled" textline " " bitfld.word 0x04 7. " PLD0_MC3_RESET_SEL ,PLD0 MC3 reset select enable" "Disabled,Enabled" bitfld.word 0x04 6. " PLD0_MC3_SET_SEL ,PLD0 MC3 set select enable" "Disabled,Enabled" bitfld.word 0x04 5. " PLD0_MC2_RESET_SEL ,PLD0 MC2 reset select enable" "Disabled,Enabled" bitfld.word 0x04 4. " PLD0_MC2_SET_SEL ,PLD0 MC2 set select enable" "Disabled,Enabled" textline " " bitfld.word 0x04 3. " PLD0_MC1_RESET_SEL ,PLD0 MC1 reset select enable" "Disabled,Enabled" bitfld.word 0x04 2. " PLD0_MC1_SET_SEL ,PLD0 MC1 set select enable" "Disabled,Enabled" bitfld.word 0x04 1. " PLD0_MC0_RESET_SEL ,Reset select enable" "Disabled,Enabled" bitfld.word 0x04 0. " PLD0_MC0_SET_SEL ,PLD0 MC0 set select enable" "Disabled,Enabled" line.word 0x06 "PLD_MC_CFG_BYPASS,PLD Macro Cell Bypass Control" bitfld.word 0x06 15. " NC15 ,Spare register bit NC15" "0,1" bitfld.word 0x06 14. " PLD1_MC3_BYPASS ,PLD1 MC3 bypass selection" "REGISTER,COMBINATIONAL" bitfld.word 0x06 13. " NC13 ,Spare register bit NC13" "0,1" bitfld.word 0x06 12. " PLD1_MC2_BYPASS ,PLD1 MC2 bypass selection" "REGISTER,COMBINATIONAL" textline " " bitfld.word 0x06 11. " NC11 ,Spare register bit NC11" "0,1" bitfld.word 0x06 10. " PLD1_MC1_BYPASS ,PLD1 MC1 bypass selection" "REGISTER,COMBINATIONAL" bitfld.word 0x06 9. " NC9 ,Spare register bit NC9" "0,1" bitfld.word 0x06 8. " PLD1_MC0_BYPASS ,PLD1 MC0 bypass selection" "REGISTER,COMBINATIONAL" textline " " bitfld.word 0x06 7. " NC7 ,Spare register bit NC7" "0,1" bitfld.word 0x06 6. " PLD0_MC3_BYPASS ,PLD0 MC3 bypass selection" "REGISTER,COMBINATIONAL" bitfld.word 0x06 5. " NC5 ,Spare register bit NC5" "0,1" bitfld.word 0x06 4. " PLD0_MC2_BYPASS ,PLD0 MC2 bypass selection" "REGISTER,COMBINATIONAL" textline " " bitfld.word 0x06 3. " NC3 ,Spare register bit NC3" "0,1" bitfld.word 0x06 2. " PLD0_MC1_BYPASS ,PLD0 MC1 bypass selection" "REGISTER,COMBINATIONAL" bitfld.word 0x06 1. " NC1 ,Spare register bit NC1" "0,1" bitfld.word 0x06 0. " PLD0_MC0_BYPASS ,PLD0 MC0 bypass selection" "REGISTER,COMBINATIONAL" group.byte 0x40++0x17 line.byte 0x00 "CFG0,Datapath Input Selection - RAD1 RAD0. Address Bits 0 And 1 To The Dynamic Configuration RAM" bitfld.byte 0x00 4.--6. " RAD1 ,Datapath permutable input mux RAD1" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." bitfld.byte 0x00 0.--2. " RAD0 ,Datapath permutable input mux RAD0" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." line.byte 0x01 "CFG1,Datapath Input Selection - RAD2. Address Bit 2 To The Dynamic Configuration RAM" bitfld.byte 0x01 7. " DP_RTE_BYPASS4 ,Dp_in bypass control 4" "DP_IN4_ROUTE,DP_IN4_BYPASS" bitfld.byte 0x01 6. " DP_RTE_BYPASS3 ,Dp_in bypass control 3" "DP_IN3_ROUTE,DP_IN3_BYPASS" bitfld.byte 0x01 5. " DP_RTE_BYPASS2 ,Dp_in bypass control 2" "DP_IN2_ROUTE,DP_IN2_BYPASS" bitfld.byte 0x01 4. " DP_RTE_BYPASS1 ,Dp_in bypass control 1" "DP_IN1_ROUTE,DP_IN1_BYPASS" textline " " bitfld.byte 0x01 3. " DP_RTE_BYPASS0 ,Dp_in bypass control 0" "DP_IN0_ROUTE,DP_IN0_BYPASS" bitfld.byte 0x01 0.--2. " RAD2 ,Datapath permutable input mux 2" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." line.byte 0x02 "CFG2,Datapath Input Selection - F1_LD, F0_LD" bitfld.byte 0x02 7. " NC7 ,Spare register bit NC7" "0,1" bitfld.byte 0x02 4.--6. " F1_LD ,Datapath permutable input mux F1_LD" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." bitfld.byte 0x02 3. " DP_RTE_BYPASS5 ,Dp_in bypass control 5" "DP_IN5_ROUTE,DP_IN5_BYPASS" bitfld.byte 0x02 0.--2. " F0_LD ,Datapath permutable input mux F0_LD" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." line.byte 0x03 "CFG3,Datapath Input Selection - D1_LD, D0_LD" bitfld.byte 0x03 4.--6. " D1_LD ,Datapath permutable input mux D1_LD" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." bitfld.byte 0x03 0.--2. " D0_LD ,Datapath permutable input mux D0_LD" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." line.byte 0x04 "CFG4,Datapath Input Selection - CI_MUX SI_MUX" bitfld.byte 0x04 4.--6. " CI_MUX ,Datapath permutable input mux CI_MUX" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." bitfld.byte 0x04 0.--2. " SI_MUX ,Datapath permutable input mux SI_MUX" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." line.byte 0x05 "CFG5,Datapath Output Selection For OUT1 OUT0" bitfld.byte 0x05 4.--7. " OUT1 ,Datapath permutable output mux OUT1" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT" bitfld.byte 0x05 0.--3. " OUT0 ,Datapath permutable output mux OUT0" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT" line.byte 0x06 "CFG6,Datapath Output Selection For OUT3 OUT2" bitfld.byte 0x06 4.--7. " OUT3 ,Datapath permutable output mux OUT3" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT" bitfld.byte 0x06 0.--3. " OUT2 ,Datapath permutable output mux OUT2" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT" line.byte 0x07 "CFG7,Datapath Output Selection For OUT5 OUT4" bitfld.byte 0x07 4.--7. " OUT5 ,Datapath permutable output mux OUT5" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT" bitfld.byte 0x07 0.--3. " OUT4 ,Datapath permutable output mux OUT4" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT" line.byte 0x08 "CFG8,Datapath Output Synchronization Option" bitfld.byte 0x08 7. " NC7 ,Spare register bit NC7" "0,1" bitfld.byte 0x08 6. " NC6 ,Spare register bit NC6" "0,1" bitfld.byte 0x08 0.--5. " OUT_SYNC ,Datapath output synchronization" "REGISTERED,COMBINATIONAL,?..." line.byte 0x09 "CFG9,Datapath ALU Mask" line.byte 0x0A "CFG10,Datapath Compare 0 Mask" line.byte 0x0B "CFG11,Datapath Compare 1 Mask" line.byte 0x0C "CFG12,Datapath Mask Enables And Shift In Configuration" bitfld.byte 0x0C 7. " CMASK1_EN ,Datapath mask CMASK1 enable" "Disabled,Enabled" bitfld.byte 0x0C 6. " CMASK0_EN ,Datapath mask CMASK0 enable" "Disabled,Enabled" bitfld.byte 0x0C 5. " AMASK_EN ,Datapath mask AMASK enable" "Disabled,Enabled" bitfld.byte 0x0C 4. " DEF_SI ,Datapath default shift value" "DEFAULT_0,DEFAULT_1" textline " " bitfld.byte 0x0C 2.--3. " SI_SELB ,Datapath shift in source select" "DEFAULT,REGISTERED,ROUTE,CHAIN" bitfld.byte 0x0C 0.--1. " SI_SELA ,Datapath shift in source select" "DEFAULT,REGISTERED,ROUTE,CHAIN" line.byte 0x0D "CFG13,Datapath Carry In And Compare Configuration" bitfld.byte 0x0D 6.--7. " CMP_SELB ,Datapath compare select B" "A1_D1,A1_A0,A0_D1,A0_A0" bitfld.byte 0x0D 4.--5. " CMP_SELA ,Datapath compare select A" "A1_D1,A1_A0,A0_D1,A0_A0" bitfld.byte 0x0D 2.--3. " CI_SELB ,Datapath carry in source select B" "DEFAULT,REGISTERED,ROUTE,CHAIN" bitfld.byte 0x0D 0.--1. " CI_SELA ,Datapath carry in source select A" "DEFAULT,REGISTERED,ROUTE,CHAIN" line.byte 0x0E "CFG14,Datapath Chaining And MSB Configuration" bitfld.byte 0x0E 7. " MSB_EN ,Datapath MSB selection enable" "Disabled,Enabled" bitfld.byte 0x0E 4.--6. " MSB_SEL ,Datapath MSB selection" "BIT0,BIT1,BIT2,BIT3,BIT4,BIT5,BIT6,BIT7" bitfld.byte 0x0E 3. " CHAIN_CMSB ,Datapath CRC MSB chaining enable" "Disabled,Enabled" bitfld.byte 0x0E 2. " CHAIN_FB ,Datapath CRC feedback chaining enable" "Disabled,Enabled" textline " " bitfld.byte 0x0E 1. " CHAIN1 ,Datapath condition chaining enable 1" "Disabled,Enabled" bitfld.byte 0x0E 0. " CHAIN0 ,Datapath condition chaining enable 0" "Disabled,Enabled" line.byte 0x0F "CFG15,Datapath FIFO, Shift And Parallel Input Control" bitfld.byte 0x0F 7. " PI_SEL ,Datapath parallel input selection" "NORMAL,PARALLEL" bitfld.byte 0x0F 6. " SHIFT_SEL ,Datapath shift out selection" "SOL_MSB,SOR" bitfld.byte 0x0F 5. " PI_DYN ,Enable for dynamic control of parallel data input (Pi) mux" "Disabled,Enabled" bitfld.byte 0x0F 4. " MSB_SI ,Arithmetic shift right operation shift in selection" "DEFAULT,MSB" textline " " bitfld.byte 0x0F 2.--3. " F1_INSEL ,Datapath FIFO configuration 1" "INPUT,OUTPUT_A0,OUTPUT_A1,OUTPUT_ALU" bitfld.byte 0x0F 0.--1. " F0_INSEL ,Datapath FIFO configuration 0" "INPUT,OUTPUT_A0,OUTPUT_A1,OUTPUT_ALU" line.byte 0x10 "CFG16,Datapath FIFO And Register Access Configuration Control" bitfld.byte 0x10 7. " F1_CK_INV ,FIFO 1 clock Inverted" "NORMAL,Inverted" bitfld.byte 0x10 6. " F0_CK_INV ,FIFO 0 clock Inverted" "NORMAL,Inverted" bitfld.byte 0x10 5. " FIFO_FAST ,FIFO fast mode" "Disabled,Enabled" bitfld.byte 0x10 4. " FIFO_CAP ,FIFO software capture mode" "Disabled,Enabled" textline " " bitfld.byte 0x10 3. " FIFO_EDGE ,Edge/level sensitive FIFO write control (Fx_ld)" "LEVEL,EDGE" bitfld.byte 0x10 2. " FIFO_ASYNC ,Asynchronous FIFO clocking support" "Disabled,Enabled" bitfld.byte 0x10 1. " EXT_CRCPRS ,External CRC/PRS mode" "INTERNAL,EXTERNAL" bitfld.byte 0x10 0. " WRK16_CONCAT ,Datapath register access mode" "DEFAULT,CONCATENATE" line.byte 0x11 "CFG17,Datapath FIFO Control" bitfld.byte 0x11 4. " FIFO_ADD_SYNC ,Sync flip-flop to FIFO block status" "Disabled,Enabled" bitfld.byte 0x11 3. " NC3 ,Spare register bit NC3" "0,1" bitfld.byte 0x11 2. " NC2 ,Spare register bit NC2" "0,1" bitfld.byte 0x11 1. " F1_DYN ,FIFO 1 direction" "STATIC,DYNAMIC" textline " " bitfld.byte 0x11 0. " F0_DYN ,FIFO 0 direction" "STATIC,DYNAMIC" line.byte 0x12 "CFG18,Control Register Mode 0" line.byte 0x13 "CFG19,Control Register Mode 1" line.byte 0x14 "CFG20,Status Register Input Mode Selection" bitfld.byte 0x14 7. " STAT_MD[7] ,Bit 7 status input mode select" "Transparent,Sticky cleared" bitfld.byte 0x14 6. " [6] ,Bit 6 status input mode select" "Transparent,Sticky cleared" bitfld.byte 0x14 5. " [5] ,Bit 5 status input mode select" "Transparent,Sticky cleared" bitfld.byte 0x14 4. " [4] ,Bit 4 status input mode select" "Transparent,Sticky cleared" textline " " bitfld.byte 0x14 3. " [3] ,Bit 3 status input mode select" "Transparent,Sticky cleared" bitfld.byte 0x14 2. " [2] ,Bit 2 status input mode select" "Transparent,Sticky cleared" bitfld.byte 0x14 1. " [1] ,Bit 1 status input mode select" "Transparent,Sticky cleared" bitfld.byte 0x14 0. " [0] ,Bit 0 status input mode select" "Transparent,Sticky cleared" line.byte 0x15 "CFG21,Spare Register Bits" bitfld.byte 0x15 1. " NC1 ,Spare register bit NC1" "0,1" bitfld.byte 0x15 0. " NC0 ,Spare register bit NC0" "0,1" line.byte 0x16 "CFG22,SC Block Configuration Control" bitfld.byte 0x16 4. " SC_EXT_RES ,Control register external reset operation" "Disabled,Enabled" bitfld.byte 0x16 3. " SC_SYNC_MD ,SC sync mode" "NORMAL,SYNC_MODE" bitfld.byte 0x16 2. " SC_INT_MD ,SC interrupt mode" "NORMAL,INT_MODE" bitfld.byte 0x16 0.--1. " SC_OUT_CTL ,Output source for the status and control routing connections" "CONTROL,PARALLEL,COUNTER,?..." line.byte 0x17 "CFG23,Counter Control" bitfld.byte 0x17 6. " ALT_CNT ,Alternate operating mode of the counter" "DEFAULT_MODE,ALT_MODE" bitfld.byte 0x17 5. " ROUTE_EN ,Counter enable signal for routing input" "Disabled,Enabled" bitfld.byte 0x17 4. " ROUTE_LD ,Counter load signal for routing input" "Disabled,Enabled" bitfld.byte 0x17 2.--3. " CNT_EN_SEL ,Routing inputs for the counter enable signal" "SC_IN4,SC_IN5,SC_IN6,SC_IO" textline " " bitfld.byte 0x17 0.--1. " CNT_LD_SEL ,Routing inputs for the counter load signal" "SC_IN0,SC_IN1,SC_IN2,SC_IN3" if (((per.b(ad:0x400F3000+0x5F))&0x01)==0x01) group.byte 0x58++0x03 line.byte 0x00 "CFG24,PLD0 Clock And Reset Control" bitfld.byte 0x00 6.--7. " RC_RES_SEL ,Routed reset for the associated UDB component block" "0,1,2,3" bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x00 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x00 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x00 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x01 "CFG25,PLD1 Clock And Reset Control" bitfld.byte 0x00 6.--7. " RC_RES_SEL ,Routed reset for the associated UDB component block" "0,1,2,3" bitfld.byte 0x01 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x01 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x01 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x01 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x02 "CFG26,Datapath Clock And Reset Control" bitfld.byte 0x00 6.--7. " RC_RES_SEL ,Routed reset for the associated UDB component block" "0,1,2,3" bitfld.byte 0x02 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x02 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x02 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x02 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x03 "CFG27,Status/control Clock And Reset Control" bitfld.byte 0x00 6.--7. " RC_RES_SEL ,Routed reset for the associated UDB component block" "0,1,2,3" bitfld.byte 0x03 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x03 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x03 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x03 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" else group.byte 0x58++0x03 line.byte 0x00 "CFG24,PLD0 Clock And Reset Control" bitfld.byte 0x00 6. " FRES ,Firmware reset for the associated UDB component block" "No reset,Reset" bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x00 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x00 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x00 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x01 "CFG25,PLD1 Clock And Reset Control" bitfld.byte 0x00 6. " FRES ,Firmware reset for the associated UDB component block" "No reset,Reset" bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x00 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x00 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x00 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x02 "CFG26,Datapath Clock And Reset Control" bitfld.byte 0x00 6. " FRES ,Firmware reset for the associated UDB component block" "No reset,Reset" bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x00 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x00 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x00 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x03 "CFG27,Status/control Clock And Reset Control" rbitfld.byte 0x00 6. " FRES ,Firmware reset for the associated UDB component block" "No reset,Reset" bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x03 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x03 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x03 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" endif group.byte 0x5C++0x01 line.byte 0x00 "CFG28,Clock Selection For PLD1 And PLD0" bitfld.byte 0x00 4.--7. " PLD1_CK_SEL ,PLD1 clock selection registers" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,EXT_CLK,SYSCLK,?..." bitfld.byte 0x00 0.--3. " PLD0_CK_SEL ,PLD0 clock selection registers" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,EXT_CLK,SYSCLK,?..." line.byte 0x01 "CFG29,Clock Selection For Datapath, Status And Control" bitfld.byte 0x01 4.--7. " SC_CK_SEL ,SC clock selection registers" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,EXT_CLK,SYSCLK,?..." bitfld.byte 0x01 0.--3. " DP_CK_SEL ,DP clock selection registers" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,EXT_CLK,SYSCLK,?..." if (((per.b(ad:0x400F3000+0x5F))&0x01)==0x01) group.byte 0x5E++0x01 line.byte 0x00 "CFG30,Reset Control" bitfld.byte 0x00 7. " SC_RES_POL ,Polarity of the selected SC routed reset" "Not inverted,Inverted" bitfld.byte 0x00 6. " DP_RES_POL ,Polarity of the selected datapath routed reset" "Not inverted,Inverted" bitfld.byte 0x00 4. " GUDB_WR ,Global write operation for the configuration and working registers UDB" "Disabled,Enabled" bitfld.byte 0x00 3. " EN_RES_CNTCTL ,Routed reset to the counter/control register" "Disabled,Enabled" textline " " rbitfld.byte 0x00 2. " RES_POL ,Polarity of the routed reset" "NEGATED,ASSERTED" rbitfld.byte 0x00 0.--1. " RES_SEL ,RC routing input for the compatible reset scheme" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x01 "CFG31,Reset Control" bitfld.byte 0x01 7. " PLD1_RES_POL ,Polarity of the routed reset for both plds" "Not inverted,Inverted" bitfld.byte 0x01 6. " PLD0_RES_POL ,Polarity of the routed reset for both plds" "Not inverted,Inverted" bitfld.byte 0x01 4.--5. " EXT_CK_SEL ,External clock selection" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" bitfld.byte 0x01 3. " EN_RES_DP ,Routed reset to the datapath block" "Disabled,Enabled" textline " " bitfld.byte 0x01 2. " EN_RES_STAT ,Routed reset to the status register" "NEGATED,ASSERTED" bitfld.byte 0x01 1. " EXT_SYNC ,Synchronization of selected external clock" "Disabled,Enabled" bitfld.byte 0x01 0. " ALT_RES ,Toggles between two reset configurations" "COMPATIBLE,ALTERNATE" else group.byte 0x5E++0x01 line.byte 0x00 "CFG30,Reset Control" rbitfld.byte 0x00 7. " SC_RES_POL ,Polarity of the selected SC routed reset" "Not inverted,Inverted" rbitfld.byte 0x00 6. " DP_RES_POL ,Polarity of the selected datapath routed reset" "Not inverted,Inverted" bitfld.byte 0x00 4. " GUDB_WR ,Global write operation for the configuration and working registers UDB" "Disabled,Enabled" bitfld.byte 0x00 3. " EN_RES_CNTCTL ,Routed reset to the counter/control register" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " RES_POL ,Polarity of the routed reset" "NEGATED,ASSERTED" bitfld.byte 0x00 0.--1. " RES_SEL ,RC routing input for the compatible reset scheme" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x01 "CFG31,Reset Control" bitfld.byte 0x01 7. " PLD1_RES_POL ,Polarity of the routed reset for both plds" "Not inverted,Inverted" bitfld.byte 0x01 6. " PLD0_RES_POL ,Polarity of the routed reset for both plds" "Not inverted,Inverted" bitfld.byte 0x01 4.--5. " EXT_CK_SEL ,External clock selection" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" rbitfld.byte 0x01 3. " EN_RES_DP ,Routed reset to the datapath block" "Disabled,Enabled" textline " " rbitfld.byte 0x01 2. " EN_RES_STAT ,Routed reset to the status register" "NEGATED,ASSERTED" bitfld.byte 0x01 1. " EXT_SYNC ,Synchronization of selected external clock" "Disabled,Enabled" bitfld.byte 0x01 0. " ALT_RES ,Toggles between two reset configurations" "COMPATIBLE,ALTERNATE" endif group.word 0x60++0x01 line.word 0x00 "DCFG0,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x62++0x01 line.word 0x00 "DCFG1,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x64++0x01 line.word 0x00 "DCFG2,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x66++0x01 line.word 0x00 "DCFG3,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x68++0x01 line.word 0x00 "DCFG4,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x6A++0x01 line.word 0x00 "DCFG5,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x6C++0x01 line.word 0x00 "DCFG6,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x6E++0x01 line.word 0x00 "DCFG7,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" width 0x0B tree.end tree "UDB P0 U1" base ad:0x400F3080 width 22. group.long 0x0++0x03 line.long 0x00 "PLD_IT0,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT0T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT0T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT0T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT0T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT0T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT0T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT0T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT0T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT0T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT0T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT0T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT0T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT0T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT0T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT0T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT0T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT0C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT0C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT0C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT0C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT0C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT0C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT0C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT0C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT0C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT0C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT0C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT0C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT0C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT0C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT0C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT0C_0 ,PLD0 complement input term 0" "0,1" group.long 0x4++0x03 line.long 0x00 "PLD_IT1,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT1T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT1T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT1T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT1T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT1T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT1T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT1T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT1T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT1T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT1T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT1T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT1T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT1T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT1T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT1T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT1T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT1C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT1C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT1C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT1C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT1C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT1C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT1C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT1C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT1C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT1C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT1C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT1C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT1C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT1C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT1C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT1C_0 ,PLD0 complement input term 0" "0,1" group.long 0x8++0x03 line.long 0x00 "PLD_IT2,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT2T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT2T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT2T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT2T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT2T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT2T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT2T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT2T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT2T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT2T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT2T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT2T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT2T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT2T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT2T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT2T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT2C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT2C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT2C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT2C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT2C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT2C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT2C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT2C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT2C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT2C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT2C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT2C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT2C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT2C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT2C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT2C_0 ,PLD0 complement input term 0" "0,1" group.long 0xC++0x03 line.long 0x00 "PLD_IT3,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT3T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT3T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT3T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT3T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT3T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT3T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT3T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT3T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT3T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT3T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT3T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT3T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT3T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT3T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT3T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT3T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT3C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT3C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT3C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT3C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT3C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT3C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT3C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT3C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT3C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT3C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT3C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT3C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT3C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT3C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT3C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT3C_0 ,PLD0 complement input term 0" "0,1" group.long 0x10++0x03 line.long 0x00 "PLD_IT4,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT4T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT4T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT4T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT4T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT4T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT4T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT4T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT4T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT4T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT4T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT4T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT4T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT4T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT4T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT4T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT4T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT4C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT4C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT4C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT4C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT4C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT4C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT4C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT4C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT4C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT4C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT4C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT4C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT4C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT4C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT4C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT4C_0 ,PLD0 complement input term 0" "0,1" group.long 0x14++0x03 line.long 0x00 "PLD_IT5,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT5T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT5T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT5T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT5T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT5T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT5T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT5T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT5T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT5T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT5T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT5T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT5T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT5T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT5T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT5T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT5T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT5C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT5C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT5C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT5C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT5C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT5C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT5C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT5C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT5C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT5C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT5C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT5C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT5C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT5C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT5C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT5C_0 ,PLD0 complement input term 0" "0,1" group.long 0x18++0x03 line.long 0x00 "PLD_IT6,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT6T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT6T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT6T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT6T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT6T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT6T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT6T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT6T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT6T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT6T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT6T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT6T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT6T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT6T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT6T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT6T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT6C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT6C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT6C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT6C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT6C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT6C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT6C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT6C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT6C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT6C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT6C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT6C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT6C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT6C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT6C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT6C_0 ,PLD0 complement input term 0" "0,1" group.long 0x1C++0x03 line.long 0x00 "PLD_IT7,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT7T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT7T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT7T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT7T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT7T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT7T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT7T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT7T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT7T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT7T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT7T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT7T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT7T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT7T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT7T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT7T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT7C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT7C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT7C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT7C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT7C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT7C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT7C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT7C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT7C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT7C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT7C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT7C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT7C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT7C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT7C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT7C_0 ,PLD0 complement input term 0" "0,1" group.long 0x20++0x03 line.long 0x00 "PLD_IT8,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT8T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT8T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT8T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT8T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT8T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT8T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT8T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT8T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT8T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT8T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT8T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT8T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT8T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT8T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT8T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT8T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT8C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT8C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT8C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT8C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT8C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT8C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT8C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT8C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT8C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT8C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT8C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT8C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT8C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT8C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT8C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT8C_0 ,PLD0 complement input term 0" "0,1" group.long 0x24++0x03 line.long 0x00 "PLD_IT9,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT9T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT9T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT9T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT9T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT9T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT9T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT9T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT9T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT9T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT9T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT9T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT9T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT9T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT9T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT9T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT9T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT9C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT9C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT9C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT9C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT9C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT9C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT9C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT9C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT9C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT9C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT9C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT9C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT9C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT9C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT9C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT9C_0 ,PLD0 complement input term 0" "0,1" group.long 0x28++0x03 line.long 0x00 "PLD_IT10,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT10T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT10T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT10T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT10T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT10T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT10T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT10T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT10T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT10T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT10T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT10T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT10T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT10T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT10T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT10T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT10T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT10C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT10C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT10C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT10C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT10C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT10C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT10C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT10C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT10C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT10C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT10C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT10C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT10C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT10C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT10C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT10C_0 ,PLD0 complement input term 0" "0,1" group.long 0x2C++0x03 line.long 0x00 "PLD_IT11,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT11T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT11T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT11T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT11T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT11T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT11T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT11T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT11T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT11T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT11T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT11T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT11T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT11T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT11T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT11T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT11T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT11C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT11C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT11C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT11C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT11C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT11C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT11C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT11C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT11C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT11C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT11C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT11C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT11C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT11C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT11C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT11C_0 ,PLD0 complement input term 0" "0,1" group.word 0x30++0x01 line.word 0x00 "PLD_ORT0,PLD OR Terms" bitfld.word 0x00 15. " PLD1_ORT_PT0_7 ,PLD1 OR term 7" "0,1" bitfld.word 0x00 14. " PLD1_ORT_PT0_6 ,PLD1 OR term 6" "0,1" bitfld.word 0x00 13. " PLD1_ORT_PT0_5 ,PLD1 OR term 5" "0,1" bitfld.word 0x00 12. " PLD1_ORT_PT0_4 ,PLD1 OR term 4" "0,1" textline " " bitfld.word 0x00 11. " PLD1_ORT_PT0_3 ,PLD1 OR term 3" "0,1" bitfld.word 0x00 10. " PLD1_ORT_PT0_2 ,PLD1 OR term 2" "0,1" bitfld.word 0x00 9. " PLD1_ORT_PT0_1 ,PLD1 OR term 1" "0,1" bitfld.word 0x00 8. " PLD1_ORT_PT0_0 ,PLD1 OR term 0" "0,1" textline " " bitfld.word 0x00 7. " PLD0_ORT_PT0_7 ,PLD0 OR term 7" "0,1" bitfld.word 0x00 6. " PLD0_ORT_PT0_6 ,PLD0 OR term 6" "0,1" bitfld.word 0x00 5. " PLD0_ORT_PT0_5 ,PLD0 OR term 5" "0,1" bitfld.word 0x00 4. " PLD0_ORT_PT0_4 ,PLD0 OR term 4" "0,1" textline " " bitfld.word 0x00 3. " PLD0_ORT_PT0_3 ,PLD0 OR term 3" "0,1" bitfld.word 0x00 2. " PLD0_ORT_PT0_2 ,PLD0 OR term 2" "0,1" bitfld.word 0x00 1. " PLD0_ORT_PT0_1 ,PLD0 OR term 1" "0,1" bitfld.word 0x00 0. " PLD0_ORT_PT0_0 ,PLD0 OR term 0" "0,1" group.word 0x32++0x01 line.word 0x00 "PLD_ORT1,PLD OR Terms" bitfld.word 0x00 15. " PLD1_ORT_PT1_7 ,PLD1 OR term 7" "0,1" bitfld.word 0x00 14. " PLD1_ORT_PT1_6 ,PLD1 OR term 6" "0,1" bitfld.word 0x00 13. " PLD1_ORT_PT1_5 ,PLD1 OR term 5" "0,1" bitfld.word 0x00 12. " PLD1_ORT_PT1_4 ,PLD1 OR term 4" "0,1" textline " " bitfld.word 0x00 11. " PLD1_ORT_PT1_3 ,PLD1 OR term 3" "0,1" bitfld.word 0x00 10. " PLD1_ORT_PT1_2 ,PLD1 OR term 2" "0,1" bitfld.word 0x00 9. " PLD1_ORT_PT1_1 ,PLD1 OR term 1" "0,1" bitfld.word 0x00 8. " PLD1_ORT_PT1_0 ,PLD1 OR term 0" "0,1" textline " " bitfld.word 0x00 7. " PLD0_ORT_PT1_7 ,PLD0 OR term 7" "0,1" bitfld.word 0x00 6. " PLD0_ORT_PT1_6 ,PLD0 OR term 6" "0,1" bitfld.word 0x00 5. " PLD0_ORT_PT1_5 ,PLD0 OR term 5" "0,1" bitfld.word 0x00 4. " PLD0_ORT_PT1_4 ,PLD0 OR term 4" "0,1" textline " " bitfld.word 0x00 3. " PLD0_ORT_PT1_3 ,PLD0 OR term 3" "0,1" bitfld.word 0x00 2. " PLD0_ORT_PT1_2 ,PLD0 OR term 2" "0,1" bitfld.word 0x00 1. " PLD0_ORT_PT1_1 ,PLD0 OR term 1" "0,1" bitfld.word 0x00 0. " PLD0_ORT_PT1_0 ,PLD0 OR term 0" "0,1" group.word 0x34++0x01 line.word 0x00 "PLD_ORT2,PLD OR Terms" bitfld.word 0x00 15. " PLD1_ORT_PT2_7 ,PLD1 OR term 7" "0,1" bitfld.word 0x00 14. " PLD1_ORT_PT2_6 ,PLD1 OR term 6" "0,1" bitfld.word 0x00 13. " PLD1_ORT_PT2_5 ,PLD1 OR term 5" "0,1" bitfld.word 0x00 12. " PLD1_ORT_PT2_4 ,PLD1 OR term 4" "0,1" textline " " bitfld.word 0x00 11. " PLD1_ORT_PT2_3 ,PLD1 OR term 3" "0,1" bitfld.word 0x00 10. " PLD1_ORT_PT2_2 ,PLD1 OR term 2" "0,1" bitfld.word 0x00 9. " PLD1_ORT_PT2_1 ,PLD1 OR term 1" "0,1" bitfld.word 0x00 8. " PLD1_ORT_PT2_0 ,PLD1 OR term 0" "0,1" textline " " bitfld.word 0x00 7. " PLD0_ORT_PT2_7 ,PLD0 OR term 7" "0,1" bitfld.word 0x00 6. " PLD0_ORT_PT2_6 ,PLD0 OR term 6" "0,1" bitfld.word 0x00 5. " PLD0_ORT_PT2_5 ,PLD0 OR term 5" "0,1" bitfld.word 0x00 4. " PLD0_ORT_PT2_4 ,PLD0 OR term 4" "0,1" textline " " bitfld.word 0x00 3. " PLD0_ORT_PT2_3 ,PLD0 OR term 3" "0,1" bitfld.word 0x00 2. " PLD0_ORT_PT2_2 ,PLD0 OR term 2" "0,1" bitfld.word 0x00 1. " PLD0_ORT_PT2_1 ,PLD0 OR term 1" "0,1" bitfld.word 0x00 0. " PLD0_ORT_PT2_0 ,PLD0 OR term 0" "0,1" group.word 0x36++0x01 line.word 0x00 "PLD_ORT3,PLD OR Terms" bitfld.word 0x00 15. " PLD1_ORT_PT3_7 ,PLD1 OR term 7" "0,1" bitfld.word 0x00 14. " PLD1_ORT_PT3_6 ,PLD1 OR term 6" "0,1" bitfld.word 0x00 13. " PLD1_ORT_PT3_5 ,PLD1 OR term 5" "0,1" bitfld.word 0x00 12. " PLD1_ORT_PT3_4 ,PLD1 OR term 4" "0,1" textline " " bitfld.word 0x00 11. " PLD1_ORT_PT3_3 ,PLD1 OR term 3" "0,1" bitfld.word 0x00 10. " PLD1_ORT_PT3_2 ,PLD1 OR term 2" "0,1" bitfld.word 0x00 9. " PLD1_ORT_PT3_1 ,PLD1 OR term 1" "0,1" bitfld.word 0x00 8. " PLD1_ORT_PT3_0 ,PLD1 OR term 0" "0,1" textline " " bitfld.word 0x00 7. " PLD0_ORT_PT3_7 ,PLD0 OR term 7" "0,1" bitfld.word 0x00 6. " PLD0_ORT_PT3_6 ,PLD0 OR term 6" "0,1" bitfld.word 0x00 5. " PLD0_ORT_PT3_5 ,PLD0 OR term 5" "0,1" bitfld.word 0x00 4. " PLD0_ORT_PT3_4 ,PLD0 OR term 4" "0,1" textline " " bitfld.word 0x00 3. " PLD0_ORT_PT3_3 ,PLD0 OR term 3" "0,1" bitfld.word 0x00 2. " PLD0_ORT_PT3_2 ,PLD0 OR term 2" "0,1" bitfld.word 0x00 1. " PLD0_ORT_PT3_1 ,PLD0 OR term 1" "0,1" bitfld.word 0x00 0. " PLD0_ORT_PT3_0 ,PLD0 OR term 0" "0,1" group.word 0x38++0x07 line.word 0x00 "PLD_MC_CFG_CEN_CONST,Macrocell Configuration For Carry Enable And Constant" bitfld.word 0x00 15. " PLD1_MC3_DFF_C ,PLD1 MC3 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 14. " PLD1_MC3_CEN ,PLD1 MC3 carry enable" "Disabled,Enabled" bitfld.word 0x00 13. " PLD1_MC2_DFF_C ,PLD1 MC2 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 12. " PLD1_MC2_CEN ,PLD1 MC2 carry enable" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " PLD1_MC1_DFF_C ,PLD1 MC1 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 10. " PLD1_MC1_CEN ,PLD1 MC1 carry enable" "Disabled,Enabled" bitfld.word 0x00 9. " PLD1_MC0_DFF_C ,PLD1 MC0 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 8. " PLD1_MC0_CEN ,PLD1 MC0 carry enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " PLD0_MC3_DFF_C ,PLD0 MC3 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 6. " PLD0_MC3_CEN ,PLD0 MC3 carry enable" "Disabled,Enabled" bitfld.word 0x00 5. " PLD0_MC2_DFF_C ,PLD0 MC2 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 4. " PLD0_MC2_CEN ,PLD0 MC2 carry enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " PLD0_MC1_DFF_C ,PLD0 MC1 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 2. " PLD0_MC1_CEN ,PLD0 MC1 carry enable" "Disabled,Enabled" bitfld.word 0x00 1. " PLD0_MC0_DFF_C ,PLD0 MC0 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 0. " PLD0_MC0_CEN ,PLD0_MC0 carry enable" "Disabled,Enabled" line.word 0x02 "PLD_MC_CFG_XORFB,PLD Macro Cell XOR Feedback" bitfld.word 0x02 14.--15. " PLD1_MC3_XORFB ,PLD1 MC3 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" bitfld.word 0x02 12.--13. " PLD1_MC2_XORFB ,PLD1 MC2 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" bitfld.word 0x02 10.--11. " PLD1_MC1_XORFB ,PLD1 MC1 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" bitfld.word 0x02 8.--9. " PLD1_MC0_XORFB ,PLD1 MC0 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" textline " " bitfld.word 0x02 6.--7. " PLD0_MC3_XORFB ,PLD0 MC3 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" bitfld.word 0x02 4.--5. " PLD0_MC2_XORFB ,PLD0 MC2 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" bitfld.word 0x02 2.--3. " PLD0_MC1_XORFB ,PLD0 MC1 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" bitfld.word 0x02 0.--1. " PLD0_MC0_XORFB ,PLD0 MC0 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" line.word 0x04 "PLD_MC_SET_RESET,PLD Macro Cell Set Reset Selection" bitfld.word 0x04 15. " PLD1_MC3_RESET_SEL ,PLD1 MC3 reset select enable" "Disabled,Enabled" bitfld.word 0x04 14. " PLD1_MC3_SET_SEL ,PLD1 MC3 set select enable" "Disabled,Enabled" bitfld.word 0x04 13. " PLD1_MC2_RESET_SEL ,PLD1 MC2 reset select enable" "Disabled,Enabled" bitfld.word 0x04 12. " PLD1_MC2_SET_SEL ,PLD1 MC2 set select enable" "Disabled,Enabled" textline " " bitfld.word 0x04 11. " PLD1_MC1_RESET_SEL ,PLD1 MC1 reset select enable" "Disabled,Enabled" bitfld.word 0x04 10. " PLD1_MC1_SET_SEL ,PLD1 MC0 set select enable" "Disabled,Enabled" bitfld.word 0x04 9. " PLD1_MC0_RESET_SEL ,PLD1 MC0 reset select enable" "Disabled,Enabled" bitfld.word 0x04 8. " PLD1_MC0_SET_SEL ,PLD1 MC0 set select enable" "Disabled,Enabled" textline " " bitfld.word 0x04 7. " PLD0_MC3_RESET_SEL ,PLD0 MC3 reset select enable" "Disabled,Enabled" bitfld.word 0x04 6. " PLD0_MC3_SET_SEL ,PLD0 MC3 set select enable" "Disabled,Enabled" bitfld.word 0x04 5. " PLD0_MC2_RESET_SEL ,PLD0 MC2 reset select enable" "Disabled,Enabled" bitfld.word 0x04 4. " PLD0_MC2_SET_SEL ,PLD0 MC2 set select enable" "Disabled,Enabled" textline " " bitfld.word 0x04 3. " PLD0_MC1_RESET_SEL ,PLD0 MC1 reset select enable" "Disabled,Enabled" bitfld.word 0x04 2. " PLD0_MC1_SET_SEL ,PLD0 MC1 set select enable" "Disabled,Enabled" bitfld.word 0x04 1. " PLD0_MC0_RESET_SEL ,Reset select enable" "Disabled,Enabled" bitfld.word 0x04 0. " PLD0_MC0_SET_SEL ,PLD0 MC0 set select enable" "Disabled,Enabled" line.word 0x06 "PLD_MC_CFG_BYPASS,PLD Macro Cell Bypass Control" bitfld.word 0x06 15. " NC15 ,Spare register bit NC15" "0,1" bitfld.word 0x06 14. " PLD1_MC3_BYPASS ,PLD1 MC3 bypass selection" "REGISTER,COMBINATIONAL" bitfld.word 0x06 13. " NC13 ,Spare register bit NC13" "0,1" bitfld.word 0x06 12. " PLD1_MC2_BYPASS ,PLD1 MC2 bypass selection" "REGISTER,COMBINATIONAL" textline " " bitfld.word 0x06 11. " NC11 ,Spare register bit NC11" "0,1" bitfld.word 0x06 10. " PLD1_MC1_BYPASS ,PLD1 MC1 bypass selection" "REGISTER,COMBINATIONAL" bitfld.word 0x06 9. " NC9 ,Spare register bit NC9" "0,1" bitfld.word 0x06 8. " PLD1_MC0_BYPASS ,PLD1 MC0 bypass selection" "REGISTER,COMBINATIONAL" textline " " bitfld.word 0x06 7. " NC7 ,Spare register bit NC7" "0,1" bitfld.word 0x06 6. " PLD0_MC3_BYPASS ,PLD0 MC3 bypass selection" "REGISTER,COMBINATIONAL" bitfld.word 0x06 5. " NC5 ,Spare register bit NC5" "0,1" bitfld.word 0x06 4. " PLD0_MC2_BYPASS ,PLD0 MC2 bypass selection" "REGISTER,COMBINATIONAL" textline " " bitfld.word 0x06 3. " NC3 ,Spare register bit NC3" "0,1" bitfld.word 0x06 2. " PLD0_MC1_BYPASS ,PLD0 MC1 bypass selection" "REGISTER,COMBINATIONAL" bitfld.word 0x06 1. " NC1 ,Spare register bit NC1" "0,1" bitfld.word 0x06 0. " PLD0_MC0_BYPASS ,PLD0 MC0 bypass selection" "REGISTER,COMBINATIONAL" group.byte 0x40++0x17 line.byte 0x00 "CFG0,Datapath Input Selection - RAD1 RAD0. Address Bits 0 And 1 To The Dynamic Configuration RAM" bitfld.byte 0x00 4.--6. " RAD1 ,Datapath permutable input mux RAD1" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." bitfld.byte 0x00 0.--2. " RAD0 ,Datapath permutable input mux RAD0" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." line.byte 0x01 "CFG1,Datapath Input Selection - RAD2. Address Bit 2 To The Dynamic Configuration RAM" bitfld.byte 0x01 7. " DP_RTE_BYPASS4 ,Dp_in bypass control 4" "DP_IN4_ROUTE,DP_IN4_BYPASS" bitfld.byte 0x01 6. " DP_RTE_BYPASS3 ,Dp_in bypass control 3" "DP_IN3_ROUTE,DP_IN3_BYPASS" bitfld.byte 0x01 5. " DP_RTE_BYPASS2 ,Dp_in bypass control 2" "DP_IN2_ROUTE,DP_IN2_BYPASS" bitfld.byte 0x01 4. " DP_RTE_BYPASS1 ,Dp_in bypass control 1" "DP_IN1_ROUTE,DP_IN1_BYPASS" textline " " bitfld.byte 0x01 3. " DP_RTE_BYPASS0 ,Dp_in bypass control 0" "DP_IN0_ROUTE,DP_IN0_BYPASS" bitfld.byte 0x01 0.--2. " RAD2 ,Datapath permutable input mux 2" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." line.byte 0x02 "CFG2,Datapath Input Selection - F1_LD, F0_LD" bitfld.byte 0x02 7. " NC7 ,Spare register bit NC7" "0,1" bitfld.byte 0x02 4.--6. " F1_LD ,Datapath permutable input mux F1_LD" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." bitfld.byte 0x02 3. " DP_RTE_BYPASS5 ,Dp_in bypass control 5" "DP_IN5_ROUTE,DP_IN5_BYPASS" bitfld.byte 0x02 0.--2. " F0_LD ,Datapath permutable input mux F0_LD" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." line.byte 0x03 "CFG3,Datapath Input Selection - D1_LD, D0_LD" bitfld.byte 0x03 4.--6. " D1_LD ,Datapath permutable input mux D1_LD" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." bitfld.byte 0x03 0.--2. " D0_LD ,Datapath permutable input mux D0_LD" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." line.byte 0x04 "CFG4,Datapath Input Selection - CI_MUX SI_MUX" bitfld.byte 0x04 4.--6. " CI_MUX ,Datapath permutable input mux CI_MUX" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." bitfld.byte 0x04 0.--2. " SI_MUX ,Datapath permutable input mux SI_MUX" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." line.byte 0x05 "CFG5,Datapath Output Selection For OUT1 OUT0" bitfld.byte 0x05 4.--7. " OUT1 ,Datapath permutable output mux OUT1" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT" bitfld.byte 0x05 0.--3. " OUT0 ,Datapath permutable output mux OUT0" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT" line.byte 0x06 "CFG6,Datapath Output Selection For OUT3 OUT2" bitfld.byte 0x06 4.--7. " OUT3 ,Datapath permutable output mux OUT3" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT" bitfld.byte 0x06 0.--3. " OUT2 ,Datapath permutable output mux OUT2" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT" line.byte 0x07 "CFG7,Datapath Output Selection For OUT5 OUT4" bitfld.byte 0x07 4.--7. " OUT5 ,Datapath permutable output mux OUT5" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT" bitfld.byte 0x07 0.--3. " OUT4 ,Datapath permutable output mux OUT4" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT" line.byte 0x08 "CFG8,Datapath Output Synchronization Option" bitfld.byte 0x08 7. " NC7 ,Spare register bit NC7" "0,1" bitfld.byte 0x08 6. " NC6 ,Spare register bit NC6" "0,1" bitfld.byte 0x08 0.--5. " OUT_SYNC ,Datapath output synchronization" "REGISTERED,COMBINATIONAL,?..." line.byte 0x09 "CFG9,Datapath ALU Mask" line.byte 0x0A "CFG10,Datapath Compare 0 Mask" line.byte 0x0B "CFG11,Datapath Compare 1 Mask" line.byte 0x0C "CFG12,Datapath Mask Enables And Shift In Configuration" bitfld.byte 0x0C 7. " CMASK1_EN ,Datapath mask CMASK1 enable" "Disabled,Enabled" bitfld.byte 0x0C 6. " CMASK0_EN ,Datapath mask CMASK0 enable" "Disabled,Enabled" bitfld.byte 0x0C 5. " AMASK_EN ,Datapath mask AMASK enable" "Disabled,Enabled" bitfld.byte 0x0C 4. " DEF_SI ,Datapath default shift value" "DEFAULT_0,DEFAULT_1" textline " " bitfld.byte 0x0C 2.--3. " SI_SELB ,Datapath shift in source select" "DEFAULT,REGISTERED,ROUTE,CHAIN" bitfld.byte 0x0C 0.--1. " SI_SELA ,Datapath shift in source select" "DEFAULT,REGISTERED,ROUTE,CHAIN" line.byte 0x0D "CFG13,Datapath Carry In And Compare Configuration" bitfld.byte 0x0D 6.--7. " CMP_SELB ,Datapath compare select B" "A1_D1,A1_A0,A0_D1,A0_A0" bitfld.byte 0x0D 4.--5. " CMP_SELA ,Datapath compare select A" "A1_D1,A1_A0,A0_D1,A0_A0" bitfld.byte 0x0D 2.--3. " CI_SELB ,Datapath carry in source select B" "DEFAULT,REGISTERED,ROUTE,CHAIN" bitfld.byte 0x0D 0.--1. " CI_SELA ,Datapath carry in source select A" "DEFAULT,REGISTERED,ROUTE,CHAIN" line.byte 0x0E "CFG14,Datapath Chaining And MSB Configuration" bitfld.byte 0x0E 7. " MSB_EN ,Datapath MSB selection enable" "Disabled,Enabled" bitfld.byte 0x0E 4.--6. " MSB_SEL ,Datapath MSB selection" "BIT0,BIT1,BIT2,BIT3,BIT4,BIT5,BIT6,BIT7" bitfld.byte 0x0E 3. " CHAIN_CMSB ,Datapath CRC MSB chaining enable" "Disabled,Enabled" bitfld.byte 0x0E 2. " CHAIN_FB ,Datapath CRC feedback chaining enable" "Disabled,Enabled" textline " " bitfld.byte 0x0E 1. " CHAIN1 ,Datapath condition chaining enable 1" "Disabled,Enabled" bitfld.byte 0x0E 0. " CHAIN0 ,Datapath condition chaining enable 0" "Disabled,Enabled" line.byte 0x0F "CFG15,Datapath FIFO, Shift And Parallel Input Control" bitfld.byte 0x0F 7. " PI_SEL ,Datapath parallel input selection" "NORMAL,PARALLEL" bitfld.byte 0x0F 6. " SHIFT_SEL ,Datapath shift out selection" "SOL_MSB,SOR" bitfld.byte 0x0F 5. " PI_DYN ,Enable for dynamic control of parallel data input (Pi) mux" "Disabled,Enabled" bitfld.byte 0x0F 4. " MSB_SI ,Arithmetic shift right operation shift in selection" "DEFAULT,MSB" textline " " bitfld.byte 0x0F 2.--3. " F1_INSEL ,Datapath FIFO configuration 1" "INPUT,OUTPUT_A0,OUTPUT_A1,OUTPUT_ALU" bitfld.byte 0x0F 0.--1. " F0_INSEL ,Datapath FIFO configuration 0" "INPUT,OUTPUT_A0,OUTPUT_A1,OUTPUT_ALU" line.byte 0x10 "CFG16,Datapath FIFO And Register Access Configuration Control" bitfld.byte 0x10 7. " F1_CK_INV ,FIFO 1 clock Inverted" "NORMAL,Inverted" bitfld.byte 0x10 6. " F0_CK_INV ,FIFO 0 clock Inverted" "NORMAL,Inverted" bitfld.byte 0x10 5. " FIFO_FAST ,FIFO fast mode" "Disabled,Enabled" bitfld.byte 0x10 4. " FIFO_CAP ,FIFO software capture mode" "Disabled,Enabled" textline " " bitfld.byte 0x10 3. " FIFO_EDGE ,Edge/level sensitive FIFO write control (Fx_ld)" "LEVEL,EDGE" bitfld.byte 0x10 2. " FIFO_ASYNC ,Asynchronous FIFO clocking support" "Disabled,Enabled" bitfld.byte 0x10 1. " EXT_CRCPRS ,External CRC/PRS mode" "INTERNAL,EXTERNAL" bitfld.byte 0x10 0. " WRK16_CONCAT ,Datapath register access mode" "DEFAULT,CONCATENATE" line.byte 0x11 "CFG17,Datapath FIFO Control" bitfld.byte 0x11 4. " FIFO_ADD_SYNC ,Sync flip-flop to FIFO block status" "Disabled,Enabled" bitfld.byte 0x11 3. " NC3 ,Spare register bit NC3" "0,1" bitfld.byte 0x11 2. " NC2 ,Spare register bit NC2" "0,1" bitfld.byte 0x11 1. " F1_DYN ,FIFO 1 direction" "STATIC,DYNAMIC" textline " " bitfld.byte 0x11 0. " F0_DYN ,FIFO 0 direction" "STATIC,DYNAMIC" line.byte 0x12 "CFG18,Control Register Mode 0" line.byte 0x13 "CFG19,Control Register Mode 1" line.byte 0x14 "CFG20,Status Register Input Mode Selection" bitfld.byte 0x14 7. " STAT_MD[7] ,Bit 7 status input mode select" "Transparent,Sticky cleared" bitfld.byte 0x14 6. " [6] ,Bit 6 status input mode select" "Transparent,Sticky cleared" bitfld.byte 0x14 5. " [5] ,Bit 5 status input mode select" "Transparent,Sticky cleared" bitfld.byte 0x14 4. " [4] ,Bit 4 status input mode select" "Transparent,Sticky cleared" textline " " bitfld.byte 0x14 3. " [3] ,Bit 3 status input mode select" "Transparent,Sticky cleared" bitfld.byte 0x14 2. " [2] ,Bit 2 status input mode select" "Transparent,Sticky cleared" bitfld.byte 0x14 1. " [1] ,Bit 1 status input mode select" "Transparent,Sticky cleared" bitfld.byte 0x14 0. " [0] ,Bit 0 status input mode select" "Transparent,Sticky cleared" line.byte 0x15 "CFG21,Spare Register Bits" bitfld.byte 0x15 1. " NC1 ,Spare register bit NC1" "0,1" bitfld.byte 0x15 0. " NC0 ,Spare register bit NC0" "0,1" line.byte 0x16 "CFG22,SC Block Configuration Control" bitfld.byte 0x16 4. " SC_EXT_RES ,Control register external reset operation" "Disabled,Enabled" bitfld.byte 0x16 3. " SC_SYNC_MD ,SC sync mode" "NORMAL,SYNC_MODE" bitfld.byte 0x16 2. " SC_INT_MD ,SC interrupt mode" "NORMAL,INT_MODE" bitfld.byte 0x16 0.--1. " SC_OUT_CTL ,Output source for the status and control routing connections" "CONTROL,PARALLEL,COUNTER,?..." line.byte 0x17 "CFG23,Counter Control" bitfld.byte 0x17 6. " ALT_CNT ,Alternate operating mode of the counter" "DEFAULT_MODE,ALT_MODE" bitfld.byte 0x17 5. " ROUTE_EN ,Counter enable signal for routing input" "Disabled,Enabled" bitfld.byte 0x17 4. " ROUTE_LD ,Counter load signal for routing input" "Disabled,Enabled" bitfld.byte 0x17 2.--3. " CNT_EN_SEL ,Routing inputs for the counter enable signal" "SC_IN4,SC_IN5,SC_IN6,SC_IO" textline " " bitfld.byte 0x17 0.--1. " CNT_LD_SEL ,Routing inputs for the counter load signal" "SC_IN0,SC_IN1,SC_IN2,SC_IN3" if (((per.b(ad:0x400F3080+0x5F))&0x01)==0x01) group.byte 0x58++0x03 line.byte 0x00 "CFG24,PLD0 Clock And Reset Control" bitfld.byte 0x00 6.--7. " RC_RES_SEL ,Routed reset for the associated UDB component block" "0,1,2,3" bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x00 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x00 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x00 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x01 "CFG25,PLD1 Clock And Reset Control" bitfld.byte 0x00 6.--7. " RC_RES_SEL ,Routed reset for the associated UDB component block" "0,1,2,3" bitfld.byte 0x01 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x01 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x01 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x01 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x02 "CFG26,Datapath Clock And Reset Control" bitfld.byte 0x00 6.--7. " RC_RES_SEL ,Routed reset for the associated UDB component block" "0,1,2,3" bitfld.byte 0x02 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x02 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x02 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x02 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x03 "CFG27,Status/control Clock And Reset Control" bitfld.byte 0x00 6.--7. " RC_RES_SEL ,Routed reset for the associated UDB component block" "0,1,2,3" bitfld.byte 0x03 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x03 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x03 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x03 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" else group.byte 0x58++0x03 line.byte 0x00 "CFG24,PLD0 Clock And Reset Control" bitfld.byte 0x00 6. " FRES ,Firmware reset for the associated UDB component block" "No reset,Reset" bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x00 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x00 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x00 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x01 "CFG25,PLD1 Clock And Reset Control" bitfld.byte 0x00 6. " FRES ,Firmware reset for the associated UDB component block" "No reset,Reset" bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x00 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x00 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x00 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x02 "CFG26,Datapath Clock And Reset Control" bitfld.byte 0x00 6. " FRES ,Firmware reset for the associated UDB component block" "No reset,Reset" bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x00 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x00 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x00 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x03 "CFG27,Status/control Clock And Reset Control" rbitfld.byte 0x00 6. " FRES ,Firmware reset for the associated UDB component block" "No reset,Reset" bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x03 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x03 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x03 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" endif group.byte 0x5C++0x01 line.byte 0x00 "CFG28,Clock Selection For PLD1 And PLD0" bitfld.byte 0x00 4.--7. " PLD1_CK_SEL ,PLD1 clock selection registers" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,EXT_CLK,SYSCLK,?..." bitfld.byte 0x00 0.--3. " PLD0_CK_SEL ,PLD0 clock selection registers" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,EXT_CLK,SYSCLK,?..." line.byte 0x01 "CFG29,Clock Selection For Datapath, Status And Control" bitfld.byte 0x01 4.--7. " SC_CK_SEL ,SC clock selection registers" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,EXT_CLK,SYSCLK,?..." bitfld.byte 0x01 0.--3. " DP_CK_SEL ,DP clock selection registers" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,EXT_CLK,SYSCLK,?..." if (((per.b(ad:0x400F3080+0x5F))&0x01)==0x01) group.byte 0x5E++0x01 line.byte 0x00 "CFG30,Reset Control" bitfld.byte 0x00 7. " SC_RES_POL ,Polarity of the selected SC routed reset" "Not inverted,Inverted" bitfld.byte 0x00 6. " DP_RES_POL ,Polarity of the selected datapath routed reset" "Not inverted,Inverted" bitfld.byte 0x00 4. " GUDB_WR ,Global write operation for the configuration and working registers UDB" "Disabled,Enabled" bitfld.byte 0x00 3. " EN_RES_CNTCTL ,Routed reset to the counter/control register" "Disabled,Enabled" textline " " rbitfld.byte 0x00 2. " RES_POL ,Polarity of the routed reset" "NEGATED,ASSERTED" rbitfld.byte 0x00 0.--1. " RES_SEL ,RC routing input for the compatible reset scheme" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x01 "CFG31,Reset Control" bitfld.byte 0x01 7. " PLD1_RES_POL ,Polarity of the routed reset for both plds" "Not inverted,Inverted" bitfld.byte 0x01 6. " PLD0_RES_POL ,Polarity of the routed reset for both plds" "Not inverted,Inverted" bitfld.byte 0x01 4.--5. " EXT_CK_SEL ,External clock selection" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" bitfld.byte 0x01 3. " EN_RES_DP ,Routed reset to the datapath block" "Disabled,Enabled" textline " " bitfld.byte 0x01 2. " EN_RES_STAT ,Routed reset to the status register" "NEGATED,ASSERTED" bitfld.byte 0x01 1. " EXT_SYNC ,Synchronization of selected external clock" "Disabled,Enabled" bitfld.byte 0x01 0. " ALT_RES ,Toggles between two reset configurations" "COMPATIBLE,ALTERNATE" else group.byte 0x5E++0x01 line.byte 0x00 "CFG30,Reset Control" rbitfld.byte 0x00 7. " SC_RES_POL ,Polarity of the selected SC routed reset" "Not inverted,Inverted" rbitfld.byte 0x00 6. " DP_RES_POL ,Polarity of the selected datapath routed reset" "Not inverted,Inverted" bitfld.byte 0x00 4. " GUDB_WR ,Global write operation for the configuration and working registers UDB" "Disabled,Enabled" bitfld.byte 0x00 3. " EN_RES_CNTCTL ,Routed reset to the counter/control register" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " RES_POL ,Polarity of the routed reset" "NEGATED,ASSERTED" bitfld.byte 0x00 0.--1. " RES_SEL ,RC routing input for the compatible reset scheme" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x01 "CFG31,Reset Control" bitfld.byte 0x01 7. " PLD1_RES_POL ,Polarity of the routed reset for both plds" "Not inverted,Inverted" bitfld.byte 0x01 6. " PLD0_RES_POL ,Polarity of the routed reset for both plds" "Not inverted,Inverted" bitfld.byte 0x01 4.--5. " EXT_CK_SEL ,External clock selection" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" rbitfld.byte 0x01 3. " EN_RES_DP ,Routed reset to the datapath block" "Disabled,Enabled" textline " " rbitfld.byte 0x01 2. " EN_RES_STAT ,Routed reset to the status register" "NEGATED,ASSERTED" bitfld.byte 0x01 1. " EXT_SYNC ,Synchronization of selected external clock" "Disabled,Enabled" bitfld.byte 0x01 0. " ALT_RES ,Toggles between two reset configurations" "COMPATIBLE,ALTERNATE" endif group.word 0x60++0x01 line.word 0x00 "DCFG0,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x62++0x01 line.word 0x00 "DCFG1,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x64++0x01 line.word 0x00 "DCFG2,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x66++0x01 line.word 0x00 "DCFG3,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x68++0x01 line.word 0x00 "DCFG4,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x6A++0x01 line.word 0x00 "DCFG5,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x6C++0x01 line.word 0x00 "DCFG6,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x6E++0x01 line.word 0x00 "DCFG7,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" width 0x0B tree.end tree "UDB P1 U0" base ad:0x400F3200 width 22. group.long 0x0++0x03 line.long 0x00 "PLD_IT0,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT0T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT0T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT0T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT0T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT0T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT0T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT0T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT0T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT0T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT0T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT0T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT0T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT0T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT0T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT0T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT0T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT0C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT0C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT0C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT0C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT0C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT0C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT0C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT0C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT0C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT0C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT0C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT0C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT0C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT0C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT0C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT0C_0 ,PLD0 complement input term 0" "0,1" group.long 0x4++0x03 line.long 0x00 "PLD_IT1,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT1T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT1T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT1T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT1T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT1T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT1T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT1T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT1T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT1T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT1T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT1T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT1T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT1T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT1T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT1T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT1T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT1C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT1C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT1C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT1C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT1C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT1C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT1C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT1C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT1C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT1C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT1C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT1C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT1C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT1C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT1C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT1C_0 ,PLD0 complement input term 0" "0,1" group.long 0x8++0x03 line.long 0x00 "PLD_IT2,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT2T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT2T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT2T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT2T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT2T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT2T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT2T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT2T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT2T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT2T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT2T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT2T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT2T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT2T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT2T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT2T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT2C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT2C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT2C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT2C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT2C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT2C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT2C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT2C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT2C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT2C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT2C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT2C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT2C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT2C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT2C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT2C_0 ,PLD0 complement input term 0" "0,1" group.long 0xC++0x03 line.long 0x00 "PLD_IT3,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT3T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT3T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT3T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT3T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT3T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT3T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT3T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT3T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT3T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT3T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT3T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT3T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT3T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT3T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT3T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT3T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT3C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT3C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT3C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT3C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT3C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT3C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT3C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT3C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT3C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT3C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT3C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT3C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT3C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT3C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT3C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT3C_0 ,PLD0 complement input term 0" "0,1" group.long 0x10++0x03 line.long 0x00 "PLD_IT4,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT4T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT4T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT4T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT4T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT4T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT4T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT4T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT4T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT4T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT4T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT4T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT4T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT4T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT4T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT4T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT4T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT4C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT4C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT4C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT4C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT4C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT4C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT4C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT4C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT4C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT4C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT4C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT4C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT4C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT4C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT4C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT4C_0 ,PLD0 complement input term 0" "0,1" group.long 0x14++0x03 line.long 0x00 "PLD_IT5,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT5T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT5T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT5T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT5T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT5T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT5T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT5T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT5T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT5T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT5T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT5T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT5T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT5T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT5T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT5T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT5T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT5C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT5C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT5C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT5C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT5C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT5C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT5C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT5C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT5C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT5C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT5C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT5C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT5C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT5C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT5C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT5C_0 ,PLD0 complement input term 0" "0,1" group.long 0x18++0x03 line.long 0x00 "PLD_IT6,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT6T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT6T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT6T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT6T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT6T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT6T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT6T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT6T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT6T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT6T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT6T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT6T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT6T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT6T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT6T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT6T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT6C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT6C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT6C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT6C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT6C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT6C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT6C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT6C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT6C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT6C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT6C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT6C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT6C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT6C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT6C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT6C_0 ,PLD0 complement input term 0" "0,1" group.long 0x1C++0x03 line.long 0x00 "PLD_IT7,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT7T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT7T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT7T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT7T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT7T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT7T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT7T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT7T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT7T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT7T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT7T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT7T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT7T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT7T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT7T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT7T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT7C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT7C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT7C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT7C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT7C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT7C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT7C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT7C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT7C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT7C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT7C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT7C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT7C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT7C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT7C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT7C_0 ,PLD0 complement input term 0" "0,1" group.long 0x20++0x03 line.long 0x00 "PLD_IT8,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT8T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT8T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT8T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT8T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT8T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT8T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT8T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT8T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT8T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT8T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT8T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT8T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT8T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT8T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT8T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT8T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT8C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT8C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT8C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT8C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT8C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT8C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT8C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT8C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT8C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT8C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT8C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT8C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT8C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT8C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT8C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT8C_0 ,PLD0 complement input term 0" "0,1" group.long 0x24++0x03 line.long 0x00 "PLD_IT9,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT9T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT9T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT9T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT9T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT9T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT9T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT9T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT9T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT9T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT9T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT9T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT9T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT9T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT9T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT9T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT9T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT9C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT9C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT9C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT9C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT9C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT9C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT9C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT9C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT9C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT9C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT9C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT9C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT9C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT9C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT9C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT9C_0 ,PLD0 complement input term 0" "0,1" group.long 0x28++0x03 line.long 0x00 "PLD_IT10,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT10T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT10T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT10T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT10T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT10T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT10T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT10T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT10T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT10T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT10T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT10T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT10T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT10T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT10T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT10T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT10T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT10C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT10C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT10C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT10C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT10C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT10C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT10C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT10C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT10C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT10C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT10C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT10C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT10C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT10C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT10C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT10C_0 ,PLD0 complement input term 0" "0,1" group.long 0x2C++0x03 line.long 0x00 "PLD_IT11,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT11T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT11T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT11T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT11T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT11T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT11T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT11T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT11T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT11T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT11T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT11T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT11T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT11T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT11T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT11T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT11T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT11C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT11C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT11C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT11C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT11C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT11C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT11C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT11C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT11C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT11C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT11C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT11C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT11C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT11C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT11C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT11C_0 ,PLD0 complement input term 0" "0,1" group.word 0x30++0x01 line.word 0x00 "PLD_ORT0,PLD OR Terms" bitfld.word 0x00 15. " PLD1_ORT_PT0_7 ,PLD1 OR term 7" "0,1" bitfld.word 0x00 14. " PLD1_ORT_PT0_6 ,PLD1 OR term 6" "0,1" bitfld.word 0x00 13. " PLD1_ORT_PT0_5 ,PLD1 OR term 5" "0,1" bitfld.word 0x00 12. " PLD1_ORT_PT0_4 ,PLD1 OR term 4" "0,1" textline " " bitfld.word 0x00 11. " PLD1_ORT_PT0_3 ,PLD1 OR term 3" "0,1" bitfld.word 0x00 10. " PLD1_ORT_PT0_2 ,PLD1 OR term 2" "0,1" bitfld.word 0x00 9. " PLD1_ORT_PT0_1 ,PLD1 OR term 1" "0,1" bitfld.word 0x00 8. " PLD1_ORT_PT0_0 ,PLD1 OR term 0" "0,1" textline " " bitfld.word 0x00 7. " PLD0_ORT_PT0_7 ,PLD0 OR term 7" "0,1" bitfld.word 0x00 6. " PLD0_ORT_PT0_6 ,PLD0 OR term 6" "0,1" bitfld.word 0x00 5. " PLD0_ORT_PT0_5 ,PLD0 OR term 5" "0,1" bitfld.word 0x00 4. " PLD0_ORT_PT0_4 ,PLD0 OR term 4" "0,1" textline " " bitfld.word 0x00 3. " PLD0_ORT_PT0_3 ,PLD0 OR term 3" "0,1" bitfld.word 0x00 2. " PLD0_ORT_PT0_2 ,PLD0 OR term 2" "0,1" bitfld.word 0x00 1. " PLD0_ORT_PT0_1 ,PLD0 OR term 1" "0,1" bitfld.word 0x00 0. " PLD0_ORT_PT0_0 ,PLD0 OR term 0" "0,1" group.word 0x32++0x01 line.word 0x00 "PLD_ORT1,PLD OR Terms" bitfld.word 0x00 15. " PLD1_ORT_PT1_7 ,PLD1 OR term 7" "0,1" bitfld.word 0x00 14. " PLD1_ORT_PT1_6 ,PLD1 OR term 6" "0,1" bitfld.word 0x00 13. " PLD1_ORT_PT1_5 ,PLD1 OR term 5" "0,1" bitfld.word 0x00 12. " PLD1_ORT_PT1_4 ,PLD1 OR term 4" "0,1" textline " " bitfld.word 0x00 11. " PLD1_ORT_PT1_3 ,PLD1 OR term 3" "0,1" bitfld.word 0x00 10. " PLD1_ORT_PT1_2 ,PLD1 OR term 2" "0,1" bitfld.word 0x00 9. " PLD1_ORT_PT1_1 ,PLD1 OR term 1" "0,1" bitfld.word 0x00 8. " PLD1_ORT_PT1_0 ,PLD1 OR term 0" "0,1" textline " " bitfld.word 0x00 7. " PLD0_ORT_PT1_7 ,PLD0 OR term 7" "0,1" bitfld.word 0x00 6. " PLD0_ORT_PT1_6 ,PLD0 OR term 6" "0,1" bitfld.word 0x00 5. " PLD0_ORT_PT1_5 ,PLD0 OR term 5" "0,1" bitfld.word 0x00 4. " PLD0_ORT_PT1_4 ,PLD0 OR term 4" "0,1" textline " " bitfld.word 0x00 3. " PLD0_ORT_PT1_3 ,PLD0 OR term 3" "0,1" bitfld.word 0x00 2. " PLD0_ORT_PT1_2 ,PLD0 OR term 2" "0,1" bitfld.word 0x00 1. " PLD0_ORT_PT1_1 ,PLD0 OR term 1" "0,1" bitfld.word 0x00 0. " PLD0_ORT_PT1_0 ,PLD0 OR term 0" "0,1" group.word 0x34++0x01 line.word 0x00 "PLD_ORT2,PLD OR Terms" bitfld.word 0x00 15. " PLD1_ORT_PT2_7 ,PLD1 OR term 7" "0,1" bitfld.word 0x00 14. " PLD1_ORT_PT2_6 ,PLD1 OR term 6" "0,1" bitfld.word 0x00 13. " PLD1_ORT_PT2_5 ,PLD1 OR term 5" "0,1" bitfld.word 0x00 12. " PLD1_ORT_PT2_4 ,PLD1 OR term 4" "0,1" textline " " bitfld.word 0x00 11. " PLD1_ORT_PT2_3 ,PLD1 OR term 3" "0,1" bitfld.word 0x00 10. " PLD1_ORT_PT2_2 ,PLD1 OR term 2" "0,1" bitfld.word 0x00 9. " PLD1_ORT_PT2_1 ,PLD1 OR term 1" "0,1" bitfld.word 0x00 8. " PLD1_ORT_PT2_0 ,PLD1 OR term 0" "0,1" textline " " bitfld.word 0x00 7. " PLD0_ORT_PT2_7 ,PLD0 OR term 7" "0,1" bitfld.word 0x00 6. " PLD0_ORT_PT2_6 ,PLD0 OR term 6" "0,1" bitfld.word 0x00 5. " PLD0_ORT_PT2_5 ,PLD0 OR term 5" "0,1" bitfld.word 0x00 4. " PLD0_ORT_PT2_4 ,PLD0 OR term 4" "0,1" textline " " bitfld.word 0x00 3. " PLD0_ORT_PT2_3 ,PLD0 OR term 3" "0,1" bitfld.word 0x00 2. " PLD0_ORT_PT2_2 ,PLD0 OR term 2" "0,1" bitfld.word 0x00 1. " PLD0_ORT_PT2_1 ,PLD0 OR term 1" "0,1" bitfld.word 0x00 0. " PLD0_ORT_PT2_0 ,PLD0 OR term 0" "0,1" group.word 0x36++0x01 line.word 0x00 "PLD_ORT3,PLD OR Terms" bitfld.word 0x00 15. " PLD1_ORT_PT3_7 ,PLD1 OR term 7" "0,1" bitfld.word 0x00 14. " PLD1_ORT_PT3_6 ,PLD1 OR term 6" "0,1" bitfld.word 0x00 13. " PLD1_ORT_PT3_5 ,PLD1 OR term 5" "0,1" bitfld.word 0x00 12. " PLD1_ORT_PT3_4 ,PLD1 OR term 4" "0,1" textline " " bitfld.word 0x00 11. " PLD1_ORT_PT3_3 ,PLD1 OR term 3" "0,1" bitfld.word 0x00 10. " PLD1_ORT_PT3_2 ,PLD1 OR term 2" "0,1" bitfld.word 0x00 9. " PLD1_ORT_PT3_1 ,PLD1 OR term 1" "0,1" bitfld.word 0x00 8. " PLD1_ORT_PT3_0 ,PLD1 OR term 0" "0,1" textline " " bitfld.word 0x00 7. " PLD0_ORT_PT3_7 ,PLD0 OR term 7" "0,1" bitfld.word 0x00 6. " PLD0_ORT_PT3_6 ,PLD0 OR term 6" "0,1" bitfld.word 0x00 5. " PLD0_ORT_PT3_5 ,PLD0 OR term 5" "0,1" bitfld.word 0x00 4. " PLD0_ORT_PT3_4 ,PLD0 OR term 4" "0,1" textline " " bitfld.word 0x00 3. " PLD0_ORT_PT3_3 ,PLD0 OR term 3" "0,1" bitfld.word 0x00 2. " PLD0_ORT_PT3_2 ,PLD0 OR term 2" "0,1" bitfld.word 0x00 1. " PLD0_ORT_PT3_1 ,PLD0 OR term 1" "0,1" bitfld.word 0x00 0. " PLD0_ORT_PT3_0 ,PLD0 OR term 0" "0,1" group.word 0x38++0x07 line.word 0x00 "PLD_MC_CFG_CEN_CONST,Macrocell Configuration For Carry Enable And Constant" bitfld.word 0x00 15. " PLD1_MC3_DFF_C ,PLD1 MC3 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 14. " PLD1_MC3_CEN ,PLD1 MC3 carry enable" "Disabled,Enabled" bitfld.word 0x00 13. " PLD1_MC2_DFF_C ,PLD1 MC2 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 12. " PLD1_MC2_CEN ,PLD1 MC2 carry enable" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " PLD1_MC1_DFF_C ,PLD1 MC1 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 10. " PLD1_MC1_CEN ,PLD1 MC1 carry enable" "Disabled,Enabled" bitfld.word 0x00 9. " PLD1_MC0_DFF_C ,PLD1 MC0 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 8. " PLD1_MC0_CEN ,PLD1 MC0 carry enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " PLD0_MC3_DFF_C ,PLD0 MC3 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 6. " PLD0_MC3_CEN ,PLD0 MC3 carry enable" "Disabled,Enabled" bitfld.word 0x00 5. " PLD0_MC2_DFF_C ,PLD0 MC2 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 4. " PLD0_MC2_CEN ,PLD0 MC2 carry enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " PLD0_MC1_DFF_C ,PLD0 MC1 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 2. " PLD0_MC1_CEN ,PLD0 MC1 carry enable" "Disabled,Enabled" bitfld.word 0x00 1. " PLD0_MC0_DFF_C ,PLD0 MC0 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 0. " PLD0_MC0_CEN ,PLD0_MC0 carry enable" "Disabled,Enabled" line.word 0x02 "PLD_MC_CFG_XORFB,PLD Macro Cell XOR Feedback" bitfld.word 0x02 14.--15. " PLD1_MC3_XORFB ,PLD1 MC3 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" bitfld.word 0x02 12.--13. " PLD1_MC2_XORFB ,PLD1 MC2 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" bitfld.word 0x02 10.--11. " PLD1_MC1_XORFB ,PLD1 MC1 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" bitfld.word 0x02 8.--9. " PLD1_MC0_XORFB ,PLD1 MC0 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" textline " " bitfld.word 0x02 6.--7. " PLD0_MC3_XORFB ,PLD0 MC3 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" bitfld.word 0x02 4.--5. " PLD0_MC2_XORFB ,PLD0 MC2 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" bitfld.word 0x02 2.--3. " PLD0_MC1_XORFB ,PLD0 MC1 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" bitfld.word 0x02 0.--1. " PLD0_MC0_XORFB ,PLD0 MC0 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" line.word 0x04 "PLD_MC_SET_RESET,PLD Macro Cell Set Reset Selection" bitfld.word 0x04 15. " PLD1_MC3_RESET_SEL ,PLD1 MC3 reset select enable" "Disabled,Enabled" bitfld.word 0x04 14. " PLD1_MC3_SET_SEL ,PLD1 MC3 set select enable" "Disabled,Enabled" bitfld.word 0x04 13. " PLD1_MC2_RESET_SEL ,PLD1 MC2 reset select enable" "Disabled,Enabled" bitfld.word 0x04 12. " PLD1_MC2_SET_SEL ,PLD1 MC2 set select enable" "Disabled,Enabled" textline " " bitfld.word 0x04 11. " PLD1_MC1_RESET_SEL ,PLD1 MC1 reset select enable" "Disabled,Enabled" bitfld.word 0x04 10. " PLD1_MC1_SET_SEL ,PLD1 MC0 set select enable" "Disabled,Enabled" bitfld.word 0x04 9. " PLD1_MC0_RESET_SEL ,PLD1 MC0 reset select enable" "Disabled,Enabled" bitfld.word 0x04 8. " PLD1_MC0_SET_SEL ,PLD1 MC0 set select enable" "Disabled,Enabled" textline " " bitfld.word 0x04 7. " PLD0_MC3_RESET_SEL ,PLD0 MC3 reset select enable" "Disabled,Enabled" bitfld.word 0x04 6. " PLD0_MC3_SET_SEL ,PLD0 MC3 set select enable" "Disabled,Enabled" bitfld.word 0x04 5. " PLD0_MC2_RESET_SEL ,PLD0 MC2 reset select enable" "Disabled,Enabled" bitfld.word 0x04 4. " PLD0_MC2_SET_SEL ,PLD0 MC2 set select enable" "Disabled,Enabled" textline " " bitfld.word 0x04 3. " PLD0_MC1_RESET_SEL ,PLD0 MC1 reset select enable" "Disabled,Enabled" bitfld.word 0x04 2. " PLD0_MC1_SET_SEL ,PLD0 MC1 set select enable" "Disabled,Enabled" bitfld.word 0x04 1. " PLD0_MC0_RESET_SEL ,Reset select enable" "Disabled,Enabled" bitfld.word 0x04 0. " PLD0_MC0_SET_SEL ,PLD0 MC0 set select enable" "Disabled,Enabled" line.word 0x06 "PLD_MC_CFG_BYPASS,PLD Macro Cell Bypass Control" bitfld.word 0x06 15. " NC15 ,Spare register bit NC15" "0,1" bitfld.word 0x06 14. " PLD1_MC3_BYPASS ,PLD1 MC3 bypass selection" "REGISTER,COMBINATIONAL" bitfld.word 0x06 13. " NC13 ,Spare register bit NC13" "0,1" bitfld.word 0x06 12. " PLD1_MC2_BYPASS ,PLD1 MC2 bypass selection" "REGISTER,COMBINATIONAL" textline " " bitfld.word 0x06 11. " NC11 ,Spare register bit NC11" "0,1" bitfld.word 0x06 10. " PLD1_MC1_BYPASS ,PLD1 MC1 bypass selection" "REGISTER,COMBINATIONAL" bitfld.word 0x06 9. " NC9 ,Spare register bit NC9" "0,1" bitfld.word 0x06 8. " PLD1_MC0_BYPASS ,PLD1 MC0 bypass selection" "REGISTER,COMBINATIONAL" textline " " bitfld.word 0x06 7. " NC7 ,Spare register bit NC7" "0,1" bitfld.word 0x06 6. " PLD0_MC3_BYPASS ,PLD0 MC3 bypass selection" "REGISTER,COMBINATIONAL" bitfld.word 0x06 5. " NC5 ,Spare register bit NC5" "0,1" bitfld.word 0x06 4. " PLD0_MC2_BYPASS ,PLD0 MC2 bypass selection" "REGISTER,COMBINATIONAL" textline " " bitfld.word 0x06 3. " NC3 ,Spare register bit NC3" "0,1" bitfld.word 0x06 2. " PLD0_MC1_BYPASS ,PLD0 MC1 bypass selection" "REGISTER,COMBINATIONAL" bitfld.word 0x06 1. " NC1 ,Spare register bit NC1" "0,1" bitfld.word 0x06 0. " PLD0_MC0_BYPASS ,PLD0 MC0 bypass selection" "REGISTER,COMBINATIONAL" group.byte 0x40++0x17 line.byte 0x00 "CFG0,Datapath Input Selection - RAD1 RAD0. Address Bits 0 And 1 To The Dynamic Configuration RAM" bitfld.byte 0x00 4.--6. " RAD1 ,Datapath permutable input mux RAD1" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." bitfld.byte 0x00 0.--2. " RAD0 ,Datapath permutable input mux RAD0" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." line.byte 0x01 "CFG1,Datapath Input Selection - RAD2. Address Bit 2 To The Dynamic Configuration RAM" bitfld.byte 0x01 7. " DP_RTE_BYPASS4 ,Dp_in bypass control 4" "DP_IN4_ROUTE,DP_IN4_BYPASS" bitfld.byte 0x01 6. " DP_RTE_BYPASS3 ,Dp_in bypass control 3" "DP_IN3_ROUTE,DP_IN3_BYPASS" bitfld.byte 0x01 5. " DP_RTE_BYPASS2 ,Dp_in bypass control 2" "DP_IN2_ROUTE,DP_IN2_BYPASS" bitfld.byte 0x01 4. " DP_RTE_BYPASS1 ,Dp_in bypass control 1" "DP_IN1_ROUTE,DP_IN1_BYPASS" textline " " bitfld.byte 0x01 3. " DP_RTE_BYPASS0 ,Dp_in bypass control 0" "DP_IN0_ROUTE,DP_IN0_BYPASS" bitfld.byte 0x01 0.--2. " RAD2 ,Datapath permutable input mux 2" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." line.byte 0x02 "CFG2,Datapath Input Selection - F1_LD, F0_LD" bitfld.byte 0x02 7. " NC7 ,Spare register bit NC7" "0,1" bitfld.byte 0x02 4.--6. " F1_LD ,Datapath permutable input mux F1_LD" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." bitfld.byte 0x02 3. " DP_RTE_BYPASS5 ,Dp_in bypass control 5" "DP_IN5_ROUTE,DP_IN5_BYPASS" bitfld.byte 0x02 0.--2. " F0_LD ,Datapath permutable input mux F0_LD" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." line.byte 0x03 "CFG3,Datapath Input Selection - D1_LD, D0_LD" bitfld.byte 0x03 4.--6. " D1_LD ,Datapath permutable input mux D1_LD" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." bitfld.byte 0x03 0.--2. " D0_LD ,Datapath permutable input mux D0_LD" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." line.byte 0x04 "CFG4,Datapath Input Selection - CI_MUX SI_MUX" bitfld.byte 0x04 4.--6. " CI_MUX ,Datapath permutable input mux CI_MUX" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." bitfld.byte 0x04 0.--2. " SI_MUX ,Datapath permutable input mux SI_MUX" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." line.byte 0x05 "CFG5,Datapath Output Selection For OUT1 OUT0" bitfld.byte 0x05 4.--7. " OUT1 ,Datapath permutable output mux OUT1" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT" bitfld.byte 0x05 0.--3. " OUT0 ,Datapath permutable output mux OUT0" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT" line.byte 0x06 "CFG6,Datapath Output Selection For OUT3 OUT2" bitfld.byte 0x06 4.--7. " OUT3 ,Datapath permutable output mux OUT3" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT" bitfld.byte 0x06 0.--3. " OUT2 ,Datapath permutable output mux OUT2" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT" line.byte 0x07 "CFG7,Datapath Output Selection For OUT5 OUT4" bitfld.byte 0x07 4.--7. " OUT5 ,Datapath permutable output mux OUT5" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT" bitfld.byte 0x07 0.--3. " OUT4 ,Datapath permutable output mux OUT4" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT" line.byte 0x08 "CFG8,Datapath Output Synchronization Option" bitfld.byte 0x08 7. " NC7 ,Spare register bit NC7" "0,1" bitfld.byte 0x08 6. " NC6 ,Spare register bit NC6" "0,1" bitfld.byte 0x08 0.--5. " OUT_SYNC ,Datapath output synchronization" "REGISTERED,COMBINATIONAL,?..." line.byte 0x09 "CFG9,Datapath ALU Mask" line.byte 0x0A "CFG10,Datapath Compare 0 Mask" line.byte 0x0B "CFG11,Datapath Compare 1 Mask" line.byte 0x0C "CFG12,Datapath Mask Enables And Shift In Configuration" bitfld.byte 0x0C 7. " CMASK1_EN ,Datapath mask CMASK1 enable" "Disabled,Enabled" bitfld.byte 0x0C 6. " CMASK0_EN ,Datapath mask CMASK0 enable" "Disabled,Enabled" bitfld.byte 0x0C 5. " AMASK_EN ,Datapath mask AMASK enable" "Disabled,Enabled" bitfld.byte 0x0C 4. " DEF_SI ,Datapath default shift value" "DEFAULT_0,DEFAULT_1" textline " " bitfld.byte 0x0C 2.--3. " SI_SELB ,Datapath shift in source select" "DEFAULT,REGISTERED,ROUTE,CHAIN" bitfld.byte 0x0C 0.--1. " SI_SELA ,Datapath shift in source select" "DEFAULT,REGISTERED,ROUTE,CHAIN" line.byte 0x0D "CFG13,Datapath Carry In And Compare Configuration" bitfld.byte 0x0D 6.--7. " CMP_SELB ,Datapath compare select B" "A1_D1,A1_A0,A0_D1,A0_A0" bitfld.byte 0x0D 4.--5. " CMP_SELA ,Datapath compare select A" "A1_D1,A1_A0,A0_D1,A0_A0" bitfld.byte 0x0D 2.--3. " CI_SELB ,Datapath carry in source select B" "DEFAULT,REGISTERED,ROUTE,CHAIN" bitfld.byte 0x0D 0.--1. " CI_SELA ,Datapath carry in source select A" "DEFAULT,REGISTERED,ROUTE,CHAIN" line.byte 0x0E "CFG14,Datapath Chaining And MSB Configuration" bitfld.byte 0x0E 7. " MSB_EN ,Datapath MSB selection enable" "Disabled,Enabled" bitfld.byte 0x0E 4.--6. " MSB_SEL ,Datapath MSB selection" "BIT0,BIT1,BIT2,BIT3,BIT4,BIT5,BIT6,BIT7" bitfld.byte 0x0E 3. " CHAIN_CMSB ,Datapath CRC MSB chaining enable" "Disabled,Enabled" bitfld.byte 0x0E 2. " CHAIN_FB ,Datapath CRC feedback chaining enable" "Disabled,Enabled" textline " " bitfld.byte 0x0E 1. " CHAIN1 ,Datapath condition chaining enable 1" "Disabled,Enabled" bitfld.byte 0x0E 0. " CHAIN0 ,Datapath condition chaining enable 0" "Disabled,Enabled" line.byte 0x0F "CFG15,Datapath FIFO, Shift And Parallel Input Control" bitfld.byte 0x0F 7. " PI_SEL ,Datapath parallel input selection" "NORMAL,PARALLEL" bitfld.byte 0x0F 6. " SHIFT_SEL ,Datapath shift out selection" "SOL_MSB,SOR" bitfld.byte 0x0F 5. " PI_DYN ,Enable for dynamic control of parallel data input (Pi) mux" "Disabled,Enabled" bitfld.byte 0x0F 4. " MSB_SI ,Arithmetic shift right operation shift in selection" "DEFAULT,MSB" textline " " bitfld.byte 0x0F 2.--3. " F1_INSEL ,Datapath FIFO configuration 1" "INPUT,OUTPUT_A0,OUTPUT_A1,OUTPUT_ALU" bitfld.byte 0x0F 0.--1. " F0_INSEL ,Datapath FIFO configuration 0" "INPUT,OUTPUT_A0,OUTPUT_A1,OUTPUT_ALU" line.byte 0x10 "CFG16,Datapath FIFO And Register Access Configuration Control" bitfld.byte 0x10 7. " F1_CK_INV ,FIFO 1 clock Inverted" "NORMAL,Inverted" bitfld.byte 0x10 6. " F0_CK_INV ,FIFO 0 clock Inverted" "NORMAL,Inverted" bitfld.byte 0x10 5. " FIFO_FAST ,FIFO fast mode" "Disabled,Enabled" bitfld.byte 0x10 4. " FIFO_CAP ,FIFO software capture mode" "Disabled,Enabled" textline " " bitfld.byte 0x10 3. " FIFO_EDGE ,Edge/level sensitive FIFO write control (Fx_ld)" "LEVEL,EDGE" bitfld.byte 0x10 2. " FIFO_ASYNC ,Asynchronous FIFO clocking support" "Disabled,Enabled" bitfld.byte 0x10 1. " EXT_CRCPRS ,External CRC/PRS mode" "INTERNAL,EXTERNAL" bitfld.byte 0x10 0. " WRK16_CONCAT ,Datapath register access mode" "DEFAULT,CONCATENATE" line.byte 0x11 "CFG17,Datapath FIFO Control" bitfld.byte 0x11 4. " FIFO_ADD_SYNC ,Sync flip-flop to FIFO block status" "Disabled,Enabled" bitfld.byte 0x11 3. " NC3 ,Spare register bit NC3" "0,1" bitfld.byte 0x11 2. " NC2 ,Spare register bit NC2" "0,1" bitfld.byte 0x11 1. " F1_DYN ,FIFO 1 direction" "STATIC,DYNAMIC" textline " " bitfld.byte 0x11 0. " F0_DYN ,FIFO 0 direction" "STATIC,DYNAMIC" line.byte 0x12 "CFG18,Control Register Mode 0" line.byte 0x13 "CFG19,Control Register Mode 1" line.byte 0x14 "CFG20,Status Register Input Mode Selection" bitfld.byte 0x14 7. " STAT_MD[7] ,Bit 7 status input mode select" "Transparent,Sticky cleared" bitfld.byte 0x14 6. " [6] ,Bit 6 status input mode select" "Transparent,Sticky cleared" bitfld.byte 0x14 5. " [5] ,Bit 5 status input mode select" "Transparent,Sticky cleared" bitfld.byte 0x14 4. " [4] ,Bit 4 status input mode select" "Transparent,Sticky cleared" textline " " bitfld.byte 0x14 3. " [3] ,Bit 3 status input mode select" "Transparent,Sticky cleared" bitfld.byte 0x14 2. " [2] ,Bit 2 status input mode select" "Transparent,Sticky cleared" bitfld.byte 0x14 1. " [1] ,Bit 1 status input mode select" "Transparent,Sticky cleared" bitfld.byte 0x14 0. " [0] ,Bit 0 status input mode select" "Transparent,Sticky cleared" line.byte 0x15 "CFG21,Spare Register Bits" bitfld.byte 0x15 1. " NC1 ,Spare register bit NC1" "0,1" bitfld.byte 0x15 0. " NC0 ,Spare register bit NC0" "0,1" line.byte 0x16 "CFG22,SC Block Configuration Control" bitfld.byte 0x16 4. " SC_EXT_RES ,Control register external reset operation" "Disabled,Enabled" bitfld.byte 0x16 3. " SC_SYNC_MD ,SC sync mode" "NORMAL,SYNC_MODE" bitfld.byte 0x16 2. " SC_INT_MD ,SC interrupt mode" "NORMAL,INT_MODE" bitfld.byte 0x16 0.--1. " SC_OUT_CTL ,Output source for the status and control routing connections" "CONTROL,PARALLEL,COUNTER,?..." line.byte 0x17 "CFG23,Counter Control" bitfld.byte 0x17 6. " ALT_CNT ,Alternate operating mode of the counter" "DEFAULT_MODE,ALT_MODE" bitfld.byte 0x17 5. " ROUTE_EN ,Counter enable signal for routing input" "Disabled,Enabled" bitfld.byte 0x17 4. " ROUTE_LD ,Counter load signal for routing input" "Disabled,Enabled" bitfld.byte 0x17 2.--3. " CNT_EN_SEL ,Routing inputs for the counter enable signal" "SC_IN4,SC_IN5,SC_IN6,SC_IO" textline " " bitfld.byte 0x17 0.--1. " CNT_LD_SEL ,Routing inputs for the counter load signal" "SC_IN0,SC_IN1,SC_IN2,SC_IN3" if (((per.b(ad:0x400F3200+0x5F))&0x01)==0x01) group.byte 0x58++0x03 line.byte 0x00 "CFG24,PLD0 Clock And Reset Control" bitfld.byte 0x00 6.--7. " RC_RES_SEL ,Routed reset for the associated UDB component block" "0,1,2,3" bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x00 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x00 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x00 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x01 "CFG25,PLD1 Clock And Reset Control" bitfld.byte 0x00 6.--7. " RC_RES_SEL ,Routed reset for the associated UDB component block" "0,1,2,3" bitfld.byte 0x01 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x01 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x01 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x01 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x02 "CFG26,Datapath Clock And Reset Control" bitfld.byte 0x00 6.--7. " RC_RES_SEL ,Routed reset for the associated UDB component block" "0,1,2,3" bitfld.byte 0x02 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x02 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x02 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x02 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x03 "CFG27,Status/control Clock And Reset Control" bitfld.byte 0x00 6.--7. " RC_RES_SEL ,Routed reset for the associated UDB component block" "0,1,2,3" bitfld.byte 0x03 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x03 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x03 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x03 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" else group.byte 0x58++0x03 line.byte 0x00 "CFG24,PLD0 Clock And Reset Control" bitfld.byte 0x00 6. " FRES ,Firmware reset for the associated UDB component block" "No reset,Reset" bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x00 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x00 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x00 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x01 "CFG25,PLD1 Clock And Reset Control" bitfld.byte 0x00 6. " FRES ,Firmware reset for the associated UDB component block" "No reset,Reset" bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x00 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x00 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x00 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x02 "CFG26,Datapath Clock And Reset Control" bitfld.byte 0x00 6. " FRES ,Firmware reset for the associated UDB component block" "No reset,Reset" bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x00 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x00 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x00 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x03 "CFG27,Status/control Clock And Reset Control" rbitfld.byte 0x00 6. " FRES ,Firmware reset for the associated UDB component block" "No reset,Reset" bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x03 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x03 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x03 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" endif group.byte 0x5C++0x01 line.byte 0x00 "CFG28,Clock Selection For PLD1 And PLD0" bitfld.byte 0x00 4.--7. " PLD1_CK_SEL ,PLD1 clock selection registers" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,EXT_CLK,SYSCLK,?..." bitfld.byte 0x00 0.--3. " PLD0_CK_SEL ,PLD0 clock selection registers" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,EXT_CLK,SYSCLK,?..." line.byte 0x01 "CFG29,Clock Selection For Datapath, Status And Control" bitfld.byte 0x01 4.--7. " SC_CK_SEL ,SC clock selection registers" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,EXT_CLK,SYSCLK,?..." bitfld.byte 0x01 0.--3. " DP_CK_SEL ,DP clock selection registers" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,EXT_CLK,SYSCLK,?..." if (((per.b(ad:0x400F3200+0x5F))&0x01)==0x01) group.byte 0x5E++0x01 line.byte 0x00 "CFG30,Reset Control" bitfld.byte 0x00 7. " SC_RES_POL ,Polarity of the selected SC routed reset" "Not inverted,Inverted" bitfld.byte 0x00 6. " DP_RES_POL ,Polarity of the selected datapath routed reset" "Not inverted,Inverted" bitfld.byte 0x00 4. " GUDB_WR ,Global write operation for the configuration and working registers UDB" "Disabled,Enabled" bitfld.byte 0x00 3. " EN_RES_CNTCTL ,Routed reset to the counter/control register" "Disabled,Enabled" textline " " rbitfld.byte 0x00 2. " RES_POL ,Polarity of the routed reset" "NEGATED,ASSERTED" rbitfld.byte 0x00 0.--1. " RES_SEL ,RC routing input for the compatible reset scheme" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x01 "CFG31,Reset Control" bitfld.byte 0x01 7. " PLD1_RES_POL ,Polarity of the routed reset for both plds" "Not inverted,Inverted" bitfld.byte 0x01 6. " PLD0_RES_POL ,Polarity of the routed reset for both plds" "Not inverted,Inverted" bitfld.byte 0x01 4.--5. " EXT_CK_SEL ,External clock selection" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" bitfld.byte 0x01 3. " EN_RES_DP ,Routed reset to the datapath block" "Disabled,Enabled" textline " " bitfld.byte 0x01 2. " EN_RES_STAT ,Routed reset to the status register" "NEGATED,ASSERTED" bitfld.byte 0x01 1. " EXT_SYNC ,Synchronization of selected external clock" "Disabled,Enabled" bitfld.byte 0x01 0. " ALT_RES ,Toggles between two reset configurations" "COMPATIBLE,ALTERNATE" else group.byte 0x5E++0x01 line.byte 0x00 "CFG30,Reset Control" rbitfld.byte 0x00 7. " SC_RES_POL ,Polarity of the selected SC routed reset" "Not inverted,Inverted" rbitfld.byte 0x00 6. " DP_RES_POL ,Polarity of the selected datapath routed reset" "Not inverted,Inverted" bitfld.byte 0x00 4. " GUDB_WR ,Global write operation for the configuration and working registers UDB" "Disabled,Enabled" bitfld.byte 0x00 3. " EN_RES_CNTCTL ,Routed reset to the counter/control register" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " RES_POL ,Polarity of the routed reset" "NEGATED,ASSERTED" bitfld.byte 0x00 0.--1. " RES_SEL ,RC routing input for the compatible reset scheme" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x01 "CFG31,Reset Control" bitfld.byte 0x01 7. " PLD1_RES_POL ,Polarity of the routed reset for both plds" "Not inverted,Inverted" bitfld.byte 0x01 6. " PLD0_RES_POL ,Polarity of the routed reset for both plds" "Not inverted,Inverted" bitfld.byte 0x01 4.--5. " EXT_CK_SEL ,External clock selection" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" rbitfld.byte 0x01 3. " EN_RES_DP ,Routed reset to the datapath block" "Disabled,Enabled" textline " " rbitfld.byte 0x01 2. " EN_RES_STAT ,Routed reset to the status register" "NEGATED,ASSERTED" bitfld.byte 0x01 1. " EXT_SYNC ,Synchronization of selected external clock" "Disabled,Enabled" bitfld.byte 0x01 0. " ALT_RES ,Toggles between two reset configurations" "COMPATIBLE,ALTERNATE" endif group.word 0x60++0x01 line.word 0x00 "DCFG0,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x62++0x01 line.word 0x00 "DCFG1,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x64++0x01 line.word 0x00 "DCFG2,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x66++0x01 line.word 0x00 "DCFG3,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x68++0x01 line.word 0x00 "DCFG4,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x6A++0x01 line.word 0x00 "DCFG5,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x6C++0x01 line.word 0x00 "DCFG6,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x6E++0x01 line.word 0x00 "DCFG7,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" width 0x0B tree.end tree "UDB P1 U1" base ad:0x400F3280 width 22. group.long 0x0++0x03 line.long 0x00 "PLD_IT0,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT0T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT0T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT0T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT0T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT0T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT0T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT0T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT0T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT0T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT0T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT0T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT0T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT0T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT0T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT0T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT0T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT0C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT0C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT0C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT0C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT0C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT0C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT0C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT0C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT0C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT0C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT0C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT0C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT0C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT0C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT0C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT0C_0 ,PLD0 complement input term 0" "0,1" group.long 0x4++0x03 line.long 0x00 "PLD_IT1,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT1T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT1T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT1T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT1T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT1T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT1T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT1T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT1T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT1T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT1T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT1T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT1T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT1T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT1T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT1T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT1T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT1C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT1C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT1C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT1C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT1C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT1C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT1C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT1C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT1C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT1C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT1C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT1C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT1C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT1C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT1C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT1C_0 ,PLD0 complement input term 0" "0,1" group.long 0x8++0x03 line.long 0x00 "PLD_IT2,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT2T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT2T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT2T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT2T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT2T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT2T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT2T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT2T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT2T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT2T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT2T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT2T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT2T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT2T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT2T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT2T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT2C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT2C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT2C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT2C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT2C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT2C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT2C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT2C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT2C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT2C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT2C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT2C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT2C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT2C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT2C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT2C_0 ,PLD0 complement input term 0" "0,1" group.long 0xC++0x03 line.long 0x00 "PLD_IT3,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT3T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT3T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT3T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT3T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT3T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT3T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT3T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT3T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT3T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT3T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT3T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT3T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT3T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT3T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT3T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT3T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT3C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT3C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT3C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT3C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT3C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT3C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT3C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT3C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT3C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT3C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT3C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT3C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT3C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT3C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT3C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT3C_0 ,PLD0 complement input term 0" "0,1" group.long 0x10++0x03 line.long 0x00 "PLD_IT4,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT4T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT4T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT4T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT4T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT4T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT4T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT4T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT4T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT4T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT4T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT4T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT4T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT4T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT4T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT4T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT4T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT4C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT4C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT4C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT4C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT4C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT4C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT4C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT4C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT4C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT4C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT4C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT4C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT4C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT4C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT4C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT4C_0 ,PLD0 complement input term 0" "0,1" group.long 0x14++0x03 line.long 0x00 "PLD_IT5,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT5T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT5T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT5T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT5T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT5T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT5T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT5T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT5T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT5T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT5T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT5T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT5T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT5T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT5T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT5T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT5T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT5C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT5C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT5C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT5C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT5C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT5C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT5C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT5C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT5C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT5C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT5C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT5C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT5C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT5C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT5C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT5C_0 ,PLD0 complement input term 0" "0,1" group.long 0x18++0x03 line.long 0x00 "PLD_IT6,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT6T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT6T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT6T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT6T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT6T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT6T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT6T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT6T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT6T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT6T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT6T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT6T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT6T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT6T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT6T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT6T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT6C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT6C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT6C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT6C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT6C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT6C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT6C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT6C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT6C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT6C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT6C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT6C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT6C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT6C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT6C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT6C_0 ,PLD0 complement input term 0" "0,1" group.long 0x1C++0x03 line.long 0x00 "PLD_IT7,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT7T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT7T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT7T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT7T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT7T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT7T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT7T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT7T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT7T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT7T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT7T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT7T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT7T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT7T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT7T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT7T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT7C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT7C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT7C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT7C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT7C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT7C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT7C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT7C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT7C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT7C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT7C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT7C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT7C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT7C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT7C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT7C_0 ,PLD0 complement input term 0" "0,1" group.long 0x20++0x03 line.long 0x00 "PLD_IT8,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT8T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT8T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT8T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT8T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT8T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT8T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT8T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT8T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT8T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT8T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT8T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT8T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT8T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT8T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT8T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT8T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT8C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT8C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT8C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT8C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT8C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT8C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT8C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT8C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT8C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT8C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT8C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT8C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT8C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT8C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT8C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT8C_0 ,PLD0 complement input term 0" "0,1" group.long 0x24++0x03 line.long 0x00 "PLD_IT9,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT9T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT9T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT9T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT9T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT9T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT9T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT9T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT9T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT9T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT9T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT9T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT9T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT9T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT9T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT9T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT9T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT9C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT9C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT9C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT9C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT9C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT9C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT9C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT9C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT9C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT9C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT9C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT9C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT9C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT9C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT9C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT9C_0 ,PLD0 complement input term 0" "0,1" group.long 0x28++0x03 line.long 0x00 "PLD_IT10,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT10T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT10T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT10T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT10T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT10T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT10T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT10T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT10T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT10T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT10T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT10T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT10T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT10T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT10T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT10T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT10T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT10C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT10C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT10C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT10C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT10C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT10C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT10C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT10C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT10C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT10C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT10C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT10C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT10C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT10C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT10C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT10C_0 ,PLD0 complement input term 0" "0,1" group.long 0x2C++0x03 line.long 0x00 "PLD_IT11,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT11T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT11T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT11T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT11T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT11T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT11T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT11T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT11T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT11T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT11T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT11T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT11T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT11T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT11T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT11T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT11T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT11C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT11C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT11C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT11C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT11C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT11C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT11C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT11C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT11C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT11C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT11C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT11C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT11C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT11C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT11C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT11C_0 ,PLD0 complement input term 0" "0,1" group.word 0x30++0x01 line.word 0x00 "PLD_ORT0,PLD OR Terms" bitfld.word 0x00 15. " PLD1_ORT_PT0_7 ,PLD1 OR term 7" "0,1" bitfld.word 0x00 14. " PLD1_ORT_PT0_6 ,PLD1 OR term 6" "0,1" bitfld.word 0x00 13. " PLD1_ORT_PT0_5 ,PLD1 OR term 5" "0,1" bitfld.word 0x00 12. " PLD1_ORT_PT0_4 ,PLD1 OR term 4" "0,1" textline " " bitfld.word 0x00 11. " PLD1_ORT_PT0_3 ,PLD1 OR term 3" "0,1" bitfld.word 0x00 10. " PLD1_ORT_PT0_2 ,PLD1 OR term 2" "0,1" bitfld.word 0x00 9. " PLD1_ORT_PT0_1 ,PLD1 OR term 1" "0,1" bitfld.word 0x00 8. " PLD1_ORT_PT0_0 ,PLD1 OR term 0" "0,1" textline " " bitfld.word 0x00 7. " PLD0_ORT_PT0_7 ,PLD0 OR term 7" "0,1" bitfld.word 0x00 6. " PLD0_ORT_PT0_6 ,PLD0 OR term 6" "0,1" bitfld.word 0x00 5. " PLD0_ORT_PT0_5 ,PLD0 OR term 5" "0,1" bitfld.word 0x00 4. " PLD0_ORT_PT0_4 ,PLD0 OR term 4" "0,1" textline " " bitfld.word 0x00 3. " PLD0_ORT_PT0_3 ,PLD0 OR term 3" "0,1" bitfld.word 0x00 2. " PLD0_ORT_PT0_2 ,PLD0 OR term 2" "0,1" bitfld.word 0x00 1. " PLD0_ORT_PT0_1 ,PLD0 OR term 1" "0,1" bitfld.word 0x00 0. " PLD0_ORT_PT0_0 ,PLD0 OR term 0" "0,1" group.word 0x32++0x01 line.word 0x00 "PLD_ORT1,PLD OR Terms" bitfld.word 0x00 15. " PLD1_ORT_PT1_7 ,PLD1 OR term 7" "0,1" bitfld.word 0x00 14. " PLD1_ORT_PT1_6 ,PLD1 OR term 6" "0,1" bitfld.word 0x00 13. " PLD1_ORT_PT1_5 ,PLD1 OR term 5" "0,1" bitfld.word 0x00 12. " PLD1_ORT_PT1_4 ,PLD1 OR term 4" "0,1" textline " " bitfld.word 0x00 11. " PLD1_ORT_PT1_3 ,PLD1 OR term 3" "0,1" bitfld.word 0x00 10. " PLD1_ORT_PT1_2 ,PLD1 OR term 2" "0,1" bitfld.word 0x00 9. " PLD1_ORT_PT1_1 ,PLD1 OR term 1" "0,1" bitfld.word 0x00 8. " PLD1_ORT_PT1_0 ,PLD1 OR term 0" "0,1" textline " " bitfld.word 0x00 7. " PLD0_ORT_PT1_7 ,PLD0 OR term 7" "0,1" bitfld.word 0x00 6. " PLD0_ORT_PT1_6 ,PLD0 OR term 6" "0,1" bitfld.word 0x00 5. " PLD0_ORT_PT1_5 ,PLD0 OR term 5" "0,1" bitfld.word 0x00 4. " PLD0_ORT_PT1_4 ,PLD0 OR term 4" "0,1" textline " " bitfld.word 0x00 3. " PLD0_ORT_PT1_3 ,PLD0 OR term 3" "0,1" bitfld.word 0x00 2. " PLD0_ORT_PT1_2 ,PLD0 OR term 2" "0,1" bitfld.word 0x00 1. " PLD0_ORT_PT1_1 ,PLD0 OR term 1" "0,1" bitfld.word 0x00 0. " PLD0_ORT_PT1_0 ,PLD0 OR term 0" "0,1" group.word 0x34++0x01 line.word 0x00 "PLD_ORT2,PLD OR Terms" bitfld.word 0x00 15. " PLD1_ORT_PT2_7 ,PLD1 OR term 7" "0,1" bitfld.word 0x00 14. " PLD1_ORT_PT2_6 ,PLD1 OR term 6" "0,1" bitfld.word 0x00 13. " PLD1_ORT_PT2_5 ,PLD1 OR term 5" "0,1" bitfld.word 0x00 12. " PLD1_ORT_PT2_4 ,PLD1 OR term 4" "0,1" textline " " bitfld.word 0x00 11. " PLD1_ORT_PT2_3 ,PLD1 OR term 3" "0,1" bitfld.word 0x00 10. " PLD1_ORT_PT2_2 ,PLD1 OR term 2" "0,1" bitfld.word 0x00 9. " PLD1_ORT_PT2_1 ,PLD1 OR term 1" "0,1" bitfld.word 0x00 8. " PLD1_ORT_PT2_0 ,PLD1 OR term 0" "0,1" textline " " bitfld.word 0x00 7. " PLD0_ORT_PT2_7 ,PLD0 OR term 7" "0,1" bitfld.word 0x00 6. " PLD0_ORT_PT2_6 ,PLD0 OR term 6" "0,1" bitfld.word 0x00 5. " PLD0_ORT_PT2_5 ,PLD0 OR term 5" "0,1" bitfld.word 0x00 4. " PLD0_ORT_PT2_4 ,PLD0 OR term 4" "0,1" textline " " bitfld.word 0x00 3. " PLD0_ORT_PT2_3 ,PLD0 OR term 3" "0,1" bitfld.word 0x00 2. " PLD0_ORT_PT2_2 ,PLD0 OR term 2" "0,1" bitfld.word 0x00 1. " PLD0_ORT_PT2_1 ,PLD0 OR term 1" "0,1" bitfld.word 0x00 0. " PLD0_ORT_PT2_0 ,PLD0 OR term 0" "0,1" group.word 0x36++0x01 line.word 0x00 "PLD_ORT3,PLD OR Terms" bitfld.word 0x00 15. " PLD1_ORT_PT3_7 ,PLD1 OR term 7" "0,1" bitfld.word 0x00 14. " PLD1_ORT_PT3_6 ,PLD1 OR term 6" "0,1" bitfld.word 0x00 13. " PLD1_ORT_PT3_5 ,PLD1 OR term 5" "0,1" bitfld.word 0x00 12. " PLD1_ORT_PT3_4 ,PLD1 OR term 4" "0,1" textline " " bitfld.word 0x00 11. " PLD1_ORT_PT3_3 ,PLD1 OR term 3" "0,1" bitfld.word 0x00 10. " PLD1_ORT_PT3_2 ,PLD1 OR term 2" "0,1" bitfld.word 0x00 9. " PLD1_ORT_PT3_1 ,PLD1 OR term 1" "0,1" bitfld.word 0x00 8. " PLD1_ORT_PT3_0 ,PLD1 OR term 0" "0,1" textline " " bitfld.word 0x00 7. " PLD0_ORT_PT3_7 ,PLD0 OR term 7" "0,1" bitfld.word 0x00 6. " PLD0_ORT_PT3_6 ,PLD0 OR term 6" "0,1" bitfld.word 0x00 5. " PLD0_ORT_PT3_5 ,PLD0 OR term 5" "0,1" bitfld.word 0x00 4. " PLD0_ORT_PT3_4 ,PLD0 OR term 4" "0,1" textline " " bitfld.word 0x00 3. " PLD0_ORT_PT3_3 ,PLD0 OR term 3" "0,1" bitfld.word 0x00 2. " PLD0_ORT_PT3_2 ,PLD0 OR term 2" "0,1" bitfld.word 0x00 1. " PLD0_ORT_PT3_1 ,PLD0 OR term 1" "0,1" bitfld.word 0x00 0. " PLD0_ORT_PT3_0 ,PLD0 OR term 0" "0,1" group.word 0x38++0x07 line.word 0x00 "PLD_MC_CFG_CEN_CONST,Macrocell Configuration For Carry Enable And Constant" bitfld.word 0x00 15. " PLD1_MC3_DFF_C ,PLD1 MC3 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 14. " PLD1_MC3_CEN ,PLD1 MC3 carry enable" "Disabled,Enabled" bitfld.word 0x00 13. " PLD1_MC2_DFF_C ,PLD1 MC2 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 12. " PLD1_MC2_CEN ,PLD1 MC2 carry enable" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " PLD1_MC1_DFF_C ,PLD1 MC1 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 10. " PLD1_MC1_CEN ,PLD1 MC1 carry enable" "Disabled,Enabled" bitfld.word 0x00 9. " PLD1_MC0_DFF_C ,PLD1 MC0 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 8. " PLD1_MC0_CEN ,PLD1 MC0 carry enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " PLD0_MC3_DFF_C ,PLD0 MC3 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 6. " PLD0_MC3_CEN ,PLD0 MC3 carry enable" "Disabled,Enabled" bitfld.word 0x00 5. " PLD0_MC2_DFF_C ,PLD0 MC2 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 4. " PLD0_MC2_CEN ,PLD0 MC2 carry enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " PLD0_MC1_DFF_C ,PLD0 MC1 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 2. " PLD0_MC1_CEN ,PLD0 MC1 carry enable" "Disabled,Enabled" bitfld.word 0x00 1. " PLD0_MC0_DFF_C ,PLD0 MC0 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 0. " PLD0_MC0_CEN ,PLD0_MC0 carry enable" "Disabled,Enabled" line.word 0x02 "PLD_MC_CFG_XORFB,PLD Macro Cell XOR Feedback" bitfld.word 0x02 14.--15. " PLD1_MC3_XORFB ,PLD1 MC3 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" bitfld.word 0x02 12.--13. " PLD1_MC2_XORFB ,PLD1 MC2 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" bitfld.word 0x02 10.--11. " PLD1_MC1_XORFB ,PLD1 MC1 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" bitfld.word 0x02 8.--9. " PLD1_MC0_XORFB ,PLD1 MC0 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" textline " " bitfld.word 0x02 6.--7. " PLD0_MC3_XORFB ,PLD0 MC3 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" bitfld.word 0x02 4.--5. " PLD0_MC2_XORFB ,PLD0 MC2 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" bitfld.word 0x02 2.--3. " PLD0_MC1_XORFB ,PLD0 MC1 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" bitfld.word 0x02 0.--1. " PLD0_MC0_XORFB ,PLD0 MC0 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" line.word 0x04 "PLD_MC_SET_RESET,PLD Macro Cell Set Reset Selection" bitfld.word 0x04 15. " PLD1_MC3_RESET_SEL ,PLD1 MC3 reset select enable" "Disabled,Enabled" bitfld.word 0x04 14. " PLD1_MC3_SET_SEL ,PLD1 MC3 set select enable" "Disabled,Enabled" bitfld.word 0x04 13. " PLD1_MC2_RESET_SEL ,PLD1 MC2 reset select enable" "Disabled,Enabled" bitfld.word 0x04 12. " PLD1_MC2_SET_SEL ,PLD1 MC2 set select enable" "Disabled,Enabled" textline " " bitfld.word 0x04 11. " PLD1_MC1_RESET_SEL ,PLD1 MC1 reset select enable" "Disabled,Enabled" bitfld.word 0x04 10. " PLD1_MC1_SET_SEL ,PLD1 MC0 set select enable" "Disabled,Enabled" bitfld.word 0x04 9. " PLD1_MC0_RESET_SEL ,PLD1 MC0 reset select enable" "Disabled,Enabled" bitfld.word 0x04 8. " PLD1_MC0_SET_SEL ,PLD1 MC0 set select enable" "Disabled,Enabled" textline " " bitfld.word 0x04 7. " PLD0_MC3_RESET_SEL ,PLD0 MC3 reset select enable" "Disabled,Enabled" bitfld.word 0x04 6. " PLD0_MC3_SET_SEL ,PLD0 MC3 set select enable" "Disabled,Enabled" bitfld.word 0x04 5. " PLD0_MC2_RESET_SEL ,PLD0 MC2 reset select enable" "Disabled,Enabled" bitfld.word 0x04 4. " PLD0_MC2_SET_SEL ,PLD0 MC2 set select enable" "Disabled,Enabled" textline " " bitfld.word 0x04 3. " PLD0_MC1_RESET_SEL ,PLD0 MC1 reset select enable" "Disabled,Enabled" bitfld.word 0x04 2. " PLD0_MC1_SET_SEL ,PLD0 MC1 set select enable" "Disabled,Enabled" bitfld.word 0x04 1. " PLD0_MC0_RESET_SEL ,Reset select enable" "Disabled,Enabled" bitfld.word 0x04 0. " PLD0_MC0_SET_SEL ,PLD0 MC0 set select enable" "Disabled,Enabled" line.word 0x06 "PLD_MC_CFG_BYPASS,PLD Macro Cell Bypass Control" bitfld.word 0x06 15. " NC15 ,Spare register bit NC15" "0,1" bitfld.word 0x06 14. " PLD1_MC3_BYPASS ,PLD1 MC3 bypass selection" "REGISTER,COMBINATIONAL" bitfld.word 0x06 13. " NC13 ,Spare register bit NC13" "0,1" bitfld.word 0x06 12. " PLD1_MC2_BYPASS ,PLD1 MC2 bypass selection" "REGISTER,COMBINATIONAL" textline " " bitfld.word 0x06 11. " NC11 ,Spare register bit NC11" "0,1" bitfld.word 0x06 10. " PLD1_MC1_BYPASS ,PLD1 MC1 bypass selection" "REGISTER,COMBINATIONAL" bitfld.word 0x06 9. " NC9 ,Spare register bit NC9" "0,1" bitfld.word 0x06 8. " PLD1_MC0_BYPASS ,PLD1 MC0 bypass selection" "REGISTER,COMBINATIONAL" textline " " bitfld.word 0x06 7. " NC7 ,Spare register bit NC7" "0,1" bitfld.word 0x06 6. " PLD0_MC3_BYPASS ,PLD0 MC3 bypass selection" "REGISTER,COMBINATIONAL" bitfld.word 0x06 5. " NC5 ,Spare register bit NC5" "0,1" bitfld.word 0x06 4. " PLD0_MC2_BYPASS ,PLD0 MC2 bypass selection" "REGISTER,COMBINATIONAL" textline " " bitfld.word 0x06 3. " NC3 ,Spare register bit NC3" "0,1" bitfld.word 0x06 2. " PLD0_MC1_BYPASS ,PLD0 MC1 bypass selection" "REGISTER,COMBINATIONAL" bitfld.word 0x06 1. " NC1 ,Spare register bit NC1" "0,1" bitfld.word 0x06 0. " PLD0_MC0_BYPASS ,PLD0 MC0 bypass selection" "REGISTER,COMBINATIONAL" group.byte 0x40++0x17 line.byte 0x00 "CFG0,Datapath Input Selection - RAD1 RAD0. Address Bits 0 And 1 To The Dynamic Configuration RAM" bitfld.byte 0x00 4.--6. " RAD1 ,Datapath permutable input mux RAD1" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." bitfld.byte 0x00 0.--2. " RAD0 ,Datapath permutable input mux RAD0" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." line.byte 0x01 "CFG1,Datapath Input Selection - RAD2. Address Bit 2 To The Dynamic Configuration RAM" bitfld.byte 0x01 7. " DP_RTE_BYPASS4 ,Dp_in bypass control 4" "DP_IN4_ROUTE,DP_IN4_BYPASS" bitfld.byte 0x01 6. " DP_RTE_BYPASS3 ,Dp_in bypass control 3" "DP_IN3_ROUTE,DP_IN3_BYPASS" bitfld.byte 0x01 5. " DP_RTE_BYPASS2 ,Dp_in bypass control 2" "DP_IN2_ROUTE,DP_IN2_BYPASS" bitfld.byte 0x01 4. " DP_RTE_BYPASS1 ,Dp_in bypass control 1" "DP_IN1_ROUTE,DP_IN1_BYPASS" textline " " bitfld.byte 0x01 3. " DP_RTE_BYPASS0 ,Dp_in bypass control 0" "DP_IN0_ROUTE,DP_IN0_BYPASS" bitfld.byte 0x01 0.--2. " RAD2 ,Datapath permutable input mux 2" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." line.byte 0x02 "CFG2,Datapath Input Selection - F1_LD, F0_LD" bitfld.byte 0x02 7. " NC7 ,Spare register bit NC7" "0,1" bitfld.byte 0x02 4.--6. " F1_LD ,Datapath permutable input mux F1_LD" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." bitfld.byte 0x02 3. " DP_RTE_BYPASS5 ,Dp_in bypass control 5" "DP_IN5_ROUTE,DP_IN5_BYPASS" bitfld.byte 0x02 0.--2. " F0_LD ,Datapath permutable input mux F0_LD" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." line.byte 0x03 "CFG3,Datapath Input Selection - D1_LD, D0_LD" bitfld.byte 0x03 4.--6. " D1_LD ,Datapath permutable input mux D1_LD" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." bitfld.byte 0x03 0.--2. " D0_LD ,Datapath permutable input mux D0_LD" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." line.byte 0x04 "CFG4,Datapath Input Selection - CI_MUX SI_MUX" bitfld.byte 0x04 4.--6. " CI_MUX ,Datapath permutable input mux CI_MUX" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." bitfld.byte 0x04 0.--2. " SI_MUX ,Datapath permutable input mux SI_MUX" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." line.byte 0x05 "CFG5,Datapath Output Selection For OUT1 OUT0" bitfld.byte 0x05 4.--7. " OUT1 ,Datapath permutable output mux OUT1" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT" bitfld.byte 0x05 0.--3. " OUT0 ,Datapath permutable output mux OUT0" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT" line.byte 0x06 "CFG6,Datapath Output Selection For OUT3 OUT2" bitfld.byte 0x06 4.--7. " OUT3 ,Datapath permutable output mux OUT3" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT" bitfld.byte 0x06 0.--3. " OUT2 ,Datapath permutable output mux OUT2" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT" line.byte 0x07 "CFG7,Datapath Output Selection For OUT5 OUT4" bitfld.byte 0x07 4.--7. " OUT5 ,Datapath permutable output mux OUT5" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT" bitfld.byte 0x07 0.--3. " OUT4 ,Datapath permutable output mux OUT4" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT" line.byte 0x08 "CFG8,Datapath Output Synchronization Option" bitfld.byte 0x08 7. " NC7 ,Spare register bit NC7" "0,1" bitfld.byte 0x08 6. " NC6 ,Spare register bit NC6" "0,1" bitfld.byte 0x08 0.--5. " OUT_SYNC ,Datapath output synchronization" "REGISTERED,COMBINATIONAL,?..." line.byte 0x09 "CFG9,Datapath ALU Mask" line.byte 0x0A "CFG10,Datapath Compare 0 Mask" line.byte 0x0B "CFG11,Datapath Compare 1 Mask" line.byte 0x0C "CFG12,Datapath Mask Enables And Shift In Configuration" bitfld.byte 0x0C 7. " CMASK1_EN ,Datapath mask CMASK1 enable" "Disabled,Enabled" bitfld.byte 0x0C 6. " CMASK0_EN ,Datapath mask CMASK0 enable" "Disabled,Enabled" bitfld.byte 0x0C 5. " AMASK_EN ,Datapath mask AMASK enable" "Disabled,Enabled" bitfld.byte 0x0C 4. " DEF_SI ,Datapath default shift value" "DEFAULT_0,DEFAULT_1" textline " " bitfld.byte 0x0C 2.--3. " SI_SELB ,Datapath shift in source select" "DEFAULT,REGISTERED,ROUTE,CHAIN" bitfld.byte 0x0C 0.--1. " SI_SELA ,Datapath shift in source select" "DEFAULT,REGISTERED,ROUTE,CHAIN" line.byte 0x0D "CFG13,Datapath Carry In And Compare Configuration" bitfld.byte 0x0D 6.--7. " CMP_SELB ,Datapath compare select B" "A1_D1,A1_A0,A0_D1,A0_A0" bitfld.byte 0x0D 4.--5. " CMP_SELA ,Datapath compare select A" "A1_D1,A1_A0,A0_D1,A0_A0" bitfld.byte 0x0D 2.--3. " CI_SELB ,Datapath carry in source select B" "DEFAULT,REGISTERED,ROUTE,CHAIN" bitfld.byte 0x0D 0.--1. " CI_SELA ,Datapath carry in source select A" "DEFAULT,REGISTERED,ROUTE,CHAIN" line.byte 0x0E "CFG14,Datapath Chaining And MSB Configuration" bitfld.byte 0x0E 7. " MSB_EN ,Datapath MSB selection enable" "Disabled,Enabled" bitfld.byte 0x0E 4.--6. " MSB_SEL ,Datapath MSB selection" "BIT0,BIT1,BIT2,BIT3,BIT4,BIT5,BIT6,BIT7" bitfld.byte 0x0E 3. " CHAIN_CMSB ,Datapath CRC MSB chaining enable" "Disabled,Enabled" bitfld.byte 0x0E 2. " CHAIN_FB ,Datapath CRC feedback chaining enable" "Disabled,Enabled" textline " " bitfld.byte 0x0E 1. " CHAIN1 ,Datapath condition chaining enable 1" "Disabled,Enabled" bitfld.byte 0x0E 0. " CHAIN0 ,Datapath condition chaining enable 0" "Disabled,Enabled" line.byte 0x0F "CFG15,Datapath FIFO, Shift And Parallel Input Control" bitfld.byte 0x0F 7. " PI_SEL ,Datapath parallel input selection" "NORMAL,PARALLEL" bitfld.byte 0x0F 6. " SHIFT_SEL ,Datapath shift out selection" "SOL_MSB,SOR" bitfld.byte 0x0F 5. " PI_DYN ,Enable for dynamic control of parallel data input (Pi) mux" "Disabled,Enabled" bitfld.byte 0x0F 4. " MSB_SI ,Arithmetic shift right operation shift in selection" "DEFAULT,MSB" textline " " bitfld.byte 0x0F 2.--3. " F1_INSEL ,Datapath FIFO configuration 1" "INPUT,OUTPUT_A0,OUTPUT_A1,OUTPUT_ALU" bitfld.byte 0x0F 0.--1. " F0_INSEL ,Datapath FIFO configuration 0" "INPUT,OUTPUT_A0,OUTPUT_A1,OUTPUT_ALU" line.byte 0x10 "CFG16,Datapath FIFO And Register Access Configuration Control" bitfld.byte 0x10 7. " F1_CK_INV ,FIFO 1 clock Inverted" "NORMAL,Inverted" bitfld.byte 0x10 6. " F0_CK_INV ,FIFO 0 clock Inverted" "NORMAL,Inverted" bitfld.byte 0x10 5. " FIFO_FAST ,FIFO fast mode" "Disabled,Enabled" bitfld.byte 0x10 4. " FIFO_CAP ,FIFO software capture mode" "Disabled,Enabled" textline " " bitfld.byte 0x10 3. " FIFO_EDGE ,Edge/level sensitive FIFO write control (Fx_ld)" "LEVEL,EDGE" bitfld.byte 0x10 2. " FIFO_ASYNC ,Asynchronous FIFO clocking support" "Disabled,Enabled" bitfld.byte 0x10 1. " EXT_CRCPRS ,External CRC/PRS mode" "INTERNAL,EXTERNAL" bitfld.byte 0x10 0. " WRK16_CONCAT ,Datapath register access mode" "DEFAULT,CONCATENATE" line.byte 0x11 "CFG17,Datapath FIFO Control" bitfld.byte 0x11 4. " FIFO_ADD_SYNC ,Sync flip-flop to FIFO block status" "Disabled,Enabled" bitfld.byte 0x11 3. " NC3 ,Spare register bit NC3" "0,1" bitfld.byte 0x11 2. " NC2 ,Spare register bit NC2" "0,1" bitfld.byte 0x11 1. " F1_DYN ,FIFO 1 direction" "STATIC,DYNAMIC" textline " " bitfld.byte 0x11 0. " F0_DYN ,FIFO 0 direction" "STATIC,DYNAMIC" line.byte 0x12 "CFG18,Control Register Mode 0" line.byte 0x13 "CFG19,Control Register Mode 1" line.byte 0x14 "CFG20,Status Register Input Mode Selection" bitfld.byte 0x14 7. " STAT_MD[7] ,Bit 7 status input mode select" "Transparent,Sticky cleared" bitfld.byte 0x14 6. " [6] ,Bit 6 status input mode select" "Transparent,Sticky cleared" bitfld.byte 0x14 5. " [5] ,Bit 5 status input mode select" "Transparent,Sticky cleared" bitfld.byte 0x14 4. " [4] ,Bit 4 status input mode select" "Transparent,Sticky cleared" textline " " bitfld.byte 0x14 3. " [3] ,Bit 3 status input mode select" "Transparent,Sticky cleared" bitfld.byte 0x14 2. " [2] ,Bit 2 status input mode select" "Transparent,Sticky cleared" bitfld.byte 0x14 1. " [1] ,Bit 1 status input mode select" "Transparent,Sticky cleared" bitfld.byte 0x14 0. " [0] ,Bit 0 status input mode select" "Transparent,Sticky cleared" line.byte 0x15 "CFG21,Spare Register Bits" bitfld.byte 0x15 1. " NC1 ,Spare register bit NC1" "0,1" bitfld.byte 0x15 0. " NC0 ,Spare register bit NC0" "0,1" line.byte 0x16 "CFG22,SC Block Configuration Control" bitfld.byte 0x16 4. " SC_EXT_RES ,Control register external reset operation" "Disabled,Enabled" bitfld.byte 0x16 3. " SC_SYNC_MD ,SC sync mode" "NORMAL,SYNC_MODE" bitfld.byte 0x16 2. " SC_INT_MD ,SC interrupt mode" "NORMAL,INT_MODE" bitfld.byte 0x16 0.--1. " SC_OUT_CTL ,Output source for the status and control routing connections" "CONTROL,PARALLEL,COUNTER,?..." line.byte 0x17 "CFG23,Counter Control" bitfld.byte 0x17 6. " ALT_CNT ,Alternate operating mode of the counter" "DEFAULT_MODE,ALT_MODE" bitfld.byte 0x17 5. " ROUTE_EN ,Counter enable signal for routing input" "Disabled,Enabled" bitfld.byte 0x17 4. " ROUTE_LD ,Counter load signal for routing input" "Disabled,Enabled" bitfld.byte 0x17 2.--3. " CNT_EN_SEL ,Routing inputs for the counter enable signal" "SC_IN4,SC_IN5,SC_IN6,SC_IO" textline " " bitfld.byte 0x17 0.--1. " CNT_LD_SEL ,Routing inputs for the counter load signal" "SC_IN0,SC_IN1,SC_IN2,SC_IN3" if (((per.b(ad:0x400F3280+0x5F))&0x01)==0x01) group.byte 0x58++0x03 line.byte 0x00 "CFG24,PLD0 Clock And Reset Control" bitfld.byte 0x00 6.--7. " RC_RES_SEL ,Routed reset for the associated UDB component block" "0,1,2,3" bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x00 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x00 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x00 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x01 "CFG25,PLD1 Clock And Reset Control" bitfld.byte 0x00 6.--7. " RC_RES_SEL ,Routed reset for the associated UDB component block" "0,1,2,3" bitfld.byte 0x01 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x01 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x01 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x01 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x02 "CFG26,Datapath Clock And Reset Control" bitfld.byte 0x00 6.--7. " RC_RES_SEL ,Routed reset for the associated UDB component block" "0,1,2,3" bitfld.byte 0x02 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x02 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x02 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x02 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x03 "CFG27,Status/control Clock And Reset Control" bitfld.byte 0x00 6.--7. " RC_RES_SEL ,Routed reset for the associated UDB component block" "0,1,2,3" bitfld.byte 0x03 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x03 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x03 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x03 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" else group.byte 0x58++0x03 line.byte 0x00 "CFG24,PLD0 Clock And Reset Control" bitfld.byte 0x00 6. " FRES ,Firmware reset for the associated UDB component block" "No reset,Reset" bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x00 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x00 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x00 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x01 "CFG25,PLD1 Clock And Reset Control" bitfld.byte 0x00 6. " FRES ,Firmware reset for the associated UDB component block" "No reset,Reset" bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x00 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x00 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x00 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x02 "CFG26,Datapath Clock And Reset Control" bitfld.byte 0x00 6. " FRES ,Firmware reset for the associated UDB component block" "No reset,Reset" bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x00 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x00 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x00 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x03 "CFG27,Status/control Clock And Reset Control" rbitfld.byte 0x00 6. " FRES ,Firmware reset for the associated UDB component block" "No reset,Reset" bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x03 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x03 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x03 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" endif group.byte 0x5C++0x01 line.byte 0x00 "CFG28,Clock Selection For PLD1 And PLD0" bitfld.byte 0x00 4.--7. " PLD1_CK_SEL ,PLD1 clock selection registers" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,EXT_CLK,SYSCLK,?..." bitfld.byte 0x00 0.--3. " PLD0_CK_SEL ,PLD0 clock selection registers" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,EXT_CLK,SYSCLK,?..." line.byte 0x01 "CFG29,Clock Selection For Datapath, Status And Control" bitfld.byte 0x01 4.--7. " SC_CK_SEL ,SC clock selection registers" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,EXT_CLK,SYSCLK,?..." bitfld.byte 0x01 0.--3. " DP_CK_SEL ,DP clock selection registers" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,EXT_CLK,SYSCLK,?..." if (((per.b(ad:0x400F3280+0x5F))&0x01)==0x01) group.byte 0x5E++0x01 line.byte 0x00 "CFG30,Reset Control" bitfld.byte 0x00 7. " SC_RES_POL ,Polarity of the selected SC routed reset" "Not inverted,Inverted" bitfld.byte 0x00 6. " DP_RES_POL ,Polarity of the selected datapath routed reset" "Not inverted,Inverted" bitfld.byte 0x00 4. " GUDB_WR ,Global write operation for the configuration and working registers UDB" "Disabled,Enabled" bitfld.byte 0x00 3. " EN_RES_CNTCTL ,Routed reset to the counter/control register" "Disabled,Enabled" textline " " rbitfld.byte 0x00 2. " RES_POL ,Polarity of the routed reset" "NEGATED,ASSERTED" rbitfld.byte 0x00 0.--1. " RES_SEL ,RC routing input for the compatible reset scheme" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x01 "CFG31,Reset Control" bitfld.byte 0x01 7. " PLD1_RES_POL ,Polarity of the routed reset for both plds" "Not inverted,Inverted" bitfld.byte 0x01 6. " PLD0_RES_POL ,Polarity of the routed reset for both plds" "Not inverted,Inverted" bitfld.byte 0x01 4.--5. " EXT_CK_SEL ,External clock selection" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" bitfld.byte 0x01 3. " EN_RES_DP ,Routed reset to the datapath block" "Disabled,Enabled" textline " " bitfld.byte 0x01 2. " EN_RES_STAT ,Routed reset to the status register" "NEGATED,ASSERTED" bitfld.byte 0x01 1. " EXT_SYNC ,Synchronization of selected external clock" "Disabled,Enabled" bitfld.byte 0x01 0. " ALT_RES ,Toggles between two reset configurations" "COMPATIBLE,ALTERNATE" else group.byte 0x5E++0x01 line.byte 0x00 "CFG30,Reset Control" rbitfld.byte 0x00 7. " SC_RES_POL ,Polarity of the selected SC routed reset" "Not inverted,Inverted" rbitfld.byte 0x00 6. " DP_RES_POL ,Polarity of the selected datapath routed reset" "Not inverted,Inverted" bitfld.byte 0x00 4. " GUDB_WR ,Global write operation for the configuration and working registers UDB" "Disabled,Enabled" bitfld.byte 0x00 3. " EN_RES_CNTCTL ,Routed reset to the counter/control register" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " RES_POL ,Polarity of the routed reset" "NEGATED,ASSERTED" bitfld.byte 0x00 0.--1. " RES_SEL ,RC routing input for the compatible reset scheme" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x01 "CFG31,Reset Control" bitfld.byte 0x01 7. " PLD1_RES_POL ,Polarity of the routed reset for both plds" "Not inverted,Inverted" bitfld.byte 0x01 6. " PLD0_RES_POL ,Polarity of the routed reset for both plds" "Not inverted,Inverted" bitfld.byte 0x01 4.--5. " EXT_CK_SEL ,External clock selection" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" rbitfld.byte 0x01 3. " EN_RES_DP ,Routed reset to the datapath block" "Disabled,Enabled" textline " " rbitfld.byte 0x01 2. " EN_RES_STAT ,Routed reset to the status register" "NEGATED,ASSERTED" bitfld.byte 0x01 1. " EXT_SYNC ,Synchronization of selected external clock" "Disabled,Enabled" bitfld.byte 0x01 0. " ALT_RES ,Toggles between two reset configurations" "COMPATIBLE,ALTERNATE" endif group.word 0x60++0x01 line.word 0x00 "DCFG0,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x62++0x01 line.word 0x00 "DCFG1,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x64++0x01 line.word 0x00 "DCFG2,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x66++0x01 line.word 0x00 "DCFG3,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x68++0x01 line.word 0x00 "DCFG4,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x6A++0x01 line.word 0x00 "DCFG5,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x6C++0x01 line.word 0x00 "DCFG6,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x6E++0x01 line.word 0x00 "DCFG7,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" width 0x0B tree.end tree "UDB P2 U0" base ad:0x400F3400 width 22. group.long 0x0++0x03 line.long 0x00 "PLD_IT0,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT0T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT0T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT0T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT0T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT0T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT0T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT0T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT0T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT0T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT0T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT0T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT0T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT0T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT0T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT0T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT0T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT0C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT0C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT0C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT0C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT0C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT0C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT0C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT0C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT0C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT0C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT0C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT0C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT0C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT0C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT0C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT0C_0 ,PLD0 complement input term 0" "0,1" group.long 0x4++0x03 line.long 0x00 "PLD_IT1,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT1T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT1T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT1T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT1T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT1T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT1T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT1T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT1T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT1T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT1T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT1T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT1T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT1T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT1T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT1T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT1T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT1C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT1C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT1C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT1C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT1C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT1C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT1C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT1C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT1C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT1C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT1C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT1C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT1C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT1C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT1C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT1C_0 ,PLD0 complement input term 0" "0,1" group.long 0x8++0x03 line.long 0x00 "PLD_IT2,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT2T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT2T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT2T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT2T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT2T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT2T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT2T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT2T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT2T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT2T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT2T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT2T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT2T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT2T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT2T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT2T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT2C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT2C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT2C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT2C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT2C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT2C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT2C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT2C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT2C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT2C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT2C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT2C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT2C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT2C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT2C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT2C_0 ,PLD0 complement input term 0" "0,1" group.long 0xC++0x03 line.long 0x00 "PLD_IT3,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT3T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT3T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT3T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT3T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT3T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT3T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT3T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT3T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT3T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT3T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT3T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT3T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT3T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT3T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT3T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT3T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT3C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT3C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT3C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT3C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT3C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT3C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT3C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT3C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT3C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT3C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT3C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT3C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT3C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT3C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT3C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT3C_0 ,PLD0 complement input term 0" "0,1" group.long 0x10++0x03 line.long 0x00 "PLD_IT4,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT4T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT4T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT4T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT4T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT4T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT4T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT4T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT4T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT4T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT4T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT4T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT4T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT4T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT4T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT4T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT4T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT4C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT4C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT4C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT4C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT4C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT4C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT4C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT4C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT4C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT4C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT4C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT4C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT4C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT4C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT4C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT4C_0 ,PLD0 complement input term 0" "0,1" group.long 0x14++0x03 line.long 0x00 "PLD_IT5,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT5T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT5T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT5T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT5T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT5T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT5T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT5T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT5T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT5T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT5T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT5T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT5T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT5T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT5T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT5T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT5T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT5C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT5C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT5C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT5C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT5C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT5C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT5C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT5C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT5C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT5C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT5C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT5C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT5C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT5C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT5C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT5C_0 ,PLD0 complement input term 0" "0,1" group.long 0x18++0x03 line.long 0x00 "PLD_IT6,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT6T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT6T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT6T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT6T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT6T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT6T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT6T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT6T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT6T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT6T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT6T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT6T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT6T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT6T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT6T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT6T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT6C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT6C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT6C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT6C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT6C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT6C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT6C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT6C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT6C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT6C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT6C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT6C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT6C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT6C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT6C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT6C_0 ,PLD0 complement input term 0" "0,1" group.long 0x1C++0x03 line.long 0x00 "PLD_IT7,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT7T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT7T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT7T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT7T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT7T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT7T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT7T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT7T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT7T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT7T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT7T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT7T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT7T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT7T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT7T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT7T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT7C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT7C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT7C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT7C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT7C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT7C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT7C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT7C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT7C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT7C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT7C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT7C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT7C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT7C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT7C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT7C_0 ,PLD0 complement input term 0" "0,1" group.long 0x20++0x03 line.long 0x00 "PLD_IT8,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT8T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT8T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT8T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT8T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT8T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT8T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT8T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT8T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT8T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT8T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT8T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT8T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT8T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT8T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT8T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT8T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT8C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT8C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT8C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT8C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT8C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT8C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT8C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT8C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT8C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT8C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT8C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT8C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT8C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT8C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT8C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT8C_0 ,PLD0 complement input term 0" "0,1" group.long 0x24++0x03 line.long 0x00 "PLD_IT9,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT9T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT9T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT9T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT9T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT9T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT9T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT9T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT9T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT9T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT9T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT9T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT9T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT9T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT9T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT9T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT9T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT9C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT9C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT9C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT9C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT9C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT9C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT9C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT9C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT9C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT9C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT9C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT9C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT9C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT9C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT9C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT9C_0 ,PLD0 complement input term 0" "0,1" group.long 0x28++0x03 line.long 0x00 "PLD_IT10,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT10T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT10T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT10T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT10T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT10T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT10T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT10T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT10T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT10T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT10T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT10T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT10T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT10T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT10T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT10T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT10T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT10C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT10C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT10C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT10C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT10C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT10C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT10C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT10C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT10C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT10C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT10C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT10C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT10C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT10C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT10C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT10C_0 ,PLD0 complement input term 0" "0,1" group.long 0x2C++0x03 line.long 0x00 "PLD_IT11,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT11T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT11T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT11T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT11T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT11T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT11T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT11T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT11T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT11T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT11T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT11T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT11T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT11T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT11T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT11T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT11T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT11C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT11C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT11C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT11C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT11C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT11C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT11C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT11C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT11C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT11C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT11C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT11C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT11C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT11C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT11C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT11C_0 ,PLD0 complement input term 0" "0,1" group.word 0x30++0x01 line.word 0x00 "PLD_ORT0,PLD OR Terms" bitfld.word 0x00 15. " PLD1_ORT_PT0_7 ,PLD1 OR term 7" "0,1" bitfld.word 0x00 14. " PLD1_ORT_PT0_6 ,PLD1 OR term 6" "0,1" bitfld.word 0x00 13. " PLD1_ORT_PT0_5 ,PLD1 OR term 5" "0,1" bitfld.word 0x00 12. " PLD1_ORT_PT0_4 ,PLD1 OR term 4" "0,1" textline " " bitfld.word 0x00 11. " PLD1_ORT_PT0_3 ,PLD1 OR term 3" "0,1" bitfld.word 0x00 10. " PLD1_ORT_PT0_2 ,PLD1 OR term 2" "0,1" bitfld.word 0x00 9. " PLD1_ORT_PT0_1 ,PLD1 OR term 1" "0,1" bitfld.word 0x00 8. " PLD1_ORT_PT0_0 ,PLD1 OR term 0" "0,1" textline " " bitfld.word 0x00 7. " PLD0_ORT_PT0_7 ,PLD0 OR term 7" "0,1" bitfld.word 0x00 6. " PLD0_ORT_PT0_6 ,PLD0 OR term 6" "0,1" bitfld.word 0x00 5. " PLD0_ORT_PT0_5 ,PLD0 OR term 5" "0,1" bitfld.word 0x00 4. " PLD0_ORT_PT0_4 ,PLD0 OR term 4" "0,1" textline " " bitfld.word 0x00 3. " PLD0_ORT_PT0_3 ,PLD0 OR term 3" "0,1" bitfld.word 0x00 2. " PLD0_ORT_PT0_2 ,PLD0 OR term 2" "0,1" bitfld.word 0x00 1. " PLD0_ORT_PT0_1 ,PLD0 OR term 1" "0,1" bitfld.word 0x00 0. " PLD0_ORT_PT0_0 ,PLD0 OR term 0" "0,1" group.word 0x32++0x01 line.word 0x00 "PLD_ORT1,PLD OR Terms" bitfld.word 0x00 15. " PLD1_ORT_PT1_7 ,PLD1 OR term 7" "0,1" bitfld.word 0x00 14. " PLD1_ORT_PT1_6 ,PLD1 OR term 6" "0,1" bitfld.word 0x00 13. " PLD1_ORT_PT1_5 ,PLD1 OR term 5" "0,1" bitfld.word 0x00 12. " PLD1_ORT_PT1_4 ,PLD1 OR term 4" "0,1" textline " " bitfld.word 0x00 11. " PLD1_ORT_PT1_3 ,PLD1 OR term 3" "0,1" bitfld.word 0x00 10. " PLD1_ORT_PT1_2 ,PLD1 OR term 2" "0,1" bitfld.word 0x00 9. " PLD1_ORT_PT1_1 ,PLD1 OR term 1" "0,1" bitfld.word 0x00 8. " PLD1_ORT_PT1_0 ,PLD1 OR term 0" "0,1" textline " " bitfld.word 0x00 7. " PLD0_ORT_PT1_7 ,PLD0 OR term 7" "0,1" bitfld.word 0x00 6. " PLD0_ORT_PT1_6 ,PLD0 OR term 6" "0,1" bitfld.word 0x00 5. " PLD0_ORT_PT1_5 ,PLD0 OR term 5" "0,1" bitfld.word 0x00 4. " PLD0_ORT_PT1_4 ,PLD0 OR term 4" "0,1" textline " " bitfld.word 0x00 3. " PLD0_ORT_PT1_3 ,PLD0 OR term 3" "0,1" bitfld.word 0x00 2. " PLD0_ORT_PT1_2 ,PLD0 OR term 2" "0,1" bitfld.word 0x00 1. " PLD0_ORT_PT1_1 ,PLD0 OR term 1" "0,1" bitfld.word 0x00 0. " PLD0_ORT_PT1_0 ,PLD0 OR term 0" "0,1" group.word 0x34++0x01 line.word 0x00 "PLD_ORT2,PLD OR Terms" bitfld.word 0x00 15. " PLD1_ORT_PT2_7 ,PLD1 OR term 7" "0,1" bitfld.word 0x00 14. " PLD1_ORT_PT2_6 ,PLD1 OR term 6" "0,1" bitfld.word 0x00 13. " PLD1_ORT_PT2_5 ,PLD1 OR term 5" "0,1" bitfld.word 0x00 12. " PLD1_ORT_PT2_4 ,PLD1 OR term 4" "0,1" textline " " bitfld.word 0x00 11. " PLD1_ORT_PT2_3 ,PLD1 OR term 3" "0,1" bitfld.word 0x00 10. " PLD1_ORT_PT2_2 ,PLD1 OR term 2" "0,1" bitfld.word 0x00 9. " PLD1_ORT_PT2_1 ,PLD1 OR term 1" "0,1" bitfld.word 0x00 8. " PLD1_ORT_PT2_0 ,PLD1 OR term 0" "0,1" textline " " bitfld.word 0x00 7. " PLD0_ORT_PT2_7 ,PLD0 OR term 7" "0,1" bitfld.word 0x00 6. " PLD0_ORT_PT2_6 ,PLD0 OR term 6" "0,1" bitfld.word 0x00 5. " PLD0_ORT_PT2_5 ,PLD0 OR term 5" "0,1" bitfld.word 0x00 4. " PLD0_ORT_PT2_4 ,PLD0 OR term 4" "0,1" textline " " bitfld.word 0x00 3. " PLD0_ORT_PT2_3 ,PLD0 OR term 3" "0,1" bitfld.word 0x00 2. " PLD0_ORT_PT2_2 ,PLD0 OR term 2" "0,1" bitfld.word 0x00 1. " PLD0_ORT_PT2_1 ,PLD0 OR term 1" "0,1" bitfld.word 0x00 0. " PLD0_ORT_PT2_0 ,PLD0 OR term 0" "0,1" group.word 0x36++0x01 line.word 0x00 "PLD_ORT3,PLD OR Terms" bitfld.word 0x00 15. " PLD1_ORT_PT3_7 ,PLD1 OR term 7" "0,1" bitfld.word 0x00 14. " PLD1_ORT_PT3_6 ,PLD1 OR term 6" "0,1" bitfld.word 0x00 13. " PLD1_ORT_PT3_5 ,PLD1 OR term 5" "0,1" bitfld.word 0x00 12. " PLD1_ORT_PT3_4 ,PLD1 OR term 4" "0,1" textline " " bitfld.word 0x00 11. " PLD1_ORT_PT3_3 ,PLD1 OR term 3" "0,1" bitfld.word 0x00 10. " PLD1_ORT_PT3_2 ,PLD1 OR term 2" "0,1" bitfld.word 0x00 9. " PLD1_ORT_PT3_1 ,PLD1 OR term 1" "0,1" bitfld.word 0x00 8. " PLD1_ORT_PT3_0 ,PLD1 OR term 0" "0,1" textline " " bitfld.word 0x00 7. " PLD0_ORT_PT3_7 ,PLD0 OR term 7" "0,1" bitfld.word 0x00 6. " PLD0_ORT_PT3_6 ,PLD0 OR term 6" "0,1" bitfld.word 0x00 5. " PLD0_ORT_PT3_5 ,PLD0 OR term 5" "0,1" bitfld.word 0x00 4. " PLD0_ORT_PT3_4 ,PLD0 OR term 4" "0,1" textline " " bitfld.word 0x00 3. " PLD0_ORT_PT3_3 ,PLD0 OR term 3" "0,1" bitfld.word 0x00 2. " PLD0_ORT_PT3_2 ,PLD0 OR term 2" "0,1" bitfld.word 0x00 1. " PLD0_ORT_PT3_1 ,PLD0 OR term 1" "0,1" bitfld.word 0x00 0. " PLD0_ORT_PT3_0 ,PLD0 OR term 0" "0,1" group.word 0x38++0x07 line.word 0x00 "PLD_MC_CFG_CEN_CONST,Macrocell Configuration For Carry Enable And Constant" bitfld.word 0x00 15. " PLD1_MC3_DFF_C ,PLD1 MC3 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 14. " PLD1_MC3_CEN ,PLD1 MC3 carry enable" "Disabled,Enabled" bitfld.word 0x00 13. " PLD1_MC2_DFF_C ,PLD1 MC2 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 12. " PLD1_MC2_CEN ,PLD1 MC2 carry enable" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " PLD1_MC1_DFF_C ,PLD1 MC1 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 10. " PLD1_MC1_CEN ,PLD1 MC1 carry enable" "Disabled,Enabled" bitfld.word 0x00 9. " PLD1_MC0_DFF_C ,PLD1 MC0 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 8. " PLD1_MC0_CEN ,PLD1 MC0 carry enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " PLD0_MC3_DFF_C ,PLD0 MC3 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 6. " PLD0_MC3_CEN ,PLD0 MC3 carry enable" "Disabled,Enabled" bitfld.word 0x00 5. " PLD0_MC2_DFF_C ,PLD0 MC2 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 4. " PLD0_MC2_CEN ,PLD0 MC2 carry enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " PLD0_MC1_DFF_C ,PLD0 MC1 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 2. " PLD0_MC1_CEN ,PLD0 MC1 carry enable" "Disabled,Enabled" bitfld.word 0x00 1. " PLD0_MC0_DFF_C ,PLD0 MC0 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 0. " PLD0_MC0_CEN ,PLD0_MC0 carry enable" "Disabled,Enabled" line.word 0x02 "PLD_MC_CFG_XORFB,PLD Macro Cell XOR Feedback" bitfld.word 0x02 14.--15. " PLD1_MC3_XORFB ,PLD1 MC3 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" bitfld.word 0x02 12.--13. " PLD1_MC2_XORFB ,PLD1 MC2 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" bitfld.word 0x02 10.--11. " PLD1_MC1_XORFB ,PLD1 MC1 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" bitfld.word 0x02 8.--9. " PLD1_MC0_XORFB ,PLD1 MC0 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" textline " " bitfld.word 0x02 6.--7. " PLD0_MC3_XORFB ,PLD0 MC3 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" bitfld.word 0x02 4.--5. " PLD0_MC2_XORFB ,PLD0 MC2 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" bitfld.word 0x02 2.--3. " PLD0_MC1_XORFB ,PLD0 MC1 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" bitfld.word 0x02 0.--1. " PLD0_MC0_XORFB ,PLD0 MC0 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" line.word 0x04 "PLD_MC_SET_RESET,PLD Macro Cell Set Reset Selection" bitfld.word 0x04 15. " PLD1_MC3_RESET_SEL ,PLD1 MC3 reset select enable" "Disabled,Enabled" bitfld.word 0x04 14. " PLD1_MC3_SET_SEL ,PLD1 MC3 set select enable" "Disabled,Enabled" bitfld.word 0x04 13. " PLD1_MC2_RESET_SEL ,PLD1 MC2 reset select enable" "Disabled,Enabled" bitfld.word 0x04 12. " PLD1_MC2_SET_SEL ,PLD1 MC2 set select enable" "Disabled,Enabled" textline " " bitfld.word 0x04 11. " PLD1_MC1_RESET_SEL ,PLD1 MC1 reset select enable" "Disabled,Enabled" bitfld.word 0x04 10. " PLD1_MC1_SET_SEL ,PLD1 MC0 set select enable" "Disabled,Enabled" bitfld.word 0x04 9. " PLD1_MC0_RESET_SEL ,PLD1 MC0 reset select enable" "Disabled,Enabled" bitfld.word 0x04 8. " PLD1_MC0_SET_SEL ,PLD1 MC0 set select enable" "Disabled,Enabled" textline " " bitfld.word 0x04 7. " PLD0_MC3_RESET_SEL ,PLD0 MC3 reset select enable" "Disabled,Enabled" bitfld.word 0x04 6. " PLD0_MC3_SET_SEL ,PLD0 MC3 set select enable" "Disabled,Enabled" bitfld.word 0x04 5. " PLD0_MC2_RESET_SEL ,PLD0 MC2 reset select enable" "Disabled,Enabled" bitfld.word 0x04 4. " PLD0_MC2_SET_SEL ,PLD0 MC2 set select enable" "Disabled,Enabled" textline " " bitfld.word 0x04 3. " PLD0_MC1_RESET_SEL ,PLD0 MC1 reset select enable" "Disabled,Enabled" bitfld.word 0x04 2. " PLD0_MC1_SET_SEL ,PLD0 MC1 set select enable" "Disabled,Enabled" bitfld.word 0x04 1. " PLD0_MC0_RESET_SEL ,Reset select enable" "Disabled,Enabled" bitfld.word 0x04 0. " PLD0_MC0_SET_SEL ,PLD0 MC0 set select enable" "Disabled,Enabled" line.word 0x06 "PLD_MC_CFG_BYPASS,PLD Macro Cell Bypass Control" bitfld.word 0x06 15. " NC15 ,Spare register bit NC15" "0,1" bitfld.word 0x06 14. " PLD1_MC3_BYPASS ,PLD1 MC3 bypass selection" "REGISTER,COMBINATIONAL" bitfld.word 0x06 13. " NC13 ,Spare register bit NC13" "0,1" bitfld.word 0x06 12. " PLD1_MC2_BYPASS ,PLD1 MC2 bypass selection" "REGISTER,COMBINATIONAL" textline " " bitfld.word 0x06 11. " NC11 ,Spare register bit NC11" "0,1" bitfld.word 0x06 10. " PLD1_MC1_BYPASS ,PLD1 MC1 bypass selection" "REGISTER,COMBINATIONAL" bitfld.word 0x06 9. " NC9 ,Spare register bit NC9" "0,1" bitfld.word 0x06 8. " PLD1_MC0_BYPASS ,PLD1 MC0 bypass selection" "REGISTER,COMBINATIONAL" textline " " bitfld.word 0x06 7. " NC7 ,Spare register bit NC7" "0,1" bitfld.word 0x06 6. " PLD0_MC3_BYPASS ,PLD0 MC3 bypass selection" "REGISTER,COMBINATIONAL" bitfld.word 0x06 5. " NC5 ,Spare register bit NC5" "0,1" bitfld.word 0x06 4. " PLD0_MC2_BYPASS ,PLD0 MC2 bypass selection" "REGISTER,COMBINATIONAL" textline " " bitfld.word 0x06 3. " NC3 ,Spare register bit NC3" "0,1" bitfld.word 0x06 2. " PLD0_MC1_BYPASS ,PLD0 MC1 bypass selection" "REGISTER,COMBINATIONAL" bitfld.word 0x06 1. " NC1 ,Spare register bit NC1" "0,1" bitfld.word 0x06 0. " PLD0_MC0_BYPASS ,PLD0 MC0 bypass selection" "REGISTER,COMBINATIONAL" group.byte 0x40++0x17 line.byte 0x00 "CFG0,Datapath Input Selection - RAD1 RAD0. Address Bits 0 And 1 To The Dynamic Configuration RAM" bitfld.byte 0x00 4.--6. " RAD1 ,Datapath permutable input mux RAD1" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." bitfld.byte 0x00 0.--2. " RAD0 ,Datapath permutable input mux RAD0" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." line.byte 0x01 "CFG1,Datapath Input Selection - RAD2. Address Bit 2 To The Dynamic Configuration RAM" bitfld.byte 0x01 7. " DP_RTE_BYPASS4 ,Dp_in bypass control 4" "DP_IN4_ROUTE,DP_IN4_BYPASS" bitfld.byte 0x01 6. " DP_RTE_BYPASS3 ,Dp_in bypass control 3" "DP_IN3_ROUTE,DP_IN3_BYPASS" bitfld.byte 0x01 5. " DP_RTE_BYPASS2 ,Dp_in bypass control 2" "DP_IN2_ROUTE,DP_IN2_BYPASS" bitfld.byte 0x01 4. " DP_RTE_BYPASS1 ,Dp_in bypass control 1" "DP_IN1_ROUTE,DP_IN1_BYPASS" textline " " bitfld.byte 0x01 3. " DP_RTE_BYPASS0 ,Dp_in bypass control 0" "DP_IN0_ROUTE,DP_IN0_BYPASS" bitfld.byte 0x01 0.--2. " RAD2 ,Datapath permutable input mux 2" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." line.byte 0x02 "CFG2,Datapath Input Selection - F1_LD, F0_LD" bitfld.byte 0x02 7. " NC7 ,Spare register bit NC7" "0,1" bitfld.byte 0x02 4.--6. " F1_LD ,Datapath permutable input mux F1_LD" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." bitfld.byte 0x02 3. " DP_RTE_BYPASS5 ,Dp_in bypass control 5" "DP_IN5_ROUTE,DP_IN5_BYPASS" bitfld.byte 0x02 0.--2. " F0_LD ,Datapath permutable input mux F0_LD" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." line.byte 0x03 "CFG3,Datapath Input Selection - D1_LD, D0_LD" bitfld.byte 0x03 4.--6. " D1_LD ,Datapath permutable input mux D1_LD" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." bitfld.byte 0x03 0.--2. " D0_LD ,Datapath permutable input mux D0_LD" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." line.byte 0x04 "CFG4,Datapath Input Selection - CI_MUX SI_MUX" bitfld.byte 0x04 4.--6. " CI_MUX ,Datapath permutable input mux CI_MUX" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." bitfld.byte 0x04 0.--2. " SI_MUX ,Datapath permutable input mux SI_MUX" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." line.byte 0x05 "CFG5,Datapath Output Selection For OUT1 OUT0" bitfld.byte 0x05 4.--7. " OUT1 ,Datapath permutable output mux OUT1" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT" bitfld.byte 0x05 0.--3. " OUT0 ,Datapath permutable output mux OUT0" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT" line.byte 0x06 "CFG6,Datapath Output Selection For OUT3 OUT2" bitfld.byte 0x06 4.--7. " OUT3 ,Datapath permutable output mux OUT3" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT" bitfld.byte 0x06 0.--3. " OUT2 ,Datapath permutable output mux OUT2" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT" line.byte 0x07 "CFG7,Datapath Output Selection For OUT5 OUT4" bitfld.byte 0x07 4.--7. " OUT5 ,Datapath permutable output mux OUT5" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT" bitfld.byte 0x07 0.--3. " OUT4 ,Datapath permutable output mux OUT4" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT" line.byte 0x08 "CFG8,Datapath Output Synchronization Option" bitfld.byte 0x08 7. " NC7 ,Spare register bit NC7" "0,1" bitfld.byte 0x08 6. " NC6 ,Spare register bit NC6" "0,1" bitfld.byte 0x08 0.--5. " OUT_SYNC ,Datapath output synchronization" "REGISTERED,COMBINATIONAL,?..." line.byte 0x09 "CFG9,Datapath ALU Mask" line.byte 0x0A "CFG10,Datapath Compare 0 Mask" line.byte 0x0B "CFG11,Datapath Compare 1 Mask" line.byte 0x0C "CFG12,Datapath Mask Enables And Shift In Configuration" bitfld.byte 0x0C 7. " CMASK1_EN ,Datapath mask CMASK1 enable" "Disabled,Enabled" bitfld.byte 0x0C 6. " CMASK0_EN ,Datapath mask CMASK0 enable" "Disabled,Enabled" bitfld.byte 0x0C 5. " AMASK_EN ,Datapath mask AMASK enable" "Disabled,Enabled" bitfld.byte 0x0C 4. " DEF_SI ,Datapath default shift value" "DEFAULT_0,DEFAULT_1" textline " " bitfld.byte 0x0C 2.--3. " SI_SELB ,Datapath shift in source select" "DEFAULT,REGISTERED,ROUTE,CHAIN" bitfld.byte 0x0C 0.--1. " SI_SELA ,Datapath shift in source select" "DEFAULT,REGISTERED,ROUTE,CHAIN" line.byte 0x0D "CFG13,Datapath Carry In And Compare Configuration" bitfld.byte 0x0D 6.--7. " CMP_SELB ,Datapath compare select B" "A1_D1,A1_A0,A0_D1,A0_A0" bitfld.byte 0x0D 4.--5. " CMP_SELA ,Datapath compare select A" "A1_D1,A1_A0,A0_D1,A0_A0" bitfld.byte 0x0D 2.--3. " CI_SELB ,Datapath carry in source select B" "DEFAULT,REGISTERED,ROUTE,CHAIN" bitfld.byte 0x0D 0.--1. " CI_SELA ,Datapath carry in source select A" "DEFAULT,REGISTERED,ROUTE,CHAIN" line.byte 0x0E "CFG14,Datapath Chaining And MSB Configuration" bitfld.byte 0x0E 7. " MSB_EN ,Datapath MSB selection enable" "Disabled,Enabled" bitfld.byte 0x0E 4.--6. " MSB_SEL ,Datapath MSB selection" "BIT0,BIT1,BIT2,BIT3,BIT4,BIT5,BIT6,BIT7" bitfld.byte 0x0E 3. " CHAIN_CMSB ,Datapath CRC MSB chaining enable" "Disabled,Enabled" bitfld.byte 0x0E 2. " CHAIN_FB ,Datapath CRC feedback chaining enable" "Disabled,Enabled" textline " " bitfld.byte 0x0E 1. " CHAIN1 ,Datapath condition chaining enable 1" "Disabled,Enabled" bitfld.byte 0x0E 0. " CHAIN0 ,Datapath condition chaining enable 0" "Disabled,Enabled" line.byte 0x0F "CFG15,Datapath FIFO, Shift And Parallel Input Control" bitfld.byte 0x0F 7. " PI_SEL ,Datapath parallel input selection" "NORMAL,PARALLEL" bitfld.byte 0x0F 6. " SHIFT_SEL ,Datapath shift out selection" "SOL_MSB,SOR" bitfld.byte 0x0F 5. " PI_DYN ,Enable for dynamic control of parallel data input (Pi) mux" "Disabled,Enabled" bitfld.byte 0x0F 4. " MSB_SI ,Arithmetic shift right operation shift in selection" "DEFAULT,MSB" textline " " bitfld.byte 0x0F 2.--3. " F1_INSEL ,Datapath FIFO configuration 1" "INPUT,OUTPUT_A0,OUTPUT_A1,OUTPUT_ALU" bitfld.byte 0x0F 0.--1. " F0_INSEL ,Datapath FIFO configuration 0" "INPUT,OUTPUT_A0,OUTPUT_A1,OUTPUT_ALU" line.byte 0x10 "CFG16,Datapath FIFO And Register Access Configuration Control" bitfld.byte 0x10 7. " F1_CK_INV ,FIFO 1 clock Inverted" "NORMAL,Inverted" bitfld.byte 0x10 6. " F0_CK_INV ,FIFO 0 clock Inverted" "NORMAL,Inverted" bitfld.byte 0x10 5. " FIFO_FAST ,FIFO fast mode" "Disabled,Enabled" bitfld.byte 0x10 4. " FIFO_CAP ,FIFO software capture mode" "Disabled,Enabled" textline " " bitfld.byte 0x10 3. " FIFO_EDGE ,Edge/level sensitive FIFO write control (Fx_ld)" "LEVEL,EDGE" bitfld.byte 0x10 2. " FIFO_ASYNC ,Asynchronous FIFO clocking support" "Disabled,Enabled" bitfld.byte 0x10 1. " EXT_CRCPRS ,External CRC/PRS mode" "INTERNAL,EXTERNAL" bitfld.byte 0x10 0. " WRK16_CONCAT ,Datapath register access mode" "DEFAULT,CONCATENATE" line.byte 0x11 "CFG17,Datapath FIFO Control" bitfld.byte 0x11 4. " FIFO_ADD_SYNC ,Sync flip-flop to FIFO block status" "Disabled,Enabled" bitfld.byte 0x11 3. " NC3 ,Spare register bit NC3" "0,1" bitfld.byte 0x11 2. " NC2 ,Spare register bit NC2" "0,1" bitfld.byte 0x11 1. " F1_DYN ,FIFO 1 direction" "STATIC,DYNAMIC" textline " " bitfld.byte 0x11 0. " F0_DYN ,FIFO 0 direction" "STATIC,DYNAMIC" line.byte 0x12 "CFG18,Control Register Mode 0" line.byte 0x13 "CFG19,Control Register Mode 1" line.byte 0x14 "CFG20,Status Register Input Mode Selection" bitfld.byte 0x14 7. " STAT_MD[7] ,Bit 7 status input mode select" "Transparent,Sticky cleared" bitfld.byte 0x14 6. " [6] ,Bit 6 status input mode select" "Transparent,Sticky cleared" bitfld.byte 0x14 5. " [5] ,Bit 5 status input mode select" "Transparent,Sticky cleared" bitfld.byte 0x14 4. " [4] ,Bit 4 status input mode select" "Transparent,Sticky cleared" textline " " bitfld.byte 0x14 3. " [3] ,Bit 3 status input mode select" "Transparent,Sticky cleared" bitfld.byte 0x14 2. " [2] ,Bit 2 status input mode select" "Transparent,Sticky cleared" bitfld.byte 0x14 1. " [1] ,Bit 1 status input mode select" "Transparent,Sticky cleared" bitfld.byte 0x14 0. " [0] ,Bit 0 status input mode select" "Transparent,Sticky cleared" line.byte 0x15 "CFG21,Spare Register Bits" bitfld.byte 0x15 1. " NC1 ,Spare register bit NC1" "0,1" bitfld.byte 0x15 0. " NC0 ,Spare register bit NC0" "0,1" line.byte 0x16 "CFG22,SC Block Configuration Control" bitfld.byte 0x16 4. " SC_EXT_RES ,Control register external reset operation" "Disabled,Enabled" bitfld.byte 0x16 3. " SC_SYNC_MD ,SC sync mode" "NORMAL,SYNC_MODE" bitfld.byte 0x16 2. " SC_INT_MD ,SC interrupt mode" "NORMAL,INT_MODE" bitfld.byte 0x16 0.--1. " SC_OUT_CTL ,Output source for the status and control routing connections" "CONTROL,PARALLEL,COUNTER,?..." line.byte 0x17 "CFG23,Counter Control" bitfld.byte 0x17 6. " ALT_CNT ,Alternate operating mode of the counter" "DEFAULT_MODE,ALT_MODE" bitfld.byte 0x17 5. " ROUTE_EN ,Counter enable signal for routing input" "Disabled,Enabled" bitfld.byte 0x17 4. " ROUTE_LD ,Counter load signal for routing input" "Disabled,Enabled" bitfld.byte 0x17 2.--3. " CNT_EN_SEL ,Routing inputs for the counter enable signal" "SC_IN4,SC_IN5,SC_IN6,SC_IO" textline " " bitfld.byte 0x17 0.--1. " CNT_LD_SEL ,Routing inputs for the counter load signal" "SC_IN0,SC_IN1,SC_IN2,SC_IN3" if (((per.b(ad:0x400F3400+0x5F))&0x01)==0x01) group.byte 0x58++0x03 line.byte 0x00 "CFG24,PLD0 Clock And Reset Control" bitfld.byte 0x00 6.--7. " RC_RES_SEL ,Routed reset for the associated UDB component block" "0,1,2,3" bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x00 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x00 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x00 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x01 "CFG25,PLD1 Clock And Reset Control" bitfld.byte 0x00 6.--7. " RC_RES_SEL ,Routed reset for the associated UDB component block" "0,1,2,3" bitfld.byte 0x01 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x01 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x01 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x01 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x02 "CFG26,Datapath Clock And Reset Control" bitfld.byte 0x00 6.--7. " RC_RES_SEL ,Routed reset for the associated UDB component block" "0,1,2,3" bitfld.byte 0x02 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x02 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x02 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x02 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x03 "CFG27,Status/control Clock And Reset Control" bitfld.byte 0x00 6.--7. " RC_RES_SEL ,Routed reset for the associated UDB component block" "0,1,2,3" bitfld.byte 0x03 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x03 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x03 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x03 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" else group.byte 0x58++0x03 line.byte 0x00 "CFG24,PLD0 Clock And Reset Control" bitfld.byte 0x00 6. " FRES ,Firmware reset for the associated UDB component block" "No reset,Reset" bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x00 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x00 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x00 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x01 "CFG25,PLD1 Clock And Reset Control" bitfld.byte 0x00 6. " FRES ,Firmware reset for the associated UDB component block" "No reset,Reset" bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x00 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x00 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x00 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x02 "CFG26,Datapath Clock And Reset Control" bitfld.byte 0x00 6. " FRES ,Firmware reset for the associated UDB component block" "No reset,Reset" bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x00 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x00 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x00 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x03 "CFG27,Status/control Clock And Reset Control" rbitfld.byte 0x00 6. " FRES ,Firmware reset for the associated UDB component block" "No reset,Reset" bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x03 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x03 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x03 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" endif group.byte 0x5C++0x01 line.byte 0x00 "CFG28,Clock Selection For PLD1 And PLD0" bitfld.byte 0x00 4.--7. " PLD1_CK_SEL ,PLD1 clock selection registers" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,EXT_CLK,SYSCLK,?..." bitfld.byte 0x00 0.--3. " PLD0_CK_SEL ,PLD0 clock selection registers" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,EXT_CLK,SYSCLK,?..." line.byte 0x01 "CFG29,Clock Selection For Datapath, Status And Control" bitfld.byte 0x01 4.--7. " SC_CK_SEL ,SC clock selection registers" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,EXT_CLK,SYSCLK,?..." bitfld.byte 0x01 0.--3. " DP_CK_SEL ,DP clock selection registers" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,EXT_CLK,SYSCLK,?..." if (((per.b(ad:0x400F3400+0x5F))&0x01)==0x01) group.byte 0x5E++0x01 line.byte 0x00 "CFG30,Reset Control" bitfld.byte 0x00 7. " SC_RES_POL ,Polarity of the selected SC routed reset" "Not inverted,Inverted" bitfld.byte 0x00 6. " DP_RES_POL ,Polarity of the selected datapath routed reset" "Not inverted,Inverted" bitfld.byte 0x00 4. " GUDB_WR ,Global write operation for the configuration and working registers UDB" "Disabled,Enabled" bitfld.byte 0x00 3. " EN_RES_CNTCTL ,Routed reset to the counter/control register" "Disabled,Enabled" textline " " rbitfld.byte 0x00 2. " RES_POL ,Polarity of the routed reset" "NEGATED,ASSERTED" rbitfld.byte 0x00 0.--1. " RES_SEL ,RC routing input for the compatible reset scheme" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x01 "CFG31,Reset Control" bitfld.byte 0x01 7. " PLD1_RES_POL ,Polarity of the routed reset for both plds" "Not inverted,Inverted" bitfld.byte 0x01 6. " PLD0_RES_POL ,Polarity of the routed reset for both plds" "Not inverted,Inverted" bitfld.byte 0x01 4.--5. " EXT_CK_SEL ,External clock selection" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" bitfld.byte 0x01 3. " EN_RES_DP ,Routed reset to the datapath block" "Disabled,Enabled" textline " " bitfld.byte 0x01 2. " EN_RES_STAT ,Routed reset to the status register" "NEGATED,ASSERTED" bitfld.byte 0x01 1. " EXT_SYNC ,Synchronization of selected external clock" "Disabled,Enabled" bitfld.byte 0x01 0. " ALT_RES ,Toggles between two reset configurations" "COMPATIBLE,ALTERNATE" else group.byte 0x5E++0x01 line.byte 0x00 "CFG30,Reset Control" rbitfld.byte 0x00 7. " SC_RES_POL ,Polarity of the selected SC routed reset" "Not inverted,Inverted" rbitfld.byte 0x00 6. " DP_RES_POL ,Polarity of the selected datapath routed reset" "Not inverted,Inverted" bitfld.byte 0x00 4. " GUDB_WR ,Global write operation for the configuration and working registers UDB" "Disabled,Enabled" bitfld.byte 0x00 3. " EN_RES_CNTCTL ,Routed reset to the counter/control register" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " RES_POL ,Polarity of the routed reset" "NEGATED,ASSERTED" bitfld.byte 0x00 0.--1. " RES_SEL ,RC routing input for the compatible reset scheme" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x01 "CFG31,Reset Control" bitfld.byte 0x01 7. " PLD1_RES_POL ,Polarity of the routed reset for both plds" "Not inverted,Inverted" bitfld.byte 0x01 6. " PLD0_RES_POL ,Polarity of the routed reset for both plds" "Not inverted,Inverted" bitfld.byte 0x01 4.--5. " EXT_CK_SEL ,External clock selection" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" rbitfld.byte 0x01 3. " EN_RES_DP ,Routed reset to the datapath block" "Disabled,Enabled" textline " " rbitfld.byte 0x01 2. " EN_RES_STAT ,Routed reset to the status register" "NEGATED,ASSERTED" bitfld.byte 0x01 1. " EXT_SYNC ,Synchronization of selected external clock" "Disabled,Enabled" bitfld.byte 0x01 0. " ALT_RES ,Toggles between two reset configurations" "COMPATIBLE,ALTERNATE" endif group.word 0x60++0x01 line.word 0x00 "DCFG0,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x62++0x01 line.word 0x00 "DCFG1,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x64++0x01 line.word 0x00 "DCFG2,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x66++0x01 line.word 0x00 "DCFG3,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x68++0x01 line.word 0x00 "DCFG4,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x6A++0x01 line.word 0x00 "DCFG5,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x6C++0x01 line.word 0x00 "DCFG6,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x6E++0x01 line.word 0x00 "DCFG7,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" width 0x0B tree.end tree "UDB P2 U1" base ad:0x400F3480 width 22. group.long 0x0++0x03 line.long 0x00 "PLD_IT0,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT0T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT0T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT0T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT0T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT0T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT0T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT0T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT0T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT0T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT0T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT0T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT0T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT0T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT0T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT0T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT0T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT0C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT0C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT0C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT0C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT0C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT0C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT0C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT0C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT0C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT0C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT0C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT0C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT0C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT0C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT0C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT0C_0 ,PLD0 complement input term 0" "0,1" group.long 0x4++0x03 line.long 0x00 "PLD_IT1,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT1T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT1T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT1T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT1T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT1T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT1T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT1T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT1T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT1T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT1T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT1T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT1T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT1T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT1T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT1T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT1T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT1C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT1C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT1C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT1C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT1C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT1C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT1C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT1C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT1C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT1C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT1C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT1C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT1C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT1C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT1C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT1C_0 ,PLD0 complement input term 0" "0,1" group.long 0x8++0x03 line.long 0x00 "PLD_IT2,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT2T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT2T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT2T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT2T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT2T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT2T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT2T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT2T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT2T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT2T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT2T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT2T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT2T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT2T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT2T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT2T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT2C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT2C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT2C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT2C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT2C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT2C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT2C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT2C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT2C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT2C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT2C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT2C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT2C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT2C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT2C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT2C_0 ,PLD0 complement input term 0" "0,1" group.long 0xC++0x03 line.long 0x00 "PLD_IT3,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT3T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT3T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT3T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT3T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT3T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT3T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT3T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT3T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT3T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT3T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT3T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT3T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT3T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT3T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT3T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT3T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT3C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT3C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT3C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT3C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT3C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT3C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT3C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT3C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT3C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT3C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT3C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT3C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT3C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT3C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT3C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT3C_0 ,PLD0 complement input term 0" "0,1" group.long 0x10++0x03 line.long 0x00 "PLD_IT4,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT4T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT4T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT4T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT4T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT4T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT4T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT4T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT4T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT4T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT4T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT4T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT4T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT4T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT4T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT4T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT4T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT4C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT4C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT4C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT4C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT4C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT4C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT4C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT4C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT4C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT4C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT4C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT4C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT4C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT4C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT4C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT4C_0 ,PLD0 complement input term 0" "0,1" group.long 0x14++0x03 line.long 0x00 "PLD_IT5,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT5T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT5T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT5T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT5T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT5T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT5T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT5T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT5T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT5T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT5T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT5T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT5T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT5T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT5T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT5T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT5T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT5C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT5C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT5C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT5C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT5C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT5C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT5C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT5C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT5C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT5C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT5C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT5C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT5C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT5C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT5C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT5C_0 ,PLD0 complement input term 0" "0,1" group.long 0x18++0x03 line.long 0x00 "PLD_IT6,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT6T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT6T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT6T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT6T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT6T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT6T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT6T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT6T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT6T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT6T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT6T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT6T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT6T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT6T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT6T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT6T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT6C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT6C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT6C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT6C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT6C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT6C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT6C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT6C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT6C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT6C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT6C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT6C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT6C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT6C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT6C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT6C_0 ,PLD0 complement input term 0" "0,1" group.long 0x1C++0x03 line.long 0x00 "PLD_IT7,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT7T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT7T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT7T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT7T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT7T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT7T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT7T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT7T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT7T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT7T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT7T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT7T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT7T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT7T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT7T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT7T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT7C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT7C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT7C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT7C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT7C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT7C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT7C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT7C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT7C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT7C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT7C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT7C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT7C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT7C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT7C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT7C_0 ,PLD0 complement input term 0" "0,1" group.long 0x20++0x03 line.long 0x00 "PLD_IT8,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT8T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT8T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT8T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT8T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT8T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT8T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT8T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT8T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT8T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT8T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT8T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT8T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT8T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT8T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT8T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT8T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT8C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT8C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT8C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT8C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT8C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT8C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT8C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT8C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT8C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT8C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT8C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT8C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT8C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT8C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT8C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT8C_0 ,PLD0 complement input term 0" "0,1" group.long 0x24++0x03 line.long 0x00 "PLD_IT9,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT9T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT9T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT9T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT9T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT9T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT9T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT9T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT9T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT9T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT9T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT9T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT9T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT9T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT9T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT9T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT9T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT9C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT9C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT9C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT9C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT9C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT9C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT9C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT9C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT9C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT9C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT9C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT9C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT9C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT9C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT9C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT9C_0 ,PLD0 complement input term 0" "0,1" group.long 0x28++0x03 line.long 0x00 "PLD_IT10,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT10T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT10T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT10T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT10T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT10T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT10T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT10T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT10T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT10T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT10T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT10T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT10T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT10T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT10T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT10T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT10T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT10C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT10C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT10C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT10C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT10C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT10C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT10C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT10C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT10C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT10C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT10C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT10C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT10C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT10C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT10C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT10C_0 ,PLD0 complement input term 0" "0,1" group.long 0x2C++0x03 line.long 0x00 "PLD_IT11,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT11T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT11T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT11T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT11T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT11T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT11T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT11T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT11T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT11T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT11T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT11T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT11T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT11T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT11T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT11T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT11T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT11C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT11C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT11C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT11C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT11C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT11C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT11C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT11C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT11C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT11C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT11C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT11C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT11C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT11C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT11C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT11C_0 ,PLD0 complement input term 0" "0,1" group.word 0x30++0x01 line.word 0x00 "PLD_ORT0,PLD OR Terms" bitfld.word 0x00 15. " PLD1_ORT_PT0_7 ,PLD1 OR term 7" "0,1" bitfld.word 0x00 14. " PLD1_ORT_PT0_6 ,PLD1 OR term 6" "0,1" bitfld.word 0x00 13. " PLD1_ORT_PT0_5 ,PLD1 OR term 5" "0,1" bitfld.word 0x00 12. " PLD1_ORT_PT0_4 ,PLD1 OR term 4" "0,1" textline " " bitfld.word 0x00 11. " PLD1_ORT_PT0_3 ,PLD1 OR term 3" "0,1" bitfld.word 0x00 10. " PLD1_ORT_PT0_2 ,PLD1 OR term 2" "0,1" bitfld.word 0x00 9. " PLD1_ORT_PT0_1 ,PLD1 OR term 1" "0,1" bitfld.word 0x00 8. " PLD1_ORT_PT0_0 ,PLD1 OR term 0" "0,1" textline " " bitfld.word 0x00 7. " PLD0_ORT_PT0_7 ,PLD0 OR term 7" "0,1" bitfld.word 0x00 6. " PLD0_ORT_PT0_6 ,PLD0 OR term 6" "0,1" bitfld.word 0x00 5. " PLD0_ORT_PT0_5 ,PLD0 OR term 5" "0,1" bitfld.word 0x00 4. " PLD0_ORT_PT0_4 ,PLD0 OR term 4" "0,1" textline " " bitfld.word 0x00 3. " PLD0_ORT_PT0_3 ,PLD0 OR term 3" "0,1" bitfld.word 0x00 2. " PLD0_ORT_PT0_2 ,PLD0 OR term 2" "0,1" bitfld.word 0x00 1. " PLD0_ORT_PT0_1 ,PLD0 OR term 1" "0,1" bitfld.word 0x00 0. " PLD0_ORT_PT0_0 ,PLD0 OR term 0" "0,1" group.word 0x32++0x01 line.word 0x00 "PLD_ORT1,PLD OR Terms" bitfld.word 0x00 15. " PLD1_ORT_PT1_7 ,PLD1 OR term 7" "0,1" bitfld.word 0x00 14. " PLD1_ORT_PT1_6 ,PLD1 OR term 6" "0,1" bitfld.word 0x00 13. " PLD1_ORT_PT1_5 ,PLD1 OR term 5" "0,1" bitfld.word 0x00 12. " PLD1_ORT_PT1_4 ,PLD1 OR term 4" "0,1" textline " " bitfld.word 0x00 11. " PLD1_ORT_PT1_3 ,PLD1 OR term 3" "0,1" bitfld.word 0x00 10. " PLD1_ORT_PT1_2 ,PLD1 OR term 2" "0,1" bitfld.word 0x00 9. " PLD1_ORT_PT1_1 ,PLD1 OR term 1" "0,1" bitfld.word 0x00 8. " PLD1_ORT_PT1_0 ,PLD1 OR term 0" "0,1" textline " " bitfld.word 0x00 7. " PLD0_ORT_PT1_7 ,PLD0 OR term 7" "0,1" bitfld.word 0x00 6. " PLD0_ORT_PT1_6 ,PLD0 OR term 6" "0,1" bitfld.word 0x00 5. " PLD0_ORT_PT1_5 ,PLD0 OR term 5" "0,1" bitfld.word 0x00 4. " PLD0_ORT_PT1_4 ,PLD0 OR term 4" "0,1" textline " " bitfld.word 0x00 3. " PLD0_ORT_PT1_3 ,PLD0 OR term 3" "0,1" bitfld.word 0x00 2. " PLD0_ORT_PT1_2 ,PLD0 OR term 2" "0,1" bitfld.word 0x00 1. " PLD0_ORT_PT1_1 ,PLD0 OR term 1" "0,1" bitfld.word 0x00 0. " PLD0_ORT_PT1_0 ,PLD0 OR term 0" "0,1" group.word 0x34++0x01 line.word 0x00 "PLD_ORT2,PLD OR Terms" bitfld.word 0x00 15. " PLD1_ORT_PT2_7 ,PLD1 OR term 7" "0,1" bitfld.word 0x00 14. " PLD1_ORT_PT2_6 ,PLD1 OR term 6" "0,1" bitfld.word 0x00 13. " PLD1_ORT_PT2_5 ,PLD1 OR term 5" "0,1" bitfld.word 0x00 12. " PLD1_ORT_PT2_4 ,PLD1 OR term 4" "0,1" textline " " bitfld.word 0x00 11. " PLD1_ORT_PT2_3 ,PLD1 OR term 3" "0,1" bitfld.word 0x00 10. " PLD1_ORT_PT2_2 ,PLD1 OR term 2" "0,1" bitfld.word 0x00 9. " PLD1_ORT_PT2_1 ,PLD1 OR term 1" "0,1" bitfld.word 0x00 8. " PLD1_ORT_PT2_0 ,PLD1 OR term 0" "0,1" textline " " bitfld.word 0x00 7. " PLD0_ORT_PT2_7 ,PLD0 OR term 7" "0,1" bitfld.word 0x00 6. " PLD0_ORT_PT2_6 ,PLD0 OR term 6" "0,1" bitfld.word 0x00 5. " PLD0_ORT_PT2_5 ,PLD0 OR term 5" "0,1" bitfld.word 0x00 4. " PLD0_ORT_PT2_4 ,PLD0 OR term 4" "0,1" textline " " bitfld.word 0x00 3. " PLD0_ORT_PT2_3 ,PLD0 OR term 3" "0,1" bitfld.word 0x00 2. " PLD0_ORT_PT2_2 ,PLD0 OR term 2" "0,1" bitfld.word 0x00 1. " PLD0_ORT_PT2_1 ,PLD0 OR term 1" "0,1" bitfld.word 0x00 0. " PLD0_ORT_PT2_0 ,PLD0 OR term 0" "0,1" group.word 0x36++0x01 line.word 0x00 "PLD_ORT3,PLD OR Terms" bitfld.word 0x00 15. " PLD1_ORT_PT3_7 ,PLD1 OR term 7" "0,1" bitfld.word 0x00 14. " PLD1_ORT_PT3_6 ,PLD1 OR term 6" "0,1" bitfld.word 0x00 13. " PLD1_ORT_PT3_5 ,PLD1 OR term 5" "0,1" bitfld.word 0x00 12. " PLD1_ORT_PT3_4 ,PLD1 OR term 4" "0,1" textline " " bitfld.word 0x00 11. " PLD1_ORT_PT3_3 ,PLD1 OR term 3" "0,1" bitfld.word 0x00 10. " PLD1_ORT_PT3_2 ,PLD1 OR term 2" "0,1" bitfld.word 0x00 9. " PLD1_ORT_PT3_1 ,PLD1 OR term 1" "0,1" bitfld.word 0x00 8. " PLD1_ORT_PT3_0 ,PLD1 OR term 0" "0,1" textline " " bitfld.word 0x00 7. " PLD0_ORT_PT3_7 ,PLD0 OR term 7" "0,1" bitfld.word 0x00 6. " PLD0_ORT_PT3_6 ,PLD0 OR term 6" "0,1" bitfld.word 0x00 5. " PLD0_ORT_PT3_5 ,PLD0 OR term 5" "0,1" bitfld.word 0x00 4. " PLD0_ORT_PT3_4 ,PLD0 OR term 4" "0,1" textline " " bitfld.word 0x00 3. " PLD0_ORT_PT3_3 ,PLD0 OR term 3" "0,1" bitfld.word 0x00 2. " PLD0_ORT_PT3_2 ,PLD0 OR term 2" "0,1" bitfld.word 0x00 1. " PLD0_ORT_PT3_1 ,PLD0 OR term 1" "0,1" bitfld.word 0x00 0. " PLD0_ORT_PT3_0 ,PLD0 OR term 0" "0,1" group.word 0x38++0x07 line.word 0x00 "PLD_MC_CFG_CEN_CONST,Macrocell Configuration For Carry Enable And Constant" bitfld.word 0x00 15. " PLD1_MC3_DFF_C ,PLD1 MC3 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 14. " PLD1_MC3_CEN ,PLD1 MC3 carry enable" "Disabled,Enabled" bitfld.word 0x00 13. " PLD1_MC2_DFF_C ,PLD1 MC2 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 12. " PLD1_MC2_CEN ,PLD1 MC2 carry enable" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " PLD1_MC1_DFF_C ,PLD1 MC1 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 10. " PLD1_MC1_CEN ,PLD1 MC1 carry enable" "Disabled,Enabled" bitfld.word 0x00 9. " PLD1_MC0_DFF_C ,PLD1 MC0 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 8. " PLD1_MC0_CEN ,PLD1 MC0 carry enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " PLD0_MC3_DFF_C ,PLD0 MC3 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 6. " PLD0_MC3_CEN ,PLD0 MC3 carry enable" "Disabled,Enabled" bitfld.word 0x00 5. " PLD0_MC2_DFF_C ,PLD0 MC2 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 4. " PLD0_MC2_CEN ,PLD0 MC2 carry enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " PLD0_MC1_DFF_C ,PLD0 MC1 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 2. " PLD0_MC1_CEN ,PLD0 MC1 carry enable" "Disabled,Enabled" bitfld.word 0x00 1. " PLD0_MC0_DFF_C ,PLD0 MC0 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 0. " PLD0_MC0_CEN ,PLD0_MC0 carry enable" "Disabled,Enabled" line.word 0x02 "PLD_MC_CFG_XORFB,PLD Macro Cell XOR Feedback" bitfld.word 0x02 14.--15. " PLD1_MC3_XORFB ,PLD1 MC3 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" bitfld.word 0x02 12.--13. " PLD1_MC2_XORFB ,PLD1 MC2 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" bitfld.word 0x02 10.--11. " PLD1_MC1_XORFB ,PLD1 MC1 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" bitfld.word 0x02 8.--9. " PLD1_MC0_XORFB ,PLD1 MC0 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" textline " " bitfld.word 0x02 6.--7. " PLD0_MC3_XORFB ,PLD0 MC3 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" bitfld.word 0x02 4.--5. " PLD0_MC2_XORFB ,PLD0 MC2 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" bitfld.word 0x02 2.--3. " PLD0_MC1_XORFB ,PLD0 MC1 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" bitfld.word 0x02 0.--1. " PLD0_MC0_XORFB ,PLD0 MC0 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" line.word 0x04 "PLD_MC_SET_RESET,PLD Macro Cell Set Reset Selection" bitfld.word 0x04 15. " PLD1_MC3_RESET_SEL ,PLD1 MC3 reset select enable" "Disabled,Enabled" bitfld.word 0x04 14. " PLD1_MC3_SET_SEL ,PLD1 MC3 set select enable" "Disabled,Enabled" bitfld.word 0x04 13. " PLD1_MC2_RESET_SEL ,PLD1 MC2 reset select enable" "Disabled,Enabled" bitfld.word 0x04 12. " PLD1_MC2_SET_SEL ,PLD1 MC2 set select enable" "Disabled,Enabled" textline " " bitfld.word 0x04 11. " PLD1_MC1_RESET_SEL ,PLD1 MC1 reset select enable" "Disabled,Enabled" bitfld.word 0x04 10. " PLD1_MC1_SET_SEL ,PLD1 MC0 set select enable" "Disabled,Enabled" bitfld.word 0x04 9. " PLD1_MC0_RESET_SEL ,PLD1 MC0 reset select enable" "Disabled,Enabled" bitfld.word 0x04 8. " PLD1_MC0_SET_SEL ,PLD1 MC0 set select enable" "Disabled,Enabled" textline " " bitfld.word 0x04 7. " PLD0_MC3_RESET_SEL ,PLD0 MC3 reset select enable" "Disabled,Enabled" bitfld.word 0x04 6. " PLD0_MC3_SET_SEL ,PLD0 MC3 set select enable" "Disabled,Enabled" bitfld.word 0x04 5. " PLD0_MC2_RESET_SEL ,PLD0 MC2 reset select enable" "Disabled,Enabled" bitfld.word 0x04 4. " PLD0_MC2_SET_SEL ,PLD0 MC2 set select enable" "Disabled,Enabled" textline " " bitfld.word 0x04 3. " PLD0_MC1_RESET_SEL ,PLD0 MC1 reset select enable" "Disabled,Enabled" bitfld.word 0x04 2. " PLD0_MC1_SET_SEL ,PLD0 MC1 set select enable" "Disabled,Enabled" bitfld.word 0x04 1. " PLD0_MC0_RESET_SEL ,Reset select enable" "Disabled,Enabled" bitfld.word 0x04 0. " PLD0_MC0_SET_SEL ,PLD0 MC0 set select enable" "Disabled,Enabled" line.word 0x06 "PLD_MC_CFG_BYPASS,PLD Macro Cell Bypass Control" bitfld.word 0x06 15. " NC15 ,Spare register bit NC15" "0,1" bitfld.word 0x06 14. " PLD1_MC3_BYPASS ,PLD1 MC3 bypass selection" "REGISTER,COMBINATIONAL" bitfld.word 0x06 13. " NC13 ,Spare register bit NC13" "0,1" bitfld.word 0x06 12. " PLD1_MC2_BYPASS ,PLD1 MC2 bypass selection" "REGISTER,COMBINATIONAL" textline " " bitfld.word 0x06 11. " NC11 ,Spare register bit NC11" "0,1" bitfld.word 0x06 10. " PLD1_MC1_BYPASS ,PLD1 MC1 bypass selection" "REGISTER,COMBINATIONAL" bitfld.word 0x06 9. " NC9 ,Spare register bit NC9" "0,1" bitfld.word 0x06 8. " PLD1_MC0_BYPASS ,PLD1 MC0 bypass selection" "REGISTER,COMBINATIONAL" textline " " bitfld.word 0x06 7. " NC7 ,Spare register bit NC7" "0,1" bitfld.word 0x06 6. " PLD0_MC3_BYPASS ,PLD0 MC3 bypass selection" "REGISTER,COMBINATIONAL" bitfld.word 0x06 5. " NC5 ,Spare register bit NC5" "0,1" bitfld.word 0x06 4. " PLD0_MC2_BYPASS ,PLD0 MC2 bypass selection" "REGISTER,COMBINATIONAL" textline " " bitfld.word 0x06 3. " NC3 ,Spare register bit NC3" "0,1" bitfld.word 0x06 2. " PLD0_MC1_BYPASS ,PLD0 MC1 bypass selection" "REGISTER,COMBINATIONAL" bitfld.word 0x06 1. " NC1 ,Spare register bit NC1" "0,1" bitfld.word 0x06 0. " PLD0_MC0_BYPASS ,PLD0 MC0 bypass selection" "REGISTER,COMBINATIONAL" group.byte 0x40++0x17 line.byte 0x00 "CFG0,Datapath Input Selection - RAD1 RAD0. Address Bits 0 And 1 To The Dynamic Configuration RAM" bitfld.byte 0x00 4.--6. " RAD1 ,Datapath permutable input mux RAD1" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." bitfld.byte 0x00 0.--2. " RAD0 ,Datapath permutable input mux RAD0" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." line.byte 0x01 "CFG1,Datapath Input Selection - RAD2. Address Bit 2 To The Dynamic Configuration RAM" bitfld.byte 0x01 7. " DP_RTE_BYPASS4 ,Dp_in bypass control 4" "DP_IN4_ROUTE,DP_IN4_BYPASS" bitfld.byte 0x01 6. " DP_RTE_BYPASS3 ,Dp_in bypass control 3" "DP_IN3_ROUTE,DP_IN3_BYPASS" bitfld.byte 0x01 5. " DP_RTE_BYPASS2 ,Dp_in bypass control 2" "DP_IN2_ROUTE,DP_IN2_BYPASS" bitfld.byte 0x01 4. " DP_RTE_BYPASS1 ,Dp_in bypass control 1" "DP_IN1_ROUTE,DP_IN1_BYPASS" textline " " bitfld.byte 0x01 3. " DP_RTE_BYPASS0 ,Dp_in bypass control 0" "DP_IN0_ROUTE,DP_IN0_BYPASS" bitfld.byte 0x01 0.--2. " RAD2 ,Datapath permutable input mux 2" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." line.byte 0x02 "CFG2,Datapath Input Selection - F1_LD, F0_LD" bitfld.byte 0x02 7. " NC7 ,Spare register bit NC7" "0,1" bitfld.byte 0x02 4.--6. " F1_LD ,Datapath permutable input mux F1_LD" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." bitfld.byte 0x02 3. " DP_RTE_BYPASS5 ,Dp_in bypass control 5" "DP_IN5_ROUTE,DP_IN5_BYPASS" bitfld.byte 0x02 0.--2. " F0_LD ,Datapath permutable input mux F0_LD" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." line.byte 0x03 "CFG3,Datapath Input Selection - D1_LD, D0_LD" bitfld.byte 0x03 4.--6. " D1_LD ,Datapath permutable input mux D1_LD" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." bitfld.byte 0x03 0.--2. " D0_LD ,Datapath permutable input mux D0_LD" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." line.byte 0x04 "CFG4,Datapath Input Selection - CI_MUX SI_MUX" bitfld.byte 0x04 4.--6. " CI_MUX ,Datapath permutable input mux CI_MUX" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." bitfld.byte 0x04 0.--2. " SI_MUX ,Datapath permutable input mux SI_MUX" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." line.byte 0x05 "CFG5,Datapath Output Selection For OUT1 OUT0" bitfld.byte 0x05 4.--7. " OUT1 ,Datapath permutable output mux OUT1" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT" bitfld.byte 0x05 0.--3. " OUT0 ,Datapath permutable output mux OUT0" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT" line.byte 0x06 "CFG6,Datapath Output Selection For OUT3 OUT2" bitfld.byte 0x06 4.--7. " OUT3 ,Datapath permutable output mux OUT3" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT" bitfld.byte 0x06 0.--3. " OUT2 ,Datapath permutable output mux OUT2" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT" line.byte 0x07 "CFG7,Datapath Output Selection For OUT5 OUT4" bitfld.byte 0x07 4.--7. " OUT5 ,Datapath permutable output mux OUT5" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT" bitfld.byte 0x07 0.--3. " OUT4 ,Datapath permutable output mux OUT4" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT" line.byte 0x08 "CFG8,Datapath Output Synchronization Option" bitfld.byte 0x08 7. " NC7 ,Spare register bit NC7" "0,1" bitfld.byte 0x08 6. " NC6 ,Spare register bit NC6" "0,1" bitfld.byte 0x08 0.--5. " OUT_SYNC ,Datapath output synchronization" "REGISTERED,COMBINATIONAL,?..." line.byte 0x09 "CFG9,Datapath ALU Mask" line.byte 0x0A "CFG10,Datapath Compare 0 Mask" line.byte 0x0B "CFG11,Datapath Compare 1 Mask" line.byte 0x0C "CFG12,Datapath Mask Enables And Shift In Configuration" bitfld.byte 0x0C 7. " CMASK1_EN ,Datapath mask CMASK1 enable" "Disabled,Enabled" bitfld.byte 0x0C 6. " CMASK0_EN ,Datapath mask CMASK0 enable" "Disabled,Enabled" bitfld.byte 0x0C 5. " AMASK_EN ,Datapath mask AMASK enable" "Disabled,Enabled" bitfld.byte 0x0C 4. " DEF_SI ,Datapath default shift value" "DEFAULT_0,DEFAULT_1" textline " " bitfld.byte 0x0C 2.--3. " SI_SELB ,Datapath shift in source select" "DEFAULT,REGISTERED,ROUTE,CHAIN" bitfld.byte 0x0C 0.--1. " SI_SELA ,Datapath shift in source select" "DEFAULT,REGISTERED,ROUTE,CHAIN" line.byte 0x0D "CFG13,Datapath Carry In And Compare Configuration" bitfld.byte 0x0D 6.--7. " CMP_SELB ,Datapath compare select B" "A1_D1,A1_A0,A0_D1,A0_A0" bitfld.byte 0x0D 4.--5. " CMP_SELA ,Datapath compare select A" "A1_D1,A1_A0,A0_D1,A0_A0" bitfld.byte 0x0D 2.--3. " CI_SELB ,Datapath carry in source select B" "DEFAULT,REGISTERED,ROUTE,CHAIN" bitfld.byte 0x0D 0.--1. " CI_SELA ,Datapath carry in source select A" "DEFAULT,REGISTERED,ROUTE,CHAIN" line.byte 0x0E "CFG14,Datapath Chaining And MSB Configuration" bitfld.byte 0x0E 7. " MSB_EN ,Datapath MSB selection enable" "Disabled,Enabled" bitfld.byte 0x0E 4.--6. " MSB_SEL ,Datapath MSB selection" "BIT0,BIT1,BIT2,BIT3,BIT4,BIT5,BIT6,BIT7" bitfld.byte 0x0E 3. " CHAIN_CMSB ,Datapath CRC MSB chaining enable" "Disabled,Enabled" bitfld.byte 0x0E 2. " CHAIN_FB ,Datapath CRC feedback chaining enable" "Disabled,Enabled" textline " " bitfld.byte 0x0E 1. " CHAIN1 ,Datapath condition chaining enable 1" "Disabled,Enabled" bitfld.byte 0x0E 0. " CHAIN0 ,Datapath condition chaining enable 0" "Disabled,Enabled" line.byte 0x0F "CFG15,Datapath FIFO, Shift And Parallel Input Control" bitfld.byte 0x0F 7. " PI_SEL ,Datapath parallel input selection" "NORMAL,PARALLEL" bitfld.byte 0x0F 6. " SHIFT_SEL ,Datapath shift out selection" "SOL_MSB,SOR" bitfld.byte 0x0F 5. " PI_DYN ,Enable for dynamic control of parallel data input (Pi) mux" "Disabled,Enabled" bitfld.byte 0x0F 4. " MSB_SI ,Arithmetic shift right operation shift in selection" "DEFAULT,MSB" textline " " bitfld.byte 0x0F 2.--3. " F1_INSEL ,Datapath FIFO configuration 1" "INPUT,OUTPUT_A0,OUTPUT_A1,OUTPUT_ALU" bitfld.byte 0x0F 0.--1. " F0_INSEL ,Datapath FIFO configuration 0" "INPUT,OUTPUT_A0,OUTPUT_A1,OUTPUT_ALU" line.byte 0x10 "CFG16,Datapath FIFO And Register Access Configuration Control" bitfld.byte 0x10 7. " F1_CK_INV ,FIFO 1 clock Inverted" "NORMAL,Inverted" bitfld.byte 0x10 6. " F0_CK_INV ,FIFO 0 clock Inverted" "NORMAL,Inverted" bitfld.byte 0x10 5. " FIFO_FAST ,FIFO fast mode" "Disabled,Enabled" bitfld.byte 0x10 4. " FIFO_CAP ,FIFO software capture mode" "Disabled,Enabled" textline " " bitfld.byte 0x10 3. " FIFO_EDGE ,Edge/level sensitive FIFO write control (Fx_ld)" "LEVEL,EDGE" bitfld.byte 0x10 2. " FIFO_ASYNC ,Asynchronous FIFO clocking support" "Disabled,Enabled" bitfld.byte 0x10 1. " EXT_CRCPRS ,External CRC/PRS mode" "INTERNAL,EXTERNAL" bitfld.byte 0x10 0. " WRK16_CONCAT ,Datapath register access mode" "DEFAULT,CONCATENATE" line.byte 0x11 "CFG17,Datapath FIFO Control" bitfld.byte 0x11 4. " FIFO_ADD_SYNC ,Sync flip-flop to FIFO block status" "Disabled,Enabled" bitfld.byte 0x11 3. " NC3 ,Spare register bit NC3" "0,1" bitfld.byte 0x11 2. " NC2 ,Spare register bit NC2" "0,1" bitfld.byte 0x11 1. " F1_DYN ,FIFO 1 direction" "STATIC,DYNAMIC" textline " " bitfld.byte 0x11 0. " F0_DYN ,FIFO 0 direction" "STATIC,DYNAMIC" line.byte 0x12 "CFG18,Control Register Mode 0" line.byte 0x13 "CFG19,Control Register Mode 1" line.byte 0x14 "CFG20,Status Register Input Mode Selection" bitfld.byte 0x14 7. " STAT_MD[7] ,Bit 7 status input mode select" "Transparent,Sticky cleared" bitfld.byte 0x14 6. " [6] ,Bit 6 status input mode select" "Transparent,Sticky cleared" bitfld.byte 0x14 5. " [5] ,Bit 5 status input mode select" "Transparent,Sticky cleared" bitfld.byte 0x14 4. " [4] ,Bit 4 status input mode select" "Transparent,Sticky cleared" textline " " bitfld.byte 0x14 3. " [3] ,Bit 3 status input mode select" "Transparent,Sticky cleared" bitfld.byte 0x14 2. " [2] ,Bit 2 status input mode select" "Transparent,Sticky cleared" bitfld.byte 0x14 1. " [1] ,Bit 1 status input mode select" "Transparent,Sticky cleared" bitfld.byte 0x14 0. " [0] ,Bit 0 status input mode select" "Transparent,Sticky cleared" line.byte 0x15 "CFG21,Spare Register Bits" bitfld.byte 0x15 1. " NC1 ,Spare register bit NC1" "0,1" bitfld.byte 0x15 0. " NC0 ,Spare register bit NC0" "0,1" line.byte 0x16 "CFG22,SC Block Configuration Control" bitfld.byte 0x16 4. " SC_EXT_RES ,Control register external reset operation" "Disabled,Enabled" bitfld.byte 0x16 3. " SC_SYNC_MD ,SC sync mode" "NORMAL,SYNC_MODE" bitfld.byte 0x16 2. " SC_INT_MD ,SC interrupt mode" "NORMAL,INT_MODE" bitfld.byte 0x16 0.--1. " SC_OUT_CTL ,Output source for the status and control routing connections" "CONTROL,PARALLEL,COUNTER,?..." line.byte 0x17 "CFG23,Counter Control" bitfld.byte 0x17 6. " ALT_CNT ,Alternate operating mode of the counter" "DEFAULT_MODE,ALT_MODE" bitfld.byte 0x17 5. " ROUTE_EN ,Counter enable signal for routing input" "Disabled,Enabled" bitfld.byte 0x17 4. " ROUTE_LD ,Counter load signal for routing input" "Disabled,Enabled" bitfld.byte 0x17 2.--3. " CNT_EN_SEL ,Routing inputs for the counter enable signal" "SC_IN4,SC_IN5,SC_IN6,SC_IO" textline " " bitfld.byte 0x17 0.--1. " CNT_LD_SEL ,Routing inputs for the counter load signal" "SC_IN0,SC_IN1,SC_IN2,SC_IN3" if (((per.b(ad:0x400F3480+0x5F))&0x01)==0x01) group.byte 0x58++0x03 line.byte 0x00 "CFG24,PLD0 Clock And Reset Control" bitfld.byte 0x00 6.--7. " RC_RES_SEL ,Routed reset for the associated UDB component block" "0,1,2,3" bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x00 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x00 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x00 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x01 "CFG25,PLD1 Clock And Reset Control" bitfld.byte 0x00 6.--7. " RC_RES_SEL ,Routed reset for the associated UDB component block" "0,1,2,3" bitfld.byte 0x01 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x01 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x01 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x01 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x02 "CFG26,Datapath Clock And Reset Control" bitfld.byte 0x00 6.--7. " RC_RES_SEL ,Routed reset for the associated UDB component block" "0,1,2,3" bitfld.byte 0x02 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x02 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x02 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x02 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x03 "CFG27,Status/control Clock And Reset Control" bitfld.byte 0x00 6.--7. " RC_RES_SEL ,Routed reset for the associated UDB component block" "0,1,2,3" bitfld.byte 0x03 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x03 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x03 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x03 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" else group.byte 0x58++0x03 line.byte 0x00 "CFG24,PLD0 Clock And Reset Control" bitfld.byte 0x00 6. " FRES ,Firmware reset for the associated UDB component block" "No reset,Reset" bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x00 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x00 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x00 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x01 "CFG25,PLD1 Clock And Reset Control" bitfld.byte 0x00 6. " FRES ,Firmware reset for the associated UDB component block" "No reset,Reset" bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x00 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x00 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x00 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x02 "CFG26,Datapath Clock And Reset Control" bitfld.byte 0x00 6. " FRES ,Firmware reset for the associated UDB component block" "No reset,Reset" bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x00 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x00 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x00 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x03 "CFG27,Status/control Clock And Reset Control" rbitfld.byte 0x00 6. " FRES ,Firmware reset for the associated UDB component block" "No reset,Reset" bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x03 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x03 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x03 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" endif group.byte 0x5C++0x01 line.byte 0x00 "CFG28,Clock Selection For PLD1 And PLD0" bitfld.byte 0x00 4.--7. " PLD1_CK_SEL ,PLD1 clock selection registers" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,EXT_CLK,SYSCLK,?..." bitfld.byte 0x00 0.--3. " PLD0_CK_SEL ,PLD0 clock selection registers" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,EXT_CLK,SYSCLK,?..." line.byte 0x01 "CFG29,Clock Selection For Datapath, Status And Control" bitfld.byte 0x01 4.--7. " SC_CK_SEL ,SC clock selection registers" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,EXT_CLK,SYSCLK,?..." bitfld.byte 0x01 0.--3. " DP_CK_SEL ,DP clock selection registers" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,EXT_CLK,SYSCLK,?..." if (((per.b(ad:0x400F3480+0x5F))&0x01)==0x01) group.byte 0x5E++0x01 line.byte 0x00 "CFG30,Reset Control" bitfld.byte 0x00 7. " SC_RES_POL ,Polarity of the selected SC routed reset" "Not inverted,Inverted" bitfld.byte 0x00 6. " DP_RES_POL ,Polarity of the selected datapath routed reset" "Not inverted,Inverted" bitfld.byte 0x00 4. " GUDB_WR ,Global write operation for the configuration and working registers UDB" "Disabled,Enabled" bitfld.byte 0x00 3. " EN_RES_CNTCTL ,Routed reset to the counter/control register" "Disabled,Enabled" textline " " rbitfld.byte 0x00 2. " RES_POL ,Polarity of the routed reset" "NEGATED,ASSERTED" rbitfld.byte 0x00 0.--1. " RES_SEL ,RC routing input for the compatible reset scheme" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x01 "CFG31,Reset Control" bitfld.byte 0x01 7. " PLD1_RES_POL ,Polarity of the routed reset for both plds" "Not inverted,Inverted" bitfld.byte 0x01 6. " PLD0_RES_POL ,Polarity of the routed reset for both plds" "Not inverted,Inverted" bitfld.byte 0x01 4.--5. " EXT_CK_SEL ,External clock selection" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" bitfld.byte 0x01 3. " EN_RES_DP ,Routed reset to the datapath block" "Disabled,Enabled" textline " " bitfld.byte 0x01 2. " EN_RES_STAT ,Routed reset to the status register" "NEGATED,ASSERTED" bitfld.byte 0x01 1. " EXT_SYNC ,Synchronization of selected external clock" "Disabled,Enabled" bitfld.byte 0x01 0. " ALT_RES ,Toggles between two reset configurations" "COMPATIBLE,ALTERNATE" else group.byte 0x5E++0x01 line.byte 0x00 "CFG30,Reset Control" rbitfld.byte 0x00 7. " SC_RES_POL ,Polarity of the selected SC routed reset" "Not inverted,Inverted" rbitfld.byte 0x00 6. " DP_RES_POL ,Polarity of the selected datapath routed reset" "Not inverted,Inverted" bitfld.byte 0x00 4. " GUDB_WR ,Global write operation for the configuration and working registers UDB" "Disabled,Enabled" bitfld.byte 0x00 3. " EN_RES_CNTCTL ,Routed reset to the counter/control register" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " RES_POL ,Polarity of the routed reset" "NEGATED,ASSERTED" bitfld.byte 0x00 0.--1. " RES_SEL ,RC routing input for the compatible reset scheme" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x01 "CFG31,Reset Control" bitfld.byte 0x01 7. " PLD1_RES_POL ,Polarity of the routed reset for both plds" "Not inverted,Inverted" bitfld.byte 0x01 6. " PLD0_RES_POL ,Polarity of the routed reset for both plds" "Not inverted,Inverted" bitfld.byte 0x01 4.--5. " EXT_CK_SEL ,External clock selection" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" rbitfld.byte 0x01 3. " EN_RES_DP ,Routed reset to the datapath block" "Disabled,Enabled" textline " " rbitfld.byte 0x01 2. " EN_RES_STAT ,Routed reset to the status register" "NEGATED,ASSERTED" bitfld.byte 0x01 1. " EXT_SYNC ,Synchronization of selected external clock" "Disabled,Enabled" bitfld.byte 0x01 0. " ALT_RES ,Toggles between two reset configurations" "COMPATIBLE,ALTERNATE" endif group.word 0x60++0x01 line.word 0x00 "DCFG0,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x62++0x01 line.word 0x00 "DCFG1,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x64++0x01 line.word 0x00 "DCFG2,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x66++0x01 line.word 0x00 "DCFG3,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x68++0x01 line.word 0x00 "DCFG4,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x6A++0x01 line.word 0x00 "DCFG5,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x6C++0x01 line.word 0x00 "DCFG6,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x6E++0x01 line.word 0x00 "DCFG7,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" width 0x0B tree.end tree "UDB P3 U0" base ad:0x400F3600 width 22. group.long 0x0++0x03 line.long 0x00 "PLD_IT0,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT0T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT0T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT0T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT0T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT0T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT0T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT0T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT0T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT0T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT0T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT0T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT0T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT0T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT0T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT0T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT0T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT0C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT0C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT0C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT0C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT0C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT0C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT0C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT0C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT0C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT0C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT0C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT0C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT0C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT0C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT0C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT0C_0 ,PLD0 complement input term 0" "0,1" group.long 0x4++0x03 line.long 0x00 "PLD_IT1,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT1T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT1T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT1T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT1T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT1T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT1T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT1T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT1T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT1T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT1T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT1T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT1T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT1T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT1T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT1T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT1T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT1C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT1C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT1C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT1C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT1C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT1C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT1C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT1C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT1C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT1C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT1C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT1C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT1C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT1C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT1C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT1C_0 ,PLD0 complement input term 0" "0,1" group.long 0x8++0x03 line.long 0x00 "PLD_IT2,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT2T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT2T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT2T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT2T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT2T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT2T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT2T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT2T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT2T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT2T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT2T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT2T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT2T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT2T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT2T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT2T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT2C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT2C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT2C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT2C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT2C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT2C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT2C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT2C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT2C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT2C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT2C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT2C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT2C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT2C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT2C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT2C_0 ,PLD0 complement input term 0" "0,1" group.long 0xC++0x03 line.long 0x00 "PLD_IT3,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT3T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT3T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT3T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT3T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT3T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT3T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT3T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT3T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT3T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT3T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT3T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT3T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT3T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT3T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT3T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT3T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT3C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT3C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT3C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT3C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT3C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT3C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT3C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT3C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT3C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT3C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT3C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT3C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT3C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT3C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT3C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT3C_0 ,PLD0 complement input term 0" "0,1" group.long 0x10++0x03 line.long 0x00 "PLD_IT4,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT4T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT4T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT4T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT4T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT4T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT4T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT4T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT4T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT4T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT4T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT4T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT4T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT4T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT4T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT4T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT4T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT4C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT4C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT4C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT4C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT4C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT4C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT4C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT4C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT4C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT4C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT4C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT4C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT4C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT4C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT4C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT4C_0 ,PLD0 complement input term 0" "0,1" group.long 0x14++0x03 line.long 0x00 "PLD_IT5,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT5T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT5T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT5T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT5T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT5T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT5T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT5T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT5T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT5T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT5T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT5T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT5T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT5T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT5T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT5T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT5T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT5C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT5C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT5C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT5C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT5C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT5C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT5C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT5C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT5C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT5C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT5C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT5C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT5C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT5C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT5C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT5C_0 ,PLD0 complement input term 0" "0,1" group.long 0x18++0x03 line.long 0x00 "PLD_IT6,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT6T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT6T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT6T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT6T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT6T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT6T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT6T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT6T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT6T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT6T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT6T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT6T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT6T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT6T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT6T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT6T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT6C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT6C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT6C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT6C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT6C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT6C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT6C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT6C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT6C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT6C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT6C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT6C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT6C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT6C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT6C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT6C_0 ,PLD0 complement input term 0" "0,1" group.long 0x1C++0x03 line.long 0x00 "PLD_IT7,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT7T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT7T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT7T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT7T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT7T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT7T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT7T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT7T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT7T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT7T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT7T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT7T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT7T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT7T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT7T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT7T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT7C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT7C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT7C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT7C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT7C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT7C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT7C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT7C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT7C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT7C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT7C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT7C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT7C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT7C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT7C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT7C_0 ,PLD0 complement input term 0" "0,1" group.long 0x20++0x03 line.long 0x00 "PLD_IT8,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT8T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT8T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT8T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT8T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT8T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT8T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT8T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT8T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT8T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT8T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT8T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT8T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT8T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT8T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT8T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT8T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT8C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT8C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT8C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT8C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT8C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT8C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT8C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT8C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT8C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT8C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT8C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT8C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT8C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT8C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT8C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT8C_0 ,PLD0 complement input term 0" "0,1" group.long 0x24++0x03 line.long 0x00 "PLD_IT9,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT9T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT9T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT9T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT9T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT9T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT9T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT9T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT9T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT9T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT9T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT9T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT9T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT9T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT9T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT9T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT9T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT9C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT9C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT9C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT9C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT9C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT9C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT9C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT9C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT9C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT9C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT9C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT9C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT9C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT9C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT9C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT9C_0 ,PLD0 complement input term 0" "0,1" group.long 0x28++0x03 line.long 0x00 "PLD_IT10,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT10T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT10T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT10T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT10T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT10T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT10T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT10T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT10T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT10T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT10T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT10T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT10T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT10T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT10T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT10T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT10T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT10C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT10C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT10C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT10C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT10C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT10C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT10C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT10C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT10C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT10C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT10C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT10C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT10C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT10C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT10C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT10C_0 ,PLD0 complement input term 0" "0,1" group.long 0x2C++0x03 line.long 0x00 "PLD_IT11,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT11T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT11T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT11T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT11T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT11T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT11T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT11T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT11T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT11T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT11T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT11T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT11T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT11T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT11T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT11T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT11T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT11C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT11C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT11C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT11C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT11C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT11C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT11C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT11C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT11C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT11C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT11C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT11C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT11C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT11C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT11C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT11C_0 ,PLD0 complement input term 0" "0,1" group.word 0x30++0x01 line.word 0x00 "PLD_ORT0,PLD OR Terms" bitfld.word 0x00 15. " PLD1_ORT_PT0_7 ,PLD1 OR term 7" "0,1" bitfld.word 0x00 14. " PLD1_ORT_PT0_6 ,PLD1 OR term 6" "0,1" bitfld.word 0x00 13. " PLD1_ORT_PT0_5 ,PLD1 OR term 5" "0,1" bitfld.word 0x00 12. " PLD1_ORT_PT0_4 ,PLD1 OR term 4" "0,1" textline " " bitfld.word 0x00 11. " PLD1_ORT_PT0_3 ,PLD1 OR term 3" "0,1" bitfld.word 0x00 10. " PLD1_ORT_PT0_2 ,PLD1 OR term 2" "0,1" bitfld.word 0x00 9. " PLD1_ORT_PT0_1 ,PLD1 OR term 1" "0,1" bitfld.word 0x00 8. " PLD1_ORT_PT0_0 ,PLD1 OR term 0" "0,1" textline " " bitfld.word 0x00 7. " PLD0_ORT_PT0_7 ,PLD0 OR term 7" "0,1" bitfld.word 0x00 6. " PLD0_ORT_PT0_6 ,PLD0 OR term 6" "0,1" bitfld.word 0x00 5. " PLD0_ORT_PT0_5 ,PLD0 OR term 5" "0,1" bitfld.word 0x00 4. " PLD0_ORT_PT0_4 ,PLD0 OR term 4" "0,1" textline " " bitfld.word 0x00 3. " PLD0_ORT_PT0_3 ,PLD0 OR term 3" "0,1" bitfld.word 0x00 2. " PLD0_ORT_PT0_2 ,PLD0 OR term 2" "0,1" bitfld.word 0x00 1. " PLD0_ORT_PT0_1 ,PLD0 OR term 1" "0,1" bitfld.word 0x00 0. " PLD0_ORT_PT0_0 ,PLD0 OR term 0" "0,1" group.word 0x32++0x01 line.word 0x00 "PLD_ORT1,PLD OR Terms" bitfld.word 0x00 15. " PLD1_ORT_PT1_7 ,PLD1 OR term 7" "0,1" bitfld.word 0x00 14. " PLD1_ORT_PT1_6 ,PLD1 OR term 6" "0,1" bitfld.word 0x00 13. " PLD1_ORT_PT1_5 ,PLD1 OR term 5" "0,1" bitfld.word 0x00 12. " PLD1_ORT_PT1_4 ,PLD1 OR term 4" "0,1" textline " " bitfld.word 0x00 11. " PLD1_ORT_PT1_3 ,PLD1 OR term 3" "0,1" bitfld.word 0x00 10. " PLD1_ORT_PT1_2 ,PLD1 OR term 2" "0,1" bitfld.word 0x00 9. " PLD1_ORT_PT1_1 ,PLD1 OR term 1" "0,1" bitfld.word 0x00 8. " PLD1_ORT_PT1_0 ,PLD1 OR term 0" "0,1" textline " " bitfld.word 0x00 7. " PLD0_ORT_PT1_7 ,PLD0 OR term 7" "0,1" bitfld.word 0x00 6. " PLD0_ORT_PT1_6 ,PLD0 OR term 6" "0,1" bitfld.word 0x00 5. " PLD0_ORT_PT1_5 ,PLD0 OR term 5" "0,1" bitfld.word 0x00 4. " PLD0_ORT_PT1_4 ,PLD0 OR term 4" "0,1" textline " " bitfld.word 0x00 3. " PLD0_ORT_PT1_3 ,PLD0 OR term 3" "0,1" bitfld.word 0x00 2. " PLD0_ORT_PT1_2 ,PLD0 OR term 2" "0,1" bitfld.word 0x00 1. " PLD0_ORT_PT1_1 ,PLD0 OR term 1" "0,1" bitfld.word 0x00 0. " PLD0_ORT_PT1_0 ,PLD0 OR term 0" "0,1" group.word 0x34++0x01 line.word 0x00 "PLD_ORT2,PLD OR Terms" bitfld.word 0x00 15. " PLD1_ORT_PT2_7 ,PLD1 OR term 7" "0,1" bitfld.word 0x00 14. " PLD1_ORT_PT2_6 ,PLD1 OR term 6" "0,1" bitfld.word 0x00 13. " PLD1_ORT_PT2_5 ,PLD1 OR term 5" "0,1" bitfld.word 0x00 12. " PLD1_ORT_PT2_4 ,PLD1 OR term 4" "0,1" textline " " bitfld.word 0x00 11. " PLD1_ORT_PT2_3 ,PLD1 OR term 3" "0,1" bitfld.word 0x00 10. " PLD1_ORT_PT2_2 ,PLD1 OR term 2" "0,1" bitfld.word 0x00 9. " PLD1_ORT_PT2_1 ,PLD1 OR term 1" "0,1" bitfld.word 0x00 8. " PLD1_ORT_PT2_0 ,PLD1 OR term 0" "0,1" textline " " bitfld.word 0x00 7. " PLD0_ORT_PT2_7 ,PLD0 OR term 7" "0,1" bitfld.word 0x00 6. " PLD0_ORT_PT2_6 ,PLD0 OR term 6" "0,1" bitfld.word 0x00 5. " PLD0_ORT_PT2_5 ,PLD0 OR term 5" "0,1" bitfld.word 0x00 4. " PLD0_ORT_PT2_4 ,PLD0 OR term 4" "0,1" textline " " bitfld.word 0x00 3. " PLD0_ORT_PT2_3 ,PLD0 OR term 3" "0,1" bitfld.word 0x00 2. " PLD0_ORT_PT2_2 ,PLD0 OR term 2" "0,1" bitfld.word 0x00 1. " PLD0_ORT_PT2_1 ,PLD0 OR term 1" "0,1" bitfld.word 0x00 0. " PLD0_ORT_PT2_0 ,PLD0 OR term 0" "0,1" group.word 0x36++0x01 line.word 0x00 "PLD_ORT3,PLD OR Terms" bitfld.word 0x00 15. " PLD1_ORT_PT3_7 ,PLD1 OR term 7" "0,1" bitfld.word 0x00 14. " PLD1_ORT_PT3_6 ,PLD1 OR term 6" "0,1" bitfld.word 0x00 13. " PLD1_ORT_PT3_5 ,PLD1 OR term 5" "0,1" bitfld.word 0x00 12. " PLD1_ORT_PT3_4 ,PLD1 OR term 4" "0,1" textline " " bitfld.word 0x00 11. " PLD1_ORT_PT3_3 ,PLD1 OR term 3" "0,1" bitfld.word 0x00 10. " PLD1_ORT_PT3_2 ,PLD1 OR term 2" "0,1" bitfld.word 0x00 9. " PLD1_ORT_PT3_1 ,PLD1 OR term 1" "0,1" bitfld.word 0x00 8. " PLD1_ORT_PT3_0 ,PLD1 OR term 0" "0,1" textline " " bitfld.word 0x00 7. " PLD0_ORT_PT3_7 ,PLD0 OR term 7" "0,1" bitfld.word 0x00 6. " PLD0_ORT_PT3_6 ,PLD0 OR term 6" "0,1" bitfld.word 0x00 5. " PLD0_ORT_PT3_5 ,PLD0 OR term 5" "0,1" bitfld.word 0x00 4. " PLD0_ORT_PT3_4 ,PLD0 OR term 4" "0,1" textline " " bitfld.word 0x00 3. " PLD0_ORT_PT3_3 ,PLD0 OR term 3" "0,1" bitfld.word 0x00 2. " PLD0_ORT_PT3_2 ,PLD0 OR term 2" "0,1" bitfld.word 0x00 1. " PLD0_ORT_PT3_1 ,PLD0 OR term 1" "0,1" bitfld.word 0x00 0. " PLD0_ORT_PT3_0 ,PLD0 OR term 0" "0,1" group.word 0x38++0x07 line.word 0x00 "PLD_MC_CFG_CEN_CONST,Macrocell Configuration For Carry Enable And Constant" bitfld.word 0x00 15. " PLD1_MC3_DFF_C ,PLD1 MC3 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 14. " PLD1_MC3_CEN ,PLD1 MC3 carry enable" "Disabled,Enabled" bitfld.word 0x00 13. " PLD1_MC2_DFF_C ,PLD1 MC2 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 12. " PLD1_MC2_CEN ,PLD1 MC2 carry enable" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " PLD1_MC1_DFF_C ,PLD1 MC1 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 10. " PLD1_MC1_CEN ,PLD1 MC1 carry enable" "Disabled,Enabled" bitfld.word 0x00 9. " PLD1_MC0_DFF_C ,PLD1 MC0 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 8. " PLD1_MC0_CEN ,PLD1 MC0 carry enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " PLD0_MC3_DFF_C ,PLD0 MC3 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 6. " PLD0_MC3_CEN ,PLD0 MC3 carry enable" "Disabled,Enabled" bitfld.word 0x00 5. " PLD0_MC2_DFF_C ,PLD0 MC2 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 4. " PLD0_MC2_CEN ,PLD0 MC2 carry enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " PLD0_MC1_DFF_C ,PLD0 MC1 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 2. " PLD0_MC1_CEN ,PLD0 MC1 carry enable" "Disabled,Enabled" bitfld.word 0x00 1. " PLD0_MC0_DFF_C ,PLD0 MC0 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 0. " PLD0_MC0_CEN ,PLD0_MC0 carry enable" "Disabled,Enabled" line.word 0x02 "PLD_MC_CFG_XORFB,PLD Macro Cell XOR Feedback" bitfld.word 0x02 14.--15. " PLD1_MC3_XORFB ,PLD1 MC3 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" bitfld.word 0x02 12.--13. " PLD1_MC2_XORFB ,PLD1 MC2 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" bitfld.word 0x02 10.--11. " PLD1_MC1_XORFB ,PLD1 MC1 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" bitfld.word 0x02 8.--9. " PLD1_MC0_XORFB ,PLD1 MC0 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" textline " " bitfld.word 0x02 6.--7. " PLD0_MC3_XORFB ,PLD0 MC3 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" bitfld.word 0x02 4.--5. " PLD0_MC2_XORFB ,PLD0 MC2 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" bitfld.word 0x02 2.--3. " PLD0_MC1_XORFB ,PLD0 MC1 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" bitfld.word 0x02 0.--1. " PLD0_MC0_XORFB ,PLD0 MC0 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" line.word 0x04 "PLD_MC_SET_RESET,PLD Macro Cell Set Reset Selection" bitfld.word 0x04 15. " PLD1_MC3_RESET_SEL ,PLD1 MC3 reset select enable" "Disabled,Enabled" bitfld.word 0x04 14. " PLD1_MC3_SET_SEL ,PLD1 MC3 set select enable" "Disabled,Enabled" bitfld.word 0x04 13. " PLD1_MC2_RESET_SEL ,PLD1 MC2 reset select enable" "Disabled,Enabled" bitfld.word 0x04 12. " PLD1_MC2_SET_SEL ,PLD1 MC2 set select enable" "Disabled,Enabled" textline " " bitfld.word 0x04 11. " PLD1_MC1_RESET_SEL ,PLD1 MC1 reset select enable" "Disabled,Enabled" bitfld.word 0x04 10. " PLD1_MC1_SET_SEL ,PLD1 MC0 set select enable" "Disabled,Enabled" bitfld.word 0x04 9. " PLD1_MC0_RESET_SEL ,PLD1 MC0 reset select enable" "Disabled,Enabled" bitfld.word 0x04 8. " PLD1_MC0_SET_SEL ,PLD1 MC0 set select enable" "Disabled,Enabled" textline " " bitfld.word 0x04 7. " PLD0_MC3_RESET_SEL ,PLD0 MC3 reset select enable" "Disabled,Enabled" bitfld.word 0x04 6. " PLD0_MC3_SET_SEL ,PLD0 MC3 set select enable" "Disabled,Enabled" bitfld.word 0x04 5. " PLD0_MC2_RESET_SEL ,PLD0 MC2 reset select enable" "Disabled,Enabled" bitfld.word 0x04 4. " PLD0_MC2_SET_SEL ,PLD0 MC2 set select enable" "Disabled,Enabled" textline " " bitfld.word 0x04 3. " PLD0_MC1_RESET_SEL ,PLD0 MC1 reset select enable" "Disabled,Enabled" bitfld.word 0x04 2. " PLD0_MC1_SET_SEL ,PLD0 MC1 set select enable" "Disabled,Enabled" bitfld.word 0x04 1. " PLD0_MC0_RESET_SEL ,Reset select enable" "Disabled,Enabled" bitfld.word 0x04 0. " PLD0_MC0_SET_SEL ,PLD0 MC0 set select enable" "Disabled,Enabled" line.word 0x06 "PLD_MC_CFG_BYPASS,PLD Macro Cell Bypass Control" bitfld.word 0x06 15. " NC15 ,Spare register bit NC15" "0,1" bitfld.word 0x06 14. " PLD1_MC3_BYPASS ,PLD1 MC3 bypass selection" "REGISTER,COMBINATIONAL" bitfld.word 0x06 13. " NC13 ,Spare register bit NC13" "0,1" bitfld.word 0x06 12. " PLD1_MC2_BYPASS ,PLD1 MC2 bypass selection" "REGISTER,COMBINATIONAL" textline " " bitfld.word 0x06 11. " NC11 ,Spare register bit NC11" "0,1" bitfld.word 0x06 10. " PLD1_MC1_BYPASS ,PLD1 MC1 bypass selection" "REGISTER,COMBINATIONAL" bitfld.word 0x06 9. " NC9 ,Spare register bit NC9" "0,1" bitfld.word 0x06 8. " PLD1_MC0_BYPASS ,PLD1 MC0 bypass selection" "REGISTER,COMBINATIONAL" textline " " bitfld.word 0x06 7. " NC7 ,Spare register bit NC7" "0,1" bitfld.word 0x06 6. " PLD0_MC3_BYPASS ,PLD0 MC3 bypass selection" "REGISTER,COMBINATIONAL" bitfld.word 0x06 5. " NC5 ,Spare register bit NC5" "0,1" bitfld.word 0x06 4. " PLD0_MC2_BYPASS ,PLD0 MC2 bypass selection" "REGISTER,COMBINATIONAL" textline " " bitfld.word 0x06 3. " NC3 ,Spare register bit NC3" "0,1" bitfld.word 0x06 2. " PLD0_MC1_BYPASS ,PLD0 MC1 bypass selection" "REGISTER,COMBINATIONAL" bitfld.word 0x06 1. " NC1 ,Spare register bit NC1" "0,1" bitfld.word 0x06 0. " PLD0_MC0_BYPASS ,PLD0 MC0 bypass selection" "REGISTER,COMBINATIONAL" group.byte 0x40++0x17 line.byte 0x00 "CFG0,Datapath Input Selection - RAD1 RAD0. Address Bits 0 And 1 To The Dynamic Configuration RAM" bitfld.byte 0x00 4.--6. " RAD1 ,Datapath permutable input mux RAD1" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." bitfld.byte 0x00 0.--2. " RAD0 ,Datapath permutable input mux RAD0" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." line.byte 0x01 "CFG1,Datapath Input Selection - RAD2. Address Bit 2 To The Dynamic Configuration RAM" bitfld.byte 0x01 7. " DP_RTE_BYPASS4 ,Dp_in bypass control 4" "DP_IN4_ROUTE,DP_IN4_BYPASS" bitfld.byte 0x01 6. " DP_RTE_BYPASS3 ,Dp_in bypass control 3" "DP_IN3_ROUTE,DP_IN3_BYPASS" bitfld.byte 0x01 5. " DP_RTE_BYPASS2 ,Dp_in bypass control 2" "DP_IN2_ROUTE,DP_IN2_BYPASS" bitfld.byte 0x01 4. " DP_RTE_BYPASS1 ,Dp_in bypass control 1" "DP_IN1_ROUTE,DP_IN1_BYPASS" textline " " bitfld.byte 0x01 3. " DP_RTE_BYPASS0 ,Dp_in bypass control 0" "DP_IN0_ROUTE,DP_IN0_BYPASS" bitfld.byte 0x01 0.--2. " RAD2 ,Datapath permutable input mux 2" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." line.byte 0x02 "CFG2,Datapath Input Selection - F1_LD, F0_LD" bitfld.byte 0x02 7. " NC7 ,Spare register bit NC7" "0,1" bitfld.byte 0x02 4.--6. " F1_LD ,Datapath permutable input mux F1_LD" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." bitfld.byte 0x02 3. " DP_RTE_BYPASS5 ,Dp_in bypass control 5" "DP_IN5_ROUTE,DP_IN5_BYPASS" bitfld.byte 0x02 0.--2. " F0_LD ,Datapath permutable input mux F0_LD" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." line.byte 0x03 "CFG3,Datapath Input Selection - D1_LD, D0_LD" bitfld.byte 0x03 4.--6. " D1_LD ,Datapath permutable input mux D1_LD" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." bitfld.byte 0x03 0.--2. " D0_LD ,Datapath permutable input mux D0_LD" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." line.byte 0x04 "CFG4,Datapath Input Selection - CI_MUX SI_MUX" bitfld.byte 0x04 4.--6. " CI_MUX ,Datapath permutable input mux CI_MUX" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." bitfld.byte 0x04 0.--2. " SI_MUX ,Datapath permutable input mux SI_MUX" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." line.byte 0x05 "CFG5,Datapath Output Selection For OUT1 OUT0" bitfld.byte 0x05 4.--7. " OUT1 ,Datapath permutable output mux OUT1" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT" bitfld.byte 0x05 0.--3. " OUT0 ,Datapath permutable output mux OUT0" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT" line.byte 0x06 "CFG6,Datapath Output Selection For OUT3 OUT2" bitfld.byte 0x06 4.--7. " OUT3 ,Datapath permutable output mux OUT3" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT" bitfld.byte 0x06 0.--3. " OUT2 ,Datapath permutable output mux OUT2" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT" line.byte 0x07 "CFG7,Datapath Output Selection For OUT5 OUT4" bitfld.byte 0x07 4.--7. " OUT5 ,Datapath permutable output mux OUT5" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT" bitfld.byte 0x07 0.--3. " OUT4 ,Datapath permutable output mux OUT4" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT" line.byte 0x08 "CFG8,Datapath Output Synchronization Option" bitfld.byte 0x08 7. " NC7 ,Spare register bit NC7" "0,1" bitfld.byte 0x08 6. " NC6 ,Spare register bit NC6" "0,1" bitfld.byte 0x08 0.--5. " OUT_SYNC ,Datapath output synchronization" "REGISTERED,COMBINATIONAL,?..." line.byte 0x09 "CFG9,Datapath ALU Mask" line.byte 0x0A "CFG10,Datapath Compare 0 Mask" line.byte 0x0B "CFG11,Datapath Compare 1 Mask" line.byte 0x0C "CFG12,Datapath Mask Enables And Shift In Configuration" bitfld.byte 0x0C 7. " CMASK1_EN ,Datapath mask CMASK1 enable" "Disabled,Enabled" bitfld.byte 0x0C 6. " CMASK0_EN ,Datapath mask CMASK0 enable" "Disabled,Enabled" bitfld.byte 0x0C 5. " AMASK_EN ,Datapath mask AMASK enable" "Disabled,Enabled" bitfld.byte 0x0C 4. " DEF_SI ,Datapath default shift value" "DEFAULT_0,DEFAULT_1" textline " " bitfld.byte 0x0C 2.--3. " SI_SELB ,Datapath shift in source select" "DEFAULT,REGISTERED,ROUTE,CHAIN" bitfld.byte 0x0C 0.--1. " SI_SELA ,Datapath shift in source select" "DEFAULT,REGISTERED,ROUTE,CHAIN" line.byte 0x0D "CFG13,Datapath Carry In And Compare Configuration" bitfld.byte 0x0D 6.--7. " CMP_SELB ,Datapath compare select B" "A1_D1,A1_A0,A0_D1,A0_A0" bitfld.byte 0x0D 4.--5. " CMP_SELA ,Datapath compare select A" "A1_D1,A1_A0,A0_D1,A0_A0" bitfld.byte 0x0D 2.--3. " CI_SELB ,Datapath carry in source select B" "DEFAULT,REGISTERED,ROUTE,CHAIN" bitfld.byte 0x0D 0.--1. " CI_SELA ,Datapath carry in source select A" "DEFAULT,REGISTERED,ROUTE,CHAIN" line.byte 0x0E "CFG14,Datapath Chaining And MSB Configuration" bitfld.byte 0x0E 7. " MSB_EN ,Datapath MSB selection enable" "Disabled,Enabled" bitfld.byte 0x0E 4.--6. " MSB_SEL ,Datapath MSB selection" "BIT0,BIT1,BIT2,BIT3,BIT4,BIT5,BIT6,BIT7" bitfld.byte 0x0E 3. " CHAIN_CMSB ,Datapath CRC MSB chaining enable" "Disabled,Enabled" bitfld.byte 0x0E 2. " CHAIN_FB ,Datapath CRC feedback chaining enable" "Disabled,Enabled" textline " " bitfld.byte 0x0E 1. " CHAIN1 ,Datapath condition chaining enable 1" "Disabled,Enabled" bitfld.byte 0x0E 0. " CHAIN0 ,Datapath condition chaining enable 0" "Disabled,Enabled" line.byte 0x0F "CFG15,Datapath FIFO, Shift And Parallel Input Control" bitfld.byte 0x0F 7. " PI_SEL ,Datapath parallel input selection" "NORMAL,PARALLEL" bitfld.byte 0x0F 6. " SHIFT_SEL ,Datapath shift out selection" "SOL_MSB,SOR" bitfld.byte 0x0F 5. " PI_DYN ,Enable for dynamic control of parallel data input (Pi) mux" "Disabled,Enabled" bitfld.byte 0x0F 4. " MSB_SI ,Arithmetic shift right operation shift in selection" "DEFAULT,MSB" textline " " bitfld.byte 0x0F 2.--3. " F1_INSEL ,Datapath FIFO configuration 1" "INPUT,OUTPUT_A0,OUTPUT_A1,OUTPUT_ALU" bitfld.byte 0x0F 0.--1. " F0_INSEL ,Datapath FIFO configuration 0" "INPUT,OUTPUT_A0,OUTPUT_A1,OUTPUT_ALU" line.byte 0x10 "CFG16,Datapath FIFO And Register Access Configuration Control" bitfld.byte 0x10 7. " F1_CK_INV ,FIFO 1 clock Inverted" "NORMAL,Inverted" bitfld.byte 0x10 6. " F0_CK_INV ,FIFO 0 clock Inverted" "NORMAL,Inverted" bitfld.byte 0x10 5. " FIFO_FAST ,FIFO fast mode" "Disabled,Enabled" bitfld.byte 0x10 4. " FIFO_CAP ,FIFO software capture mode" "Disabled,Enabled" textline " " bitfld.byte 0x10 3. " FIFO_EDGE ,Edge/level sensitive FIFO write control (Fx_ld)" "LEVEL,EDGE" bitfld.byte 0x10 2. " FIFO_ASYNC ,Asynchronous FIFO clocking support" "Disabled,Enabled" bitfld.byte 0x10 1. " EXT_CRCPRS ,External CRC/PRS mode" "INTERNAL,EXTERNAL" bitfld.byte 0x10 0. " WRK16_CONCAT ,Datapath register access mode" "DEFAULT,CONCATENATE" line.byte 0x11 "CFG17,Datapath FIFO Control" bitfld.byte 0x11 4. " FIFO_ADD_SYNC ,Sync flip-flop to FIFO block status" "Disabled,Enabled" bitfld.byte 0x11 3. " NC3 ,Spare register bit NC3" "0,1" bitfld.byte 0x11 2. " NC2 ,Spare register bit NC2" "0,1" bitfld.byte 0x11 1. " F1_DYN ,FIFO 1 direction" "STATIC,DYNAMIC" textline " " bitfld.byte 0x11 0. " F0_DYN ,FIFO 0 direction" "STATIC,DYNAMIC" line.byte 0x12 "CFG18,Control Register Mode 0" line.byte 0x13 "CFG19,Control Register Mode 1" line.byte 0x14 "CFG20,Status Register Input Mode Selection" bitfld.byte 0x14 7. " STAT_MD[7] ,Bit 7 status input mode select" "Transparent,Sticky cleared" bitfld.byte 0x14 6. " [6] ,Bit 6 status input mode select" "Transparent,Sticky cleared" bitfld.byte 0x14 5. " [5] ,Bit 5 status input mode select" "Transparent,Sticky cleared" bitfld.byte 0x14 4. " [4] ,Bit 4 status input mode select" "Transparent,Sticky cleared" textline " " bitfld.byte 0x14 3. " [3] ,Bit 3 status input mode select" "Transparent,Sticky cleared" bitfld.byte 0x14 2. " [2] ,Bit 2 status input mode select" "Transparent,Sticky cleared" bitfld.byte 0x14 1. " [1] ,Bit 1 status input mode select" "Transparent,Sticky cleared" bitfld.byte 0x14 0. " [0] ,Bit 0 status input mode select" "Transparent,Sticky cleared" line.byte 0x15 "CFG21,Spare Register Bits" bitfld.byte 0x15 1. " NC1 ,Spare register bit NC1" "0,1" bitfld.byte 0x15 0. " NC0 ,Spare register bit NC0" "0,1" line.byte 0x16 "CFG22,SC Block Configuration Control" bitfld.byte 0x16 4. " SC_EXT_RES ,Control register external reset operation" "Disabled,Enabled" bitfld.byte 0x16 3. " SC_SYNC_MD ,SC sync mode" "NORMAL,SYNC_MODE" bitfld.byte 0x16 2. " SC_INT_MD ,SC interrupt mode" "NORMAL,INT_MODE" bitfld.byte 0x16 0.--1. " SC_OUT_CTL ,Output source for the status and control routing connections" "CONTROL,PARALLEL,COUNTER,?..." line.byte 0x17 "CFG23,Counter Control" bitfld.byte 0x17 6. " ALT_CNT ,Alternate operating mode of the counter" "DEFAULT_MODE,ALT_MODE" bitfld.byte 0x17 5. " ROUTE_EN ,Counter enable signal for routing input" "Disabled,Enabled" bitfld.byte 0x17 4. " ROUTE_LD ,Counter load signal for routing input" "Disabled,Enabled" bitfld.byte 0x17 2.--3. " CNT_EN_SEL ,Routing inputs for the counter enable signal" "SC_IN4,SC_IN5,SC_IN6,SC_IO" textline " " bitfld.byte 0x17 0.--1. " CNT_LD_SEL ,Routing inputs for the counter load signal" "SC_IN0,SC_IN1,SC_IN2,SC_IN3" if (((per.b(ad:0x400F3600+0x5F))&0x01)==0x01) group.byte 0x58++0x03 line.byte 0x00 "CFG24,PLD0 Clock And Reset Control" bitfld.byte 0x00 6.--7. " RC_RES_SEL ,Routed reset for the associated UDB component block" "0,1,2,3" bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x00 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x00 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x00 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x01 "CFG25,PLD1 Clock And Reset Control" bitfld.byte 0x00 6.--7. " RC_RES_SEL ,Routed reset for the associated UDB component block" "0,1,2,3" bitfld.byte 0x01 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x01 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x01 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x01 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x02 "CFG26,Datapath Clock And Reset Control" bitfld.byte 0x00 6.--7. " RC_RES_SEL ,Routed reset for the associated UDB component block" "0,1,2,3" bitfld.byte 0x02 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x02 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x02 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x02 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x03 "CFG27,Status/control Clock And Reset Control" bitfld.byte 0x00 6.--7. " RC_RES_SEL ,Routed reset for the associated UDB component block" "0,1,2,3" bitfld.byte 0x03 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x03 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x03 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x03 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" else group.byte 0x58++0x03 line.byte 0x00 "CFG24,PLD0 Clock And Reset Control" bitfld.byte 0x00 6. " FRES ,Firmware reset for the associated UDB component block" "No reset,Reset" bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x00 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x00 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x00 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x01 "CFG25,PLD1 Clock And Reset Control" bitfld.byte 0x00 6. " FRES ,Firmware reset for the associated UDB component block" "No reset,Reset" bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x00 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x00 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x00 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x02 "CFG26,Datapath Clock And Reset Control" bitfld.byte 0x00 6. " FRES ,Firmware reset for the associated UDB component block" "No reset,Reset" bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x00 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x00 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x00 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x03 "CFG27,Status/control Clock And Reset Control" rbitfld.byte 0x00 6. " FRES ,Firmware reset for the associated UDB component block" "No reset,Reset" bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x03 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x03 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x03 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" endif group.byte 0x5C++0x01 line.byte 0x00 "CFG28,Clock Selection For PLD1 And PLD0" bitfld.byte 0x00 4.--7. " PLD1_CK_SEL ,PLD1 clock selection registers" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,EXT_CLK,SYSCLK,?..." bitfld.byte 0x00 0.--3. " PLD0_CK_SEL ,PLD0 clock selection registers" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,EXT_CLK,SYSCLK,?..." line.byte 0x01 "CFG29,Clock Selection For Datapath, Status And Control" bitfld.byte 0x01 4.--7. " SC_CK_SEL ,SC clock selection registers" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,EXT_CLK,SYSCLK,?..." bitfld.byte 0x01 0.--3. " DP_CK_SEL ,DP clock selection registers" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,EXT_CLK,SYSCLK,?..." if (((per.b(ad:0x400F3600+0x5F))&0x01)==0x01) group.byte 0x5E++0x01 line.byte 0x00 "CFG30,Reset Control" bitfld.byte 0x00 7. " SC_RES_POL ,Polarity of the selected SC routed reset" "Not inverted,Inverted" bitfld.byte 0x00 6. " DP_RES_POL ,Polarity of the selected datapath routed reset" "Not inverted,Inverted" bitfld.byte 0x00 4. " GUDB_WR ,Global write operation for the configuration and working registers UDB" "Disabled,Enabled" bitfld.byte 0x00 3. " EN_RES_CNTCTL ,Routed reset to the counter/control register" "Disabled,Enabled" textline " " rbitfld.byte 0x00 2. " RES_POL ,Polarity of the routed reset" "NEGATED,ASSERTED" rbitfld.byte 0x00 0.--1. " RES_SEL ,RC routing input for the compatible reset scheme" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x01 "CFG31,Reset Control" bitfld.byte 0x01 7. " PLD1_RES_POL ,Polarity of the routed reset for both plds" "Not inverted,Inverted" bitfld.byte 0x01 6. " PLD0_RES_POL ,Polarity of the routed reset for both plds" "Not inverted,Inverted" bitfld.byte 0x01 4.--5. " EXT_CK_SEL ,External clock selection" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" bitfld.byte 0x01 3. " EN_RES_DP ,Routed reset to the datapath block" "Disabled,Enabled" textline " " bitfld.byte 0x01 2. " EN_RES_STAT ,Routed reset to the status register" "NEGATED,ASSERTED" bitfld.byte 0x01 1. " EXT_SYNC ,Synchronization of selected external clock" "Disabled,Enabled" bitfld.byte 0x01 0. " ALT_RES ,Toggles between two reset configurations" "COMPATIBLE,ALTERNATE" else group.byte 0x5E++0x01 line.byte 0x00 "CFG30,Reset Control" rbitfld.byte 0x00 7. " SC_RES_POL ,Polarity of the selected SC routed reset" "Not inverted,Inverted" rbitfld.byte 0x00 6. " DP_RES_POL ,Polarity of the selected datapath routed reset" "Not inverted,Inverted" bitfld.byte 0x00 4. " GUDB_WR ,Global write operation for the configuration and working registers UDB" "Disabled,Enabled" bitfld.byte 0x00 3. " EN_RES_CNTCTL ,Routed reset to the counter/control register" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " RES_POL ,Polarity of the routed reset" "NEGATED,ASSERTED" bitfld.byte 0x00 0.--1. " RES_SEL ,RC routing input for the compatible reset scheme" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x01 "CFG31,Reset Control" bitfld.byte 0x01 7. " PLD1_RES_POL ,Polarity of the routed reset for both plds" "Not inverted,Inverted" bitfld.byte 0x01 6. " PLD0_RES_POL ,Polarity of the routed reset for both plds" "Not inverted,Inverted" bitfld.byte 0x01 4.--5. " EXT_CK_SEL ,External clock selection" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" rbitfld.byte 0x01 3. " EN_RES_DP ,Routed reset to the datapath block" "Disabled,Enabled" textline " " rbitfld.byte 0x01 2. " EN_RES_STAT ,Routed reset to the status register" "NEGATED,ASSERTED" bitfld.byte 0x01 1. " EXT_SYNC ,Synchronization of selected external clock" "Disabled,Enabled" bitfld.byte 0x01 0. " ALT_RES ,Toggles between two reset configurations" "COMPATIBLE,ALTERNATE" endif group.word 0x60++0x01 line.word 0x00 "DCFG0,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x62++0x01 line.word 0x00 "DCFG1,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x64++0x01 line.word 0x00 "DCFG2,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x66++0x01 line.word 0x00 "DCFG3,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x68++0x01 line.word 0x00 "DCFG4,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x6A++0x01 line.word 0x00 "DCFG5,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x6C++0x01 line.word 0x00 "DCFG6,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x6E++0x01 line.word 0x00 "DCFG7,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" width 0x0B tree.end tree "UDB P3 U1" base ad:0x400F3680 width 22. group.long 0x0++0x03 line.long 0x00 "PLD_IT0,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT0T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT0T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT0T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT0T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT0T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT0T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT0T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT0T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT0T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT0T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT0T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT0T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT0T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT0T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT0T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT0T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT0C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT0C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT0C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT0C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT0C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT0C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT0C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT0C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT0C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT0C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT0C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT0C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT0C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT0C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT0C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT0C_0 ,PLD0 complement input term 0" "0,1" group.long 0x4++0x03 line.long 0x00 "PLD_IT1,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT1T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT1T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT1T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT1T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT1T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT1T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT1T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT1T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT1T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT1T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT1T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT1T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT1T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT1T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT1T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT1T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT1C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT1C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT1C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT1C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT1C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT1C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT1C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT1C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT1C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT1C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT1C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT1C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT1C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT1C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT1C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT1C_0 ,PLD0 complement input term 0" "0,1" group.long 0x8++0x03 line.long 0x00 "PLD_IT2,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT2T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT2T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT2T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT2T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT2T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT2T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT2T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT2T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT2T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT2T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT2T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT2T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT2T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT2T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT2T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT2T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT2C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT2C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT2C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT2C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT2C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT2C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT2C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT2C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT2C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT2C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT2C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT2C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT2C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT2C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT2C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT2C_0 ,PLD0 complement input term 0" "0,1" group.long 0xC++0x03 line.long 0x00 "PLD_IT3,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT3T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT3T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT3T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT3T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT3T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT3T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT3T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT3T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT3T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT3T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT3T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT3T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT3T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT3T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT3T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT3T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT3C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT3C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT3C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT3C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT3C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT3C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT3C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT3C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT3C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT3C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT3C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT3C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT3C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT3C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT3C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT3C_0 ,PLD0 complement input term 0" "0,1" group.long 0x10++0x03 line.long 0x00 "PLD_IT4,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT4T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT4T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT4T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT4T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT4T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT4T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT4T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT4T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT4T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT4T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT4T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT4T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT4T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT4T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT4T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT4T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT4C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT4C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT4C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT4C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT4C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT4C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT4C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT4C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT4C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT4C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT4C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT4C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT4C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT4C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT4C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT4C_0 ,PLD0 complement input term 0" "0,1" group.long 0x14++0x03 line.long 0x00 "PLD_IT5,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT5T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT5T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT5T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT5T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT5T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT5T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT5T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT5T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT5T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT5T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT5T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT5T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT5T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT5T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT5T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT5T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT5C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT5C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT5C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT5C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT5C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT5C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT5C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT5C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT5C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT5C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT5C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT5C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT5C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT5C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT5C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT5C_0 ,PLD0 complement input term 0" "0,1" group.long 0x18++0x03 line.long 0x00 "PLD_IT6,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT6T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT6T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT6T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT6T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT6T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT6T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT6T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT6T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT6T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT6T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT6T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT6T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT6T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT6T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT6T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT6T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT6C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT6C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT6C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT6C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT6C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT6C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT6C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT6C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT6C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT6C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT6C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT6C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT6C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT6C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT6C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT6C_0 ,PLD0 complement input term 0" "0,1" group.long 0x1C++0x03 line.long 0x00 "PLD_IT7,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT7T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT7T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT7T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT7T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT7T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT7T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT7T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT7T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT7T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT7T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT7T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT7T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT7T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT7T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT7T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT7T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT7C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT7C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT7C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT7C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT7C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT7C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT7C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT7C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT7C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT7C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT7C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT7C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT7C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT7C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT7C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT7C_0 ,PLD0 complement input term 0" "0,1" group.long 0x20++0x03 line.long 0x00 "PLD_IT8,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT8T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT8T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT8T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT8T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT8T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT8T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT8T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT8T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT8T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT8T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT8T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT8T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT8T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT8T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT8T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT8T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT8C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT8C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT8C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT8C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT8C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT8C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT8C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT8C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT8C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT8C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT8C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT8C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT8C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT8C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT8C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT8C_0 ,PLD0 complement input term 0" "0,1" group.long 0x24++0x03 line.long 0x00 "PLD_IT9,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT9T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT9T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT9T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT9T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT9T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT9T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT9T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT9T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT9T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT9T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT9T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT9T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT9T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT9T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT9T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT9T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT9C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT9C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT9C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT9C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT9C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT9C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT9C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT9C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT9C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT9C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT9C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT9C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT9C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT9C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT9C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT9C_0 ,PLD0 complement input term 0" "0,1" group.long 0x28++0x03 line.long 0x00 "PLD_IT10,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT10T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT10T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT10T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT10T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT10T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT10T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT10T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT10T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT10T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT10T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT10T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT10T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT10T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT10T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT10T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT10T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT10C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT10C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT10C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT10C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT10C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT10C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT10C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT10C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT10C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT10C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT10C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT10C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT10C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT10C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT10C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT10C_0 ,PLD0 complement input term 0" "0,1" group.long 0x2C++0x03 line.long 0x00 "PLD_IT11,PLD Input Terms" bitfld.long 0x00 31. " PLD1_IT11T_7 ,PLD1 true input term 7" "0,1" bitfld.long 0x00 30. " PLD1_IT11T_6 ,PLD1 true input term 6" "0,1" bitfld.long 0x00 29. " PLD1_IT11T_5 ,PLD1 true input term 5" "0,1" bitfld.long 0x00 28. " PLD1_IT11T_4 ,PLD1 true input term 4" "0,1" textline " " bitfld.long 0x00 27. " PLD1_IT11T_3 ,PLD1 true input term 3" "0,1" bitfld.long 0x00 26. " PLD1_IT11T_2 ,PLD1 true input term 2" "0,1" bitfld.long 0x00 25. " PLD1_IT11T_1 ,PLD1 true input term 1" "0,1" bitfld.long 0x00 24. " PLD1_IT11T_0 ,PLD1 true input term 0" "0,1" textline " " bitfld.long 0x00 23. " PLD0_IT11T_7 ,PLD0 true input term 7" "0,1" bitfld.long 0x00 22. " PLD0_IT11T_6 ,PLD0 true input term 6" "0,1" bitfld.long 0x00 21. " PLD0_IT11T_5 ,PLD0 true input term 5" "0,1" bitfld.long 0x00 20. " PLD0_IT11T_4 ,PLD0 true input term 4" "0,1" textline " " bitfld.long 0x00 19. " PLD0_IT11T_3 ,PLD0 true input term 3" "0,1" bitfld.long 0x00 18. " PLD0_IT11T_2 ,PLD0 true input term 2" "0,1" bitfld.long 0x00 17. " PLD0_IT11T_1 ,PLD0 true input term 1" "0,1" bitfld.long 0x00 16. " PLD0_IT11T_0 ,PLD0 true input term 0" "0,1" textline " " bitfld.long 0x00 15. " PLD1_IT11C_7 ,PLD1 complement input term 7" "0,1" bitfld.long 0x00 14. " PLD1_IT11C_6 ,PLD1 complement input term 6" "0,1" bitfld.long 0x00 13. " PLD1_IT11C_5 ,PLD1 complement input term 5" "0,1" bitfld.long 0x00 12. " PLD1_IT11C_4 ,PLD1 complement input term 4" "0,1" textline " " bitfld.long 0x00 11. " PLD1_IT11C_3 ,PLD1 complement input term 3" "0,1" bitfld.long 0x00 10. " PLD1_IT11C_2 ,PLD1 complement input term 2" "0,1" bitfld.long 0x00 9. " PLD1_IT11C_1 ,PLD1 complement input term 1" "0,1" bitfld.long 0x00 8. " PLD1_IT11C_0 ,PLD1 complement input term 0" "0,1" textline " " bitfld.long 0x00 7. " PLD0_IT11C_7 ,PLD0 complement input term 7" "0,1" bitfld.long 0x00 6. " PLD0_IT11C_6 ,PLD0 complement input term 6" "0,1" bitfld.long 0x00 5. " PLD0_IT11C_5 ,PLD0 complement input term 5" "0,1" bitfld.long 0x00 4. " PLD0_IT11C_4 ,PLD0 complement input term 4" "0,1" textline " " bitfld.long 0x00 3. " PLD0_IT11C_3 ,PLD0 complement input term 3" "0,1" bitfld.long 0x00 2. " PLD0_IT11C_2 ,PLD0 complement input term 2" "0,1" bitfld.long 0x00 1. " PLD0_IT11C_1 ,PLD0 complement input term 1" "0,1" bitfld.long 0x00 0. " PLD0_IT11C_0 ,PLD0 complement input term 0" "0,1" group.word 0x30++0x01 line.word 0x00 "PLD_ORT0,PLD OR Terms" bitfld.word 0x00 15. " PLD1_ORT_PT0_7 ,PLD1 OR term 7" "0,1" bitfld.word 0x00 14. " PLD1_ORT_PT0_6 ,PLD1 OR term 6" "0,1" bitfld.word 0x00 13. " PLD1_ORT_PT0_5 ,PLD1 OR term 5" "0,1" bitfld.word 0x00 12. " PLD1_ORT_PT0_4 ,PLD1 OR term 4" "0,1" textline " " bitfld.word 0x00 11. " PLD1_ORT_PT0_3 ,PLD1 OR term 3" "0,1" bitfld.word 0x00 10. " PLD1_ORT_PT0_2 ,PLD1 OR term 2" "0,1" bitfld.word 0x00 9. " PLD1_ORT_PT0_1 ,PLD1 OR term 1" "0,1" bitfld.word 0x00 8. " PLD1_ORT_PT0_0 ,PLD1 OR term 0" "0,1" textline " " bitfld.word 0x00 7. " PLD0_ORT_PT0_7 ,PLD0 OR term 7" "0,1" bitfld.word 0x00 6. " PLD0_ORT_PT0_6 ,PLD0 OR term 6" "0,1" bitfld.word 0x00 5. " PLD0_ORT_PT0_5 ,PLD0 OR term 5" "0,1" bitfld.word 0x00 4. " PLD0_ORT_PT0_4 ,PLD0 OR term 4" "0,1" textline " " bitfld.word 0x00 3. " PLD0_ORT_PT0_3 ,PLD0 OR term 3" "0,1" bitfld.word 0x00 2. " PLD0_ORT_PT0_2 ,PLD0 OR term 2" "0,1" bitfld.word 0x00 1. " PLD0_ORT_PT0_1 ,PLD0 OR term 1" "0,1" bitfld.word 0x00 0. " PLD0_ORT_PT0_0 ,PLD0 OR term 0" "0,1" group.word 0x32++0x01 line.word 0x00 "PLD_ORT1,PLD OR Terms" bitfld.word 0x00 15. " PLD1_ORT_PT1_7 ,PLD1 OR term 7" "0,1" bitfld.word 0x00 14. " PLD1_ORT_PT1_6 ,PLD1 OR term 6" "0,1" bitfld.word 0x00 13. " PLD1_ORT_PT1_5 ,PLD1 OR term 5" "0,1" bitfld.word 0x00 12. " PLD1_ORT_PT1_4 ,PLD1 OR term 4" "0,1" textline " " bitfld.word 0x00 11. " PLD1_ORT_PT1_3 ,PLD1 OR term 3" "0,1" bitfld.word 0x00 10. " PLD1_ORT_PT1_2 ,PLD1 OR term 2" "0,1" bitfld.word 0x00 9. " PLD1_ORT_PT1_1 ,PLD1 OR term 1" "0,1" bitfld.word 0x00 8. " PLD1_ORT_PT1_0 ,PLD1 OR term 0" "0,1" textline " " bitfld.word 0x00 7. " PLD0_ORT_PT1_7 ,PLD0 OR term 7" "0,1" bitfld.word 0x00 6. " PLD0_ORT_PT1_6 ,PLD0 OR term 6" "0,1" bitfld.word 0x00 5. " PLD0_ORT_PT1_5 ,PLD0 OR term 5" "0,1" bitfld.word 0x00 4. " PLD0_ORT_PT1_4 ,PLD0 OR term 4" "0,1" textline " " bitfld.word 0x00 3. " PLD0_ORT_PT1_3 ,PLD0 OR term 3" "0,1" bitfld.word 0x00 2. " PLD0_ORT_PT1_2 ,PLD0 OR term 2" "0,1" bitfld.word 0x00 1. " PLD0_ORT_PT1_1 ,PLD0 OR term 1" "0,1" bitfld.word 0x00 0. " PLD0_ORT_PT1_0 ,PLD0 OR term 0" "0,1" group.word 0x34++0x01 line.word 0x00 "PLD_ORT2,PLD OR Terms" bitfld.word 0x00 15. " PLD1_ORT_PT2_7 ,PLD1 OR term 7" "0,1" bitfld.word 0x00 14. " PLD1_ORT_PT2_6 ,PLD1 OR term 6" "0,1" bitfld.word 0x00 13. " PLD1_ORT_PT2_5 ,PLD1 OR term 5" "0,1" bitfld.word 0x00 12. " PLD1_ORT_PT2_4 ,PLD1 OR term 4" "0,1" textline " " bitfld.word 0x00 11. " PLD1_ORT_PT2_3 ,PLD1 OR term 3" "0,1" bitfld.word 0x00 10. " PLD1_ORT_PT2_2 ,PLD1 OR term 2" "0,1" bitfld.word 0x00 9. " PLD1_ORT_PT2_1 ,PLD1 OR term 1" "0,1" bitfld.word 0x00 8. " PLD1_ORT_PT2_0 ,PLD1 OR term 0" "0,1" textline " " bitfld.word 0x00 7. " PLD0_ORT_PT2_7 ,PLD0 OR term 7" "0,1" bitfld.word 0x00 6. " PLD0_ORT_PT2_6 ,PLD0 OR term 6" "0,1" bitfld.word 0x00 5. " PLD0_ORT_PT2_5 ,PLD0 OR term 5" "0,1" bitfld.word 0x00 4. " PLD0_ORT_PT2_4 ,PLD0 OR term 4" "0,1" textline " " bitfld.word 0x00 3. " PLD0_ORT_PT2_3 ,PLD0 OR term 3" "0,1" bitfld.word 0x00 2. " PLD0_ORT_PT2_2 ,PLD0 OR term 2" "0,1" bitfld.word 0x00 1. " PLD0_ORT_PT2_1 ,PLD0 OR term 1" "0,1" bitfld.word 0x00 0. " PLD0_ORT_PT2_0 ,PLD0 OR term 0" "0,1" group.word 0x36++0x01 line.word 0x00 "PLD_ORT3,PLD OR Terms" bitfld.word 0x00 15. " PLD1_ORT_PT3_7 ,PLD1 OR term 7" "0,1" bitfld.word 0x00 14. " PLD1_ORT_PT3_6 ,PLD1 OR term 6" "0,1" bitfld.word 0x00 13. " PLD1_ORT_PT3_5 ,PLD1 OR term 5" "0,1" bitfld.word 0x00 12. " PLD1_ORT_PT3_4 ,PLD1 OR term 4" "0,1" textline " " bitfld.word 0x00 11. " PLD1_ORT_PT3_3 ,PLD1 OR term 3" "0,1" bitfld.word 0x00 10. " PLD1_ORT_PT3_2 ,PLD1 OR term 2" "0,1" bitfld.word 0x00 9. " PLD1_ORT_PT3_1 ,PLD1 OR term 1" "0,1" bitfld.word 0x00 8. " PLD1_ORT_PT3_0 ,PLD1 OR term 0" "0,1" textline " " bitfld.word 0x00 7. " PLD0_ORT_PT3_7 ,PLD0 OR term 7" "0,1" bitfld.word 0x00 6. " PLD0_ORT_PT3_6 ,PLD0 OR term 6" "0,1" bitfld.word 0x00 5. " PLD0_ORT_PT3_5 ,PLD0 OR term 5" "0,1" bitfld.word 0x00 4. " PLD0_ORT_PT3_4 ,PLD0 OR term 4" "0,1" textline " " bitfld.word 0x00 3. " PLD0_ORT_PT3_3 ,PLD0 OR term 3" "0,1" bitfld.word 0x00 2. " PLD0_ORT_PT3_2 ,PLD0 OR term 2" "0,1" bitfld.word 0x00 1. " PLD0_ORT_PT3_1 ,PLD0 OR term 1" "0,1" bitfld.word 0x00 0. " PLD0_ORT_PT3_0 ,PLD0 OR term 0" "0,1" group.word 0x38++0x07 line.word 0x00 "PLD_MC_CFG_CEN_CONST,Macrocell Configuration For Carry Enable And Constant" bitfld.word 0x00 15. " PLD1_MC3_DFF_C ,PLD1 MC3 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 14. " PLD1_MC3_CEN ,PLD1 MC3 carry enable" "Disabled,Enabled" bitfld.word 0x00 13. " PLD1_MC2_DFF_C ,PLD1 MC2 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 12. " PLD1_MC2_CEN ,PLD1 MC2 carry enable" "Disabled,Enabled" textline " " bitfld.word 0x00 11. " PLD1_MC1_DFF_C ,PLD1 MC1 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 10. " PLD1_MC1_CEN ,PLD1 MC1 carry enable" "Disabled,Enabled" bitfld.word 0x00 9. " PLD1_MC0_DFF_C ,PLD1 MC0 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 8. " PLD1_MC0_CEN ,PLD1 MC0 carry enable" "Disabled,Enabled" textline " " bitfld.word 0x00 7. " PLD0_MC3_DFF_C ,PLD0 MC3 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 6. " PLD0_MC3_CEN ,PLD0 MC3 carry enable" "Disabled,Enabled" bitfld.word 0x00 5. " PLD0_MC2_DFF_C ,PLD0 MC2 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 4. " PLD0_MC2_CEN ,PLD0 MC2 carry enable" "Disabled,Enabled" textline " " bitfld.word 0x00 3. " PLD0_MC1_DFF_C ,PLD0 MC1 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 2. " PLD0_MC1_CEN ,PLD0 MC1 carry enable" "Disabled,Enabled" bitfld.word 0x00 1. " PLD0_MC0_DFF_C ,PLD0 MC0 DFF constant" "Not inverted,Inverted" bitfld.word 0x00 0. " PLD0_MC0_CEN ,PLD0_MC0 carry enable" "Disabled,Enabled" line.word 0x02 "PLD_MC_CFG_XORFB,PLD Macro Cell XOR Feedback" bitfld.word 0x02 14.--15. " PLD1_MC3_XORFB ,PLD1 MC3 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" bitfld.word 0x02 12.--13. " PLD1_MC2_XORFB ,PLD1 MC2 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" bitfld.word 0x02 10.--11. " PLD1_MC1_XORFB ,PLD1 MC1 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" bitfld.word 0x02 8.--9. " PLD1_MC0_XORFB ,PLD1 MC0 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" textline " " bitfld.word 0x02 6.--7. " PLD0_MC3_XORFB ,PLD0 MC3 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" bitfld.word 0x02 4.--5. " PLD0_MC2_XORFB ,PLD0 MC2 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" bitfld.word 0x02 2.--3. " PLD0_MC1_XORFB ,PLD0 MC1 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" bitfld.word 0x02 0.--1. " PLD0_MC0_XORFB ,PLD0 MC0 XOR feedback" "DFF,CARRY,TFF_H,TFF_L" line.word 0x04 "PLD_MC_SET_RESET,PLD Macro Cell Set Reset Selection" bitfld.word 0x04 15. " PLD1_MC3_RESET_SEL ,PLD1 MC3 reset select enable" "Disabled,Enabled" bitfld.word 0x04 14. " PLD1_MC3_SET_SEL ,PLD1 MC3 set select enable" "Disabled,Enabled" bitfld.word 0x04 13. " PLD1_MC2_RESET_SEL ,PLD1 MC2 reset select enable" "Disabled,Enabled" bitfld.word 0x04 12. " PLD1_MC2_SET_SEL ,PLD1 MC2 set select enable" "Disabled,Enabled" textline " " bitfld.word 0x04 11. " PLD1_MC1_RESET_SEL ,PLD1 MC1 reset select enable" "Disabled,Enabled" bitfld.word 0x04 10. " PLD1_MC1_SET_SEL ,PLD1 MC0 set select enable" "Disabled,Enabled" bitfld.word 0x04 9. " PLD1_MC0_RESET_SEL ,PLD1 MC0 reset select enable" "Disabled,Enabled" bitfld.word 0x04 8. " PLD1_MC0_SET_SEL ,PLD1 MC0 set select enable" "Disabled,Enabled" textline " " bitfld.word 0x04 7. " PLD0_MC3_RESET_SEL ,PLD0 MC3 reset select enable" "Disabled,Enabled" bitfld.word 0x04 6. " PLD0_MC3_SET_SEL ,PLD0 MC3 set select enable" "Disabled,Enabled" bitfld.word 0x04 5. " PLD0_MC2_RESET_SEL ,PLD0 MC2 reset select enable" "Disabled,Enabled" bitfld.word 0x04 4. " PLD0_MC2_SET_SEL ,PLD0 MC2 set select enable" "Disabled,Enabled" textline " " bitfld.word 0x04 3. " PLD0_MC1_RESET_SEL ,PLD0 MC1 reset select enable" "Disabled,Enabled" bitfld.word 0x04 2. " PLD0_MC1_SET_SEL ,PLD0 MC1 set select enable" "Disabled,Enabled" bitfld.word 0x04 1. " PLD0_MC0_RESET_SEL ,Reset select enable" "Disabled,Enabled" bitfld.word 0x04 0. " PLD0_MC0_SET_SEL ,PLD0 MC0 set select enable" "Disabled,Enabled" line.word 0x06 "PLD_MC_CFG_BYPASS,PLD Macro Cell Bypass Control" bitfld.word 0x06 15. " NC15 ,Spare register bit NC15" "0,1" bitfld.word 0x06 14. " PLD1_MC3_BYPASS ,PLD1 MC3 bypass selection" "REGISTER,COMBINATIONAL" bitfld.word 0x06 13. " NC13 ,Spare register bit NC13" "0,1" bitfld.word 0x06 12. " PLD1_MC2_BYPASS ,PLD1 MC2 bypass selection" "REGISTER,COMBINATIONAL" textline " " bitfld.word 0x06 11. " NC11 ,Spare register bit NC11" "0,1" bitfld.word 0x06 10. " PLD1_MC1_BYPASS ,PLD1 MC1 bypass selection" "REGISTER,COMBINATIONAL" bitfld.word 0x06 9. " NC9 ,Spare register bit NC9" "0,1" bitfld.word 0x06 8. " PLD1_MC0_BYPASS ,PLD1 MC0 bypass selection" "REGISTER,COMBINATIONAL" textline " " bitfld.word 0x06 7. " NC7 ,Spare register bit NC7" "0,1" bitfld.word 0x06 6. " PLD0_MC3_BYPASS ,PLD0 MC3 bypass selection" "REGISTER,COMBINATIONAL" bitfld.word 0x06 5. " NC5 ,Spare register bit NC5" "0,1" bitfld.word 0x06 4. " PLD0_MC2_BYPASS ,PLD0 MC2 bypass selection" "REGISTER,COMBINATIONAL" textline " " bitfld.word 0x06 3. " NC3 ,Spare register bit NC3" "0,1" bitfld.word 0x06 2. " PLD0_MC1_BYPASS ,PLD0 MC1 bypass selection" "REGISTER,COMBINATIONAL" bitfld.word 0x06 1. " NC1 ,Spare register bit NC1" "0,1" bitfld.word 0x06 0. " PLD0_MC0_BYPASS ,PLD0 MC0 bypass selection" "REGISTER,COMBINATIONAL" group.byte 0x40++0x17 line.byte 0x00 "CFG0,Datapath Input Selection - RAD1 RAD0. Address Bits 0 And 1 To The Dynamic Configuration RAM" bitfld.byte 0x00 4.--6. " RAD1 ,Datapath permutable input mux RAD1" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." bitfld.byte 0x00 0.--2. " RAD0 ,Datapath permutable input mux RAD0" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." line.byte 0x01 "CFG1,Datapath Input Selection - RAD2. Address Bit 2 To The Dynamic Configuration RAM" bitfld.byte 0x01 7. " DP_RTE_BYPASS4 ,Dp_in bypass control 4" "DP_IN4_ROUTE,DP_IN4_BYPASS" bitfld.byte 0x01 6. " DP_RTE_BYPASS3 ,Dp_in bypass control 3" "DP_IN3_ROUTE,DP_IN3_BYPASS" bitfld.byte 0x01 5. " DP_RTE_BYPASS2 ,Dp_in bypass control 2" "DP_IN2_ROUTE,DP_IN2_BYPASS" bitfld.byte 0x01 4. " DP_RTE_BYPASS1 ,Dp_in bypass control 1" "DP_IN1_ROUTE,DP_IN1_BYPASS" textline " " bitfld.byte 0x01 3. " DP_RTE_BYPASS0 ,Dp_in bypass control 0" "DP_IN0_ROUTE,DP_IN0_BYPASS" bitfld.byte 0x01 0.--2. " RAD2 ,Datapath permutable input mux 2" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." line.byte 0x02 "CFG2,Datapath Input Selection - F1_LD, F0_LD" bitfld.byte 0x02 7. " NC7 ,Spare register bit NC7" "0,1" bitfld.byte 0x02 4.--6. " F1_LD ,Datapath permutable input mux F1_LD" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." bitfld.byte 0x02 3. " DP_RTE_BYPASS5 ,Dp_in bypass control 5" "DP_IN5_ROUTE,DP_IN5_BYPASS" bitfld.byte 0x02 0.--2. " F0_LD ,Datapath permutable input mux F0_LD" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." line.byte 0x03 "CFG3,Datapath Input Selection - D1_LD, D0_LD" bitfld.byte 0x03 4.--6. " D1_LD ,Datapath permutable input mux D1_LD" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." bitfld.byte 0x03 0.--2. " D0_LD ,Datapath permutable input mux D0_LD" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." line.byte 0x04 "CFG4,Datapath Input Selection - CI_MUX SI_MUX" bitfld.byte 0x04 4.--6. " CI_MUX ,Datapath permutable input mux CI_MUX" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." bitfld.byte 0x04 0.--2. " SI_MUX ,Datapath permutable input mux SI_MUX" "OFF,DP_IN0,DP_IN1,DP_IN2,DP_IN3,DP_IN4,DP_IN5,?..." line.byte 0x05 "CFG5,Datapath Output Selection For OUT1 OUT0" bitfld.byte 0x05 4.--7. " OUT1 ,Datapath permutable output mux OUT1" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT" bitfld.byte 0x05 0.--3. " OUT0 ,Datapath permutable output mux OUT0" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT" line.byte 0x06 "CFG6,Datapath Output Selection For OUT3 OUT2" bitfld.byte 0x06 4.--7. " OUT3 ,Datapath permutable output mux OUT3" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT" bitfld.byte 0x06 0.--3. " OUT2 ,Datapath permutable output mux OUT2" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT" line.byte 0x07 "CFG7,Datapath Output Selection For OUT5 OUT4" bitfld.byte 0x07 4.--7. " OUT5 ,Datapath permutable output mux OUT5" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT" bitfld.byte 0x07 0.--3. " OUT4 ,Datapath permutable output mux OUT4" "CE0,CL0,Z0,FF0,CE1,CL1,Z1,FF1,OV_MSB,CO_MSB,CMSBO,SO,F0_BLK_STAT,F1_BLK_STAT,F0_BUS_STAT,F1_BUS_STAT" line.byte 0x08 "CFG8,Datapath Output Synchronization Option" bitfld.byte 0x08 7. " NC7 ,Spare register bit NC7" "0,1" bitfld.byte 0x08 6. " NC6 ,Spare register bit NC6" "0,1" bitfld.byte 0x08 0.--5. " OUT_SYNC ,Datapath output synchronization" "REGISTERED,COMBINATIONAL,?..." line.byte 0x09 "CFG9,Datapath ALU Mask" line.byte 0x0A "CFG10,Datapath Compare 0 Mask" line.byte 0x0B "CFG11,Datapath Compare 1 Mask" line.byte 0x0C "CFG12,Datapath Mask Enables And Shift In Configuration" bitfld.byte 0x0C 7. " CMASK1_EN ,Datapath mask CMASK1 enable" "Disabled,Enabled" bitfld.byte 0x0C 6. " CMASK0_EN ,Datapath mask CMASK0 enable" "Disabled,Enabled" bitfld.byte 0x0C 5. " AMASK_EN ,Datapath mask AMASK enable" "Disabled,Enabled" bitfld.byte 0x0C 4. " DEF_SI ,Datapath default shift value" "DEFAULT_0,DEFAULT_1" textline " " bitfld.byte 0x0C 2.--3. " SI_SELB ,Datapath shift in source select" "DEFAULT,REGISTERED,ROUTE,CHAIN" bitfld.byte 0x0C 0.--1. " SI_SELA ,Datapath shift in source select" "DEFAULT,REGISTERED,ROUTE,CHAIN" line.byte 0x0D "CFG13,Datapath Carry In And Compare Configuration" bitfld.byte 0x0D 6.--7. " CMP_SELB ,Datapath compare select B" "A1_D1,A1_A0,A0_D1,A0_A0" bitfld.byte 0x0D 4.--5. " CMP_SELA ,Datapath compare select A" "A1_D1,A1_A0,A0_D1,A0_A0" bitfld.byte 0x0D 2.--3. " CI_SELB ,Datapath carry in source select B" "DEFAULT,REGISTERED,ROUTE,CHAIN" bitfld.byte 0x0D 0.--1. " CI_SELA ,Datapath carry in source select A" "DEFAULT,REGISTERED,ROUTE,CHAIN" line.byte 0x0E "CFG14,Datapath Chaining And MSB Configuration" bitfld.byte 0x0E 7. " MSB_EN ,Datapath MSB selection enable" "Disabled,Enabled" bitfld.byte 0x0E 4.--6. " MSB_SEL ,Datapath MSB selection" "BIT0,BIT1,BIT2,BIT3,BIT4,BIT5,BIT6,BIT7" bitfld.byte 0x0E 3. " CHAIN_CMSB ,Datapath CRC MSB chaining enable" "Disabled,Enabled" bitfld.byte 0x0E 2. " CHAIN_FB ,Datapath CRC feedback chaining enable" "Disabled,Enabled" textline " " bitfld.byte 0x0E 1. " CHAIN1 ,Datapath condition chaining enable 1" "Disabled,Enabled" bitfld.byte 0x0E 0. " CHAIN0 ,Datapath condition chaining enable 0" "Disabled,Enabled" line.byte 0x0F "CFG15,Datapath FIFO, Shift And Parallel Input Control" bitfld.byte 0x0F 7. " PI_SEL ,Datapath parallel input selection" "NORMAL,PARALLEL" bitfld.byte 0x0F 6. " SHIFT_SEL ,Datapath shift out selection" "SOL_MSB,SOR" bitfld.byte 0x0F 5. " PI_DYN ,Enable for dynamic control of parallel data input (Pi) mux" "Disabled,Enabled" bitfld.byte 0x0F 4. " MSB_SI ,Arithmetic shift right operation shift in selection" "DEFAULT,MSB" textline " " bitfld.byte 0x0F 2.--3. " F1_INSEL ,Datapath FIFO configuration 1" "INPUT,OUTPUT_A0,OUTPUT_A1,OUTPUT_ALU" bitfld.byte 0x0F 0.--1. " F0_INSEL ,Datapath FIFO configuration 0" "INPUT,OUTPUT_A0,OUTPUT_A1,OUTPUT_ALU" line.byte 0x10 "CFG16,Datapath FIFO And Register Access Configuration Control" bitfld.byte 0x10 7. " F1_CK_INV ,FIFO 1 clock Inverted" "NORMAL,Inverted" bitfld.byte 0x10 6. " F0_CK_INV ,FIFO 0 clock Inverted" "NORMAL,Inverted" bitfld.byte 0x10 5. " FIFO_FAST ,FIFO fast mode" "Disabled,Enabled" bitfld.byte 0x10 4. " FIFO_CAP ,FIFO software capture mode" "Disabled,Enabled" textline " " bitfld.byte 0x10 3. " FIFO_EDGE ,Edge/level sensitive FIFO write control (Fx_ld)" "LEVEL,EDGE" bitfld.byte 0x10 2. " FIFO_ASYNC ,Asynchronous FIFO clocking support" "Disabled,Enabled" bitfld.byte 0x10 1. " EXT_CRCPRS ,External CRC/PRS mode" "INTERNAL,EXTERNAL" bitfld.byte 0x10 0. " WRK16_CONCAT ,Datapath register access mode" "DEFAULT,CONCATENATE" line.byte 0x11 "CFG17,Datapath FIFO Control" bitfld.byte 0x11 4. " FIFO_ADD_SYNC ,Sync flip-flop to FIFO block status" "Disabled,Enabled" bitfld.byte 0x11 3. " NC3 ,Spare register bit NC3" "0,1" bitfld.byte 0x11 2. " NC2 ,Spare register bit NC2" "0,1" bitfld.byte 0x11 1. " F1_DYN ,FIFO 1 direction" "STATIC,DYNAMIC" textline " " bitfld.byte 0x11 0. " F0_DYN ,FIFO 0 direction" "STATIC,DYNAMIC" line.byte 0x12 "CFG18,Control Register Mode 0" line.byte 0x13 "CFG19,Control Register Mode 1" line.byte 0x14 "CFG20,Status Register Input Mode Selection" bitfld.byte 0x14 7. " STAT_MD[7] ,Bit 7 status input mode select" "Transparent,Sticky cleared" bitfld.byte 0x14 6. " [6] ,Bit 6 status input mode select" "Transparent,Sticky cleared" bitfld.byte 0x14 5. " [5] ,Bit 5 status input mode select" "Transparent,Sticky cleared" bitfld.byte 0x14 4. " [4] ,Bit 4 status input mode select" "Transparent,Sticky cleared" textline " " bitfld.byte 0x14 3. " [3] ,Bit 3 status input mode select" "Transparent,Sticky cleared" bitfld.byte 0x14 2. " [2] ,Bit 2 status input mode select" "Transparent,Sticky cleared" bitfld.byte 0x14 1. " [1] ,Bit 1 status input mode select" "Transparent,Sticky cleared" bitfld.byte 0x14 0. " [0] ,Bit 0 status input mode select" "Transparent,Sticky cleared" line.byte 0x15 "CFG21,Spare Register Bits" bitfld.byte 0x15 1. " NC1 ,Spare register bit NC1" "0,1" bitfld.byte 0x15 0. " NC0 ,Spare register bit NC0" "0,1" line.byte 0x16 "CFG22,SC Block Configuration Control" bitfld.byte 0x16 4. " SC_EXT_RES ,Control register external reset operation" "Disabled,Enabled" bitfld.byte 0x16 3. " SC_SYNC_MD ,SC sync mode" "NORMAL,SYNC_MODE" bitfld.byte 0x16 2. " SC_INT_MD ,SC interrupt mode" "NORMAL,INT_MODE" bitfld.byte 0x16 0.--1. " SC_OUT_CTL ,Output source for the status and control routing connections" "CONTROL,PARALLEL,COUNTER,?..." line.byte 0x17 "CFG23,Counter Control" bitfld.byte 0x17 6. " ALT_CNT ,Alternate operating mode of the counter" "DEFAULT_MODE,ALT_MODE" bitfld.byte 0x17 5. " ROUTE_EN ,Counter enable signal for routing input" "Disabled,Enabled" bitfld.byte 0x17 4. " ROUTE_LD ,Counter load signal for routing input" "Disabled,Enabled" bitfld.byte 0x17 2.--3. " CNT_EN_SEL ,Routing inputs for the counter enable signal" "SC_IN4,SC_IN5,SC_IN6,SC_IO" textline " " bitfld.byte 0x17 0.--1. " CNT_LD_SEL ,Routing inputs for the counter load signal" "SC_IN0,SC_IN1,SC_IN2,SC_IN3" if (((per.b(ad:0x400F3680+0x5F))&0x01)==0x01) group.byte 0x58++0x03 line.byte 0x00 "CFG24,PLD0 Clock And Reset Control" bitfld.byte 0x00 6.--7. " RC_RES_SEL ,Routed reset for the associated UDB component block" "0,1,2,3" bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x00 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x00 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x00 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x01 "CFG25,PLD1 Clock And Reset Control" bitfld.byte 0x00 6.--7. " RC_RES_SEL ,Routed reset for the associated UDB component block" "0,1,2,3" bitfld.byte 0x01 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x01 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x01 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x01 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x02 "CFG26,Datapath Clock And Reset Control" bitfld.byte 0x00 6.--7. " RC_RES_SEL ,Routed reset for the associated UDB component block" "0,1,2,3" bitfld.byte 0x02 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x02 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x02 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x02 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x03 "CFG27,Status/control Clock And Reset Control" bitfld.byte 0x00 6.--7. " RC_RES_SEL ,Routed reset for the associated UDB component block" "0,1,2,3" bitfld.byte 0x03 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x03 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x03 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x03 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" else group.byte 0x58++0x03 line.byte 0x00 "CFG24,PLD0 Clock And Reset Control" bitfld.byte 0x00 6. " FRES ,Firmware reset for the associated UDB component block" "No reset,Reset" bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x00 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x00 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x00 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x01 "CFG25,PLD1 Clock And Reset Control" bitfld.byte 0x00 6. " FRES ,Firmware reset for the associated UDB component block" "No reset,Reset" bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x00 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x00 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x00 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x02 "CFG26,Datapath Clock And Reset Control" bitfld.byte 0x00 6. " FRES ,Firmware reset for the associated UDB component block" "No reset,Reset" bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x00 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x00 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x00 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x03 "CFG27,Status/control Clock And Reset Control" rbitfld.byte 0x00 6. " FRES ,Firmware reset for the associated UDB component block" "No reset,Reset" bitfld.byte 0x00 5. " RC_INV ,Inverts the clock selection for the associated UDB component block" "Not inverted,Inverted" bitfld.byte 0x03 4. " RC_EN_INV ,Inverts the clock enable selection for the associated UDB component blocks" "Not inverted,Inverted" textline " " bitfld.byte 0x03 2.--3. " RC_EN_MODE ,Operating mode for the clock to the associated UDB component block" "OFF,ON,POSEDGE,LEVEL" bitfld.byte 0x03 0.--1. " RC_EN_SEL ,Channel route for enable control to the associated UDB component block" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" endif group.byte 0x5C++0x01 line.byte 0x00 "CFG28,Clock Selection For PLD1 And PLD0" bitfld.byte 0x00 4.--7. " PLD1_CK_SEL ,PLD1 clock selection registers" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,EXT_CLK,SYSCLK,?..." bitfld.byte 0x00 0.--3. " PLD0_CK_SEL ,PLD0 clock selection registers" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,EXT_CLK,SYSCLK,?..." line.byte 0x01 "CFG29,Clock Selection For Datapath, Status And Control" bitfld.byte 0x01 4.--7. " SC_CK_SEL ,SC clock selection registers" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,EXT_CLK,SYSCLK,?..." bitfld.byte 0x01 0.--3. " DP_CK_SEL ,DP clock selection registers" "GCLK0,GCLK1,GCLK2,GCLK3,GCLK4,GCLK5,GCLK6,GCLK7,EXT_CLK,SYSCLK,?..." if (((per.b(ad:0x400F3680+0x5F))&0x01)==0x01) group.byte 0x5E++0x01 line.byte 0x00 "CFG30,Reset Control" bitfld.byte 0x00 7. " SC_RES_POL ,Polarity of the selected SC routed reset" "Not inverted,Inverted" bitfld.byte 0x00 6. " DP_RES_POL ,Polarity of the selected datapath routed reset" "Not inverted,Inverted" bitfld.byte 0x00 4. " GUDB_WR ,Global write operation for the configuration and working registers UDB" "Disabled,Enabled" bitfld.byte 0x00 3. " EN_RES_CNTCTL ,Routed reset to the counter/control register" "Disabled,Enabled" textline " " rbitfld.byte 0x00 2. " RES_POL ,Polarity of the routed reset" "NEGATED,ASSERTED" rbitfld.byte 0x00 0.--1. " RES_SEL ,RC routing input for the compatible reset scheme" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x01 "CFG31,Reset Control" bitfld.byte 0x01 7. " PLD1_RES_POL ,Polarity of the routed reset for both plds" "Not inverted,Inverted" bitfld.byte 0x01 6. " PLD0_RES_POL ,Polarity of the routed reset for both plds" "Not inverted,Inverted" bitfld.byte 0x01 4.--5. " EXT_CK_SEL ,External clock selection" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" bitfld.byte 0x01 3. " EN_RES_DP ,Routed reset to the datapath block" "Disabled,Enabled" textline " " bitfld.byte 0x01 2. " EN_RES_STAT ,Routed reset to the status register" "NEGATED,ASSERTED" bitfld.byte 0x01 1. " EXT_SYNC ,Synchronization of selected external clock" "Disabled,Enabled" bitfld.byte 0x01 0. " ALT_RES ,Toggles between two reset configurations" "COMPATIBLE,ALTERNATE" else group.byte 0x5E++0x01 line.byte 0x00 "CFG30,Reset Control" rbitfld.byte 0x00 7. " SC_RES_POL ,Polarity of the selected SC routed reset" "Not inverted,Inverted" rbitfld.byte 0x00 6. " DP_RES_POL ,Polarity of the selected datapath routed reset" "Not inverted,Inverted" bitfld.byte 0x00 4. " GUDB_WR ,Global write operation for the configuration and working registers UDB" "Disabled,Enabled" bitfld.byte 0x00 3. " EN_RES_CNTCTL ,Routed reset to the counter/control register" "Disabled,Enabled" textline " " bitfld.byte 0x00 2. " RES_POL ,Polarity of the routed reset" "NEGATED,ASSERTED" bitfld.byte 0x00 0.--1. " RES_SEL ,RC routing input for the compatible reset scheme" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" line.byte 0x01 "CFG31,Reset Control" bitfld.byte 0x01 7. " PLD1_RES_POL ,Polarity of the routed reset for both plds" "Not inverted,Inverted" bitfld.byte 0x01 6. " PLD0_RES_POL ,Polarity of the routed reset for both plds" "Not inverted,Inverted" bitfld.byte 0x01 4.--5. " EXT_CK_SEL ,External clock selection" "RC_IN0,RC_IN1,RC_IN2,RC_IN3" rbitfld.byte 0x01 3. " EN_RES_DP ,Routed reset to the datapath block" "Disabled,Enabled" textline " " rbitfld.byte 0x01 2. " EN_RES_STAT ,Routed reset to the status register" "NEGATED,ASSERTED" bitfld.byte 0x01 1. " EXT_SYNC ,Synchronization of selected external clock" "Disabled,Enabled" bitfld.byte 0x01 0. " ALT_RES ,Toggles between two reset configurations" "COMPATIBLE,ALTERNATE" endif group.word 0x60++0x01 line.word 0x00 "DCFG0,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x62++0x01 line.word 0x00 "DCFG1,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x64++0x01 line.word 0x00 "DCFG2,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x66++0x01 line.word 0x00 "DCFG3,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x68++0x01 line.word 0x00 "DCFG4,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x6A++0x01 line.word 0x00 "DCFG5,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x6C++0x01 line.word 0x00 "DCFG6,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" group.word 0x6E++0x01 line.word 0x00 "DCFG7,Dynamic Configuration RAM" bitfld.word 0x00 13.--15. " FUNC ,Dynamic ALU function selection" "PASS,INC_A,DEC_A,ADD,SUB,XOR,AND,OR" bitfld.word 0x00 12. " SRC_A ,Dynamic ALU source A selection" "A0,A1" bitfld.word 0x00 10.--11. " SRC_B ,Dynamic ALU source B selection" "D0,D1,A0,A1" bitfld.word 0x00 8.--9. " SHIFT ,Dynamic shift selection" "NOSHIFT,LEFT,RIGHT,SWAP" textline " " bitfld.word 0x00 6.--7. " A0_WR_SRC ,Dynamic A0 write source selection" "NOWRITE,ALU,D0,F0" bitfld.word 0x00 4.--5. " A1_WR_SRC ,Dynamic A1 write source selection" "NOWRITE,ALU,D1,F1" bitfld.word 0x00 3. " CFB_EN ,Dynamic CRC feedback selection" "Disabled,Enabled" bitfld.word 0x00 2. " CI_SEL ,Dynamic carry in selection" "CFG_A,CFG_B" textline " " bitfld.word 0x00 1. " SI_SEL ,Dynamic shift in selection" "CFG_A,CFG_B" bitfld.word 0x00 0. " CMP_SEL ,Dynamic compare selection" "CFG_A,CFG_B" width 0x0B tree.end tree.end sif !CPUIS("CY8C4246AZI-L423")&&!CPUIS("CY8C4247AZI-L423") tree "USB Registers" base ad:0x402C0000 width 16. group.long 0x0++0x03 line.long 0x00 "EP0_DR0,Control End Point EP0 Data Register 0" hexmask.long.byte 0x00 0.--7. 1. " DATA_BYTE ,Transmit and receive data byte" group.long 0x4++0x03 line.long 0x00 "EP0_DR1,Control End Point EP0 Data Register 1" hexmask.long.byte 0x00 0.--7. 1. " DATA_BYTE ,Transmit and receive data byte" group.long 0x8++0x03 line.long 0x00 "EP0_DR2,Control End Point EP0 Data Register 2" hexmask.long.byte 0x00 0.--7. 1. " DATA_BYTE ,Transmit and receive data byte" group.long 0xC++0x03 line.long 0x00 "EP0_DR3,Control End Point EP0 Data Register 3" hexmask.long.byte 0x00 0.--7. 1. " DATA_BYTE ,Transmit and receive data byte" group.long 0x10++0x03 line.long 0x00 "EP0_DR4,Control End Point EP0 Data Register 4" hexmask.long.byte 0x00 0.--7. 1. " DATA_BYTE ,Transmit and receive data byte" group.long 0x14++0x03 line.long 0x00 "EP0_DR5,Control End Point EP0 Data Register 5" hexmask.long.byte 0x00 0.--7. 1. " DATA_BYTE ,Transmit and receive data byte" group.long 0x18++0x03 line.long 0x00 "EP0_DR6,Control End Point EP0 Data Register 6" hexmask.long.byte 0x00 0.--7. 1. " DATA_BYTE ,Transmit and receive data byte" group.long 0x1C++0x03 line.long 0x00 "EP0_DR7,Control End Point EP0 Data Register 7" hexmask.long.byte 0x00 0.--7. 1. " DATA_BYTE ,Transmit and receive data byte" group.long 0x20++0x1B line.long 0x00 "CR0,USB Control 0 Register" bitfld.long 0x00 7. " USB_ENABLE ,USB enable bit" "Disabled,Enabled" hexmask.long.byte 0x00 0.--6. 1. " DEVICE_ADDRESS ,USB device address" line.long 0x04 "CR1,USB Control 1 Register" bitfld.long 0x04 3. " TRIM_OFFSET_MSB ,Enable trim bit[7]" "Disabled,Enabled" bitfld.long 0x04 2. " BUS_ACTIVITY ,Bus activity event bit" "No occurred,Occurred" bitfld.long 0x04 1. " ENABLE_LOCK ,Automatic frequency locking of the internal oscillator to USB traffic" "Disabled,Enabled" bitfld.long 0x04 0. " REG_ENABLE ,Internal USB regulator" "Disabled,Enabled" line.long 0x08 "SIE_EP_INT_EN,USB SIE Data Endpoints Interrupt Enable Register" bitfld.long 0x08 7. " EP8_INTR_EN ,Enables interrupt for EP8" "No interrupt,Interrupt" bitfld.long 0x08 6. " EP7_INTR_EN ,Enables interrupt for EP7" "No interrupt,Interrupt" bitfld.long 0x08 5. " EP6_INTR_EN ,Enables interrupt for EP6" "No interrupt,Interrupt" bitfld.long 0x08 4. " EP5_INTR_EN ,Enables interrupt for EP5" "No interrupt,Interrupt" textline " " bitfld.long 0x08 3. " EP4_INTR_EN ,Enables interrupt for EP4" "No interrupt,Interrupt" bitfld.long 0x08 2. " EP3_INTR_EN ,Enables interrupt for EP3" "No interrupt,Interrupt" bitfld.long 0x08 1. " EP2_INTR_EN ,Enables interrupt for EP2" "No interrupt,Interrupt" bitfld.long 0x08 0. " EP1_INTR_EN ,Enables interrupt for EP1" "No interrupt,Interrupt" line.long 0x0C "SIE_EP_INT_SR,USB SIE Data Endpoint Interrupt Status" eventfld.long 0x0C 7. " EP8_INTR ,Interrupt status for EP8" "No interrupt,Interrupt" eventfld.long 0x0C 6. " EP7_INTR ,Interrupt status for EP7" "No interrupt,Interrupt" eventfld.long 0x0C 5. " EP6_INTR ,Interrupt status for EP6" "No interrupt,Interrupt" eventfld.long 0x0C 4. " EP5_INTR ,Interrupt status for EP5" "No interrupt,Interrupt" textline " " eventfld.long 0x0C 3. " EP4_INTR ,Interrupt status for EP4" "No interrupt,Interrupt" eventfld.long 0x0C 2. " EP3_INTR ,Interrupt status for EP3" "No interrupt,Interrupt" eventfld.long 0x0C 1. " EP2_INTR ,Interrupt status for EP2" "No interrupt,Interrupt" eventfld.long 0x0C 0. " EP1_INTR ,Interrupt status for EP1" "No interrupt,Interrupt" line.long 0x10 "SIE_EP1_CNT0,Non-control Endpoint Count Register" bitfld.long 0x10 7. " DATA_TOGGLE ,DATA packet's toggle state" "IN,OUT" rbitfld.long 0x10 6. " DATA_VALID ,Data valid bit" "DATA_ERROR,DATA_VALID" bitfld.long 0x10 0.--2. " DATA_COUNT_MSB ,3 MSB bits of an 11-bit counter" "0,1,2,3,4,5,6,7" line.long 0x14 "SIE_EP1_CNT1,8 LSB Of A 11-bit Counter" hexmask.long.byte 0x14 0.--7. 1. " DATA_COUNT ,8 LSB of a 11-bit counter" line.long 0x18 "SIE_EP1_CR0,Non-control Endpoint's Control Register" bitfld.long 0x18 7. " STALL ,SIE stalls an OUT/IN packet" "OUT,IN" rbitfld.long 0x18 6. " ERR_IN_TXN ,Error in transaction bit" "No error,Error" bitfld.long 0x18 5. " NAK_INT_EN ,NAK endpoint interrupt" "No interrupt,Interrupt" rbitfld.long 0x18 4. " ACKED_TXN ,Ack'd transaction bit" "ACKED_NO,ACKED_YES" textline " " bitfld.long 0x18 0.--3. " MODE ,Mode USB SIE" "Disabled,NAK_INOUT,STATUS_OUT_ONLY,STALL_INOUT,,ISO_OUT,STATUS_IN_ONLY,ISO_IN,NAK_OUT,ACK_OUT,,ACK_OUT_STATUS_IN,NAK_IN,ACK_IN,,ACK_IN_STATUS_OUT" if (((per.l(ad:0x402C0000+0x40))&0x80)==0x80) if (((per.l(ad:0x402C0000+0x40))&0x40)==0x40) group.long 0x40++0x03 line.long 0x00 "USBIO_CR0,USBIO Control 0 Register" bitfld.long 0x00 7. " TEN ,USB transmit enable" "Disabled,Enabled" bitfld.long 0x00 6. " TSE0 ,Transmit Single-Ended zero" "Disabled,Enabled" rbitfld.long 0x00 5. " TD ,Transmit data" "DIFF_K,DIFF_J" rbitfld.long 0x00 0. " RD ,Received data" "DIFF_LOW,DIFF_HIGH" else group.long 0x40++0x03 line.long 0x00 "USBIO_CR0,USBIO Control 0 Register" bitfld.long 0x00 7. " TEN ,USB transmit enable" "Disabled,Enabled" bitfld.long 0x00 6. " TSE0 ,Transmit Single-Ended zero" "Disabled,Enabled" bitfld.long 0x00 5. " TD ,Transmit data" "DIFF_K,DIFF_J" rbitfld.long 0x00 0. " RD ,Received data" "DIFF_LOW,DIFF_HIGH" endif else if (((per.l(ad:0x402C0000+0x40))&0x40)==0x40) group.long 0x40++0x03 line.long 0x00 "USBIO_CR0,USBIO Control 0 Register" bitfld.long 0x00 7. " TEN ,USB transmit enable" "Disabled,Enabled" rbitfld.long 0x00 6. " TSE0 ,Transmit Single-Ended zero" "Disabled,Enabled" rbitfld.long 0x00 5. " TD ,Transmit data" "DIFF_K,DIFF_J" rbitfld.long 0x00 0. " RD ,Received data" "DIFF_LOW,DIFF_HIGH" else group.long 0x40++0x03 line.long 0x00 "USBIO_CR0,USBIO Control 0 Register" bitfld.long 0x00 7. " TEN ,USB transmit enable" "Disabled,Enabled" rbitfld.long 0x00 6. " TSE0 ,Transmit Single-Ended zero" "Disabled,Enabled" rbitfld.long 0x00 5. " TD ,Transmit data" "DIFF_K,DIFF_J" rbitfld.long 0x00 0. " RD ,Received data" "DIFF_LOW,DIFF_HIGH" endif endif group.long 0x44++0x07 line.long 0x00 "USBIO_CR2,USBIO Control 2 Register" bitfld.long 0x00 7. " TEST_RES ,Testing the non-passthrough suspend mode pull up" "Not tested,Tested_d+" bitfld.long 0x00 6. " TEST_PKT ,Generated IN test packet" "Disabled,Enabled" line.long 0x04 "USBIO_CR1,USBIO Control 1 Register" bitfld.long 0x04 5. " IOMODE ,D+/D- configuration USB/bit-banged modes" "Not configured,Configured" bitfld.long 0x04 2. " USBPUEN ,Connection of the internal 1.5 k pull up resistor on the D+ pin" "No connected,Connected" rbitfld.long 0x04 1. " DPO ,State of the D+ pin" "0,1" rbitfld.long 0x04 0. " DMO ,State of the D- pin" "0,1" group.long 0x50++0x03 line.long 0x00 "DYN_RECONFIG,USB Dynamic Reconfiguration Register" rbitfld.long 0x00 4. " DYN_RECONFIG_RDY_STS ,Status for the dynamic reconfiguration" "Not ready,Ready" bitfld.long 0x00 1.--3. " DYN_RECONFIG_EPNO ,EP number reconfiguration required" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " DYN_CONFIG_EN ,Enable the dynamic re-configuration for the selected EP" "EP1,EP2" rgroup.long 0x60++0x07 line.long 0x00 "SOF0,Start Of Frame Register" hexmask.long.byte 0x00 0.--7. 1. " FRAME_NUMBER ,8 bits [7:0] of the SOF frame number" line.long 0x04 "SOF1,Start Of Frame Register" bitfld.long 0x04 0.--2. " FRAME_NUMBER_MSB , 3 bits [10:8] of the SOF frame number" "0,1,2,3,4,5,6,7" group.long 0x70++0x0B line.long 0x00 "SIE_EP2_CNT0,Non-control Endpoint Count Register" bitfld.long 0x00 7. " DATA_TOGGLE ,DATA packet's toggle state" "IN,OUT" rbitfld.long 0x00 6. " DATA_VALID ,Data valid bit" "DATA_ERROR,DATA_VALID" bitfld.long 0x00 0.--2. " DATA_COUNT_MSB ,3 MSB bits of an 11-bit counter" "0,1,2,3,4,5,6,7" line.long 0x04 "SIE_EP2_CNT1,8 LSB Of A 11-bit Counter" hexmask.long.byte 0x04 0.--7. 1. " DATA_COUNT ,8 LSB of a 11-bit counter" line.long 0x08 "SIE_EP2_CR0,Non-control Endpoint's Control Register" bitfld.long 0x08 7. " STALL ,SIE stalls an OUT/IN packet" "OUT,IN" rbitfld.long 0x08 6. " ERR_IN_TXN ,Error in transaction bit" "No error,Error" bitfld.long 0x08 5. " NAK_INT_EN ,NAK endpoint interrupt" "No interrupt,Interrupt" rbitfld.long 0x08 4. " ACKED_TXN ,Ack'd transaction bit" "ACKED_NO,ACKED_YES" textline " " bitfld.long 0x08 0.--3. " MODE ,Mode USB SIE" "Disabled,NAK_INOUT,STATUS_OUT_ONLY,STALL_INOUT,,ISO_OUT,STATUS_IN_ONLY,ISO_IN,NAK_OUT,ACK_OUT,,ACK_OUT_STATUS_IN,NAK_IN,ACK_IN,,ACK_IN_STATUS_OUT" rgroup.long 0x80++0x07 line.long 0x00 "OSCLK_DR0,Oscillator lock data register 0" hexmask.long.byte 0x00 0.--7. 1. " ADDER ,lower 8 bits of the oscillator locking circuits adder output" line.long 0x04 "OSCLK_DR1,Oscillator lock data register 1" hexmask.long.byte 0x04 0.--6. 1. " ADDER_MSB ,upper 7 bits of the oscillator locking circuits adder output" group.long 0xA0++0x03 line.long 0x00 "EP0_CR,Endpoint 0 control Register" rbitfld.long 0x00 7. " SETUP_RCVD , indicates a valid SETUP packet was received and ACKed" "No occurred,Occurred" rbitfld.long 0x00 6. " IN_RCVD ,indicates a valid IN packet has been received" "No occurred,Occurred" rbitfld.long 0x00 5. " OUT_RCVD ,indicates a valid OUT packet has been received and ACKed" "No occurred,Occurred" rbitfld.long 0x00 4. " ACKED_TXN ,ACK'd transaction bit" "ACKED_NO,ACKED_YES" textline " " bitfld.long 0x00 0.--3. " MODE ,Mode USB SIE" "Disabled,NAK_INOUT,STATUS_OUT_ONLY,STALL_INOUT,,ISO_OUT,STATUS_IN_ONLY,ISO_IN,NAK_OUT,ACK_OUT,,ACK_OUT_STATUS_IN,NAK_IN,ACK_IN,,ACK_IN_STATUS_OUT" if (((per.l(ad:0x402C0000+0xA4))&0x8)==0x8) group.long 0xA4++0x03 line.long 0x00 "EP0_CNT,Endpoint 0 count Register" bitfld.long 0x00 7. " DATA_TOGGLE ,DATA packet's toggle state" "IN,OUT" bitfld.long 0x00 6. " DATA_VALID ,OUT/SETUP transactions" "DATA_ERROR,DATA_VALID" bitfld.long 0x00 0.--3. " BYTE_COUNT , indicate the number of data bytes in a transaction" ",,2,3,4,5,6,7,8,9,10,?..." else group.long 0xA4++0x03 line.long 0x00 "EP0_CNT,Endpoint 0 count Register" bitfld.long 0x00 7. " DATA_TOGGLE ,DATA packet's toggle state" "IN,OUT" bitfld.long 0x00 6. " DATA_VALID ,OUT/SETUP transactions" "DATA_ERROR,DATA_VALID" bitfld.long 0x00 0.--3. " BYTE_COUNT , indicate the number of data bytes in a transaction" "0,1,2,3,4,5,6,7,8,?..." endif group.long 0xB0++0x0B line.long 0x00 "SIE_EP3_CNT0,Non-control Endpoint Count Register 0" bitfld.long 0x00 7. " DATA_TOGGLE ,DATA packet's toggle state" "IN,OUT" rbitfld.long 0x00 6. " DATA_VALID ,Data valid bit" "DATA_ERROR,DATA_VALID" bitfld.long 0x00 0.--2. " DATA_COUNT_MSB ,3 MSB bits of an 11-bit counter" "0,1,2,3,4,5,6,7" line.long 0x04 "SIE_EP3_CNT1,8 LSB Of A 11-bit Counter 1" hexmask.long.byte 0x04 0.--7. 1. " DATA_COUNT ,8 LSB of a 11-bit counter" line.long 0x08 "SIE_EP3_CR0,Non-control Endpoint's Control Register 0" rbitfld.long 0x08 7. " STALL ,SIE stalls an OUT/IN packet" "OUT,IN" rbitfld.long 0x08 6. " ERR_IN_TXN ,Error in transaction bit" "No error,Error" rbitfld.long 0x08 5. " NAK_INT_EN ,NAK endpoint interrupt" "No interrupt,Interrupt" rbitfld.long 0x08 4. " ACKED_TXN ,Ack'd transaction bit" "ACKED_NO,ACKED_YES" textline " " bitfld.long 0x08 0.--3. " MODE ,Mode USB SIE" "Disabled,NAK_INOUT,STATUS_OUT_ONLY,STALL_INOUT,,ISO_OUT,STATUS_IN_ONLY,ISO_IN,NAK_OUT,ACK_OUT,,ACK_OUT_STATUS_IN,NAK_IN,ACK_IN,,ACK_IN_STATUS_OUT" group.long 0xF0++0x0B line.long 0x00 "SIE_EP4_CNT0,Non-control Endpoint Count Register 0" bitfld.long 0x00 7. " DATA_TOGGLE ,DATA packet's toggle state" "IN,OUT" rbitfld.long 0x00 6. " DATA_VALID ,Data valid bit" "DATA_ERROR,DATA_VALID" bitfld.long 0x00 0.--2. " DATA_COUNT_MSB ,3 MSB bits of an 11-bit counter" "0,1,2,3,4,5,6,7" line.long 0x04 "SIE_EP4_CNT1,8 LSB Of A 11-bit Counter 1" hexmask.long.byte 0x04 0.--7. 1. " DATA_COUNT ,8 LSB of a 11-bit counter" line.long 0x08 "SIE_EP4_CR0,Non-control Endpoint's Control Register 0" rbitfld.long 0x08 7. " STALL ,SIE stalls an OUT/IN packet" "OUT,IN" rbitfld.long 0x08 6. " ERR_IN_TXN ,Error in transaction bit" "No error,Error" rbitfld.long 0x08 5. " NAK_INT_EN ,NAK endpoint interrupt" "No interrupt,Interrupt" rbitfld.long 0x08 4. " ACKED_TXN ,Ack'd transaction bit" "ACKED_NO,ACKED_YES" textline " " bitfld.long 0x08 0.--3. " MODE ,Mode USB SIE" "Disabled,NAK_INOUT,STATUS_OUT_ONLY,STALL_INOUT,,ISO_OUT,STATUS_IN_ONLY,ISO_IN,NAK_OUT,ACK_OUT,,ACK_OUT_STATUS_IN,NAK_IN,ACK_IN,,ACK_IN_STATUS_OUT" group.long 0x130++0x0B line.long 0x00 "SIE_EP5_CNT0,Non-control Endpoint Count Register 0" bitfld.long 0x00 7. " DATA_TOGGLE ,DATA packet's toggle state" "IN,OUT" rbitfld.long 0x00 6. " DATA_VALID ,Data valid bit" "DATA_ERROR,DATA_VALID" bitfld.long 0x00 0.--2. " DATA_COUNT_MSB ,3 MSB bits of an 11-bit counter" "0,1,2,3,4,5,6,7" line.long 0x04 "SIE_EP5_CNT1,8 LSB Of A 11-bit Counter 1" hexmask.long.byte 0x04 0.--7. 1. " DATA_COUNT ,8 LSB of a 11-bit counter" line.long 0x08 "SIE_EP5_CR0,Non-control Endpoint's Control Register 0" rbitfld.long 0x08 7. " STALL ,SIE stalls an OUT/IN packet" "OUT,IN" rbitfld.long 0x08 6. " ERR_IN_TXN ,Error in transaction bit" "No error,Error" rbitfld.long 0x08 5. " NAK_INT_EN ,NAK endpoint interrupt" "No interrupt,Interrupt" rbitfld.long 0x08 4. " ACKED_TXN ,Ack'd transaction bit" "ACKED_NO,ACKED_YES" textline " " bitfld.long 0x08 0.--3. " MODE ,Mode USB SIE" "Disabled,NAK_INOUT,STATUS_OUT_ONLY,STALL_INOUT,,ISO_OUT,STATUS_IN_ONLY,ISO_IN,NAK_OUT,ACK_OUT,,ACK_OUT_STATUS_IN,NAK_IN,ACK_IN,,ACK_IN_STATUS_OUT" group.long 0x170++0x0B line.long 0x00 "SIE_EP6_CNT0,Non-control Endpoint Count Register 0" bitfld.long 0x00 7. " DATA_TOGGLE ,DATA packet's toggle state" "IN,OUT" rbitfld.long 0x00 6. " DATA_VALID ,Data valid bit" "DATA_ERROR,DATA_VALID" bitfld.long 0x00 0.--2. " DATA_COUNT_MSB ,3 MSB bits of an 11-bit counter" "0,1,2,3,4,5,6,7" line.long 0x04 "SIE_EP6_CNT1,8 LSB Of A 11-bit Counter 1" hexmask.long.byte 0x04 0.--7. 1. " DATA_COUNT ,8 LSB of a 11-bit counter" line.long 0x08 "SIE_EP6_CR0,Non-control Endpoint's Control Register 0" rbitfld.long 0x08 7. " STALL ,SIE stalls an OUT/IN packet" "OUT,IN" rbitfld.long 0x08 6. " ERR_IN_TXN ,Error in transaction bit" "No error,Error" rbitfld.long 0x08 5. " NAK_INT_EN ,NAK endpoint interrupt" "No interrupt,Interrupt" rbitfld.long 0x08 4. " ACKED_TXN ,Ack'd transaction bit" "ACKED_NO,ACKED_YES" textline " " bitfld.long 0x08 0.--3. " MODE ,Mode USB SIE" "Disabled,NAK_INOUT,STATUS_OUT_ONLY,STALL_INOUT,,ISO_OUT,STATUS_IN_ONLY,ISO_IN,NAK_OUT,ACK_OUT,,ACK_OUT_STATUS_IN,NAK_IN,ACK_IN,,ACK_IN_STATUS_OUT" group.long 0x1B0++0x0B line.long 0x00 "SIE_EP7_CNT0,Non-control Endpoint Count Register 0" bitfld.long 0x00 7. " DATA_TOGGLE ,DATA packet's toggle state" "IN,OUT" rbitfld.long 0x00 6. " DATA_VALID ,Data valid bit" "DATA_ERROR,DATA_VALID" bitfld.long 0x00 0.--2. " DATA_COUNT_MSB ,3 MSB bits of an 11-bit counter" "0,1,2,3,4,5,6,7" line.long 0x04 "SIE_EP7_CNT1,8 LSB Of A 11-bit Counter 1" hexmask.long.byte 0x04 0.--7. 1. " DATA_COUNT ,8 LSB of a 11-bit counter" line.long 0x08 "SIE_EP7_CR0,Non-control Endpoint's Control Register 0" rbitfld.long 0x08 7. " STALL ,SIE stalls an OUT/IN packet" "OUT,IN" rbitfld.long 0x08 6. " ERR_IN_TXN ,Error in transaction bit" "No error,Error" rbitfld.long 0x08 5. " NAK_INT_EN ,NAK endpoint interrupt" "No interrupt,Interrupt" rbitfld.long 0x08 4. " ACKED_TXN ,Ack'd transaction bit" "ACKED_NO,ACKED_YES" textline " " bitfld.long 0x08 0.--3. " MODE ,Mode USB SIE" "Disabled,NAK_INOUT,STATUS_OUT_ONLY,STALL_INOUT,,ISO_OUT,STATUS_IN_ONLY,ISO_IN,NAK_OUT,ACK_OUT,,ACK_OUT_STATUS_IN,NAK_IN,ACK_IN,,ACK_IN_STATUS_OUT" group.long 0x1F0++0x0B line.long 0x00 "SIE_EP8_CNT0,Non-control Endpoint Count Register 0" bitfld.long 0x00 7. " DATA_TOGGLE ,DATA packet's toggle state" "IN,OUT" rbitfld.long 0x00 6. " DATA_VALID ,Data valid bit" "DATA_ERROR,DATA_VALID" bitfld.long 0x00 0.--2. " DATA_COUNT_MSB ,3 MSB bits of an 11-bit counter" "0,1,2,3,4,5,6,7" line.long 0x04 "SIE_EP8_CNT1,8 LSB Of A 11-bit Counter 1" hexmask.long.byte 0x04 0.--7. 1. " DATA_COUNT ,8 LSB of a 11-bit counter" line.long 0x08 "SIE_EP8_CR0,Non-control Endpoint's Control Register 0" rbitfld.long 0x08 7. " STALL ,SIE stalls an OUT/IN packet" "OUT,IN" rbitfld.long 0x08 6. " ERR_IN_TXN ,Error in transaction bit" "No error,Error" rbitfld.long 0x08 5. " NAK_INT_EN ,NAK endpoint interrupt" "No interrupt,Interrupt" rbitfld.long 0x08 4. " ACKED_TXN ,Ack'd transaction bit" "ACKED_NO,ACKED_YES" textline " " bitfld.long 0x08 0.--3. " MODE ,Mode USB SIE" "Disabled,NAK_INOUT,STATUS_OUT_ONLY,STALL_INOUT,,ISO_OUT,STATUS_IN_ONLY,ISO_IN,NAK_OUT,ACK_OUT,,ACK_OUT_STATUS_IN,NAK_IN,ACK_IN,,ACK_IN_STATUS_OUT" group.long 0x200++0xB line.long 0x00 "ARB_EP1_CFG,Endpoint Configuration Register" bitfld.long 0x00 3. " RESET_PTR ,Configuration Setting to Reset the RA and WA Pointer" "RESET_KRYPTON,RESET_NORMAL" bitfld.long 0x00 2. " CRC_BYPASS ,Configuration Setting to prevent CRC bytes" "CRC_NORMAL,CRC_NORMAL" bitfld.long 0x00 1. " DMA_REQ ,DMA Request" "Not requested,Requested" bitfld.long 0x00 0. " IN_DATA_RDY ,Endpoint Packet Data is Ready" "Not ready,Ready" line.long 0x04 "ARB_EP1_INT_EN,Endpoint Interrupt Enable Register" bitfld.long 0x04 5. " DMA_TERMIN_EN ,Endpoint DMA Terminated Enable" "Disabled,Enabled" bitfld.long 0x04 4. " ERR_INT_EN ,Endpoint Error in Transaction Interrupt Enable" "No interrupt,Interrupt" bitfld.long 0x04 3. " BUF_UNDER_EN ,Endpoint Buffer Underflow Enable" "Disabled,Enabled" bitfld.long 0x04 2. " BUF_OVER_EN ,Endpoint Buffer Overflow Enable" "No overflow,Overflow" textline " " bitfld.long 0x04 1. " DMA_GNT_EN ,Endpoint DMA Grant Enable" "Disabled,Enabled" bitfld.long 0x04 0. " IN_BUF_FULL_EN ,IN Endpoint Local Buffer Full Enable" "Disabled,Enabled" line.long 0x08 "ARB_EP1_SR,Endpoint Interrupt Enable Register" eventfld.long 0x08 5. " DMA_TERMIN ,Endpoint DMA Terminated Interrupt" "No interrupt,Interrupt" eventfld.long 0x08 3. " BUF_UNDER ,Endpoint Buffer Underflow Interrupt" "No interrupt,Interrupt" eventfld.long 0x08 2. " BUF_OVER ,Endpoint Buffer Overflow Interrupt" "No interrupt,Interrupt" eventfld.long 0x08 1. " DMA_GNT ,Endpoint DMA Grant Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 0. " IN_BUF_FULL ,IN Endpoint Local Buffer Full Interrupt" "No interrupt,Interrupt" group.long 0x210++0x13 line.long 0x00 "ARB_RW1_WA,Endpoint Write Address value" hexmask.long.byte 0x00 0.--7. 1. " WA ,Write Address for EP" line.long 0x04 "ARB_RW1_WA_MSB,Endpoint Write Address value" bitfld.long 0x04 0. " WA_MSB ,Write Address for EP" "0,1" line.long 0x08 "ARB_RW1_RA,Endpoint Read Address value" hexmask.long.byte 0x08 0.--7. 1. " RA ,Read Address for EP" line.long 0x0C "ARB_RW1_RA_MSB,Endpoint Read Address value" bitfld.long 0x0C 0. " RA_MSB ,Read Address for EP" "0,1" line.long 0x10 "ARB_RW1_DR,Endpoint Data Register" hexmask.long.byte 0x10 0.--7. 1. " DR ,Data Register for EP" group.long 0x230++0x03 line.long 0x00 "BUF_SIZE,Dedicated Endpoint Buffer Size Register" bitfld.long 0x00 4.--7. " OUT_BUF ,Buffer size for OUT Endpoints" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. " IN_BUF ,Buffer size for IN Endpoints" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x238++0x13 line.long 0x00 "EP_ACTIVE,Endpoint Active Indication Register" bitfld.long 0x00 7. " EP8_ACT ,Indicates that Endpoint is currently active" "Disabled,Enabled" bitfld.long 0x00 6. " EP7_ACT ,Indicates that Endpoint is currently active" "Disabled,Enabled" bitfld.long 0x00 5. " EP6_ACT ,Indicates that Endpoint is currently active" "Disabled,Enabled" bitfld.long 0x00 4. " EP5_ACT ,Indicates that Endpoint is currently active" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " EP4_ACT ,Indicates that Endpoint is currently active" "Disabled,Enabled" bitfld.long 0x00 2. " EP3_ACT ,Indicates that Endpoint is currently active" "Disabled,Enabled" bitfld.long 0x00 1. " EP2_ACT ,Indicates that Endpoint is currently active" "Disabled,Enabled" bitfld.long 0x00 0. " EP1_ACT ,Indicates that Endpoint is currently active" "Disabled,Enabled" line.long 0x04 "EP_TYPE,Endpoint Type (IN/OUT) Indication" bitfld.long 0x04 7. " EP8_TYP ,Endpoint Type Indication" "EP_IN,EP_OUT" bitfld.long 0x04 6. " EP7_TYP ,Endpoint Type Indication" "EP_IN,EP_OUT" bitfld.long 0x04 5. " EP6_TYP ,Endpoint Type Indication" "EP_IN,EP_OUT" bitfld.long 0x04 4. " EP5_TYP ,Endpoint Type Indication" "EP_IN,EP_OUT" textline " " bitfld.long 0x04 3. " EP4_TYP ,Endpoint Type Indication" "EP_IN,EP_OUT" bitfld.long 0x04 2. " EP3_TYP ,Endpoint Type Indication" "EP_IN,EP_OUT" bitfld.long 0x04 1. " EP2_TYP ,Endpoint Type Indication" "EP_IN,EP_OUT" bitfld.long 0x04 0. " EP1_TYP ,Endpoint Type Indication" "EP_IN,EP_OUT" line.long 0x08 "ARB_EP2_CFG,Endpoint Configuration Register" bitfld.long 0x08 3. " RESET_PTR ,Reset the RA and WA Pointers" "RESET_KRYPTON,RESET_NORMAL" bitfld.long 0x08 2. " CRC_BYPASS ,prevent CRC bytes" "CRC_NORMAL,CRC_BYPASS" bitfld.long 0x08 1. " DMA_REQ ,DMA Request" "No effect,Generated DMA" bitfld.long 0x08 0. " IN_DATA_RDY ,Endpoint Packet Data is Ready" "Not occurred,Occurred" line.long 0x0C "ARB_EP2_INT_EN,Endpoint Interrupt Enable Register" bitfld.long 0x0C 5. " DMA_TERMIN_EN ,Endpoint DMA Terminated Enable" "Disabled,Enabled" bitfld.long 0x0C 4. " ERR_INT_EN ,Endpoint Error in Transaction Interrupt Enable" "Disabled,Enabled" bitfld.long 0x0C 3. " BUF_UNDER_EN ,Endpoint Buffer Underflow Enable" "Disabled,Enabled" bitfld.long 0x0C 2. " BUF_OVER_EN ,Endpoint Buffer Overflow Enable" "No overflow,Overflow" textline " " bitfld.long 0x0C 1. " DMA_GNT_EN ,Endpoint DMA Grant Enable" "Disabled,Enabled" bitfld.long 0x0C 0. " IN_BUF_FULL_EN ,IN Endpoint Local Buffer Full Enable" "Disabled,Enabled" line.long 0x10 "ARB_EP2_SR,Endpoint Interrupt Enable Register" eventfld.long 0x10 5. " DMA_TERMIN ,Endpoint DMA Terminated Interrupt" "No interrupt,Interrupt" eventfld.long 0x10 3. " BUF_UNDER ,Endpoint Buffer Underflow Interrupt" "No interrupt,Interrupt" eventfld.long 0x10 2. " BUF_OVER ,Endpoint Buffer Overflow Interrupt" "No interrupt,Interrupt" eventfld.long 0x10 1. " DMA_GNT ,Endpoint DMA Grant Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x10 0. " IN_BUF_FULL ,IN Endpoint Local Buffer Full Interrupt" "No interrupt,Interrupt" group.long 0x250++0x0F line.long 0x00 "ARB_RW2_WA,Endpoint Write Address value" hexmask.long.byte 0x00 0.--7. 1. " WA , Write Address for EP" line.long 0x04 "ARB_RW2_WA_MSB,Endpoint Write Address value" bitfld.long 0x04 0. " WA_MSB ,Write Address for EP" "0,1" line.long 0x08 "ARB_RW2_RA,Read Address for EP" hexmask.long.byte 0x08 0.--7. 1. " RA ,Read Address for EP" line.long 0x0C "ARB_RW2_RA_MSB,Endpoint Read Address value" bitfld.long 0x0C 0. " RA_MSB ,Read Address for EP" "0,1" group.long 0x260++0x03 line.long 0x00 "ARB_RW2_DR,Endpoint Data Register" hexmask.long.byte 0x00 0.--7. 1. " ARB_RW2_DR ,Endpoint Data Register" group.long 0x270++0x0F line.long 0x00 "ARB_CFG,Arbiter Configuration Register" bitfld.long 0x00 7. " CFG_CMP ,Register Configuration Complete Indication" "Not required,Required" bitfld.long 0x00 5.--6. " DMA_CFG ,DMA Access Configuration" "DMA_NONE,DMA_MANUAL,DMA_AUTO,?.." bitfld.long 0x00 4. " AUTO_MEM ,Enables Auto Memory Configuration" "Disabled,enabled" line.long 0x04 "USB_CLK_EN,USB Block Clock Enable Register" bitfld.long 0x04 0. " CSR_CLK_EN ,Clock Enable for Core Logic clocked by AHB bus clock" "Disabled,Enabled" line.long 0x08 "ARB_INT_EN,Arbiter Interrupt Enable" bitfld.long 0x08 7. " EP8_INTR_EN ,Enables interrupt for EP8" "Disabled,Enabled" bitfld.long 0x08 6. " EP7_INTR_EN ,Enables interrupt for EP8" "Disabled,Enabled" bitfld.long 0x08 5. " EP6_INTR_EN ,Enables interrupt for EP8" "Disabled,Enabled" bitfld.long 0x08 4. " EP5_INTR_EN ,Enables interrupt for EP8" "Disabled,Enabled" textline " " bitfld.long 0x08 3. " EP4_INTR_EN ,Enables interrupt for EP8" "Disabled,Enabled" bitfld.long 0x08 2. " EP3_INTR_EN ,Enables interrupt for EP8" "Disabled,Enabled" bitfld.long 0x08 1. " EP2_INTR_EN ,Enables interrupt for EP8" "Disabled,Enabled" bitfld.long 0x08 0. " EP1_INTR_EN ,Enables interrupt for EP8" "Disabled,Enabled" line.long 0x0C "ARB_INT_SR,Arbiter Interrupt Status" rbitfld.long 0x0C 7. " EP8_INTR ,Interrupt status for EP8" "No interrupt,Interrupt" rbitfld.long 0x0C 6. " EP7_INTR ,Interrupt status for EP8" "No interrupt,Interrupt" rbitfld.long 0x0C 5. " EP6_INTR ,Interrupt status for EP8" "No interrupt,Interrupt" rbitfld.long 0x0C 4. " EP5_INTR ,Interrupt status for EP8" "No interrupt,Interrupt" textline " " rbitfld.long 0x0C 3. " EP4_INTR ,Interrupt status for EP8" "No interrupt,Interrupt" rbitfld.long 0x0C 2. " EP3_INTR ,Interrupt status for EP8" "No interrupt,Interrupt" rbitfld.long 0x0C 1. " EP2_INTR ,Interrupt status for EP8" "No interrupt,Interrupt" rbitfld.long 0x0C 0. " EP1_INTR ,Interrupt status for EP8" "No interrupt,Interrupt" group.long 0x280++0x0B line.long 0x00 "ARB_EP3_CFG,Endpoint Configuration Register" bitfld.long 0x00 3. " RESET_PTR ,Configuration Setting to Reset the RA and WA Pointer" "RESET_KRYPTON,RESET_NORMAL" bitfld.long 0x00 2. " CRC_BYPASS ,Configuration Setting to prevent CRC bytes" "CRC_NORMAL,CRC_NORMAL" bitfld.long 0x00 1. " DMA_REQ ,DMA Request" "Not requested,Requested" bitfld.long 0x00 0. " IN_DATA_RDY ,Endpoint Packet Data is Ready" "Not ready,Ready" line.long 0x04 "ARB_EP3_INT_EN,Endpoint Interrupt Enable Register" bitfld.long 0x04 5. " DMA_TERMIN_EN ,Endpoint DMA Terminated Enable" "Disabled,Enabled" bitfld.long 0x04 4. " ERR_INT_EN ,Endpoint Error in Transaction Interrupt Enable" "No interrupt,Interrupt" bitfld.long 0x04 3. " BUF_UNDER_EN ,Endpoint Buffer Underflow Enable" "Disabled,Enabled" bitfld.long 0x04 2. " BUF_OVER_EN ,Endpoint Buffer Overflow Enable" "No overflow,Overflow" textline " " bitfld.long 0x04 1. " DMA_GNT_EN ,Endpoint DMA Grant Enable" "Disabled,Enabled" bitfld.long 0x04 0. " IN_BUF_FULL_EN ,IN Endpoint Local Buffer Full Enable" "Disabled,Enabled" line.long 0x08 "ARB_EP3_SR,Endpoint Interrupt Enable Register" eventfld.long 0x08 5. " DMA_TERMIN ,Endpoint DMA Terminated Interrupt" "No interrupt,Interrupt" eventfld.long 0x08 3. " BUF_UNDER ,Endpoint Buffer Underflow Interrupt" "No interrupt,Interrupt" eventfld.long 0x08 2. " BUF_OVER ,Endpoint Buffer Overflow Interrupt" "No interrupt,Interrupt" eventfld.long 0x08 1. " DMA_GNT ,Endpoint DMA Grant Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 0. " IN_BUF_FULL ,IN Endpoint Local Buffer Full Interrupt" "No interrupt,Interrupt" group.long 0x290++0x0F line.long 0x00 "ARB_RW3_WA,Endpoint Write Address value" hexmask.long.byte 0x00 0.--7. 1. " WA , Write Address for EP" line.long 0x04 "ARB_RW3_WA_MSB,Endpoint Write Address value" bitfld.long 0x04 0. " WA_MSB ,Write Address for EP" "0,1" line.long 0x08 "ARB_RW3_RA,Read Address for EP" hexmask.long.byte 0x08 0.--7. 1. " RA ,Read Address for EP" line.long 0x0C "ARB_RW3_RA_MSB,Endpoint Read Address value" bitfld.long 0x0C 0. " RA_MSB ,Read Address for EP" "0,1" group.long 0x2A0++0x03 line.long 0x00 "ARB_RW3_DR,Endpoint Data Register" hexmask.long.byte 0x00 0.--7. 1. " ARB_RW2_DR ,Endpoint Data Register" group.long 0x2B0++0x07 line.long 0x00 "CWA,Common Area Write Address" hexmask.long.byte 0x00 0.--7. 1. " CWA ,Write Address for Common Area" line.long 0x04 "CWA_MSB,Endpoint Read Address value" bitfld.long 0x04 0. " CWA_MSB ,Write Address for Common Area" "0,1" group.long 0x2C0++0xB line.long 0x00 "ARB_EP4_CFG,Endpoint Configuration Register" bitfld.long 0x00 3. " RESET_PTR ,Configuration Setting to Reset the RA and WA Pointer" "RESET_KRYPTON,RESET_NORMAL" bitfld.long 0x00 2. " CRC_BYPASS ,Configuration Setting to prevent CRC bytes" "CRC_NORMAL,CRC_NORMAL" bitfld.long 0x00 1. " DMA_REQ ,DMA Request" "Not requested,Requested" bitfld.long 0x00 0. " IN_DATA_RDY ,Endpoint Packet Data is Ready" "Not ready,Ready" line.long 0x04 "ARB_EP4_INT_EN,Endpoint Interrupt Enable Register" bitfld.long 0x04 5. " DMA_TERMIN_EN ,Endpoint DMA Terminated Enable" "Disabled,Enabled" bitfld.long 0x04 4. " ERR_INT_EN ,Endpoint Error in Transaction Interrupt Enable" "No interrupt,Interrupt" bitfld.long 0x04 3. " BUF_UNDER_EN ,Endpoint Buffer Underflow Enable" "Disabled,Enabled" bitfld.long 0x04 2. " BUF_OVER_EN ,Endpoint Buffer Overflow Enable" "No overflow,Overflow" textline " " bitfld.long 0x04 1. " DMA_GNT_EN ,Endpoint DMA Grant Enable" "Disabled,Enabled" bitfld.long 0x04 0. " IN_BUF_FULL_EN ,IN Endpoint Local Buffer Full Enable" "Disabled,Enabled" line.long 0x08 "ARB_EP4_SR,Endpoint Interrupt Enable Register" eventfld.long 0x08 5. " DMA_TERMIN ,Endpoint DMA Terminated Interrupt" "No interrupt,Interrupt" eventfld.long 0x08 3. " BUF_UNDER ,Endpoint Buffer Underflow Interrupt" "No interrupt,Interrupt" eventfld.long 0x08 2. " BUF_OVER ,Endpoint Buffer Overflow Interrupt" "No interrupt,Interrupt" eventfld.long 0x08 1. " DMA_GNT ,Endpoint DMA Grant Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 0. " IN_BUF_FULL ,IN Endpoint Local Buffer Full Interrupt" "No interrupt,Interrupt" group.long 0x2D0++0x17 line.long 0x00 "ARB_RW4_WA,Endpoint Write Address value" hexmask.long.byte 0x00 0.--7. 1. " WA ,Write Address for EP" line.long 0x04 "ARB_RW4_WA_MSB,Endpoint Write Address value" bitfld.long 0x04 0. " WA_MSB ,Write Address for EP" "0,1" line.long 0x08 "ARB_RW4_RA,Endpoint Read Address value" hexmask.long.byte 0x08 0.--7. 1. " RA ,Read Address for EP" line.long 0x0C "ARB_RW4_RA_MSB,Endpoint Read Address value" bitfld.long 0x0C 0. " RA_MSB ,Read Address for EP" "0,1" line.long 0x10 "ARB_RW4_DR,Endpoint Data Register" hexmask.long.byte 0x10 0.--7. 1. " DR ,Data Register for EP" group.long 0x2F0++0x07 line.long 0x00 "DMA_THRES,DMA Burst / Threshold Configuration" hexmask.long.byte 0x00 0.--7. 1. " DMA_THS ,DMA Threshold count" line.long 0x04 "DMA_THRES_MSB,DMA Burst / Threshold Configuration" bitfld.long 0x04 0. " DMA_THS_MSB ,DMA Threshold count" "0,1" group.long 0x300++0xB line.long 0x00 "ARB_EP5_CFG,Endpoint Configuration Register" bitfld.long 0x00 3. " RESET_PTR ,Configuration Setting to Reset the RA and WA Pointer" "RESET_KRYPTON,RESET_NORMAL" bitfld.long 0x00 2. " CRC_BYPASS ,Configuration Setting to prevent CRC bytes" "CRC_NORMAL,CRC_NORMAL" bitfld.long 0x00 1. " DMA_REQ ,DMA Request" "Not requested,Requested" bitfld.long 0x00 0. " IN_DATA_RDY ,Endpoint Packet Data is Ready" "Not ready,Ready" line.long 0x04 "ARB_EP5_INT_EN,Endpoint Interrupt Enable Register" bitfld.long 0x04 5. " DMA_TERMIN_EN ,Endpoint DMA Terminated Enable" "Disabled,Enabled" bitfld.long 0x04 4. " ERR_INT_EN ,Endpoint Error in Transaction Interrupt Enable" "No interrupt,Interrupt" bitfld.long 0x04 3. " BUF_UNDER_EN ,Endpoint Buffer Underflow Enable" "Disabled,Enabled" bitfld.long 0x04 2. " BUF_OVER_EN ,Endpoint Buffer Overflow Enable" "No overflow,Overflow" textline " " bitfld.long 0x04 1. " DMA_GNT_EN ,Endpoint DMA Grant Enable" "Disabled,Enabled" bitfld.long 0x04 0. " IN_BUF_FULL_EN ,IN Endpoint Local Buffer Full Enable" "Disabled,Enabled" line.long 0x08 "ARB_EP5_SR,Endpoint Interrupt Enable Register" eventfld.long 0x08 5. " DMA_TERMIN ,Endpoint DMA Terminated Interrupt" "No interrupt,Interrupt" eventfld.long 0x08 3. " BUF_UNDER ,Endpoint Buffer Underflow Interrupt" "No interrupt,Interrupt" eventfld.long 0x08 2. " BUF_OVER ,Endpoint Buffer Overflow Interrupt" "No interrupt,Interrupt" eventfld.long 0x08 1. " DMA_GNT ,Endpoint DMA Grant Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 0. " IN_BUF_FULL ,IN Endpoint Local Buffer Full Interrupt" "No interrupt,Interrupt" group.long 0x310++0x13 line.long 0x00 "ARB_RW5_WA,Endpoint Write Address value" hexmask.long.byte 0x00 0.--7. 1. " WA ,Write Address for EP" line.long 0x04 "ARB_RW5_WA_MSB,Endpoint Write Address value" bitfld.long 0x04 0. " WA_MSB ,Write Address for EP" "0,1" line.long 0x08 "ARB_RW5_RA,Endpoint Read Address value" hexmask.long.byte 0x08 0.--7. 1. " RA ,Read Address for EP" line.long 0x0C "ARB_RW5_RA_MSB,Endpoint Read Address value" bitfld.long 0x0C 0. " RA_MSB ,Read Address for EP" "0,1" line.long 0x10 "ARB_RW5_DR,Endpoint Data Register" hexmask.long.byte 0x10 0.--7. 1. " DR ,Data Register for EP" group.long 0x330++0x03 line.long 0x00 "BUS_RST_CNT,Bus Reset Count Register" bitfld.long 0x00 0.--3. " bus_rst_cnt ,Bus Reset Count Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x340++0x0B line.long 0x00 "ARB_EP6_CFG,Endpoint Configuration Register" bitfld.long 0x00 3. " RESET_PTR ,Configuration Setting to Reset the RA and WA Pointer" "RESET_KRYPTON,RESET_NORMAL" bitfld.long 0x00 2. " CRC_BYPASS ,Configuration Setting to prevent CRC bytes" "CRC_NORMAL,CRC_NORMAL" bitfld.long 0x00 1. " DMA_REQ ,DMA Request" "Not requested,Requested" bitfld.long 0x00 0. " IN_DATA_RDY ,Endpoint Packet Data is Ready" "Not ready,Ready" line.long 0x04 "ARB_EP6_INT_EN,Endpoint Interrupt Enable Register" bitfld.long 0x04 5. " DMA_TERMIN_EN ,Endpoint DMA Terminated Enable" "Disabled,Enabled" bitfld.long 0x04 4. " ERR_INT_EN ,Endpoint Error in Transaction Interrupt Enable" "No interrupt,Interrupt" bitfld.long 0x04 3. " BUF_UNDER_EN ,Endpoint Buffer Underflow Enable" "Disabled,Enabled" bitfld.long 0x04 2. " BUF_OVER_EN ,Endpoint Buffer Overflow Enable" "No overflow,Overflow" textline " " bitfld.long 0x04 1. " DMA_GNT_EN ,Endpoint DMA Grant Enable" "Disabled,Enabled" bitfld.long 0x04 0. " IN_BUF_FULL_EN ,IN Endpoint Local Buffer Full Enable" "Disabled,Enabled" line.long 0x08 "ARB_EP6_SR,Endpoint Interrupt Enable Register" eventfld.long 0x08 5. " DMA_TERMIN ,Endpoint DMA Terminated Interrupt" "No interrupt,Interrupt" eventfld.long 0x08 3. " BUF_UNDER ,Endpoint Buffer Underflow Interrupt" "No interrupt,Interrupt" eventfld.long 0x08 2. " BUF_OVER ,Endpoint Buffer Overflow Interrupt" "No interrupt,Interrupt" eventfld.long 0x08 1. " DMA_GNT ,Endpoint DMA Grant Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 0. " IN_BUF_FULL ,IN Endpoint Local Buffer Full Interrupt" "No interrupt,Interrupt" group.long (0x340+0x10)++0x18 line.long 0x00 "ARB_RW6_WA,Endpoint Write Address value" hexmask.long.byte 0x00 0.--7. 1. " WA ,Write Address for EP" line.long 0x04 "ARB_RW6_WA_MSB,Endpoint Write Address value" bitfld.long 0x04 0. " WA_MSB ,Write Address for EP" "0,1" line.long 0x08 "ARB_RW6_RA,Endpoint Read Address value" hexmask.long.byte 0x08 0.--7. 1. " RA ,Read Address for EP" line.long 0x0C "ARB_RW6_RA_MSB,Endpoint Read Address value" bitfld.long 0x0C 0. " RA_MSB ,Read Address for EP" "0,1" line.long 0x10 "ARB_RW6_DR,Endpoint Data Register" hexmask.long.byte 0x10 0.--7. 1. " DR ,Data Register for EP" group.long 0x380++0x0B line.long 0x00 "ARB_EP7_CFG,Endpoint Configuration Register" bitfld.long 0x00 3. " RESET_PTR ,Configuration Setting to Reset the RA and WA Pointer" "RESET_KRYPTON,RESET_NORMAL" bitfld.long 0x00 2. " CRC_BYPASS ,Configuration Setting to prevent CRC bytes" "CRC_NORMAL,CRC_NORMAL" bitfld.long 0x00 1. " DMA_REQ ,DMA Request" "Not requested,Requested" bitfld.long 0x00 0. " IN_DATA_RDY ,Endpoint Packet Data is Ready" "Not ready,Ready" line.long 0x04 "ARB_EP7_INT_EN,Endpoint Interrupt Enable Register" bitfld.long 0x04 5. " DMA_TERMIN_EN ,Endpoint DMA Terminated Enable" "Disabled,Enabled" bitfld.long 0x04 4. " ERR_INT_EN ,Endpoint Error in Transaction Interrupt Enable" "No interrupt,Interrupt" bitfld.long 0x04 3. " BUF_UNDER_EN ,Endpoint Buffer Underflow Enable" "Disabled,Enabled" bitfld.long 0x04 2. " BUF_OVER_EN ,Endpoint Buffer Overflow Enable" "No overflow,Overflow" textline " " bitfld.long 0x04 1. " DMA_GNT_EN ,Endpoint DMA Grant Enable" "Disabled,Enabled" bitfld.long 0x04 0. " IN_BUF_FULL_EN ,IN Endpoint Local Buffer Full Enable" "Disabled,Enabled" line.long 0x08 "ARB_EP7_SR,Endpoint Interrupt Enable Register" eventfld.long 0x08 5. " DMA_TERMIN ,Endpoint DMA Terminated Interrupt" "No interrupt,Interrupt" eventfld.long 0x08 3. " BUF_UNDER ,Endpoint Buffer Underflow Interrupt" "No interrupt,Interrupt" eventfld.long 0x08 2. " BUF_OVER ,Endpoint Buffer Overflow Interrupt" "No interrupt,Interrupt" eventfld.long 0x08 1. " DMA_GNT ,Endpoint DMA Grant Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 0. " IN_BUF_FULL ,IN Endpoint Local Buffer Full Interrupt" "No interrupt,Interrupt" group.long (0x380+0x10)++0x18 line.long 0x00 "ARB_RW7_WA,Endpoint Write Address value" hexmask.long.byte 0x00 0.--7. 1. " WA ,Write Address for EP" line.long 0x04 "ARB_RW7_WA_MSB,Endpoint Write Address value" bitfld.long 0x04 0. " WA_MSB ,Write Address for EP" "0,1" line.long 0x08 "ARB_RW7_RA,Endpoint Read Address value" hexmask.long.byte 0x08 0.--7. 1. " RA ,Read Address for EP" line.long 0x0C "ARB_RW7_RA_MSB,Endpoint Read Address value" bitfld.long 0x0C 0. " RA_MSB ,Read Address for EP" "0,1" line.long 0x10 "ARB_RW7_DR,Endpoint Data Register" hexmask.long.byte 0x10 0.--7. 1. " DR ,Data Register for EP" group.long 0x3C0++0x0B line.long 0x00 "ARB_EP8_CFG,Endpoint Configuration Register" bitfld.long 0x00 3. " RESET_PTR ,Configuration Setting to Reset the RA and WA Pointer" "RESET_KRYPTON,RESET_NORMAL" bitfld.long 0x00 2. " CRC_BYPASS ,Configuration Setting to prevent CRC bytes" "CRC_NORMAL,CRC_NORMAL" bitfld.long 0x00 1. " DMA_REQ ,DMA Request" "Not requested,Requested" bitfld.long 0x00 0. " IN_DATA_RDY ,Endpoint Packet Data is Ready" "Not ready,Ready" line.long 0x04 "ARB_EP8_INT_EN,Endpoint Interrupt Enable Register" bitfld.long 0x04 5. " DMA_TERMIN_EN ,Endpoint DMA Terminated Enable" "Disabled,Enabled" bitfld.long 0x04 4. " ERR_INT_EN ,Endpoint Error in Transaction Interrupt Enable" "No interrupt,Interrupt" bitfld.long 0x04 3. " BUF_UNDER_EN ,Endpoint Buffer Underflow Enable" "Disabled,Enabled" bitfld.long 0x04 2. " BUF_OVER_EN ,Endpoint Buffer Overflow Enable" "No overflow,Overflow" textline " " bitfld.long 0x04 1. " DMA_GNT_EN ,Endpoint DMA Grant Enable" "Disabled,Enabled" bitfld.long 0x04 0. " IN_BUF_FULL_EN ,IN Endpoint Local Buffer Full Enable" "Disabled,Enabled" line.long 0x08 "ARB_EP8_SR,Endpoint Interrupt Enable Register" eventfld.long 0x08 5. " DMA_TERMIN ,Endpoint DMA Terminated Interrupt" "No interrupt,Interrupt" eventfld.long 0x08 3. " BUF_UNDER ,Endpoint Buffer Underflow Interrupt" "No interrupt,Interrupt" eventfld.long 0x08 2. " BUF_OVER ,Endpoint Buffer Overflow Interrupt" "No interrupt,Interrupt" eventfld.long 0x08 1. " DMA_GNT ,Endpoint DMA Grant Interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 0. " IN_BUF_FULL ,IN Endpoint Local Buffer Full Interrupt" "No interrupt,Interrupt" group.long (0x3C0+0x10)++0x18 line.long 0x00 "ARB_RW8_WA,Endpoint Write Address value" hexmask.long.byte 0x00 0.--7. 1. " WA ,Write Address for EP" line.long 0x04 "ARB_RW8_WA_MSB,Endpoint Write Address value" bitfld.long 0x04 0. " WA_MSB ,Write Address for EP" "0,1" line.long 0x08 "ARB_RW8_RA,Endpoint Read Address value" hexmask.long.byte 0x08 0.--7. 1. " RA ,Read Address for EP" line.long 0x0C "ARB_RW8_RA_MSB,Endpoint Read Address value" bitfld.long 0x0C 0. " RA_MSB ,Read Address for EP" "0,1" line.long 0x10 "ARB_RW8_DR,Endpoint Data Register" hexmask.long.byte 0x10 0.--7. 1. " DR ,Data Register for EP" tree "MEM_DATA" group.long 0x400++0x03 line.long 0x00 "MEM_DATA0,DATA 0" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x404++0x03 line.long 0x00 "MEM_DATA1,DATA 1" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x408++0x03 line.long 0x00 "MEM_DATA2,DATA 2" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x40C++0x03 line.long 0x00 "MEM_DATA3,DATA 3" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x410++0x03 line.long 0x00 "MEM_DATA4,DATA 4" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x414++0x03 line.long 0x00 "MEM_DATA5,DATA 5" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x418++0x03 line.long 0x00 "MEM_DATA6,DATA 6" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x41C++0x03 line.long 0x00 "MEM_DATA7,DATA 7" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x420++0x03 line.long 0x00 "MEM_DATA8,DATA 8" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x424++0x03 line.long 0x00 "MEM_DATA9,DATA 9" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x428++0x03 line.long 0x00 "MEM_DATA10,DATA 10" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x42C++0x03 line.long 0x00 "MEM_DATA11,DATA 11" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x430++0x03 line.long 0x00 "MEM_DATA12,DATA 12" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x434++0x03 line.long 0x00 "MEM_DATA13,DATA 13" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x438++0x03 line.long 0x00 "MEM_DATA14,DATA 14" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x43C++0x03 line.long 0x00 "MEM_DATA15,DATA 15" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x440++0x03 line.long 0x00 "MEM_DATA16,DATA 16" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x444++0x03 line.long 0x00 "MEM_DATA17,DATA 17" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x448++0x03 line.long 0x00 "MEM_DATA18,DATA 18" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x44C++0x03 line.long 0x00 "MEM_DATA19,DATA 19" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x450++0x03 line.long 0x00 "MEM_DATA20,DATA 20" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x454++0x03 line.long 0x00 "MEM_DATA21,DATA 21" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x458++0x03 line.long 0x00 "MEM_DATA22,DATA 22" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x45C++0x03 line.long 0x00 "MEM_DATA23,DATA 23" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x460++0x03 line.long 0x00 "MEM_DATA24,DATA 24" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x464++0x03 line.long 0x00 "MEM_DATA25,DATA 25" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x468++0x03 line.long 0x00 "MEM_DATA26,DATA 26" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x46C++0x03 line.long 0x00 "MEM_DATA27,DATA 27" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x470++0x03 line.long 0x00 "MEM_DATA28,DATA 28" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x474++0x03 line.long 0x00 "MEM_DATA29,DATA 29" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x478++0x03 line.long 0x00 "MEM_DATA30,DATA 30" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x47C++0x03 line.long 0x00 "MEM_DATA31,DATA 31" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x480++0x03 line.long 0x00 "MEM_DATA32,DATA 32" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x484++0x03 line.long 0x00 "MEM_DATA33,DATA 33" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x488++0x03 line.long 0x00 "MEM_DATA34,DATA 34" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x48C++0x03 line.long 0x00 "MEM_DATA35,DATA 35" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x490++0x03 line.long 0x00 "MEM_DATA36,DATA 36" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x494++0x03 line.long 0x00 "MEM_DATA37,DATA 37" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x498++0x03 line.long 0x00 "MEM_DATA38,DATA 38" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x49C++0x03 line.long 0x00 "MEM_DATA39,DATA 39" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x4A0++0x03 line.long 0x00 "MEM_DATA40,DATA 40" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x4A4++0x03 line.long 0x00 "MEM_DATA41,DATA 41" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x4A8++0x03 line.long 0x00 "MEM_DATA42,DATA 42" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x4AC++0x03 line.long 0x00 "MEM_DATA43,DATA 43" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x4B0++0x03 line.long 0x00 "MEM_DATA44,DATA 44" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x4B4++0x03 line.long 0x00 "MEM_DATA45,DATA 45" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x4B8++0x03 line.long 0x00 "MEM_DATA46,DATA 46" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x4BC++0x03 line.long 0x00 "MEM_DATA47,DATA 47" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x4C0++0x03 line.long 0x00 "MEM_DATA48,DATA 48" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x4C4++0x03 line.long 0x00 "MEM_DATA49,DATA 49" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x4C8++0x03 line.long 0x00 "MEM_DATA50,DATA 50" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x4CC++0x03 line.long 0x00 "MEM_DATA51,DATA 51" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x4D0++0x03 line.long 0x00 "MEM_DATA52,DATA 52" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x4D4++0x03 line.long 0x00 "MEM_DATA53,DATA 53" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x4D8++0x03 line.long 0x00 "MEM_DATA54,DATA 54" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x4DC++0x03 line.long 0x00 "MEM_DATA55,DATA 55" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x4E0++0x03 line.long 0x00 "MEM_DATA56,DATA 56" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x4E4++0x03 line.long 0x00 "MEM_DATA57,DATA 57" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x4E8++0x03 line.long 0x00 "MEM_DATA58,DATA 58" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x4EC++0x03 line.long 0x00 "MEM_DATA59,DATA 59" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x4F0++0x03 line.long 0x00 "MEM_DATA60,DATA 60" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x4F4++0x03 line.long 0x00 "MEM_DATA61,DATA 61" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x4F8++0x03 line.long 0x00 "MEM_DATA62,DATA 62" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x4FC++0x03 line.long 0x00 "MEM_DATA63,DATA 63" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x500++0x03 line.long 0x00 "MEM_DATA64,DATA 64" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x504++0x03 line.long 0x00 "MEM_DATA65,DATA 65" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x508++0x03 line.long 0x00 "MEM_DATA66,DATA 66" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x50C++0x03 line.long 0x00 "MEM_DATA67,DATA 67" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x510++0x03 line.long 0x00 "MEM_DATA68,DATA 68" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x514++0x03 line.long 0x00 "MEM_DATA69,DATA 69" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x518++0x03 line.long 0x00 "MEM_DATA70,DATA 70" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x51C++0x03 line.long 0x00 "MEM_DATA71,DATA 71" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x520++0x03 line.long 0x00 "MEM_DATA72,DATA 72" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x524++0x03 line.long 0x00 "MEM_DATA73,DATA 73" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x528++0x03 line.long 0x00 "MEM_DATA74,DATA 74" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x52C++0x03 line.long 0x00 "MEM_DATA75,DATA 75" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x530++0x03 line.long 0x00 "MEM_DATA76,DATA 76" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x534++0x03 line.long 0x00 "MEM_DATA77,DATA 77" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x538++0x03 line.long 0x00 "MEM_DATA78,DATA 78" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x53C++0x03 line.long 0x00 "MEM_DATA79,DATA 79" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x540++0x03 line.long 0x00 "MEM_DATA80,DATA 80" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x544++0x03 line.long 0x00 "MEM_DATA81,DATA 81" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x548++0x03 line.long 0x00 "MEM_DATA82,DATA 82" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x54C++0x03 line.long 0x00 "MEM_DATA83,DATA 83" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x550++0x03 line.long 0x00 "MEM_DATA84,DATA 84" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x554++0x03 line.long 0x00 "MEM_DATA85,DATA 85" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x558++0x03 line.long 0x00 "MEM_DATA86,DATA 86" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x55C++0x03 line.long 0x00 "MEM_DATA87,DATA 87" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x560++0x03 line.long 0x00 "MEM_DATA88,DATA 88" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x564++0x03 line.long 0x00 "MEM_DATA89,DATA 89" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x568++0x03 line.long 0x00 "MEM_DATA90,DATA 90" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x56C++0x03 line.long 0x00 "MEM_DATA91,DATA 91" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x570++0x03 line.long 0x00 "MEM_DATA92,DATA 92" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x574++0x03 line.long 0x00 "MEM_DATA93,DATA 93" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x578++0x03 line.long 0x00 "MEM_DATA94,DATA 94" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x57C++0x03 line.long 0x00 "MEM_DATA95,DATA 95" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x580++0x03 line.long 0x00 "MEM_DATA96,DATA 96" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x584++0x03 line.long 0x00 "MEM_DATA97,DATA 97" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x588++0x03 line.long 0x00 "MEM_DATA98,DATA 98" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x58C++0x03 line.long 0x00 "MEM_DATA99,DATA 99" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x590++0x03 line.long 0x00 "MEM_DATA100,DATA 100" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x594++0x03 line.long 0x00 "MEM_DATA101,DATA 101" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x598++0x03 line.long 0x00 "MEM_DATA102,DATA 102" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x59C++0x03 line.long 0x00 "MEM_DATA103,DATA 103" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x5A0++0x03 line.long 0x00 "MEM_DATA104,DATA 104" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x5A4++0x03 line.long 0x00 "MEM_DATA105,DATA 105" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x5A8++0x03 line.long 0x00 "MEM_DATA106,DATA 106" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x5AC++0x03 line.long 0x00 "MEM_DATA107,DATA 107" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x5B0++0x03 line.long 0x00 "MEM_DATA108,DATA 108" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x5B4++0x03 line.long 0x00 "MEM_DATA109,DATA 109" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x5B8++0x03 line.long 0x00 "MEM_DATA110,DATA 110" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x5BC++0x03 line.long 0x00 "MEM_DATA111,DATA 111" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x5C0++0x03 line.long 0x00 "MEM_DATA112,DATA 112" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x5C4++0x03 line.long 0x00 "MEM_DATA113,DATA 113" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x5C8++0x03 line.long 0x00 "MEM_DATA114,DATA 114" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x5CC++0x03 line.long 0x00 "MEM_DATA115,DATA 115" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x5D0++0x03 line.long 0x00 "MEM_DATA116,DATA 116" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x5D4++0x03 line.long 0x00 "MEM_DATA117,DATA 117" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x5D8++0x03 line.long 0x00 "MEM_DATA118,DATA 118" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x5DC++0x03 line.long 0x00 "MEM_DATA119,DATA 119" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x5E0++0x03 line.long 0x00 "MEM_DATA120,DATA 120" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x5E4++0x03 line.long 0x00 "MEM_DATA121,DATA 121" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x5E8++0x03 line.long 0x00 "MEM_DATA122,DATA 122" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x5EC++0x03 line.long 0x00 "MEM_DATA123,DATA 123" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x5F0++0x03 line.long 0x00 "MEM_DATA124,DATA 124" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x5F4++0x03 line.long 0x00 "MEM_DATA125,DATA 125" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x5F8++0x03 line.long 0x00 "MEM_DATA126,DATA 126" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x5FC++0x03 line.long 0x00 "MEM_DATA127,DATA 127" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x600++0x03 line.long 0x00 "MEM_DATA128,DATA 128" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x604++0x03 line.long 0x00 "MEM_DATA129,DATA 129" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x608++0x03 line.long 0x00 "MEM_DATA130,DATA 130" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x60C++0x03 line.long 0x00 "MEM_DATA131,DATA 131" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x610++0x03 line.long 0x00 "MEM_DATA132,DATA 132" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x614++0x03 line.long 0x00 "MEM_DATA133,DATA 133" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x618++0x03 line.long 0x00 "MEM_DATA134,DATA 134" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x61C++0x03 line.long 0x00 "MEM_DATA135,DATA 135" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x620++0x03 line.long 0x00 "MEM_DATA136,DATA 136" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x624++0x03 line.long 0x00 "MEM_DATA137,DATA 137" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x628++0x03 line.long 0x00 "MEM_DATA138,DATA 138" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x62C++0x03 line.long 0x00 "MEM_DATA139,DATA 139" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x630++0x03 line.long 0x00 "MEM_DATA140,DATA 140" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x634++0x03 line.long 0x00 "MEM_DATA141,DATA 141" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x638++0x03 line.long 0x00 "MEM_DATA142,DATA 142" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x63C++0x03 line.long 0x00 "MEM_DATA143,DATA 143" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x640++0x03 line.long 0x00 "MEM_DATA144,DATA 144" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x644++0x03 line.long 0x00 "MEM_DATA145,DATA 145" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x648++0x03 line.long 0x00 "MEM_DATA146,DATA 146" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x64C++0x03 line.long 0x00 "MEM_DATA147,DATA 147" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x650++0x03 line.long 0x00 "MEM_DATA148,DATA 148" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x654++0x03 line.long 0x00 "MEM_DATA149,DATA 149" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x658++0x03 line.long 0x00 "MEM_DATA150,DATA 150" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x65C++0x03 line.long 0x00 "MEM_DATA151,DATA 151" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x660++0x03 line.long 0x00 "MEM_DATA152,DATA 152" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x664++0x03 line.long 0x00 "MEM_DATA153,DATA 153" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x668++0x03 line.long 0x00 "MEM_DATA154,DATA 154" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x66C++0x03 line.long 0x00 "MEM_DATA155,DATA 155" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x670++0x03 line.long 0x00 "MEM_DATA156,DATA 156" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x674++0x03 line.long 0x00 "MEM_DATA157,DATA 157" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x678++0x03 line.long 0x00 "MEM_DATA158,DATA 158" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x67C++0x03 line.long 0x00 "MEM_DATA159,DATA 159" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x680++0x03 line.long 0x00 "MEM_DATA160,DATA 160" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x684++0x03 line.long 0x00 "MEM_DATA161,DATA 161" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x688++0x03 line.long 0x00 "MEM_DATA162,DATA 162" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x68C++0x03 line.long 0x00 "MEM_DATA163,DATA 163" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x690++0x03 line.long 0x00 "MEM_DATA164,DATA 164" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x694++0x03 line.long 0x00 "MEM_DATA165,DATA 165" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x698++0x03 line.long 0x00 "MEM_DATA166,DATA 166" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x69C++0x03 line.long 0x00 "MEM_DATA167,DATA 167" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x6A0++0x03 line.long 0x00 "MEM_DATA168,DATA 168" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x6A4++0x03 line.long 0x00 "MEM_DATA169,DATA 169" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x6A8++0x03 line.long 0x00 "MEM_DATA170,DATA 170" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x6AC++0x03 line.long 0x00 "MEM_DATA171,DATA 171" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x6B0++0x03 line.long 0x00 "MEM_DATA172,DATA 172" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x6B4++0x03 line.long 0x00 "MEM_DATA173,DATA 173" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x6B8++0x03 line.long 0x00 "MEM_DATA174,DATA 174" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x6BC++0x03 line.long 0x00 "MEM_DATA175,DATA 175" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x6C0++0x03 line.long 0x00 "MEM_DATA176,DATA 176" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x6C4++0x03 line.long 0x00 "MEM_DATA177,DATA 177" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x6C8++0x03 line.long 0x00 "MEM_DATA178,DATA 178" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x6CC++0x03 line.long 0x00 "MEM_DATA179,DATA 179" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x6D0++0x03 line.long 0x00 "MEM_DATA180,DATA 180" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x6D4++0x03 line.long 0x00 "MEM_DATA181,DATA 181" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x6D8++0x03 line.long 0x00 "MEM_DATA182,DATA 182" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x6DC++0x03 line.long 0x00 "MEM_DATA183,DATA 183" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x6E0++0x03 line.long 0x00 "MEM_DATA184,DATA 184" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x6E4++0x03 line.long 0x00 "MEM_DATA185,DATA 185" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x6E8++0x03 line.long 0x00 "MEM_DATA186,DATA 186" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x6EC++0x03 line.long 0x00 "MEM_DATA187,DATA 187" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x6F0++0x03 line.long 0x00 "MEM_DATA188,DATA 188" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x6F4++0x03 line.long 0x00 "MEM_DATA189,DATA 189" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x6F8++0x03 line.long 0x00 "MEM_DATA190,DATA 190" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x6FC++0x03 line.long 0x00 "MEM_DATA191,DATA 191" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x700++0x03 line.long 0x00 "MEM_DATA192,DATA 192" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x704++0x03 line.long 0x00 "MEM_DATA193,DATA 193" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x708++0x03 line.long 0x00 "MEM_DATA194,DATA 194" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x70C++0x03 line.long 0x00 "MEM_DATA195,DATA 195" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x710++0x03 line.long 0x00 "MEM_DATA196,DATA 196" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x714++0x03 line.long 0x00 "MEM_DATA197,DATA 197" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x718++0x03 line.long 0x00 "MEM_DATA198,DATA 198" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x71C++0x03 line.long 0x00 "MEM_DATA199,DATA 199" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x720++0x03 line.long 0x00 "MEM_DATA200,DATA 200" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x724++0x03 line.long 0x00 "MEM_DATA201,DATA 201" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x728++0x03 line.long 0x00 "MEM_DATA202,DATA 202" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x72C++0x03 line.long 0x00 "MEM_DATA203,DATA 203" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x730++0x03 line.long 0x00 "MEM_DATA204,DATA 204" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x734++0x03 line.long 0x00 "MEM_DATA205,DATA 205" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x738++0x03 line.long 0x00 "MEM_DATA206,DATA 206" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x73C++0x03 line.long 0x00 "MEM_DATA207,DATA 207" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x740++0x03 line.long 0x00 "MEM_DATA208,DATA 208" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x744++0x03 line.long 0x00 "MEM_DATA209,DATA 209" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x748++0x03 line.long 0x00 "MEM_DATA210,DATA 210" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x74C++0x03 line.long 0x00 "MEM_DATA211,DATA 211" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x750++0x03 line.long 0x00 "MEM_DATA212,DATA 212" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x754++0x03 line.long 0x00 "MEM_DATA213,DATA 213" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x758++0x03 line.long 0x00 "MEM_DATA214,DATA 214" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x75C++0x03 line.long 0x00 "MEM_DATA215,DATA 215" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x760++0x03 line.long 0x00 "MEM_DATA216,DATA 216" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x764++0x03 line.long 0x00 "MEM_DATA217,DATA 217" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x768++0x03 line.long 0x00 "MEM_DATA218,DATA 218" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x76C++0x03 line.long 0x00 "MEM_DATA219,DATA 219" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x770++0x03 line.long 0x00 "MEM_DATA220,DATA 220" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x774++0x03 line.long 0x00 "MEM_DATA221,DATA 221" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x778++0x03 line.long 0x00 "MEM_DATA222,DATA 222" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x77C++0x03 line.long 0x00 "MEM_DATA223,DATA 223" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x780++0x03 line.long 0x00 "MEM_DATA224,DATA 224" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x784++0x03 line.long 0x00 "MEM_DATA225,DATA 225" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x788++0x03 line.long 0x00 "MEM_DATA226,DATA 226" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x78C++0x03 line.long 0x00 "MEM_DATA227,DATA 227" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x790++0x03 line.long 0x00 "MEM_DATA228,DATA 228" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x794++0x03 line.long 0x00 "MEM_DATA229,DATA 229" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x798++0x03 line.long 0x00 "MEM_DATA230,DATA 230" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x79C++0x03 line.long 0x00 "MEM_DATA231,DATA 231" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x7A0++0x03 line.long 0x00 "MEM_DATA232,DATA 232" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x7A4++0x03 line.long 0x00 "MEM_DATA233,DATA 233" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x7A8++0x03 line.long 0x00 "MEM_DATA234,DATA 234" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x7AC++0x03 line.long 0x00 "MEM_DATA235,DATA 235" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x7B0++0x03 line.long 0x00 "MEM_DATA236,DATA 236" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x7B4++0x03 line.long 0x00 "MEM_DATA237,DATA 237" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x7B8++0x03 line.long 0x00 "MEM_DATA238,DATA 238" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x7BC++0x03 line.long 0x00 "MEM_DATA239,DATA 239" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x7C0++0x03 line.long 0x00 "MEM_DATA240,DATA 240" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x7C4++0x03 line.long 0x00 "MEM_DATA241,DATA 241" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x7C8++0x03 line.long 0x00 "MEM_DATA242,DATA 242" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x7CC++0x03 line.long 0x00 "MEM_DATA243,DATA 243" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x7D0++0x03 line.long 0x00 "MEM_DATA244,DATA 244" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x7D4++0x03 line.long 0x00 "MEM_DATA245,DATA 245" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x7D8++0x03 line.long 0x00 "MEM_DATA246,DATA 246" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x7DC++0x03 line.long 0x00 "MEM_DATA247,DATA 247" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x7E0++0x03 line.long 0x00 "MEM_DATA248,DATA 248" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x7E4++0x03 line.long 0x00 "MEM_DATA249,DATA 249" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x7E8++0x03 line.long 0x00 "MEM_DATA250,DATA 250" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x7EC++0x03 line.long 0x00 "MEM_DATA251,DATA 251" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x7F0++0x03 line.long 0x00 "MEM_DATA252,DATA 252" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x7F4++0x03 line.long 0x00 "MEM_DATA253,DATA 253" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x7F8++0x03 line.long 0x00 "MEM_DATA254,DATA 254" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x7FC++0x03 line.long 0x00 "MEM_DATA255,DATA 255" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x800++0x03 line.long 0x00 "MEM_DATA256,DATA 256" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x804++0x03 line.long 0x00 "MEM_DATA257,DATA 257" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x808++0x03 line.long 0x00 "MEM_DATA258,DATA 258" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x80C++0x03 line.long 0x00 "MEM_DATA259,DATA 259" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x810++0x03 line.long 0x00 "MEM_DATA260,DATA 260" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x814++0x03 line.long 0x00 "MEM_DATA261,DATA 261" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x818++0x03 line.long 0x00 "MEM_DATA262,DATA 262" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x81C++0x03 line.long 0x00 "MEM_DATA263,DATA 263" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x820++0x03 line.long 0x00 "MEM_DATA264,DATA 264" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x824++0x03 line.long 0x00 "MEM_DATA265,DATA 265" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x828++0x03 line.long 0x00 "MEM_DATA266,DATA 266" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x82C++0x03 line.long 0x00 "MEM_DATA267,DATA 267" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x830++0x03 line.long 0x00 "MEM_DATA268,DATA 268" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x834++0x03 line.long 0x00 "MEM_DATA269,DATA 269" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x838++0x03 line.long 0x00 "MEM_DATA270,DATA 270" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x83C++0x03 line.long 0x00 "MEM_DATA271,DATA 271" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x840++0x03 line.long 0x00 "MEM_DATA272,DATA 272" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x844++0x03 line.long 0x00 "MEM_DATA273,DATA 273" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x848++0x03 line.long 0x00 "MEM_DATA274,DATA 274" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x84C++0x03 line.long 0x00 "MEM_DATA275,DATA 275" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x850++0x03 line.long 0x00 "MEM_DATA276,DATA 276" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x854++0x03 line.long 0x00 "MEM_DATA277,DATA 277" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x858++0x03 line.long 0x00 "MEM_DATA278,DATA 278" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x85C++0x03 line.long 0x00 "MEM_DATA279,DATA 279" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x860++0x03 line.long 0x00 "MEM_DATA280,DATA 280" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x864++0x03 line.long 0x00 "MEM_DATA281,DATA 281" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x868++0x03 line.long 0x00 "MEM_DATA282,DATA 282" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x86C++0x03 line.long 0x00 "MEM_DATA283,DATA 283" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x870++0x03 line.long 0x00 "MEM_DATA284,DATA 284" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x874++0x03 line.long 0x00 "MEM_DATA285,DATA 285" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x878++0x03 line.long 0x00 "MEM_DATA286,DATA 286" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x87C++0x03 line.long 0x00 "MEM_DATA287,DATA 287" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x880++0x03 line.long 0x00 "MEM_DATA288,DATA 288" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x884++0x03 line.long 0x00 "MEM_DATA289,DATA 289" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x888++0x03 line.long 0x00 "MEM_DATA290,DATA 290" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x88C++0x03 line.long 0x00 "MEM_DATA291,DATA 291" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x890++0x03 line.long 0x00 "MEM_DATA292,DATA 292" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x894++0x03 line.long 0x00 "MEM_DATA293,DATA 293" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x898++0x03 line.long 0x00 "MEM_DATA294,DATA 294" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x89C++0x03 line.long 0x00 "MEM_DATA295,DATA 295" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x8A0++0x03 line.long 0x00 "MEM_DATA296,DATA 296" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x8A4++0x03 line.long 0x00 "MEM_DATA297,DATA 297" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x8A8++0x03 line.long 0x00 "MEM_DATA298,DATA 298" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x8AC++0x03 line.long 0x00 "MEM_DATA299,DATA 299" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x8B0++0x03 line.long 0x00 "MEM_DATA300,DATA 300" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x8B4++0x03 line.long 0x00 "MEM_DATA301,DATA 301" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x8B8++0x03 line.long 0x00 "MEM_DATA302,DATA 302" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x8BC++0x03 line.long 0x00 "MEM_DATA303,DATA 303" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x8C0++0x03 line.long 0x00 "MEM_DATA304,DATA 304" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x8C4++0x03 line.long 0x00 "MEM_DATA305,DATA 305" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x8C8++0x03 line.long 0x00 "MEM_DATA306,DATA 306" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x8CC++0x03 line.long 0x00 "MEM_DATA307,DATA 307" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x8D0++0x03 line.long 0x00 "MEM_DATA308,DATA 308" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x8D4++0x03 line.long 0x00 "MEM_DATA309,DATA 309" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x8D8++0x03 line.long 0x00 "MEM_DATA310,DATA 310" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x8DC++0x03 line.long 0x00 "MEM_DATA311,DATA 311" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x8E0++0x03 line.long 0x00 "MEM_DATA312,DATA 312" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x8E4++0x03 line.long 0x00 "MEM_DATA313,DATA 313" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x8E8++0x03 line.long 0x00 "MEM_DATA314,DATA 314" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x8EC++0x03 line.long 0x00 "MEM_DATA315,DATA 315" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x8F0++0x03 line.long 0x00 "MEM_DATA316,DATA 316" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x8F4++0x03 line.long 0x00 "MEM_DATA317,DATA 317" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x8F8++0x03 line.long 0x00 "MEM_DATA318,DATA 318" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x8FC++0x03 line.long 0x00 "MEM_DATA319,DATA 319" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x900++0x03 line.long 0x00 "MEM_DATA320,DATA 320" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x904++0x03 line.long 0x00 "MEM_DATA321,DATA 321" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x908++0x03 line.long 0x00 "MEM_DATA322,DATA 322" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x90C++0x03 line.long 0x00 "MEM_DATA323,DATA 323" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x910++0x03 line.long 0x00 "MEM_DATA324,DATA 324" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x914++0x03 line.long 0x00 "MEM_DATA325,DATA 325" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x918++0x03 line.long 0x00 "MEM_DATA326,DATA 326" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x91C++0x03 line.long 0x00 "MEM_DATA327,DATA 327" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x920++0x03 line.long 0x00 "MEM_DATA328,DATA 328" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x924++0x03 line.long 0x00 "MEM_DATA329,DATA 329" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x928++0x03 line.long 0x00 "MEM_DATA330,DATA 330" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x92C++0x03 line.long 0x00 "MEM_DATA331,DATA 331" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x930++0x03 line.long 0x00 "MEM_DATA332,DATA 332" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x934++0x03 line.long 0x00 "MEM_DATA333,DATA 333" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x938++0x03 line.long 0x00 "MEM_DATA334,DATA 334" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x93C++0x03 line.long 0x00 "MEM_DATA335,DATA 335" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x940++0x03 line.long 0x00 "MEM_DATA336,DATA 336" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x944++0x03 line.long 0x00 "MEM_DATA337,DATA 337" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x948++0x03 line.long 0x00 "MEM_DATA338,DATA 338" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x94C++0x03 line.long 0x00 "MEM_DATA339,DATA 339" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x950++0x03 line.long 0x00 "MEM_DATA340,DATA 340" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x954++0x03 line.long 0x00 "MEM_DATA341,DATA 341" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x958++0x03 line.long 0x00 "MEM_DATA342,DATA 342" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x95C++0x03 line.long 0x00 "MEM_DATA343,DATA 343" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x960++0x03 line.long 0x00 "MEM_DATA344,DATA 344" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x964++0x03 line.long 0x00 "MEM_DATA345,DATA 345" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x968++0x03 line.long 0x00 "MEM_DATA346,DATA 346" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x96C++0x03 line.long 0x00 "MEM_DATA347,DATA 347" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x970++0x03 line.long 0x00 "MEM_DATA348,DATA 348" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x974++0x03 line.long 0x00 "MEM_DATA349,DATA 349" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x978++0x03 line.long 0x00 "MEM_DATA350,DATA 350" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x97C++0x03 line.long 0x00 "MEM_DATA351,DATA 351" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x980++0x03 line.long 0x00 "MEM_DATA352,DATA 352" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x984++0x03 line.long 0x00 "MEM_DATA353,DATA 353" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x988++0x03 line.long 0x00 "MEM_DATA354,DATA 354" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x98C++0x03 line.long 0x00 "MEM_DATA355,DATA 355" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x990++0x03 line.long 0x00 "MEM_DATA356,DATA 356" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x994++0x03 line.long 0x00 "MEM_DATA357,DATA 357" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x998++0x03 line.long 0x00 "MEM_DATA358,DATA 358" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x99C++0x03 line.long 0x00 "MEM_DATA359,DATA 359" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x9A0++0x03 line.long 0x00 "MEM_DATA360,DATA 360" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x9A4++0x03 line.long 0x00 "MEM_DATA361,DATA 361" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x9A8++0x03 line.long 0x00 "MEM_DATA362,DATA 362" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x9AC++0x03 line.long 0x00 "MEM_DATA363,DATA 363" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x9B0++0x03 line.long 0x00 "MEM_DATA364,DATA 364" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x9B4++0x03 line.long 0x00 "MEM_DATA365,DATA 365" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x9B8++0x03 line.long 0x00 "MEM_DATA366,DATA 366" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x9BC++0x03 line.long 0x00 "MEM_DATA367,DATA 367" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x9C0++0x03 line.long 0x00 "MEM_DATA368,DATA 368" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x9C4++0x03 line.long 0x00 "MEM_DATA369,DATA 369" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x9C8++0x03 line.long 0x00 "MEM_DATA370,DATA 370" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x9CC++0x03 line.long 0x00 "MEM_DATA371,DATA 371" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x9D0++0x03 line.long 0x00 "MEM_DATA372,DATA 372" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x9D4++0x03 line.long 0x00 "MEM_DATA373,DATA 373" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x9D8++0x03 line.long 0x00 "MEM_DATA374,DATA 374" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x9DC++0x03 line.long 0x00 "MEM_DATA375,DATA 375" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x9E0++0x03 line.long 0x00 "MEM_DATA376,DATA 376" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x9E4++0x03 line.long 0x00 "MEM_DATA377,DATA 377" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x9E8++0x03 line.long 0x00 "MEM_DATA378,DATA 378" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x9EC++0x03 line.long 0x00 "MEM_DATA379,DATA 379" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x9F0++0x03 line.long 0x00 "MEM_DATA380,DATA 380" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x9F4++0x03 line.long 0x00 "MEM_DATA381,DATA 381" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x9F8++0x03 line.long 0x00 "MEM_DATA382,DATA 382" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0x9FC++0x03 line.long 0x00 "MEM_DATA383,DATA 383" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xA00++0x03 line.long 0x00 "MEM_DATA384,DATA 384" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xA04++0x03 line.long 0x00 "MEM_DATA385,DATA 385" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xA08++0x03 line.long 0x00 "MEM_DATA386,DATA 386" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xA0C++0x03 line.long 0x00 "MEM_DATA387,DATA 387" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xA10++0x03 line.long 0x00 "MEM_DATA388,DATA 388" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xA14++0x03 line.long 0x00 "MEM_DATA389,DATA 389" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xA18++0x03 line.long 0x00 "MEM_DATA390,DATA 390" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xA1C++0x03 line.long 0x00 "MEM_DATA391,DATA 391" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xA20++0x03 line.long 0x00 "MEM_DATA392,DATA 392" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xA24++0x03 line.long 0x00 "MEM_DATA393,DATA 393" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xA28++0x03 line.long 0x00 "MEM_DATA394,DATA 394" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xA2C++0x03 line.long 0x00 "MEM_DATA395,DATA 395" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xA30++0x03 line.long 0x00 "MEM_DATA396,DATA 396" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xA34++0x03 line.long 0x00 "MEM_DATA397,DATA 397" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xA38++0x03 line.long 0x00 "MEM_DATA398,DATA 398" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xA3C++0x03 line.long 0x00 "MEM_DATA399,DATA 399" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xA40++0x03 line.long 0x00 "MEM_DATA400,DATA 400" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xA44++0x03 line.long 0x00 "MEM_DATA401,DATA 401" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xA48++0x03 line.long 0x00 "MEM_DATA402,DATA 402" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xA4C++0x03 line.long 0x00 "MEM_DATA403,DATA 403" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xA50++0x03 line.long 0x00 "MEM_DATA404,DATA 404" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xA54++0x03 line.long 0x00 "MEM_DATA405,DATA 405" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xA58++0x03 line.long 0x00 "MEM_DATA406,DATA 406" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xA5C++0x03 line.long 0x00 "MEM_DATA407,DATA 407" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xA60++0x03 line.long 0x00 "MEM_DATA408,DATA 408" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xA64++0x03 line.long 0x00 "MEM_DATA409,DATA 409" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xA68++0x03 line.long 0x00 "MEM_DATA410,DATA 410" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xA6C++0x03 line.long 0x00 "MEM_DATA411,DATA 411" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xA70++0x03 line.long 0x00 "MEM_DATA412,DATA 412" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xA74++0x03 line.long 0x00 "MEM_DATA413,DATA 413" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xA78++0x03 line.long 0x00 "MEM_DATA414,DATA 414" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xA7C++0x03 line.long 0x00 "MEM_DATA415,DATA 415" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xA80++0x03 line.long 0x00 "MEM_DATA416,DATA 416" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xA84++0x03 line.long 0x00 "MEM_DATA417,DATA 417" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xA88++0x03 line.long 0x00 "MEM_DATA418,DATA 418" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xA8C++0x03 line.long 0x00 "MEM_DATA419,DATA 419" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xA90++0x03 line.long 0x00 "MEM_DATA420,DATA 420" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xA94++0x03 line.long 0x00 "MEM_DATA421,DATA 421" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xA98++0x03 line.long 0x00 "MEM_DATA422,DATA 422" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xA9C++0x03 line.long 0x00 "MEM_DATA423,DATA 423" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xAA0++0x03 line.long 0x00 "MEM_DATA424,DATA 424" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xAA4++0x03 line.long 0x00 "MEM_DATA425,DATA 425" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xAA8++0x03 line.long 0x00 "MEM_DATA426,DATA 426" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xAAC++0x03 line.long 0x00 "MEM_DATA427,DATA 427" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xAB0++0x03 line.long 0x00 "MEM_DATA428,DATA 428" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xAB4++0x03 line.long 0x00 "MEM_DATA429,DATA 429" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xAB8++0x03 line.long 0x00 "MEM_DATA430,DATA 430" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xABC++0x03 line.long 0x00 "MEM_DATA431,DATA 431" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xAC0++0x03 line.long 0x00 "MEM_DATA432,DATA 432" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xAC4++0x03 line.long 0x00 "MEM_DATA433,DATA 433" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xAC8++0x03 line.long 0x00 "MEM_DATA434,DATA 434" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xACC++0x03 line.long 0x00 "MEM_DATA435,DATA 435" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xAD0++0x03 line.long 0x00 "MEM_DATA436,DATA 436" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xAD4++0x03 line.long 0x00 "MEM_DATA437,DATA 437" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xAD8++0x03 line.long 0x00 "MEM_DATA438,DATA 438" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xADC++0x03 line.long 0x00 "MEM_DATA439,DATA 439" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xAE0++0x03 line.long 0x00 "MEM_DATA440,DATA 440" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xAE4++0x03 line.long 0x00 "MEM_DATA441,DATA 441" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xAE8++0x03 line.long 0x00 "MEM_DATA442,DATA 442" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xAEC++0x03 line.long 0x00 "MEM_DATA443,DATA 443" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xAF0++0x03 line.long 0x00 "MEM_DATA444,DATA 444" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xAF4++0x03 line.long 0x00 "MEM_DATA445,DATA 445" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xAF8++0x03 line.long 0x00 "MEM_DATA446,DATA 446" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xAFC++0x03 line.long 0x00 "MEM_DATA447,DATA 447" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xB00++0x03 line.long 0x00 "MEM_DATA448,DATA 448" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xB04++0x03 line.long 0x00 "MEM_DATA449,DATA 449" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xB08++0x03 line.long 0x00 "MEM_DATA450,DATA 450" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xB0C++0x03 line.long 0x00 "MEM_DATA451,DATA 451" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xB10++0x03 line.long 0x00 "MEM_DATA452,DATA 452" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xB14++0x03 line.long 0x00 "MEM_DATA453,DATA 453" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xB18++0x03 line.long 0x00 "MEM_DATA454,DATA 454" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xB1C++0x03 line.long 0x00 "MEM_DATA455,DATA 455" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xB20++0x03 line.long 0x00 "MEM_DATA456,DATA 456" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xB24++0x03 line.long 0x00 "MEM_DATA457,DATA 457" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xB28++0x03 line.long 0x00 "MEM_DATA458,DATA 458" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xB2C++0x03 line.long 0x00 "MEM_DATA459,DATA 459" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xB30++0x03 line.long 0x00 "MEM_DATA460,DATA 460" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xB34++0x03 line.long 0x00 "MEM_DATA461,DATA 461" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xB38++0x03 line.long 0x00 "MEM_DATA462,DATA 462" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xB3C++0x03 line.long 0x00 "MEM_DATA463,DATA 463" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xB40++0x03 line.long 0x00 "MEM_DATA464,DATA 464" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xB44++0x03 line.long 0x00 "MEM_DATA465,DATA 465" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xB48++0x03 line.long 0x00 "MEM_DATA466,DATA 466" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xB4C++0x03 line.long 0x00 "MEM_DATA467,DATA 467" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xB50++0x03 line.long 0x00 "MEM_DATA468,DATA 468" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xB54++0x03 line.long 0x00 "MEM_DATA469,DATA 469" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xB58++0x03 line.long 0x00 "MEM_DATA470,DATA 470" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xB5C++0x03 line.long 0x00 "MEM_DATA471,DATA 471" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xB60++0x03 line.long 0x00 "MEM_DATA472,DATA 472" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xB64++0x03 line.long 0x00 "MEM_DATA473,DATA 473" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xB68++0x03 line.long 0x00 "MEM_DATA474,DATA 474" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xB6C++0x03 line.long 0x00 "MEM_DATA475,DATA 475" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xB70++0x03 line.long 0x00 "MEM_DATA476,DATA 476" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xB74++0x03 line.long 0x00 "MEM_DATA477,DATA 477" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xB78++0x03 line.long 0x00 "MEM_DATA478,DATA 478" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xB7C++0x03 line.long 0x00 "MEM_DATA479,DATA 479" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xB80++0x03 line.long 0x00 "MEM_DATA480,DATA 480" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xB84++0x03 line.long 0x00 "MEM_DATA481,DATA 481" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xB88++0x03 line.long 0x00 "MEM_DATA482,DATA 482" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xB8C++0x03 line.long 0x00 "MEM_DATA483,DATA 483" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xB90++0x03 line.long 0x00 "MEM_DATA484,DATA 484" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xB94++0x03 line.long 0x00 "MEM_DATA485,DATA 485" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xB98++0x03 line.long 0x00 "MEM_DATA486,DATA 486" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xB9C++0x03 line.long 0x00 "MEM_DATA487,DATA 487" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xBA0++0x03 line.long 0x00 "MEM_DATA488,DATA 488" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xBA4++0x03 line.long 0x00 "MEM_DATA489,DATA 489" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xBA8++0x03 line.long 0x00 "MEM_DATA490,DATA 490" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xBAC++0x03 line.long 0x00 "MEM_DATA491,DATA 491" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xBB0++0x03 line.long 0x00 "MEM_DATA492,DATA 492" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xBB4++0x03 line.long 0x00 "MEM_DATA493,DATA 493" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xBB8++0x03 line.long 0x00 "MEM_DATA494,DATA 494" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xBBC++0x03 line.long 0x00 "MEM_DATA495,DATA 495" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xBC0++0x03 line.long 0x00 "MEM_DATA496,DATA 496" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xBC4++0x03 line.long 0x00 "MEM_DATA497,DATA 497" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xBC8++0x03 line.long 0x00 "MEM_DATA498,DATA 498" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xBCC++0x03 line.long 0x00 "MEM_DATA499,DATA 499" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xBD0++0x03 line.long 0x00 "MEM_DATA500,DATA 500" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xBD4++0x03 line.long 0x00 "MEM_DATA501,DATA 501" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xBD8++0x03 line.long 0x00 "MEM_DATA502,DATA 502" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xBDC++0x03 line.long 0x00 "MEM_DATA503,DATA 503" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xBE0++0x03 line.long 0x00 "MEM_DATA504,DATA 504" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xBE4++0x03 line.long 0x00 "MEM_DATA505,DATA 505" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xBE8++0x03 line.long 0x00 "MEM_DATA506,DATA 506" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xBEC++0x03 line.long 0x00 "MEM_DATA507,DATA 507" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xBF0++0x03 line.long 0x00 "MEM_DATA508,DATA 508" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xBF4++0x03 line.long 0x00 "MEM_DATA509,DATA 509" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xBF8++0x03 line.long 0x00 "MEM_DATA510,DATA 510" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" group.long 0xBFC++0x03 line.long 0x00 "MEM_DATA511,DATA 511" hexmask.long.byte 0x00 0.--7. 1. " DR ,Data Register for EP" tree.end textline " " rgroup.long 0x1060++0x03 line.long 0x00 "SOF16,Start Of Frame Register" hexmask.long.word 0x00 0.--10. 1. " FRAME_NUMBER16 ,The frame number (11b)" rgroup.long 0x1080++0x03 line.long 0x00 "OSCLK_DR16,Oscillator lock data register" hexmask.long.word 0x00 0.--14. 1. " ADDER16 ,oscillator locking circuits adder output" group.long 0x1210++0x03 line.long 0x00 "ARB_RW1_WA16,Endpoint Write Address value" hexmask.long.word 0x00 0.--8. 1. " WA16 ,Write Address for EP" group.long (0x1210+0x08)++0x03 line.long 0x00 "ARB_RW1_RA16,Endpoint Read Address value" hexmask.long.word 0x00 0.--8. 1. " RA16 ,Read Address for EP" group.long (0x1210+0x10)++0x03 line.long 0x00 "ARB_RW1_DR16,Endpoint Data Register" hexmask.long.word 0x00 0.--15. 1. " DR16 ,Data Register for EP" group.long 0x1250++0x03 line.long 0x00 "ARB_RW2_WA16,Endpoint Write Address value" hexmask.long.word 0x00 0.--8. 1. " WA16 ,Write Address for EP" group.long (0x1250+0x08)++0x03 line.long 0x00 "ARB_RW2_RA16,Endpoint Read Address value" hexmask.long.word 0x00 0.--8. 1. " RA16 ,Read Address for EP" group.long (0x1250+0x10)++0x03 line.long 0x00 "ARB_RW2_DR16,Endpoint Data Register" hexmask.long.word 0x00 0.--15. 1. " DR16 ,Data Register for EP" group.long 0x1290++0x03 line.long 0x00 "ARB_RW3_WA16,Endpoint Write Address value" hexmask.long.word 0x00 0.--8. 1. " WA16 ,Write Address for EP" group.long (0x1290+0x08)++0x03 line.long 0x00 "ARB_RW3_RA16,Endpoint Read Address value" hexmask.long.word 0x00 0.--8. 1. " RA16 ,Read Address for EP" group.long (0x1290+0x10)++0x03 line.long 0x00 "ARB_RW3_DR16,Endpoint Data Register" hexmask.long.word 0x00 0.--15. 1. " DR16 ,Data Register for EP" group.long 0x12B0++0x03 line.long 0x00 "CWA16,Common Area Write Address" hexmask.long.word 0x00 0.--8. 1. " CWA16 ,Write Address for Common Area" group.long 0x12D0++0x03 line.long 0x00 "ARB_RW4_WA16,Endpoint Write Address value" hexmask.long.word 0x00 0.--8. 1. " WA16 ,Write Address for EP" group.long 0x12D8++0x03 line.long 0x00 "ARB_RW4_RA16,Endpoint Read Address value" hexmask.long.word 0x00 0.--8. 1. " RA16 ,Read Address for EP" group.long 0x12E0++0x03 line.long 0x00 "ARB_RW4_DR16,Endpoint Data Register" hexmask.long.word 0x00 0.--15. 1. " DR16 ,Data Register for EP" group.long 0x12F0++0x03 line.long 0x00 "DMA_THRES16,DMA Burst / Threshold Configuration" hexmask.long.word 0x00 0.--8. 1. " DMA_THS16 ,DMA Threshold count" group.long 0x1310++0x03 line.long 0x00 "ARB_RW5_WA16,Endpoint Write Address value" hexmask.long.word 0x00 0.--8. 1. " WA16 ,Write Address for EP" group.long (0x1310+0x08)++0x03 line.long 0x00 "ARB_RW5_RA16,Read Address for EP" hexmask.long.word 0x00 0.--8. 1. " RA16 ,Read Address for EP" group.long (0x1310+0x10)++0x03 line.long 0x00 "ARB_RW5_DR16,Endpoint Data Register" hexmask.long.word 0x00 0.--15. 1. " DR16 ,Data Register for EP" group.long 0x1350++0x03 line.long 0x00 "ARB_RW5_WA16,Endpoint Write Address value" hexmask.long.word 0x00 0.--8. 1. " WA16 ,Write Address for EP" group.long (0x1350+0x08)++0x03 line.long 0x00 "ARB_RW5_RA16,Read Address for EP" hexmask.long.word 0x00 0.--8. 1. " RA16 ,Read Address for EP" group.long (0x1350+0x10)++0x03 line.long 0x00 "ARB_RW5_DR16,Endpoint Data Register" hexmask.long.word 0x00 0.--15. 1. " DR16 ,Data Register for EP" group.long 0x1390++0x03 line.long 0x00 "ARB_RW5_WA16,Endpoint Write Address value" hexmask.long.word 0x00 0.--8. 1. " WA16 ,Write Address for EP" group.long (0x1390+0x08)++0x03 line.long 0x00 "ARB_RW5_RA16,Read Address for EP" hexmask.long.word 0x00 0.--8. 1. " RA16 ,Read Address for EP" group.long (0x1390+0x10)++0x03 line.long 0x00 "ARB_RW5_DR16,Endpoint Data Register" hexmask.long.word 0x00 0.--15. 1. " DR16 ,Data Register for EP" group.long 0x13D0++0x03 line.long 0x00 "ARB_RW5_WA16,Endpoint Write Address value" hexmask.long.word 0x00 0.--8. 1. " WA16 ,Write Address for EP" group.long (0x13D0+0x08)++0x03 line.long 0x00 "ARB_RW5_RA16,Read Address for EP" hexmask.long.word 0x00 0.--8. 1. " RA16 ,Read Address for EP" group.long (0x13D0+0x10)++0x03 line.long 0x00 "ARB_RW5_DR16,Endpoint Data Register" hexmask.long.word 0x00 0.--15. 1. " DR16 ,Data Register for EP" width 0x0B tree.end tree "USB Control registers" base ad:0x402C2000 width 30. if (((per.l(ad:0x402C2000))&0x80000000)==0x80000000) group.long 0x00++0x03 line.long 0x00 "USB_POWER_CTRL,Power Control Register" bitfld.long 0x00 31. " ENABLE ,Enable of PHY and charger detector" "Disabled,Enabled" rbitfld.long 0x00 30. " ENABLE_CHGDET ,Enables the charger detection circuitry" "Disabled,Enabled" rbitfld.long 0x00 29. " ENABLE_DMO ,Enables the single ended receiver on D-" "Disabled,Enabled" textline " " rbitfld.long 0x00 28. " ENABLE_DPO ,Enables the single ended receiver on D+" "Disabled,Enabled" rbitfld.long 0x00 27. " ENABLE_RCVR ,Enables the differential USB receiver" "Disabled,Enabled" rbitfld.long 0x00 26. " ENABLE_VBUS_PULLDOWN ,Enables the weak pull down on the VBUS" "Disabled,Enabled" textline " " rbitfld.long 0x00 25. " ENABLE_DM_PULLDOWN ,Enables the ~15k pull down on the DM" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " CHDET_PWR_CTL ,Power programmability for bandgap voltage buffer in the charger detect block" "Low_power_mode,Bandgap_voltage_buffer,Bandgap_voltage_buffer,Bandgap_voltage_buffer" rbitfld.long 0x00 4. " ISOLATE ,Isolates the PHY outputs" "Disabled,Enabled" textline " " rbitfld.long 0x00 3. " SUSPEND_DEL ,Delayed version of SUSPEND" "Disabled,Enabled" rbitfld.long 0x00 2. " SUSPEND ,Put PHY into suspend mode" "Disabled,Enabled" rbitfld.long 0x00 0.--1. " VBUS_VALID_OVR ,Overrides the value received from the GPIO input buffer connected to VBUS" "Vbus_valid_0,Vbus_valid_1,Vbus_valid_gpio,Vbus_valid_phy_detector" else group.long 0x00++0x03 line.long 0x00 "USB_POWER_CTRL,Power Control Register" bitfld.long 0x00 31. " ENABLE ,Enable of PHY and charger detector" "Disabled,Enabled" bitfld.long 0x00 30. " ENABLE_CHGDET ,Enables the charger detection circuitry" "Disabled,Enabled" bitfld.long 0x00 29. " ENABLE_DMO ,Enables the single ended receiver on D-" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " ENABLE_DPO ,Enables the single ended receiver on D+" "Disabled,Enabled" bitfld.long 0x00 27. " ENABLE_RCVR ,Enables the differential USB receiver" "Disabled,Enabled" bitfld.long 0x00 26. " ENABLE_VBUS_PULLDOWN ,Enables the weak pull down on the VBUS" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " ENABLE_DM_PULLDOWN ,Enables the ~15k pull down on the DM" "Disabled,Enabled" bitfld.long 0x00 5.--6. " CHDET_PWR_CTL ,Power programmability for bandgap voltage buffer in the charger detect block" "Low_power_mode,Bandgap_voltage_buffer,Bandgap_voltage_buffer,Bandgap_voltage_buffer" bitfld.long 0x00 4. " ISOLATE ,Isolates the PHY outputs" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " SUSPEND_DEL ,Delayed version of SUSPEND" "Disabled,Enabled" bitfld.long 0x00 2. " SUSPEND ,Put PHY into suspend mode" "Disabled,Enabled" bitfld.long 0x00 0.--1. " VBUS_VALID_OVR ,Overrides the value received from the GPIO input buffer connected to VBUS" "Vbus_valid_0,Vbus_valid_1,Vbus_valid_gpio,Vbus_valid_phy_detector" endif if (((per.l(ad:0x402C2000+0x04))&0x20)==0x20) group.long 0x04++0x03 line.long 0x00 "USB_CHGDET_CTRL,Charger Detection Control Register" bitfld.long 0x00 31. " COMP_OUT ,Output of the primary/secondary detection comparator" "Not filtered,Debounced" bitfld.long 0x00 6. " DCD_SRC_EN ,Enable the data contact detect current source on D+" "Disabled,Enabled" bitfld.long 0x00 5. " REF_EN ,Enable the primary/secondary reference driver" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " REF_DM ,Connect the primary/secondary detection reference driver to D-" "Not connected,Connected" bitfld.long 0x00 3. " REF_DP ,Connect the primary/secondary detection reference driver to D+" "Not connected,Connected" bitfld.long 0x00 2. " COMP_EN ,Enable the primary/secondary detection comparator and current sink" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " COMP_DM ,Connect the primary/secondary detection comparator and current sink to D-" "Not connected,Connected" bitfld.long 0x00 0. " COMP_DP ,Connect the primary/secondary detection comparator and current sink to D+" "Not connected,Connected" else group.long 0x04++0x03 line.long 0x00 "USB_CHGDET_CTRL,Charger Detection Control Register" bitfld.long 0x00 31. " COMP_OUT ,Output of the primary/secondary detection comparator" "Not filtered,Debounced" bitfld.long 0x00 6. " DCD_SRC_EN ,Enable the data contact detect current source on D+" "Disabled,Enabled" bitfld.long 0x00 5. " REF_EN ,Enable the primary/secondary reference driver" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " REF_DM ,Connect the primary/secondary detection reference driver to D-" "Not connected,Connected" bitfld.long 0x00 3. " REF_DP ,Connect the primary/secondary detection reference driver to D+" "Not connected,Connected" rbitfld.long 0x00 2. " COMP_EN ,Enable the primary/secondary detection comparator and current sink" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " COMP_DM ,Connect the primary/secondary detection comparator and current sink to D-" "Not connected,Connected" bitfld.long 0x00 0. " COMP_DP ,Connect the primary/secondary detection comparator and current sink to D+" "Not connected,Connected" endif if (((per.l(ad:0x402C0048))&0x20)==0x20) group.long 0x08++0x03 line.long 0x00 "USB_USBIO_CTRL,USB IO Control Register" bitfld.long 0x00 3.--5. " DM_M ,The GPIO drive mode for DM IO pad" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " DM_P ,The GPIO drive mode for DP IO pad" "OFF,INPUT,0_PU,0_Z,0_1,?..." else group.long 0x08++0x03 line.long 0x00 "USB_USBIO_CTRL,USB IO Control Register" bitfld.long 0x00 3.--5. " DM_M ,GPIO drive mode for DM IO pad" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 0.--2. " DM_P ,GPIO drive mode for DP IO pad" "OFF,INPUT,0_PU,0_Z,0_1,?..." endif group.long 0x0C++0x03 line.long 0x00 "USB_FLOW_CTRL,Flow Control Register" bitfld.long 0x00 7. " EP8_ERR_RESP ,End point 8 error response" "No error,Error" bitfld.long 0x00 6. " EP7_ERR_RESP ,End point 7 error response" "No error,Error" bitfld.long 0x00 5. " EP6_ERR_RESP ,End point 6 error response" "No error,Error" textline " " bitfld.long 0x00 4. " EP5_ERR_RESP ,End point 5 error response" "No error,Error" bitfld.long 0x00 3. " EP4_ERR_RESP ,End point 4 error response" "No error,Error" bitfld.long 0x00 2. " EP3_ERR_RESP ,End point 3 error response" "No error,Error" textline " " bitfld.long 0x00 1. " EP2_ERR_RESP ,End point 2 error response" "No error,Error" bitfld.long 0x00 0. " EP1_ERR_RESP ,End point 1 error response" "No error,Error" if (((per.l(ad:0x402C2000+0x10))&0x01)==0x01) group.long 0x10++0x03 line.long 0x00 "USB_LPM_CTRL,LPM Control Register" bitfld.long 0x00 4. " SUB_RESP ,Enable a STALL response for all undefined SubPIDs" "Disabled,Enabled" bitfld.long 0x00 2. " NYET_EN ,NYET enabled" "NAK,NYET" bitfld.long 0x00 1. " LPM_ACK_RESP ,LPM ACK response enable" "NYET/NAK,ACK" textline " " bitfld.long 0x00 0. " LPM_EN ,LPM enable" "Disabled,Enabled" else group.long 0x10++0x03 line.long 0x00 "USB_LPM_CTRL,LPM Control Register" bitfld.long 0x00 4. " SUB_RESP ,Enable a STALL response for all undefined SubPIDs" "Disabled,Enabled" rbitfld.long 0x00 2. " NYET_EN ,NYET enabled" "NAK,NYET" rbitfld.long 0x00 1. " LPM_ACK_RESP ,LPM ACK response enable" "NYET/NAK,ACK" textline " " bitfld.long 0x00 0. " LPM_EN ,LPM enable" "Disabled,Enabled" endif rgroup.long 0x14++0x03 line.long 0x00 "USB_LPM_STAT,LPM Status Register" bitfld.long 0x00 4. " LPM_REMOTEWAKE ,Device remote wake" "Remote_wake,Wake_host" bitfld.long 0x00 0.--3. " LPM_BESL ,Best effort service latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x20++0x0B line.long 0x00 "USB_INTR_SIE,USB SOF/BUS RESET And EP0 Interrupt Status" eventfld.long 0x00 4. " RESUME_INTR ,Interrupt status for resume" "No interrupt,Interrupt" eventfld.long 0x00 3. " LPM_INTR ,Interrupt status for LPM" "No interrupt,Interrupt" eventfld.long 0x00 2. " EP0_INTR ,Interrupt status for EP0" "No interrupt,Interrupt" textline " " eventfld.long 0x00 1. " BUS_RESET_INTR ,Interrupt status for BUS RESET" "No interrupt,Interrupt" eventfld.long 0x00 0. " SOF_INTR ,Interrupt status for USB SOF" "No interrupt,Interrupt" line.long 0x04 "USB_INTR_SIE_SET,USB SOF/BUS RESET And EP0 Interrupt Set" bitfld.long 0x04 4. " RESUME_INTR_SET ,Resume interrupt set" "No interrupt,Interrupt" bitfld.long 0x04 3. " LPM_INTR_SET ,LPM interrupt set" "No interrupt,Interrupt" bitfld.long 0x04 2. " EP0_INTR_SET ,EP0 interrupt set" "No interrupt,Interrupt" textline " " bitfld.long 0x04 1. " BUS_RESET_INTR_SET ,BUS reset interrupt set" "No interrupt,Interrupt" bitfld.long 0x04 0. " SOF_INTR_SET ,USB SOF interrupt set" "No interrupt,Interrupt" line.long 0x08 "USB_INTR_SIE_MASK,USB SOF/BUS RESET And EP0 Interrupt Mask" bitfld.long 0x08 4. " RESUME_INTR_MASK ,Resume Interrupt Mask" "No Interrupt,Interrupt" bitfld.long 0x08 3. " LPM_INTR_MASK ,LPM Interrupt Mask" "No Interrupt,Interrupt" bitfld.long 0x08 2. " EP0_INTR_MASK ,EP0 Interrupt Mask" "No Interrupt,Interrupt" textline " " bitfld.long 0x08 1. " BUS_RESET_INTR_MASK ,BUS Reset Interrupt Mask" "No Interrupt,Interrupt" bitfld.long 0x08 0. " SOF_INTR_MASK ,SOF Interrupt Mask" "No Interrupt,Interrupt" rgroup.long 0x2C++0x03 line.long 0x00 "USB_INTR_SIE_MASKED,USB SOF/BUS RESET And EP0 Interrupt Masked" bitfld.long 0x00 4. " RESUME_INTR_MASKED ,Resume Interrupt Masked" "No Interrupt,Interrupt" bitfld.long 0x00 3. " LPM_INTR_MASKED ,LPM Interrupt Masked" "No Interrupt,Interrupt" bitfld.long 0x00 2. " EP0_INTR_MASKED ,EP0 Interrupt Masked" "No Interrupt,Interrupt" textline " " bitfld.long 0x00 1. " BUS_RESET_INTR_MASKED , BUS Reset Interrupt Masked" "No Interrupt,Interrupt" bitfld.long 0x00 0. " SOF_INTR_MASKED ,SOF Interrupt Masked" "No Interrupt,Interrupt" group.long 0x30++0x03 line.long 0x00 "USB_INTR_LVL_SEL,Select Interrupt Level For Each Interrupt Source" bitfld.long 0x00 30.--31. " EP8_LVL_SEL ,EP8 Interrupt level select" "0,1,2,3" bitfld.long 0x00 28.--29. " EP7_LVL_SEL ,EP7 Interrupt level select" "0,1,2,3" bitfld.long 0x00 26.--27. " EP6_LVL_SEL ,EP6 Interrupt level select" "0,1,2,3" textline " " bitfld.long 0x00 24.--25. " EP5_LVL_SEL ,EP5 Interrupt level select" "0,1,2,3" bitfld.long 0x00 22.--23. " EP4_LVL_SEL ,EP4 Interrupt level select" "0,1,2,3" bitfld.long 0x00 20.--21. " EP3_LVL_SEL ,EP3 Interrupt level select" "0,1,2,3" textline " " bitfld.long 0x00 18.--19. " EP2_LVL_SEL ,EP2 Interrupt level select" "0,1,2,3" bitfld.long 0x00 16.--17. " EP1_LVL_SEL ,EP1 Interrupt level select" "0,1,2,3" bitfld.long 0x00 14.--15. " ARB_EP_LVL_SEL ,Arbiter Endpoint Interrupt level select" "0,1,2,3" textline " " bitfld.long 0x00 8.--9. " RESUME_LVL_SEL ,Resume Interrupt level select" "0,1,2,3" bitfld.long 0x00 6.--7. " LPM_LVL_SEL ,LPM Interrupt level select" "0,1,2,3" bitfld.long 0x00 4.--5. " EP0_LVL_SEL ,EP0 Interrupt level select" "0,1,2,3" textline " " bitfld.long 0x00 2.--3. " BUS_RESET_LVL_SEL ,BUS RESET Interrupt level select" "0,1,2,3" bitfld.long 0x00 0.--1. " SOF_LVL_SEL ,USB SOF Interrupt level select" "High,Medium,Low,?..." rgroup.long 0x34++0x0B line.long 0x00 "USB_INTR_CAUSE_HI,High Priority Interrupt Cause Register" bitfld.long 0x00 15. " EP8_INTR ,EP8 interrupt" "No interrupt,Interrupt" bitfld.long 0x00 14. " EP7_INTR ,EP7 interrupt" "No interrupt,Interrupt" bitfld.long 0x00 13. " EP6_INTR ,EP6 interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 12. " EP5_INTR ,EP5 interrupt" "No interrupt,Interrupt" bitfld.long 0x00 11. " EP4_INTR ,EP4 interrupt" "No interrupt,Interrupt" bitfld.long 0x00 10. " EP3_INTR ,EP3 interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 9. " EP2_INTR ,EP2 interrupt" "No interrupt,Interrupt" bitfld.long 0x00 8. " EP1_INTR ,EP1 interrupt" "No interrupt,Interrupt" bitfld.long 0x00 7. " ARB_EP_INTR ,Arbiter endpoint interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 4. " RESUME_INTR ,Resume interrupt" "No interrupt,Interrupt" bitfld.long 0x00 3. " LPM_INTR ,LPM interrupt" "No interrupt,Interrupt" bitfld.long 0x00 2. " EP0_INTR ,EP0 interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " BUS_RESET_INTR ,BUS RESET interrupt" "No interrupt,Interrupt" bitfld.long 0x00 0. " SOF_INTR ,USB SOF interrupt" "No interrupt,Interrupt" line.long 0x04 "USB_INTR_CAUSE_MED,Medium Priority Interrupt Cause Register" bitfld.long 0x04 15. " EP8_INTR ,EP8 interrupt" "No interrupt,Interrupt" bitfld.long 0x04 14. " EP7_INTR ,EP7 interrupt" "No interrupt,Interrupt" bitfld.long 0x04 13. " EP6_INTR ,EP6 interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x04 12. " EP5_INTR ,EP5 interrupt" "No interrupt,Interrupt" bitfld.long 0x04 11. " EP4_INTR ,EP4 interrupt" "No interrupt,Interrupt" bitfld.long 0x04 10. " EP3_INTR ,EP3 interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x04 9. " EP2_INTR ,EP2 interrupt" "No interrupt,Interrupt" bitfld.long 0x04 8. " EP1_INTR ,EP1 interrupt" "No interrupt,Interrupt" bitfld.long 0x04 7. " ARB_EP_INTR ,Arbiter endpoint interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x04 4. " RESUME_INTR ,Resume interrupt" "No interrupt,Interrupt" bitfld.long 0x04 3. " LPM_INTR ,LPM interrupt" "No interrupt,Interrupt" bitfld.long 0x04 2. " EP0_INTR ,EP0 interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x04 1. " BUS_RESET_INTR ,BUS RESET interrupt" "No interrupt,Interrupt" bitfld.long 0x04 0. " SOF_INTR ,USB SOF interrupt" "No interrupt,Interrupt" line.long 0x08 "USB_INTR_CAUSE_LO,Low priority interrupt Cause register" bitfld.long 0x08 15. " EP8_INTR ,EP8 interrupt" "No interrupt,Interrupt" bitfld.long 0x08 14. " EP7_INTR ,EP7 interrupt" "No interrupt,Interrupt" bitfld.long 0x08 13. " EP6_INTR ,EP6 interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x08 12. " EP5_INTR ,EP5 interrupt" "No interrupt,Interrupt" bitfld.long 0x08 11. " EP4_INTR ,EP4 interrupt" "No interrupt,Interrupt" bitfld.long 0x08 10. " EP3_INTR ,EP3 interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x08 9. " EP2_INTR ,EP2 interrupt" "No interrupt,Interrupt" bitfld.long 0x08 8. " EP1_INTR ,EP1 interrupt" "No interrupt,Interrupt" bitfld.long 0x08 7. " ARB_EP_INTR ,Arbiter endpoint interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x08 4. " RESUME_INTR ,Resume interrupt" "No interrupt,Interrupt" bitfld.long 0x08 3. " LPM_INTR ,LPM interrupt" "No interrupt,Interrupt" bitfld.long 0x08 2. " EP0_INTR ,EP0 interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x08 1. " BUS_RESET_INTR ,BUS RESET interrupt" "No interrupt,Interrupt" bitfld.long 0x08 0. " SOF_INTR ,USB SOF interrupt" "No interrupt,Interrupt" group.long 0xF00++0x1F line.long 0x00 "USB_PHY_TRIM0,PHY Trim Control Register 0" bitfld.long 0x00 0.--5. " TRIM_DP_R_REG ,Trim control for D+ pin poly termination resistors when PHY is in regulated mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "USB_PHY_TRIM1,PHY trim control register 1" bitfld.long 0x04 0.--5. " TRIM_DM_R_REG ,Trim control for D- pin poly termination resistors when PHY is in regulated mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "USB_PHY_TRIM2,PHY trim control register 2" bitfld.long 0x08 0.--5. " TRIM_DP_R_BYPASS ,Trim control for D+ pin poly termination resistors when PHY is in bypass mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "USB_PHY_TRIM3,PHY trim control register 3" bitfld.long 0x0C 0.--5. " TRIM_DM_R_BYPASS ,Trim control for D- pin poly termination resistors when PHY is in bypass mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "USB_CHGDET_TRIM,Charger detect trim values" bitfld.long 0x10 4.--6. " V600M_TRIM ,Trim bits for 600mV voltage reference" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0.--1. " V325M_TRIM ,Trim bits for 325mV voltage reference" "0,1,2,3" line.long 0x14 "USB_TRIM,trim values" bitfld.long 0x14 0.--1. " DM_PD_VAL ,Trim bit for DM Pull Down register" "0,1,2,3" line.long 0x18 "USB_USBIO_TRIM,trim values for IOs" bitfld.long 0x18 5. " X_DEC ,decrease of the USB crossover voltage" "Disabled,Enabled" bitfld.long 0x18 4. " X_INC ,increase of the USB crossover voltage" "Disabled,Enabled" bitfld.long 0x18 3. " MINC ,increases the USB edge matching ratio" "0,1" textline " " bitfld.long 0x18 2. " MDEC ,decreases the USB edge matching ratio" "0,1" bitfld.long 0x18 0.--1. " TRIM , Trim suspend mode resistor" "No effect,TRIM_LOWER,TRIM_HIGHER,TRIM_DONT_USE" if (((per.l(ad:0x402C2000+0xD000))&0x80000000)==0x80000000) group.long 0xD000++0x03 line.long 0x00 "USB_POWER_CTRL,Power Control Register" bitfld.long 0x00 31. " ENABLE ,Enable of PHY and charger detector" "Disabled,Enabled" rbitfld.long 0x00 30. " ENABLE_CHGDET ,Enables the charger detection circuitry" "Disabled,Enabled" rbitfld.long 0x00 29. " ENABLE_DMO ,Enables the single ended receiver on D-" "Disabled,Enabled" textline " " rbitfld.long 0x00 28. " ENABLE_DPO ,Enables the single ended receiver on D+" "Disabled,Enabled" rbitfld.long 0x00 27. " ENABLE_RCVR ,Enables the differential USB receiver" "Disabled,Enabled" rbitfld.long 0x00 26. " ENABLE_VBUS_PULLDOWN ,Enables the weak pull down on the VBUS" "Disabled,Enabled" textline " " rbitfld.long 0x00 25. " ENABLE_DM_PULLDOWN ,Enables the ~15k pull down on the DM" "Disabled,Enabled" rbitfld.long 0x00 5.--6. " CHDET_PWR_CTL ,Power programmability for bandgap voltage buffer in the charger detect block" "Low_power_mode,Bandgap_voltage_buffer,Bandgap_voltage_buffer,Bandgap_voltage_buffer" rbitfld.long 0x00 4. " ISOLATE ,Isolates the PHY outputs" "Disabled,Enabled" textline " " rbitfld.long 0x00 3. " SUSPEND_DEL ,Delayed version of SUSPEND" "Disabled,Enabled" rbitfld.long 0x00 2. " SUSPEND ,Put PHY into suspend mode" "Disabled,Enabled" rbitfld.long 0x00 0.--1. " VBUS_VALID_OVR ,Overrides the value received from the GPIO input buffer connected to VBUS" "Vbus_valid_0,Vbus_valid_1,Vbus_valid_gpio,Vbus_valid_phy_detector" else group.long 0xD000++0x03 line.long 0x00 "USB_POWER_CTRL,Power Control Register" bitfld.long 0x00 31. " ENABLE ,Enable of PHY and charger detector" "Disabled,Enabled" bitfld.long 0x00 30. " ENABLE_CHGDET ,Enables the charger detection circuitry" "Disabled,Enabled" bitfld.long 0x00 29. " ENABLE_DMO ,Enables the single ended receiver on D-" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " ENABLE_DPO ,Enables the single ended receiver on D+" "Disabled,Enabled" bitfld.long 0x00 27. " ENABLE_RCVR ,Enables the differential USB receiver" "Disabled,Enabled" bitfld.long 0x00 26. " ENABLE_VBUS_PULLDOWN ,Enables the weak pull down on the VBUS" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " ENABLE_DM_PULLDOWN ,Enables the ~15k pull down on the DM" "Disabled,Enabled" bitfld.long 0x00 5.--6. " CHDET_PWR_CTL ,Power programmability for bandgap voltage buffer in the charger detect block" "Low_power_mode,Bandgap_voltage_buffer,Bandgap_voltage_buffer,Bandgap_voltage_buffer" bitfld.long 0x00 4. " ISOLATE ,Isolates the PHY outputs" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " SUSPEND_DEL ,Delayed version of SUSPEND" "Disabled,Enabled" bitfld.long 0x00 2. " SUSPEND ,Put PHY into suspend mode" "Disabled,Enabled" bitfld.long 0x00 0.--1. " VBUS_VALID_OVR ,Overrides the value received from the GPIO input buffer connected to VBUS" "Vbus_valid_0,Vbus_valid_1,Vbus_valid_gpio,Vbus_valid_phy_detector" endif if (((per.l(ad:0x402C2000+0xD004))&0x20)==0x20) group.long 0xD004++0x03 line.long 0x00 "USB_CHGDET_CTRL,Charger Detection Control Register" bitfld.long 0x00 31. " COMP_OUT ,Output of the primary/secondary detection comparator" "Not filtered,Debounced" bitfld.long 0x00 6. " DCD_SRC_EN ,Enable the data contact detect current source on D+" "Disabled,Enabled" bitfld.long 0x00 5. " REF_EN ,Enable the primary/secondary reference driver" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " REF_DM ,Connect the primary/secondary detection reference driver to D-" "Not connected,Connected" bitfld.long 0x00 3. " REF_DP ,Connect the primary/secondary detection reference driver to D+" "Not connected,Connected" bitfld.long 0x00 2. " COMP_EN ,Enable the primary/secondary detection comparator and current sink" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " COMP_DM ,Connect the primary/secondary detection comparator and current sink to D-" "Not connected,Connected" bitfld.long 0x00 0. " COMP_DP ,Connect the primary/secondary detection comparator and current sink to D+" "Not connected,Connected" else group.long 0xD004++0x03 line.long 0x00 "USB_CHGDET_CTRL,Charger Detection Control Register" bitfld.long 0x00 31. " COMP_OUT ,Output of the primary/secondary detection comparator" "Not filtered,Debounced" bitfld.long 0x00 6. " DCD_SRC_EN ,Enable the data contact detect current source on D+" "Disabled,Enabled" bitfld.long 0x00 5. " REF_EN ,Enable the primary/secondary reference driver" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " REF_DM ,Connect the primary/secondary detection reference driver to D-" "Not connected,Connected" bitfld.long 0x00 3. " REF_DP ,Connect the primary/secondary detection reference driver to D+" "Not connected,Connected" rbitfld.long 0x00 2. " COMP_EN ,Enable the primary/secondary detection comparator and current sink" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " COMP_DM ,Connect the primary/secondary detection comparator and current sink to D-" "Not connected,Connected" bitfld.long 0x00 0. " COMP_DP ,Connect the primary/secondary detection comparator and current sink to D+" "Not connected,Connected" endif if (((per.l(ad:0x402C0048))&0x20)==0x20) group.long 0xD008++0x03 line.long 0x00 "USB_USBIO_CTRL,USB IO Control Register" bitfld.long 0x00 3.--5. " DM_M ,The GPIO drive mode for DM IO pad" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " DM_P ,The GPIO drive mode for DP IO pad" "OFF,INPUT,0_PU,0_Z,0_1,?..." else group.long 0xD008++0x03 line.long 0x00 "USB_USBIO_CTRL,USB IO Control Register" bitfld.long 0x00 3.--5. " DM_M ,GPIO drive mode for DM IO pad" "0,1,2,3,4,5,6,7" rbitfld.long 0x00 0.--2. " DM_P ,GPIO drive mode for DP IO pad" "OFF,INPUT,0_PU,0_Z,0_1,?..." endif group.long 0xD00C++0x03 line.long 0x00 "USB_FLOW_CTRL,Flow Control Register" bitfld.long 0x00 7. " EP8_ERR_RESP ,End point 8 error response" "No error,Error" bitfld.long 0x00 6. " EP7_ERR_RESP ,End point 7 error response" "No error,Error" bitfld.long 0x00 5. " EP6_ERR_RESP ,End point 6 error response" "No error,Error" textline " " bitfld.long 0x00 4. " EP5_ERR_RESP ,End point 5 error response" "No error,Error" bitfld.long 0x00 3. " EP4_ERR_RESP ,End point 4 error response" "No error,Error" bitfld.long 0x00 2. " EP3_ERR_RESP ,End point 3 error response" "No error,Error" textline " " bitfld.long 0x00 1. " EP2_ERR_RESP ,End point 2 error response" "No error,Error" bitfld.long 0x00 0. " EP1_ERR_RESP ,End point 1 error response" "No error,Error" if (((per.l(ad:0x402C2000+0xD010))&0x01)==0x01) group.long 0xD010++0x03 line.long 0x00 "USB_LPM_CTRL,LPM Control Register" bitfld.long 0x00 4. " SUB_RESP ,Enable a STALL response for all undefined subpids" "Disabled,Enabled" bitfld.long 0x00 2. " NYET_EN ,NYET enabled" "NAK,NYET" bitfld.long 0x00 1. " LPM_ACK_RESP ,LPM ACK response enable" "NYET/NAK,ACK" textline " " bitfld.long 0x00 0. " LPM_EN ,LPM enable" "Disabled,Enabled" else group.long 0xD010++0x03 line.long 0x00 "USB_LPM_CTRL,LPM Control Register" bitfld.long 0x00 4. " SUB_RESP ,Enable a STALL response for all undefined subpids" "Disabled,Enabled" rbitfld.long 0x00 2. " NYET_EN ,NYET enabled" "NAK,NYET" rbitfld.long 0x00 1. " LPM_ACK_RESP ,LPM ACK response enable" "NYET/NAK,ACK" textline " " bitfld.long 0x00 0. " LPM_EN ,LPM enable" "Disabled,Enabled" endif rgroup.long 0xD014++0x03 line.long 0x00 "USB_LPM_STAT,LPM Status Register" bitfld.long 0x00 4. " LPM_REMOTEWAKE ,Device remote wake" "Remote_wake,Wake_host" bitfld.long 0x00 0.--3. " LPM_BESL ,Best effort service latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xD020++0x0B line.long 0x00 "USB_INTR_SIE,USB SOF/BUS RESET And EP0 Interrupt Status" eventfld.long 0x00 4. " RESUME_INTR ,Interrupt status for resume" "No interrupt,Interrupt" eventfld.long 0x00 3. " LPM_INTR ,Interrupt status for LPM" "No interrupt,Interrupt" eventfld.long 0x00 2. " EP0_INTR ,Interrupt status for EP0" "No interrupt,Interrupt" textline " " eventfld.long 0x00 1. " BUS_RESET_INTR ,Interrupt status for BUS RESET" "No interrupt,Interrupt" eventfld.long 0x00 0. " SOF_INTR ,Interrupt status for USB SOF" "No interrupt,Interrupt" line.long 0x04 "USB_INTR_SIE_SET,USB SOF/BUS RESET And EP0 Interrupt Set" bitfld.long 0x04 4. " RESUME_INTR_SET ,Resume interrupt set" "No interrupt,Interrupt" bitfld.long 0x04 3. " LPM_INTR_SET ,LPM interrupt set" "No interrupt,Interrupt" bitfld.long 0x04 2. " EP0_INTR_SET ,EP0 interrupt set" "No interrupt,Interrupt" textline " " bitfld.long 0x04 1. " BUS_RESET_INTR_SET ,BUS reset interrupt set" "No interrupt,Interrupt" bitfld.long 0x04 0. " SOF_INTR_SET ,USB SOF interrupt set" "No interrupt,Interrupt" line.long 0x08 "USB_INTR_SIE_MASK,USB SOF/BUS RESET And EP0 Interrupt Mask" bitfld.long 0x08 4. " RESUME_INTR_MASK ,Resume Interrupt Mask" "No Interrupt,Interrupt" bitfld.long 0x08 3. " LPM_INTR_MASK ,LPM Interrupt Mask" "No Interrupt,Interrupt" bitfld.long 0x08 2. " EP0_INTR_MASK ,EP0 Interrupt Mask" "No Interrupt,Interrupt" textline " " bitfld.long 0x08 1. " BUS_RESET_INTR_MASK ,BUS Reset Interrupt Mask" "No Interrupt,Interrupt" bitfld.long 0x08 0. " SOF_INTR_MASK ,SOF Interrupt Mask" "No Interrupt,Interrupt" rgroup.long 0xD02C++0x03 line.long 0x00 "USB_INTR_SIE_MASKED,USB SOF/BUS RESET And EP0 Interrupt Masked" bitfld.long 0x00 4. " RESUME_INTR_MASKED ,Resume Interrupt Masked" "No Interrupt,Interrupt" bitfld.long 0x00 3. " LPM_INTR_MASKED ,LPM Interrupt Masked" "No Interrupt,Interrupt" bitfld.long 0x00 2. " EP0_INTR_MASKED ,EP0 Interrupt Masked" "No Interrupt,Interrupt" textline " " bitfld.long 0x00 1. " BUS_RESET_INTR_MASKED , BUS Reset Interrupt Masked" "No Interrupt,Interrupt" bitfld.long 0x00 0. " SOF_INTR_MASKED ,SOF Interrupt Masked" "No Interrupt,Interrupt" group.long 0xD030++0x03 line.long 0x00 "USB_INTR_LVL_SEL,Select Interrupt Level For Each Interrupt Source" bitfld.long 0x00 30.--31. " EP8_LVL_SEL ,EP8 Interrupt level select" "0,1,2,3" bitfld.long 0x00 28.--29. " EP7_LVL_SEL ,EP7 Interrupt level select" "0,1,2,3" bitfld.long 0x00 26.--27. " EP6_LVL_SEL ,EP6 Interrupt level select" "0,1,2,3" textline " " bitfld.long 0x00 24.--25. " EP5_LVL_SEL ,EP5 Interrupt level select" "0,1,2,3" bitfld.long 0x00 22.--23. " EP4_LVL_SEL ,EP4 Interrupt level select" "0,1,2,3" bitfld.long 0x00 20.--21. " EP3_LVL_SEL ,EP3 Interrupt level select" "0,1,2,3" textline " " bitfld.long 0x00 18.--19. " EP2_LVL_SEL ,EP2 Interrupt level select" "0,1,2,3" bitfld.long 0x00 16.--17. " EP1_LVL_SEL ,EP1 Interrupt level select" "0,1,2,3" bitfld.long 0x00 14.--15. " ARB_EP_LVL_SEL ,Arbiter Endpoint Interrupt level select" "0,1,2,3" textline " " bitfld.long 0x00 8.--9. " RESUME_LVL_SEL ,Resume Interrupt level select" "0,1,2,3" bitfld.long 0x00 6.--7. " LPM_LVL_SEL ,LPM Interrupt level select" "0,1,2,3" bitfld.long 0x00 4.--5. " EP0_LVL_SEL ,EP0 Interrupt level select" "0,1,2,3" textline " " bitfld.long 0x00 2.--3. " BUS_RESET_LVL_SEL ,BUS RESET Interrupt level select" "0,1,2,3" bitfld.long 0x00 0.--1. " SOF_LVL_SEL ,USB SOF Interrupt level select" "High,Medium,Low,?..." rgroup.long 0xD034++0x0B line.long 0x00 "USB_INTR_CAUSE_HI,High Priority Interrupt Cause Register" bitfld.long 0x00 15. " EP8_INTR ,EP8 interrupt" "No interrupt,Interrupt" bitfld.long 0x00 14. " EP7_INTR ,EP7 interrupt" "No interrupt,Interrupt" bitfld.long 0x00 13. " EP6_INTR ,EP6 interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 12. " EP5_INTR ,EP5 interrupt" "No interrupt,Interrupt" bitfld.long 0x00 11. " EP4_INTR ,EP4 interrupt" "No interrupt,Interrupt" bitfld.long 0x00 10. " EP3_INTR ,EP3 interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 9. " EP2_INTR ,EP2 interrupt" "No interrupt,Interrupt" bitfld.long 0x00 8. " EP1_INTR ,EP1 interrupt" "No interrupt,Interrupt" bitfld.long 0x00 7. " ARB_EP_INTR ,Arbiter endpoint interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 4. " RESUME_INTR ,Resume interrupt" "No interrupt,Interrupt" bitfld.long 0x00 3. " LPM_INTR ,LPM interrupt" "No interrupt,Interrupt" bitfld.long 0x00 2. " EP0_INTR ,EP0 interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x00 1. " BUS_RESET_INTR ,BUS RESET interrupt" "No interrupt,Interrupt" bitfld.long 0x00 0. " SOF_INTR ,USB SOF interrupt" "No interrupt,Interrupt" line.long 0x04 "USB_INTR_CAUSE_MED,Medium Priority Interrupt Cause Register" bitfld.long 0x04 15. " EP8_INTR ,EP8 interrupt" "No interrupt,Interrupt" bitfld.long 0x04 14. " EP7_INTR ,EP7 interrupt" "No interrupt,Interrupt" bitfld.long 0x04 13. " EP6_INTR ,EP6 interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x04 12. " EP5_INTR ,EP5 interrupt" "No interrupt,Interrupt" bitfld.long 0x04 11. " EP4_INTR ,EP4 interrupt" "No interrupt,Interrupt" bitfld.long 0x04 10. " EP3_INTR ,EP3 interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x04 9. " EP2_INTR ,EP2 interrupt" "No interrupt,Interrupt" bitfld.long 0x04 8. " EP1_INTR ,EP1 interrupt" "No interrupt,Interrupt" bitfld.long 0x04 7. " ARB_EP_INTR ,Arbiter endpoint interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x04 4. " RESUME_INTR ,Resume interrupt" "No interrupt,Interrupt" bitfld.long 0x04 3. " LPM_INTR ,LPM interrupt" "No interrupt,Interrupt" bitfld.long 0x04 2. " EP0_INTR ,EP0 interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x04 1. " BUS_RESET_INTR ,BUS RESET interrupt" "No interrupt,Interrupt" bitfld.long 0x04 0. " SOF_INTR ,USB SOF interrupt" "No interrupt,Interrupt" line.long 0x08 "USB_INTR_CAUSE_LO,Low priority interrupt Cause register" bitfld.long 0x08 15. " EP8_INTR ,EP8 interrupt" "No interrupt,Interrupt" bitfld.long 0x08 14. " EP7_INTR ,EP7 interrupt" "No interrupt,Interrupt" bitfld.long 0x08 13. " EP6_INTR ,EP6 interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x08 12. " EP5_INTR ,EP5 interrupt" "No interrupt,Interrupt" bitfld.long 0x08 11. " EP4_INTR ,EP4 interrupt" "No interrupt,Interrupt" bitfld.long 0x08 10. " EP3_INTR ,EP3 interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x08 9. " EP2_INTR ,EP2 interrupt" "No interrupt,Interrupt" bitfld.long 0x08 8. " EP1_INTR ,EP1 interrupt" "No interrupt,Interrupt" bitfld.long 0x08 7. " ARB_EP_INTR ,Arbiter endpoint interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x08 4. " RESUME_INTR ,Resume interrupt" "No interrupt,Interrupt" bitfld.long 0x08 3. " LPM_INTR ,LPM interrupt" "No interrupt,Interrupt" bitfld.long 0x08 2. " EP0_INTR ,EP0 interrupt" "No interrupt,Interrupt" textline " " bitfld.long 0x08 1. " BUS_RESET_INTR ,BUS RESET interrupt" "No interrupt,Interrupt" bitfld.long 0x08 0. " SOF_INTR ,USB SOF interrupt" "No interrupt,Interrupt" group.long 0xDF00++0x1F line.long 0x00 "USB_PHY_TRIM0,PHY Trim Control Register 0" bitfld.long 0x00 0.--5. " TRIM_DP_R_REG ,Trim control for D+ pin poly termination resistors when PHY is in regulated mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "USB_PHY_TRIM1,PHY trim control register 1" bitfld.long 0x04 0.--5. " TRIM_DM_R_REG ,Trim control for D- pin poly termination resistors when PHY is in regulated mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "USB_PHY_TRIM2,PHY trim control register 2" bitfld.long 0x08 0.--5. " TRIM_DP_R_BYPASS ,Trim control for D+ pin poly termination resistors when PHY is in bypass mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0C "USB_PHY_TRIM3,PHY trim control register 3" bitfld.long 0x0C 0.--5. " TRIM_DM_R_BYPASS ,Trim control for D- pin poly termination resistors when PHY is in bypass mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x10 "USB_CHGDET_TRIM,Charger detect trim values" bitfld.long 0x10 4.--6. " V600M_TRIM ,Trim bits for 600mV voltage reference" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0.--1. " V325M_TRIM ,Trim bits for 325mV voltage reference" "0,1,2,3" line.long 0x14 "USB_TRIM,trim values" bitfld.long 0x14 0.--1. " DM_PD_VAL ,Trim bit for DM Pull Down register" "0,1,2,3" line.long 0x18 "USB_USBIO_TRIM,trim values for IOs" bitfld.long 0x18 5. " X_DEC ,decrease of the USB crossover voltage" "Disabled,Enabled" bitfld.long 0x18 4. " X_INC ,increase of the USB crossover voltage" "Disabled,Enabled" bitfld.long 0x18 3. " MINC ,increases the USB edge matching ratio" "0,1" textline " " bitfld.long 0x18 2. " MDEC ,decreases the USB edge matching ratio" "0,1" bitfld.long 0x18 0.--1. " TRIM , Trim suspend mode resistor" "No effect,TRIM_LOWER,TRIM_HIGHER,TRIM_DONT_USE" width 0x0B tree.end endif textline ""