; -------------------------------------------------------------------------------- ; @Title: PMG1-Sx On-Chip Peripherals ; @Props: Released ; @Author: KRZ ; @Changelog: 2023-01-31 KRZ ; @Manufacturer: INFINEON - Infineon Technologies AG ; @Doc: SVD generated (SVD2PER 1.8.6) based on: pmg1s0.svd (Ver. 1.0), ; pmg1s1.svd (Ver. 1.0), pmg1s2.svd (Ver. 1.0), pmg1s3.svd (Ver. 1.0) ; @Core: Cortex-M0 / Cortex-M0+ ; @Chip: PMG1-S0, PMG1-S1, PMG1-S2, PMG1-S3 ; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: perpmg1sx.per 15699 2023-01-31 10:28:38Z kwisniewski $ sif (CORENAME()=="CORTEXM0") tree.close "Core Registers (Cortex-M0)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 0x8 if (CORENAME()=="CORTEXM1") group.long 0x10++0x0b line.long 0x00 "STCSR,SysTick Control and Status Register" bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1" bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock" textline " " bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick" bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled" line.long 0x04 "STRVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0" line.long 0x08 "STCVR,SysTick Current Value Register" hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter" else group.long 0x10++0x0b line.long 0x00 "STCSR,SysTick Control and Status Register" bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1" bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock" textline " " bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick" bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled" line.long 0x04 "STRVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0" line.long 0x08 "STCVR,SysTick Current Value Register" hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter" endif if (CORENAME()=="CORTEXM1") rgroup.long 0x1c++0x03 line.long 0x00 "STCR,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1" bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1" textline " " hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known" else rgroup.long 0x1c++0x03 line.long 0x00 "STCR,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" textline " " hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors" endif rgroup.long 0xd00++0x03 line.long 0x00 "CPUID,CPU ID Base Register" hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code" hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number" textline " " hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family" hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number" group.long 0xd04++0x03 line.long 0x00 "ICSR,Interrupt Control State Register" bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending" bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending" textline " " bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending" bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending" textline " " bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending" bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service" textline " " bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt" hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field" textline " " hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field" if (CORENAME()=="CORTEXM0+") group.long 0xd08++0x03 line.long 0x00 "VTOR,Vector Table Offset Register" hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address" else textline " " endif group.long 0xd0c++0x03 line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key" bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian" textline " " bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset" bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear" group.long 0xd10++0x03 line.long 0x00 "SCR,System Control Register" bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" textline " " bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" rgroup.long 0xd14++0x03 line.long 0x00 "CCR,Configuration and Control Register" bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned" bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped" group.long 0xd1c++0x0b line.long 0x00 "SHPR2,System Handler Priority Register 2" bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11" line.long 0x04 "SHPR3,System Handler Priority Register 3" bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11" bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11" line.long 0x08 "SHCSR,System Handler Control and State Register" bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending" if (CORENAME()=="CORTEXM0+") hgroup.long 0x08++0x03 hide.long 0x00 "ACTLR,Auxiliary Control Register" else textline " " endif else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller (NVIC)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. tree "Interrupt Enable Registers" group.long 0x100++0x03 line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" tree.end tree "Interrupt Pending Registers" group.long 0x200++0x03 line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" tree.end width 6. tree "Interrupt Priority Registers" group.long 0x400++0x1F line.long 0x00 "INT0,Interrupt Priority Register" bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3" bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3" bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3" bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3" line.long 0x04 "INT1,Interrupt Priority Register" bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3" bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3" bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3" bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3" line.long 0x08 "INT2,Interrupt Priority Register" bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3" bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3" bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3" bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3" line.long 0x0C "INT3,Interrupt Priority Register" bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3" bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3" bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3" bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3" line.long 0x10 "INT4,Interrupt Priority Register" bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3" bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3" bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3" bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3" line.long 0x14 "INT5,Interrupt Priority Register" bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3" bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3" bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3" bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3" line.long 0x18 "INT6,Interrupt Priority Register" bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3" bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3" bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3" bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3" line.long 0x1C "INT7,Interrupt Priority Register" bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3" bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3" bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3" bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3" tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 0xA group.long 0xD30++0x03 line.long 0x00 "DFSR,Data Fault Status Register" eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred" eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred" textline " " eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match" textline " " eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match" eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request" if (CORENAME()=="CORTEXM1") if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00) group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " textline " " textfld " " bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" else group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked" bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted" textline " " bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted" bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" endif else if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00) group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up" bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " textline " " textfld " " bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" else group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up" bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked" bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted" textline " " bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted" bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" endif endif wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Selector Register" bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write" bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..." group.long 0xDF8++0x07 line.long 0x00 "DCRDR,Debug Core Register Data Register" hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor" line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled" bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error" textline " " bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset" width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Breakpoint Unit (BPU)" sif COMPonent.AVAILABLE("BPU") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1)) width 8. group.long 0x00++0x03 line.long 0x00 "BP_CTRL,Breakpoint Control Register" bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. " KEY ,Key field" "No write,Write" bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled" group.long 0x8++0x03 line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled" group.long 0xC++0x03 line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled" group.long 0x10++0x03 line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled" group.long 0x14++0x03 line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled" else newline textline "BPU component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 14. rgroup.long 0x00++0x03 line.long 0x00 "DW_CTRL,DW Control Register " bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x1c++0x03 line.long 0x00 "DW_PCSR,DW Program Counter Sample Register" hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF" group.long 0x20++0x0b line.long 0x00 "DW_COMP0,DW Comparator Register 0" hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address" line.long 0x04 "DW_MASK0,DW Mask Register 0" hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP" line.long 0x08 "DW_FUNCTION0,DW Function Register 0" bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match" bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..." group.long 0x30++0x0b line.long 0x00 "DW_COMP1,DW Comparator Register 1" hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address" line.long 0x04 "DW_MASK1,DW Mask Register 1 " hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP" line.long 0x08 "DW_FUNCTION1,DW Function Register 1" bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match" bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..." else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end elif (CORENAME()=="CORTEXM0+") tree.close "Core Registers (Cortex-M0+)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 0x8 if (CORENAME()=="CORTEXM1") group.long 0x10++0x0b line.long 0x00 "STCSR,SysTick Control and Status Register" bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1" bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock" textline " " bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick" bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled" line.long 0x04 "STRVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0" line.long 0x08 "STCVR,SysTick Current Value Register" hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter" else group.long 0x10++0x0b line.long 0x00 "STCSR,SysTick Control and Status Register" bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1" bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock" textline " " bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick" bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled" line.long 0x04 "STRVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0" line.long 0x08 "STCVR,SysTick Current Value Register" hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter" endif if (CORENAME()=="CORTEXM1") rgroup.long 0x1c++0x03 line.long 0x00 "STCR,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1" bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1" textline " " hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known" else rgroup.long 0x1c++0x03 line.long 0x00 "STCR,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" textline " " hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors" endif rgroup.long 0xd00++0x03 line.long 0x00 "CPUID,CPU ID Base Register" hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code" hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number" textline " " hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family" hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number" group.long 0xd04++0x03 line.long 0x00 "ICSR,Interrupt Control State Register" bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending" bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending" textline " " bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending" bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending" textline " " bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending" bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service" textline " " bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt" hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field" textline " " hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field" if (CORENAME()=="CORTEXM0+") group.long 0xd08++0x03 line.long 0x00 "VTOR,Vector Table Offset Register" hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address" else textline " " endif group.long 0xd0c++0x03 line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key" bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian" textline " " bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset" bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear" group.long 0xd10++0x03 line.long 0x00 "SCR,System Control Register" bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" textline " " bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" rgroup.long 0xd14++0x03 line.long 0x00 "CCR,Configuration and Control Register" bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned" bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped" group.long 0xd1c++0x0b line.long 0x00 "SHPR2,System Handler Priority Register 2" bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11" line.long 0x04 "SHPR3,System Handler Priority Register 3" bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11" bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11" line.long 0x08 "SHCSR,System Handler Control and State Register" bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending" if (CORENAME()=="CORTEXM0+") hgroup.long 0x08++0x03 hide.long 0x00 "ACTLR,Auxiliary Control Register" else textline " " endif else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Memory Protection Unit (MPU)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 15. rgroup.long 0xD90++0x03 line.long 0x00 "MPU_TYPE,MPU Type Register" bitfld.long 0x00 8.--15. 1. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,?..." group.long 0xD94++0x03 line.long 0x00 "MPU_CTRL,MPU Control Register" bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled" bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled" bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled" group.long 0xD98++0x03 line.long 0x00 "MPU_RNR,MPU Region Number Register" hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR" tree.close "MPU regions" if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0 group.long 0xD9C++0x03 "Region 0" saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x0 line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 0 (not implemented)" saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x0 hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1 group.long 0xD9C++0x03 "Region 1" saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x1 line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 1 (not implemented)" saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x1 hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2 group.long 0xD9C++0x03 "Region 2" saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x2 line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 2 (not implemented)" saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x2 hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3 group.long 0xD9C++0x03 "Region 3" saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x3 line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 3 (not implemented)" saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x3 hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4 group.long 0xD9C++0x03 "Region 4" saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x4 line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 4 (not implemented)" saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x4 hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5 group.long 0xD9C++0x03 "Region 5" saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x5 line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 5 (not implemented)" saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x5 hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6 group.long 0xD9C++0x03 "Region 6" saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x6 line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 6 (not implemented)" saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x6 hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6" textline " " textline " " endif if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7 group.long 0xD9C++0x03 "Region 7" saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region" group.long 0xDA0++0x03 saveout 0xD98 %l 0x7 line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute" bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-" bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable" bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable" bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable" textline " " bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1" bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1" bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1" bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1" bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1" bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1" bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1" bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1" bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB" bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled" else hgroup.long 0xD9C++0x03 "Region 7 (not implemented)" saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7" hgroup.long 0xDA0++0x03 saveout 0xD98 %l 0x7 hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7" textline " " textline " " endif tree.end width 0x0b else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller (NVIC)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. tree "Interrupt Enable Registers" group.long 0x100++0x03 line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" tree.end tree "Interrupt Pending Registers" group.long 0x200++0x03 line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" tree.end width 6. tree "Interrupt Priority Registers" group.long 0x400++0x1F line.long 0x00 "INT0,Interrupt Priority Register" bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3" bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3" bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3" bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3" line.long 0x04 "INT1,Interrupt Priority Register" bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3" bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3" bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3" bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3" line.long 0x08 "INT2,Interrupt Priority Register" bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3" bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3" bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3" bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3" line.long 0x0C "INT3,Interrupt Priority Register" bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3" bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3" bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3" bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3" line.long 0x10 "INT4,Interrupt Priority Register" bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3" bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3" bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3" bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3" line.long 0x14 "INT5,Interrupt Priority Register" bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3" bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3" bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3" bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3" line.long 0x18 "INT6,Interrupt Priority Register" bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3" bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3" bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3" bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3" line.long 0x1C "INT7,Interrupt Priority Register" bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3" bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3" bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3" bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3" tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 0xA group.long 0xD30++0x03 line.long 0x00 "DFSR,Data Fault Status Register" eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred" eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred" textline " " eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match" textline " " eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match" eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request" if (CORENAME()=="CORTEXM1") if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00) group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " textline " " textfld " " bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" else group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked" bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted" textline " " bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted" bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" endif else if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00) group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up" bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " textline " " textfld " " bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" else group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up" bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked" bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted" textline " " bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted" bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" endif endif wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Selector Register" bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write" bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..." group.long 0xDF8++0x07 line.long 0x00 "DCRDR,Debug Core Register Data Register" hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor" line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled" bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error" textline " " bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset" width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Breakpoint Unit (BPU)" sif COMPonent.AVAILABLE("BPU") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1)) width 8. group.long 0x00++0x03 line.long 0x00 "BP_CTRL,Breakpoint Control Register" bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. " KEY ,Key field" "No write,Write" bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled" group.long 0x8++0x03 line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled" group.long 0xC++0x03 line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled" group.long 0x10++0x03 line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled" group.long 0x14++0x03 line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled" else newline textline "BPU component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 14. rgroup.long 0x00++0x03 line.long 0x00 "DW_CTRL,DW Control Register " bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x1c++0x03 line.long 0x00 "DW_PCSR,DW Program Counter Sample Register" hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF" group.long 0x20++0x0b line.long 0x00 "DW_COMP0,DW Comparator Register 0" hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address" line.long 0x04 "DW_MASK0,DW Mask Register 0" hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP" line.long 0x08 "DW_FUNCTION0,DW Function Register 0" bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match" bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..." group.long 0x30++0x0b line.long 0x00 "DW_COMP1,DW Comparator Register 1" hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address" line.long 0x04 "DW_MASK1,DW Mask Register 1 " hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP" line.long 0x08 "DW_FUNCTION1,DW Function Register 1" bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match" bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..." else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end endif autoindent.on center tree tree "CPUSS (CPU Subsystem)" base ad:0x40100000 group.long 0x00++0x03 line.long 0x00 "CONFIG,Configuration register" bitfld.long 0x00 0. "VECT_IN_RAM,0': Vector Table is located at 0x0000:0000 in flash '1': Vector Table is located at 0x2000:0000 in SRAM Note that vectors for RESET and FAULT are always fetched from ROM" "0,1" group.long 0x04++0x03 line.long 0x00 "SYSREQ,SYSCALL control register" bitfld.long 0x00 31. "SYSCALL_REQ,CPU/DAP writes a '1' to this field to request a SystemCall" "0,1" rbitfld.long 0x00 30. "HMASTER_0,Indicates the source of the write access to the SYSREQ register" "0,1" rbitfld.long 0x00 29. "ROM_ACCESS_EN,Indicates that executing from Boot ROM is enabled" "0,1" bitfld.long 0x00 28. "PRIVILEGED,Indicates whether the system is in privileged ('1') or user mode ('0')" "0,1" bitfld.long 0x00 27. "DIS_RESET_VECT_REL,Disable Reset Vector fetch relocation: '0': CPU accesses to locations 0x0000:0000" "0,1" newline hexmask.long.word 0x00 0.--15. 1. "SYSCALL_COMMAND,Opcode of the system call being requested" group.long 0x08++0x03 line.long 0x00 "SYSARG,SYSARG control register" hexmask.long 0x00 0.--31. 1. "SYSCALL_ARG,Argument to System Call specified in SYSREQ" group.long 0x0C++0x03 line.long 0x00 "PROTECTION,Protection control register" bitfld.long 0x00 31. "PROTECTION_LOCK,Setting this field will block (ignore) any further writes to the PROTECTION_MODE field in this register" "0,1" bitfld.long 0x00 30. "FLASH_LOCK,Setting this bit will force SPCIF.ADDRESS.AXA to be ignored which prevents SM Flash from being erased or overwritten" "0,1" bitfld.long 0x00 0.--3. "PROTECTION_MODE,Current protection mode this field is available as a global signal everywhere in the system" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x10++0x03 line.long 0x00 "PRIV_ROM,ROM privilege register" hexmask.long.word 0x00 16.--25. 1. "SROM_PROT_LIMIT,Indicates the limit where the privileged area of System ROM partition starts in increments of 256 Bytes" hexmask.long.byte 0x00 0.--7. 1. "BROM_PROT_LIMIT,Indicates the limit where the privileged area of the Boot ROM partition starts in increments of 256 Bytes" group.long 0x10++0x03 line.long 0x00 "PRIV_ROM,ROM privilege register" hexmask.long.word 0x00 16.--25. 1. "SROM_PROT_LIMIT,Indicates the limit where the privileged area of System ROM partition starts in increments of 256 Bytes" hexmask.long.byte 0x00 0.--7. 1. "BROM_PROT_LIMIT,Indicates the limit where the privileged area of the Boot ROM partition starts in increments of 256 Bytes" group.long 0x14++0x03 line.long 0x00 "PRIV_RAM,RAM privilege register" hexmask.long.word 0x00 0.--8. 1. "RAM_PROT_LIMIT,Indicates the limit where the privileged area of SRAM starts in increments of 256 Bytes" group.long 0x14++0x03 line.long 0x00 "PRIV_RAM,RAM privilege register" hexmask.long.word 0x00 0.--8. 1. "RAM_PROT_LIMIT,Indicates the limit where the privileged area of SRAM starts in increments of 256 Bytes" group.long 0x18++0x03 line.long 0x00 "PRIV_FLASH,Flash privilege register" hexmask.long.word 0x00 0.--11. 1. "FLASH_PROT_LIMIT,Indicates the limit where the privileged area of flash starts in increments of 256 Bytes" group.long 0x18++0x03 line.long 0x00 "PRIV_FLASH,Flash privilege register" hexmask.long.word 0x00 0.--11. 1. "FLASH_PROT_LIMIT,Indicates the limit where the privileged area of flash starts in increments of 256 Bytes" group.long 0x1C++0x03 line.long 0x00 "WOUNDING,Wounding register" bitfld.long 0x00 24.--26. "RAM1_WOUND,Wounding of RAM 1 (see description of RAM_WOUND)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 20.--22. "FLASH_WOUND,Indicates the amount of accessible flash in this part" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. "RAM_WOUND,Indicates the amount of accessible RAM 0 memory capacitty in this part" "0,1,2,3,4,5,6,7" group.long 0x20++0x03 line.long 0x00 "INT_SEL,Interrupt multiplexer select register" hexmask.long 0x00 0.--31. 1. "DSI,Specifies interrupt source: '0': Fixed Function" group.long 0x24++0x03 line.long 0x00 "INT_MODE,DSI interrupt pulse mode register" hexmask.long 0x00 0.--31. 1. "DSI_INT_PULSE,Specifies DSI interrupt format: '0': level sensitive i.e" group.long 0x28++0x03 line.long 0x00 "NMI_MODE,DSI NMI pulse mode register" bitfld.long 0x00 0. "DSI_NMI_PULSE,Specifies DSI NMI format: '0': level sensitive i.e" "0,1" group.long 0x30++0x03 line.long 0x00 "FLASH_CTL,FLASH control register" bitfld.long 0x00 16.--17. "ARB,Arbitration policy: '0': CPU has priority '1': DW/DMA has priority '2': Roundrobin '3': Roundrobin - sticky" "0,1,2,3" bitfld.long 0x00 8. "FLASH_INVALIDATE,1': Invalidates the content of the flash controller's buffers" "0,1" bitfld.long 0x00 4. "PREF_EN,Prefetch enable: '0': disabled" "0,1" bitfld.long 0x00 0.--1. "FLASH_WS,Amount of ROM wait states: '0': 0 wait states (fast flash: [0 24] MHz system frequency slow flash: [0 16] MHz system frequency) '1': 1 wait state (fast flash: [24 48] MHz system frequency slow flash: [16 32] MHz system frequency) '2': 2 wait.." "0,1,2,3" sif cpuis("PMG1-S0")||cpuis("PMG1-S2") group.long 0x34++0x03 line.long 0x00 "ROM_CTL,ROM control register" bitfld.long 0x00 0. "ROM_WS,Amount of ROM wait states: '0': 0 wait states" "0,1" endif sif cpuis("PMG1-S1")||cpuis("PMG1-S3") group.long 0x34++0x03 line.long 0x00 "ROM_CTL,ROM control register" bitfld.long 0x00 16.--17. "ARB,Arbitration policy: '0': CPU has priority '1': DW/DMA has priority '2': Roundrobin '3': Roundrobin - sticky" "0,1,2,3" bitfld.long 0x00 0. "ROM_WS,Amount of ROM wait states: '0': 0 wait states" "0,1" endif group.long 0x38++0x03 line.long 0x00 "RAM_CTL,RAM control register" bitfld.long 0x00 16.--17. "ARB,Arbitration policy: '0': CPU has priority '1': DW/DMA has priority '2': Roundrobin '3': Roundrobin - sticky" "0,1,2,3" group.long 0x3C++0x03 line.long 0x00 "DMAC_CTL,DMA controller register" bitfld.long 0x00 16.--17. "ARB,Arbitration policy: '0': CPU has priority '1': DW/DMA has priority '2': Roundrobin '3': Roundrobin - sticky" "0,1,2,3" group.long 0xA0++0x03 line.long 0x00 "PRIV_RAM1,RAM 1 privilege register" hexmask.long.word 0x00 0.--8. 1. "RAM_PROT_LIMIT,See description of PRIV_RAM.RAM_PROT_LIMIT" group.long 0xA0++0x03 line.long 0x00 "PRIV_RAM1,RAM 1 privilege register" hexmask.long.word 0x00 0.--8. 1. "RAM_PROT_LIMIT,See description of PRIV_RAM.RAM_PROT_LIMIT" group.long 0xA4++0x03 line.long 0x00 "RAM1_CTL,RAM 1 control register" bitfld.long 0x00 16.--17. "ARB,Arbitration policy (for RAM controller 1): '0': CPU has priority '1': DW/DMA has priority '2': Roundrobin '3': Roundrobin - sticky" "0,1,2,3" group.long 0xB0++0x03 line.long 0x00 "MTB_CTL,MTB control register" bitfld.long 0x00 0. "CPU_HALT_TSTOP_EN,1': Enable CPU Halt to stop MTB trace" "0,1" repeat 24. (increment 0 1) (increment 0 0x04) group.long ($2+0x100)++0x03 line.long 0x00 "SL_CTL[$1],Slave control register $1" bitfld.long 0x00 16.--17. "ARB,Arbitration policy: '0': CPU priority '1': DMA priority '2': Roundrobin '3': Roundrobin - sticky" "0,1,2,3" repeat.end group.long 0x400++0x03 line.long 0x00 "EXT_MS_CTL,External master control register" bitfld.long 0x00 16.--17. "ARB,Arbitration policy" "0: EXTM0/DMAC has priority,1: EXTM1 has priority,2: Roundrobin,3: Roundrobin - sticky" tree.end sif cpuis("PMG1-S3") tree "CRYPTOLITE" base ad:0x402D0000 rgroup.long 0x00++0x03 line.long 0x00 "CTL,Control" bitfld.long 0x00 8.--11. "MS,Master identifier of the cryptography IP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. "PC,Protection context" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. "NS,Secure/on-secure access control: '0': secure" "0,1" bitfld.long 0x00 0. "P,User/privileged access control: '0': user mode" "0,1" rgroup.long 0x04++0x03 line.long 0x00 "STATUS,Status" bitfld.long 0x00 0. "BUSY,Busy indication: '0': IP not busy" "0,1" group.long 0x10++0x03 line.long 0x00 "ECC_CTL,ECC control" bitfld.long 0x00 3. "CHECK_EN,ECC checking enable: '0': Disabled" "0,1" group.long 0x40++0x03 line.long 0x00 "AES_DESCR,AES descriptor pointer" abitfld.long 0x00 2.--31. "PTR,AES descriptor pointer" "0x00000000=0: Pointer to a 128-bit AES key,0x00000001=1: Pointer to a 128-bit..,0x00000002=2: Pointer to a 128-bit.." group.long 0x80++0x03 line.long 0x00 "VU_DESCR,VU descriptor pointer" abitfld.long 0x00 2.--31. "PTR,VU descriptor pointer" "0x00000000=0: Control word,0x00000001=1: Pointer to source 0,0x00000002=2: Pointer to source 1,0x00000003=3: Pointer to destination" group.long 0xC0++0x03 line.long 0x00 "SHA_DESCR,SHA descriptor pointer" abitfld.long 0x00 2.--31. "PTR,SHA-256 descriptor pointer" "0x00000000=0: Control word,0x00000001=1: Pointer to 8 * 32 b word current..,0x00000002=2: Pointer to 64 * 32 b word message.." group.long 0xF0++0x03 line.long 0x00 "INTR_ERROR,Error interrupt" bitfld.long 0x00 0. "BUS_ERROR,AHB-Lite master interface bus error or ECC error" "0,1" group.long 0xF4++0x03 line.long 0x00 "INTR_ERROR_SET,Error interrupt set" bitfld.long 0x00 0. "BUS_ERROR,Write this field with '1' to set corresponding INTR_ERROR field to '1' (a write of '0' has no effect)" "0,1" group.long 0xF8++0x03 line.long 0x00 "INTR_ERROR_MASK,Error interrupt mask" bitfld.long 0x00 0. "BUS_ERROR,Mask for corresponding field in INTR_ERROR register" "0,1" rgroup.long 0xFC++0x03 line.long 0x00 "INTR_ERROR_MASKED,Error interrupt masked" bitfld.long 0x00 0. "BUS_ERROR,Logical and of corresponding INTR_ERROR and INTR_ERROR_MASK fields" "0,1" group.long 0x100++0x03 line.long 0x00 "TRNG_CTL0,TRNG control 0" bitfld.long 0x00 29. "STOP_ON_RC_DETECT,Specifies if TRNG functionality is stopped on a repetition count test detection (when HW sets INTR_ERROR.TRNG_RC_DETECT to '1'): '0': Functionality is NOT stopped" "0,1" bitfld.long 0x00 28. "STOP_ON_AP_DETECT,Specifies if TRNG functionality is stopped on an adaptive proportion test detection (when HW sets INTR_ERROR.TRNG_AP_DETECT to '1'): '0': Functionality is NOT stopped" "0,1" bitfld.long 0x00 25. "FEEDBACK_EN,Specifies if the feedback of the reducution state is enabled: '0': Disabled" "0,1" bitfld.long 0x00 24. "VON_NEUMANN_CORR,Specifies if the 'von Neumann corrector' is disabled or enabled: '0': disabled" "0,1" hexmask.long.byte 0x00 16.--23. 1. "INIT_DELAY,Specifies an initialization delay: number of removed/dropped samples before reduced bits are generated" newline hexmask.long.byte 0x00 8.--15. 1. "RED_CLOCK_DIV,Specifies the clock divider that is used to produce reduced bits" hexmask.long.byte 0x00 0.--7. 1. "SAMPLE_CLOCK_DIV,Specifies the clock divider that is used to sample oscillator data" group.long 0x104++0x03 line.long 0x00 "TRNG_CTL1,TRNG control 1" bitfld.long 0x00 5. "FIRO31_EN,FW sets this field to '1' to enable the programmable Fibonacci ring oscillator with up to 31 inverters" "0,1" bitfld.long 0x00 4. "FIRO15_EN,FW sets this field to '1' to enable the fixed Fibonacci ring oscillator with 15 inverters" "0,1" bitfld.long 0x00 3. "GARO31_EN,FW sets this field to '1' to enable the programmable Galois ring oscillator with up to 31 inverters" "0,1" bitfld.long 0x00 2. "GARO15_EN,FW sets this field to '1' to enable the fixed Galois ring oscillator with 15 inverters" "0,1" bitfld.long 0x00 1. "RO15_EN,FW sets this field to '1' to enable the ring oscillator with 15 inverters" "0,1" newline bitfld.long 0x00 0. "RO11_EN,FW sets this field to '1' to enable the ring oscillator with 11 inverters" "0,1" rgroup.long 0x10C++0x03 line.long 0x00 "TRNG_STATUS,TRNG status" bitfld.long 0x00 0. "INITIALIZED,Reflects the state of the true random number generator: '0': Not initialized (TRNG_CTL0.INIT_DELAY has NOT passed)" "0,1" rgroup.long 0x110++0x03 line.long 0x00 "TRNG_RESULT,TRNG result" hexmask.long 0x00 0.--31. 1. "DATA,Generated 32-bit true random number" group.long 0x120++0x03 line.long 0x00 "TRNG_GARO_CTL,TRNG GARO control" hexmask.long 0x00 0.--30. 1. "POLYNOMIAL,Polynomial for programmable Galois ring oscillator" group.long 0x124++0x03 line.long 0x00 "TRNG_FIRO_CTL,TRNG FIRO control" hexmask.long 0x00 0.--30. 1. "POLYNOMIAL,Polynomial for programmable Fibonacci ring oscillator" group.long 0x140++0x03 line.long 0x00 "TRNG_MON_CTL,TRNG monitor control" bitfld.long 0x00 9. "RC,Repetition count (RC) test enable: '0': Disabled" "0,1" bitfld.long 0x00 8. "AP,Adaptive proportion (AP) test enable: '0': Disabled" "0,1" bitfld.long 0x00 0.--1. "BITSTREAM_SEL,Selection of the bitstream: '0': DAS bitstream" "0,1,2,3" group.long 0x150++0x03 line.long 0x00 "TRNG_MON_RC_CTL,TRNG monitor RC control" hexmask.long.byte 0x00 0.--7. 1. "CUTOFF_COUNT8,Cutoff count (legal range is [1 255]): '0': Illegal" rgroup.long 0x158++0x03 line.long 0x00 "TRNG_MON_RC_STATUS0,TRNG monitor RC status 0" bitfld.long 0x00 0. "BIT,Current active bit value: '0': '0'" "0,1" rgroup.long 0x15C++0x03 line.long 0x00 "TRNG_MON_RC_STATUS1,TRNG monitor RC status 1" hexmask.long.byte 0x00 0.--7. 1. "REP_COUNT,Number of repetitions of the current active bit counter: '0': 0 repetitions" group.long 0x160++0x03 line.long 0x00 "TRNG_MON_AP_CTL,TRNG monitor AP control" hexmask.long.word 0x00 16.--31. 1. "WINDOW_SIZE,Window size (minus 1) : '0': 1 bit" hexmask.long.word 0x00 0.--15. 1. "CUTOFF_COUNT16,Cutoff count (legal range is [1 65535])" rgroup.long 0x168++0x03 line.long 0x00 "TRNG_MON_AP_STATUS0,TRNG monitor AP status 0" bitfld.long 0x00 0. "BIT,Current active bit value: '0': '0'" "0,1" rgroup.long 0x16C++0x03 line.long 0x00 "TRNG_MON_AP_STATUS1,TRNG monitor AP status 1" hexmask.long.word 0x00 16.--31. 1. "WINDOW_INDEX,Counter to keep track of the current index in the window (counts from '0' to TRNG_MON_AP_CTL.WINDOW_SIZE to '0')" hexmask.long.word 0x00 0.--15. 1. "OCC_COUNT,Number of occurrences of the current active bit counter: '0': 0 occurrences" group.long 0x1F0++0x03 line.long 0x00 "INTR_TRNG,TRNG interrupt" bitfld.long 0x00 3. "RC_DETECT,This interrupt cause is activated (HW sets the field to '1') when the TRNG monitor detects an 'repetition count' error" "0,1" bitfld.long 0x00 2. "AP_DETECT,This interrupt cause is activated (HW sets the field to '1') when the TRNG monitor detects an 'adaptive proportion' error" "0,1" bitfld.long 0x00 1. "DATA_AVAILABLE,This interrupt cause is activated (HW sets the field to '1') when 32 bits of TRNG data becomes available in TRNG_RESULT" "0,1" bitfld.long 0x00 0. "INITIALIZED,This interrupt cause is activated (HW sets the field to '1') when the TRNG is initialized" "0,1" group.long 0x1F4++0x03 line.long 0x00 "INTR_TRNG_SET,TRNG Interrupt set" bitfld.long 0x00 3. "RC_DETECT,SW writes a '1' to this field to set the corresponding field in interrupt request register" "0,1" bitfld.long 0x00 2. "AP_DETECT,SW writes a '1' to this field to set the corresponding field in interrupt request register" "0,1" bitfld.long 0x00 1. "DATA_AVAILABLE,SW writes a '1' to this field to set the corresponding field in interrupt request register" "0,1" bitfld.long 0x00 0. "INITIALIZED,SW writes a '1' to this field to set the corresponding field in interrupt request register" "0,1" group.long 0x1F8++0x03 line.long 0x00 "INTR_TRNG_MASK,TRNG Interrupt mask" bitfld.long 0x00 3. "RC_DETECT,Mask bit for corresponding field in interrupt request register" "0,1" bitfld.long 0x00 2. "AP_DETECT,Mask bit for corresponding field in interrupt request register" "0,1" bitfld.long 0x00 1. "DATA_AVAILABLE,Mask bit for corresponding field in interrupt request register" "0,1" bitfld.long 0x00 0. "INITIALIZED,Mask bit for corresponding field in interrupt request register" "0,1" rgroup.long 0x1FC++0x03 line.long 0x00 "INTR_TRNG_MASKED,TRNG Interrupt masked" bitfld.long 0x00 3. "RC_DETECT,Logical and of corresponding request and mask bits" "0,1" bitfld.long 0x00 2. "AP_DETECT,Logical and of corresponding request and mask bits" "0,1" bitfld.long 0x00 1. "DATA_AVAILABLE,Logical and of corresponding request and mask bits" "0,1" bitfld.long 0x00 0. "INITIALIZED,Logical and of corresponding request and mask bits" "0,1" tree.end tree "CSD0 (Capsense Controller)" base ad:0x402A0000 group.long 0x00++0x03 line.long 0x00 "CONFIG,Configuration and Control" bitfld.long 0x00 31. "ENABLE,Master enable of the CSDv2 IP" "0,1" bitfld.long 0x00 30. "LP_MODE,Select the power mode for the CSD components (REFGEN AMBUF CSDCMP HSCMP)" "0: High Power mode,1: Low Power mode" newline bitfld.long 0x00 27. "DSI_SENSE_EN,Enables the use of the dsi_sense_in input instead of the internally generated modulation signal to drive csd_sense and csd_shield signals" "0,1" bitfld.long 0x00 26. "SAMPLE_SYNC,Enables double synchronizing of sample input from DSI (only relevant when DSI_SAMPLE_EN=1)" "0,1" newline bitfld.long 0x00 25. "DSI_SAMPLE_EN,Enables the use of the dsi_sample_in input instead of the comparator output to strobe COUNTER" "0,1" bitfld.long 0x00 24. "DSI_COUNT_SEL,Select what to output on the dsi_count bus" "0: depending on the dsi_count_val_sel input..,1: output ADC_RES.VIN_CNT on the dsi_count bus" newline bitfld.long 0x00 19. "CSX_DUAL_CNT,Enable the use of two counters for MUTUAL cap sensing mode (CSX) do not use when MUTUAL_CAP=0" "0: Use one counter for both phases (source and..,1: Use two counters separate count for when.." bitfld.long 0x00 18. "MUTUAL_CAP,Enables mutual cap sensing mode" "0: Self-cap mode (configure sense line as..,1: Mutual-cap mode (configure Tx line as.." newline bitfld.long 0x00 17. "FULL_WAVE,Enables full wave cap sensing mode" "0: Half Wave mode (normal),1: Full Wave mode" bitfld.long 0x00 14. "CHARGE_MODE,Enable charging of the Cmod/Csh_tank capacitor using the GPIO digital output buffer using the csd_charge signal" "0: Use this to keep csd_charge signal low,1: Use csd_charge to enable the GPIO Driver to.." newline bitfld.long 0x00 12. "SENSE_EN,Enables the sense modulator output" "0: all switches static or dynamic are open and..,1: switches and IDAC can be closed/on as per MMIO" bitfld.long 0x00 8.--9. "SHIELD_DELAY,Selects the delay by which csd_shield is delayed relative to csd_sense" "0: Delay line is off csd_shield=csd_sense,1: Introduces a 5ns delay (typ),2: Introduces a 10ns delay (typ),3: Introduces a 20ns delay (typ)" newline bitfld.long 0x00 4.--6. "FILTER_DELAY,This value determines the number of cycles that the digital filter makes the CSDCMP output ignored while the counter counts and IDAC is on" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. "LOW_VDDA,Set this bit when VDDA is known to be below ~2V this bit is used to improve IDACs performance at low voltages" "0,1" group.long 0x04++0x03 line.long 0x00 "SPARE,Spare MMIO" bitfld.long 0x00 0.--3. "SPARE,Spare MMIO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x80++0x03 line.long 0x00 "STATUS,Status Register" bitfld.long 0x00 3. "CSDCMP_OUT,Output of main sensing comparator (synchronized)" "0,1" bitfld.long 0x00 2. "HSCMP_OUT,Output of reference buffer comparator used to charge up Cmod and/or Csh_tank (synchronized)" "0: Vin < Vref,1: Vin > Vref" newline bitfld.long 0x00 1. "CSD_SENSE,Signal used to drive the Cs switches" "0,1" bitfld.long 0x00 0. "CSD_CHARGE,Qualified and possible inverted value of COMP_OUT that is used to drive GPIO's charging Cmod or Csh_tank" "0,1" rgroup.long 0x84++0x03 line.long 0x00 "STAT_SEQ,Current Sequencer status" bitfld.long 0x00 16.--18. "ADC_STATE,ADC sequencer state (only relevant after SEQ_STATE has reached SAMPLE_NORM and ADC sequencer has started)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "SEQ_STATE,CSD sequencer state" "0,1,2,3,4,5,6,7" rgroup.long 0x88++0x03 line.long 0x00 "STAT_CNTS,Current status counts" hexmask.long.word 0x00 0.--15. 1. "NUM_CONV,Current number of conversions remaining when in Sample_* states (note that in AutoZero* states the same down counter is reused to count the cycles)" rgroup.long 0x8C++0x03 line.long 0x00 "STAT_HCNT,Current count of the HSCMP counter" hexmask.long.word 0x00 0.--15. 1. "CNT,Current value of HSCMP counter" rgroup.long 0xD0++0x03 line.long 0x00 "RESULT_VAL1,Result CSD/CSX accumulation counter value 1" hexmask.long.byte 0x00 16.--23. 1. "BAD_CONVS,Number of 'bad' conversion for which the CSD comparator did not trigger within the normal time window either because Vref was not crossed at all or if the Vref was already crossed before the window started" hexmask.long.word 0x00 0.--15. 1. "VALUE,Accumulated counter value for this result" rgroup.long 0xD4++0x03 line.long 0x00 "RESULT_VAL2,Result CSX accumulation counter value 2" hexmask.long.word 0x00 0.--15. 1. "VALUE,Only used in case of Mutual cap with two counters (CSX = config.mutual_cap & config.csx_dual_cnt) this counter counts when csd_sense is low" rgroup.long 0xE0++0x03 line.long 0x00 "ADC_RES,ADC measurement" bitfld.long 0x00 31. "ADC_ABORT,This flag is set when the ADC sequencer was aborted before tripping HSCMP" "0,1" bitfld.long 0x00 30. "ADC_OVERFLOW,This flag is set when the ADC counter overflows" "0,1" newline bitfld.long 0x00 16. "HSCMP_POL,Polarity used for IDACB for this last ADC result" "0: source,1: sink" hexmask.long.word 0x00 0.--15. 1. "VIN_CNT,Count to source/sink Cref1 + Cref2 from Vin to Vrefhi or Vssa" group.long 0xF0++0x03 line.long 0x00 "INTR,CSD Interrupt Request Register" bitfld.long 0x00 8. "ADC_RES,ADC Result ready" "0,1" bitfld.long 0x00 2. "INIT,Coarse initialization complete or Sample initialization complete (the latter is typically ignored)" "0,1" newline bitfld.long 0x00 1. "SAMPLE,A normal sample is complete (CSDv1 compatible interrupt)" "0,1" group.long 0xF4++0x03 line.long 0x00 "INTR_SET,CSD Interrupt set register" bitfld.long 0x00 8. "ADC_RES,Write with '1' to set corresponding bit in interrupt request register" "0,1" bitfld.long 0x00 2. "INIT,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 1. "SAMPLE,Write with '1' to set corresponding bit in interrupt request register" "0,1" group.long 0xF8++0x03 line.long 0x00 "INTR_MASK,CSD Interrupt mask register" bitfld.long 0x00 8. "ADC_RES,Mask bit for corresponding bit in interrupt request register" "0,1" bitfld.long 0x00 2. "INIT,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 1. "SAMPLE,Mask bit for corresponding bit in interrupt request register" "0,1" rgroup.long 0xFC++0x03 line.long 0x00 "INTR_MASKED,CSD Interrupt masked register" bitfld.long 0x00 8. "ADC_RES,Logical and of corresponding request and mask bits" "0,1" bitfld.long 0x00 2. "INIT,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 1. "SAMPLE,Logical and of corresponding request and mask bits" "0,1" group.long 0x180++0x03 line.long 0x00 "HSCMP,High Speed Comparator configuration" bitfld.long 0x00 31. "AZ_EN,Auto-Zero enable allow the Sequencer to Auto-Zero this component" "0,1" bitfld.long 0x00 4. "HSCMP_INVERT,Invert the HSCMP output before it is used to control switches and the CSD sequencer" "0,1" newline bitfld.long 0x00 0. "HSCMP_EN,High Speed Comparator enable" "0: Disable comparator output is zero,1: On regular operation" group.long 0x184++0x03 line.long 0x00 "AMBUF,Reference Generator configuration" bitfld.long 0x00 0.--1. "PWR_MODE,Amux buffer power level" "0: Disable buffer,1: On normal or low power level depending on..,2: On high or low power level depending on..,?..." group.long 0x188++0x03 line.long 0x00 "REFGEN,Reference Generator configuration" bitfld.long 0x00 23. "VREFLO_INT,Ouput the resistor string tap either to Vreflo (0) or Vreflo_int (1)" "0,1" bitfld.long 0x00 16.--20. "VREFLO_SEL,Select resistor string tap for Vreflo/Vreflo_int" "0: minimum vout,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: maximum vout = vrefhi (only works" newline bitfld.long 0x00 8.--12. "GAIN,Select resistor string tap for feedback" "0: minimum vout,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: maximum vout = vrefhi -> gain=1" bitfld.long 0x00 6. "RES_EN,Resistor string enable" "0,1" newline bitfld.long 0x00 5. "VDDA_EN,Close Vdda switch to top of resistor string (or Vrefhi?)" "0,1" bitfld.long 0x00 4. "BYPASS,Bypass selected input reference unbuffered to Vrefhi" "0,1" newline bitfld.long 0x00 0. "REFGEN_EN,Reference Generator Enable" "0: Disable Reference Generator,1: On regular operation" group.long 0x18C++0x03 line.long 0x00 "CSDCMP,CSD Comparator configuration" bitfld.long 0x00 31. "AZ_EN,Auto-Zero enable allow the Sequencer to Auto-Zero this component" "0,1" bitfld.long 0x00 29. "FEEDBACK_MODE,This bit controls whether the output directly from the comparator (csdcmp_out) or the flopped version (csdcmp_out_ff) is used" "0: Use feedback from sampling flip-flop (used in..,1: Use feedback from comparator directly (used.." newline bitfld.long 0x00 28. "CMP_MODE,Select which signal to output on dsi_sample_out" "0: CSD mode,1: General Purpose mode" bitfld.long 0x00 8.--9. "CMP_PHASE,Select in what phase(s) the comparator is active" "0: Comparator is active from start of Phi2 and..,1: Comparator is active during Phi1 only,2: Comparator is active during Phi2 only,3: Comparator is activated at the start of both.." newline bitfld.long 0x00 4.--5. "POLARITY_SEL,Select which IDAC polarity to use to detect CSDCMP triggering" "0: Use idaca_pol (firmware setting with CSX and..,1: Use idacb_pol (firmware setting with optional..,2: Use the expression (csd_sense ? idaca_pol :..,?..." bitfld.long 0x00 0. "CSDCMP_EN,CSD Comparator Enable" "0: Disable comparator output is zero,1: On regular operation" group.long 0x1C0++0x03 line.long 0x00 "IDACA,IDACA Configuration" bitfld.long 0x00 25. "LEG2_EN,output enable for leg 2 to CSDBUSA" "0,1" bitfld.long 0x00 24. "LEG1_EN,output enable for leg 1 to CSDBUSA" "0,1" newline bitfld.long 0x00 22.--23. "RANGE,IDAC multiplier" "0: 1 LSB = 37.5 nA,1: 1 LSB = 300 nA,2: 1 LSB = 2400 nA,3: 1 LSB = 1200 nA" bitfld.long 0x00 21. "DSI_CTRL_EN,Mix DSI inputs with MMIO controls or not (before getting mixed with CSD controls if enabled)" "0: no DSI control IDACA_POLARITY = IDACA.POLARITY,1: Mix MMIO with DSI control IDACA_POLARITY =" newline bitfld.long 0x00 18.--19. "LEG2_MODE,Controls the usage mode of LEG2" "0: General Purpose static mode,1: General Purpose dynamic mode,2: CSD static mode,3: CSD dynamic mode" bitfld.long 0x00 16.--17. "LEG1_MODE,Controls the usage mode of LEG1 and the Polarity bit" "0: General Purpose static mode,1: General Purpose dynamic mode,2: CSD static mode,3: CSD dynamic mode" newline bitfld.long 0x00 10.--11. "BAL_MODE,Balancing mode: only applies to legs configured as CSD" "0: enabled from start of Phi2 until disabled by..,1: enabled from start of Phi1 and disabled by..,2: enabled from start of Phi2 and disabled by..,3: enabled from start of both Phi1 and Phi2 and.." bitfld.long 0x00 8.--9. "POLARITY,Selects the polarity of the IDAC (sensing operation)" "0: Normal,1: Inverted,2: The polarity of the IDAC will follow the..,3: The polarity of the IDAC will follow the.." newline bitfld.long 0x00 7. "POL_DYN,Polarity is dynamic this bit does not influence the logic in the SoftIP it only goes to the HardIP" "0: Static polarity,1: Dynamic polarity" hexmask.long.byte 0x00 0.--6. 1. "VAL,Current value setting for this IDAC (7 bits)" group.long 0x1C4++0x03 line.long 0x00 "IDACB,IDACB Configuration" bitfld.long 0x00 26. "LEG3_EN,output enable for leg3 to CSDBUSC only allowed when RANGE = IDAC_LO" "0,1" bitfld.long 0x00 25. "LEG2_EN,output enable for leg 2 to CSDBUSB or CSDBUSA" "0,1" newline bitfld.long 0x00 24. "LEG1_EN,output enable for leg 1 to CSDBUSB or CSDBUSA" "0,1" bitfld.long 0x00 22.--23. "RANGE,IDAC multiplier" "0: 1 LSB = 37.5 nA,1: 1 LSB = 300 nA,2: 1 LSB = 2400 nA,3: 1 LSB = 1200 nA" newline bitfld.long 0x00 21. "DSI_CTRL_EN,Mix DSI inputs with MMIO controls or not (before getting mixed with CSD controls if enabled)" "0: no DSI control IDACB_POLARITY = IDACB.POLARITY,1: Mix MMIO with DSI control IDACB_POLARITY =" bitfld.long 0x00 18.--19. "LEG2_MODE,Controls the usage mode of LEG2" "0: same as corresponding IDACA.LEG2_MODE,1: same as corresponding IDACA.LEG2_MODE,2: same as corresponding IDACA.LEG2_MODE,3: same as corresponding IDACA.LEG2_MODE" newline bitfld.long 0x00 16.--17. "LEG1_MODE,Controls the usage mode of LEG1 and the Polarity bit" "0: same as corresponding IDACA.LEG1_MODE,1: same as corresponding IDACA.LEG1_MODE,2: same as corresponding IDACA.LEG1_MODE,3: same as corresponding IDACA.LEG1_MODE" bitfld.long 0x00 10.--11. "BAL_MODE,same as corresponding IDACA Balancing mode" "0: same as corresponding IDACA Balancing mode,1: same as corresponding IDACA Balancing mode,2: same as corresponding IDACA Balancing mode,3: same as corresponding IDACA Balancing mode" newline bitfld.long 0x00 8.--9. "POLARITY,Selects the polarity of the IDAC (sensing operation)" "0: Normal,1: Inverted,2: The polarity of the IDAC will follow the..,3: The polarity of the IDAC will follow the.." bitfld.long 0x00 7. "POL_DYN,Polarity is dynamic this bit does not influence the logic in the SoftIP it only goes to the HardIP" "0: Static polarity,1: Dynamic polarity" newline hexmask.long.byte 0x00 0.--6. 1. "VAL,Current value setting for this IDAC (7 bits)" group.long 0x1F0++0x03 line.long 0x00 "SW_RES,Switch Resistance configuration" bitfld.long 0x00 18.--19. "RES_F2PT,Select resistance for the corresponding switch" "0,1,2,3" bitfld.long 0x00 16.--17. "RES_F1PM,Select resistance for the corresponding switch" "0: LOW,1: Medium,2: HIGH,3: RSVD" newline bitfld.long 0x00 6.--7. "RES_HCBG,Select resistance or low EMI for the corresponding switch" "0,1,2,3" bitfld.long 0x00 4.--5. "RES_HCBV,Select resistance or low EMI for the corresponding switch" "0,1,2,3" newline bitfld.long 0x00 2.--3. "RES_HCAG,Select resistance or low EMI for the corresponding switch" "0,1,2,3" bitfld.long 0x00 0.--1. "RES_HCAV,Select resistance or low EMI (slow ramp) for the HCAV switch" "0: LOW,1: Medium,2: HIGH,3: Low EMI (slow ramp: 3 switches closed by.." group.long 0x200++0x03 line.long 0x00 "SENSE_PERIOD,Sense clock period" bitfld.long 0x00 26.--27. "LFSR_BITS,Selects the number of LSB bits to use from the LSFR to provide the clock dithering variation on the base period" "0: use 2 bits,1: use 3 bits,2: use 4 bits,3: use 5 bits" bitfld.long 0x00 25. "SEL_LFSR_MSB,Use the MSB of configured LSFR size as csd_sense signal" "0,1" newline bitfld.long 0x00 24. "LFSR_CLEAR,When set forces the LFSR to it's initial state (all ones)" "0,1" bitfld.long 0x00 20.--23. "LFSR_SCALE,Shift the LFSR output left by LSFR_SCALE bits before adding to SENSE_DIV" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16.--18. "LFSR_SIZE,Selects the length of the LFSR which determines the LFSR repeat period" "0: Don't use clock dithering (=spreadspectrum)..,1: 6-bit LFSR (G(x)=X^6 +X^4+X^3+ X+1 period= 63),2: 7-bit LFSR (G(x)=X^7 +X^4+X^3+X^2+1 period=..,3: 9-bit LFSR (G(x)=X^9 +X^4+X^3+ X+1 period= 511),4: 10-bit LFSR (G(x)=X^10+X^4+X^3+ X+1 period=..,5: 8-bit LFSR (G(x)=X^8+X^4+X^3+X^2+1 period= 255),6: 12-bit LFSR (G(x)=X^12+X^7+X^4+X^3+1 period=..,?..." hexmask.long.word 0x00 0.--11. 1. "SENSE_DIV,The length-1 of the Sense modulation 'clock' period in clk_csd cycles" group.long 0x204++0x03 line.long 0x00 "SENSE_DUTY,Sense clock duty cycle" bitfld.long 0x00 19. "OVERLAP_PHI2,Same as OVERLAP_PHI1 but for Phi2 (csd_sense=1)" "0,1" bitfld.long 0x00 18. "OVERLAP_PHI1,NonOverlap or not for Phi1 (csd_sense=0)" "0: Non-overlap for Phi1 the Phi1 signal is,1: 'Overlap' (= not non-overlap) for Phi1 the Phi1" newline bitfld.long 0x00 16. "SENSE_POL,Polarity of the sense clock" "0: start with low phase (typical for regular,1: start with high phase" hexmask.long.word 0x00 0.--11. 1. "SENSE_WIDTH,Defines the length of the first phase of the sense clock in clk_csd cycles" group.long 0x280++0x03 line.long 0x00 "SW_HS_P_SEL,HSCMP Pos input switch Waveform selection" bitfld.long 0x00 28. "SW_HMRH,Set corresponding switch" "0,1" bitfld.long 0x00 24. "SW_HMCB,Set corresponding switch" "0,1" newline bitfld.long 0x00 20. "SW_HMCA,Set corresponding switch" "0,1" bitfld.long 0x00 16. "SW_HMMB,Set corresponding switch" "0,1" newline bitfld.long 0x00 12. "SW_HMMA,Set corresponding switch" "0,1" bitfld.long 0x00 8. "SW_HMPS,Set corresponding switch" "0,1" newline bitfld.long 0x00 4. "SW_HMPT,Set corresponding switch" "0,1" bitfld.long 0x00 0. "SW_HMPM,Set HMPM switch" "0: static open,1: static closed" group.long 0x284++0x03 line.long 0x00 "SW_HS_N_SEL,HSCMP Neg input switch Waveform selection" bitfld.long 0x00 28.--30. "SW_HCRL,Select waveform for corresponding switch" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "SW_HCRH,Select waveform for corresponding switch" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 20. "SW_HCCD,Set corresponding switch" "0,1" bitfld.long 0x00 16. "SW_HCCC,Set corresponding switch" "0,1" group.long 0x288++0x03 line.long 0x00 "SW_SHIELD_SEL,Shielding switches Waveform selection" bitfld.long 0x00 20. "SW_HCCG,Set corresponding switch If the ADC is enabled then this switch is directly controlled by the ADC sequencer" "0,1" bitfld.long 0x00 16. "SW_HCCV,Set corresponding switch" "0,1" newline bitfld.long 0x00 12.--14. "SW_HCBG,Select waveform for corresponding switch using csd_shield as base" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "SW_HCBV,N/A" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4.--6. "SW_HCAG,Select waveform for corresponding switch" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "SW_HCAV,N/A" "0,1,2,3,4,5,6,7" group.long 0x28C++0x03 line.long 0x00 "SW_HS_P_SEL1,HSCMP Pos input switch Waveform selection 1" bitfld.long 0x00 0. "SW_HMRE,Set HMRE switch" "0: static open,1: static closed" group.long 0x290++0x03 line.long 0x00 "SW_AMUXBUF_SEL,Amuxbuffer switches Waveform selection" bitfld.long 0x00 28. "SW_IRL,Set corresponding switch" "0,1" bitfld.long 0x00 24. "SW_IRH,Set corresponding switch" "0,1" newline bitfld.long 0x00 20. "SW_IRLI,Set corresponding switch" "0,1" bitfld.long 0x00 16.--18. "SW_ICB,Select waveform for corresponding switch" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12. "SW_ICA,Set corresponding switch" "0,1" bitfld.long 0x00 8. "SW_IRLB,Set corresponding switch" "0,1" newline bitfld.long 0x00 4. "SW_IRBY,Set corresponding switch" "0,1" group.long 0x294++0x03 line.long 0x00 "SW_BYP_SEL,AMUXBUS bypass switches Waveform selection" bitfld.long 0x00 20. "SW_CBCC,Set corresponding switch If the ADC is enabled then this switch is directly controlled by the ADC sequencer" "0,1" bitfld.long 0x00 16. "SW_BYB,Set corresponding switch" "0,1" newline bitfld.long 0x00 12. "SW_BYA,Set corresponding switch" "0,1" group.long 0x2A0++0x03 line.long 0x00 "SW_CMP_P_SEL,CSDCMP Pos Switch Waveform selection" bitfld.long 0x00 24. "SW_SFCB,Set corresponding switch" "0,1" bitfld.long 0x00 20. "SW_SFCA,Set corresponding switch" "0,1" newline bitfld.long 0x00 16. "SW_SFMB,Set corresponding switch" "0,1" bitfld.long 0x00 12. "SW_SFMA,Set corresponding switch" "0,1" newline bitfld.long 0x00 8.--10. "SW_SFPS,Select waveform for corresponding switch" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--6. "SW_SFPT,Select waveform for corresponding switch" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--2. "SW_SFPM,Select waveform for corresponding switch" "0,1,2,3,4,5,6,7" group.long 0x2A4++0x03 line.long 0x00 "SW_CMP_N_SEL,CSDCMP Neg Switch Waveform selection" bitfld.long 0x00 28.--30. "SW_SCRL,Select waveform for corresponding switch" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. "SW_SCRH,Select waveform for corresponding switch" "0,1,2,3,4,5,6,7" group.long 0x2A8++0x03 line.long 0x00 "SW_REFGEN_SEL,Reference Generator Switch Waveform selection" bitfld.long 0x00 28. "SW_SGR,Set corresponding switch" "0,1" bitfld.long 0x00 24. "SW_SGRE,Set corresponding switch" "0,1" newline bitfld.long 0x00 16. "SW_SGMB,Set corresponding switch" "0,1" bitfld.long 0x00 4. "SW_IBCB,Set corresponding switch" "0,1" newline bitfld.long 0x00 0. "SW_IAIB,Set corresponding switch" "0,1" group.long 0x2B0++0x03 line.long 0x00 "SW_FW_MOD_SEL,Full Wave Cmod Switch Waveform selection" bitfld.long 0x00 28. "SW_C1F1,Set corresponding switch" "0,1" bitfld.long 0x00 24. "SW_C1CD,Set corresponding switch" "0,1" newline bitfld.long 0x00 20. "SW_C1CC,Set corresponding switch" "0,1" bitfld.long 0x00 16.--18. "SW_F1CA,Select waveform for corresponding switch" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--10. "SW_F1MA,Select waveform for corresponding switch" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. "SW_F1PM,Set corresponding switch" "0,1" group.long 0x2B4++0x03 line.long 0x00 "SW_FW_TANK_SEL,Full Wave Csh_tank Switch Waveform selection" bitfld.long 0x00 28. "SW_C2F2,Set corresponding switch" "0,1" bitfld.long 0x00 24. "SW_C2CD,Set corresponding switch" "0,1" newline bitfld.long 0x00 20. "SW_C2CC,Set corresponding switch" "0,1" bitfld.long 0x00 16.--18. "SW_F2CB,Select waveform for corresponding switch" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 12.--14. "SW_F2CA,Select waveform for corresponding switch" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--10. "SW_F2MA,Select waveform for corresponding switch" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 4. "SW_F2PT,Set corresponding switch" "0,1" group.long 0x2C0++0x03 line.long 0x00 "SW_DSI_SEL,DSI output switch control Waveform selection" bitfld.long 0x00 4.--6. "DSI_CMOD,Select waveform for dsi_cmod signal (called dsi_cap_hi_en in CDSv1)" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "DSI_CSH_TANK,Select waveform for dsi_csh_tank signal (called dsi_cap_lo_en in CDSv1)" "0,1,2,3,4,5,6,7" group.long 0x300++0x03 line.long 0x00 "SEQ_TIME,Sequencer Timing" hexmask.long.byte 0x00 0.--7. 1. "AZ_TIME,Define Auto-Zero time in csd_sense cycles -1" group.long 0x310++0x03 line.long 0x00 "SEQ_INIT_CNT,Sequencer Initial conversion and sample counts" hexmask.long.word 0x00 0.--15. 1. "CONV_CNT,Number of conversion per sample if set to 0 the Sample_init state will be skipped" group.long 0x314++0x03 line.long 0x00 "SEQ_NORM_CNT,Sequencer Normal conversion and sample counts" hexmask.long.word 0x00 0.--15. 1. "CONV_CNT,Number of conversion per sample if set to 0 the Sample_norm state will be skipped" group.long 0x320++0x03 line.long 0x00 "ADC_CTL,ADC Control" bitfld.long 0x00 16.--17. "ADC_MODE,Enable ADC measurement" "0: No ADC measurement,1: Count time A to bring Cref1 + Cref2 up from..,2: Count time B to bring Cref1 + Cref2 back up..,3: Determine HSCMP polarity and count time C to.." hexmask.long.byte 0x00 0.--7. 1. "ADC_TIME,ADC timing -1 in csd_sense clock cycles (actual time is ADC_TIME+1 cycles) either used to discharge Cref1&2 or as the aperture to capture the input voltage on Cref1&2" group.long 0x340++0x03 line.long 0x00 "SEQ_START,Sequencer start" bitfld.long 0x00 9. "AZ1_SKIP,When set the AutoZero_1 state will be skipped" "0,1" bitfld.long 0x00 8. "AZ0_SKIP,When set the AutoZero_0 state will be skipped" "0,1" newline bitfld.long 0x00 4. "DSI_START_EN,When this bit is set a positive edge on dsi_start will start the CSD sequencer and if enabled also the ADC sequencer" "0,1" bitfld.long 0x00 3. "ABORT,When a 1 is written the CSD and ADC sequencers will be aborted (if they are running) and the START bit will be cleared" "0,1" newline bitfld.long 0x00 1. "SEQ_MODE," "0,1" bitfld.long 0x00 0. "START,Start the CSD sequencer" "0,1" tree.end tree "CTBM0 (Continuous Time Block Mini)" base ad:0x40300000 group.long 0x00++0x03 line.long 0x00 "CTB_CTRL,global CTB and power control" bitfld.long 0x00 31. "ENABLED," "0: CTB IP disabled (put analog in power,1: CTB IP enabled" newline bitfld.long 0x00 30. "DEEPSLEEP_ON," "0: CTB IP disabled off during DeepSleep power mode,1: CTB IP remains enabled during DeepSleep power" group.long 0x04++0x03 line.long 0x00 "OA_RES0_CTRL,Opamp0 and resistor0 control" bitfld.long 0x00 11. "OA0_PUMP_EN,Opamp0 pump enable" "0,1" newline bitfld.long 0x00 8.--9. "OA0_COMPINT,Opamp0 comparator edge detect for interrupt and pulse mode of DSI (trigger)" "0: Disabled no interrupts will be detected,1: Rising edge,2: Falling edge,3: Both rising and falling edges" newline bitfld.long 0x00 7. "OA0_DSI_LEVEL,Opamp0 comparator DSI (trigger) out level" "0: pulse each time an edge is detected (see,1: level DSI output is a synchronized version of" newline bitfld.long 0x00 6. "OA0_BYPASS_DSI_SYNC,Opamp0 bypass comparator output synchronization for DSI (trigger) output" "0: synchronize (level or pulse),1: bypass (output async)" newline bitfld.long 0x00 5. "OA0_HYST_EN,Opamp0 hysteresis enable (10mV)" "0,1" newline bitfld.long 0x00 4. "OA0_COMP_EN,Opamp0 comparator enable" "0,1" newline bitfld.long 0x00 2. "OA0_DRIVE_STR_SEL,Opamp0 output strenght select" "0,1" newline bitfld.long 0x00 0.--1. "OA0_PWR_MODE,Opamp0 power level" "0: OFF,1: Low compensation setting (smallest cap..,2: Medium compensation setting,3: Highest compensation (largest cap lowest GBW)" group.long 0x08++0x03 line.long 0x00 "OA_RES1_CTRL,Opamp1 and resistor1 control" bitfld.long 0x00 11. "OA1_PUMP_EN,Opamp1 pump enable" "0,1" newline bitfld.long 0x00 8.--9. "OA1_COMPINT,Opamp1 comparator edge detect for interrupt and pulse mode of DSI (trigger)" "0: Disabled no interrupts will be detected,1: Rising edge,2: Falling edge,3: Both rising and falling edges" newline bitfld.long 0x00 7. "OA1_DSI_LEVEL,Opamp1 comparator DSI (trigger) out level" "0: pulse each time an edge is detected (see,1: level DSI output is a synchronized version of" newline bitfld.long 0x00 6. "OA1_BYPASS_DSI_SYNC,Opamp1 bypass comparator output synchronization for DSI output" "0: synchronize,1: bypass" newline bitfld.long 0x00 5. "OA1_HYST_EN,Opamp1 hysteresis enable (10mV)" "0,1" newline bitfld.long 0x00 4. "OA1_COMP_EN,Opamp1 comparator enable" "0,1" newline bitfld.long 0x00 2. "OA1_DRIVE_STR_SEL,Opamp1 output strenght select" "0,1" newline bitfld.long 0x00 0.--1. "OA1_PWR_MODE,Opamp1 power level: see description of OA0_PWR_MODE" "0,1,2,3" rgroup.long 0x0C++0x03 line.long 0x00 "COMP_STAT,Comparator status" bitfld.long 0x00 16. "OA1_COMP,Opamp1 current comparator status" "0,1" newline bitfld.long 0x00 0. "OA0_COMP,Opamp0 current comparator status" "0,1" group.long 0x20++0x03 line.long 0x00 "INTR,Interrupt request register" bitfld.long 0x00 1. "COMP1,Comparator 1 Interrupt: hardware sets this interrupt when comparator 1 triggers" "0,1" newline bitfld.long 0x00 0. "COMP0,Comparator 0 Interrupt: hardware sets this interrupt when comparator 0 triggers" "0,1" group.long 0x24++0x03 line.long 0x00 "INTR_SET,Interrupt request set register" bitfld.long 0x00 1. "COMP1_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 0. "COMP0_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1" group.long 0x28++0x03 line.long 0x00 "INTR_MASK,Interrupt request mask" bitfld.long 0x00 1. "COMP1_MASK,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 0. "COMP0_MASK,Mask bit for corresponding bit in interrupt request register" "0,1" rgroup.long 0x2C++0x03 line.long 0x00 "INTR_MASKED,Interrupt request masked" bitfld.long 0x00 1. "COMP1_MASKED,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 0. "COMP0_MASKED,Logical and of corresponding request and mask bits" "0,1" group.long 0x30++0x03 line.long 0x00 "DFT_CTRL,Was 'Analog DfT controls' now used as Risk Mitigation bits (RMP)" bitfld.long 0x00 31. "DFT_EN,this bit is combined with the 3 bits 2:0 to form RMP[3:0]" "0,1" newline bitfld.long 0x00 0.--2. "DFT_MODE,this bit is combined with bit 31 to form RMP[3:0] it must always be written with '3' for correct operation" "0,1,2,3,4,5,6,7" group.long 0x80++0x03 line.long 0x00 "OA0_SW,Opamp0 switch control" bitfld.long 0x00 21. "OA0O_D81,Opamp0 output switch to short 1x with 1L0xdrive" "0,1" newline bitfld.long 0x00 18. "OA0O_D51,Opamp0 output sarbus0 (ctbbus2 in CTB)" "0,1" newline bitfld.long 0x00 14. "OA0M_A81,Opamp0 negative terminal Opamp0 output" "0,1" newline bitfld.long 0x00 8. "OA0M_A11,Opamp0 negative terminal P1" "0,1" newline bitfld.long 0x00 3. "OA0P_A30,Opamp0 positive terminal ctbbus0" "0,1" newline bitfld.long 0x00 2. "OA0P_A20,Opamp0 positive terminal P0" "0,1" newline bitfld.long 0x00 0. "OA0P_A00,Opamp0 positive terminal amuxbusa" "0,1" group.long 0x84++0x03 line.long 0x00 "OA0_SW_CLEAR,Opamp0 switch control clear" bitfld.long 0x00 21. "OA0O_D81,see corresponding bit in OA0_SW" "0,1" newline bitfld.long 0x00 18. "OA0O_D51,see corresponding bit in OA0_SW" "0,1" newline bitfld.long 0x00 14. "OA0M_A81,see corresponding bit in OA0_SW" "0,1" newline bitfld.long 0x00 8. "OA0M_A11,see corresponding bit in OA0_SW" "0,1" newline bitfld.long 0x00 3. "OA0P_A30,see corresponding bit in OA0_SW" "0,1" newline bitfld.long 0x00 2. "OA0P_A20,see corresponding bit in OA0_SW" "0,1" newline bitfld.long 0x00 0. "OA0P_A00,see corresponding bit in OA0_SW" "0,1" group.long 0x88++0x03 line.long 0x00 "OA1_SW,Opamp1 switch control" bitfld.long 0x00 21. "OA1O_D82,Opamp1 output switch to short 1x with 1L0xdrive" "0,1" newline bitfld.long 0x00 19. "OA1O_D62,Opamp1 output sarbus1 (ctbbus3 in CTB)" "0,1" newline bitfld.long 0x00 18. "OA1O_D52,Opamp1 output sarbus0 (ctbbus2 in CTB)" "0,1" newline bitfld.long 0x00 14. "OA1M_A82,Opamp1 negative terminal Opamp1 output" "0,1" newline bitfld.long 0x00 8. "OA1M_A22,Opamp1 negative terminal P4" "0,1" newline bitfld.long 0x00 4. "OA1P_A43,Opamp1 positive terminal ctbbus1" "0,1" newline bitfld.long 0x00 1. "OA1P_A13,Opamp1 positive terminal P5" "0,1" newline bitfld.long 0x00 0. "OA1P_A03,Opamp1 positive terminal amuxbusb" "0,1" group.long 0x8C++0x03 line.long 0x00 "OA1_SW_CLEAR,Opamp1 switch control clear" bitfld.long 0x00 21. "OA1O_D82,see corresponding bit in OA1_SW" "0,1" newline bitfld.long 0x00 19. "OA1O_D62,see corresponding bit in OA1_SW" "0,1" newline bitfld.long 0x00 18. "OA1O_D52,see corresponding bit in OA1_SW" "0,1" newline bitfld.long 0x00 14. "OA1M_A82,see corresponding bit in OA1_SW" "0,1" newline bitfld.long 0x00 8. "OA1M_A22,see corresponding bit in OA1_SW" "0,1" newline bitfld.long 0x00 4. "OA1P_A43,see corresponding bit in OA1_SW" "0,1" newline bitfld.long 0x00 1. "OA1P_A13,see corresponding bit in OA1_SW" "0,1" newline bitfld.long 0x00 0. "OA1P_A03,see corresponding bit in OA1_SW" "0,1" group.long 0xC0++0x03 line.long 0x00 "CTB_SW_HW_CTRL,CTB bus switch control" bitfld.long 0x00 3. "P3_HW_CTRL,for P33 D52 D62 (dsi_out[3])" "0,1" newline bitfld.long 0x00 2. "P2_HW_CTRL,for P22 D51 (dsi_out[2])" "0,1" rgroup.long 0xC4++0x03 line.long 0x00 "CTB_SW_STATUS,CTB bus switch control status" bitfld.long 0x00 30. "OA1O_D62_STAT,see OA1O_D62 bit in OA1_SW" "0,1" newline bitfld.long 0x00 29. "OA1O_D52_STAT,see OA1O_D52 bit in OA1_SW" "0,1" newline bitfld.long 0x00 28. "OA0O_D51_STAT,see OA0O_D51 bit in OA0_SW" "0,1" group.long 0xF00++0x03 line.long 0x00 "OA0_OFFSET_TRIM,Opamp0 trim control" bitfld.long 0x00 0.--5. "OA0_OFFSET_TRIM,Opamp0 offset trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xF04++0x03 line.long 0x00 "OA0_SLOPE_OFFSET_TRIM,Opamp0 trim control" bitfld.long 0x00 0.--5. "OA0_SLOPE_OFFSET_TRIM,Opamp0 slope offset drift trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xF08++0x03 line.long 0x00 "OA0_COMP_TRIM,Opamp0 trim control" bitfld.long 0x00 0.--1. "OA0_COMP_TRIM,Opamp 0 Compensation Capacitor Trim" "0,1,2,3" group.long 0xF0C++0x03 line.long 0x00 "OA1_OFFSET_TRIM,Opamp1 trim control" bitfld.long 0x00 0.--5. "OA1_OFFSET_TRIM,Opamp1 offset trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xF10++0x03 line.long 0x00 "OA1_SLOPE_OFFSET_TRIM,Opamp1 trim control" bitfld.long 0x00 0.--5. "OA1_SLOPE_OFFSET_TRIM,Opamp1 slope offset drift trim" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xF14++0x03 line.long 0x00 "OA1_COMP_TRIM,Opamp1 trim control" bitfld.long 0x00 0.--1. "OA1_COMP_TRIM,Opamp 1 Compensation Capacitor Trim" "0,1,2,3" tree.end tree "DMAC (DataWire/DMA Controller)" base ad:0x40101000 group.long 0x00++0x03 line.long 0x00 "CTL,Control register" bitfld.long 0x00 31. "ENABLED,0': IP is disabled" "0,1" rgroup.long 0x10++0x03 line.long 0x00 "STATUS,Status register" bitfld.long 0x00 31. "ACTIVE,Specifies if there is a currently active (pending) channel in the data transfer engine: '0': no currently active channel" "0,1" bitfld.long 0x00 30. "PING_PONG,Specifies the descriptor of the channel is currently in use" "0,1" bitfld.long 0x00 28.--29. "PRIO,Specifies the priority of the currently active channel" "0,1,2,3" bitfld.long 0x00 24.--26. "STATE,State of the data transfer engine" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--20. "CH_ADDR,Specifies the channel number of the currently active channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x00 0.--15. 1. "DATA_NR,Specifies the index of the currently active data transfer" rgroup.long 0x14++0x03 line.long 0x00 "STATUS_SRC_ADDR,Source address status register" hexmask.long 0x00 0.--31. 1. "ADDR,Base address or current address of source location of currently active channel" rgroup.long 0x18++0x03 line.long 0x00 "STATUS_DST_ADDR,Destination address register" hexmask.long 0x00 0.--31. 1. "ADDR,Base address or current address of destination location of currently active channel" rgroup.long 0x1C++0x03 line.long 0x00 "STATUS_CH_ACT,Channel activation status register" hexmask.long 0x00 0.--31. 1. "CH,Channel activation status" repeat 32. (increment 0 1) (increment 0 0x4) group.long ($2+0x80)++0x03 line.long 0x00 "CH_CTL[$1],Channel control register $1" bitfld.long 0x00 31. "ENABLED,'0': channel disabled" "0,1" bitfld.long 0x00 30. "PING_PONG,Each channel has two descriptor structures for double buffering purposes" "0,1" bitfld.long 0x00 28.--29. "PRIO,Channel priority with '0' representing the highest priority and '3' representing the lowest priority" "0,1,2,3" repeat.end group.long 0x7F0++0x03 line.long 0x00 "INTR,Interrupt register" hexmask.long 0x00 0.--31. 1. "CH,Set to '1' when event is detected" group.long 0x7F4++0x03 line.long 0x00 "INTR_SET,Interrupt set register" hexmask.long 0x00 0.--31. 1. "CH,Write INTR_SET field with '1' to set corresponding INTR field (a write of '0' has no effect)" group.long 0x7F8++0x03 line.long 0x00 "INTR_MASK,Interrupt mask register" hexmask.long 0x00 0.--31. 1. "CH,Mask for corresponding field in INTR register" rgroup.long 0x7FC++0x03 line.long 0x00 "INTR_MASKED,Interrupt masked register" hexmask.long 0x00 0.--31. 1. "CH,Logical BITWISE AND of corresponding request and mask fields" repeat 16. (increment 0 1)(increment 0 0x20) tree "DESCR[$1]" group.long ($2+0x800)++0x03 line.long 0x00 "PING_SRC,Ping source address" hexmask.long 0x00 0.--31. 1. "ADDR,Base address of source location" group.long ($2+0x804)++0x03 line.long 0x00 "PING_DST,Ping destination address" hexmask.long 0x00 0.--31. 1. "ADDR,Base address of destination location" group.long ($2+0x808)++0x03 line.long 0x00 "PING_CTL,Ping control word" bitfld.long 0x00 30.--31. "OPCODE,Specifies the specific data transfer (only when the VALID bit of the descriptor's STATUS word is '1'): '0': A single trigger initiates a single data element transfer (DW mode)" "0,1,2,3" bitfld.long 0x00 29. "FLIPPING,'1': On completion of the current descriptor structure the current descriptor identifier CH_CTLi.PING_PONG is flipped/inverted" "0,1" bitfld.long 0x00 28. "PREEMPTABLE,'1': Transfer is preemptable" "0,1" bitfld.long 0x00 27. "SET_CAUSE,'1': On completion of the current descriptor structure the interrupt cause field of the channel is set to '1' (INTR.CH[i])" "0,1" bitfld.long 0x00 26. "INV_DESCR,'1': On completion of the current descriptor structure the VALID bit of the descriptor's STATUS word is set to '0'" "0,1" bitfld.long 0x00 24.--25. "WAIT_FOR_DEACT,Specifies whether the data transfer engine should wait for the channel to be deactivated i.e" "0,1,2,3" newline bitfld.long 0x00 23. "SRC_ADDR_INCR,Specifies whether the source location address is incremented by the SRC_TRANSFER_SIZE after each single data element transfer or not" "0,1" bitfld.long 0x00 22. "SRC_TRANSFER_SIZE,Specifies the bus transfer size to the source location: '0': As specified by DATA_SIZE" "0,1" bitfld.long 0x00 21. "DST_ADDR_INCR,Specifies whether the destination location address is incremented by the DST_TRANSFER_SIZE after each single data element transfer or not" "0,1" bitfld.long 0x00 20. "DST_TRANSFER_SIZE,Specifies the bus transfer size to the destination location: '0': As specified by DATA_SIZE" "0,1" bitfld.long 0x00 16.--17. "DATA_SIZE,Specifies the data element size: '0': Byte (8 bits)" "0,1,2,3" hexmask.long.word 0x00 0.--15. 1. "DATA_NR,Number of data elements that are transferred by a single descriptor" group.long ($2+0x80C)++0x03 line.long 0x00 "PING_STATUS,Ping status word" bitfld.long 0x00 31. "VALID,'0': Invalid cannot be used for a data transfer" "0,1" bitfld.long 0x00 16.--18. "RESPONSE,Response code (the first two codes NO_ERROR and DONE are the result of normal behavior the other codes are the result of erroneous behavior)" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--15. 1. "CURR_DATA_NR,Specifies the index of the current data transfer" group.long ($2+0x810)++0x03 line.long 0x00 "PONG_SRC,Pong source address" hexmask.long 0x00 0.--31. 1. "ADDR,See description of PING_SRC" group.long ($2+0x814)++0x03 line.long 0x00 "PONG_DST,Pong destination address" hexmask.long 0x00 0.--31. 1. "ADDR,See description of PING_DST" group.long ($2+0x818)++0x03 line.long 0x00 "PONG_CTL,Pong control word" bitfld.long 0x00 30.--31. "OPCODE,See description of PING_CTL" "0,1,2,3" bitfld.long 0x00 29. "FLIPPING,See description of PING_CTL" "0,1" bitfld.long 0x00 28. "PREEMPTABLE,See description of PING_CTL" "0,1" bitfld.long 0x00 27. "SET_CAUSE,See description of PING_CTL" "0,1" bitfld.long 0x00 26. "INV_DESCR,See description of PING_CTL" "0,1" bitfld.long 0x00 24.--25. "WAIT_FOR_DEACT,See description of PING_CTL" "0,1,2,3" newline bitfld.long 0x00 23. "SRC_ADDR_INCR,See description of PING_CTL" "0,1" bitfld.long 0x00 22. "SRC_TRANSFER_SIZE,See description of PING_CTL" "0,1" bitfld.long 0x00 21. "DST_ADDR_INCR,See description of PING_CTL" "0,1" bitfld.long 0x00 20. "DST_TRANSFER_SIZE,See description of PING_CTL" "0,1" bitfld.long 0x00 16.--17. "DATA_SIZE,See description of PING_CTL" "0,1,2,3" hexmask.long.word 0x00 0.--15. 1. "DATA_NR,See description of PING_CTL" group.long ($2+0x81C)++0x03 line.long 0x00 "PONG_STATUS,Pong status word" bitfld.long 0x00 31. "VALID,See description of PING_STATUS" "0,1" bitfld.long 0x00 16.--18. "RESPONSE,See description of PING_STATUS" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--15. 1. "CURR_DATA_NR,See description of PING_STATUS" tree.end repeat.end tree.end endif tree "GPIO (General Purpose I/O Ports And Peripheral I/O Lines)" base ad:0x40040000 rgroup.long 0x1000++0x03 line.long 0x00 "INTR_CAUSE,Interrupt port cause register" hexmask.long 0x00 0.--31. 1. "PORT_INT,Each IO port has an associated bit field in this register" rgroup.long 0x1020++0x03 line.long 0x00 "GPIOV1P2_DET,GPIOV1P2 Detect output" bitfld.long 0x00 0. "DET,Indicates HI when VDDIO is in 1.8V range and LOW when VDDIO is in 1.2V range" "0,1" repeat 9. (increment 0 1)(increment 0 0x100) tree "PRT[$1]" group.long ($2+0x00)++0x03 line.long 0x00 "DR,Port output data register" bitfld.long 0x00 7. "DATA7,IO pad 7 output data" "0,1" newline bitfld.long 0x00 6. "DATA6,IO pad 6 output data" "0,1" newline bitfld.long 0x00 5. "DATA5,IO pad 5 output data" "0,1" newline bitfld.long 0x00 4. "DATA4,IO pad 4 output data" "0,1" newline bitfld.long 0x00 3. "DATA3,IO pad 3 output data" "0,1" newline bitfld.long 0x00 2. "DATA2,IO pad 2 output data" "0,1" newline bitfld.long 0x00 1. "DATA1,IO pad 1 output data" "0,1" newline bitfld.long 0x00 0. "DATA0,IO pad 0 output data" "0,1" rgroup.long ($2+0x04)++0x03 line.long 0x00 "PS,Port IO pad state register" bitfld.long 0x00 8. "FLT_DATA,Reads of this register return the logical state of the filtered pin" "0,1" newline bitfld.long 0x00 7. "DATA7,IO pad 7 state" "0,1" newline bitfld.long 0x00 6. "DATA6,IO pad 6 state" "0,1" newline bitfld.long 0x00 5. "DATA5,IO pad 5 state" "0,1" newline bitfld.long 0x00 4. "DATA4,IO pad 4 state" "0,1" newline bitfld.long 0x00 3. "DATA3,IO pad 3 state" "0,1" newline bitfld.long 0x00 2. "DATA2,IO pad 2 state" "0,1" newline bitfld.long 0x00 1. "DATA1,IO pad 1 state" "0,1" newline bitfld.long 0x00 0. "DATA0,IO pad 0 state" "0: Logic low if the pin voltage is below that,1: Logic high if the pin voltage is above the.." group.long ($2+0x08)++0x03 line.long 0x00 "PC,Port configuration register" bitfld.long 0x00 30.--31. "PORT_IB_MODE_SEL,This field selects the input buffer reference" "0,1,2,3" newline bitfld.long 0x00 28.--29. "PORT_SLEW_CTL,Slew control" "0: HS mode (100pf < Cb < 400pF 1.712.8..,2: HS mode (100pf,2: PTAT<1>,3: PTAT<1:0>,4: PTAT<2>,?,?,7: PTAT<2:0>,8: PTAT<3>,9: DSAB Reg Out,?,?,?,?,?,15: PTAT<3:0>" tree.end tree.end endif tree "PERI (Peripheral Interconnect)" base ad:0x40010000 group.long 0x00++0x03 line.long 0x00 "DIV_CMD,Divider command register" bitfld.long 0x00 31. "ENABLE,Clock divider enable command (mutually exclusive with DISABLE)" "0: Disable the divider using the DIV_CMD.DISABLE,1: Configure the divider's DIV_XXX_CTL register" bitfld.long 0x00 30. "DISABLE,Clock divider disable command (mutually exlusive with ENABLE)" "0,1" newline bitfld.long 0x00 14.--15. "PA_SEL_TYPE,Specifies the divider type of the divider to which phase alignment is performed for the clock enable command" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers" bitfld.long 0x00 8.--13. "PA_SEL_DIV,(PA_SEL_TYPE PA_SEL_DIV) pecifies the divider to which phase alignment is performed for the clock enable command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 6.--7. "SEL_TYPE,Specifies the divider type of the divider on which the command is performed" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers" bitfld.long 0x00 0.--5. "SEL_DIV,(SEL_TYPE SEL_DIV) specifies the divider on which the command (DISABLE/ENABLE) is performed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" repeat 64. (increment 0 1) (increment 0 0x04) group.long ($2+0x100)++0x03 line.long 0x00 "PCLK_CTL[$1],Programmable clock control register $1" bitfld.long 0x00 6.--7. "SEL_TYPE,Specifies divider type" "0: 8.0 (integer) clock dividers,1: 16.0 (integer) clock dividers,2: 16.5 (fractional) clock dividers,3: 24.5 (fractional) clock dividers" bitfld.long 0x00 0.--5. "SEL_DIV,Specifies one of the dividers of the divider type specified by SEL_TYPE" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" repeat.end repeat 64. (increment 0 1) (increment 0 0x04) group.long ($2+0x200)++0x03 line.long 0x00 "DIV_8_CTL[$1],Divider control register (for 8.0 divider $1" hexmask.long.byte 0x00 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV)" rbitfld.long 0x00 0. "EN,Divider enabled" "0,1" repeat.end repeat 64. (increment 0 1) (increment 0 0x04) group.long ($2+0x300)++0x03 line.long 0x00 "DIV_16_CTL[$1],Divider control register (for 16.0 divider $1" hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)" rbitfld.long 0x00 0. "EN,Divider enabled" "0,1" repeat.end repeat 64. (increment 0 1) (increment 0 0x04) group.long ($2+0x400)++0x03 line.long 0x00 "DIV_16_5_CTL[$1],Divider control register (for 16.5 divider $1" hexmask.long.word 0x00 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV)" bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 0. "EN,Divider enabled" "0,1" repeat.end repeat 63. (increment 0 1) (increment 0 0x04) group.long ($2+0x500)++0x03 line.long 0x00 "DIV_24_5_CTL[$1],Divider control register (for 24.5 divider $1" hexmask.long.tbyte 0x00 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV)" bitfld.long 0x00 3.--7. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 0. "EN,Divider enabled" "0,1" repeat.end group.long 0x600++0x03 line.long 0x00 "TR_CTL,Trigger control register" bitfld.long 0x00 31. "TR_ACT,SW sets this field to '1' by to activate (set to '1') a trigger as identified by TR_SEL and TR_OUT for TR_COUNT cycles" "0,1" bitfld.long 0x00 30. "TR_OUT,Specifies whether trigger activation is for a specific input or ouput trigger of the trigger multiplexer" "0,1" newline hexmask.long.byte 0x00 16.--23. 1. "TR_COUNT,Amount of cycles a specific trigger is activated" bitfld.long 0x00 8.--11. "TR_GROUP,Specifies the trigger group" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 0.--6. 1. "TR_SEL,Specifies the activated trigger when TR_ACT is '1'" repeat 5. (increment 0 1)(increment 0 0x200) tree "TR_GROUP[$1]" group.long ($2+0x2000)++0x03 line.long 0x00 "TR_OUT_CTL[0],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2004)++0x03 line.long 0x00 "TR_OUT_CTL[1],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2008)++0x03 line.long 0x00 "TR_OUT_CTL[2],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x200C)++0x03 line.long 0x00 "TR_OUT_CTL[3],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2010)++0x03 line.long 0x00 "TR_OUT_CTL[4],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2014)++0x03 line.long 0x00 "TR_OUT_CTL[5],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2018)++0x03 line.long 0x00 "TR_OUT_CTL[6],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x201C)++0x03 line.long 0x00 "TR_OUT_CTL[7],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2020)++0x03 line.long 0x00 "TR_OUT_CTL[8],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2024)++0x03 line.long 0x00 "TR_OUT_CTL[9],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2028)++0x03 line.long 0x00 "TR_OUT_CTL[10],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x202C)++0x03 line.long 0x00 "TR_OUT_CTL[11],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2030)++0x03 line.long 0x00 "TR_OUT_CTL[12],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2034)++0x03 line.long 0x00 "TR_OUT_CTL[13],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2038)++0x03 line.long 0x00 "TR_OUT_CTL[14],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x203C)++0x03 line.long 0x00 "TR_OUT_CTL[15],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2040)++0x03 line.long 0x00 "TR_OUT_CTL[16],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2044)++0x03 line.long 0x00 "TR_OUT_CTL[17],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2048)++0x03 line.long 0x00 "TR_OUT_CTL[18],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x204C)++0x03 line.long 0x00 "TR_OUT_CTL[19],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2050)++0x03 line.long 0x00 "TR_OUT_CTL[20],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2054)++0x03 line.long 0x00 "TR_OUT_CTL[21],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2058)++0x03 line.long 0x00 "TR_OUT_CTL[22],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x205C)++0x03 line.long 0x00 "TR_OUT_CTL[23],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2060)++0x03 line.long 0x00 "TR_OUT_CTL[24],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2064)++0x03 line.long 0x00 "TR_OUT_CTL[25],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2068)++0x03 line.long 0x00 "TR_OUT_CTL[26],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x206C)++0x03 line.long 0x00 "TR_OUT_CTL[27],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2070)++0x03 line.long 0x00 "TR_OUT_CTL[28],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2074)++0x03 line.long 0x00 "TR_OUT_CTL[29],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2078)++0x03 line.long 0x00 "TR_OUT_CTL[30],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x207C)++0x03 line.long 0x00 "TR_OUT_CTL[31],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2080)++0x03 line.long 0x00 "TR_OUT_CTL[32],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2084)++0x03 line.long 0x00 "TR_OUT_CTL[33],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2088)++0x03 line.long 0x00 "TR_OUT_CTL[34],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x208C)++0x03 line.long 0x00 "TR_OUT_CTL[35],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2090)++0x03 line.long 0x00 "TR_OUT_CTL[36],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2094)++0x03 line.long 0x00 "TR_OUT_CTL[37],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2098)++0x03 line.long 0x00 "TR_OUT_CTL[38],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x209C)++0x03 line.long 0x00 "TR_OUT_CTL[39],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x20A0)++0x03 line.long 0x00 "TR_OUT_CTL[40],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x20A4)++0x03 line.long 0x00 "TR_OUT_CTL[41],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x20A8)++0x03 line.long 0x00 "TR_OUT_CTL[42],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x20AC)++0x03 line.long 0x00 "TR_OUT_CTL[43],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x20B0)++0x03 line.long 0x00 "TR_OUT_CTL[44],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x20B4)++0x03 line.long 0x00 "TR_OUT_CTL[45],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x20B8)++0x03 line.long 0x00 "TR_OUT_CTL[46],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x20BC)++0x03 line.long 0x00 "TR_OUT_CTL[47],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x20C0)++0x03 line.long 0x00 "TR_OUT_CTL[48],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x20C4)++0x03 line.long 0x00 "TR_OUT_CTL[49],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x20C8)++0x03 line.long 0x00 "TR_OUT_CTL[50],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x20CC)++0x03 line.long 0x00 "TR_OUT_CTL[51],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x20D0)++0x03 line.long 0x00 "TR_OUT_CTL[52],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x20D4)++0x03 line.long 0x00 "TR_OUT_CTL[53],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x20D8)++0x03 line.long 0x00 "TR_OUT_CTL[54],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x20DC)++0x03 line.long 0x00 "TR_OUT_CTL[55],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x20E0)++0x03 line.long 0x00 "TR_OUT_CTL[56],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x20E4)++0x03 line.long 0x00 "TR_OUT_CTL[57],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x20E8)++0x03 line.long 0x00 "TR_OUT_CTL[58],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x20EC)++0x03 line.long 0x00 "TR_OUT_CTL[59],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x20F0)++0x03 line.long 0x00 "TR_OUT_CTL[60],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x20F4)++0x03 line.long 0x00 "TR_OUT_CTL[61],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x20F8)++0x03 line.long 0x00 "TR_OUT_CTL[62],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x20FC)++0x03 line.long 0x00 "TR_OUT_CTL[63],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2100)++0x03 line.long 0x00 "TR_OUT_CTL[64],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2104)++0x03 line.long 0x00 "TR_OUT_CTL[65],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2108)++0x03 line.long 0x00 "TR_OUT_CTL[66],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x210C)++0x03 line.long 0x00 "TR_OUT_CTL[67],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2110)++0x03 line.long 0x00 "TR_OUT_CTL[68],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2114)++0x03 line.long 0x00 "TR_OUT_CTL[69],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2118)++0x03 line.long 0x00 "TR_OUT_CTL[70],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x211C)++0x03 line.long 0x00 "TR_OUT_CTL[71],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2120)++0x03 line.long 0x00 "TR_OUT_CTL[72],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2124)++0x03 line.long 0x00 "TR_OUT_CTL[73],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2128)++0x03 line.long 0x00 "TR_OUT_CTL[74],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x212C)++0x03 line.long 0x00 "TR_OUT_CTL[75],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2130)++0x03 line.long 0x00 "TR_OUT_CTL[76],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2134)++0x03 line.long 0x00 "TR_OUT_CTL[77],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2138)++0x03 line.long 0x00 "TR_OUT_CTL[78],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x213C)++0x03 line.long 0x00 "TR_OUT_CTL[79],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2140)++0x03 line.long 0x00 "TR_OUT_CTL[80],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2144)++0x03 line.long 0x00 "TR_OUT_CTL[81],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2148)++0x03 line.long 0x00 "TR_OUT_CTL[82],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x214C)++0x03 line.long 0x00 "TR_OUT_CTL[83],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2150)++0x03 line.long 0x00 "TR_OUT_CTL[84],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2154)++0x03 line.long 0x00 "TR_OUT_CTL[85],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2158)++0x03 line.long 0x00 "TR_OUT_CTL[86],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x215C)++0x03 line.long 0x00 "TR_OUT_CTL[87],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2160)++0x03 line.long 0x00 "TR_OUT_CTL[88],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2164)++0x03 line.long 0x00 "TR_OUT_CTL[89],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2168)++0x03 line.long 0x00 "TR_OUT_CTL[90],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x216C)++0x03 line.long 0x00 "TR_OUT_CTL[91],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2170)++0x03 line.long 0x00 "TR_OUT_CTL[92],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2174)++0x03 line.long 0x00 "TR_OUT_CTL[93],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2178)++0x03 line.long 0x00 "TR_OUT_CTL[94],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x217C)++0x03 line.long 0x00 "TR_OUT_CTL[95],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2180)++0x03 line.long 0x00 "TR_OUT_CTL[96],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2184)++0x03 line.long 0x00 "TR_OUT_CTL[97],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2188)++0x03 line.long 0x00 "TR_OUT_CTL[98],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x218C)++0x03 line.long 0x00 "TR_OUT_CTL[99],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2190)++0x03 line.long 0x00 "TR_OUT_CTL[100],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2194)++0x03 line.long 0x00 "TR_OUT_CTL[101],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x2198)++0x03 line.long 0x00 "TR_OUT_CTL[102],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x219C)++0x03 line.long 0x00 "TR_OUT_CTL[103],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x21A0)++0x03 line.long 0x00 "TR_OUT_CTL[104],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x21A4)++0x03 line.long 0x00 "TR_OUT_CTL[105],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x21A8)++0x03 line.long 0x00 "TR_OUT_CTL[106],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x21AC)++0x03 line.long 0x00 "TR_OUT_CTL[107],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x21B0)++0x03 line.long 0x00 "TR_OUT_CTL[108],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x21B4)++0x03 line.long 0x00 "TR_OUT_CTL[109],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x21B8)++0x03 line.long 0x00 "TR_OUT_CTL[110],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x21BC)++0x03 line.long 0x00 "TR_OUT_CTL[111],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x21C0)++0x03 line.long 0x00 "TR_OUT_CTL[112],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x21C4)++0x03 line.long 0x00 "TR_OUT_CTL[113],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x21C8)++0x03 line.long 0x00 "TR_OUT_CTL[114],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x21CC)++0x03 line.long 0x00 "TR_OUT_CTL[115],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x21D0)++0x03 line.long 0x00 "TR_OUT_CTL[116],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x21D4)++0x03 line.long 0x00 "TR_OUT_CTL[117],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x21D8)++0x03 line.long 0x00 "TR_OUT_CTL[118],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x21DC)++0x03 line.long 0x00 "TR_OUT_CTL[119],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x21E0)++0x03 line.long 0x00 "TR_OUT_CTL[120],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x21E4)++0x03 line.long 0x00 "TR_OUT_CTL[121],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x21E8)++0x03 line.long 0x00 "TR_OUT_CTL[122],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x21EC)++0x03 line.long 0x00 "TR_OUT_CTL[123],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x21F0)++0x03 line.long 0x00 "TR_OUT_CTL[124],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x21F4)++0x03 line.long 0x00 "TR_OUT_CTL[125],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x21F8)++0x03 line.long 0x00 "TR_OUT_CTL[126],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" group.long ($2+0x21FC)++0x03 line.long 0x00 "TR_OUT_CTL[127],Trigger control register" hexmask.long.byte 0x00 0.--6. 1. "SEL,Specifies input trigger" tree.end repeat.end tree.end sif cpuis("PMG1-S3") tree "SAR0 (SAR ADC with Sequencer)" base ad:0x403A0000 group.long 0x00++0x03 line.long 0x00 "CTRL,Analog control register" bitfld.long 0x00 31. "ENABLED,Before enabling always make sure the SAR is idle (STATUS.BUSY==0)" "0: SAR IP disabled (put analog in power,1: SAR IP enabled" newline bitfld.long 0x00 30. "SWITCH_DISABLE,Disable SAR sequencer from enabling routing switches (note DSI and firmware can always close switches independent of this control)" "0: Normal mode SAR sequencer changes switches,1: Switches disabled SAR sequencer does not enable" newline bitfld.long 0x00 29. "DSI_MODE,SAR sequencer takes configuration from DSI signals (note this also has the same effect as SWITCH_DISABLE==1)" "0: Normal mode SAR sequencer operates according to,1: CHAN_EN INJ_START_EN and channel configurations" newline bitfld.long 0x00 28. "DSI_SYNC_CONFIG," "0: bypass clock domain synchronisation of the DSI,1: synchronize the DSI config signals to.." newline bitfld.long 0x00 27. "DEEPSLEEP_ON," "0: SARMUX IP disabled off during DeepSleep power..,1: SARMUX IP remains enabled during DeepSleep.." newline bitfld.long 0x00 24.--25. "ICONT_LV,SARADC low power mode" "0: normal power (default) max clk_sar is 18MHz,1: 1/2 power mode max clk_sar is 9MHz,2: 1.333 power mode max clk_sar is 18MHz,3: 1/4 power mode max clk_sar is 4.5MHz" newline bitfld.long 0x00 20. "BOOSTPUMP_EN,SARADC internal pump" "0: disabled,1: enabled" newline bitfld.long 0x00 16.--19. "SPARE,Spare controls not yet designated for late changes done with an ECO" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "PWR_CTRL_VREF,VREF buffer low power mode" "0: normal power (default) bypass cap max clk_sar..,1: deprecated,2: Invalid for PSoC4A otherwise 2X power no..,3: QUARTER_PWR" newline bitfld.long 0x00 13. "SAR_HW_CTRL_NEGVREF,Hardware control" "0: only firmware control,1: hardware control masked by firmware setting for" newline bitfld.long 0x00 9.--11. "NEG_SEL,SARADC internal NEG selection for Single ended conversion" "0: NEG input of SARADC is connected to..,1: NEG input of SARADC is connected to VSSA in..,2: NEG input of SARADC is connected to P1 pin of..,3: NEG input of SARADC is connected to P3 pin of..,4: NEG input of SARADC is connected to P5 pin of..,5: NEG input of SARADC is connected to P7 pin of..,6: NEG input of SARADC is connected to an ACORE..,7: NEG input of SARADC is shorted with VREF.." newline bitfld.long 0x00 7. "VREF_BYP_CAP_EN,VREF bypass cap enable for when VREF buffer is on" "0,1" newline bitfld.long 0x00 4.--6. "VREF_SEL,SARADC internal VREF selection" "0: VREF0 from PRB (VREF buffer on),1: VREF1 from PRB (VREF buffer on),2: VREF2 from PRB (VREF buffer on),3: VREF from AROUTE (VREF buffer on),4: 1.024V from BandGap (VREF buffer on),5: External precision Vref direct from a pin..,6: Vdda/2 (VREF buffer on),7: Vdda" group.long 0x04++0x03 line.long 0x00 "SAMPLE_CTRL,Sample control register" bitfld.long 0x00 31. "EOS_DSI_OUT_EN,Enable to output EOS_INTR to DSI" "0,1" newline bitfld.long 0x00 19. "DSI_SYNC_TRIGGER," "0: bypass clock domain synchronisation of the DSI,1: synchronize the DSI trigger signal to the SAR" newline bitfld.long 0x00 18. "DSI_TRIGGER_LEVEL," "0: DSI trigger signal is a pulse input a positive,1: DSI trigger signal is a level input as long as" newline bitfld.long 0x00 17. "DSI_TRIGGER_EN," "0: firmware trigger only,1: enable hardware (DSI) trigger (e.g. from TCPWM" newline bitfld.long 0x00 16. "CONTINUOUS," "0: Wait for next FW_TRIGGER (one shot) or hardware,1: Continuously scan enabled channels ignore.." newline bitfld.long 0x00 7. "AVG_SHIFT,Averaging shifting: after averaging the result is shifted right to fit in the sample resolution" "0,1" newline bitfld.long 0x00 4.--6. "AVG_CNT,Averaging Count for channels that have over sampling enabled (AVG_EN)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 3. "DIFFERENTIAL_SIGNED,Output data from a differential conversion as a signed value" "0: result data is unsigned (zero extended if..,1: Default" newline bitfld.long 0x00 2. "SINGLE_ENDED_SIGNED,Output data from a single ended conversion as a signed value" "0: Default,1: result data is signed (sign extended if needed)" newline bitfld.long 0x00 1. "LEFT_ALIGN,Left align data in data[15:0] default data is right aligned in data[11:0] with sign extension to 16 bits if the channel is differential" "0,1" newline bitfld.long 0x00 0. "SUB_RESOLUTION,Conversion resolution for channels that have sub-resolution enabled (RESOLUTION=1) (otherwise resolution is 12-bit)" "0: 8-bit,1: 10-bit" group.long 0x10++0x03 line.long 0x00 "SAMPLE_TIME01,Sample time specification ST0 and ST1" hexmask.long.word 0x00 16.--25. 1. "SAMPLE_TIME1,Sample time1" newline hexmask.long.word 0x00 0.--9. 1. "SAMPLE_TIME0,Sample time0 (aperture) in ADC clock cycles" group.long 0x14++0x03 line.long 0x00 "SAMPLE_TIME23,Sample time specification ST2 and ST3" hexmask.long.word 0x00 16.--25. 1. "SAMPLE_TIME3,Sample time3" newline hexmask.long.word 0x00 0.--9. 1. "SAMPLE_TIME2,Sample time2" group.long 0x18++0x03 line.long 0x00 "RANGE_THRES,Global range detect threshold register" hexmask.long.word 0x00 16.--31. 1. "RANGE_HIGH,High threshold for range detect" newline hexmask.long.word 0x00 0.--15. 1. "RANGE_LOW,Low threshold for range detect" group.long 0x1C++0x03 line.long 0x00 "RANGE_COND,Global range detect mode register" bitfld.long 0x00 30.--31. "RANGE_COND,Range condition select" "0: result < RANGE_LOW,1: RANGE_LOW <= result < RANGE_HIGH,2: RANGE_HIGH <= result,3: result < RANGE_LOW || RANGE_HIGH <= result" group.long 0x20++0x03 line.long 0x00 "CHAN_EN,Enable bits for the channels" abitfld.long 0x00 0.--15. "CHAN_EN,Channel enable" "0x0000=0: the corresponding channel is disabled,0x0001=1: the corresponding channel is enabled.." group.long 0x24++0x03 line.long 0x00 "START_CTRL,Start control register (firmware trigger)" bitfld.long 0x00 0. "FW_TRIGGER,When firmware writes a 1 here it will trigger the next scan of enabled channels hardware clears this bit when the scan started with this trigger is completed" "0,1" group.long 0x30++0x03 line.long 0x00 "DFT_CTRL,DFT control register" bitfld.long 0x00 31. "ADFT_OVERRIDE,During deepsleep/ hibernate mode keep SARMUX active i.e" "0,1" newline bitfld.long 0x00 29. "DCEN,Delay Control Enable for latch" "0: doubles the latch enable time,1: normal latch enable time (default)" newline bitfld.long 0x00 28. "EN_CSEL_DFT,Mux select signal for DAC control" "0,1" newline bitfld.long 0x00 24.--27. "SEL_CSEL_DFT,Usage" "?,1: DFT bits for DAC array Usage,2: For [0]=1 (when dcen=0),?..." newline bitfld.long 0x00 20.--22. "DFT_OUTC,DFT control for preamp outputs" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 16.--19. "DFT_INC,DFT control for preamp inputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 1. "HIZ,DFT control for getting higher input impedance must be 1 (0 is deprecated)" "0,1" newline bitfld.long 0x00 0. "DLY_INC,DFT control: Control for delay circuits on sampling phase =1 doubes the non-overlap delay" "0,1" repeat 16. (increment 0 1) (increment 0 0x4) group.long ($2+0x80)++0x03 line.long 0x00 "CHAN_CONFIG[$1],Channel configuration register $1" bitfld.long 0x00 31. "DSI_OUT_EN,DSI data output enable for this channel" "0: the conversion result for this channel is only,1: the conversion result for this channel is.." newline bitfld.long 0x00 12.--13. "SAMPLE_TIME_SEL,Sample time select: select which of the 4 global sample times to use for this channel" "0,1,2,3" newline bitfld.long 0x00 10. "AVG_EN,Averaging enable for this channel" "0,1" newline bitfld.long 0x00 9. "RESOLUTION,Resolution for this channel" "0: The maximum resolution is used for this..,1: The resolution specified by SUB_RESOLUTION in.." newline bitfld.long 0x00 8. "DIFFERENTIAL_EN,Differential enable for this channel" "0: The voltage on the addressed pin is measured,1: The differential voltage on the addressed pin" newline bitfld.long 0x00 4.--6. "PORT_ADDR,Address of the port that contains the pin to be sampled by this channel" "0: SARMUX pins,1: CTB0,2: CTB1,3: CTB2,4: CTB3,5: AROUTE virtual port2 (VPORT2),6: AROUTE virtual port1 (VPORT1),7: SARMUX virtual port (VPORT0)" newline bitfld.long 0x00 0.--2. "PIN_ADDR,Address of the pin to be sampled by this channel" "0,1,2,3,4,5,6,7" repeat.end repeat 16. (increment 0 1) (increment 0 0x04) rgroup.long ($2+0x100)++0x03 line.long 0x00 "CHAN_WORK[$1],Channel working data register $1" bitfld.long 0x00 31. "CHAN_WORK_VALID_MIR,mirror bit of corresponding bit in SAR_CHAN_WORK_VALID register" "0,1" newline hexmask.long.word 0x00 0.--15. 1. "WORK,SAR conversion working data of the channel" repeat.end repeat 16. (increment 0 1) (increment 0 0x04) rgroup.long ($2+0x180)++0x03 line.long 0x00 "CHAN_RESULT[$1],Channel result data register $1" bitfld.long 0x00 31. "CHAN_RESULT_VALID_MIR,mirror bit of corresponding bit in SAR_CHAN_RESULT_VALID register" "0,1" newline bitfld.long 0x00 30. "RANGE_INTR_MIR,mirror bit of corresponding bit in SAR_RANGE_INTR register" "0,1" newline bitfld.long 0x00 29. "SATURATE_INTR_MIR,mirror bit of corresponding bit in SAR_SATURATE_INTR register" "0,1" newline hexmask.long.word 0x00 0.--15. 1. "RESULT,SAR conversion result of the channel" repeat.end rgroup.long 0x200++0x03 line.long 0x00 "CHAN_WORK_VALID,Channel working data register valid bits" hexmask.long.word 0x00 0.--15. 1. "CHAN_WORK_VALID,If set the corresponding WORK data is valid i.e" rgroup.long 0x204++0x03 line.long 0x00 "CHAN_RESULT_VALID,Channel result data register valid bits" hexmask.long.word 0x00 0.--15. 1. "CHAN_RESULT_VALID,If set the corresponding RESULT data is valid i.e" rgroup.long 0x208++0x03 line.long 0x00 "STATUS,Current status of internal SAR registers (mostly for debug)" bitfld.long 0x00 31. "BUSY,If high then the SAR is busy with a conversion" "0,1" newline bitfld.long 0x00 30. "SW_VREF_NEG,the current switch status including DSI and sequencer controls of the switch in the SARADC that shorts NEG with VREF input (see NEG_SEL)" "0,1" newline bitfld.long 0x00 0.--4. "CUR_CHAN,current channel being sampled (channel 16 indicates the injection channel) only valid if BUSY" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x20C++0x03 line.long 0x00 "AVG_STAT,Current averaging status (for debug)" hexmask.long.byte 0x00 24.--31. 1. "CUR_AVG_CNT,the current value of the averaging counter" newline hexmask.long.tbyte 0x00 0.--19. 1. "CUR_AVG_ACCU,the current value of the averaging accumulator" group.long 0x210++0x03 line.long 0x00 "INTR,Interrupt request register" bitfld.long 0x00 7. "INJ_COLLISION_INTR,Injection Collision Interrupt: hardware sets this interrupt when the injection trigger signal is asserted (INJ_START_EN==1 && INJ_TAILGATING==0) while the SAR is BUSY" "0,1" newline bitfld.long 0x00 6. "INJ_RANGE_INTR,Injection Range detect Interrupt: hardware sets this interrupt if the injection conversion result (after averaging) met the condition specified by the SAR_RANGE registers" "0,1" newline bitfld.long 0x00 5. "INJ_SATURATE_INTR,Injection Saturation Interrupt: hardware sets this interrupt if an injection conversion result (before averaging) is either 0x000 or 0xFFF (for 12-bit resolution) this is an indication that the ADC likely saturated" "0,1" newline bitfld.long 0x00 4. "INJ_EOC_INTR,Injection End of Conversion Interrupt: hardware sets this interrupt after completing the conversion for the injection channel (irrespective of if tailgating was used)" "0,1" newline bitfld.long 0x00 3. "DSI_COLLISION_INTR,DSI Collision Interrupt: hardware sets this interrupt when the DSI trigger signal is asserted while the SAR is BUSY" "0,1" newline bitfld.long 0x00 2. "FW_COLLISION_INTR,Firmware Collision Interrupt: hardware sets this interrupt when FW_TRIGGER is asserted while the SAR is BUSY" "0,1" newline bitfld.long 0x00 1. "OVERFLOW_INTR,Overflow Interrupt: hardware sets this interrupt when it sets a new EOS_INTR while that bit was not yet cleared by the firmware" "0,1" newline bitfld.long 0x00 0. "EOS_INTR,End Of Scan Interrupt: hardware sets this interrupt after completing a scan of all the enabled channels" "0,1" group.long 0x214++0x03 line.long 0x00 "INTR_SET,Interrupt set request register" bitfld.long 0x00 7. "INJ_COLLISION_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 6. "INJ_RANGE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 5. "INJ_SATURATE_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 4. "INJ_EOC_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 3. "DSI_COLLISION_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 2. "FW_COLLISION_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 1. "OVERFLOW_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 0. "EOS_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1" group.long 0x218++0x03 line.long 0x00 "INTR_MASK,Interrupt mask register" bitfld.long 0x00 7. "INJ_COLLISION_MASK,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 6. "INJ_RANGE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 5. "INJ_SATURATE_MASK,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 4. "INJ_EOC_MASK,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 3. "DSI_COLLISION_MASK,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 2. "FW_COLLISION_MASK,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 1. "OVERFLOW_MASK,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 0. "EOS_MASK,Mask bit for corresponding bit in interrupt request register" "0,1" rgroup.long 0x21C++0x03 line.long 0x00 "INTR_MASKED,Interrupt masked request register" bitfld.long 0x00 7. "INJ_COLLISION_MASKED,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 6. "INJ_RANGE_MASKED,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 5. "INJ_SATURATE_MASKED,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 4. "INJ_EOC_MASKED,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 3. "DSI_COLLISION_MASKED,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 2. "FW_COLLISION_MASKED,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 1. "OVERFLOW_MASKED,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 0. "EOS_MASKED,Logical and of corresponding request and mask bits" "0,1" group.long 0x220++0x03 line.long 0x00 "SATURATE_INTR,Saturate interrupt request register" hexmask.long.word 0x00 0.--15. 1. "SATURATE_INTR,Saturate Interrupt: hardware sets this interrupt for each channel if a conversion result (before averaging) of that channel is either 0x000 or 0xFFF (for 12-bit resolution) this is an indication that the ADC likely saturated" group.long 0x224++0x03 line.long 0x00 "SATURATE_INTR_SET,Saturate interrupt set request register" hexmask.long.word 0x00 0.--15. 1. "SATURATE_SET,Write with '1' to set corresponding bit in interrupt request register" group.long 0x228++0x03 line.long 0x00 "SATURATE_INTR_MASK,Saturate interrupt mask register" hexmask.long.word 0x00 0.--15. 1. "SATURATE_MASK,Mask bit for corresponding bit in interrupt request register" rgroup.long 0x22C++0x03 line.long 0x00 "SATURATE_INTR_MASKED,Saturate interrupt masked request register" hexmask.long.word 0x00 0.--15. 1. "SATURATE_MASKED,Logical and of corresponding request and mask bits" group.long 0x230++0x03 line.long 0x00 "RANGE_INTR,Range detect interrupt request register" hexmask.long.word 0x00 0.--15. 1. "RANGE_INTR,Range detect Interrupt: hardware sets this interrupt for each channel if the conversion result (after averaging) of that channel met the condition specified by the SAR_RANGE registers" group.long 0x234++0x03 line.long 0x00 "RANGE_INTR_SET,Range detect interrupt set request register" hexmask.long.word 0x00 0.--15. 1. "RANGE_SET,Write with '1' to set corresponding bit in interrupt request register" group.long 0x238++0x03 line.long 0x00 "RANGE_INTR_MASK,Range detect interrupt mask register" hexmask.long.word 0x00 0.--15. 1. "RANGE_MASK,Mask bit for corresponding bit in interrupt request register" rgroup.long 0x23C++0x03 line.long 0x00 "RANGE_INTR_MASKED,Range interrupt masked request register" hexmask.long.word 0x00 0.--15. 1. "RANGE_MASKED,Logical and of corresponding request and mask bits" rgroup.long 0x240++0x03 line.long 0x00 "INTR_CAUSE,Interrupt cause register" bitfld.long 0x00 31. "RANGE_MASKED_RED,Reduction OR of all SAR_RANGE_INTR_MASKED bits" "0,1" newline bitfld.long 0x00 30. "SATURATE_MASKED_RED,Reduction OR of all SAR_SATURATION_INTR_MASKED bits" "0,1" newline bitfld.long 0x00 7. "INJ_COLLISION_MASKED_MIR,Mirror copy of corresponding bit in SAR_INTR_MASKED" "0,1" newline bitfld.long 0x00 6. "INJ_RANGE_MASKED_MIR,Mirror copy of corresponding bit in SAR_INTR_MASKED" "0,1" newline bitfld.long 0x00 5. "INJ_SATURATE_MASKED_MIR,Mirror copy of corresponding bit in SAR_INTR_MASKED" "0,1" newline bitfld.long 0x00 4. "INJ_EOC_MASKED_MIR,Mirror copy of corresponding bit in SAR_INTR_MASKED" "0,1" newline bitfld.long 0x00 3. "DSI_COLLISION_MASKED_MIR,Mirror copy of corresponding bit in SAR_INTR_MASKED" "0,1" newline bitfld.long 0x00 2. "FW_COLLISION_MASKED_MIR,Mirror copy of corresponding bit in SAR_INTR_MASKED" "0,1" newline bitfld.long 0x00 1. "OVERFLOW_MASKED_MIR,Mirror copy of corresponding bit in SAR_INTR_MASKED" "0,1" newline bitfld.long 0x00 0. "EOS_MASKED_MIR,Mirror copy of corresponding bit in SAR_INTR_MASKED" "0,1" group.long 0x280++0x03 line.long 0x00 "INJ_CHAN_CONFIG,Injection channel configuration register" bitfld.long 0x00 31. "INJ_START_EN,Set by firmware to enable the injection channel" "0,1" newline bitfld.long 0x00 30. "INJ_TAILGATING,Injection channel tailgating" "0: no tailgating for this channel SAR is,1: injection channel tailgating" newline bitfld.long 0x00 12.--13. "INJ_SAMPLE_TIME_SEL,Injection sample time select: select which of the 4 global sample times to use for this channel" "0,1,2,3" newline bitfld.long 0x00 10. "INJ_AVG_EN,Averaging enable for this channel" "0,1" newline bitfld.long 0x00 9. "INJ_RESOLUTION,Resolution for this channel" "0: 12-bit resolution is used for this channel,1: The resolution specified by SUB_RESOLUTION in.." newline bitfld.long 0x00 8. "INJ_DIFFERENTIAL_EN,Differential enable for this channel" "0: The voltage on the addressed pin is measured,1: The differential voltage on the addressed pin" newline bitfld.long 0x00 4.--6. "INJ_PORT_ADDR,Address of the port that contains the pin to be sampled by this channel" "0: SARMUX pins,1: CTB0,2: CTB1,3: CTB2,4: CTB3,?,6: AROUTE virtual port,7: SARMUX virtual port" newline bitfld.long 0x00 0.--2. "INJ_PIN_ADDR,Address of the pin to be sampled by this injection channel" "0,1,2,3,4,5,6,7" rgroup.long 0x290++0x03 line.long 0x00 "INJ_RESULT,Injection channel result register" bitfld.long 0x00 31. "INJ_EOC_INTR_MIR,mirror bit of corresponding bit in SAR_INTR register" "0,1" newline bitfld.long 0x00 30. "INJ_RANGE_INTR_MIR,mirror bit of corresponding bit in SAR_INTR register" "0,1" newline bitfld.long 0x00 29. "INJ_SATURATE_INTR_MIR,mirror bit of corresponding bit in SAR_INTR register" "0,1" newline bitfld.long 0x00 28. "INJ_COLLISION_INTR_MIR,mirror bit of corresponding bit in SAR_INTR register" "0,1" newline hexmask.long.word 0x00 0.--15. 1. "INJ_RESULT,SAR conversion result of the channel" group.long 0x300++0x03 line.long 0x00 "MUX_SWITCH0,SARMUX Firmware switch controls" bitfld.long 0x00 29. "MUX_FW_P7_COREIO3,Firmware control" "0: open,1: close" newline bitfld.long 0x00 28. "MUX_FW_P6_COREIO2,Firmware control" "0: open,1: close" newline bitfld.long 0x00 27. "MUX_FW_P5_COREIO1,Firmware control" "0: open,1: close" newline bitfld.long 0x00 26. "MUX_FW_P4_COREIO0,Firmware control" "0: open,1: close" newline bitfld.long 0x00 25. "MUX_FW_SARBUS1_VMINUS,Firmware control" "0: open,1: close" newline bitfld.long 0x00 24. "MUX_FW_SARBUS0_VMINUS,Firmware control" "0: open,1: close" newline bitfld.long 0x00 23. "MUX_FW_SARBUS1_VPLUS,Firmware control" "0: open,1: close" newline bitfld.long 0x00 22. "MUX_FW_SARBUS0_VPLUS,Firmware control" "0: open,1: close" newline bitfld.long 0x00 21. "MUX_FW_AMUXBUSB_VMINUS,Firmware control" "0: open,1: close" newline bitfld.long 0x00 20. "MUX_FW_AMUXBUSA_VMINUS,Firmware control" "0: open,1: close" newline bitfld.long 0x00 19. "MUX_FW_AMUXBUSB_VPLUS,Firmware control" "0: open,1: close" newline bitfld.long 0x00 18. "MUX_FW_AMUXBUSA_VPLUS,Firmware control" "0: open,1: close" newline bitfld.long 0x00 17. "MUX_FW_TEMP_VPLUS,Firmware control" "0: open,1: close" newline bitfld.long 0x00 16. "MUX_FW_VSSA_VMINUS,Firmware control" "0: open,1: close" newline bitfld.long 0x00 15. "MUX_FW_P7_VMINUS,Firmware control" "0: open,1: close" newline bitfld.long 0x00 14. "MUX_FW_P6_VMINUS,Firmware control" "0: open,1: close" newline bitfld.long 0x00 13. "MUX_FW_P5_VMINUS,Firmware control" "0: open,1: close" newline bitfld.long 0x00 12. "MUX_FW_P4_VMINUS,Firmware control" "0: open,1: close" newline bitfld.long 0x00 11. "MUX_FW_P3_VMINUS,Firmware control" "0: open,1: close" newline bitfld.long 0x00 10. "MUX_FW_P2_VMINUS,Firmware control" "0: open,1: close" newline bitfld.long 0x00 9. "MUX_FW_P1_VMINUS,Firmware control" "0: open,1: close" newline bitfld.long 0x00 8. "MUX_FW_P0_VMINUS,Firmware control" "0: open,1: close" newline bitfld.long 0x00 7. "MUX_FW_P7_VPLUS,Firmware control" "0: open,1: close" newline bitfld.long 0x00 6. "MUX_FW_P6_VPLUS,Firmware control" "0: open,1: close" newline bitfld.long 0x00 5. "MUX_FW_P5_VPLUS,Firmware control" "0: open,1: close" newline bitfld.long 0x00 4. "MUX_FW_P4_VPLUS,Firmware control" "0: open,1: close" newline bitfld.long 0x00 3. "MUX_FW_P3_VPLUS,Firmware control" "0: open,1: close" newline bitfld.long 0x00 2. "MUX_FW_P2_VPLUS,Firmware control" "0: open,1: close" newline bitfld.long 0x00 1. "MUX_FW_P1_VPLUS,Firmware control" "0: open,1: close" newline bitfld.long 0x00 0. "MUX_FW_P0_VPLUS,Firmware control" "0: open,1: close" group.long 0x304++0x03 line.long 0x00 "MUX_SWITCH_CLEAR0,SARMUX Firmware switch control clear" bitfld.long 0x00 29. "MUX_FW_P7_COREIO3,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 28. "MUX_FW_P6_COREIO2,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 27. "MUX_FW_P5_COREIO1,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 26. "MUX_FW_P4_COREIO0,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 25. "MUX_FW_SARBUS1_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 24. "MUX_FW_SARBUS0_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 23. "MUX_FW_SARBUS1_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 22. "MUX_FW_SARBUS0_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 21. "MUX_FW_AMUXBUSB_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 20. "MUX_FW_AMUXBUSA_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 19. "MUX_FW_AMUXBUSB_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 18. "MUX_FW_AMUXBUSA_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 17. "MUX_FW_TEMP_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 16. "MUX_FW_VSSA_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 15. "MUX_FW_P7_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 14. "MUX_FW_P6_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 13. "MUX_FW_P5_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 12. "MUX_FW_P4_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 11. "MUX_FW_P3_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 10. "MUX_FW_P2_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 9. "MUX_FW_P1_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 8. "MUX_FW_P0_VMINUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 7. "MUX_FW_P7_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 6. "MUX_FW_P6_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 5. "MUX_FW_P5_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 4. "MUX_FW_P4_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 3. "MUX_FW_P3_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 2. "MUX_FW_P2_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 1. "MUX_FW_P1_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 0. "MUX_FW_P0_VPLUS,Write '1' to clear corresponding bit in MUX_SWITCH0" "0,1" group.long 0x308++0x03 line.long 0x00 "MUX_SWITCH1,SARMUX Firmware switch controls" bitfld.long 0x00 3. "MUX_FW_ADFT1_SARBUS1,Firmware control" "0: open,1: close" newline bitfld.long 0x00 2. "MUX_FW_ADFT0_SARBUS0,Firmware control" "0: open,1: close" newline bitfld.long 0x00 1. "MUX_FW_P5_DFT_INM,Firmware control" "0: open,1: close" newline bitfld.long 0x00 0. "MUX_FW_P4_DFT_INP,Firmware control" "0: open,1: close" group.long 0x30C++0x03 line.long 0x00 "MUX_SWITCH_CLEAR1,SARMUX Firmware switch control clear" bitfld.long 0x00 3. "MUX_FW_ADFT1_SARBUS1,Write '1' to clear corresponding bit in MUX_SWITCH1" "0,1" newline bitfld.long 0x00 2. "MUX_FW_ADFT0_SARBUS0,Write '1' to clear corresponding bit in MUX_SWITCH1" "0,1" newline bitfld.long 0x00 1. "MUX_FW_P5_DFT_INM,Write '1' to clear corresponding bit in MUX_SWITCH1" "0,1" newline bitfld.long 0x00 0. "MUX_FW_P4_DFT_INP,Write '1' to clear corresponding bit in MUX_SWITCH1" "0,1" group.long 0x340++0x03 line.long 0x00 "MUX_SWITCH_HW_CTRL,SARMUX switch hardware control" bitfld.long 0x00 23. "MUX_HW_CTRL_SARBUS1,Hardware control" "0: only firmware control,1: hardware control masked by firmware setting for" newline bitfld.long 0x00 22. "MUX_HW_CTRL_SARBUS0,Hardware control" "0: only firmware control,1: hardware control masked by firmware setting for" newline bitfld.long 0x00 19. "MUX_HW_CTRL_AMUXBUSB,Hardware control" "0: only firmware control,1: hardware control masked by firmware setting for" newline bitfld.long 0x00 18. "MUX_HW_CTRL_AMUXBUSA,Hardware control" "0: only firmware control,1: hardware control masked by firmware setting for" newline bitfld.long 0x00 17. "MUX_HW_CTRL_TEMP,Hardware control" "0: only firmware control,1: hardware control masked by firmware setting for" newline bitfld.long 0x00 16. "MUX_HW_CTRL_VSSA,Hardware control" "0: only firmware control,1: hardware control masked by firmware setting for" newline bitfld.long 0x00 7. "MUX_HW_CTRL_P7,Hardware control" "0: only firmware control,1: hardware control masked by firmware setting for" newline bitfld.long 0x00 6. "MUX_HW_CTRL_P6,Hardware control" "0: only firmware control,1: hardware control masked by firmware setting for" newline bitfld.long 0x00 5. "MUX_HW_CTRL_P5,Hardware control" "0: only firmware control,1: hardware control masked by firmware setting for" newline bitfld.long 0x00 4. "MUX_HW_CTRL_P4,Hardware control" "0: only firmware control,1: hardware control masked by firmware setting for" newline bitfld.long 0x00 3. "MUX_HW_CTRL_P3,Hardware control" "0: only firmware control,1: hardware control masked by firmware setting for" newline bitfld.long 0x00 2. "MUX_HW_CTRL_P2,Hardware control" "0: only firmware control,1: hardware control masked by firmware setting for" newline bitfld.long 0x00 1. "MUX_HW_CTRL_P1,Hardware control" "0: only firmware control,1: hardware control masked by firmware setting for" newline bitfld.long 0x00 0. "MUX_HW_CTRL_P0,Hardware control" "0: only firmware control,1: hardware control masked by firmware setting for" rgroup.long 0x348++0x03 line.long 0x00 "MUX_SWITCH_STATUS,SARMUX switch status" bitfld.long 0x00 25. "MUX_FW_SARBUS1_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 24. "MUX_FW_SARBUS0_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 23. "MUX_FW_SARBUS1_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 22. "MUX_FW_SARBUS0_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 21. "MUX_FW_AMUXBUSB_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 20. "MUX_FW_AMUXBUSA_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 19. "MUX_FW_AMUXBUSB_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 18. "MUX_FW_AMUXBUSA_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 17. "MUX_FW_TEMP_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 16. "MUX_FW_VSSA_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 15. "MUX_FW_P7_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 14. "MUX_FW_P6_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 13. "MUX_FW_P5_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 12. "MUX_FW_P4_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 11. "MUX_FW_P3_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 10. "MUX_FW_P2_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 9. "MUX_FW_P1_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 8. "MUX_FW_P0_VMINUS,switch status of corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 7. "MUX_FW_P7_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 6. "MUX_FW_P6_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 5. "MUX_FW_P5_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 4. "MUX_FW_P4_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 3. "MUX_FW_P3_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 2. "MUX_FW_P2_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 1. "MUX_FW_P1_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1" newline bitfld.long 0x00 0. "MUX_FW_P0_VPLUS,switch status of corresponding bit in MUX_SWITCH0" "0,1" group.long 0x380++0x03 line.long 0x00 "PUMP_CTRL,Switch pump control" bitfld.long 0x00 31. "ENABLED," "0,1" newline bitfld.long 0x00 0. "CLOCK_SEL,Clock select" "0: external clock,1: internal clock (deprecated)" group.long 0xF00++0x03 line.long 0x00 "ANA_TRIM,Analog trim register" bitfld.long 0x00 3. "TRIMUNIT,Attenuation cap trimming" "0,1" newline bitfld.long 0x00 0.--2. "CAP_TRIM,Attenuation cap trimming" "0,1,2,3,4,5,6,7" group.long 0xF04++0x03 line.long 0x00 "WOUNDING,SAR wounding register" bitfld.long 0x00 0.--1. "WOUND_RESOLUTION,Maximum SAR resolution allowed" "0: unwounded,1: wounded,2: wounded,3: wounded" tree.end endif tree "SCB (Serial Communications Block (SPI/UART/I2C))" sif cpuis("PMG1-S0")||cpuis("PMG1-S1")||cpuis("PMG1-S2")||cpuis("PMG1-S3") repeat 2. (list 0. 1.) (list ad:0x40050000 ad:0x40060000) (list ad:0x40220000 ad:0x40230000) tree "SCB$1" sif cpuis("PMG1-S0")||cpuis("PMG1-S1")||cpuis("PMG1-S2") base $2 group.long 0x00++0x03 line.long 0x00 "CTRL,Generic control register" bitfld.long 0x00 31. "ENABLED,IP enabled ('1') or not ('0')" "0,1" newline bitfld.long 0x00 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode,1: Serial Peripheral Interface (SPI) mode,2: Universal Asynchronous Receiver/Transmitter..,?..." newline bitfld.long 0x00 17. "BLOCK,Only used in externally clocked mode" "0,1" newline bitfld.long 0x00 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0')" "0,1" newline bitfld.long 0x00 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation: '0': CMD_RESP mode disabled" "0,1" newline bitfld.long 0x00 11. "BYTE_MODE,Determines the number of bits per FIFO data element: '0': 16-bit FIFO data elements" "0,1" newline bitfld.long 0x00 10. "EZ_MODE,Non EZ mode ('0') or EZ mode ('1')" "0,1" newline bitfld.long 0x00 9. "EC_OP_MODE,Internally clocked mode ('0') or externally clocked mode ('1') operation" "0,1" newline bitfld.long 0x00 8. "EC_AM_MODE,Internally clocked mode ('0') or externally clocked mode ('1') address matching (I2C) or selection (SPI)" "0,1" newline bitfld.long 0x00 0.--3. "OVS,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x04++0x03 line.long 0x00 "STATUS,Generic status register" bitfld.long 0x00 0. "EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode)" "0,1" group.long 0x08++0x03 line.long 0x00 "CMD_RESP_CTRL,Command/response control register" hexmask.long.word 0x00 16.--24. 1. "BASE_WR_ADDR,I2C/SPI read base address for CMD_RESP mode" newline hexmask.long.word 0x00 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode" rgroup.long 0x0C++0x03 line.long 0x00 "CMD_RESP_STATUS,Command/response status register" bitfld.long 0x00 31. "CMD_RESP_EC_BUSY,Indicates whether the CURR_RD_ADDR and CURR_WR_ADDR fields in this register are reliable (when CMD_RESP_EC_BUSY is '0') or not reliable (when CMD_RESP_EC_BUSY is '1')" "0,1" newline bitfld.long 0x00 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the IP" "0,1" newline hexmask.long.word 0x00 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode" newline hexmask.long.word 0x00 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode" group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI control register" bitfld.long 0x00 31. "MASTER_MODE,Master ('1') or slave ('0') mode" "0,1" newline bitfld.long 0x00 26.--27. "SLAVE_SELECT,Selects one of the four outgoing SPI slave select signals" "0: Slave 0 SPI_SELECT[0],1: Slave 1 SPI_SELECT[1],2: Slave 2 SPI_SELECT[2],3: Slave 3 SPI_SELECT[3]" newline bitfld.long 0x00 24.--25. "MODE,N/A" "0: SPI Motorola submode,1: SPI Texas Instruments submode,2: SPI National Semiconducturs submode,?..." newline bitfld.long 0x00 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)" "0,1" newline bitfld.long 0x00 11. "SSEL_POLARITY3,Slave select polarity" "0,1" newline bitfld.long 0x00 10. "SSEL_POLARITY2,Slave select polarity" "0,1" newline bitfld.long 0x00 9. "SSEL_POLARITY1,Slave select polarity" "0,1" newline bitfld.long 0x00 8. "SSEL_POLARITY0,Slave select polarity" "0,1" newline bitfld.long 0x00 5. "SCLK_CONTINUOUS,Only applicable in master mode" "0,1" newline bitfld.long 0x00 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured" "0,1" newline bitfld.long 0x00 3. "CPOL,Indicates the clock polarity" "0,1" newline bitfld.long 0x00 2. "CPHA,Only applicable in SPI Motorola submode" "0,1" newline bitfld.long 0x00 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode" "0,1" newline bitfld.long 0x00 0. "CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0')" "0,1" rgroup.long 0x24++0x03 line.long 0x00 "SPI_STATUS,SPI status register" hexmask.long.byte 0x00 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address" newline hexmask.long.byte 0x00 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address" newline bitfld.long 0x00 1. "SPI_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode)" "0,1" newline bitfld.long 0x00 0. "BUS_BUSY,SPI bus is busy" "0,1" group.long 0x40++0x03 line.long 0x00 "UART_CTRL,UART control register" bitfld.long 0x00 24.--25. "MODE,N/A" "0: Standard UART submode,1: SmartCard (ISO7816) submode,2: Infrared Data Association (IrDA) submode,?..." newline bitfld.long 0x00 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)" "0,1" group.long 0x44++0x03 line.long 0x00 "UART_TX_CTRL,UART transmitter control register" bitfld.long 0x00 8. "RETRY_ON_NACK,When '1' a data frame is retransmitted when a negative acknowledgement is received" "0,1" newline bitfld.long 0x00 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0')" "0,1" newline bitfld.long 0x00 4. "PARITY,Parity bit" "0,1" newline bitfld.long 0x00 0.--2. "STOP_BITS,Stop bits" "0,1,2,3,4,5,6,7" group.long 0x48++0x03 line.long 0x00 "UART_RX_CTRL,UART receiver control register" bitfld.long 0x00 16.--19. "BREAK_WIDTH,Break width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 13. "SKIP_START,Only applicable in standard UART submode" "0,1" newline bitfld.long 0x00 12. "LIN_MODE,Only applicable in standard UART submode" "0,1" newline bitfld.long 0x00 10. "MP_MODE,Multi-processor mode" "0,1" newline bitfld.long 0x00 9. "DROP_ON_FRAME_ERROR,Behaviour when an error is detected in a start or stop period" "0,1" newline bitfld.long 0x00 8. "DROP_ON_PARITY_ERROR,Behaviour when a parity check fails" "0,1" newline bitfld.long 0x00 6. "POLARITY,Inverts incoming RX line signal 'uart_rx_in'" "0,1" newline bitfld.long 0x00 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0')" "0,1" newline bitfld.long 0x00 4. "PARITY,Parity bit" "0,1" newline bitfld.long 0x00 0.--2. "STOP_BITS,Stop bits" "0,1,2,3,4,5,6,7" rgroup.long 0x4C++0x03 line.long 0x00 "UART_RX_STATUS,UART receiver status register" hexmask.long.word 0x00 0.--11. 1. "BR_COUNTER,Amount of peripheral clock periods that constitute the transmission of a 0x55 data frame (sent least signficant bit first) as determined by the receiver" group.long 0x50++0x03 line.long 0x00 "UART_FLOW_CTRL,UART flow control register" bitfld.long 0x00 25. "CTS_ENABLED,Enable use of CTS input signal 'uart_cts_in' by the UART transmitter: '0': Disabled" "0,1" newline bitfld.long 0x00 24. "CTS_POLARITY,Polarity of the CTS input signal 'uart_cts_in': '0': CTS is low/'0' active 'uart_cts_in' is '0' when active and 'uart_cts_in' is '1' when inactive" "0,1" newline bitfld.long 0x00 16. "RTS_POLARITY,Polarity of the RTS output signal 'uart_rts_out': '0': RTS is low/'0' active 'uart_rts_out' is '0' when active and 'uart_rts_out' is '1' when inactive" "0,1" newline hexmask.long.byte 0x00 0.--7. 1. "TRIGGER_LEVEL,Trigger level" group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C control register" bitfld.long 0x00 31. "MASTER_MODE,Master mode enabled ('1') or not ('0')" "0,1" newline bitfld.long 0x00 30. "SLAVE_MODE,Slave mode enabled ('1') or not ('0')" "0,1" newline bitfld.long 0x00 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)" "0,1" newline bitfld.long 0x00 15. "S_NOT_READY_DATA_NACK,For internally clocked logic only" "0: clock stretching is performed (till the..,1: a received data element byte the slave is" newline bitfld.long 0x00 14. "S_NOT_READY_ADDR_NACK,For internally clocked logic (EC_AM is '0' and EC_OP is '0') on an address match or general call address (and S_GENERAL_IGNORE is '0')" "0: clock stretching is performed (till the,1: a received (matching or general) slave address" newline bitfld.long 0x00 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the receiver FIFO is not full" "0,1" newline bitfld.long 0x00 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full" "0,1" newline bitfld.long 0x00 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address" "0,1" newline bitfld.long 0x00 9. "M_NOT_READY_DATA_NACK,When '1' a received data element byte the master is immediately NACK'd when the receiver FIFO is full" "0,1" newline bitfld.long 0x00 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the receiver FIFO is not full" "0,1" newline bitfld.long 0x00 4.--7. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x64++0x03 line.long 0x00 "I2C_STATUS,I2C status register" hexmask.long.byte 0x00 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address" newline hexmask.long.byte 0x00 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address" newline bitfld.long 0x00 5. "M_READ,I2C master read transfer ('1') or I2C master write transfer ('0')" "0,1" newline bitfld.long 0x00 4. "S_READ,I2C slave read transfer ('1') or I2C slave write transfer ('0')" "0,1" newline bitfld.long 0x00 1. "I2C_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ mode)" "0,1" newline bitfld.long 0x00 0. "BUS_BUSY,I2C bus is busy" "0,1" group.long 0x68++0x03 line.long 0x00 "I2C_M_CMD,I2C master command register" bitfld.long 0x00 4. "M_STOP,When '1' attempt to transmit a STOP" "0,1" newline bitfld.long 0x00 3. "M_NACK,When '1' attempt to transmit a negative acknowledgement (NACK)" "0,1" newline bitfld.long 0x00 2. "M_ACK,When '1' attempt to transmit an acknowledgement (ACK)" "0,1" newline bitfld.long 0x00 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0')" "0,1" newline bitfld.long 0x00 0. "M_START,When '1' transmit a START or REPEATED START" "0,1" group.long 0x6C++0x03 line.long 0x00 "I2C_S_CMD,I2C slave command register" bitfld.long 0x00 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK)" "0,1" newline bitfld.long 0x00 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK)" "0,1" group.long 0x70++0x03 line.long 0x00 "I2C_CFG,I2C configuration register" bitfld.long 0x00 28.--29. "SDA_OUT_FILT_SEL,Selection of cumulative 'i2c_sda_out' filter delay: '0': 0 ns" "0,1,2,3" newline bitfld.long 0x00 20.--21. "SDA_OUT_FILT2_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 2" "0,1,2,3" newline bitfld.long 0x00 18.--19. "SDA_OUT_FILT1_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 1" "0,1,2,3" newline bitfld.long 0x00 16.--17. "SDA_OUT_FILT0_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 0" "0,1,2,3" newline bitfld.long 0x00 12. "SCL_IN_FILT_SEL,Selection of 'i2c_scl_in' filter delay: '0': 0 ns" "0,1" newline bitfld.long 0x00 8.--9. "SCL_IN_FILT_TRIM,Trim bits for 'i2c_scl_in' 50 ns filter" "0,1,2,3" newline bitfld.long 0x00 4. "SDA_IN_FILT_SEL,Selection of 'i2c_sda_in' filter delay: '0': 0 ns" "0,1" newline bitfld.long 0x00 0.--1. "SDA_IN_FILT_TRIM,Trim bits for 'i2c_sda_in' 50 ns filter" "0,1,2,3" group.long 0x200++0x03 line.long 0x00 "TX_CTRL,Transmitter control register" bitfld.long 0x00 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1')" "0,1" newline bitfld.long 0x00 0.--3. "DATA_WIDTH,Dataframe width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x204++0x03 line.long 0x00 "TX_FIFO_CTRL,Transmitter FIFO control register" bitfld.long 0x00 17. "FREEZE,When '1' hardware reads from the transmitter FIFO do not remove FIFO entries" "0,1" newline bitfld.long 0x00 16. "CLEAR,When '1' the transmitter FIFO and transmitter shift register are cleared/invalidated" "0,1" newline hexmask.long.byte 0x00 0.--7. 1. "TRIGGER_LEVEL,Trigger level" rgroup.long 0x208++0x03 line.long 0x00 "TX_FIFO_STATUS,Transmitter FIFO status register" hexmask.long.byte 0x00 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written" newline hexmask.long.byte 0x00 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read by the hardware" newline bitfld.long 0x00 15. "SR_VALID,Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0')" "0,1" newline hexmask.long.word 0x00 0.--8. 1. "USED,Amount of entries in the transmitter FIFO" wgroup.long 0x240++0x03 line.long 0x00 "TX_FIFO_WR,Transmitter FIFO write register" hexmask.long.word 0x00 0.--15. 1. "DATA,Data frame written into the transmitter FIFO" group.long 0x300++0x03 line.long 0x00 "RX_CTRL,Receiver control register" bitfld.long 0x00 9. "MEDIAN,Median filter" "0,1" newline bitfld.long 0x00 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1')" "0,1" newline bitfld.long 0x00 0.--3. "DATA_WIDTH,Dataframe width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x304++0x03 line.long 0x00 "RX_FIFO_CTRL,Receiver FIFO control register" bitfld.long 0x00 17. "FREEZE,When '1' hardware writes to the receiver FIFO have no effect" "0,1" newline bitfld.long 0x00 16. "CLEAR,When '1' the receiver FIFO and receiver shift register are cleared/invalidated" "0,1" newline hexmask.long.byte 0x00 0.--7. 1. "TRIGGER_LEVEL,Trigger level" rgroup.long 0x308++0x03 line.long 0x00 "RX_FIFO_STATUS,Receiver FIFO status register" hexmask.long.byte 0x00 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written by the hardware" newline hexmask.long.byte 0x00 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is" newline bitfld.long 0x00 15. "SR_VALID,Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0')" "0,1" newline hexmask.long.word 0x00 0.--8. 1. "USED,Amount of entries in the receiver FIFO" group.long 0x310++0x03 line.long 0x00 "RX_MATCH,Slave address and mask register" hexmask.long.byte 0x00 16.--23. 1. "MASK,Slave device address mask" newline hexmask.long.byte 0x00 0.--7. 1. "ADDR,Slave device address" rgroup.long 0x340++0x03 line.long 0x00 "RX_FIFO_RD,Receiver FIFO read register" hexmask.long.word 0x00 0.--15. 1. "DATA,Data read from the receiver FIFO" rgroup.long 0x344++0x03 line.long 0x00 "RX_FIFO_RD_SILENT,Receiver FIFO read register" hexmask.long.word 0x00 0.--15. 1. "DATA,Data read from the receiver FIFO" rgroup.long 0xE00++0x03 line.long 0x00 "INTR_CAUSE,Active clocked interrupt signal register" bitfld.long 0x00 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0" "0,1" newline bitfld.long 0x00 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0" "0,1" newline bitfld.long 0x00 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0" "0,1" newline bitfld.long 0x00 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0" "0,1" newline bitfld.long 0x00 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0" "0,1" newline bitfld.long 0x00 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0" "0,1" group.long 0xE80++0x03 line.long 0x00 "INTR_I2C_EC,Externally clocked I2C interrupt request register" bitfld.long 0x00 3. "EZ_READ_STOP,STOP detection after a read transfer occurred" "0,1" newline bitfld.long 0x00 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred" "0,1" newline bitfld.long 0x00 1. "EZ_STOP,STOP detection" "0,1" newline bitfld.long 0x00 0. "WAKE_UP,Wake up request" "0,1" group.long 0xE88++0x03 line.long 0x00 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask register" bitfld.long 0x00 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register" "0,1" rgroup.long 0xE8C++0x03 line.long 0x00 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked register" bitfld.long 0x00 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 1. "EZ_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 0. "WAKE_UP,Logical and of corresponding request and mask bits" "0,1" group.long 0xEC0++0x03 line.long 0x00 "INTR_SPI_EC,Externally clocked SPI interrupt request register" bitfld.long 0x00 3. "EZ_READ_STOP,STOP detection after a read transfer occurred" "0,1" newline bitfld.long 0x00 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred" "0,1" newline bitfld.long 0x00 1. "EZ_STOP,STOP detection" "0,1" newline bitfld.long 0x00 0. "WAKE_UP,Wake up request" "0,1" group.long 0xEC8++0x03 line.long 0x00 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask register" bitfld.long 0x00 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register" "0,1" rgroup.long 0xECC++0x03 line.long 0x00 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked register" bitfld.long 0x00 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 1. "EZ_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 0. "WAKE_UP,Logical and of corresponding request and mask bits" "0,1" group.long 0xF00++0x03 line.long 0x00 "INTR_M,Master interrupt request register" bitfld.long 0x00 9. "SPI_DONE,SPI master transfer done event: all data frames in the transmit FIFO are sent and the transmit FIFO and shift register are empty" "0,1" newline bitfld.long 0x00 8. "I2C_BUS_ERROR,I2C master bus error (unexpected detection of START or STOP condition)" "0,1" newline bitfld.long 0x00 4. "I2C_STOP,I2C master STOP" "0,1" newline bitfld.long 0x00 2. "I2C_ACK,I2C master acknowledgement" "0,1" newline bitfld.long 0x00 1. "I2C_NACK,I2C master negative acknowledgement" "0,1" newline bitfld.long 0x00 0. "I2C_ARB_LOST,I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line" "0,1" group.long 0xF04++0x03 line.long 0x00 "INTR_M_SET,Master interrupt set request register" bitfld.long 0x00 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register" "0,1" group.long 0xF08++0x03 line.long 0x00 "INTR_M_MASK,Master interrupt mask register" bitfld.long 0x00 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register" "0,1" rgroup.long 0xF0C++0x03 line.long 0x00 "INTR_M_MASKED,Master interrupt masked request register" bitfld.long 0x00 9. "SPI_DONE,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 4. "I2C_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 2. "I2C_ACK,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 1. "I2C_NACK,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits" "0,1" group.long 0xF40++0x03 line.long 0x00 "INTR_S,Slave interrupt request register" bitfld.long 0x00 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer" "0,1" newline bitfld.long 0x00 10. "SPI_EZ_STOP,SPI slave deselected after any EZ SPI transfer occurred" "0,1" newline bitfld.long 0x00 9. "SPI_EZ_WRITE_STOP,SPI slave deselected after a write EZ SPI transfer occurred" "0,1" newline bitfld.long 0x00 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition)" "0,1" newline bitfld.long 0x00 7. "I2C_GENERAL,I2C slave general call address received" "0,1" newline bitfld.long 0x00 6. "I2C_ADDR_MATCH,I2C slave matching address received" "0,1" newline bitfld.long 0x00 5. "I2C_START,I2C slave START received" "0,1" newline bitfld.long 0x00 4. "I2C_STOP,I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed)" "0,1" newline bitfld.long 0x00 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed)" "0,1" newline bitfld.long 0x00 2. "I2C_ACK,I2C slave acknowledgement received" "0,1" newline bitfld.long 0x00 1. "I2C_NACK,I2C slave negative acknowledgement received" "0,1" newline bitfld.long 0x00 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1')" "0,1" group.long 0xF44++0x03 line.long 0x00 "INTR_S_SET,Slave interrupt set request register" bitfld.long 0x00 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register" "0,1" group.long 0xF48++0x03 line.long 0x00 "INTR_S_MASK,Slave interrupt mask register" bitfld.long 0x00 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 5. "I2C_START,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register" "0,1" rgroup.long 0xF4C++0x03 line.long 0x00 "INTR_S_MASKED,Slave interrupt masked request register" bitfld.long 0x00 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 7. "I2C_GENERAL,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 5. "I2C_START,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 4. "I2C_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 2. "I2C_ACK,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 1. "I2C_NACK,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits" "0,1" group.long 0xF80++0x03 line.long 0x00 "INTR_TX,Transmitter interrupt request register" bitfld.long 0x00 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line" "0,1" newline bitfld.long 0x00 9. "UART_DONE,UART transmitter done event" "0,1" newline bitfld.long 0x00 8. "UART_NACK,UART transmitter received a negative acknowledgement in SmartCard mode" "0,1" newline bitfld.long 0x00 7. "BLOCKED,AHB-Lite write transfer can not get access to the EZ memory (EZ data access) due to an externally clocked EZ access" "0,1" newline bitfld.long 0x00 6. "UNDERFLOW,Attempt to read from an empty TX FIFO" "0,1" newline bitfld.long 0x00 5. "OVERFLOW,Attempt to write to a full TX FIFO" "0,1" newline bitfld.long 0x00 4. "EMPTY,TX FIFO is empty i.e" "0,1" newline bitfld.long 0x00 1. "NOT_FULL,TX FIFO is not full" "0,1" newline bitfld.long 0x00 0. "TRIGGER,Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL" "0,1" group.long 0xF84++0x03 line.long 0x00 "INTR_TX_SET,Transmitter interrupt set request register" bitfld.long 0x00 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register" "0,1" group.long 0xF88++0x03 line.long 0x00 "INTR_TX_MASK,Transmitter interrupt mask register" bitfld.long 0x00 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 4. "EMPTY,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register" "0,1" rgroup.long 0xF8C++0x03 line.long 0x00 "INTR_TX_MASKED,Transmitter interrupt masked request register" bitfld.long 0x00 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 9. "UART_DONE,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 8. "UART_NACK,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 7. "BLOCKED,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 6. "UNDERFLOW,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 5. "OVERFLOW,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 4. "EMPTY,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 1. "NOT_FULL,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 0. "TRIGGER,Logical and of corresponding request and mask bits" "0,1" group.long 0xFC0++0x03 line.long 0x00 "INTR_RX,Receiver interrupt request register" bitfld.long 0x00 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period" "0,1" newline bitfld.long 0x00 10. "BAUD_DETECT,LIN baudrate detection is completed" "0,1" newline bitfld.long 0x00 9. "PARITY_ERROR,Parity error in received data frame" "0,1" newline bitfld.long 0x00 8. "FRAME_ERROR,Frame error in received data frame" "0,1" newline bitfld.long 0x00 7. "BLOCKED,AHB-Lite read transfer can not get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access" "0,1" newline bitfld.long 0x00 6. "UNDERFLOW,Attempt to read from an empty RX FIFO" "0,1" newline bitfld.long 0x00 5. "OVERFLOW,Attempt to write to a full RX FIFO" "0,1" newline bitfld.long 0x00 3. "FULL,RX FIFO is full" "0,1" newline bitfld.long 0x00 2. "NOT_EMPTY,RX FIFO is not empty" "0,1" newline bitfld.long 0x00 0. "TRIGGER,More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in SCB_RX_FIFO_CTL" "0,1" group.long 0xFC4++0x03 line.long 0x00 "INTR_RX_SET,Receiver interrupt set request register" bitfld.long 0x00 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register" "0,1" newline bitfld.long 0x00 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register" "0,1" newline bitfld.long 0x00 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register" "0,1" newline bitfld.long 0x00 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register" "0,1" newline bitfld.long 0x00 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register" "0,1" newline bitfld.long 0x00 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register" "0,1" newline bitfld.long 0x00 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register" "0,1" newline bitfld.long 0x00 3. "FULL,Write with '1' to set corresponding bit in interrupt status register" "0,1" newline bitfld.long 0x00 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register" "0,1" newline bitfld.long 0x00 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register" "0,1" group.long 0xFC8++0x03 line.long 0x00 "INTR_RX_MASK,Receiver interrupt mask register" bitfld.long 0x00 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 3. "FULL,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register" "0,1" rgroup.long 0xFCC++0x03 line.long 0x00 "INTR_RX_MASKED,Receiver interrupt masked request register" bitfld.long 0x00 11. "BREAK_DETECT,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 10. "BAUD_DETECT,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 9. "PARITY_ERROR,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 8. "FRAME_ERROR,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 7. "BLOCKED,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 6. "UNDERFLOW,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 5. "OVERFLOW,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 3. "FULL,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 2. "NOT_EMPTY,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 0. "TRIGGER,Logical and of corresponding request and mask bits" "0,1" elif cpuis("PMG1-S3") base $3 group.long 0x00++0x03 line.long 0x00 "CTRL,Generic control register" bitfld.long 0x00 31. "ENABLED,IP enabled ('1') or not ('0')" "0,1" newline bitfld.long 0x00 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode,1: Serial Peripheral Interface (SPI) mode,2: Universal Asynchronous Receiver/Transmitter..,?..." newline bitfld.long 0x00 17. "BLOCK,Only used in externally clocked mode" "0,1" newline bitfld.long 0x00 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0')" "0,1" newline bitfld.long 0x00 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation: '0': CMD_RESP mode disabled" "0,1" newline bitfld.long 0x00 11. "BYTE_MODE,Determines the number of bits per FIFO data element: '0': 16-bit FIFO data elements" "0,1" newline bitfld.long 0x00 10. "EZ_MODE,Non EZ mode ('0') or EZ mode ('1')" "0,1" newline bitfld.long 0x00 9. "EC_OP_MODE,Internally clocked mode ('0') or externally clocked mode ('1') operation" "0,1" newline bitfld.long 0x00 8. "EC_AM_MODE,Internally clocked mode ('0') or externally clocked mode ('1') address matching (I2C) or selection (SPI)" "0,1" newline bitfld.long 0x00 0.--3. "OVS,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x04++0x03 line.long 0x00 "STATUS,Generic status register" bitfld.long 0x00 0. "EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode)" "0,1" group.long 0x08++0x03 line.long 0x00 "CMD_RESP_CTRL,Command/response control register" hexmask.long.word 0x00 16.--24. 1. "BASE_WR_ADDR,I2C/SPI read base address for CMD_RESP mode" newline hexmask.long.word 0x00 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode" rgroup.long 0x0C++0x03 line.long 0x00 "CMD_RESP_STATUS,Command/response status register" bitfld.long 0x00 31. "CMD_RESP_EC_BUSY,Indicates whether the CURR_RD_ADDR and CURR_WR_ADDR fields in this register are reliable (when CMD_RESP_EC_BUSY is '0') or not reliable (when CMD_RESP_EC_BUSY is '1')" "0,1" newline bitfld.long 0x00 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the IP" "0,1" newline hexmask.long.word 0x00 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode" newline hexmask.long.word 0x00 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode" group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI control register" bitfld.long 0x00 31. "MASTER_MODE,Master ('1') or slave ('0') mode" "0,1" newline bitfld.long 0x00 26.--27. "SLAVE_SELECT,Selects one of the four outgoing SPI slave select signals" "0: Slave 0 SPI_SELECT[0],1: Slave 1 SPI_SELECT[1],2: Slave 2 SPI_SELECT[2],3: Slave 3 SPI_SELECT[3]" newline bitfld.long 0x00 24.--25. "MODE,N/A" "0: SPI Motorola submode,1: SPI Texas Instruments submode,2: SPI National Semiconducturs submode,?..." newline bitfld.long 0x00 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)" "0,1" newline bitfld.long 0x00 11. "SSEL_POLARITY3,Slave select polarity" "0,1" newline bitfld.long 0x00 10. "SSEL_POLARITY2,Slave select polarity" "0,1" newline bitfld.long 0x00 9. "SSEL_POLARITY1,Slave select polarity" "0,1" newline bitfld.long 0x00 8. "SSEL_POLARITY0,Slave select polarity" "0,1" newline bitfld.long 0x00 5. "SCLK_CONTINUOUS,Only applicable in master mode" "0,1" newline bitfld.long 0x00 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured" "0,1" newline bitfld.long 0x00 3. "CPOL,Indicates the clock polarity" "0,1" newline bitfld.long 0x00 2. "CPHA,Only applicable in SPI Motorola submode" "0,1" newline bitfld.long 0x00 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode" "0,1" newline bitfld.long 0x00 0. "CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0')" "0,1" rgroup.long 0x24++0x03 line.long 0x00 "SPI_STATUS,SPI status register" hexmask.long.byte 0x00 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address" newline hexmask.long.byte 0x00 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address" newline bitfld.long 0x00 1. "SPI_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode)" "0,1" newline bitfld.long 0x00 0. "BUS_BUSY,SPI bus is busy" "0,1" group.long 0x40++0x03 line.long 0x00 "UART_CTRL,UART control register" bitfld.long 0x00 24.--25. "MODE,N/A" "0: Standard UART submode,1: SmartCard (ISO7816) submode,2: Infrared Data Association (IrDA) submode,?..." newline bitfld.long 0x00 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)" "0,1" group.long 0x44++0x03 line.long 0x00 "UART_TX_CTRL,UART transmitter control register" bitfld.long 0x00 8. "RETRY_ON_NACK,When '1' a data frame is retransmitted when a negative acknowledgement is received" "0,1" newline bitfld.long 0x00 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0')" "0,1" newline bitfld.long 0x00 4. "PARITY,Parity bit" "0,1" newline bitfld.long 0x00 0.--2. "STOP_BITS,Stop bits" "0,1,2,3,4,5,6,7" group.long 0x48++0x03 line.long 0x00 "UART_RX_CTRL,UART receiver control register" bitfld.long 0x00 16.--19. "BREAK_WIDTH,Break width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 13. "SKIP_START,Only applicable in standard UART submode" "0,1" newline bitfld.long 0x00 12. "LIN_MODE,Only applicable in standard UART submode" "0,1" newline bitfld.long 0x00 10. "MP_MODE,Multi-processor mode" "0,1" newline bitfld.long 0x00 9. "DROP_ON_FRAME_ERROR,Behaviour when an error is detected in a start or stop period" "0,1" newline bitfld.long 0x00 8. "DROP_ON_PARITY_ERROR,Behaviour when a parity check fails" "0,1" newline bitfld.long 0x00 6. "POLARITY,Inverts incoming RX line signal 'uart_rx_in'" "0,1" newline bitfld.long 0x00 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0')" "0,1" newline bitfld.long 0x00 4. "PARITY,Parity bit" "0,1" newline bitfld.long 0x00 0.--2. "STOP_BITS,Stop bits" "0,1,2,3,4,5,6,7" rgroup.long 0x4C++0x03 line.long 0x00 "UART_RX_STATUS,UART receiver status register" hexmask.long.word 0x00 0.--11. 1. "BR_COUNTER,Amount of peripheral clock periods that constitute the transmission of a 0x55 data frame (sent least signficant bit first) as determined by the receiver" group.long 0x50++0x03 line.long 0x00 "UART_FLOW_CTRL,UART flow control register" bitfld.long 0x00 25. "CTS_ENABLED,Enable use of CTS input signal 'uart_cts_in' by the UART transmitter: '0': Disabled" "0,1" newline bitfld.long 0x00 24. "CTS_POLARITY,Polarity of the CTS input signal 'uart_cts_in': '0': CTS is low/'0' active 'uart_cts_in' is '0' when active and 'uart_cts_in' is '1' when inactive" "0,1" newline bitfld.long 0x00 16. "RTS_POLARITY,Polarity of the RTS output signal 'uart_rts_out': '0': RTS is low/'0' active 'uart_rts_out' is '0' when active and 'uart_rts_out' is '1' when inactive" "0,1" newline hexmask.long.byte 0x00 0.--7. 1. "TRIGGER_LEVEL,Trigger level" group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C control register" bitfld.long 0x00 31. "MASTER_MODE,Master mode enabled ('1') or not ('0')" "0,1" newline bitfld.long 0x00 30. "SLAVE_MODE,Slave mode enabled ('1') or not ('0')" "0,1" newline bitfld.long 0x00 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)" "0,1" newline bitfld.long 0x00 15. "S_NOT_READY_DATA_NACK,For internally clocked logic only" "0: clock stretching is performed (till the..,1: a received data element byte the slave is" newline bitfld.long 0x00 14. "S_NOT_READY_ADDR_NACK,For internally clocked logic (EC_AM is '0' and EC_OP is '0') on an address match or general call address (and S_GENERAL_IGNORE is '0')" "0: clock stretching is performed (till the,1: a received (matching or general) slave address" newline bitfld.long 0x00 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the receiver FIFO is not full" "0,1" newline bitfld.long 0x00 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full" "0,1" newline bitfld.long 0x00 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address" "0,1" newline bitfld.long 0x00 9. "M_NOT_READY_DATA_NACK,When '1' a received data element byte the master is immediately NACK'd when the receiver FIFO is full" "0,1" newline bitfld.long 0x00 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the receiver FIFO is not full" "0,1" newline bitfld.long 0x00 4.--7. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x64++0x03 line.long 0x00 "I2C_STATUS,I2C status register" hexmask.long.byte 0x00 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address" newline hexmask.long.byte 0x00 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address" newline bitfld.long 0x00 5. "M_READ,I2C master read transfer ('1') or I2C master write transfer ('0')" "0,1" newline bitfld.long 0x00 4. "S_READ,I2C slave read transfer ('1') or I2C slave write transfer ('0')" "0,1" newline bitfld.long 0x00 1. "I2C_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ mode)" "0,1" newline bitfld.long 0x00 0. "BUS_BUSY,I2C bus is busy" "0,1" group.long 0x68++0x03 line.long 0x00 "I2C_M_CMD,I2C master command register" bitfld.long 0x00 4. "M_STOP,When '1' attempt to transmit a STOP" "0,1" newline bitfld.long 0x00 3. "M_NACK,When '1' attempt to transmit a negative acknowledgement (NACK)" "0,1" newline bitfld.long 0x00 2. "M_ACK,When '1' attempt to transmit an acknowledgement (ACK)" "0,1" newline bitfld.long 0x00 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0')" "0,1" newline bitfld.long 0x00 0. "M_START,When '1' transmit a START or REPEATED START" "0,1" group.long 0x6C++0x03 line.long 0x00 "I2C_S_CMD,I2C slave command register" bitfld.long 0x00 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK)" "0,1" newline bitfld.long 0x00 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK)" "0,1" group.long 0x70++0x03 line.long 0x00 "I2C_CFG,I2C configuration register" bitfld.long 0x00 28.--29. "SDA_OUT_FILT_SEL,Selection of cumulative 'i2c_sda_out' filter delay: '0': 0 ns" "0,1,2,3" newline bitfld.long 0x00 20.--21. "SDA_OUT_FILT2_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 2" "0,1,2,3" newline bitfld.long 0x00 18.--19. "SDA_OUT_FILT1_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 1" "0,1,2,3" newline bitfld.long 0x00 16.--17. "SDA_OUT_FILT0_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 0" "0,1,2,3" newline bitfld.long 0x00 12. "SCL_IN_FILT_SEL,Selection of 'i2c_scl_in' filter delay: '0': 0 ns" "0,1" newline bitfld.long 0x00 8.--9. "SCL_IN_FILT_TRIM,Trim bits for 'i2c_scl_in' 50 ns filter" "0,1,2,3" newline bitfld.long 0x00 4. "SDA_IN_FILT_SEL,Selection of 'i2c_sda_in' filter delay: '0': 0 ns" "0,1" newline bitfld.long 0x00 0.--1. "SDA_IN_FILT_TRIM,Trim bits for 'i2c_sda_in' 50 ns filter" "0,1,2,3" group.long 0x200++0x03 line.long 0x00 "TX_CTRL,Transmitter control register" bitfld.long 0x00 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1')" "0,1" newline bitfld.long 0x00 0.--3. "DATA_WIDTH,Dataframe width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x204++0x03 line.long 0x00 "TX_FIFO_CTRL,Transmitter FIFO control register" bitfld.long 0x00 17. "FREEZE,When '1' hardware reads from the transmitter FIFO do not remove FIFO entries" "0,1" newline bitfld.long 0x00 16. "CLEAR,When '1' the transmitter FIFO and transmitter shift register are cleared/invalidated" "0,1" newline hexmask.long.byte 0x00 0.--7. 1. "TRIGGER_LEVEL,Trigger level" rgroup.long 0x208++0x03 line.long 0x00 "TX_FIFO_STATUS,Transmitter FIFO status register" hexmask.long.byte 0x00 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written" newline hexmask.long.byte 0x00 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read by the hardware" newline bitfld.long 0x00 15. "SR_VALID,Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0')" "0,1" newline hexmask.long.word 0x00 0.--8. 1. "USED,Amount of entries in the transmitter FIFO" wgroup.long 0x240++0x03 line.long 0x00 "TX_FIFO_WR,Transmitter FIFO write register" hexmask.long.word 0x00 0.--15. 1. "DATA,Data frame written into the transmitter FIFO" group.long 0x300++0x03 line.long 0x00 "RX_CTRL,Receiver control register" bitfld.long 0x00 9. "MEDIAN,Median filter" "0,1" newline bitfld.long 0x00 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1')" "0,1" newline bitfld.long 0x00 0.--3. "DATA_WIDTH,Dataframe width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x304++0x03 line.long 0x00 "RX_FIFO_CTRL,Receiver FIFO control register" bitfld.long 0x00 17. "FREEZE,When '1' hardware writes to the receiver FIFO have no effect" "0,1" newline bitfld.long 0x00 16. "CLEAR,When '1' the receiver FIFO and receiver shift register are cleared/invalidated" "0,1" newline hexmask.long.byte 0x00 0.--7. 1. "TRIGGER_LEVEL,Trigger level" rgroup.long 0x308++0x03 line.long 0x00 "RX_FIFO_STATUS,Receiver FIFO status register" hexmask.long.byte 0x00 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written by the hardware" newline hexmask.long.byte 0x00 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is" newline bitfld.long 0x00 15. "SR_VALID,Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0')" "0,1" newline hexmask.long.word 0x00 0.--8. 1. "USED,Amount of entries in the receiver FIFO" group.long 0x310++0x03 line.long 0x00 "RX_MATCH,Slave address and mask register" hexmask.long.byte 0x00 16.--23. 1. "MASK,Slave device address mask" newline hexmask.long.byte 0x00 0.--7. 1. "ADDR,Slave device address" rgroup.long 0x340++0x03 line.long 0x00 "RX_FIFO_RD,Receiver FIFO read register" hexmask.long.word 0x00 0.--15. 1. "DATA,Data read from the receiver FIFO" rgroup.long 0x344++0x03 line.long 0x00 "RX_FIFO_RD_SILENT,Receiver FIFO read register" hexmask.long.word 0x00 0.--15. 1. "DATA,Data read from the receiver FIFO" rgroup.long 0xE00++0x03 line.long 0x00 "INTR_CAUSE,Active clocked interrupt signal register" bitfld.long 0x00 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0" "0,1" newline bitfld.long 0x00 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0" "0,1" newline bitfld.long 0x00 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0" "0,1" newline bitfld.long 0x00 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0" "0,1" newline bitfld.long 0x00 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0" "0,1" newline bitfld.long 0x00 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0" "0,1" group.long 0xE80++0x03 line.long 0x00 "INTR_I2C_EC,Externally clocked I2C interrupt request register" bitfld.long 0x00 3. "EZ_READ_STOP,STOP detection after a read transfer occurred" "0,1" newline bitfld.long 0x00 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred" "0,1" newline bitfld.long 0x00 1. "EZ_STOP,STOP detection" "0,1" newline bitfld.long 0x00 0. "WAKE_UP,Wake up request" "0,1" group.long 0xE88++0x03 line.long 0x00 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask register" bitfld.long 0x00 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register" "0,1" rgroup.long 0xE8C++0x03 line.long 0x00 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked register" bitfld.long 0x00 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 1. "EZ_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 0. "WAKE_UP,Logical and of corresponding request and mask bits" "0,1" group.long 0xEC0++0x03 line.long 0x00 "INTR_SPI_EC,Externally clocked SPI interrupt request register" bitfld.long 0x00 3. "EZ_READ_STOP,STOP detection after a read transfer occurred" "0,1" newline bitfld.long 0x00 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred" "0,1" newline bitfld.long 0x00 1. "EZ_STOP,STOP detection" "0,1" newline bitfld.long 0x00 0. "WAKE_UP,Wake up request" "0,1" group.long 0xEC8++0x03 line.long 0x00 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask register" bitfld.long 0x00 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register" "0,1" rgroup.long 0xECC++0x03 line.long 0x00 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked register" bitfld.long 0x00 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 1. "EZ_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 0. "WAKE_UP,Logical and of corresponding request and mask bits" "0,1" group.long 0xF00++0x03 line.long 0x00 "INTR_M,Master interrupt request register" bitfld.long 0x00 9. "SPI_DONE,SPI master transfer done event: all data frames in the transmit FIFO are sent and the transmit FIFO and shift register are empty" "0,1" newline bitfld.long 0x00 8. "I2C_BUS_ERROR,I2C master bus error (unexpected detection of START or STOP condition)" "0,1" newline bitfld.long 0x00 4. "I2C_STOP,I2C master STOP" "0,1" newline bitfld.long 0x00 2. "I2C_ACK,I2C master acknowledgement" "0,1" newline bitfld.long 0x00 1. "I2C_NACK,I2C master negative acknowledgement" "0,1" newline bitfld.long 0x00 0. "I2C_ARB_LOST,I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line" "0,1" group.long 0xF04++0x03 line.long 0x00 "INTR_M_SET,Master interrupt set request register" bitfld.long 0x00 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register" "0,1" group.long 0xF08++0x03 line.long 0x00 "INTR_M_MASK,Master interrupt mask register" bitfld.long 0x00 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register" "0,1" rgroup.long 0xF0C++0x03 line.long 0x00 "INTR_M_MASKED,Master interrupt masked request register" bitfld.long 0x00 9. "SPI_DONE,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 4. "I2C_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 2. "I2C_ACK,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 1. "I2C_NACK,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits" "0,1" group.long 0xF40++0x03 line.long 0x00 "INTR_S,Slave interrupt request register" bitfld.long 0x00 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer" "0,1" newline bitfld.long 0x00 10. "SPI_EZ_STOP,SPI slave deselected after any EZ SPI transfer occurred" "0,1" newline bitfld.long 0x00 9. "SPI_EZ_WRITE_STOP,SPI slave deselected after a write EZ SPI transfer occurred" "0,1" newline bitfld.long 0x00 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition)" "0,1" newline bitfld.long 0x00 7. "I2C_GENERAL,I2C slave general call address received" "0,1" newline bitfld.long 0x00 6. "I2C_ADDR_MATCH,I2C slave matching address received" "0,1" newline bitfld.long 0x00 5. "I2C_START,I2C slave START received" "0,1" newline bitfld.long 0x00 4. "I2C_STOP,I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed)" "0,1" newline bitfld.long 0x00 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed)" "0,1" newline bitfld.long 0x00 2. "I2C_ACK,I2C slave acknowledgement received" "0,1" newline bitfld.long 0x00 1. "I2C_NACK,I2C slave negative acknowledgement received" "0,1" newline bitfld.long 0x00 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1')" "0,1" group.long 0xF44++0x03 line.long 0x00 "INTR_S_SET,Slave interrupt set request register" bitfld.long 0x00 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register" "0,1" group.long 0xF48++0x03 line.long 0x00 "INTR_S_MASK,Slave interrupt mask register" bitfld.long 0x00 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 5. "I2C_START,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register" "0,1" rgroup.long 0xF4C++0x03 line.long 0x00 "INTR_S_MASKED,Slave interrupt masked request register" bitfld.long 0x00 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 7. "I2C_GENERAL,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 5. "I2C_START,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 4. "I2C_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 2. "I2C_ACK,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 1. "I2C_NACK,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits" "0,1" group.long 0xF80++0x03 line.long 0x00 "INTR_TX,Transmitter interrupt request register" bitfld.long 0x00 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line" "0,1" newline bitfld.long 0x00 9. "UART_DONE,UART transmitter done event" "0,1" newline bitfld.long 0x00 8. "UART_NACK,UART transmitter received a negative acknowledgement in SmartCard mode" "0,1" newline bitfld.long 0x00 7. "BLOCKED,AHB-Lite write transfer can not get access to the EZ memory (EZ data access) due to an externally clocked EZ access" "0,1" newline bitfld.long 0x00 6. "UNDERFLOW,Attempt to read from an empty TX FIFO" "0,1" newline bitfld.long 0x00 5. "OVERFLOW,Attempt to write to a full TX FIFO" "0,1" newline bitfld.long 0x00 4. "EMPTY,TX FIFO is empty i.e" "0,1" newline bitfld.long 0x00 1. "NOT_FULL,TX FIFO is not full" "0,1" newline bitfld.long 0x00 0. "TRIGGER,Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL" "0,1" group.long 0xF84++0x03 line.long 0x00 "INTR_TX_SET,Transmitter interrupt set request register" bitfld.long 0x00 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register" "0,1" group.long 0xF88++0x03 line.long 0x00 "INTR_TX_MASK,Transmitter interrupt mask register" bitfld.long 0x00 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 4. "EMPTY,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register" "0,1" rgroup.long 0xF8C++0x03 line.long 0x00 "INTR_TX_MASKED,Transmitter interrupt masked request register" bitfld.long 0x00 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 9. "UART_DONE,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 8. "UART_NACK,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 7. "BLOCKED,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 6. "UNDERFLOW,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 5. "OVERFLOW,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 4. "EMPTY,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 1. "NOT_FULL,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 0. "TRIGGER,Logical and of corresponding request and mask bits" "0,1" group.long 0xFC0++0x03 line.long 0x00 "INTR_RX,Receiver interrupt request register" bitfld.long 0x00 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period" "0,1" newline bitfld.long 0x00 10. "BAUD_DETECT,LIN baudrate detection is completed" "0,1" newline bitfld.long 0x00 9. "PARITY_ERROR,Parity error in received data frame" "0,1" newline bitfld.long 0x00 8. "FRAME_ERROR,Frame error in received data frame" "0,1" newline bitfld.long 0x00 7. "BLOCKED,AHB-Lite read transfer can not get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access" "0,1" newline bitfld.long 0x00 6. "UNDERFLOW,Attempt to read from an empty RX FIFO" "0,1" newline bitfld.long 0x00 5. "OVERFLOW,Attempt to write to a full RX FIFO" "0,1" newline bitfld.long 0x00 3. "FULL,RX FIFO is full" "0,1" newline bitfld.long 0x00 2. "NOT_EMPTY,RX FIFO is not empty" "0,1" newline bitfld.long 0x00 0. "TRIGGER,More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in SCB_RX_FIFO_CTL" "0,1" group.long 0xFC4++0x03 line.long 0x00 "INTR_RX_SET,Receiver interrupt set request register" bitfld.long 0x00 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register" "0,1" newline bitfld.long 0x00 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register" "0,1" newline bitfld.long 0x00 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register" "0,1" newline bitfld.long 0x00 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register" "0,1" newline bitfld.long 0x00 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register" "0,1" newline bitfld.long 0x00 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register" "0,1" newline bitfld.long 0x00 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register" "0,1" newline bitfld.long 0x00 3. "FULL,Write with '1' to set corresponding bit in interrupt status register" "0,1" newline bitfld.long 0x00 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register" "0,1" newline bitfld.long 0x00 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register" "0,1" group.long 0xFC8++0x03 line.long 0x00 "INTR_RX_MASK,Receiver interrupt mask register" bitfld.long 0x00 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 3. "FULL,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register" "0,1" rgroup.long 0xFCC++0x03 line.long 0x00 "INTR_RX_MASKED,Receiver interrupt masked request register" bitfld.long 0x00 11. "BREAK_DETECT,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 10. "BAUD_DETECT,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 9. "PARITY_ERROR,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 8. "FRAME_ERROR,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 7. "BLOCKED,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 6. "UNDERFLOW,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 5. "OVERFLOW,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 3. "FULL,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 2. "NOT_EMPTY,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 0. "TRIGGER,Logical and of corresponding request and mask bits" "0,1" endif tree.end repeat.end endif sif cpuis("PMG1-S1")||cpuis("PMG1-S2")||cpuis("PMG1-S3") repeat 2. (list 2. 3.) (list ad:0x40070000 ad:0x40080000) (list ad:0x40240000 ad:0x40250000) tree "SCB$1" sif cpuis("PMG1-S1")||cpuis("PMG1-S2") base $2 group.long 0x00++0x03 line.long 0x00 "CTRL,Generic control register" bitfld.long 0x00 31. "ENABLED,IP enabled ('1') or not ('0')" "0,1" newline bitfld.long 0x00 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode,1: Serial Peripheral Interface (SPI) mode,2: Universal Asynchronous Receiver/Transmitter..,?..." newline bitfld.long 0x00 17. "BLOCK,Only used in externally clocked mode" "0,1" newline bitfld.long 0x00 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0')" "0,1" newline bitfld.long 0x00 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation: '0': CMD_RESP mode disabled" "0,1" newline bitfld.long 0x00 11. "BYTE_MODE,Determines the number of bits per FIFO data element: '0': 16-bit FIFO data elements" "0,1" newline bitfld.long 0x00 10. "EZ_MODE,Non EZ mode ('0') or EZ mode ('1')" "0,1" newline bitfld.long 0x00 9. "EC_OP_MODE,Internally clocked mode ('0') or externally clocked mode ('1') operation" "0,1" newline bitfld.long 0x00 8. "EC_AM_MODE,Internally clocked mode ('0') or externally clocked mode ('1') address matching (I2C) or selection (SPI)" "0,1" newline bitfld.long 0x00 0.--3. "OVS,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x04++0x03 line.long 0x00 "STATUS,Generic status register" bitfld.long 0x00 0. "EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode)" "0,1" group.long 0x08++0x03 line.long 0x00 "CMD_RESP_CTRL,Command/response control register" hexmask.long.word 0x00 16.--24. 1. "BASE_WR_ADDR,I2C/SPI read base address for CMD_RESP mode" newline hexmask.long.word 0x00 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode" rgroup.long 0x0C++0x03 line.long 0x00 "CMD_RESP_STATUS,Command/response status register" bitfld.long 0x00 31. "CMD_RESP_EC_BUSY,Indicates whether the CURR_RD_ADDR and CURR_WR_ADDR fields in this register are reliable (when CMD_RESP_EC_BUSY is '0') or not reliable (when CMD_RESP_EC_BUSY is '1')" "0,1" newline bitfld.long 0x00 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the IP" "0,1" newline hexmask.long.word 0x00 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode" newline hexmask.long.word 0x00 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode" group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI control register" bitfld.long 0x00 31. "MASTER_MODE,Master ('1') or slave ('0') mode" "0,1" newline bitfld.long 0x00 26.--27. "SLAVE_SELECT,Selects one of the four outgoing SPI slave select signals" "0: Slave 0 SPI_SELECT[0],1: Slave 1 SPI_SELECT[1],2: Slave 2 SPI_SELECT[2],3: Slave 3 SPI_SELECT[3]" newline bitfld.long 0x00 24.--25. "MODE,N/A" "0: SPI Motorola submode,1: SPI Texas Instruments submode,2: SPI National Semiconducturs submode,?..." newline bitfld.long 0x00 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)" "0,1" newline bitfld.long 0x00 11. "SSEL_POLARITY3,Slave select polarity" "0,1" newline bitfld.long 0x00 10. "SSEL_POLARITY2,Slave select polarity" "0,1" newline bitfld.long 0x00 9. "SSEL_POLARITY1,Slave select polarity" "0,1" newline bitfld.long 0x00 8. "SSEL_POLARITY0,Slave select polarity" "0,1" newline bitfld.long 0x00 5. "SCLK_CONTINUOUS,Only applicable in master mode" "0,1" newline bitfld.long 0x00 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured" "0,1" newline bitfld.long 0x00 3. "CPOL,Indicates the clock polarity" "0,1" newline bitfld.long 0x00 2. "CPHA,Only applicable in SPI Motorola submode" "0,1" newline bitfld.long 0x00 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode" "0,1" newline bitfld.long 0x00 0. "CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0')" "0,1" rgroup.long 0x24++0x03 line.long 0x00 "SPI_STATUS,SPI status register" hexmask.long.byte 0x00 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address" newline hexmask.long.byte 0x00 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address" newline bitfld.long 0x00 1. "SPI_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode)" "0,1" newline bitfld.long 0x00 0. "BUS_BUSY,SPI bus is busy" "0,1" group.long 0x40++0x03 line.long 0x00 "UART_CTRL,UART control register" bitfld.long 0x00 24.--25. "MODE,N/A" "0: Standard UART submode,1: SmartCard (ISO7816) submode,2: Infrared Data Association (IrDA) submode,?..." newline bitfld.long 0x00 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)" "0,1" group.long 0x44++0x03 line.long 0x00 "UART_TX_CTRL,UART transmitter control register" bitfld.long 0x00 8. "RETRY_ON_NACK,When '1' a data frame is retransmitted when a negative acknowledgement is received" "0,1" newline bitfld.long 0x00 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0')" "0,1" newline bitfld.long 0x00 4. "PARITY,Parity bit" "0,1" newline bitfld.long 0x00 0.--2. "STOP_BITS,Stop bits" "0,1,2,3,4,5,6,7" group.long 0x48++0x03 line.long 0x00 "UART_RX_CTRL,UART receiver control register" bitfld.long 0x00 16.--19. "BREAK_WIDTH,Break width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 13. "SKIP_START,Only applicable in standard UART submode" "0,1" newline bitfld.long 0x00 12. "LIN_MODE,Only applicable in standard UART submode" "0,1" newline bitfld.long 0x00 10. "MP_MODE,Multi-processor mode" "0,1" newline bitfld.long 0x00 9. "DROP_ON_FRAME_ERROR,Behaviour when an error is detected in a start or stop period" "0,1" newline bitfld.long 0x00 8. "DROP_ON_PARITY_ERROR,Behaviour when a parity check fails" "0,1" newline bitfld.long 0x00 6. "POLARITY,Inverts incoming RX line signal 'uart_rx_in'" "0,1" newline bitfld.long 0x00 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0')" "0,1" newline bitfld.long 0x00 4. "PARITY,Parity bit" "0,1" newline bitfld.long 0x00 0.--2. "STOP_BITS,Stop bits" "0,1,2,3,4,5,6,7" rgroup.long 0x4C++0x03 line.long 0x00 "UART_RX_STATUS,UART receiver status register" hexmask.long.word 0x00 0.--11. 1. "BR_COUNTER,Amount of peripheral clock periods that constitute the transmission of a 0x55 data frame (sent least signficant bit first) as determined by the receiver" group.long 0x50++0x03 line.long 0x00 "UART_FLOW_CTRL,UART flow control register" bitfld.long 0x00 25. "CTS_ENABLED,Enable use of CTS input signal 'uart_cts_in' by the UART transmitter: '0': Disabled" "0,1" newline bitfld.long 0x00 24. "CTS_POLARITY,Polarity of the CTS input signal 'uart_cts_in': '0': CTS is low/'0' active 'uart_cts_in' is '0' when active and 'uart_cts_in' is '1' when inactive" "0,1" newline bitfld.long 0x00 16. "RTS_POLARITY,Polarity of the RTS output signal 'uart_rts_out': '0': RTS is low/'0' active 'uart_rts_out' is '0' when active and 'uart_rts_out' is '1' when inactive" "0,1" newline hexmask.long.byte 0x00 0.--7. 1. "TRIGGER_LEVEL,Trigger level" group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C control register" bitfld.long 0x00 31. "MASTER_MODE,Master mode enabled ('1') or not ('0')" "0,1" newline bitfld.long 0x00 30. "SLAVE_MODE,Slave mode enabled ('1') or not ('0')" "0,1" newline bitfld.long 0x00 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)" "0,1" newline bitfld.long 0x00 15. "S_NOT_READY_DATA_NACK,For internally clocked logic only" "0: clock stretching is performed (till the..,1: a received data element byte the slave is" newline bitfld.long 0x00 14. "S_NOT_READY_ADDR_NACK,For internally clocked logic (EC_AM is '0' and EC_OP is '0') on an address match or general call address (and S_GENERAL_IGNORE is '0')" "0: clock stretching is performed (till the,1: a received (matching or general) slave address" newline bitfld.long 0x00 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the receiver FIFO is not full" "0,1" newline bitfld.long 0x00 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full" "0,1" newline bitfld.long 0x00 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address" "0,1" newline bitfld.long 0x00 9. "M_NOT_READY_DATA_NACK,When '1' a received data element byte the master is immediately NACK'd when the receiver FIFO is full" "0,1" newline bitfld.long 0x00 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the receiver FIFO is not full" "0,1" newline bitfld.long 0x00 4.--7. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x64++0x03 line.long 0x00 "I2C_STATUS,I2C status register" hexmask.long.byte 0x00 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address" newline hexmask.long.byte 0x00 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address" newline bitfld.long 0x00 5. "M_READ,I2C master read transfer ('1') or I2C master write transfer ('0')" "0,1" newline bitfld.long 0x00 4. "S_READ,I2C slave read transfer ('1') or I2C slave write transfer ('0')" "0,1" newline bitfld.long 0x00 1. "I2C_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ mode)" "0,1" newline bitfld.long 0x00 0. "BUS_BUSY,I2C bus is busy" "0,1" group.long 0x68++0x03 line.long 0x00 "I2C_M_CMD,I2C master command register" bitfld.long 0x00 4. "M_STOP,When '1' attempt to transmit a STOP" "0,1" newline bitfld.long 0x00 3. "M_NACK,When '1' attempt to transmit a negative acknowledgement (NACK)" "0,1" newline bitfld.long 0x00 2. "M_ACK,When '1' attempt to transmit an acknowledgement (ACK)" "0,1" newline bitfld.long 0x00 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0')" "0,1" newline bitfld.long 0x00 0. "M_START,When '1' transmit a START or REPEATED START" "0,1" group.long 0x6C++0x03 line.long 0x00 "I2C_S_CMD,I2C slave command register" bitfld.long 0x00 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK)" "0,1" newline bitfld.long 0x00 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK)" "0,1" group.long 0x70++0x03 line.long 0x00 "I2C_CFG,I2C configuration register" bitfld.long 0x00 28.--29. "SDA_OUT_FILT_SEL,Selection of cumulative 'i2c_sda_out' filter delay: '0': 0 ns" "0,1,2,3" newline bitfld.long 0x00 20.--21. "SDA_OUT_FILT2_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 2" "0,1,2,3" newline bitfld.long 0x00 18.--19. "SDA_OUT_FILT1_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 1" "0,1,2,3" newline bitfld.long 0x00 16.--17. "SDA_OUT_FILT0_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 0" "0,1,2,3" newline bitfld.long 0x00 12. "SCL_IN_FILT_SEL,Selection of 'i2c_scl_in' filter delay: '0': 0 ns" "0,1" newline bitfld.long 0x00 8.--9. "SCL_IN_FILT_TRIM,Trim bits for 'i2c_scl_in' 50 ns filter" "0,1,2,3" newline bitfld.long 0x00 4. "SDA_IN_FILT_SEL,Selection of 'i2c_sda_in' filter delay: '0': 0 ns" "0,1" newline bitfld.long 0x00 0.--1. "SDA_IN_FILT_TRIM,Trim bits for 'i2c_sda_in' 50 ns filter" "0,1,2,3" group.long 0x200++0x03 line.long 0x00 "TX_CTRL,Transmitter control register" bitfld.long 0x00 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1')" "0,1" newline bitfld.long 0x00 0.--3. "DATA_WIDTH,Dataframe width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x204++0x03 line.long 0x00 "TX_FIFO_CTRL,Transmitter FIFO control register" bitfld.long 0x00 17. "FREEZE,When '1' hardware reads from the transmitter FIFO do not remove FIFO entries" "0,1" newline bitfld.long 0x00 16. "CLEAR,When '1' the transmitter FIFO and transmitter shift register are cleared/invalidated" "0,1" newline hexmask.long.byte 0x00 0.--7. 1. "TRIGGER_LEVEL,Trigger level" rgroup.long 0x208++0x03 line.long 0x00 "TX_FIFO_STATUS,Transmitter FIFO status register" hexmask.long.byte 0x00 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written" newline hexmask.long.byte 0x00 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read by the hardware" newline bitfld.long 0x00 15. "SR_VALID,Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0')" "0,1" newline hexmask.long.word 0x00 0.--8. 1. "USED,Amount of entries in the transmitter FIFO" wgroup.long 0x240++0x03 line.long 0x00 "TX_FIFO_WR,Transmitter FIFO write register" hexmask.long.word 0x00 0.--15. 1. "DATA,Data frame written into the transmitter FIFO" group.long 0x300++0x03 line.long 0x00 "RX_CTRL,Receiver control register" bitfld.long 0x00 9. "MEDIAN,Median filter" "0,1" newline bitfld.long 0x00 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1')" "0,1" newline bitfld.long 0x00 0.--3. "DATA_WIDTH,Dataframe width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x304++0x03 line.long 0x00 "RX_FIFO_CTRL,Receiver FIFO control register" bitfld.long 0x00 17. "FREEZE,When '1' hardware writes to the receiver FIFO have no effect" "0,1" newline bitfld.long 0x00 16. "CLEAR,When '1' the receiver FIFO and receiver shift register are cleared/invalidated" "0,1" newline hexmask.long.byte 0x00 0.--7. 1. "TRIGGER_LEVEL,Trigger level" rgroup.long 0x308++0x03 line.long 0x00 "RX_FIFO_STATUS,Receiver FIFO status register" hexmask.long.byte 0x00 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written by the hardware" newline hexmask.long.byte 0x00 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is" newline bitfld.long 0x00 15. "SR_VALID,Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0')" "0,1" newline hexmask.long.word 0x00 0.--8. 1. "USED,Amount of entries in the receiver FIFO" group.long 0x310++0x03 line.long 0x00 "RX_MATCH,Slave address and mask register" hexmask.long.byte 0x00 16.--23. 1. "MASK,Slave device address mask" newline hexmask.long.byte 0x00 0.--7. 1. "ADDR,Slave device address" rgroup.long 0x340++0x03 line.long 0x00 "RX_FIFO_RD,Receiver FIFO read register" hexmask.long.word 0x00 0.--15. 1. "DATA,Data read from the receiver FIFO" rgroup.long 0x344++0x03 line.long 0x00 "RX_FIFO_RD_SILENT,Receiver FIFO read register" hexmask.long.word 0x00 0.--15. 1. "DATA,Data read from the receiver FIFO" rgroup.long 0xE00++0x03 line.long 0x00 "INTR_CAUSE,Active clocked interrupt signal register" bitfld.long 0x00 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0" "0,1" newline bitfld.long 0x00 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0" "0,1" newline bitfld.long 0x00 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0" "0,1" newline bitfld.long 0x00 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0" "0,1" newline bitfld.long 0x00 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0" "0,1" newline bitfld.long 0x00 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0" "0,1" group.long 0xE80++0x03 line.long 0x00 "INTR_I2C_EC,Externally clocked I2C interrupt request register" bitfld.long 0x00 3. "EZ_READ_STOP,STOP detection after a read transfer occurred" "0,1" newline bitfld.long 0x00 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred" "0,1" newline bitfld.long 0x00 1. "EZ_STOP,STOP detection" "0,1" newline bitfld.long 0x00 0. "WAKE_UP,Wake up request" "0,1" group.long 0xE88++0x03 line.long 0x00 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask register" bitfld.long 0x00 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register" "0,1" rgroup.long 0xE8C++0x03 line.long 0x00 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked register" bitfld.long 0x00 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 1. "EZ_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 0. "WAKE_UP,Logical and of corresponding request and mask bits" "0,1" group.long 0xEC0++0x03 line.long 0x00 "INTR_SPI_EC,Externally clocked SPI interrupt request register" bitfld.long 0x00 3. "EZ_READ_STOP,STOP detection after a read transfer occurred" "0,1" newline bitfld.long 0x00 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred" "0,1" newline bitfld.long 0x00 1. "EZ_STOP,STOP detection" "0,1" newline bitfld.long 0x00 0. "WAKE_UP,Wake up request" "0,1" group.long 0xEC8++0x03 line.long 0x00 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask register" bitfld.long 0x00 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register" "0,1" rgroup.long 0xECC++0x03 line.long 0x00 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked register" bitfld.long 0x00 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 1. "EZ_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 0. "WAKE_UP,Logical and of corresponding request and mask bits" "0,1" group.long 0xF00++0x03 line.long 0x00 "INTR_M,Master interrupt request register" bitfld.long 0x00 9. "SPI_DONE,SPI master transfer done event: all data frames in the transmit FIFO are sent and the transmit FIFO and shift register are empty" "0,1" newline bitfld.long 0x00 8. "I2C_BUS_ERROR,I2C master bus error (unexpected detection of START or STOP condition)" "0,1" newline bitfld.long 0x00 4. "I2C_STOP,I2C master STOP" "0,1" newline bitfld.long 0x00 2. "I2C_ACK,I2C master acknowledgement" "0,1" newline bitfld.long 0x00 1. "I2C_NACK,I2C master negative acknowledgement" "0,1" newline bitfld.long 0x00 0. "I2C_ARB_LOST,I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line" "0,1" group.long 0xF04++0x03 line.long 0x00 "INTR_M_SET,Master interrupt set request register" bitfld.long 0x00 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register" "0,1" group.long 0xF08++0x03 line.long 0x00 "INTR_M_MASK,Master interrupt mask register" bitfld.long 0x00 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register" "0,1" rgroup.long 0xF0C++0x03 line.long 0x00 "INTR_M_MASKED,Master interrupt masked request register" bitfld.long 0x00 9. "SPI_DONE,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 4. "I2C_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 2. "I2C_ACK,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 1. "I2C_NACK,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits" "0,1" group.long 0xF40++0x03 line.long 0x00 "INTR_S,Slave interrupt request register" bitfld.long 0x00 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer" "0,1" newline bitfld.long 0x00 10. "SPI_EZ_STOP,SPI slave deselected after any EZ SPI transfer occurred" "0,1" newline bitfld.long 0x00 9. "SPI_EZ_WRITE_STOP,SPI slave deselected after a write EZ SPI transfer occurred" "0,1" newline bitfld.long 0x00 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition)" "0,1" newline bitfld.long 0x00 7. "I2C_GENERAL,I2C slave general call address received" "0,1" newline bitfld.long 0x00 6. "I2C_ADDR_MATCH,I2C slave matching address received" "0,1" newline bitfld.long 0x00 5. "I2C_START,I2C slave START received" "0,1" newline bitfld.long 0x00 4. "I2C_STOP,I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed)" "0,1" newline bitfld.long 0x00 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed)" "0,1" newline bitfld.long 0x00 2. "I2C_ACK,I2C slave acknowledgement received" "0,1" newline bitfld.long 0x00 1. "I2C_NACK,I2C slave negative acknowledgement received" "0,1" newline bitfld.long 0x00 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1')" "0,1" group.long 0xF44++0x03 line.long 0x00 "INTR_S_SET,Slave interrupt set request register" bitfld.long 0x00 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register" "0,1" group.long 0xF48++0x03 line.long 0x00 "INTR_S_MASK,Slave interrupt mask register" bitfld.long 0x00 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 5. "I2C_START,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register" "0,1" rgroup.long 0xF4C++0x03 line.long 0x00 "INTR_S_MASKED,Slave interrupt masked request register" bitfld.long 0x00 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 7. "I2C_GENERAL,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 5. "I2C_START,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 4. "I2C_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 2. "I2C_ACK,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 1. "I2C_NACK,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits" "0,1" group.long 0xF80++0x03 line.long 0x00 "INTR_TX,Transmitter interrupt request register" bitfld.long 0x00 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line" "0,1" newline bitfld.long 0x00 9. "UART_DONE,UART transmitter done event" "0,1" newline bitfld.long 0x00 8. "UART_NACK,UART transmitter received a negative acknowledgement in SmartCard mode" "0,1" newline bitfld.long 0x00 7. "BLOCKED,AHB-Lite write transfer can not get access to the EZ memory (EZ data access) due to an externally clocked EZ access" "0,1" newline bitfld.long 0x00 6. "UNDERFLOW,Attempt to read from an empty TX FIFO" "0,1" newline bitfld.long 0x00 5. "OVERFLOW,Attempt to write to a full TX FIFO" "0,1" newline bitfld.long 0x00 4. "EMPTY,TX FIFO is empty i.e" "0,1" newline bitfld.long 0x00 1. "NOT_FULL,TX FIFO is not full" "0,1" newline bitfld.long 0x00 0. "TRIGGER,Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL" "0,1" group.long 0xF84++0x03 line.long 0x00 "INTR_TX_SET,Transmitter interrupt set request register" bitfld.long 0x00 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register" "0,1" group.long 0xF88++0x03 line.long 0x00 "INTR_TX_MASK,Transmitter interrupt mask register" bitfld.long 0x00 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 4. "EMPTY,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register" "0,1" rgroup.long 0xF8C++0x03 line.long 0x00 "INTR_TX_MASKED,Transmitter interrupt masked request register" bitfld.long 0x00 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 9. "UART_DONE,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 8. "UART_NACK,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 7. "BLOCKED,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 6. "UNDERFLOW,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 5. "OVERFLOW,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 4. "EMPTY,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 1. "NOT_FULL,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 0. "TRIGGER,Logical and of corresponding request and mask bits" "0,1" group.long 0xFC0++0x03 line.long 0x00 "INTR_RX,Receiver interrupt request register" bitfld.long 0x00 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period" "0,1" newline bitfld.long 0x00 10. "BAUD_DETECT,LIN baudrate detection is completed" "0,1" newline bitfld.long 0x00 9. "PARITY_ERROR,Parity error in received data frame" "0,1" newline bitfld.long 0x00 8. "FRAME_ERROR,Frame error in received data frame" "0,1" newline bitfld.long 0x00 7. "BLOCKED,AHB-Lite read transfer can not get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access" "0,1" newline bitfld.long 0x00 6. "UNDERFLOW,Attempt to read from an empty RX FIFO" "0,1" newline bitfld.long 0x00 5. "OVERFLOW,Attempt to write to a full RX FIFO" "0,1" newline bitfld.long 0x00 3. "FULL,RX FIFO is full" "0,1" newline bitfld.long 0x00 2. "NOT_EMPTY,RX FIFO is not empty" "0,1" newline bitfld.long 0x00 0. "TRIGGER,More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in SCB_RX_FIFO_CTL" "0,1" group.long 0xFC4++0x03 line.long 0x00 "INTR_RX_SET,Receiver interrupt set request register" bitfld.long 0x00 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register" "0,1" newline bitfld.long 0x00 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register" "0,1" newline bitfld.long 0x00 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register" "0,1" newline bitfld.long 0x00 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register" "0,1" newline bitfld.long 0x00 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register" "0,1" newline bitfld.long 0x00 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register" "0,1" newline bitfld.long 0x00 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register" "0,1" newline bitfld.long 0x00 3. "FULL,Write with '1' to set corresponding bit in interrupt status register" "0,1" newline bitfld.long 0x00 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register" "0,1" newline bitfld.long 0x00 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register" "0,1" group.long 0xFC8++0x03 line.long 0x00 "INTR_RX_MASK,Receiver interrupt mask register" bitfld.long 0x00 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 3. "FULL,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register" "0,1" rgroup.long 0xFCC++0x03 line.long 0x00 "INTR_RX_MASKED,Receiver interrupt masked request register" bitfld.long 0x00 11. "BREAK_DETECT,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 10. "BAUD_DETECT,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 9. "PARITY_ERROR,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 8. "FRAME_ERROR,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 7. "BLOCKED,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 6. "UNDERFLOW,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 5. "OVERFLOW,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 3. "FULL,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 2. "NOT_EMPTY,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 0. "TRIGGER,Logical and of corresponding request and mask bits" "0,1" elif cpuis("PMG1-S3") base $3 group.long 0x00++0x03 line.long 0x00 "CTRL,Generic control register" bitfld.long 0x00 31. "ENABLED,IP enabled ('1') or not ('0')" "0,1" newline bitfld.long 0x00 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode,1: Serial Peripheral Interface (SPI) mode,2: Universal Asynchronous Receiver/Transmitter..,?..." newline bitfld.long 0x00 17. "BLOCK,Only used in externally clocked mode" "0,1" newline bitfld.long 0x00 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0')" "0,1" newline bitfld.long 0x00 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation: '0': CMD_RESP mode disabled" "0,1" newline bitfld.long 0x00 11. "BYTE_MODE,Determines the number of bits per FIFO data element: '0': 16-bit FIFO data elements" "0,1" newline bitfld.long 0x00 10. "EZ_MODE,Non EZ mode ('0') or EZ mode ('1')" "0,1" newline bitfld.long 0x00 9. "EC_OP_MODE,Internally clocked mode ('0') or externally clocked mode ('1') operation" "0,1" newline bitfld.long 0x00 8. "EC_AM_MODE,Internally clocked mode ('0') or externally clocked mode ('1') address matching (I2C) or selection (SPI)" "0,1" newline bitfld.long 0x00 0.--3. "OVS,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x04++0x03 line.long 0x00 "STATUS,Generic status register" bitfld.long 0x00 0. "EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode)" "0,1" group.long 0x08++0x03 line.long 0x00 "CMD_RESP_CTRL,Command/response control register" hexmask.long.word 0x00 16.--24. 1. "BASE_WR_ADDR,I2C/SPI read base address for CMD_RESP mode" newline hexmask.long.word 0x00 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode" rgroup.long 0x0C++0x03 line.long 0x00 "CMD_RESP_STATUS,Command/response status register" bitfld.long 0x00 31. "CMD_RESP_EC_BUSY,Indicates whether the CURR_RD_ADDR and CURR_WR_ADDR fields in this register are reliable (when CMD_RESP_EC_BUSY is '0') or not reliable (when CMD_RESP_EC_BUSY is '1')" "0,1" newline bitfld.long 0x00 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the IP" "0,1" newline hexmask.long.word 0x00 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode" newline hexmask.long.word 0x00 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode" group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI control register" bitfld.long 0x00 31. "MASTER_MODE,Master ('1') or slave ('0') mode" "0,1" newline bitfld.long 0x00 26.--27. "SLAVE_SELECT,Selects one of the four outgoing SPI slave select signals" "0: Slave 0 SPI_SELECT[0],1: Slave 1 SPI_SELECT[1],2: Slave 2 SPI_SELECT[2],3: Slave 3 SPI_SELECT[3]" newline bitfld.long 0x00 24.--25. "MODE,N/A" "0: SPI Motorola submode,1: SPI Texas Instruments submode,2: SPI National Semiconducturs submode,?..." newline bitfld.long 0x00 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)" "0,1" newline bitfld.long 0x00 11. "SSEL_POLARITY3,Slave select polarity" "0,1" newline bitfld.long 0x00 10. "SSEL_POLARITY2,Slave select polarity" "0,1" newline bitfld.long 0x00 9. "SSEL_POLARITY1,Slave select polarity" "0,1" newline bitfld.long 0x00 8. "SSEL_POLARITY0,Slave select polarity" "0,1" newline bitfld.long 0x00 5. "SCLK_CONTINUOUS,Only applicable in master mode" "0,1" newline bitfld.long 0x00 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured" "0,1" newline bitfld.long 0x00 3. "CPOL,Indicates the clock polarity" "0,1" newline bitfld.long 0x00 2. "CPHA,Only applicable in SPI Motorola submode" "0,1" newline bitfld.long 0x00 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode" "0,1" newline bitfld.long 0x00 0. "CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0')" "0,1" rgroup.long 0x24++0x03 line.long 0x00 "SPI_STATUS,SPI status register" hexmask.long.byte 0x00 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address" newline hexmask.long.byte 0x00 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address" newline bitfld.long 0x00 1. "SPI_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode)" "0,1" newline bitfld.long 0x00 0. "BUS_BUSY,SPI bus is busy" "0,1" group.long 0x40++0x03 line.long 0x00 "UART_CTRL,UART control register" bitfld.long 0x00 24.--25. "MODE,N/A" "0: Standard UART submode,1: SmartCard (ISO7816) submode,2: Infrared Data Association (IrDA) submode,?..." newline bitfld.long 0x00 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)" "0,1" group.long 0x44++0x03 line.long 0x00 "UART_TX_CTRL,UART transmitter control register" bitfld.long 0x00 8. "RETRY_ON_NACK,When '1' a data frame is retransmitted when a negative acknowledgement is received" "0,1" newline bitfld.long 0x00 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0')" "0,1" newline bitfld.long 0x00 4. "PARITY,Parity bit" "0,1" newline bitfld.long 0x00 0.--2. "STOP_BITS,Stop bits" "0,1,2,3,4,5,6,7" group.long 0x48++0x03 line.long 0x00 "UART_RX_CTRL,UART receiver control register" bitfld.long 0x00 16.--19. "BREAK_WIDTH,Break width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 13. "SKIP_START,Only applicable in standard UART submode" "0,1" newline bitfld.long 0x00 12. "LIN_MODE,Only applicable in standard UART submode" "0,1" newline bitfld.long 0x00 10. "MP_MODE,Multi-processor mode" "0,1" newline bitfld.long 0x00 9. "DROP_ON_FRAME_ERROR,Behaviour when an error is detected in a start or stop period" "0,1" newline bitfld.long 0x00 8. "DROP_ON_PARITY_ERROR,Behaviour when a parity check fails" "0,1" newline bitfld.long 0x00 6. "POLARITY,Inverts incoming RX line signal 'uart_rx_in'" "0,1" newline bitfld.long 0x00 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0')" "0,1" newline bitfld.long 0x00 4. "PARITY,Parity bit" "0,1" newline bitfld.long 0x00 0.--2. "STOP_BITS,Stop bits" "0,1,2,3,4,5,6,7" rgroup.long 0x4C++0x03 line.long 0x00 "UART_RX_STATUS,UART receiver status register" hexmask.long.word 0x00 0.--11. 1. "BR_COUNTER,Amount of peripheral clock periods that constitute the transmission of a 0x55 data frame (sent least signficant bit first) as determined by the receiver" group.long 0x50++0x03 line.long 0x00 "UART_FLOW_CTRL,UART flow control register" bitfld.long 0x00 25. "CTS_ENABLED,Enable use of CTS input signal 'uart_cts_in' by the UART transmitter: '0': Disabled" "0,1" newline bitfld.long 0x00 24. "CTS_POLARITY,Polarity of the CTS input signal 'uart_cts_in': '0': CTS is low/'0' active 'uart_cts_in' is '0' when active and 'uart_cts_in' is '1' when inactive" "0,1" newline bitfld.long 0x00 16. "RTS_POLARITY,Polarity of the RTS output signal 'uart_rts_out': '0': RTS is low/'0' active 'uart_rts_out' is '0' when active and 'uart_rts_out' is '1' when inactive" "0,1" newline hexmask.long.byte 0x00 0.--7. 1. "TRIGGER_LEVEL,Trigger level" group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C control register" bitfld.long 0x00 31. "MASTER_MODE,Master mode enabled ('1') or not ('0')" "0,1" newline bitfld.long 0x00 30. "SLAVE_MODE,Slave mode enabled ('1') or not ('0')" "0,1" newline bitfld.long 0x00 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)" "0,1" newline bitfld.long 0x00 15. "S_NOT_READY_DATA_NACK,For internally clocked logic only" "0: clock stretching is performed (till the..,1: a received data element byte the slave is" newline bitfld.long 0x00 14. "S_NOT_READY_ADDR_NACK,For internally clocked logic (EC_AM is '0' and EC_OP is '0') on an address match or general call address (and S_GENERAL_IGNORE is '0')" "0: clock stretching is performed (till the,1: a received (matching or general) slave address" newline bitfld.long 0x00 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the receiver FIFO is not full" "0,1" newline bitfld.long 0x00 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full" "0,1" newline bitfld.long 0x00 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address" "0,1" newline bitfld.long 0x00 9. "M_NOT_READY_DATA_NACK,When '1' a received data element byte the master is immediately NACK'd when the receiver FIFO is full" "0,1" newline bitfld.long 0x00 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the receiver FIFO is not full" "0,1" newline bitfld.long 0x00 4.--7. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x64++0x03 line.long 0x00 "I2C_STATUS,I2C status register" hexmask.long.byte 0x00 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address" newline hexmask.long.byte 0x00 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address" newline bitfld.long 0x00 5. "M_READ,I2C master read transfer ('1') or I2C master write transfer ('0')" "0,1" newline bitfld.long 0x00 4. "S_READ,I2C slave read transfer ('1') or I2C slave write transfer ('0')" "0,1" newline bitfld.long 0x00 1. "I2C_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ mode)" "0,1" newline bitfld.long 0x00 0. "BUS_BUSY,I2C bus is busy" "0,1" group.long 0x68++0x03 line.long 0x00 "I2C_M_CMD,I2C master command register" bitfld.long 0x00 4. "M_STOP,When '1' attempt to transmit a STOP" "0,1" newline bitfld.long 0x00 3. "M_NACK,When '1' attempt to transmit a negative acknowledgement (NACK)" "0,1" newline bitfld.long 0x00 2. "M_ACK,When '1' attempt to transmit an acknowledgement (ACK)" "0,1" newline bitfld.long 0x00 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0')" "0,1" newline bitfld.long 0x00 0. "M_START,When '1' transmit a START or REPEATED START" "0,1" group.long 0x6C++0x03 line.long 0x00 "I2C_S_CMD,I2C slave command register" bitfld.long 0x00 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK)" "0,1" newline bitfld.long 0x00 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK)" "0,1" group.long 0x70++0x03 line.long 0x00 "I2C_CFG,I2C configuration register" bitfld.long 0x00 28.--29. "SDA_OUT_FILT_SEL,Selection of cumulative 'i2c_sda_out' filter delay: '0': 0 ns" "0,1,2,3" newline bitfld.long 0x00 20.--21. "SDA_OUT_FILT2_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 2" "0,1,2,3" newline bitfld.long 0x00 18.--19. "SDA_OUT_FILT1_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 1" "0,1,2,3" newline bitfld.long 0x00 16.--17. "SDA_OUT_FILT0_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 0" "0,1,2,3" newline bitfld.long 0x00 12. "SCL_IN_FILT_SEL,Selection of 'i2c_scl_in' filter delay: '0': 0 ns" "0,1" newline bitfld.long 0x00 8.--9. "SCL_IN_FILT_TRIM,Trim bits for 'i2c_scl_in' 50 ns filter" "0,1,2,3" newline bitfld.long 0x00 4. "SDA_IN_FILT_SEL,Selection of 'i2c_sda_in' filter delay: '0': 0 ns" "0,1" newline bitfld.long 0x00 0.--1. "SDA_IN_FILT_TRIM,Trim bits for 'i2c_sda_in' 50 ns filter" "0,1,2,3" group.long 0x200++0x03 line.long 0x00 "TX_CTRL,Transmitter control register" bitfld.long 0x00 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1')" "0,1" newline bitfld.long 0x00 0.--3. "DATA_WIDTH,Dataframe width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x204++0x03 line.long 0x00 "TX_FIFO_CTRL,Transmitter FIFO control register" bitfld.long 0x00 17. "FREEZE,When '1' hardware reads from the transmitter FIFO do not remove FIFO entries" "0,1" newline bitfld.long 0x00 16. "CLEAR,When '1' the transmitter FIFO and transmitter shift register are cleared/invalidated" "0,1" newline hexmask.long.byte 0x00 0.--7. 1. "TRIGGER_LEVEL,Trigger level" rgroup.long 0x208++0x03 line.long 0x00 "TX_FIFO_STATUS,Transmitter FIFO status register" hexmask.long.byte 0x00 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written" newline hexmask.long.byte 0x00 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read by the hardware" newline bitfld.long 0x00 15. "SR_VALID,Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0')" "0,1" newline hexmask.long.word 0x00 0.--8. 1. "USED,Amount of entries in the transmitter FIFO" wgroup.long 0x240++0x03 line.long 0x00 "TX_FIFO_WR,Transmitter FIFO write register" hexmask.long.word 0x00 0.--15. 1. "DATA,Data frame written into the transmitter FIFO" group.long 0x300++0x03 line.long 0x00 "RX_CTRL,Receiver control register" bitfld.long 0x00 9. "MEDIAN,Median filter" "0,1" newline bitfld.long 0x00 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1')" "0,1" newline bitfld.long 0x00 0.--3. "DATA_WIDTH,Dataframe width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x304++0x03 line.long 0x00 "RX_FIFO_CTRL,Receiver FIFO control register" bitfld.long 0x00 17. "FREEZE,When '1' hardware writes to the receiver FIFO have no effect" "0,1" newline bitfld.long 0x00 16. "CLEAR,When '1' the receiver FIFO and receiver shift register are cleared/invalidated" "0,1" newline hexmask.long.byte 0x00 0.--7. 1. "TRIGGER_LEVEL,Trigger level" rgroup.long 0x308++0x03 line.long 0x00 "RX_FIFO_STATUS,Receiver FIFO status register" hexmask.long.byte 0x00 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written by the hardware" newline hexmask.long.byte 0x00 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is" newline bitfld.long 0x00 15. "SR_VALID,Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0')" "0,1" newline hexmask.long.word 0x00 0.--8. 1. "USED,Amount of entries in the receiver FIFO" group.long 0x310++0x03 line.long 0x00 "RX_MATCH,Slave address and mask register" hexmask.long.byte 0x00 16.--23. 1. "MASK,Slave device address mask" newline hexmask.long.byte 0x00 0.--7. 1. "ADDR,Slave device address" rgroup.long 0x340++0x03 line.long 0x00 "RX_FIFO_RD,Receiver FIFO read register" hexmask.long.word 0x00 0.--15. 1. "DATA,Data read from the receiver FIFO" rgroup.long 0x344++0x03 line.long 0x00 "RX_FIFO_RD_SILENT,Receiver FIFO read register" hexmask.long.word 0x00 0.--15. 1. "DATA,Data read from the receiver FIFO" rgroup.long 0xE00++0x03 line.long 0x00 "INTR_CAUSE,Active clocked interrupt signal register" bitfld.long 0x00 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0" "0,1" newline bitfld.long 0x00 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0" "0,1" newline bitfld.long 0x00 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0" "0,1" newline bitfld.long 0x00 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0" "0,1" newline bitfld.long 0x00 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0" "0,1" newline bitfld.long 0x00 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0" "0,1" group.long 0xE80++0x03 line.long 0x00 "INTR_I2C_EC,Externally clocked I2C interrupt request register" bitfld.long 0x00 3. "EZ_READ_STOP,STOP detection after a read transfer occurred" "0,1" newline bitfld.long 0x00 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred" "0,1" newline bitfld.long 0x00 1. "EZ_STOP,STOP detection" "0,1" newline bitfld.long 0x00 0. "WAKE_UP,Wake up request" "0,1" group.long 0xE88++0x03 line.long 0x00 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask register" bitfld.long 0x00 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register" "0,1" rgroup.long 0xE8C++0x03 line.long 0x00 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked register" bitfld.long 0x00 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 1. "EZ_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 0. "WAKE_UP,Logical and of corresponding request and mask bits" "0,1" group.long 0xEC0++0x03 line.long 0x00 "INTR_SPI_EC,Externally clocked SPI interrupt request register" bitfld.long 0x00 3. "EZ_READ_STOP,STOP detection after a read transfer occurred" "0,1" newline bitfld.long 0x00 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred" "0,1" newline bitfld.long 0x00 1. "EZ_STOP,STOP detection" "0,1" newline bitfld.long 0x00 0. "WAKE_UP,Wake up request" "0,1" group.long 0xEC8++0x03 line.long 0x00 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask register" bitfld.long 0x00 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register" "0,1" rgroup.long 0xECC++0x03 line.long 0x00 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked register" bitfld.long 0x00 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 1. "EZ_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 0. "WAKE_UP,Logical and of corresponding request and mask bits" "0,1" group.long 0xF00++0x03 line.long 0x00 "INTR_M,Master interrupt request register" bitfld.long 0x00 9. "SPI_DONE,SPI master transfer done event: all data frames in the transmit FIFO are sent and the transmit FIFO and shift register are empty" "0,1" newline bitfld.long 0x00 8. "I2C_BUS_ERROR,I2C master bus error (unexpected detection of START or STOP condition)" "0,1" newline bitfld.long 0x00 4. "I2C_STOP,I2C master STOP" "0,1" newline bitfld.long 0x00 2. "I2C_ACK,I2C master acknowledgement" "0,1" newline bitfld.long 0x00 1. "I2C_NACK,I2C master negative acknowledgement" "0,1" newline bitfld.long 0x00 0. "I2C_ARB_LOST,I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line" "0,1" group.long 0xF04++0x03 line.long 0x00 "INTR_M_SET,Master interrupt set request register" bitfld.long 0x00 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register" "0,1" group.long 0xF08++0x03 line.long 0x00 "INTR_M_MASK,Master interrupt mask register" bitfld.long 0x00 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register" "0,1" rgroup.long 0xF0C++0x03 line.long 0x00 "INTR_M_MASKED,Master interrupt masked request register" bitfld.long 0x00 9. "SPI_DONE,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 4. "I2C_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 2. "I2C_ACK,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 1. "I2C_NACK,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits" "0,1" group.long 0xF40++0x03 line.long 0x00 "INTR_S,Slave interrupt request register" bitfld.long 0x00 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer" "0,1" newline bitfld.long 0x00 10. "SPI_EZ_STOP,SPI slave deselected after any EZ SPI transfer occurred" "0,1" newline bitfld.long 0x00 9. "SPI_EZ_WRITE_STOP,SPI slave deselected after a write EZ SPI transfer occurred" "0,1" newline bitfld.long 0x00 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition)" "0,1" newline bitfld.long 0x00 7. "I2C_GENERAL,I2C slave general call address received" "0,1" newline bitfld.long 0x00 6. "I2C_ADDR_MATCH,I2C slave matching address received" "0,1" newline bitfld.long 0x00 5. "I2C_START,I2C slave START received" "0,1" newline bitfld.long 0x00 4. "I2C_STOP,I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed)" "0,1" newline bitfld.long 0x00 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed)" "0,1" newline bitfld.long 0x00 2. "I2C_ACK,I2C slave acknowledgement received" "0,1" newline bitfld.long 0x00 1. "I2C_NACK,I2C slave negative acknowledgement received" "0,1" newline bitfld.long 0x00 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1')" "0,1" group.long 0xF44++0x03 line.long 0x00 "INTR_S_SET,Slave interrupt set request register" bitfld.long 0x00 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register" "0,1" group.long 0xF48++0x03 line.long 0x00 "INTR_S_MASK,Slave interrupt mask register" bitfld.long 0x00 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 5. "I2C_START,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register" "0,1" rgroup.long 0xF4C++0x03 line.long 0x00 "INTR_S_MASKED,Slave interrupt masked request register" bitfld.long 0x00 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 7. "I2C_GENERAL,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 5. "I2C_START,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 4. "I2C_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 2. "I2C_ACK,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 1. "I2C_NACK,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits" "0,1" group.long 0xF80++0x03 line.long 0x00 "INTR_TX,Transmitter interrupt request register" bitfld.long 0x00 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line" "0,1" newline bitfld.long 0x00 9. "UART_DONE,UART transmitter done event" "0,1" newline bitfld.long 0x00 8. "UART_NACK,UART transmitter received a negative acknowledgement in SmartCard mode" "0,1" newline bitfld.long 0x00 7. "BLOCKED,AHB-Lite write transfer can not get access to the EZ memory (EZ data access) due to an externally clocked EZ access" "0,1" newline bitfld.long 0x00 6. "UNDERFLOW,Attempt to read from an empty TX FIFO" "0,1" newline bitfld.long 0x00 5. "OVERFLOW,Attempt to write to a full TX FIFO" "0,1" newline bitfld.long 0x00 4. "EMPTY,TX FIFO is empty i.e" "0,1" newline bitfld.long 0x00 1. "NOT_FULL,TX FIFO is not full" "0,1" newline bitfld.long 0x00 0. "TRIGGER,Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL" "0,1" group.long 0xF84++0x03 line.long 0x00 "INTR_TX_SET,Transmitter interrupt set request register" bitfld.long 0x00 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register" "0,1" group.long 0xF88++0x03 line.long 0x00 "INTR_TX_MASK,Transmitter interrupt mask register" bitfld.long 0x00 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 4. "EMPTY,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register" "0,1" rgroup.long 0xF8C++0x03 line.long 0x00 "INTR_TX_MASKED,Transmitter interrupt masked request register" bitfld.long 0x00 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 9. "UART_DONE,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 8. "UART_NACK,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 7. "BLOCKED,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 6. "UNDERFLOW,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 5. "OVERFLOW,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 4. "EMPTY,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 1. "NOT_FULL,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 0. "TRIGGER,Logical and of corresponding request and mask bits" "0,1" group.long 0xFC0++0x03 line.long 0x00 "INTR_RX,Receiver interrupt request register" bitfld.long 0x00 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period" "0,1" newline bitfld.long 0x00 10. "BAUD_DETECT,LIN baudrate detection is completed" "0,1" newline bitfld.long 0x00 9. "PARITY_ERROR,Parity error in received data frame" "0,1" newline bitfld.long 0x00 8. "FRAME_ERROR,Frame error in received data frame" "0,1" newline bitfld.long 0x00 7. "BLOCKED,AHB-Lite read transfer can not get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access" "0,1" newline bitfld.long 0x00 6. "UNDERFLOW,Attempt to read from an empty RX FIFO" "0,1" newline bitfld.long 0x00 5. "OVERFLOW,Attempt to write to a full RX FIFO" "0,1" newline bitfld.long 0x00 3. "FULL,RX FIFO is full" "0,1" newline bitfld.long 0x00 2. "NOT_EMPTY,RX FIFO is not empty" "0,1" newline bitfld.long 0x00 0. "TRIGGER,More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in SCB_RX_FIFO_CTL" "0,1" group.long 0xFC4++0x03 line.long 0x00 "INTR_RX_SET,Receiver interrupt set request register" bitfld.long 0x00 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register" "0,1" newline bitfld.long 0x00 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register" "0,1" newline bitfld.long 0x00 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register" "0,1" newline bitfld.long 0x00 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register" "0,1" newline bitfld.long 0x00 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register" "0,1" newline bitfld.long 0x00 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register" "0,1" newline bitfld.long 0x00 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register" "0,1" newline bitfld.long 0x00 3. "FULL,Write with '1' to set corresponding bit in interrupt status register" "0,1" newline bitfld.long 0x00 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register" "0,1" newline bitfld.long 0x00 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register" "0,1" group.long 0xFC8++0x03 line.long 0x00 "INTR_RX_MASK,Receiver interrupt mask register" bitfld.long 0x00 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 3. "FULL,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register" "0,1" rgroup.long 0xFCC++0x03 line.long 0x00 "INTR_RX_MASKED,Receiver interrupt masked request register" bitfld.long 0x00 11. "BREAK_DETECT,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 10. "BAUD_DETECT,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 9. "PARITY_ERROR,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 8. "FRAME_ERROR,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 7. "BLOCKED,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 6. "UNDERFLOW,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 5. "OVERFLOW,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 3. "FULL,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 2. "NOT_EMPTY,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 0. "TRIGGER,Logical and of corresponding request and mask bits" "0,1" endif tree.end repeat.end endif sif cpuis("PMG1-S3") repeat 4. (list 4. 5. 6. 7.) (list ad:0x40260000 ad:0x40270000 ad:0x40280000 ad:0x40290000) tree "SCB$1" base $2 group.long 0x00++0x03 line.long 0x00 "CTRL,Generic control register" bitfld.long 0x00 31. "ENABLED,IP enabled ('1') or not ('0')" "0,1" newline bitfld.long 0x00 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode,1: Serial Peripheral Interface (SPI) mode,2: Universal Asynchronous Receiver/Transmitter..,?..." newline bitfld.long 0x00 17. "BLOCK,Only used in externally clocked mode" "0,1" newline bitfld.long 0x00 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0')" "0,1" newline bitfld.long 0x00 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation: '0': CMD_RESP mode disabled" "0,1" newline bitfld.long 0x00 11. "BYTE_MODE,Determines the number of bits per FIFO data element: '0': 16-bit FIFO data elements" "0,1" newline bitfld.long 0x00 10. "EZ_MODE,Non EZ mode ('0') or EZ mode ('1')" "0,1" newline bitfld.long 0x00 9. "EC_OP_MODE,Internally clocked mode ('0') or externally clocked mode ('1') operation" "0,1" newline bitfld.long 0x00 8. "EC_AM_MODE,Internally clocked mode ('0') or externally clocked mode ('1') address matching (I2C) or selection (SPI)" "0,1" newline bitfld.long 0x00 0.--3. "OVS,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x04++0x03 line.long 0x00 "STATUS,Generic status register" bitfld.long 0x00 0. "EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode)" "0,1" group.long 0x08++0x03 line.long 0x00 "CMD_RESP_CTRL,Command/response control register" hexmask.long.word 0x00 16.--24. 1. "BASE_WR_ADDR,I2C/SPI read base address for CMD_RESP mode" newline hexmask.long.word 0x00 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode" rgroup.long 0x0C++0x03 line.long 0x00 "CMD_RESP_STATUS,Command/response status register" bitfld.long 0x00 31. "CMD_RESP_EC_BUSY,Indicates whether the CURR_RD_ADDR and CURR_WR_ADDR fields in this register are reliable (when CMD_RESP_EC_BUSY is '0') or not reliable (when CMD_RESP_EC_BUSY is '1')" "0,1" newline bitfld.long 0x00 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the IP" "0,1" newline hexmask.long.word 0x00 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode" newline hexmask.long.word 0x00 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode" group.long 0x20++0x03 line.long 0x00 "SPI_CTRL,SPI control register" bitfld.long 0x00 31. "MASTER_MODE,Master ('1') or slave ('0') mode" "0,1" newline bitfld.long 0x00 26.--27. "SLAVE_SELECT,Selects one of the four outgoing SPI slave select signals" "0: Slave 0 SPI_SELECT[0],1: Slave 1 SPI_SELECT[1],2: Slave 2 SPI_SELECT[2],3: Slave 3 SPI_SELECT[3]" newline bitfld.long 0x00 24.--25. "MODE,N/A" "0: SPI Motorola submode,1: SPI Texas Instruments submode,2: SPI National Semiconducturs submode,?..." newline bitfld.long 0x00 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)" "0,1" newline bitfld.long 0x00 11. "SSEL_POLARITY3,Slave select polarity" "0,1" newline bitfld.long 0x00 10. "SSEL_POLARITY2,Slave select polarity" "0,1" newline bitfld.long 0x00 9. "SSEL_POLARITY1,Slave select polarity" "0,1" newline bitfld.long 0x00 8. "SSEL_POLARITY0,Slave select polarity" "0,1" newline bitfld.long 0x00 5. "SCLK_CONTINUOUS,Only applicable in master mode" "0,1" newline bitfld.long 0x00 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured" "0,1" newline bitfld.long 0x00 3. "CPOL,Indicates the clock polarity" "0,1" newline bitfld.long 0x00 2. "CPHA,Only applicable in SPI Motorola submode" "0,1" newline bitfld.long 0x00 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode" "0,1" newline bitfld.long 0x00 0. "CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0')" "0,1" rgroup.long 0x24++0x03 line.long 0x00 "SPI_STATUS,SPI status register" hexmask.long.byte 0x00 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address" newline hexmask.long.byte 0x00 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address" newline bitfld.long 0x00 1. "SPI_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode)" "0,1" newline bitfld.long 0x00 0. "BUS_BUSY,SPI bus is busy" "0,1" group.long 0x40++0x03 line.long 0x00 "UART_CTRL,UART control register" bitfld.long 0x00 24.--25. "MODE,N/A" "0: Standard UART submode,1: SmartCard (ISO7816) submode,2: Infrared Data Association (IrDA) submode,?..." newline bitfld.long 0x00 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)" "0,1" group.long 0x44++0x03 line.long 0x00 "UART_TX_CTRL,UART transmitter control register" bitfld.long 0x00 8. "RETRY_ON_NACK,When '1' a data frame is retransmitted when a negative acknowledgement is received" "0,1" newline bitfld.long 0x00 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0')" "0,1" newline bitfld.long 0x00 4. "PARITY,Parity bit" "0,1" newline bitfld.long 0x00 0.--2. "STOP_BITS,Stop bits" "0,1,2,3,4,5,6,7" group.long 0x48++0x03 line.long 0x00 "UART_RX_CTRL,UART receiver control register" bitfld.long 0x00 16.--19. "BREAK_WIDTH,Break width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 13. "SKIP_START,Only applicable in standard UART submode" "0,1" newline bitfld.long 0x00 12. "LIN_MODE,Only applicable in standard UART submode" "0,1" newline bitfld.long 0x00 10. "MP_MODE,Multi-processor mode" "0,1" newline bitfld.long 0x00 9. "DROP_ON_FRAME_ERROR,Behaviour when an error is detected in a start or stop period" "0,1" newline bitfld.long 0x00 8. "DROP_ON_PARITY_ERROR,Behaviour when a parity check fails" "0,1" newline bitfld.long 0x00 6. "POLARITY,Inverts incoming RX line signal 'uart_rx_in'" "0,1" newline bitfld.long 0x00 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0')" "0,1" newline bitfld.long 0x00 4. "PARITY,Parity bit" "0,1" newline bitfld.long 0x00 0.--2. "STOP_BITS,Stop bits" "0,1,2,3,4,5,6,7" rgroup.long 0x4C++0x03 line.long 0x00 "UART_RX_STATUS,UART receiver status register" hexmask.long.word 0x00 0.--11. 1. "BR_COUNTER,Amount of peripheral clock periods that constitute the transmission of a 0x55 data frame (sent least signficant bit first) as determined by the receiver" group.long 0x50++0x03 line.long 0x00 "UART_FLOW_CTRL,UART flow control register" bitfld.long 0x00 25. "CTS_ENABLED,Enable use of CTS input signal 'uart_cts_in' by the UART transmitter: '0': Disabled" "0,1" newline bitfld.long 0x00 24. "CTS_POLARITY,Polarity of the CTS input signal 'uart_cts_in': '0': CTS is low/'0' active 'uart_cts_in' is '0' when active and 'uart_cts_in' is '1' when inactive" "0,1" newline bitfld.long 0x00 16. "RTS_POLARITY,Polarity of the RTS output signal 'uart_rts_out': '0': RTS is low/'0' active 'uart_rts_out' is '0' when active and 'uart_rts_out' is '1' when inactive" "0,1" newline hexmask.long.byte 0x00 0.--7. 1. "TRIGGER_LEVEL,Trigger level" group.long 0x60++0x03 line.long 0x00 "I2C_CTRL,I2C control register" bitfld.long 0x00 31. "MASTER_MODE,Master mode enabled ('1') or not ('0')" "0,1" newline bitfld.long 0x00 30. "SLAVE_MODE,Slave mode enabled ('1') or not ('0')" "0,1" newline bitfld.long 0x00 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins)" "0,1" newline bitfld.long 0x00 15. "S_NOT_READY_DATA_NACK,For internally clocked logic only" "0: clock stretching is performed (till the..,1: a received data element byte the slave is" newline bitfld.long 0x00 14. "S_NOT_READY_ADDR_NACK,For internally clocked logic (EC_AM is '0' and EC_OP is '0') on an address match or general call address (and S_GENERAL_IGNORE is '0')" "0: clock stretching is performed (till the,1: a received (matching or general) slave address" newline bitfld.long 0x00 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the receiver FIFO is not full" "0,1" newline bitfld.long 0x00 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full" "0,1" newline bitfld.long 0x00 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address" "0,1" newline bitfld.long 0x00 9. "M_NOT_READY_DATA_NACK,When '1' a received data element byte the master is immediately NACK'd when the receiver FIFO is full" "0,1" newline bitfld.long 0x00 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the receiver FIFO is not full" "0,1" newline bitfld.long 0x00 4.--7. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x64++0x03 line.long 0x00 "I2C_STATUS,I2C status register" hexmask.long.byte 0x00 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address" newline hexmask.long.byte 0x00 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address" newline bitfld.long 0x00 5. "M_READ,I2C master read transfer ('1') or I2C master write transfer ('0')" "0,1" newline bitfld.long 0x00 4. "S_READ,I2C slave read transfer ('1') or I2C slave write transfer ('0')" "0,1" newline bitfld.long 0x00 1. "I2C_EC_BUSY,Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ mode)" "0,1" newline bitfld.long 0x00 0. "BUS_BUSY,I2C bus is busy" "0,1" group.long 0x68++0x03 line.long 0x00 "I2C_M_CMD,I2C master command register" bitfld.long 0x00 4. "M_STOP,When '1' attempt to transmit a STOP" "0,1" newline bitfld.long 0x00 3. "M_NACK,When '1' attempt to transmit a negative acknowledgement (NACK)" "0,1" newline bitfld.long 0x00 2. "M_ACK,When '1' attempt to transmit an acknowledgement (ACK)" "0,1" newline bitfld.long 0x00 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0')" "0,1" newline bitfld.long 0x00 0. "M_START,When '1' transmit a START or REPEATED START" "0,1" group.long 0x6C++0x03 line.long 0x00 "I2C_S_CMD,I2C slave command register" bitfld.long 0x00 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK)" "0,1" newline bitfld.long 0x00 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK)" "0,1" group.long 0x70++0x03 line.long 0x00 "I2C_CFG,I2C configuration register" bitfld.long 0x00 28.--29. "SDA_OUT_FILT_SEL,Selection of cumulative 'i2c_sda_out' filter delay: '0': 0 ns" "0,1,2,3" newline bitfld.long 0x00 20.--21. "SDA_OUT_FILT2_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 2" "0,1,2,3" newline bitfld.long 0x00 18.--19. "SDA_OUT_FILT1_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 1" "0,1,2,3" newline bitfld.long 0x00 16.--17. "SDA_OUT_FILT0_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 0" "0,1,2,3" newline bitfld.long 0x00 12. "SCL_IN_FILT_SEL,Selection of 'i2c_scl_in' filter delay: '0': 0 ns" "0,1" newline bitfld.long 0x00 8.--9. "SCL_IN_FILT_TRIM,Trim bits for 'i2c_scl_in' 50 ns filter" "0,1,2,3" newline bitfld.long 0x00 4. "SDA_IN_FILT_SEL,Selection of 'i2c_sda_in' filter delay: '0': 0 ns" "0,1" newline bitfld.long 0x00 0.--1. "SDA_IN_FILT_TRIM,Trim bits for 'i2c_sda_in' 50 ns filter" "0,1,2,3" group.long 0x200++0x03 line.long 0x00 "TX_CTRL,Transmitter control register" bitfld.long 0x00 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1')" "0,1" newline bitfld.long 0x00 0.--3. "DATA_WIDTH,Dataframe width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x204++0x03 line.long 0x00 "TX_FIFO_CTRL,Transmitter FIFO control register" bitfld.long 0x00 17. "FREEZE,When '1' hardware reads from the transmitter FIFO do not remove FIFO entries" "0,1" newline bitfld.long 0x00 16. "CLEAR,When '1' the transmitter FIFO and transmitter shift register are cleared/invalidated" "0,1" newline hexmask.long.byte 0x00 0.--7. 1. "TRIGGER_LEVEL,Trigger level" rgroup.long 0x208++0x03 line.long 0x00 "TX_FIFO_STATUS,Transmitter FIFO status register" hexmask.long.byte 0x00 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written" newline hexmask.long.byte 0x00 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read by the hardware" newline bitfld.long 0x00 15. "SR_VALID,Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0')" "0,1" newline hexmask.long.word 0x00 0.--8. 1. "USED,Amount of entries in the transmitter FIFO" wgroup.long 0x240++0x03 line.long 0x00 "TX_FIFO_WR,Transmitter FIFO write register" hexmask.long.word 0x00 0.--15. 1. "DATA,Data frame written into the transmitter FIFO" group.long 0x300++0x03 line.long 0x00 "RX_CTRL,Receiver control register" bitfld.long 0x00 9. "MEDIAN,Median filter" "0,1" newline bitfld.long 0x00 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1')" "0,1" newline bitfld.long 0x00 0.--3. "DATA_WIDTH,Dataframe width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x304++0x03 line.long 0x00 "RX_FIFO_CTRL,Receiver FIFO control register" bitfld.long 0x00 17. "FREEZE,When '1' hardware writes to the receiver FIFO have no effect" "0,1" newline bitfld.long 0x00 16. "CLEAR,When '1' the receiver FIFO and receiver shift register are cleared/invalidated" "0,1" newline hexmask.long.byte 0x00 0.--7. 1. "TRIGGER_LEVEL,Trigger level" rgroup.long 0x308++0x03 line.long 0x00 "RX_FIFO_STATUS,Receiver FIFO status register" hexmask.long.byte 0x00 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written by the hardware" newline hexmask.long.byte 0x00 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is" newline bitfld.long 0x00 15. "SR_VALID,Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0')" "0,1" newline hexmask.long.word 0x00 0.--8. 1. "USED,Amount of entries in the receiver FIFO" group.long 0x310++0x03 line.long 0x00 "RX_MATCH,Slave address and mask register" hexmask.long.byte 0x00 16.--23. 1. "MASK,Slave device address mask" newline hexmask.long.byte 0x00 0.--7. 1. "ADDR,Slave device address" rgroup.long 0x340++0x03 line.long 0x00 "RX_FIFO_RD,Receiver FIFO read register" hexmask.long.word 0x00 0.--15. 1. "DATA,Data read from the receiver FIFO" rgroup.long 0x344++0x03 line.long 0x00 "RX_FIFO_RD_SILENT,Receiver FIFO read register" hexmask.long.word 0x00 0.--15. 1. "DATA,Data read from the receiver FIFO" rgroup.long 0xE00++0x03 line.long 0x00 "INTR_CAUSE,Active clocked interrupt signal register" bitfld.long 0x00 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0" "0,1" newline bitfld.long 0x00 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0" "0,1" newline bitfld.long 0x00 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0" "0,1" newline bitfld.long 0x00 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0" "0,1" newline bitfld.long 0x00 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0" "0,1" newline bitfld.long 0x00 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0" "0,1" group.long 0xE80++0x03 line.long 0x00 "INTR_I2C_EC,Externally clocked I2C interrupt request register" bitfld.long 0x00 3. "EZ_READ_STOP,STOP detection after a read transfer occurred" "0,1" newline bitfld.long 0x00 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred" "0,1" newline bitfld.long 0x00 1. "EZ_STOP,STOP detection" "0,1" newline bitfld.long 0x00 0. "WAKE_UP,Wake up request" "0,1" group.long 0xE88++0x03 line.long 0x00 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask register" bitfld.long 0x00 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register" "0,1" rgroup.long 0xE8C++0x03 line.long 0x00 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked register" bitfld.long 0x00 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 1. "EZ_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 0. "WAKE_UP,Logical and of corresponding request and mask bits" "0,1" group.long 0xEC0++0x03 line.long 0x00 "INTR_SPI_EC,Externally clocked SPI interrupt request register" bitfld.long 0x00 3. "EZ_READ_STOP,STOP detection after a read transfer occurred" "0,1" newline bitfld.long 0x00 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred" "0,1" newline bitfld.long 0x00 1. "EZ_STOP,STOP detection" "0,1" newline bitfld.long 0x00 0. "WAKE_UP,Wake up request" "0,1" group.long 0xEC8++0x03 line.long 0x00 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask register" bitfld.long 0x00 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register" "0,1" rgroup.long 0xECC++0x03 line.long 0x00 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked register" bitfld.long 0x00 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 1. "EZ_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 0. "WAKE_UP,Logical and of corresponding request and mask bits" "0,1" group.long 0xF00++0x03 line.long 0x00 "INTR_M,Master interrupt request register" bitfld.long 0x00 9. "SPI_DONE,SPI master transfer done event: all data frames in the transmit FIFO are sent and the transmit FIFO and shift register are empty" "0,1" newline bitfld.long 0x00 8. "I2C_BUS_ERROR,I2C master bus error (unexpected detection of START or STOP condition)" "0,1" newline bitfld.long 0x00 4. "I2C_STOP,I2C master STOP" "0,1" newline bitfld.long 0x00 2. "I2C_ACK,I2C master acknowledgement" "0,1" newline bitfld.long 0x00 1. "I2C_NACK,I2C master negative acknowledgement" "0,1" newline bitfld.long 0x00 0. "I2C_ARB_LOST,I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line" "0,1" group.long 0xF04++0x03 line.long 0x00 "INTR_M_SET,Master interrupt set request register" bitfld.long 0x00 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register" "0,1" group.long 0xF08++0x03 line.long 0x00 "INTR_M_MASK,Master interrupt mask register" bitfld.long 0x00 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register" "0,1" rgroup.long 0xF0C++0x03 line.long 0x00 "INTR_M_MASKED,Master interrupt masked request register" bitfld.long 0x00 9. "SPI_DONE,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 4. "I2C_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 2. "I2C_ACK,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 1. "I2C_NACK,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits" "0,1" group.long 0xF40++0x03 line.long 0x00 "INTR_S,Slave interrupt request register" bitfld.long 0x00 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer" "0,1" newline bitfld.long 0x00 10. "SPI_EZ_STOP,SPI slave deselected after any EZ SPI transfer occurred" "0,1" newline bitfld.long 0x00 9. "SPI_EZ_WRITE_STOP,SPI slave deselected after a write EZ SPI transfer occurred" "0,1" newline bitfld.long 0x00 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition)" "0,1" newline bitfld.long 0x00 7. "I2C_GENERAL,I2C slave general call address received" "0,1" newline bitfld.long 0x00 6. "I2C_ADDR_MATCH,I2C slave matching address received" "0,1" newline bitfld.long 0x00 5. "I2C_START,I2C slave START received" "0,1" newline bitfld.long 0x00 4. "I2C_STOP,I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed)" "0,1" newline bitfld.long 0x00 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed)" "0,1" newline bitfld.long 0x00 2. "I2C_ACK,I2C slave acknowledgement received" "0,1" newline bitfld.long 0x00 1. "I2C_NACK,I2C slave negative acknowledgement received" "0,1" newline bitfld.long 0x00 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1')" "0,1" group.long 0xF44++0x03 line.long 0x00 "INTR_S_SET,Slave interrupt set request register" bitfld.long 0x00 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register" "0,1" group.long 0xF48++0x03 line.long 0x00 "INTR_S_MASK,Slave interrupt mask register" bitfld.long 0x00 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 5. "I2C_START,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register" "0,1" rgroup.long 0xF4C++0x03 line.long 0x00 "INTR_S_MASKED,Slave interrupt masked request register" bitfld.long 0x00 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 7. "I2C_GENERAL,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 5. "I2C_START,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 4. "I2C_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 2. "I2C_ACK,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 1. "I2C_NACK,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits" "0,1" group.long 0xF80++0x03 line.long 0x00 "INTR_TX,Transmitter interrupt request register" bitfld.long 0x00 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line" "0,1" newline bitfld.long 0x00 9. "UART_DONE,UART transmitter done event" "0,1" newline bitfld.long 0x00 8. "UART_NACK,UART transmitter received a negative acknowledgement in SmartCard mode" "0,1" newline bitfld.long 0x00 7. "BLOCKED,AHB-Lite write transfer can not get access to the EZ memory (EZ data access) due to an externally clocked EZ access" "0,1" newline bitfld.long 0x00 6. "UNDERFLOW,Attempt to read from an empty TX FIFO" "0,1" newline bitfld.long 0x00 5. "OVERFLOW,Attempt to write to a full TX FIFO" "0,1" newline bitfld.long 0x00 4. "EMPTY,TX FIFO is empty i.e" "0,1" newline bitfld.long 0x00 1. "NOT_FULL,TX FIFO is not full" "0,1" newline bitfld.long 0x00 0. "TRIGGER,Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL" "0,1" group.long 0xF84++0x03 line.long 0x00 "INTR_TX_SET,Transmitter interrupt set request register" bitfld.long 0x00 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register" "0,1" group.long 0xF88++0x03 line.long 0x00 "INTR_TX_MASK,Transmitter interrupt mask register" bitfld.long 0x00 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 4. "EMPTY,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register" "0,1" rgroup.long 0xF8C++0x03 line.long 0x00 "INTR_TX_MASKED,Transmitter interrupt masked request register" bitfld.long 0x00 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 9. "UART_DONE,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 8. "UART_NACK,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 7. "BLOCKED,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 6. "UNDERFLOW,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 5. "OVERFLOW,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 4. "EMPTY,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 1. "NOT_FULL,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 0. "TRIGGER,Logical and of corresponding request and mask bits" "0,1" group.long 0xFC0++0x03 line.long 0x00 "INTR_RX,Receiver interrupt request register" bitfld.long 0x00 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period" "0,1" newline bitfld.long 0x00 10. "BAUD_DETECT,LIN baudrate detection is completed" "0,1" newline bitfld.long 0x00 9. "PARITY_ERROR,Parity error in received data frame" "0,1" newline bitfld.long 0x00 8. "FRAME_ERROR,Frame error in received data frame" "0,1" newline bitfld.long 0x00 7. "BLOCKED,AHB-Lite read transfer can not get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access" "0,1" newline bitfld.long 0x00 6. "UNDERFLOW,Attempt to read from an empty RX FIFO" "0,1" newline bitfld.long 0x00 5. "OVERFLOW,Attempt to write to a full RX FIFO" "0,1" newline bitfld.long 0x00 3. "FULL,RX FIFO is full" "0,1" newline bitfld.long 0x00 2. "NOT_EMPTY,RX FIFO is not empty" "0,1" newline bitfld.long 0x00 0. "TRIGGER,More entries in the RX FIFO than the value specified by TRIGGER_LEVEL in SCB_RX_FIFO_CTL" "0,1" group.long 0xFC4++0x03 line.long 0x00 "INTR_RX_SET,Receiver interrupt set request register" bitfld.long 0x00 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register" "0,1" newline bitfld.long 0x00 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register" "0,1" newline bitfld.long 0x00 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register" "0,1" newline bitfld.long 0x00 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register" "0,1" newline bitfld.long 0x00 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register" "0,1" newline bitfld.long 0x00 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register" "0,1" newline bitfld.long 0x00 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register" "0,1" newline bitfld.long 0x00 3. "FULL,Write with '1' to set corresponding bit in interrupt status register" "0,1" newline bitfld.long 0x00 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register" "0,1" newline bitfld.long 0x00 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register" "0,1" group.long 0xFC8++0x03 line.long 0x00 "INTR_RX_MASK,Receiver interrupt mask register" bitfld.long 0x00 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 3. "FULL,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register" "0,1" rgroup.long 0xFCC++0x03 line.long 0x00 "INTR_RX_MASKED,Receiver interrupt masked request register" bitfld.long 0x00 11. "BREAK_DETECT,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 10. "BAUD_DETECT,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 9. "PARITY_ERROR,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 8. "FRAME_ERROR,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 7. "BLOCKED,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 6. "UNDERFLOW,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 5. "OVERFLOW,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 3. "FULL,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 2. "NOT_EMPTY,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 0. "TRIGGER,Logical and of corresponding request and mask bits" "0,1" tree.end repeat.end endif tree.end tree "SPCIF (Flash Control Interface)" base ad:0x40110000 group.long 0x00++0x03 line.long 0x00 "GEOMETRY,Flash/NVL geometry information" bitfld.long 0x00 31. "DE_CPD_LP,0': SRAM busy wait loop has not been copied" "0,1" hexmask.long.byte 0x00 24.--30. 1. "NVL,NVLatch size in Byte multiples (chip dependent): '0': 0 Bytes '1': 1 Byte" rbitfld.long 0x00 22.--23. "FLASH_ROW,Page size in 64 Byte multiples (chip dependent): '0': 64 byte '1': 128 byte '2': 192 byte '3': 256 byte The page size is used to detemine the number of Bytes in a page for Flash page based operations (e.g. PGM_PAGE)" "0,1,2,3" rbitfld.long 0x00 20.--21. "NUM_FLASH,Number of flash macros (chip dependent): '0': 1 flash macro '1': 2 flash macros '2': 3 flash macros '3': 4 flash macros" "0,1,2,3" rbitfld.long 0x00 14.--19. "SFLASH,Supervisory flash capacity in 256 Byte multiples (chip dependent)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" hexmask.long.word 0x00 0.--13. 1. "FLASH,Regular flash capacity in 256 Byte multiples (chip dependent)" group.long 0x1C++0x03 line.long 0x00 "NVL_WR_DATA,NVL write data register" hexmask.long.byte 0x00 0.--7. 1. "DATA,Data to be written to NVLatch array" group.long 0x7F0++0x03 line.long 0x00 "INTR,SPCIF interrupt request register" bitfld.long 0x00 0. "TIMER,Timer counter value reaches '0'" "0,1" group.long 0x7F4++0x03 line.long 0x00 "INTR_SET,SPCIF interrupt set request register" bitfld.long 0x00 0. "TIMER,Write INTR_SET field with '1' to set corresponding INTR field" "0,1" group.long 0x7F8++0x03 line.long 0x00 "INTR_MASK,SPCIF interrupt mask register" bitfld.long 0x00 0. "TIMER,Mask for corresponding field in INTR register" "0,1" rgroup.long 0x7FC++0x03 line.long 0x00 "INTR_MASKED,SPCIF interrupt masked request register" bitfld.long 0x00 0. "TIMER,Logical and of corresponding request and mask fields" "0,1" tree.end tree "SRSSLT (System Resources Lite Subsystem)" base ad:0x40030000 group.long 0x00++0x03 line.long 0x00 "PWR_CONTROL,Power Mode Control" bitfld.long 0x00 23. "EXT_VCCD,Always write 0 except as noted below" "0,1" rbitfld.long 0x00 18.--19. "SPARE,Spare AHB readback bits that are hooked to PWR_PWRSYS_TRIM1.SPARE_TRIM[1:0] through spare logic equivalent to bitwise inversion" "0,1,2,3" newline bitfld.long 0x00 17. "OVER_TEMP_THRESH,Over-temperature threshold" "0: TEMP_HIGH condition occurs between 120C and..,1: TEMP_HIGH condition occurs between 60C and 75C" bitfld.long 0x00 16. "OVER_TEMP_EN,Enables the die over temperature sensor" "0,1" newline rbitfld.long 0x00 5. "LPM_READY,Indicates whether the low power mode regulator is ready to enter DEEPSLEEP mode" "0: If DEEPSLEEP mode is requested device will..,1: Normal operation" rbitfld.long 0x00 4. "DEBUG_SESSION,Indicates whether a debug session is active (CDBGPWRUPREQ signal is 1)" "0: No debug session active,1: Debug session is active" newline rbitfld.long 0x00 0.--3. "POWER_MODE,Current power mode of the device" "0: RESET state,1: ACTIVE state,2: SLEEP state,3: DEEP_SLEEP state,?..." group.long 0x04++0x03 line.long 0x00 "PWR_KEY_DELAY,Power System Key&Delay Register" hexmask.long.word 0x00 0.--9. 1. "WAKEUP_HOLDOFF,Delay to wait for references to settle on wakeup from deepsleep" group.long 0x0C++0x03 line.long 0x00 "PWR_DDFT_SELECT,Power DDFT Mode Selection Register" bitfld.long 0x00 4.--7. "DDFT1_SEL,Select signal for power DDFT output #1" "0: WAKEUP,1: AWAKE,2: ACT_POWER_EN,3: ACT_POWER_UP,4: ACT_POWER_GOOD,5: ACT_REF_VALID,6: ACT_REG_VALID,7: ACT_COMP_OUT,8: ACT_TEMP_HIGH,9: DPSLP_COMP_OUT,10: DPSLP_POWER_UP,11: AWAKE_DELAYED,12: LPM_READY,13: SLEEPHOLDACK_N,14: 1'b0,15: 1'b1" bitfld.long 0x00 0.--3. "DDFT0_SEL,Select signal for power DDFT output #0" "0: WAKEUP,1: AWAKE,2: ACT_POWER_EN,3: ACT_POWER_UP,4: ACT_POWER_GOOD,5: srss_adft_control_act_ref_en,6: srss_adft_control_act_comp_en,7: srss_adft_control_dpslp_ref_en,8: srss_adft_control_dpslp_reg_en,9: srss_adft_control_dpslp_comp_en,10: pwr_control_over_temp_en,11: SLEEPHOLDREQ_N,12: ADFT_BUF_EN,13: ATPG observe point (no functional purpose),14: 1'b0,15: 1'b1" group.long 0x14++0x03 line.long 0x00 "TST_MODE,Test Mode Control Register" bitfld.long 0x00 31. "TEST_MODE,Setting this bit will prevent BootROM from yielding execution to Flash image" "0: Normal operation mode,1: Test mode (any test mode)" rbitfld.long 0x00 30. "TEST_KEY_DFT_EN,This bit is set when a XRES test mode key is shifted in" "0,1" newline bitfld.long 0x00 28. "BLOCK_ALT_XRES,Relevant only for parts that have the alternate XRES mechanism of overloading a GPIO pin temporarily as alternate XRES during test" "0,1" rbitfld.long 0x00 2. "SWD_CONNECTED," "0,1" group.long 0x28++0x03 line.long 0x00 "CLK_SELECT,Clock Select Register" bitfld.long 0x00 6.--7. "SYSCLK_DIV,Select clk_sys prescaler value" "0: clk_sys= clk_hf/1,1: clk_sys= clk_hf/2,2: clk_sys= clk_hf/4,3: clk_sys= clk_hf/8" bitfld.long 0x00 4.--5. "PUMP_SEL,Selects clock source for charge pump clock" "0: No clock connect to gnd,1: Use main IMO output,2: Use clk_hf (using selected source after..,?..." newline bitfld.long 0x00 2.--3. "HFCLK_DIV,Selects clk_hf predivider value" "0: Transparent mode feed through selected clock..,1: Divide selected clock source by 2,2: Divide selected clock source by 4,3: Divide selected clock source by 8" bitfld.long 0x00 0.--1. "HFCLK_SEL,Selects a source for clk_hf and dsi_in[0]" "0: IMO - Internal R/C Oscillator,1: EXTCLK - External Clock Pin,2: ECO - External-Crystal Oscillator or PLL..,?..." group.long 0x2C++0x03 line.long 0x00 "CLK_ILO_CONFIG,ILO Configuration" bitfld.long 0x00 31. "ENABLE,Master enable for ILO oscillator" "0,1" group.long 0x30++0x03 line.long 0x00 "CLK_IMO_CONFIG,IMO Configuration" bitfld.long 0x00 31. "ENABLE,Master enable for IMO oscillator" "0,1" group.long 0x34++0x03 line.long 0x00 "CLK_DFT_SELECT,Clock DFT Mode Selection Register" bitfld.long 0x00 14. "DFT_EDGE1,Edge sensitivity for in-line divider on output #1 (only relevant when DIV1>0)" "0: Use posedge for divider,1: Use negedge for divider" bitfld.long 0x00 12.--13. "DFT_DIV1,DFT Output Divide Down" "0: Direct Output,1: Divide by 2,2: Divide by 4,3: Divide by 8" newline bitfld.long 0x00 8.--11. "DFT_SEL1,Select signal for DFT output #1" "0: Disabled - output is 0,1: clk_ilo,2: clk_imo,3: clk_eco,4: clk_ext,5: clk_hf,6: clk_lf,7: clk_sys,8: clk_pump,9: clk_slpctrl,?..." bitfld.long 0x00 6. "DFT_EDGE0,Edge sensitivity for in-line divider on output #0 (only relevant when DIV0>0)" "0: Use posedge for divider,1: Use negedge for divider" newline bitfld.long 0x00 4.--5. "DFT_DIV0,DFT Output Divide Down" "0: Direct Output,1: Divide by 2,2: Divide by 4,3: Divide by 8" bitfld.long 0x00 0.--3. "DFT_SEL0,Select signal for DFT output #0" "0: Disabled - output is 0,1: clk_ilo,2: clk_imo,3: clk_eco,4: clk_ext,5: clk_hf,6: clk_lf,7: clk_sys,8: clk_pump,9: clk_slpctrl,?..." group.long 0x38++0x03 line.long 0x00 "WDT_DISABLE_KEY,Watchdog Disable Key Register" hexmask.long 0x00 0.--31. 1. "KEY,Disables WDT reset when equal to 0xACED8865" rgroup.long 0x3C++0x03 line.long 0x00 "WDT_COUNTER,Watchdog Counter Register" hexmask.long.word 0x00 0.--15. 1. "COUNTER,Current value of WDT Counter" group.long 0x40++0x03 line.long 0x00 "WDT_MATCH,Watchdog Match Register" bitfld.long 0x00 16.--19. "IGNORE_BITS,The number of MSB bits of the watchdog timer that are NOT checked against MATCH" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. "MATCH,Match value for Watchdog counter" group.long 0x44++0x03 line.long 0x00 "SRSS_INTR,SRSS Interrupt Register" bitfld.long 0x00 1. "TEMP_HIGH,Regulator over-temp interrupt" "0,1" bitfld.long 0x00 0. "WDT_MATCH,WDT Interrupt Request" "0,1" group.long 0x48++0x03 line.long 0x00 "SRSS_INTR_SET,SRSS Interrupt Set Register" bitfld.long 0x00 1. "TEMP_HIGH,Writing 1 to this bit internally sets the overtemp interrupt" "0,1" group.long 0x4C++0x03 line.long 0x00 "SRSS_INTR_MASK,SRSS Interrupt Mask Register" bitfld.long 0x00 1. "TEMP_HIGH,Masks REG_OVERTEMP interrupt" "0,1" bitfld.long 0x00 0. "WDT_MATCH,Clearing this bit will not forward the interrupt to the CPU" "0,1" group.long 0x54++0x03 line.long 0x00 "RES_CAUSE,Reset Cause Observation Register" bitfld.long 0x00 4. "RESET_SOFT,Cortex-M0 requested a system reset through it's SYSRESETREQ" "0,1" bitfld.long 0x00 3. "RESET_PROT_FAULT,A protection violation occurred that requires a RESET" "0,1" newline bitfld.long 0x00 0. "RESET_WDT,A WatchDog Timer reset has occurred since last power cycle" "0,1" group.long 0xF00++0x03 line.long 0x00 "PWR_BG_TRIM1,Bandgap Trim Register" bitfld.long 0x00 0.--5. "REF_VTRIM,Trims the bandgap reference voltage output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xF04++0x03 line.long 0x00 "PWR_BG_TRIM2,Bandgap Trim Register" bitfld.long 0x00 0.--5. "REF_ITRIM,Trims the bandgap reference current output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0xF08++0x03 line.long 0x00 "CLK_IMO_SELECT,IMO Frequency Select Register" bitfld.long 0x00 0.--2. "FREQ,Select operating frequency" "0: IMO runs at 24 MHz,1: IMO runs at 28 MHz,2: IMO runs at 32 MHz,3: IMO runs at 36 MHz,4: IMO runs at 40 MHz,5: IMO runs at 44 MHz,6: IMO runs at 48 MHz,?..." group.long 0xF0C++0x03 line.long 0x00 "CLK_IMO_TRIM1,IMO Trim Register" hexmask.long.byte 0x00 0.--7. 1. "OFFSET,Frequency trim bits" group.long 0xF10++0x03 line.long 0x00 "CLK_IMO_TRIM2,IMO Trim Register" bitfld.long 0x00 0.--2. "FSOFFSET,Frequency trim bits" "0,1,2,3,4,5,6,7" group.long 0xF14++0x03 line.long 0x00 "PWR_PWRSYS_TRIM1,Power System Trim Register" bitfld.long 0x00 4.--7. "SPARE_TRIM,Active-Reference temperature compensation trim (repurposed from spare bits)" "0: TC = 0 (unchanged),1: TC = -50ppm/C,?,?,?,?,?,?,?,?,10: TC = -80ppm/C,11: TC = +150ppm/C,?..." bitfld.long 0x00 0.--3. "DPSLP_REF_TRIM,Trims the DeepSleep reference that is used by the DeepSleep regulator and DeepSleep power comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xF18++0x03 line.long 0x00 "CLK_IMO_TRIM3,IMO Trim Register" bitfld.long 0x00 5.--6. "TCTRIM,IMO temperature compesation trim" "0,1,2,3" bitfld.long 0x00 0.--4. "STEPSIZE,IMO trim stepsize bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree "TCPWM (Timer/Counter/PWM)" sif cpuis("PMG1-S0")||cpuis("PMG1-S1")||cpuis("PMG1-S2") base ad:0x40090000 group.long 0x00++0x03 line.long 0x00 "CTRL,TCPWM control register 0" hexmask.long.byte 0x00 0.--7. 1. "COUNTER_ENABLED,Counter enables for counters 0 up to CNT_NR-1" group.long 0x08++0x03 line.long 0x00 "CMD,TCPWM command register" hexmask.long.byte 0x00 24.--31. 1. "COUNTER_START,Counters SW start trigger" hexmask.long.byte 0x00 16.--23. 1. "COUNTER_STOP,Counters SW stop trigger" hexmask.long.byte 0x00 8.--15. 1. "COUNTER_RELOAD,Counters SW reload trigger" hexmask.long.byte 0x00 0.--7. 1. "COUNTER_CAPTURE,Counters SW capture trigger" rgroup.long 0x0C++0x03 line.long 0x00 "INTR_CAUSE,TCPWM Counter interrupt cause register" hexmask.long.byte 0x00 0.--7. 1. "COUNTER_INT,Counters interrupt signal active" repeat 8. (increment 0 1)(increment 0 0x40) tree "CNT[$1]" group.long ($2+0x100)++0x03 line.long 0x00 "CTRL,Counter control register" bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,?,2: Capture mode,3: Quadrature encoding mode,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,?..." bitfld.long 0x00 20.--21. "QUADRATURE_MODE,In QUAD mode selects quadrature encoding mode (X1/X2/X4)" "0: X1 encoding (QUAD mode),1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),?..." newline bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1" bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')" newline hexmask.long.byte 0x00 8.--15. 1. "GENERIC,Generic 8-bit control field" bitfld.long 0x00 3. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1" newline bitfld.long 0x00 2. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1" bitfld.long 0x00 1. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1" newline bitfld.long 0x00 0. "AUTO_RELOAD_CC,Specifies switching of the CC and buffered CC values" "0,1" rgroup.long ($2+0x104)++0x03 line.long 0x00 "STATUS,Counter status register" bitfld.long 0x00 31. "RUNNING,When '0' the counter is NOT running" "0,1" hexmask.long.byte 0x00 8.--15. 1. "GENERIC,Generic 8-bit counter field" newline bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1" group.long ($2+0x108)++0x03 line.long 0x00 "COUNTER,Counter count register" hexmask.long.word 0x00 0.--15. 1. "COUNTER,16-bit counter value" group.long ($2+0x10C)++0x03 line.long 0x00 "CC,Counter compare/capture register" hexmask.long.word 0x00 0.--15. 1. "CC,In CAPTURE mode captures the counter value" group.long ($2+0x110)++0x03 line.long 0x00 "CC_BUFF,Counter buffered compare/capture register" hexmask.long.word 0x00 0.--15. 1. "CC,Additional buffer for counter CC register" group.long ($2+0x114)++0x03 line.long 0x00 "PERIOD,Counter period register" hexmask.long.word 0x00 0.--15. 1. "PERIOD,Period value: upper value of the counter" group.long ($2+0x118)++0x03 line.long 0x00 "PERIOD_BUFF,Counter buffered period register" hexmask.long.word 0x00 0.--15. 1. "PERIOD,Additional buffer for counter PERIOD register" group.long ($2+0x120)++0x03 line.long 0x00 "TR_CTRL0,Counter trigger control register 0" bitfld.long 0x00 16.--19. "START_SEL,Selects one of the 16 input triggers as a start trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "STOP_SEL,Selects one of the 16 input triggers as a stop trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "RELOAD_SEL,Selects one of the 16 input triggers as a reload trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. "COUNT_SEL,Selects one of the 16 input triggers as a count trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "CAPTURE_SEL,Selects one of the 16 input triggers as a capture trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long ($2+0x124)++0x03 line.long 0x00 "TR_CTRL1,Counter trigger control register 1" bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is" bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is" newline bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is" bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is" newline bitfld.long 0x00 0.--1. "CAPTURE_EDGE,A capture event will copy the counter value into the CC register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is" group.long ($2+0x128)++0x03 line.long 0x00 "TR_CTRL2,Counter trigger control register 2" bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE" bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE" newline bitfld.long 0x00 0.--1. "CC_MATCH_MODE,Determines the effect of a compare match event (COUNTER equals CC register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE" group.long ($2+0x130)++0x03 line.long 0x00 "INTR,Interrupt request register" bitfld.long 0x00 1. "CC_MATCH,Counter matches CC register event" "0,1" bitfld.long 0x00 0. "TC,Terminal count event" "0,1" group.long ($2+0x134)++0x03 line.long 0x00 "INTR_SET,Interrupt set request register" bitfld.long 0x00 1. "CC_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1" bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1" group.long ($2+0x138)++0x03 line.long 0x00 "INTR_MASK,Interrupt mask register" bitfld.long 0x00 1. "CC_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1" bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1" rgroup.long ($2+0x13C)++0x03 line.long 0x00 "INTR_MASKED,Interrupt masked request register" bitfld.long 0x00 1. "CC_MATCH,Logical and of corresponding request and mask bits" "0,1" bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1" tree.end repeat.end elif cpuis("PMG1-S3") base ad:0x40200000 group.long 0x00++0x03 line.long 0x00 "CTRL,TCPWM control register 0" hexmask.long.byte 0x00 0.--7. 1. "COUNTER_ENABLED,Counter enables for counters 0 up to CNT_NR-1" group.long 0x08++0x03 line.long 0x00 "CMD,TCPWM command register" hexmask.long.byte 0x00 24.--31. 1. "COUNTER_START,Counters SW start trigger" hexmask.long.byte 0x00 16.--23. 1. "COUNTER_STOP,Counters SW stop trigger" hexmask.long.byte 0x00 8.--15. 1. "COUNTER_RELOAD,Counters SW reload trigger" hexmask.long.byte 0x00 0.--7. 1. "COUNTER_CAPTURE,Counters SW capture trigger" rgroup.long 0x0C++0x03 line.long 0x00 "INTR_CAUSE,TCPWM Counter interrupt cause register" hexmask.long.byte 0x00 0.--7. 1. "COUNTER_INT,Counters interrupt signal active" repeat 8. (increment 0 1)(increment 0 0x40) tree "CNT[$1]" group.long ($2+0x100)++0x03 line.long 0x00 "CTRL,Counter control register" bitfld.long 0x00 24.--26. "MODE,Counter mode" "0: Timer mode,?,2: Capture mode,3: Quadrature encoding mode,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,?..." bitfld.long 0x00 20.--21. "QUADRATURE_MODE,In QUAD mode selects quadrature encoding mode (X1/X2/X4)" "0: X1 encoding (QUAD mode),1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),?..." newline bitfld.long 0x00 18. "ONE_SHOT,When '0' counter runs continuous" "0,1" bitfld.long 0x00 16.--17. "UP_DOWN_MODE,Determines counter direction" "0: Count up (to PERIOD),1: Count down (to '0'),2: Count up (to PERIOD) then count down (to '0'),3: Count up (to PERIOD) then count down (to '0')" newline hexmask.long.byte 0x00 8.--15. 1. "GENERIC,Generic 8-bit control field" bitfld.long 0x00 3. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter" "0,1" newline bitfld.long 0x00 2. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior: '1': synchronous kill mode: the kill event disables the 'dt_line_out' and 'dt_line_compl_out' signals till the next terminal count event (synchronous kill)" "0,1" bitfld.long 0x00 1. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values" "0,1" newline bitfld.long 0x00 0. "AUTO_RELOAD_CC,Specifies switching of the CC and buffered CC values" "0,1" rgroup.long ($2+0x104)++0x03 line.long 0x00 "STATUS,Counter status register" bitfld.long 0x00 31. "RUNNING,When '0' the counter is NOT running" "0,1" hexmask.long.byte 0x00 8.--15. 1. "GENERIC,Generic 8-bit counter field" newline bitfld.long 0x00 0. "DOWN,When '0' counter is counting up" "0,1" group.long ($2+0x108)++0x03 line.long 0x00 "COUNTER,Counter count register" hexmask.long.word 0x00 0.--15. 1. "COUNTER,16-bit counter value" group.long ($2+0x10C)++0x03 line.long 0x00 "CC,Counter compare/capture register" hexmask.long.word 0x00 0.--15. 1. "CC,In CAPTURE mode captures the counter value" group.long ($2+0x110)++0x03 line.long 0x00 "CC_BUFF,Counter buffered compare/capture register" hexmask.long.word 0x00 0.--15. 1. "CC,Additional buffer for counter CC register" group.long ($2+0x114)++0x03 line.long 0x00 "PERIOD,Counter period register" hexmask.long.word 0x00 0.--15. 1. "PERIOD,Period value: upper value of the counter" group.long ($2+0x118)++0x03 line.long 0x00 "PERIOD_BUFF,Counter buffered period register" hexmask.long.word 0x00 0.--15. 1. "PERIOD,Additional buffer for counter PERIOD register" group.long ($2+0x120)++0x03 line.long 0x00 "TR_CTRL0,Counter trigger control register 0" bitfld.long 0x00 16.--19. "START_SEL,Selects one of the 16 input triggers as a start trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "STOP_SEL,Selects one of the 16 input triggers as a stop trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "RELOAD_SEL,Selects one of the 16 input triggers as a reload trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4.--7. "COUNT_SEL,Selects one of the 16 input triggers as a count trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "CAPTURE_SEL,Selects one of the 16 input triggers as a capture trigger" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long ($2+0x124)++0x03 line.long 0x00 "TR_CTRL1,Counter trigger control register 1" bitfld.long 0x00 8.--9. "START_EDGE,A start event will start the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is" bitfld.long 0x00 6.--7. "STOP_EDGE,A stop event will stop the counter i.e" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is" newline bitfld.long 0x00 4.--5. "RELOAD_EDGE,A reload event will initialize the counter" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is" bitfld.long 0x00 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is" newline bitfld.long 0x00 0.--1. "CAPTURE_EDGE,A capture event will copy the counter value into the CC register" "0: Rising edge,1: Falling edge,2: Rising AND falling edge,3: No edge detection use trigger as is" group.long ($2+0x128)++0x03 line.long 0x00 "TR_CTRL2,Counter trigger control register 2" bitfld.long 0x00 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE" bitfld.long 0x00 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE" newline bitfld.long 0x00 0.--1. "CC_MATCH_MODE,Determines the effect of a compare match event (COUNTER equals CC register) on the 'line_out' output signals" "0: Set to '1',1: Set to '0',2: INVERT,3: NO_CHANGE" group.long ($2+0x130)++0x03 line.long 0x00 "INTR,Interrupt request register" bitfld.long 0x00 1. "CC_MATCH,Counter matches CC register event" "0,1" bitfld.long 0x00 0. "TC,Terminal count event" "0,1" group.long ($2+0x134)++0x03 line.long 0x00 "INTR_SET,Interrupt set request register" bitfld.long 0x00 1. "CC_MATCH,Write with '1' to set corresponding bit in interrupt request register" "0,1" bitfld.long 0x00 0. "TC,Write with '1' to set corresponding bit in interrupt request register" "0,1" group.long ($2+0x138)++0x03 line.long 0x00 "INTR_MASK,Interrupt mask register" bitfld.long 0x00 1. "CC_MATCH,Mask bit for corresponding bit in interrupt request register" "0,1" bitfld.long 0x00 0. "TC,Mask bit for corresponding bit in interrupt request register" "0,1" rgroup.long ($2+0x13C)++0x03 line.long 0x00 "INTR_MASKED,Interrupt masked request register" bitfld.long 0x00 1. "CC_MATCH,Logical and of corresponding request and mask bits" "0,1" bitfld.long 0x00 0. "TC,Logical and of corresponding request and mask bits" "0,1" tree.end repeat.end endif tree.end sif cpuis("PMG1-S3")||cpuis("PMG1-S2") tree "USBFS (USB Device Controller)" sif cpuis("PMG1-S2") base ad:0x400C0000 repeat 8. (increment 0 1) (increment 0 0x4) group.long ($2+0x00)++0x03 line.long 0x00 "EP0_DR[$1],Control End point EP0 Data Register $1" hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE,This register is shared for both transmit and receive" repeat.end group.long 0x20++0x03 line.long 0x00 "CR0,USB control 0 Register" bitfld.long 0x00 7. "USB_ENABLE,This bit enables the device to respond to USB traffic" "0,1" newline hexmask.long.byte 0x00 0.--6. 1. "DEVICE_ADDRESS,These bits specify the USB device address to which the SIE will respond" group.long 0x24++0x03 line.long 0x00 "CR1,USB control 1 Register" bitfld.long 0x00 3. "TRIM_OFFSET_MSB,This bit enables trim bit[7]" "0,1" newline bitfld.long 0x00 2. "BUS_ACTIVITY,The Bus Activity bit is a stickybit that detects any non-idle USB event that has occurred on the USB bus" "0,1" newline bitfld.long 0x00 1. "ENABLE_LOCK,This bit is set to turn on the automatic frequency locking of the internal oscillator to USB traffic" "0,1" newline bitfld.long 0x00 0. "REG_ENABLE,This bit controls the operation of the internal USB regulator" "0,1" group.long 0x28++0x03 line.long 0x00 "SIE_EP_INT_EN,USB SIE Data Endpoints Interrupt Enable Register" bitfld.long 0x00 7. "EP8_INTR_EN,Enables interrupt for EP8" "0,1" newline bitfld.long 0x00 6. "EP7_INTR_EN,Enables interrupt for EP7" "0,1" newline bitfld.long 0x00 5. "EP6_INTR_EN,Enables interrupt for EP6" "0,1" newline bitfld.long 0x00 4. "EP5_INTR_EN,Enables interrupt for EP5" "0,1" newline bitfld.long 0x00 3. "EP4_INTR_EN,Enables interrupt for EP4" "0,1" newline bitfld.long 0x00 2. "EP3_INTR_EN,Enables interrupt for EP3" "0,1" newline bitfld.long 0x00 1. "EP2_INTR_EN,Enables interrupt for EP2" "0,1" newline bitfld.long 0x00 0. "EP1_INTR_EN,Enables interrupt for EP1" "0,1" group.long 0x2C++0x03 line.long 0x00 "SIE_EP_INT_SR,USB SIE Data Endpoint Interrupt Status" bitfld.long 0x00 7. "EP8_INTR,Interrupt status for EP8" "0,1" newline bitfld.long 0x00 6. "EP7_INTR,Interrupt status for EP7" "0,1" newline bitfld.long 0x00 5. "EP6_INTR,Interrupt status for EP6" "0,1" newline bitfld.long 0x00 4. "EP5_INTR,Interrupt status for EP5" "0,1" newline bitfld.long 0x00 3. "EP4_INTR,Interrupt status for EP4" "0,1" newline bitfld.long 0x00 2. "EP3_INTR,Interrupt status for EP3" "0,1" newline bitfld.long 0x00 1. "EP2_INTR,Interrupt status for EP2" "0,1" newline bitfld.long 0x00 0. "EP1_INTR,Interrupt status for EP1" "0,1" group.long 0x30++0x03 line.long 0x00 "SIE_EP1_CNT0,Non-control endpoint count register" bitfld.long 0x00 7. "DATA_TOGGLE,This bit selects the DATA packet's toggle state" "0,1" newline bitfld.long 0x00 6. "DATA_VALID,This bit is used for OUT transactions only and is read only" "0: No ACK'd transactions since bit was last..,1: Indicates a transaction ended with an ACK" newline bitfld.long 0x00 0.--2. "DATA_COUNT_MSB,These bits are the 3 MSb bits of an 11-bit counter" "0,1,2,3,4,5,6,7" group.long 0x34++0x03 line.long 0x00 "SIE_EP1_CNT1,Non-control endpoint count register" hexmask.long.byte 0x00 0.--7. 1. "DATA_COUNT,These bits are the 8 LSb of a 11-bit counter" group.long 0x38++0x03 line.long 0x00 "SIE_EP1_CR0,Non-control endpoint's control Register" bitfld.long 0x00 7. "STALL,When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT" "0,1" newline bitfld.long 0x00 6. "ERR_IN_TXN,The Error in transaction bit is set whenever an error is detected" "0,1" newline bitfld.long 0x00 5. "NAK_INT_EN,When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK" "0,1" newline bitfld.long 0x00 4. "ACKED_TXN,The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet" "0: No ACK'd transactions since bit was last..,1: Indicates a transaction ended with an ACK" newline bitfld.long 0x00 0.--3. "MODE,The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint" "0: Ignore all USB traffic to this endpoint,1: SETUP,2: SETUP,3: SETUP,?,5: SETUP,6: SETUP,7: SETUP,8: SETUP,9: SETUP,?,11: SETUP,12: SETUP,13: SETUP,?,15: SETUP" group.long 0x40++0x03 line.long 0x00 "USBIO_CR0,USBIO Control 0 Register" bitfld.long 0x00 7. "TEN,USB Transmit Enable" "0,1" newline bitfld.long 0x00 6. "TSE0,Transmit Single-Ended Zero" "0,1" newline bitfld.long 0x00 5. "TD,Transmit Data" "0: Force USB K state (D+ is low D- is high),1: Force USB J state (D+ is high D- is low)" newline rbitfld.long 0x00 0. "RD,Received Data" "0: D+ < D- (K state) or D+=D-=0 (SE0),1: D+ > D- (J state)" group.long 0x44++0x03 line.long 0x00 "USBIO_CR2,USBIO control 2 Register" bitfld.long 0x00 7. "TEST_RES,This bit is for testing the non-passthrough suspend mode pull up" "0,1" newline bitfld.long 0x00 6. "TEST_PKT,This bit enables the device to transmit a packet in response to an internally generated IN packet" "0,1" newline rbitfld.long 0x00 0.--5. "RSVD,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x48++0x03 line.long 0x00 "USBIO_CR1,USBIO control 1 Register" bitfld.long 0x00 5. "IOMODE,This bit allows the D+ and D- pins to be configured for either USB mode or bit-banged modes" "0,1" newline bitfld.long 0x00 2. "USBPUEN,This bit enables the connection of the internal 1.5 k pull up resistor on the D+ pin" "0,1" newline rbitfld.long 0x00 1. "DPO,This read only bit gives the state of the D+ pin" "0,1" newline rbitfld.long 0x00 0. "DMO,This read only bit gives the state of the D- pin" "0,1" group.long 0x50++0x03 line.long 0x00 "DYN_RECONFIG,USB Dynamic reconfiguration register" rbitfld.long 0x00 4. "DYN_RECONFIG_RDY_STS,This bit indicates the ready status for the dynamic reconfiguration when set to 1 indicates the block is ready for reconfiguration" "0,1" newline bitfld.long 0x00 1.--3. "DYN_RECONFIG_EPNO,These bits indicates the EP number for which reconfiguration is required when dyn_config_en bit is set to 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0. "DYN_CONFIG_EN,This bit is used to enable the dynamic re-configuration for the selected EP" "0,1" rgroup.long 0x60++0x03 line.long 0x00 "SOF0,Start Of Frame Register" hexmask.long.byte 0x00 0.--7. 1. "FRAME_NUMBER,It has the lower 8 bits [7:0] of the SOF frame number" rgroup.long 0x64++0x03 line.long 0x00 "SOF1,Start Of Frame Register" bitfld.long 0x00 0.--2. "FRAME_NUMBER_MSB,It has the upper 3 bits [10:8] of the SOF frame number" "0,1,2,3,4,5,6,7" group.long 0x70++0x03 line.long 0x00 "SIE_EP2_CNT0,Non-control endpoint count register" bitfld.long 0x00 7. "DATA_TOGGLE,This bit selects the DATA packet's toggle state" "0,1" newline bitfld.long 0x00 6. "DATA_VALID,This bit is used for OUT transactions only and is read only" "0: No ACK'd transactions since bit was last..,1: Indicates a transaction ended with an ACK" newline bitfld.long 0x00 0.--2. "DATA_COUNT_MSB,These bits are the 3 MSb bits of an 11-bit counter" "0,1,2,3,4,5,6,7" group.long 0x74++0x03 line.long 0x00 "SIE_EP2_CNT1,Non-control endpoint count register" hexmask.long.byte 0x00 0.--7. 1. "DATA_COUNT,These bits are the 8 LSb of a 11-bit counter" group.long 0x78++0x03 line.long 0x00 "SIE_EP2_CR0,Non-control endpoint's control Register" bitfld.long 0x00 7. "STALL,When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT" "0,1" newline bitfld.long 0x00 6. "ERR_IN_TXN,The Error in transaction bit is set whenever an error is detected" "0,1" newline bitfld.long 0x00 5. "NAK_INT_EN,When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK" "0,1" newline bitfld.long 0x00 4. "ACKED_TXN,The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet" "0: No ACK'd transactions since bit was last..,1: Indicates a transaction ended with an ACK" newline bitfld.long 0x00 0.--3. "MODE,The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint" "0: Ignore all USB traffic to this endpoint,1: SETUP,2: SETUP,3: SETUP,?,5: SETUP,6: SETUP,7: SETUP,8: SETUP,9: SETUP,?,11: SETUP,12: SETUP,13: SETUP,?,15: SETUP" rgroup.long 0x80++0x03 line.long 0x00 "OSCLK_DR0,Oscillator lock data register 0" hexmask.long.byte 0x00 0.--7. 1. "ADDER,These bits return the lower 8 bits of the oscillator locking circuits adder output" rgroup.long 0x84++0x03 line.long 0x00 "OSCLK_DR1,Oscillator lock data register 1" hexmask.long.byte 0x00 0.--6. 1. "ADDER_MSB,These bits return the upper 7 bits of the oscillator locking circuits adder output" group.long 0xA0++0x03 line.long 0x00 "EP0_CR,Endpoint0 control Register" bitfld.long 0x00 7. "SETUP_RCVD,When set this bit indicates a valid SETUP packet was received and ACKed" "0,1" newline bitfld.long 0x00 6. "IN_RCVD,When set this bit indicates a valid IN packet has been received" "0,1" newline bitfld.long 0x00 5. "OUT_RCVD,When set this bit indicates a valid OUT packet has been received and ACKed" "0,1" newline bitfld.long 0x00 4. "ACKED_TXN,The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet" "0: No ACK'd transactions since bit was last..,1: Indicates a transaction ended with an ACK" newline bitfld.long 0x00 0.--3. "MODE,The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint" "0: Ignore all USB traffic to this endpoint,1: SETUP,2: SETUP,3: SETUP,?,5: SETUP,6: SETUP,7: SETUP,8: SETUP,9: SETUP,?,11: SETUP,12: SETUP,13: SETUP,?,15: SETUP" group.long 0xA4++0x03 line.long 0x00 "EP0_CNT,Endpoint0 count Register" bitfld.long 0x00 7. "DATA_TOGGLE,This bit selects the DATA packet's toggle state" "0,1" newline bitfld.long 0x00 6. "DATA_VALID,This bit is used for OUT/SETUP transactions only and is read only" "0: No ACK'd transactions since bit was last..,1: Indicates a transaction ended with an ACK" newline bitfld.long 0x00 0.--3. "BYTE_COUNT,These bits indicate the number of data bytes in a transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xB0++0x03 line.long 0x00 "SIE_EP3_CNT0,Non-control endpoint count register" bitfld.long 0x00 7. "DATA_TOGGLE,This bit selects the DATA packet's toggle state" "0,1" newline bitfld.long 0x00 6. "DATA_VALID,This bit is used for OUT transactions only and is read only" "0: No ACK'd transactions since bit was last..,1: Indicates a transaction ended with an ACK" newline bitfld.long 0x00 0.--2. "DATA_COUNT_MSB,These bits are the 3 MSb bits of an 11-bit counter" "0,1,2,3,4,5,6,7" group.long 0xB4++0x03 line.long 0x00 "SIE_EP3_CNT1,Non-control endpoint count register" hexmask.long.byte 0x00 0.--7. 1. "DATA_COUNT,These bits are the 8 LSb of a 11-bit counter" group.long 0xB8++0x03 line.long 0x00 "SIE_EP3_CR0,Non-control endpoint's control Register" bitfld.long 0x00 7. "STALL,When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT" "0,1" newline bitfld.long 0x00 6. "ERR_IN_TXN,The Error in transaction bit is set whenever an error is detected" "0,1" newline bitfld.long 0x00 5. "NAK_INT_EN,When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK" "0,1" newline bitfld.long 0x00 4. "ACKED_TXN,The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet" "0: No ACK'd transactions since bit was last..,1: Indicates a transaction ended with an ACK" newline bitfld.long 0x00 0.--3. "MODE,The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint" "0: Ignore all USB traffic to this endpoint,1: SETUP,2: SETUP,3: SETUP,?,5: SETUP,6: SETUP,7: SETUP,8: SETUP,9: SETUP,?,11: SETUP,12: SETUP,13: SETUP,?,15: SETUP" group.long 0xF0++0x03 line.long 0x00 "SIE_EP4_CNT0,Non-control endpoint count register" bitfld.long 0x00 7. "DATA_TOGGLE,This bit selects the DATA packet's toggle state" "0,1" newline bitfld.long 0x00 6. "DATA_VALID,This bit is used for OUT transactions only and is read only" "0: No ACK'd transactions since bit was last..,1: Indicates a transaction ended with an ACK" newline bitfld.long 0x00 0.--2. "DATA_COUNT_MSB,These bits are the 3 MSb bits of an 11-bit counter" "0,1,2,3,4,5,6,7" group.long 0xF4++0x03 line.long 0x00 "SIE_EP4_CNT1,Non-control endpoint count register" hexmask.long.byte 0x00 0.--7. 1. "DATA_COUNT,These bits are the 8 LSb of a 11-bit counter" group.long 0xF8++0x03 line.long 0x00 "SIE_EP4_CR0,Non-control endpoint's control Register" bitfld.long 0x00 7. "STALL,When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT" "0,1" newline bitfld.long 0x00 6. "ERR_IN_TXN,The Error in transaction bit is set whenever an error is detected" "0,1" newline bitfld.long 0x00 5. "NAK_INT_EN,When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK" "0,1" newline bitfld.long 0x00 4. "ACKED_TXN,The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet" "0: No ACK'd transactions since bit was last..,1: Indicates a transaction ended with an ACK" newline bitfld.long 0x00 0.--3. "MODE,The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint" "0: Ignore all USB traffic to this endpoint,1: SETUP,2: SETUP,3: SETUP,?,5: SETUP,6: SETUP,7: SETUP,8: SETUP,9: SETUP,?,11: SETUP,12: SETUP,13: SETUP,?,15: SETUP" group.long 0x130++0x03 line.long 0x00 "SIE_EP5_CNT0,Non-control endpoint count register" bitfld.long 0x00 7. "DATA_TOGGLE,This bit selects the DATA packet's toggle state" "0,1" newline bitfld.long 0x00 6. "DATA_VALID,This bit is used for OUT transactions only and is read only" "0: No ACK'd transactions since bit was last..,1: Indicates a transaction ended with an ACK" newline bitfld.long 0x00 0.--2. "DATA_COUNT_MSB,These bits are the 3 MSb bits of an 11-bit counter" "0,1,2,3,4,5,6,7" group.long 0x134++0x03 line.long 0x00 "SIE_EP5_CNT1,Non-control endpoint count register" hexmask.long.byte 0x00 0.--7. 1. "DATA_COUNT,These bits are the 8 LSb of a 11-bit counter" group.long 0x138++0x03 line.long 0x00 "SIE_EP5_CR0,Non-control endpoint's control Register" bitfld.long 0x00 7. "STALL,When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT" "0,1" newline bitfld.long 0x00 6. "ERR_IN_TXN,The Error in transaction bit is set whenever an error is detected" "0,1" newline bitfld.long 0x00 5. "NAK_INT_EN,When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK" "0,1" newline bitfld.long 0x00 4. "ACKED_TXN,The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet" "0: No ACK'd transactions since bit was last..,1: Indicates a transaction ended with an ACK" newline bitfld.long 0x00 0.--3. "MODE,The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint" "0: Ignore all USB traffic to this endpoint,1: SETUP,2: SETUP,3: SETUP,?,5: SETUP,6: SETUP,7: SETUP,8: SETUP,9: SETUP,?,11: SETUP,12: SETUP,13: SETUP,?,15: SETUP" group.long 0x170++0x03 line.long 0x00 "SIE_EP6_CNT0,Non-control endpoint count register" bitfld.long 0x00 7. "DATA_TOGGLE,This bit selects the DATA packet's toggle state" "0,1" newline bitfld.long 0x00 6. "DATA_VALID,This bit is used for OUT transactions only and is read only" "0: No ACK'd transactions since bit was last..,1: Indicates a transaction ended with an ACK" newline bitfld.long 0x00 0.--2. "DATA_COUNT_MSB,These bits are the 3 MSb bits of an 11-bit counter" "0,1,2,3,4,5,6,7" group.long 0x174++0x03 line.long 0x00 "SIE_EP6_CNT1,Non-control endpoint count register" hexmask.long.byte 0x00 0.--7. 1. "DATA_COUNT,These bits are the 8 LSb of a 11-bit counter" group.long 0x178++0x03 line.long 0x00 "SIE_EP6_CR0,Non-control endpoint's control Register" bitfld.long 0x00 7. "STALL,When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT" "0,1" newline bitfld.long 0x00 6. "ERR_IN_TXN,The Error in transaction bit is set whenever an error is detected" "0,1" newline bitfld.long 0x00 5. "NAK_INT_EN,When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK" "0,1" newline bitfld.long 0x00 4. "ACKED_TXN,The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet" "0: No ACK'd transactions since bit was last..,1: Indicates a transaction ended with an ACK" newline bitfld.long 0x00 0.--3. "MODE,The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint" "0: Ignore all USB traffic to this endpoint,1: SETUP,2: SETUP,3: SETUP,?,5: SETUP,6: SETUP,7: SETUP,8: SETUP,9: SETUP,?,11: SETUP,12: SETUP,13: SETUP,?,15: SETUP" group.long 0x1B0++0x03 line.long 0x00 "SIE_EP7_CNT0,Non-control endpoint count register" bitfld.long 0x00 7. "DATA_TOGGLE,This bit selects the DATA packet's toggle state" "0,1" newline bitfld.long 0x00 6. "DATA_VALID,This bit is used for OUT transactions only and is read only" "0: No ACK'd transactions since bit was last..,1: Indicates a transaction ended with an ACK" newline bitfld.long 0x00 0.--2. "DATA_COUNT_MSB,These bits are the 3 MSb bits of an 11-bit counter" "0,1,2,3,4,5,6,7" group.long 0x1B4++0x03 line.long 0x00 "SIE_EP7_CNT1,Non-control endpoint count register" hexmask.long.byte 0x00 0.--7. 1. "DATA_COUNT,These bits are the 8 LSb of a 11-bit counter" group.long 0x1B8++0x03 line.long 0x00 "SIE_EP7_CR0,Non-control endpoint's control Register" bitfld.long 0x00 7. "STALL,When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT" "0,1" newline bitfld.long 0x00 6. "ERR_IN_TXN,The Error in transaction bit is set whenever an error is detected" "0,1" newline bitfld.long 0x00 5. "NAK_INT_EN,When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK" "0,1" newline bitfld.long 0x00 4. "ACKED_TXN,The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet" "0: No ACK'd transactions since bit was last..,1: Indicates a transaction ended with an ACK" newline bitfld.long 0x00 0.--3. "MODE,The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint" "0: Ignore all USB traffic to this endpoint,1: SETUP,2: SETUP,3: SETUP,?,5: SETUP,6: SETUP,7: SETUP,8: SETUP,9: SETUP,?,11: SETUP,12: SETUP,13: SETUP,?,15: SETUP" group.long 0x1F0++0x03 line.long 0x00 "SIE_EP8_CNT0,Non-control endpoint count register" bitfld.long 0x00 7. "DATA_TOGGLE,This bit selects the DATA packet's toggle state" "0,1" newline bitfld.long 0x00 6. "DATA_VALID,This bit is used for OUT transactions only and is read only" "0: No ACK'd transactions since bit was last..,1: Indicates a transaction ended with an ACK" newline bitfld.long 0x00 0.--2. "DATA_COUNT_MSB,These bits are the 3 MSb bits of an 11-bit counter" "0,1,2,3,4,5,6,7" group.long 0x1F4++0x03 line.long 0x00 "SIE_EP8_CNT1,Non-control endpoint count register" hexmask.long.byte 0x00 0.--7. 1. "DATA_COUNT,These bits are the 8 LSb of a 11-bit counter" group.long 0x1F8++0x03 line.long 0x00 "SIE_EP8_CR0,Non-control endpoint's control Register" bitfld.long 0x00 7. "STALL,When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT" "0,1" newline bitfld.long 0x00 6. "ERR_IN_TXN,The Error in transaction bit is set whenever an error is detected" "0,1" newline bitfld.long 0x00 5. "NAK_INT_EN,When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK" "0,1" newline bitfld.long 0x00 4. "ACKED_TXN,The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet" "0: No ACK'd transactions since bit was last..,1: Indicates a transaction ended with an ACK" newline bitfld.long 0x00 0.--3. "MODE,The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint" "0: Ignore all USB traffic to this endpoint,1: SETUP,2: SETUP,3: SETUP,?,5: SETUP,6: SETUP,7: SETUP,8: SETUP,9: SETUP,?,11: SETUP,12: SETUP,13: SETUP,?,15: SETUP" group.long 0x200++0x03 line.long 0x00 "ARB_EP1_CFG,Endpoint Configuration Register" bitfld.long 0x00 3. "RESET_PTR,Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction" "0: Do not Reset Pointer Krypton Backward..,1: Reset Pointer recommended value for reduction.." newline bitfld.long 0x00 2. "CRC_BYPASS,Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware" "0: No CRC bypass CRC bytes will be written to..,1: CRC Bypass Set CRC bytes will not be written.." newline bitfld.long 0x00 1. "DMA_REQ,Manual DMA Request for a particular (1 to 8) endpoint changing this field from 0 to 1 causes a DMA request to be generated" "0,1" newline bitfld.long 0x00 0. "IN_DATA_RDY,Indication that Endpoint Packet Data is Ready in Main memory" "0,1" group.long 0x204++0x03 line.long 0x00 "ARB_EP1_INT_EN,Endpoint Interrupt Enable Register" bitfld.long 0x00 5. "DMA_TERMIN_EN,Endpoint DMA Terminated Enable" "0,1" newline bitfld.long 0x00 4. "ERR_INT_EN,Endpoint Error in Transaction Interrupt Enable" "0,1" newline bitfld.long 0x00 3. "BUF_UNDER_EN,Endpoint Buffer Underflow Enable" "0,1" newline bitfld.long 0x00 2. "BUF_OVER_EN,Endpoint Buffer Overflow Enable" "0,1" newline bitfld.long 0x00 1. "DMA_GNT_EN,Endpoint DMA Grant Enable" "0,1" newline bitfld.long 0x00 0. "IN_BUF_FULL_EN,IN Endpoint Local Buffer Full Enable" "0,1" group.long 0x208++0x03 line.long 0x00 "ARB_EP1_SR,Endpoint Interrupt Enable Register" bitfld.long 0x00 5. "DMA_TERMIN,Endpoint DMA Terminated Interrupt" "0,1" newline bitfld.long 0x00 3. "BUF_UNDER,Endpoint Buffer Underflow Interrupt" "0,1" newline bitfld.long 0x00 2. "BUF_OVER,Endpoint Buffer Overflow Interrupt" "0,1" newline bitfld.long 0x00 1. "DMA_GNT,Endpoint DMA Grant Interrupt" "0,1" newline bitfld.long 0x00 0. "IN_BUF_FULL,IN Endpoint Local Buffer Full Interrupt" "0,1" group.long 0x210++0x03 line.long 0x00 "ARB_RW1_WA,Endpoint Write Address value" hexmask.long.byte 0x00 0.--7. 1. "WA,Write Address for EP" group.long 0x214++0x03 line.long 0x00 "ARB_RW1_WA_MSB,Endpoint Write Address value" bitfld.long 0x00 0. "WA_MSB,Write Address for EP" "0,1" group.long 0x218++0x03 line.long 0x00 "ARB_RW1_RA,Endpoint Read Address value" hexmask.long.byte 0x00 0.--7. 1. "RA,Read Address for EP" group.long 0x21C++0x03 line.long 0x00 "ARB_RW1_RA_MSB,Endpoint Read Address value" bitfld.long 0x00 0. "RA_MSB,Read Address for EP" "0,1" group.long 0x220++0x03 line.long 0x00 "ARB_RW1_DR,Endpoint Data Register" hexmask.long.byte 0x00 0.--7. 1. "DR,Data Register for EP This register is linked to the memory hence reset value is undefined" group.long 0x230++0x03 line.long 0x00 "BUF_SIZE,Dedicated Endpoint Buffer Size Register" bitfld.long 0x00 4.--7. "OUT_BUF,Buffer size for OUT Endpoints" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "IN_BUF,Buffer size for IN Endpoints" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x238++0x03 line.long 0x00 "EP_ACTIVE,Endpoint Active Indication Register" bitfld.long 0x00 7. "EP8_ACT,Indicates that Endpoint is currently active" "0,1" newline bitfld.long 0x00 6. "EP7_ACT,Indicates that Endpoint is currently active" "0,1" newline bitfld.long 0x00 5. "EP6_ACT,Indicates that Endpoint is currently active" "0,1" newline bitfld.long 0x00 4. "EP5_ACT,Indicates that Endpoint is currently active" "0,1" newline bitfld.long 0x00 3. "EP4_ACT,Indicates that Endpoint is currently active" "0,1" newline bitfld.long 0x00 2. "EP3_ACT,Indicates that Endpoint is currently active" "0,1" newline bitfld.long 0x00 1. "EP2_ACT,Indicates that Endpoint is currently active" "0,1" newline bitfld.long 0x00 0. "EP1_ACT,Indicates that Endpoint is currently active" "0,1" group.long 0x23C++0x03 line.long 0x00 "EP_TYPE,Endpoint Type (IN/OUT) Indication" bitfld.long 0x00 7. "EP8_TYP,Endpoint Type Indication" "0: IN outpoint,1: OUT outpoint" newline bitfld.long 0x00 6. "EP7_TYP,Endpoint Type Indication" "0: IN outpoint,1: OUT outpoint" newline bitfld.long 0x00 5. "EP6_TYP,Endpoint Type Indication" "0: IN outpoint,1: OUT outpoint" newline bitfld.long 0x00 4. "EP5_TYP,Endpoint Type Indication" "0: IN outpoint,1: OUT outpoint" newline bitfld.long 0x00 3. "EP4_TYP,Endpoint Type Indication" "0: IN outpoint,1: OUT outpoint" newline bitfld.long 0x00 2. "EP3_TYP,Endpoint Type Indication" "0: IN outpoint,1: OUT outpoint" newline bitfld.long 0x00 1. "EP2_TYP,Endpoint Type Indication" "0: IN outpoint,1: OUT outpoint" newline bitfld.long 0x00 0. "EP1_TYP,Endpoint Type Indication" "0: IN outpoint,1: OUT outpoint" group.long 0x240++0x03 line.long 0x00 "ARB_EP2_CFG,Endpoint Configuration Register" bitfld.long 0x00 3. "RESET_PTR,Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction" "0: Do not Reset Pointer Krypton Backward..,1: Reset Pointer recommended value for reduction.." newline bitfld.long 0x00 2. "CRC_BYPASS,Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware" "0: No CRC bypass CRC bytes will be written to..,1: CRC Bypass Set CRC bytes will not be written.." newline bitfld.long 0x00 1. "DMA_REQ,Manual DMA Request for a particular (1 to 8) endpoint changing this field from 0 to 1 causes a DMA request to be generated" "0,1" newline bitfld.long 0x00 0. "IN_DATA_RDY,Indication that Endpoint Packet Data is Ready in Main memory" "0,1" group.long 0x244++0x03 line.long 0x00 "ARB_EP2_INT_EN,Endpoint Interrupt Enable Register" bitfld.long 0x00 5. "DMA_TERMIN_EN,Endpoint DMA Terminated Enable" "0,1" newline bitfld.long 0x00 4. "ERR_INT_EN,Endpoint Error in Transaction Interrupt Enable" "0,1" newline bitfld.long 0x00 3. "BUF_UNDER_EN,Endpoint Buffer Underflow Enable" "0,1" newline bitfld.long 0x00 2. "BUF_OVER_EN,Endpoint Buffer Overflow Enable" "0,1" newline bitfld.long 0x00 1. "DMA_GNT_EN,Endpoint DMA Grant Enable" "0,1" newline bitfld.long 0x00 0. "IN_BUF_FULL_EN,IN Endpoint Local Buffer Full Enable" "0,1" group.long 0x248++0x03 line.long 0x00 "ARB_EP2_SR,Endpoint Interrupt Enable Register" bitfld.long 0x00 5. "DMA_TERMIN,Endpoint DMA Terminated Interrupt" "0,1" newline bitfld.long 0x00 3. "BUF_UNDER,Endpoint Buffer Underflow Interrupt" "0,1" newline bitfld.long 0x00 2. "BUF_OVER,Endpoint Buffer Overflow Interrupt" "0,1" newline bitfld.long 0x00 1. "DMA_GNT,Endpoint DMA Grant Interrupt" "0,1" newline bitfld.long 0x00 0. "IN_BUF_FULL,IN Endpoint Local Buffer Full Interrupt" "0,1" group.long 0x250++0x03 line.long 0x00 "ARB_RW2_WA,Endpoint Write Address value" hexmask.long.byte 0x00 0.--7. 1. "WA,Write Address for EP" group.long 0x254++0x03 line.long 0x00 "ARB_RW2_WA_MSB,Endpoint Write Address value" bitfld.long 0x00 0. "WA_MSB,Write Address for EP" "0,1" group.long 0x258++0x03 line.long 0x00 "ARB_RW2_RA,Endpoint Read Address value" hexmask.long.byte 0x00 0.--7. 1. "RA,Read Address for EP" group.long 0x25C++0x03 line.long 0x00 "ARB_RW2_RA_MSB,Endpoint Read Address value" bitfld.long 0x00 0. "RA_MSB,Read Address for EP" "0,1" group.long 0x260++0x03 line.long 0x00 "ARB_RW2_DR,Endpoint Data Register" hexmask.long.byte 0x00 0.--7. 1. "DR,Data Register for EP This register is linked to the memory hence reset value is undefined" group.long 0x270++0x03 line.long 0x00 "ARB_CFG,Arbiter Configuration Register" bitfld.long 0x00 7. "CFG_CMP,Register Configuration Complete Indication" "0,1" newline bitfld.long 0x00 5.--6. "DMA_CFG,DMA Access Configuration" "0: DMA_NONE,1: DMA_MANUAL,2: DMA_AUTO,?..." newline bitfld.long 0x00 4. "AUTO_MEM,Enables Auto Memory Configuration" "0,1" group.long 0x274++0x03 line.long 0x00 "USB_CLK_EN,USB Block Clock Enable Register" bitfld.long 0x00 0. "CSR_CLK_EN,Clock Enable for Core Logic clocked by AHB bus clock" "0,1" group.long 0x278++0x03 line.long 0x00 "ARB_INT_EN,Arbiter Interrupt Enable" bitfld.long 0x00 7. "EP8_INTR_EN,Enables interrupt for EP8" "0,1" newline bitfld.long 0x00 6. "EP7_INTR_EN,Enables interrupt for EP7" "0,1" newline bitfld.long 0x00 5. "EP6_INTR_EN,Enables interrupt for EP6" "0,1" newline bitfld.long 0x00 4. "EP5_INTR_EN,Enables interrupt for EP5" "0,1" newline bitfld.long 0x00 3. "EP4_INTR_EN,Enables interrupt for EP4" "0,1" newline bitfld.long 0x00 2. "EP3_INTR_EN,Enables interrupt for EP3" "0,1" newline bitfld.long 0x00 1. "EP2_INTR_EN,Enables interrupt for EP2" "0,1" newline bitfld.long 0x00 0. "EP1_INTR_EN,Enables interrupt for EP1" "0,1" rgroup.long 0x27C++0x03 line.long 0x00 "ARB_INT_SR,Arbiter Interrupt Status" bitfld.long 0x00 7. "EP8_INTR,Interrupt status for EP8" "0,1" newline bitfld.long 0x00 6. "EP7_INTR,Interrupt status for EP7" "0,1" newline bitfld.long 0x00 5. "EP6_INTR,Interrupt status for EP6" "0,1" newline bitfld.long 0x00 4. "EP5_INTR,Interrupt status for EP5" "0,1" newline bitfld.long 0x00 3. "EP4_INTR,Interrupt status for EP4" "0,1" newline bitfld.long 0x00 2. "EP3_INTR,Interrupt status for EP3" "0,1" newline bitfld.long 0x00 1. "EP2_INTR,Interrupt status for EP2" "0,1" newline bitfld.long 0x00 0. "EP1_INTR,Interrupt status for EP1" "0,1" group.long 0x280++0x03 line.long 0x00 "ARB_EP3_CFG,Endpoint Configuration Register" bitfld.long 0x00 3. "RESET_PTR,Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction" "0: Do not Reset Pointer Krypton Backward..,1: Reset Pointer recommended value for reduction.." newline bitfld.long 0x00 2. "CRC_BYPASS,Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware" "0: No CRC bypass CRC bytes will be written to..,1: CRC Bypass Set CRC bytes will not be written.." newline bitfld.long 0x00 1. "DMA_REQ,Manual DMA Request for a particular (1 to 8) endpoint changing this field from 0 to 1 causes a DMA request to be generated" "0,1" newline bitfld.long 0x00 0. "IN_DATA_RDY,Indication that Endpoint Packet Data is Ready in Main memory" "0,1" group.long 0x284++0x03 line.long 0x00 "ARB_EP3_INT_EN,Endpoint Interrupt Enable Register" bitfld.long 0x00 5. "DMA_TERMIN_EN,Endpoint DMA Terminated Enable" "0,1" newline bitfld.long 0x00 4. "ERR_INT_EN,Endpoint Error in Transaction Interrupt Enable" "0,1" newline bitfld.long 0x00 3. "BUF_UNDER_EN,Endpoint Buffer Underflow Enable" "0,1" newline bitfld.long 0x00 2. "BUF_OVER_EN,Endpoint Buffer Overflow Enable" "0,1" newline bitfld.long 0x00 1. "DMA_GNT_EN,Endpoint DMA Grant Enable" "0,1" newline bitfld.long 0x00 0. "IN_BUF_FULL_EN,IN Endpoint Local Buffer Full Enable" "0,1" group.long 0x288++0x03 line.long 0x00 "ARB_EP3_SR,Endpoint Interrupt Enable Register" bitfld.long 0x00 5. "DMA_TERMIN,Endpoint DMA Terminated Interrupt" "0,1" newline bitfld.long 0x00 3. "BUF_UNDER,Endpoint Buffer Underflow Interrupt" "0,1" newline bitfld.long 0x00 2. "BUF_OVER,Endpoint Buffer Overflow Interrupt" "0,1" newline bitfld.long 0x00 1. "DMA_GNT,Endpoint DMA Grant Interrupt" "0,1" newline bitfld.long 0x00 0. "IN_BUF_FULL,IN Endpoint Local Buffer Full Interrupt" "0,1" group.long 0x290++0x03 line.long 0x00 "ARB_RW3_WA,Endpoint Write Address value" hexmask.long.byte 0x00 0.--7. 1. "WA,Write Address for EP" group.long 0x294++0x03 line.long 0x00 "ARB_RW3_WA_MSB,Endpoint Write Address value" bitfld.long 0x00 0. "WA_MSB,Write Address for EP" "0,1" group.long 0x298++0x03 line.long 0x00 "ARB_RW3_RA,Endpoint Read Address value" hexmask.long.byte 0x00 0.--7. 1. "RA,Read Address for EP" group.long 0x29C++0x03 line.long 0x00 "ARB_RW3_RA_MSB,Endpoint Read Address value" bitfld.long 0x00 0. "RA_MSB,Read Address for EP" "0,1" group.long 0x2A0++0x03 line.long 0x00 "ARB_RW3_DR,Endpoint Data Register" hexmask.long.byte 0x00 0.--7. 1. "DR,Data Register for EP This register is linked to the memory hence reset value is undefined" group.long 0x2B0++0x03 line.long 0x00 "CWA,Common Area Write Address" hexmask.long.byte 0x00 0.--7. 1. "CWA,Write Address for Common Area" group.long 0x2B4++0x03 line.long 0x00 "CWA_MSB,Endpoint Read Address value" bitfld.long 0x00 0. "CWA_MSB,Write Address for Common Area" "0,1" group.long 0x2C0++0x03 line.long 0x00 "ARB_EP4_CFG,Endpoint Configuration Register" bitfld.long 0x00 3. "RESET_PTR,Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction" "0: Do not Reset Pointer Krypton Backward..,1: Reset Pointer recommended value for reduction.." newline bitfld.long 0x00 2. "CRC_BYPASS,Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware" "0: No CRC bypass CRC bytes will be written to..,1: CRC Bypass Set CRC bytes will not be written.." newline bitfld.long 0x00 1. "DMA_REQ,Manual DMA Request for a particular (1 to 8) endpoint changing this field from 0 to 1 causes a DMA request to be generated" "0,1" newline bitfld.long 0x00 0. "IN_DATA_RDY,Indication that Endpoint Packet Data is Ready in Main memory" "0,1" group.long 0x2C4++0x03 line.long 0x00 "ARB_EP4_INT_EN,Endpoint Interrupt Enable Register" bitfld.long 0x00 5. "DMA_TERMIN_EN,Endpoint DMA Terminated Enable" "0,1" newline bitfld.long 0x00 4. "ERR_INT_EN,Endpoint Error in Transaction Interrupt Enable" "0,1" newline bitfld.long 0x00 3. "BUF_UNDER_EN,Endpoint Buffer Underflow Enable" "0,1" newline bitfld.long 0x00 2. "BUF_OVER_EN,Endpoint Buffer Overflow Enable" "0,1" newline bitfld.long 0x00 1. "DMA_GNT_EN,Endpoint DMA Grant Enable" "0,1" newline bitfld.long 0x00 0. "IN_BUF_FULL_EN,IN Endpoint Local Buffer Full Enable" "0,1" group.long 0x2C8++0x03 line.long 0x00 "ARB_EP4_SR,Endpoint Interrupt Enable Register" bitfld.long 0x00 5. "DMA_TERMIN,Endpoint DMA Terminated Interrupt" "0,1" newline bitfld.long 0x00 3. "BUF_UNDER,Endpoint Buffer Underflow Interrupt" "0,1" newline bitfld.long 0x00 2. "BUF_OVER,Endpoint Buffer Overflow Interrupt" "0,1" newline bitfld.long 0x00 1. "DMA_GNT,Endpoint DMA Grant Interrupt" "0,1" newline bitfld.long 0x00 0. "IN_BUF_FULL,IN Endpoint Local Buffer Full Interrupt" "0,1" group.long 0x2D0++0x03 line.long 0x00 "ARB_RW4_WA,Endpoint Write Address value" hexmask.long.byte 0x00 0.--7. 1. "WA,Write Address for EP" group.long 0x2D4++0x03 line.long 0x00 "ARB_RW4_WA_MSB,Endpoint Write Address value" bitfld.long 0x00 0. "WA_MSB,Write Address for EP" "0,1" group.long 0x2D8++0x03 line.long 0x00 "ARB_RW4_RA,Endpoint Read Address value" hexmask.long.byte 0x00 0.--7. 1. "RA,Read Address for EP" group.long 0x2DC++0x03 line.long 0x00 "ARB_RW4_RA_MSB,Endpoint Read Address value" bitfld.long 0x00 0. "RA_MSB,Read Address for EP" "0,1" group.long 0x2E0++0x03 line.long 0x00 "ARB_RW4_DR,Endpoint Data Register" hexmask.long.byte 0x00 0.--7. 1. "DR,Data Register for EP This register is linked to the memory hence reset value is undefined" group.long 0x2F0++0x03 line.long 0x00 "DMA_THRES,DMA Burst / Threshold Configuration" hexmask.long.byte 0x00 0.--7. 1. "DMA_THS,DMA Threshold count" group.long 0x2F4++0x03 line.long 0x00 "DMA_THRES_MSB,DMA Burst / Threshold Configuration" bitfld.long 0x00 0. "DMA_THS_MSB,DMA Threshold count" "0,1" group.long 0x300++0x03 line.long 0x00 "ARB_EP5_CFG,Endpoint Configuration Register" bitfld.long 0x00 3. "RESET_PTR,Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction" "0: Do not Reset Pointer Krypton Backward..,1: Reset Pointer recommended value for reduction.." newline bitfld.long 0x00 2. "CRC_BYPASS,Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware" "0: No CRC bypass CRC bytes will be written to..,1: CRC Bypass Set CRC bytes will not be written.." newline bitfld.long 0x00 1. "DMA_REQ,Manual DMA Request for a particular (1 to 8) endpoint changing this field from 0 to 1 causes a DMA request to be generated" "0,1" newline bitfld.long 0x00 0. "IN_DATA_RDY,Indication that Endpoint Packet Data is Ready in Main memory" "0,1" group.long 0x304++0x03 line.long 0x00 "ARB_EP5_INT_EN,Endpoint Interrupt Enable Register" bitfld.long 0x00 5. "DMA_TERMIN_EN,Endpoint DMA Terminated Enable" "0,1" newline bitfld.long 0x00 4. "ERR_INT_EN,Endpoint Error in Transaction Interrupt Enable" "0,1" newline bitfld.long 0x00 3. "BUF_UNDER_EN,Endpoint Buffer Underflow Enable" "0,1" newline bitfld.long 0x00 2. "BUF_OVER_EN,Endpoint Buffer Overflow Enable" "0,1" newline bitfld.long 0x00 1. "DMA_GNT_EN,Endpoint DMA Grant Enable" "0,1" newline bitfld.long 0x00 0. "IN_BUF_FULL_EN,IN Endpoint Local Buffer Full Enable" "0,1" group.long 0x308++0x03 line.long 0x00 "ARB_EP5_SR,Endpoint Interrupt Enable Register" bitfld.long 0x00 5. "DMA_TERMIN,Endpoint DMA Terminated Interrupt" "0,1" newline bitfld.long 0x00 3. "BUF_UNDER,Endpoint Buffer Underflow Interrupt" "0,1" newline bitfld.long 0x00 2. "BUF_OVER,Endpoint Buffer Overflow Interrupt" "0,1" newline bitfld.long 0x00 1. "DMA_GNT,Endpoint DMA Grant Interrupt" "0,1" newline bitfld.long 0x00 0. "IN_BUF_FULL,IN Endpoint Local Buffer Full Interrupt" "0,1" group.long 0x310++0x03 line.long 0x00 "ARB_RW5_WA,Endpoint Write Address value" hexmask.long.byte 0x00 0.--7. 1. "WA,Write Address for EP" group.long 0x314++0x03 line.long 0x00 "ARB_RW5_WA_MSB,Endpoint Write Address value" bitfld.long 0x00 0. "WA_MSB,Write Address for EP" "0,1" group.long 0x318++0x03 line.long 0x00 "ARB_RW5_RA,Endpoint Read Address value" hexmask.long.byte 0x00 0.--7. 1. "RA,Read Address for EP" group.long 0x31C++0x03 line.long 0x00 "ARB_RW5_RA_MSB,Endpoint Read Address value" bitfld.long 0x00 0. "RA_MSB,Read Address for EP" "0,1" group.long 0x320++0x03 line.long 0x00 "ARB_RW5_DR,Endpoint Data Register" hexmask.long.byte 0x00 0.--7. 1. "DR,Data Register for EP This register is linked to the memory hence reset value is undefined" group.long 0x330++0x03 line.long 0x00 "BUS_RST_CNT,Bus Reset Count Register" bitfld.long 0x00 0.--3. "BUS_RST_CNT,Bus Reset Count Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x340++0x03 line.long 0x00 "ARB_EP6_CFG,Endpoint Configuration Register" bitfld.long 0x00 3. "RESET_PTR,Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction" "0: Do not Reset Pointer Krypton Backward..,1: Reset Pointer recommended value for reduction.." newline bitfld.long 0x00 2. "CRC_BYPASS,Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware" "0: No CRC bypass CRC bytes will be written to..,1: CRC Bypass Set CRC bytes will not be written.." newline bitfld.long 0x00 1. "DMA_REQ,Manual DMA Request for a particular (1 to 8) endpoint changing this field from 0 to 1 causes a DMA request to be generated" "0,1" newline bitfld.long 0x00 0. "IN_DATA_RDY,Indication that Endpoint Packet Data is Ready in Main memory" "0,1" group.long 0x344++0x03 line.long 0x00 "ARB_EP6_INT_EN,Endpoint Interrupt Enable Register" bitfld.long 0x00 5. "DMA_TERMIN_EN,Endpoint DMA Terminated Enable" "0,1" newline bitfld.long 0x00 4. "ERR_INT_EN,Endpoint Error in Transaction Interrupt Enable" "0,1" newline bitfld.long 0x00 3. "BUF_UNDER_EN,Endpoint Buffer Underflow Enable" "0,1" newline bitfld.long 0x00 2. "BUF_OVER_EN,Endpoint Buffer Overflow Enable" "0,1" newline bitfld.long 0x00 1. "DMA_GNT_EN,Endpoint DMA Grant Enable" "0,1" newline bitfld.long 0x00 0. "IN_BUF_FULL_EN,IN Endpoint Local Buffer Full Enable" "0,1" group.long 0x348++0x03 line.long 0x00 "ARB_EP6_SR,Endpoint Interrupt Enable Register" bitfld.long 0x00 5. "DMA_TERMIN,Endpoint DMA Terminated Interrupt" "0,1" newline bitfld.long 0x00 3. "BUF_UNDER,Endpoint Buffer Underflow Interrupt" "0,1" newline bitfld.long 0x00 2. "BUF_OVER,Endpoint Buffer Overflow Interrupt" "0,1" newline bitfld.long 0x00 1. "DMA_GNT,Endpoint DMA Grant Interrupt" "0,1" newline bitfld.long 0x00 0. "IN_BUF_FULL,IN Endpoint Local Buffer Full Interrupt" "0,1" group.long 0x350++0x03 line.long 0x00 "ARB_RW6_WA,Endpoint Write Address value" hexmask.long.byte 0x00 0.--7. 1. "WA,Write Address for EP" group.long 0x354++0x03 line.long 0x00 "ARB_RW6_WA_MSB,Endpoint Write Address value" bitfld.long 0x00 0. "WA_MSB,Write Address for EP" "0,1" group.long 0x358++0x03 line.long 0x00 "ARB_RW6_RA,Endpoint Read Address value" hexmask.long.byte 0x00 0.--7. 1. "RA,Read Address for EP" group.long 0x35C++0x03 line.long 0x00 "ARB_RW6_RA_MSB,Endpoint Read Address value" bitfld.long 0x00 0. "RA_MSB,Read Address for EP" "0,1" group.long 0x360++0x03 line.long 0x00 "ARB_RW6_DR,Endpoint Data Register" hexmask.long.byte 0x00 0.--7. 1. "DR,Data Register for EP This register is linked to the memory hence reset value is undefined" group.long 0x380++0x03 line.long 0x00 "ARB_EP7_CFG,Endpoint Configuration Register" bitfld.long 0x00 3. "RESET_PTR,Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction" "0: Do not Reset Pointer Krypton Backward..,1: Reset Pointer recommended value for reduction.." newline bitfld.long 0x00 2. "CRC_BYPASS,Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware" "0: No CRC bypass CRC bytes will be written to..,1: CRC Bypass Set CRC bytes will not be written.." newline bitfld.long 0x00 1. "DMA_REQ,Manual DMA Request for a particular (1 to 8) endpoint changing this field from 0 to 1 causes a DMA request to be generated" "0,1" newline bitfld.long 0x00 0. "IN_DATA_RDY,Indication that Endpoint Packet Data is Ready in Main memory" "0,1" group.long 0x384++0x03 line.long 0x00 "ARB_EP7_INT_EN,Endpoint Interrupt Enable Register" bitfld.long 0x00 5. "DMA_TERMIN_EN,Endpoint DMA Terminated Enable" "0,1" newline bitfld.long 0x00 4. "ERR_INT_EN,Endpoint Error in Transaction Interrupt Enable" "0,1" newline bitfld.long 0x00 3. "BUF_UNDER_EN,Endpoint Buffer Underflow Enable" "0,1" newline bitfld.long 0x00 2. "BUF_OVER_EN,Endpoint Buffer Overflow Enable" "0,1" newline bitfld.long 0x00 1. "DMA_GNT_EN,Endpoint DMA Grant Enable" "0,1" newline bitfld.long 0x00 0. "IN_BUF_FULL_EN,IN Endpoint Local Buffer Full Enable" "0,1" group.long 0x388++0x03 line.long 0x00 "ARB_EP7_SR,Endpoint Interrupt Enable Register" bitfld.long 0x00 5. "DMA_TERMIN,Endpoint DMA Terminated Interrupt" "0,1" newline bitfld.long 0x00 3. "BUF_UNDER,Endpoint Buffer Underflow Interrupt" "0,1" newline bitfld.long 0x00 2. "BUF_OVER,Endpoint Buffer Overflow Interrupt" "0,1" newline bitfld.long 0x00 1. "DMA_GNT,Endpoint DMA Grant Interrupt" "0,1" newline bitfld.long 0x00 0. "IN_BUF_FULL,IN Endpoint Local Buffer Full Interrupt" "0,1" group.long 0x390++0x03 line.long 0x00 "ARB_RW7_WA,Endpoint Write Address value" hexmask.long.byte 0x00 0.--7. 1. "WA,Write Address for EP" group.long 0x394++0x03 line.long 0x00 "ARB_RW7_WA_MSB,Endpoint Write Address value" bitfld.long 0x00 0. "WA_MSB,Write Address for EP" "0,1" group.long 0x398++0x03 line.long 0x00 "ARB_RW7_RA,Endpoint Read Address value" hexmask.long.byte 0x00 0.--7. 1. "RA,Read Address for EP" group.long 0x39C++0x03 line.long 0x00 "ARB_RW7_RA_MSB,Endpoint Read Address value" bitfld.long 0x00 0. "RA_MSB,Read Address for EP" "0,1" group.long 0x3A0++0x03 line.long 0x00 "ARB_RW7_DR,Endpoint Data Register" hexmask.long.byte 0x00 0.--7. 1. "DR,Data Register for EP This register is linked to the memory hence reset value is undefined" group.long 0x3C0++0x03 line.long 0x00 "ARB_EP8_CFG,Endpoint Configuration Register" bitfld.long 0x00 3. "RESET_PTR,Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction" "0: Do not Reset Pointer Krypton Backward..,1: Reset Pointer recommended value for reduction.." newline bitfld.long 0x00 2. "CRC_BYPASS,Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware" "0: No CRC bypass CRC bytes will be written to..,1: CRC Bypass Set CRC bytes will not be written.." newline bitfld.long 0x00 1. "DMA_REQ,Manual DMA Request for a particular (1 to 8) endpoint changing this field from 0 to 1 causes a DMA request to be generated" "0,1" newline bitfld.long 0x00 0. "IN_DATA_RDY,Indication that Endpoint Packet Data is Ready in Main memory" "0,1" group.long 0x3C4++0x03 line.long 0x00 "ARB_EP8_INT_EN,Endpoint Interrupt Enable Register" bitfld.long 0x00 5. "DMA_TERMIN_EN,Endpoint DMA Terminated Enable" "0,1" newline bitfld.long 0x00 4. "ERR_INT_EN,Endpoint Error in Transaction Interrupt Enable" "0,1" newline bitfld.long 0x00 3. "BUF_UNDER_EN,Endpoint Buffer Underflow Enable" "0,1" newline bitfld.long 0x00 2. "BUF_OVER_EN,Endpoint Buffer Overflow Enable" "0,1" newline bitfld.long 0x00 1. "DMA_GNT_EN,Endpoint DMA Grant Enable" "0,1" newline bitfld.long 0x00 0. "IN_BUF_FULL_EN,IN Endpoint Local Buffer Full Enable" "0,1" group.long 0x3C8++0x03 line.long 0x00 "ARB_EP8_SR,Endpoint Interrupt Enable Register" bitfld.long 0x00 5. "DMA_TERMIN,Endpoint DMA Terminated Interrupt" "0,1" newline bitfld.long 0x00 3. "BUF_UNDER,Endpoint Buffer Underflow Interrupt" "0,1" newline bitfld.long 0x00 2. "BUF_OVER,Endpoint Buffer Overflow Interrupt" "0,1" newline bitfld.long 0x00 1. "DMA_GNT,Endpoint DMA Grant Interrupt" "0,1" newline bitfld.long 0x00 0. "IN_BUF_FULL,IN Endpoint Local Buffer Full Interrupt" "0,1" group.long 0x3D0++0x03 line.long 0x00 "ARB_RW8_WA,Endpoint Write Address value" hexmask.long.byte 0x00 0.--7. 1. "WA,Write Address for EP" group.long 0x3D4++0x03 line.long 0x00 "ARB_RW8_WA_MSB,Endpoint Write Address value" bitfld.long 0x00 0. "WA_MSB,Write Address for EP" "0,1" group.long 0x3D8++0x03 line.long 0x00 "ARB_RW8_RA,Endpoint Read Address value" hexmask.long.byte 0x00 0.--7. 1. "RA,Read Address for EP" group.long 0x3DC++0x03 line.long 0x00 "ARB_RW8_RA_MSB,Endpoint Read Address value" bitfld.long 0x00 0. "RA_MSB,Read Address for EP" "0,1" group.long 0x3E0++0x03 line.long 0x00 "ARB_RW8_DR,Endpoint Data Register" hexmask.long.byte 0x00 0.--7. 1. "DR,Data Register for EP This register is linked to the memory hence reset value is undefined" repeat 512. (increment 0 1) (increment 0 0x04) group.long ($2+0x400)++0x03 line.long 0x00 "MEM_DATA[$1],DATA $1" hexmask.long.byte 0x00 0.--7. 1. "DR,Data Register for EP This register is linked to the memory hence reset value is undefined" repeat.end rgroup.long 0x1060++0x03 line.long 0x00 "SOF16,Start Of Frame Register" hexmask.long.word 0x00 0.--10. 1. "FRAME_NUMBER16,The frame number (11b)" rgroup.long 0x1080++0x03 line.long 0x00 "OSCLK_DR16,Oscillator lock data register" hexmask.long.word 0x00 0.--14. 1. "ADDER16,These bits return the oscillator locking circuits adder output" group.long 0x1210++0x03 line.long 0x00 "ARB_RW1_WA16,Endpoint Write Address value" hexmask.long.word 0x00 0.--8. 1. "WA16,Write Address for EP" group.long 0x1218++0x03 line.long 0x00 "ARB_RW1_RA16,Endpoint Read Address value" hexmask.long.word 0x00 0.--8. 1. "RA16,Read Address for EP" group.long 0x1220++0x03 line.long 0x00 "ARB_RW1_DR16,Endpoint Data Register" hexmask.long.word 0x00 0.--15. 1. "DR16,Data Register for EP This register is linked to the memory hence reset value is undefined" group.long 0x1250++0x03 line.long 0x00 "ARB_RW2_WA16,Endpoint Write Address value" hexmask.long.word 0x00 0.--8. 1. "WA16,Write Address for EP" group.long 0x1258++0x03 line.long 0x00 "ARB_RW2_RA16,Endpoint Read Address value" hexmask.long.word 0x00 0.--8. 1. "RA16,Read Address for EP" group.long 0x1260++0x03 line.long 0x00 "ARB_RW2_DR16,Endpoint Data Register" hexmask.long.word 0x00 0.--15. 1. "DR16,Data Register for EP This register is linked to the memory hence reset value is undefined" group.long 0x1290++0x03 line.long 0x00 "ARB_RW3_WA16,Endpoint Write Address value" hexmask.long.word 0x00 0.--8. 1. "WA16,Write Address for EP" group.long 0x1298++0x03 line.long 0x00 "ARB_RW3_RA16,Endpoint Read Address value" hexmask.long.word 0x00 0.--8. 1. "RA16,Read Address for EP" group.long 0x12A0++0x03 line.long 0x00 "ARB_RW3_DR16,Endpoint Data Register" hexmask.long.word 0x00 0.--15. 1. "DR16,Data Register for EP This register is linked to the memory hence reset value is undefined" group.long 0x12B0++0x03 line.long 0x00 "CWA16,Common Area Write Address" hexmask.long.word 0x00 0.--8. 1. "CWA16,Write Address for Common Area" group.long 0x12D0++0x03 line.long 0x00 "ARB_RW4_WA16,Endpoint Write Address value" hexmask.long.word 0x00 0.--8. 1. "WA16,Write Address for EP" group.long 0x12D8++0x03 line.long 0x00 "ARB_RW4_RA16,Endpoint Read Address value" hexmask.long.word 0x00 0.--8. 1. "RA16,Read Address for EP" group.long 0x12E0++0x03 line.long 0x00 "ARB_RW4_DR16,Endpoint Data Register" hexmask.long.word 0x00 0.--15. 1. "DR16,Data Register for EP This register is linked to the memory hence reset value is undefined" group.long 0x12F0++0x03 line.long 0x00 "DMA_THRES16,DMA Burst / Threshold Configuration" hexmask.long.word 0x00 0.--8. 1. "DMA_THS16,DMA Threshold count" group.long 0x1310++0x03 line.long 0x00 "ARB_RW5_WA16,Endpoint Write Address value" hexmask.long.word 0x00 0.--8. 1. "WA16,Write Address for EP" group.long 0x1318++0x03 line.long 0x00 "ARB_RW5_RA16,Endpoint Read Address value" hexmask.long.word 0x00 0.--8. 1. "RA16,Read Address for EP" group.long 0x1320++0x03 line.long 0x00 "ARB_RW5_DR16,Endpoint Data Register" hexmask.long.word 0x00 0.--15. 1. "DR16,Data Register for EP This register is linked to the memory hence reset value is undefined" group.long 0x1350++0x03 line.long 0x00 "ARB_RW6_WA16,Endpoint Write Address value" hexmask.long.word 0x00 0.--8. 1. "WA16,Write Address for EP" group.long 0x1358++0x03 line.long 0x00 "ARB_RW6_RA16,Endpoint Read Address value" hexmask.long.word 0x00 0.--8. 1. "RA16,Read Address for EP" group.long 0x1360++0x03 line.long 0x00 "ARB_RW6_DR16,Endpoint Data Register" hexmask.long.word 0x00 0.--15. 1. "DR16,Data Register for EP This register is linked to the memory hence reset value is undefined" group.long 0x1390++0x03 line.long 0x00 "ARB_RW7_WA16,Endpoint Write Address value" hexmask.long.word 0x00 0.--8. 1. "WA16,Write Address for EP" group.long 0x1398++0x03 line.long 0x00 "ARB_RW7_RA16,Endpoint Read Address value" hexmask.long.word 0x00 0.--8. 1. "RA16,Read Address for EP" group.long 0x13A0++0x03 line.long 0x00 "ARB_RW7_DR16,Endpoint Data Register" hexmask.long.word 0x00 0.--15. 1. "DR16,Data Register for EP This register is linked to the memory hence reset value is undefined" group.long 0x13D0++0x03 line.long 0x00 "ARB_RW8_WA16,Endpoint Write Address value" hexmask.long.word 0x00 0.--8. 1. "WA16,Write Address for EP" group.long 0x13D8++0x03 line.long 0x00 "ARB_RW8_RA16,Endpoint Read Address value" hexmask.long.word 0x00 0.--8. 1. "RA16,Read Address for EP" group.long 0x13E0++0x03 line.long 0x00 "ARB_RW8_DR16,Endpoint Data Register" hexmask.long.word 0x00 0.--15. 1. "DR16,Data Register for EP This register is linked to the memory hence reset value is undefined" tree "BCD" group.long 0x2000++0x03 line.long 0x00 "POWER_CTRL,Power Control Register" bitfld.long 0x00 31. "ENABLE,Mast enable of PHY and Charger Detector" "0,1" newline bitfld.long 0x00 30. "ENABLE_CHGDET,Enables the charger detection circuitry" "0,1" newline bitfld.long 0x00 29. "ENABLE_DMO,Enables the signle ended receiver on D" "0,1" newline bitfld.long 0x00 28. "ENABLE_DPO,Enables the single ended receiver on D+" "0,1" newline bitfld.long 0x00 27. "ENABLE_RCVR,Enables the differential USB receiver" "0,1" newline bitfld.long 0x00 26. "ENABLE_VBUS_PULLDOWN,Enables the weak pull down on the VBUS default on to prevent floating node crow bar currents" "0,1" newline bitfld.long 0x00 25. "ENABLE_DM_PULLDOWN,Enables the ~15k pull down on the DM default off" "0,1" newline bitfld.long 0x00 5.--6. "CHDET_PWR_CTL,Power programmability for bandgap voltage buffer in the charger detect block" "0,1,2,3" newline bitfld.long 0x00 4. "ISOLATE,Isolates the PHY outputs" "0,1" newline bitfld.long 0x00 3. "SUSPEND_DEL,Delayed version of SUSPEND" "0,1" newline bitfld.long 0x00 2. "SUSPEND,Put PHY into Suspend mode" "0,1" newline bitfld.long 0x00 0.--1. "VBUS_VALID_OVR,Overrides the value received from the GPIO input buffer connected to VBUS" "0: Force vbus_valid=0,1: Force vbus_valid=1,2: Use vbus_valid signal from GPIO input,3: Use vbus_valid signal from PHY detector" group.long 0x2004++0x03 line.long 0x00 "CHGDET_CTRL,Charger Detection Control Register" rbitfld.long 0x00 31. "COMP_OUT,Output of the primary/secondary detection comparator" "0,1" newline bitfld.long 0x00 12.--13. "ADFT_CTRL,ADFT option to bring out buffered version of voltage reference input or adft intput to ADFT output (adft_out)" "0: Normal operating mode reference buffer used..,1: Use reference buffer to bring out voltage..,2: Illegal - do not use,3: Use reference buffer to bring out buffered.." newline bitfld.long 0x00 6. "DCD_SRC_EN,Enable the Data Contact Detect current source on D+" "0,1" newline bitfld.long 0x00 5. "REF_EN,Enable the primary/secondary reference driver" "0,1" newline bitfld.long 0x00 4. "REF_DM,Connect the primary/secondary detection reference driver to D" "0,1" newline bitfld.long 0x00 3. "REF_DP,Connect the primary/secondary detection reference driver to D+" "0,1" newline bitfld.long 0x00 2. "COMP_EN,Enable the primary/secondary detection comparator and current sink" "0,1" newline bitfld.long 0x00 1. "COMP_DM,Connect the primary/secondary detection comparator and current sink to D" "0,1" newline bitfld.long 0x00 0. "COMP_DP,Connect the primary/secondary detection comparator and current sink to D+" "0,1" group.long 0x2008++0x03 line.long 0x00 "USBIO_CTRL,USB IO Control Register" bitfld.long 0x00 3.--5. "DM_M,The GPIO Drive Mode for DM IO pad" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--2. "DM_P,The GPIO Drive Mode for DP IO pad" "0: Mode 0,1: Mode 1,2: Mode 2,?,4: Mode 4,?,6: Mode 6,?..." group.long 0x200C++0x03 line.long 0x00 "FLOW_CTRL,Flow Control Register" bitfld.long 0x00 7. "EP8_ERR_RESP,End Point 8 error response" "0,1" newline bitfld.long 0x00 6. "EP7_ERR_RESP,End Point 7 error response" "0,1" newline bitfld.long 0x00 5. "EP6_ERR_RESP,End Point 6 error response" "0,1" newline bitfld.long 0x00 4. "EP5_ERR_RESP,End Point 5 error response" "0,1" newline bitfld.long 0x00 3. "EP4_ERR_RESP,End Point 4 error response" "0,1" newline bitfld.long 0x00 2. "EP3_ERR_RESP,End Point 3 error response" "0,1" newline bitfld.long 0x00 1. "EP2_ERR_RESP,End Point 2 error response" "0,1" newline bitfld.long 0x00 0. "EP1_ERR_RESP,End Point 1 error response" "0: do nothing (backward compatibility mode),1: if this is an IN EP and an underflow occurs.." group.long 0x2010++0x03 line.long 0x00 "LPM_CTRL,LPM Control Register" bitfld.long 0x00 4. "SUB_RESP,Enable a STALL response for all undefined SubPIDs i.e" "0,1" newline bitfld.long 0x00 2. "NYET_EN,Allow firmware to choose which response to use for an LPM token (LPM_EN=1) when the device is NOT ready to go to the requested low power mode (LPM_ACK_RESP=0)" "0: a LPM token will get an NAK response..,1: a LPM token will get a NYET response" newline bitfld.long 0x00 1. "LPM_ACK_RESP,LPM ACK response enable (if LPM_EN=1) to allow firmware to refuse a low power request" "0: a LPM token will get a NYET or NAK (depending..,1: a LPM token will get an ACK response and the" newline bitfld.long 0x00 0. "LPM_EN,LPM enable" "0: Disabled LPM token will not get a response,1: Enable LPM token will get a handshake response" rgroup.long 0x2014++0x03 line.long 0x00 "LPM_STAT,LPM Status register" bitfld.long 0x00 4. "LPM_REMOTEWAKE," "0,1" newline bitfld.long 0x00 0.--3. "LPM_BESL,Best Effort Service Latency This value should match either the Baseline (DeepSleep) or Deep (Hibernate) BESL in the BOS descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2020++0x03 line.long 0x00 "INTR_SIE,USB SOF BUS RESET and EP0 Interrupt Status" bitfld.long 0x00 4. "RESUME_INTR,Interrupt status for Resume" "0,1" newline bitfld.long 0x00 3. "LPM_INTR,Interrupt status for LPM (Link Power Management L1 entry)" "0,1" newline bitfld.long 0x00 2. "EP0_INTR,Interrupt status for EP0" "0,1" newline bitfld.long 0x00 1. "BUS_RESET_INTR,Interrupt status for BUS RESET" "0,1" newline bitfld.long 0x00 0. "SOF_INTR,Interrupt status for USB SOF" "0,1" group.long 0x2024++0x03 line.long 0x00 "INTR_SIE_SET,USB SOF BUS RESET and EP0 Interrupt Set" bitfld.long 0x00 4. "RESUME_INTR_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 3. "LPM_INTR_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 2. "EP0_INTR_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 1. "BUS_RESET_INTR_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 0. "SOF_INTR_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1" group.long 0x2028++0x03 line.long 0x00 "INTR_SIE_MASK,USB SOF BUS RESET and EP0 Interrupt Mask" bitfld.long 0x00 4. "RESUME_INTR_MASK,Set to 1 to enable interrupt corresponding to interrupt request register" "0,1" newline bitfld.long 0x00 3. "LPM_INTR_MASK,Set to 1 to enable interrupt corresponding to interrupt request register" "0,1" newline bitfld.long 0x00 2. "EP0_INTR_MASK,Set to 1 to enable interrupt corresponding to interrupt request register" "0,1" newline bitfld.long 0x00 1. "BUS_RESET_INTR_MASK,Set to 1 to enable interrupt corresponding to interrupt request register" "0,1" newline bitfld.long 0x00 0. "SOF_INTR_MASK,Set to 1 to enable interrupt corresponding to interrupt request register" "0,1" rgroup.long 0x202C++0x03 line.long 0x00 "INTR_SIE_MASKED,USB SOF BUS RESET and EP0 Interrupt Masked" bitfld.long 0x00 4. "RESUME_INTR_MASKED,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 3. "LPM_INTR_MASKED,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 2. "EP0_INTR_MASKED,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 1. "BUS_RESET_INTR_MASKED,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 0. "SOF_INTR_MASKED,Logical and of corresponding request and mask bits" "0,1" group.long 0x2030++0x03 line.long 0x00 "INTR_LVL_SEL,Select interrupt level for each interrupt source" bitfld.long 0x00 30.--31. "EP8_LVL_SEL,EP8 Interrupt level select" "0,1,2,3" newline bitfld.long 0x00 28.--29. "EP7_LVL_SEL,EP7 Interrupt level select" "0,1,2,3" newline bitfld.long 0x00 26.--27. "EP6_LVL_SEL,EP6 Interrupt level select" "0,1,2,3" newline bitfld.long 0x00 24.--25. "EP5_LVL_SEL,EP5 Interrupt level select" "0,1,2,3" newline bitfld.long 0x00 22.--23. "EP4_LVL_SEL,EP4 Interrupt level select" "0,1,2,3" newline bitfld.long 0x00 20.--21. "EP3_LVL_SEL,EP3 Interrupt level select" "0,1,2,3" newline bitfld.long 0x00 18.--19. "EP2_LVL_SEL,EP2 Interrupt level select" "0,1,2,3" newline bitfld.long 0x00 16.--17. "EP1_LVL_SEL,EP1 Interrupt level select" "0,1,2,3" newline bitfld.long 0x00 14.--15. "ARB_EP_LVL_SEL,Arbiter Endpoint Interrupt level select" "0,1,2,3" newline bitfld.long 0x00 8.--9. "RESUME_LVL_SEL,Resume Interrupt level select" "0,1,2,3" newline bitfld.long 0x00 6.--7. "LPM_LVL_SEL,LPM Interrupt level select" "0,1,2,3" newline bitfld.long 0x00 4.--5. "EP0_LVL_SEL,EP0 Interrupt level select" "0,1,2,3" newline bitfld.long 0x00 2.--3. "BUS_RESET_LVL_SEL,BUS RESET Interrupt level select" "0,1,2,3" newline bitfld.long 0x00 0.--1. "SOF_LVL_SEL,USB SOF Interrupt level select" "0: High priority interrupt,1: Medium priority interrupt,2: Low priority interrupt,3: illegal" rgroup.long 0x2034++0x03 line.long 0x00 "INTR_CAUSE_HI,High priority interrupt Cause register" bitfld.long 0x00 15. "EP8_INTR,EP8 Interrupt" "0,1" newline bitfld.long 0x00 14. "EP7_INTR,EP7 Interrupt" "0,1" newline bitfld.long 0x00 13. "EP6_INTR,EP6 Interrupt" "0,1" newline bitfld.long 0x00 12. "EP5_INTR,EP5 Interrupt" "0,1" newline bitfld.long 0x00 11. "EP4_INTR,EP4 Interrupt" "0,1" newline bitfld.long 0x00 10. "EP3_INTR,EP3 Interrupt" "0,1" newline bitfld.long 0x00 9. "EP2_INTR,EP2 Interrupt" "0,1" newline bitfld.long 0x00 8. "EP1_INTR,EP1 Interrupt" "0,1" newline bitfld.long 0x00 7. "ARB_EP_INTR,Arbiter Endpoint Interrupt" "0,1" newline bitfld.long 0x00 4. "RESUME_INTR,Resume Interrupt" "0,1" newline bitfld.long 0x00 3. "LPM_INTR,LPM Interrupt" "0,1" newline bitfld.long 0x00 2. "EP0_INTR,EP0 Interrupt" "0,1" newline bitfld.long 0x00 1. "BUS_RESET_INTR,BUS RESET Interrupt" "0,1" newline bitfld.long 0x00 0. "SOF_INTR,USB SOF Interrupt" "0,1" rgroup.long 0x2038++0x03 line.long 0x00 "INTR_CAUSE_MED,Medium priority interrupt Cause register" bitfld.long 0x00 15. "EP8_INTR,EP8 Interrupt" "0,1" newline bitfld.long 0x00 14. "EP7_INTR,EP7 Interrupt" "0,1" newline bitfld.long 0x00 13. "EP6_INTR,EP6 Interrupt" "0,1" newline bitfld.long 0x00 12. "EP5_INTR,EP5 Interrupt" "0,1" newline bitfld.long 0x00 11. "EP4_INTR,EP4 Interrupt" "0,1" newline bitfld.long 0x00 10. "EP3_INTR,EP3 Interrupt" "0,1" newline bitfld.long 0x00 9. "EP2_INTR,EP2 Interrupt" "0,1" newline bitfld.long 0x00 8. "EP1_INTR,EP1 Interrupt" "0,1" newline bitfld.long 0x00 7. "ARB_EP_INTR,Arbiter Endpoint Interrupt" "0,1" newline bitfld.long 0x00 4. "RESUME_INTR,Resume Interrupt" "0,1" newline bitfld.long 0x00 3. "LPM_INTR,LPM Interrupt" "0,1" newline bitfld.long 0x00 2. "EP0_INTR,EP0 Interrupt" "0,1" newline bitfld.long 0x00 1. "BUS_RESET_INTR,BUS RESET Interrupt" "0,1" newline bitfld.long 0x00 0. "SOF_INTR,USB SOF Interrupt" "0,1" rgroup.long 0x203C++0x03 line.long 0x00 "INTR_CAUSE_LO,Low priority interrupt Cause register" bitfld.long 0x00 15. "EP8_INTR,EP8 Interrupt" "0,1" newline bitfld.long 0x00 14. "EP7_INTR,EP7 Interrupt" "0,1" newline bitfld.long 0x00 13. "EP6_INTR,EP6 Interrupt" "0,1" newline bitfld.long 0x00 12. "EP5_INTR,EP5 Interrupt" "0,1" newline bitfld.long 0x00 11. "EP4_INTR,EP4 Interrupt" "0,1" newline bitfld.long 0x00 10. "EP3_INTR,EP3 Interrupt" "0,1" newline bitfld.long 0x00 9. "EP2_INTR,EP2 Interrupt" "0,1" newline bitfld.long 0x00 8. "EP1_INTR,EP1 Interrupt" "0,1" newline bitfld.long 0x00 7. "ARB_EP_INTR,Arbiter Endpoint Interrupt" "0,1" newline bitfld.long 0x00 4. "RESUME_INTR,Resume Interrupt" "0,1" newline bitfld.long 0x00 3. "LPM_INTR,LPM Interrupt" "0,1" newline bitfld.long 0x00 2. "EP0_INTR,EP0 Interrupt" "0,1" newline bitfld.long 0x00 1. "BUS_RESET_INTR,BUS RESET Interrupt" "0,1" newline bitfld.long 0x00 0. "SOF_INTR,USB SOF Interrupt" "0,1" group.long 0x2070++0x03 line.long 0x00 "DFT_CTRL,DFT control" bitfld.long 0x00 8.--9. "ADFT_VREFOUT_SEL,Select ADFT connection for VREF_OUT" "0: no connections,1: Connect adft_vref_out output to amuxbusa..,2: Connect adft_vref_out output to amuxbusb,3: RSVD" newline bitfld.long 0x00 0.--2. "DDFT_SEL,DDFT select signal" "0: Nothing connected output 0,1: Single Ended output of DP,2: Single Ended output of DM,3: Differential Receiver output,4: Charger detect output,5: Vbus detect output,?..." group.long 0x2F00++0x03 line.long 0x00 "PHY_TRIM0,PHY trim control register" bitfld.long 0x00 0.--5. "TRIM_DP_R_REG,Trim control for D+ pin poly termination resistors when PHY is in regulated mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x2F04++0x03 line.long 0x00 "PHY_TRIM1,PHY trim control register" bitfld.long 0x00 0.--5. "TRIM_DM_R_REG,Trim control for D- pin poly termination resistors when PHY is in regulated mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x2F08++0x03 line.long 0x00 "PHY_TRIM2,PHY trim control register" bitfld.long 0x00 0.--5. "TRIM_DP_R_BYPASS,Trim control for D+ pin poly termination resistors when PHY is in bypass mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x2F0C++0x03 line.long 0x00 "PHY_TRIM3,PHY trim control register" bitfld.long 0x00 0.--5. "TRIM_DM_R_BYPASS,Trim control for D- pin poly termination resistors when PHY is in bypass mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x2F10++0x03 line.long 0x00 "CHGDET_TRIM,Charger detect trim values" bitfld.long 0x00 4.--6. "V600M_TRIM,Trim bits for 600mV voltage reference" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--1. "V325M_TRIM,Trim bits for 325mV voltage reference" "0,1,2,3" group.long 0x2F14++0x03 line.long 0x00 "TRIM,trim values" bitfld.long 0x00 0.--1. "DM_PD_VAL,Trim bit for DM Pull Down register to get resistance value close enough to 15kohm" "0,1,2,3" group.long 0x2F18++0x03 line.long 0x00 "USBIO_TRIM,trim values for IOs" bitfld.long 0x00 5. "X_DEC,This bit enables a decrease of the USB crossover voltage" "0,1" newline bitfld.long 0x00 4. "X_INC,This bit enables a increase of the USB crossover voltage" "0,1" newline bitfld.long 0x00 3. "MINC,When set this bit increases the USB edge matching ratio" "0,1" newline bitfld.long 0x00 2. "MDEC,When set this bit decreases the USB edge matching ratio" "0,1" newline bitfld.long 0x00 0.--1. "TRIM,These two bits of trim are for the suspend mode resistor" "0: No effect,1: Lower idle voltage,2: Higher idle voltage,3: TRIM_DONT_USE" tree.end elif cpuis("PMG1-S3") base ad:0x402C0000 repeat 8. (increment 0 1) (increment 0 0x4) group.long ($2+0x00)++0x03 line.long 0x00 "EP0_DR[$1],Control End point EP0 Data Register $1" hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE,This register is shared for both transmit and receive" repeat.end group.long 0x20++0x03 line.long 0x00 "CR0,USB control 0 Register" bitfld.long 0x00 7. "USB_ENABLE,This bit enables the device to respond to USB traffic" "0,1" newline hexmask.long.byte 0x00 0.--6. 1. "DEVICE_ADDRESS,These bits specify the USB device address to which the SIE will respond" group.long 0x24++0x03 line.long 0x00 "CR1,USB control 1 Register" bitfld.long 0x00 3. "TRIM_OFFSET_MSB,This bit enables trim bit[7]" "0,1" newline bitfld.long 0x00 2. "BUS_ACTIVITY,The Bus Activity bit is a stickybit that detects any non-idle USB event that has occurred on the USB bus" "0,1" newline bitfld.long 0x00 1. "ENABLE_LOCK,This bit is set to turn on the automatic frequency locking of the internal oscillator to USB traffic" "0,1" newline bitfld.long 0x00 0. "REG_ENABLE,This bit controls the operation of the internal USB regulator" "0,1" group.long 0x28++0x03 line.long 0x00 "SIE_EP_INT_EN,USB SIE Data Endpoints Interrupt Enable Register" bitfld.long 0x00 7. "EP8_INTR_EN,Enables interrupt for EP8" "0,1" newline bitfld.long 0x00 6. "EP7_INTR_EN,Enables interrupt for EP7" "0,1" newline bitfld.long 0x00 5. "EP6_INTR_EN,Enables interrupt for EP6" "0,1" newline bitfld.long 0x00 4. "EP5_INTR_EN,Enables interrupt for EP5" "0,1" newline bitfld.long 0x00 3. "EP4_INTR_EN,Enables interrupt for EP4" "0,1" newline bitfld.long 0x00 2. "EP3_INTR_EN,Enables interrupt for EP3" "0,1" newline bitfld.long 0x00 1. "EP2_INTR_EN,Enables interrupt for EP2" "0,1" newline bitfld.long 0x00 0. "EP1_INTR_EN,Enables interrupt for EP1" "0,1" group.long 0x2C++0x03 line.long 0x00 "SIE_EP_INT_SR,USB SIE Data Endpoint Interrupt Status" bitfld.long 0x00 7. "EP8_INTR,Interrupt status for EP8" "0,1" newline bitfld.long 0x00 6. "EP7_INTR,Interrupt status for EP7" "0,1" newline bitfld.long 0x00 5. "EP6_INTR,Interrupt status for EP6" "0,1" newline bitfld.long 0x00 4. "EP5_INTR,Interrupt status for EP5" "0,1" newline bitfld.long 0x00 3. "EP4_INTR,Interrupt status for EP4" "0,1" newline bitfld.long 0x00 2. "EP3_INTR,Interrupt status for EP3" "0,1" newline bitfld.long 0x00 1. "EP2_INTR,Interrupt status for EP2" "0,1" newline bitfld.long 0x00 0. "EP1_INTR,Interrupt status for EP1" "0,1" group.long 0x30++0x03 line.long 0x00 "SIE_EP1_CNT0,Non-control endpoint count register" bitfld.long 0x00 7. "DATA_TOGGLE,This bit selects the DATA packet's toggle state" "0,1" newline bitfld.long 0x00 6. "DATA_VALID,This bit is used for OUT transactions only and is read only" "0: No ACK'd transactions since bit was last..,1: Indicates a transaction ended with an ACK" newline bitfld.long 0x00 0.--2. "DATA_COUNT_MSB,These bits are the 3 MSb bits of an 11-bit counter" "0,1,2,3,4,5,6,7" group.long 0x34++0x03 line.long 0x00 "SIE_EP1_CNT1,Non-control endpoint count register" hexmask.long.byte 0x00 0.--7. 1. "DATA_COUNT,These bits are the 8 LSb of a 11-bit counter" group.long 0x38++0x03 line.long 0x00 "SIE_EP1_CR0,Non-control endpoint's control Register" bitfld.long 0x00 7. "STALL,When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT" "0,1" newline bitfld.long 0x00 6. "ERR_IN_TXN,The Error in transaction bit is set whenever an error is detected" "0,1" newline bitfld.long 0x00 5. "NAK_INT_EN,When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK" "0,1" newline bitfld.long 0x00 4. "ACKED_TXN,The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet" "0: No ACK'd transactions since bit was last..,1: Indicates a transaction ended with an ACK" newline bitfld.long 0x00 0.--3. "MODE,The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint" "0: Ignore all USB traffic to this endpoint,1: SETUP,2: SETUP,3: SETUP,?,5: SETUP,6: SETUP,7: SETUP,8: SETUP,9: SETUP,?,11: SETUP,12: SETUP,13: SETUP,?,15: SETUP" group.long 0x40++0x03 line.long 0x00 "USBIO_CR0,USBIO Control 0 Register" bitfld.long 0x00 7. "TEN,USB Transmit Enable" "0,1" newline bitfld.long 0x00 6. "TSE0,Transmit Single-Ended Zero" "0,1" newline bitfld.long 0x00 5. "TD,Transmit Data" "0: Force USB K state (D+ is low D- is high),1: Force USB J state (D+ is high D- is low)" newline rbitfld.long 0x00 0. "RD,Received Data" "0: D+ < D- (K state) or D+=D-=0 (SE0),1: D+ > D- (J state)" group.long 0x44++0x03 line.long 0x00 "USBIO_CR2,USBIO control 2 Register" bitfld.long 0x00 7. "TEST_RES,This bit is for testing the non-passthrough suspend mode pull up" "0,1" newline bitfld.long 0x00 6. "TEST_PKT,This bit enables the device to transmit a packet in response to an internally generated IN packet" "0,1" newline rbitfld.long 0x00 0.--5. "RSVD,N/A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x48++0x03 line.long 0x00 "USBIO_CR1,USBIO control 1 Register" bitfld.long 0x00 5. "IOMODE,This bit allows the D+ and D- pins to be configured for either USB mode or bit-banged modes" "0,1" newline bitfld.long 0x00 2. "USBPUEN,This bit enables the connection of the internal 1.5 k pull up resistor on the D+ pin" "0,1" newline rbitfld.long 0x00 1. "DPO,This read only bit gives the state of the D+ pin" "0,1" newline rbitfld.long 0x00 0. "DMO,This read only bit gives the state of the D- pin" "0,1" group.long 0x50++0x03 line.long 0x00 "DYN_RECONFIG,USB Dynamic reconfiguration register" rbitfld.long 0x00 4. "DYN_RECONFIG_RDY_STS,This bit indicates the ready status for the dynamic reconfiguration when set to 1 indicates the block is ready for reconfiguration" "0,1" newline bitfld.long 0x00 1.--3. "DYN_RECONFIG_EPNO,These bits indicates the EP number for which reconfiguration is required when dyn_config_en bit is set to 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0. "DYN_CONFIG_EN,This bit is used to enable the dynamic re-configuration for the selected EP" "0,1" rgroup.long 0x60++0x03 line.long 0x00 "SOF0,Start Of Frame Register" hexmask.long.byte 0x00 0.--7. 1. "FRAME_NUMBER,It has the lower 8 bits [7:0] of the SOF frame number" rgroup.long 0x64++0x03 line.long 0x00 "SOF1,Start Of Frame Register" bitfld.long 0x00 0.--2. "FRAME_NUMBER_MSB,It has the upper 3 bits [10:8] of the SOF frame number" "0,1,2,3,4,5,6,7" group.long 0x70++0x03 line.long 0x00 "SIE_EP2_CNT0,Non-control endpoint count register" bitfld.long 0x00 7. "DATA_TOGGLE,This bit selects the DATA packet's toggle state" "0,1" newline bitfld.long 0x00 6. "DATA_VALID,This bit is used for OUT transactions only and is read only" "0: No ACK'd transactions since bit was last..,1: Indicates a transaction ended with an ACK" newline bitfld.long 0x00 0.--2. "DATA_COUNT_MSB,These bits are the 3 MSb bits of an 11-bit counter" "0,1,2,3,4,5,6,7" group.long 0x74++0x03 line.long 0x00 "SIE_EP2_CNT1,Non-control endpoint count register" hexmask.long.byte 0x00 0.--7. 1. "DATA_COUNT,These bits are the 8 LSb of a 11-bit counter" group.long 0x78++0x03 line.long 0x00 "SIE_EP2_CR0,Non-control endpoint's control Register" bitfld.long 0x00 7. "STALL,When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT" "0,1" newline bitfld.long 0x00 6. "ERR_IN_TXN,The Error in transaction bit is set whenever an error is detected" "0,1" newline bitfld.long 0x00 5. "NAK_INT_EN,When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK" "0,1" newline bitfld.long 0x00 4. "ACKED_TXN,The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet" "0: No ACK'd transactions since bit was last..,1: Indicates a transaction ended with an ACK" newline bitfld.long 0x00 0.--3. "MODE,The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint" "0: Ignore all USB traffic to this endpoint,1: SETUP,2: SETUP,3: SETUP,?,5: SETUP,6: SETUP,7: SETUP,8: SETUP,9: SETUP,?,11: SETUP,12: SETUP,13: SETUP,?,15: SETUP" rgroup.long 0x80++0x03 line.long 0x00 "OSCLK_DR0,Oscillator lock data register 0" hexmask.long.byte 0x00 0.--7. 1. "ADDER,These bits return the lower 8 bits of the oscillator locking circuits adder output" rgroup.long 0x84++0x03 line.long 0x00 "OSCLK_DR1,Oscillator lock data register 1" hexmask.long.byte 0x00 0.--6. 1. "ADDER_MSB,These bits return the upper 7 bits of the oscillator locking circuits adder output" group.long 0xA0++0x03 line.long 0x00 "EP0_CR,Endpoint0 control Register" bitfld.long 0x00 7. "SETUP_RCVD,When set this bit indicates a valid SETUP packet was received and ACKed" "0,1" newline bitfld.long 0x00 6. "IN_RCVD,When set this bit indicates a valid IN packet has been received" "0,1" newline bitfld.long 0x00 5. "OUT_RCVD,When set this bit indicates a valid OUT packet has been received and ACKed" "0,1" newline bitfld.long 0x00 4. "ACKED_TXN,The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet" "0: No ACK'd transactions since bit was last..,1: Indicates a transaction ended with an ACK" newline bitfld.long 0x00 0.--3. "MODE,The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint" "0: Ignore all USB traffic to this endpoint,1: SETUP,2: SETUP,3: SETUP,?,5: SETUP,6: SETUP,7: SETUP,8: SETUP,9: SETUP,?,11: SETUP,12: SETUP,13: SETUP,?,15: SETUP" group.long 0xA4++0x03 line.long 0x00 "EP0_CNT,Endpoint0 count Register" bitfld.long 0x00 7. "DATA_TOGGLE,This bit selects the DATA packet's toggle state" "0,1" newline bitfld.long 0x00 6. "DATA_VALID,This bit is used for OUT/SETUP transactions only and is read only" "0: No ACK'd transactions since bit was last..,1: Indicates a transaction ended with an ACK" newline bitfld.long 0x00 0.--3. "BYTE_COUNT,These bits indicate the number of data bytes in a transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0xB0++0x03 line.long 0x00 "SIE_EP3_CNT0,Non-control endpoint count register" bitfld.long 0x00 7. "DATA_TOGGLE,This bit selects the DATA packet's toggle state" "0,1" newline bitfld.long 0x00 6. "DATA_VALID,This bit is used for OUT transactions only and is read only" "0: No ACK'd transactions since bit was last..,1: Indicates a transaction ended with an ACK" newline bitfld.long 0x00 0.--2. "DATA_COUNT_MSB,These bits are the 3 MSb bits of an 11-bit counter" "0,1,2,3,4,5,6,7" group.long 0xB4++0x03 line.long 0x00 "SIE_EP3_CNT1,Non-control endpoint count register" hexmask.long.byte 0x00 0.--7. 1. "DATA_COUNT,These bits are the 8 LSb of a 11-bit counter" group.long 0xB8++0x03 line.long 0x00 "SIE_EP3_CR0,Non-control endpoint's control Register" bitfld.long 0x00 7. "STALL,When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT" "0,1" newline bitfld.long 0x00 6. "ERR_IN_TXN,The Error in transaction bit is set whenever an error is detected" "0,1" newline bitfld.long 0x00 5. "NAK_INT_EN,When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK" "0,1" newline bitfld.long 0x00 4. "ACKED_TXN,The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet" "0: No ACK'd transactions since bit was last..,1: Indicates a transaction ended with an ACK" newline bitfld.long 0x00 0.--3. "MODE,The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint" "0: Ignore all USB traffic to this endpoint,1: SETUP,2: SETUP,3: SETUP,?,5: SETUP,6: SETUP,7: SETUP,8: SETUP,9: SETUP,?,11: SETUP,12: SETUP,13: SETUP,?,15: SETUP" group.long 0xF0++0x03 line.long 0x00 "SIE_EP4_CNT0,Non-control endpoint count register" bitfld.long 0x00 7. "DATA_TOGGLE,This bit selects the DATA packet's toggle state" "0,1" newline bitfld.long 0x00 6. "DATA_VALID,This bit is used for OUT transactions only and is read only" "0: No ACK'd transactions since bit was last..,1: Indicates a transaction ended with an ACK" newline bitfld.long 0x00 0.--2. "DATA_COUNT_MSB,These bits are the 3 MSb bits of an 11-bit counter" "0,1,2,3,4,5,6,7" group.long 0xF4++0x03 line.long 0x00 "SIE_EP4_CNT1,Non-control endpoint count register" hexmask.long.byte 0x00 0.--7. 1. "DATA_COUNT,These bits are the 8 LSb of a 11-bit counter" group.long 0xF8++0x03 line.long 0x00 "SIE_EP4_CR0,Non-control endpoint's control Register" bitfld.long 0x00 7. "STALL,When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT" "0,1" newline bitfld.long 0x00 6. "ERR_IN_TXN,The Error in transaction bit is set whenever an error is detected" "0,1" newline bitfld.long 0x00 5. "NAK_INT_EN,When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK" "0,1" newline bitfld.long 0x00 4. "ACKED_TXN,The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet" "0: No ACK'd transactions since bit was last..,1: Indicates a transaction ended with an ACK" newline bitfld.long 0x00 0.--3. "MODE,The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint" "0: Ignore all USB traffic to this endpoint,1: SETUP,2: SETUP,3: SETUP,?,5: SETUP,6: SETUP,7: SETUP,8: SETUP,9: SETUP,?,11: SETUP,12: SETUP,13: SETUP,?,15: SETUP" group.long 0x130++0x03 line.long 0x00 "SIE_EP5_CNT0,Non-control endpoint count register" bitfld.long 0x00 7. "DATA_TOGGLE,This bit selects the DATA packet's toggle state" "0,1" newline bitfld.long 0x00 6. "DATA_VALID,This bit is used for OUT transactions only and is read only" "0: No ACK'd transactions since bit was last..,1: Indicates a transaction ended with an ACK" newline bitfld.long 0x00 0.--2. "DATA_COUNT_MSB,These bits are the 3 MSb bits of an 11-bit counter" "0,1,2,3,4,5,6,7" group.long 0x134++0x03 line.long 0x00 "SIE_EP5_CNT1,Non-control endpoint count register" hexmask.long.byte 0x00 0.--7. 1. "DATA_COUNT,These bits are the 8 LSb of a 11-bit counter" group.long 0x138++0x03 line.long 0x00 "SIE_EP5_CR0,Non-control endpoint's control Register" bitfld.long 0x00 7. "STALL,When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT" "0,1" newline bitfld.long 0x00 6. "ERR_IN_TXN,The Error in transaction bit is set whenever an error is detected" "0,1" newline bitfld.long 0x00 5. "NAK_INT_EN,When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK" "0,1" newline bitfld.long 0x00 4. "ACKED_TXN,The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet" "0: No ACK'd transactions since bit was last..,1: Indicates a transaction ended with an ACK" newline bitfld.long 0x00 0.--3. "MODE,The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint" "0: Ignore all USB traffic to this endpoint,1: SETUP,2: SETUP,3: SETUP,?,5: SETUP,6: SETUP,7: SETUP,8: SETUP,9: SETUP,?,11: SETUP,12: SETUP,13: SETUP,?,15: SETUP" group.long 0x170++0x03 line.long 0x00 "SIE_EP6_CNT0,Non-control endpoint count register" bitfld.long 0x00 7. "DATA_TOGGLE,This bit selects the DATA packet's toggle state" "0,1" newline bitfld.long 0x00 6. "DATA_VALID,This bit is used for OUT transactions only and is read only" "0: No ACK'd transactions since bit was last..,1: Indicates a transaction ended with an ACK" newline bitfld.long 0x00 0.--2. "DATA_COUNT_MSB,These bits are the 3 MSb bits of an 11-bit counter" "0,1,2,3,4,5,6,7" group.long 0x174++0x03 line.long 0x00 "SIE_EP6_CNT1,Non-control endpoint count register" hexmask.long.byte 0x00 0.--7. 1. "DATA_COUNT,These bits are the 8 LSb of a 11-bit counter" group.long 0x178++0x03 line.long 0x00 "SIE_EP6_CR0,Non-control endpoint's control Register" bitfld.long 0x00 7. "STALL,When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT" "0,1" newline bitfld.long 0x00 6. "ERR_IN_TXN,The Error in transaction bit is set whenever an error is detected" "0,1" newline bitfld.long 0x00 5. "NAK_INT_EN,When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK" "0,1" newline bitfld.long 0x00 4. "ACKED_TXN,The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet" "0: No ACK'd transactions since bit was last..,1: Indicates a transaction ended with an ACK" newline bitfld.long 0x00 0.--3. "MODE,The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint" "0: Ignore all USB traffic to this endpoint,1: SETUP,2: SETUP,3: SETUP,?,5: SETUP,6: SETUP,7: SETUP,8: SETUP,9: SETUP,?,11: SETUP,12: SETUP,13: SETUP,?,15: SETUP" group.long 0x1B0++0x03 line.long 0x00 "SIE_EP7_CNT0,Non-control endpoint count register" bitfld.long 0x00 7. "DATA_TOGGLE,This bit selects the DATA packet's toggle state" "0,1" newline bitfld.long 0x00 6. "DATA_VALID,This bit is used for OUT transactions only and is read only" "0: No ACK'd transactions since bit was last..,1: Indicates a transaction ended with an ACK" newline bitfld.long 0x00 0.--2. "DATA_COUNT_MSB,These bits are the 3 MSb bits of an 11-bit counter" "0,1,2,3,4,5,6,7" group.long 0x1B4++0x03 line.long 0x00 "SIE_EP7_CNT1,Non-control endpoint count register" hexmask.long.byte 0x00 0.--7. 1. "DATA_COUNT,These bits are the 8 LSb of a 11-bit counter" group.long 0x1B8++0x03 line.long 0x00 "SIE_EP7_CR0,Non-control endpoint's control Register" bitfld.long 0x00 7. "STALL,When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT" "0,1" newline bitfld.long 0x00 6. "ERR_IN_TXN,The Error in transaction bit is set whenever an error is detected" "0,1" newline bitfld.long 0x00 5. "NAK_INT_EN,When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK" "0,1" newline bitfld.long 0x00 4. "ACKED_TXN,The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet" "0: No ACK'd transactions since bit was last..,1: Indicates a transaction ended with an ACK" newline bitfld.long 0x00 0.--3. "MODE,The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint" "0: Ignore all USB traffic to this endpoint,1: SETUP,2: SETUP,3: SETUP,?,5: SETUP,6: SETUP,7: SETUP,8: SETUP,9: SETUP,?,11: SETUP,12: SETUP,13: SETUP,?,15: SETUP" group.long 0x1F0++0x03 line.long 0x00 "SIE_EP8_CNT0,Non-control endpoint count register" bitfld.long 0x00 7. "DATA_TOGGLE,This bit selects the DATA packet's toggle state" "0,1" newline bitfld.long 0x00 6. "DATA_VALID,This bit is used for OUT transactions only and is read only" "0: No ACK'd transactions since bit was last..,1: Indicates a transaction ended with an ACK" newline bitfld.long 0x00 0.--2. "DATA_COUNT_MSB,These bits are the 3 MSb bits of an 11-bit counter" "0,1,2,3,4,5,6,7" group.long 0x1F4++0x03 line.long 0x00 "SIE_EP8_CNT1,Non-control endpoint count register" hexmask.long.byte 0x00 0.--7. 1. "DATA_COUNT,These bits are the 8 LSb of a 11-bit counter" group.long 0x1F8++0x03 line.long 0x00 "SIE_EP8_CR0,Non-control endpoint's control Register" bitfld.long 0x00 7. "STALL,When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT" "0,1" newline bitfld.long 0x00 6. "ERR_IN_TXN,The Error in transaction bit is set whenever an error is detected" "0,1" newline bitfld.long 0x00 5. "NAK_INT_EN,When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK" "0,1" newline bitfld.long 0x00 4. "ACKED_TXN,The ACK'd transaction bit is set whenever the SIE engages in a transaction to the register's endpoint that completes with an ACK packet" "0: No ACK'd transactions since bit was last..,1: Indicates a transaction ended with an ACK" newline bitfld.long 0x00 0.--3. "MODE,The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint" "0: Ignore all USB traffic to this endpoint,1: SETUP,2: SETUP,3: SETUP,?,5: SETUP,6: SETUP,7: SETUP,8: SETUP,9: SETUP,?,11: SETUP,12: SETUP,13: SETUP,?,15: SETUP" group.long 0x200++0x03 line.long 0x00 "ARB_EP1_CFG,Endpoint Configuration Register" bitfld.long 0x00 3. "RESET_PTR,Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction" "0: Do not Reset Pointer Krypton Backward..,1: Reset Pointer recommended value for reduction.." newline bitfld.long 0x00 2. "CRC_BYPASS,Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware" "0: No CRC bypass CRC bytes will be written to..,1: CRC Bypass Set CRC bytes will not be written.." newline bitfld.long 0x00 1. "DMA_REQ,Manual DMA Request for a particular (1 to 8) endpoint changing this field from 0 to 1 causes a DMA request to be generated" "0,1" newline bitfld.long 0x00 0. "IN_DATA_RDY,Indication that Endpoint Packet Data is Ready in Main memory" "0,1" group.long 0x204++0x03 line.long 0x00 "ARB_EP1_INT_EN,Endpoint Interrupt Enable Register" bitfld.long 0x00 5. "DMA_TERMIN_EN,Endpoint DMA Terminated Enable" "0,1" newline bitfld.long 0x00 4. "ERR_INT_EN,Endpoint Error in Transaction Interrupt Enable" "0,1" newline bitfld.long 0x00 3. "BUF_UNDER_EN,Endpoint Buffer Underflow Enable" "0,1" newline bitfld.long 0x00 2. "BUF_OVER_EN,Endpoint Buffer Overflow Enable" "0,1" newline bitfld.long 0x00 1. "DMA_GNT_EN,Endpoint DMA Grant Enable" "0,1" newline bitfld.long 0x00 0. "IN_BUF_FULL_EN,IN Endpoint Local Buffer Full Enable" "0,1" group.long 0x208++0x03 line.long 0x00 "ARB_EP1_SR,Endpoint Interrupt Enable Register" bitfld.long 0x00 5. "DMA_TERMIN,Endpoint DMA Terminated Interrupt" "0,1" newline bitfld.long 0x00 3. "BUF_UNDER,Endpoint Buffer Underflow Interrupt" "0,1" newline bitfld.long 0x00 2. "BUF_OVER,Endpoint Buffer Overflow Interrupt" "0,1" newline bitfld.long 0x00 1. "DMA_GNT,Endpoint DMA Grant Interrupt" "0,1" newline bitfld.long 0x00 0. "IN_BUF_FULL,IN Endpoint Local Buffer Full Interrupt" "0,1" group.long 0x210++0x03 line.long 0x00 "ARB_RW1_WA,Endpoint Write Address value" hexmask.long.byte 0x00 0.--7. 1. "WA,Write Address for EP" group.long 0x214++0x03 line.long 0x00 "ARB_RW1_WA_MSB,Endpoint Write Address value" bitfld.long 0x00 0. "WA_MSB,Write Address for EP" "0,1" group.long 0x218++0x03 line.long 0x00 "ARB_RW1_RA,Endpoint Read Address value" hexmask.long.byte 0x00 0.--7. 1. "RA,Read Address for EP" group.long 0x21C++0x03 line.long 0x00 "ARB_RW1_RA_MSB,Endpoint Read Address value" bitfld.long 0x00 0. "RA_MSB,Read Address for EP" "0,1" group.long 0x220++0x03 line.long 0x00 "ARB_RW1_DR,Endpoint Data Register" hexmask.long.byte 0x00 0.--7. 1. "DR,Data Register for EP This register is linked to the memory hence reset value is undefined" group.long 0x230++0x03 line.long 0x00 "BUF_SIZE,Dedicated Endpoint Buffer Size Register" bitfld.long 0x00 4.--7. "OUT_BUF,Buffer size for OUT Endpoints" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0.--3. "IN_BUF,Buffer size for IN Endpoints" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x238++0x03 line.long 0x00 "EP_ACTIVE,Endpoint Active Indication Register" bitfld.long 0x00 7. "EP8_ACT,Indicates that Endpoint is currently active" "0,1" newline bitfld.long 0x00 6. "EP7_ACT,Indicates that Endpoint is currently active" "0,1" newline bitfld.long 0x00 5. "EP6_ACT,Indicates that Endpoint is currently active" "0,1" newline bitfld.long 0x00 4. "EP5_ACT,Indicates that Endpoint is currently active" "0,1" newline bitfld.long 0x00 3. "EP4_ACT,Indicates that Endpoint is currently active" "0,1" newline bitfld.long 0x00 2. "EP3_ACT,Indicates that Endpoint is currently active" "0,1" newline bitfld.long 0x00 1. "EP2_ACT,Indicates that Endpoint is currently active" "0,1" newline bitfld.long 0x00 0. "EP1_ACT,Indicates that Endpoint is currently active" "0,1" group.long 0x23C++0x03 line.long 0x00 "EP_TYPE,Endpoint Type (IN/OUT) Indication" bitfld.long 0x00 7. "EP8_TYP,Endpoint Type Indication" "0: IN outpoint,1: OUT outpoint" newline bitfld.long 0x00 6. "EP7_TYP,Endpoint Type Indication" "0: IN outpoint,1: OUT outpoint" newline bitfld.long 0x00 5. "EP6_TYP,Endpoint Type Indication" "0: IN outpoint,1: OUT outpoint" newline bitfld.long 0x00 4. "EP5_TYP,Endpoint Type Indication" "0: IN outpoint,1: OUT outpoint" newline bitfld.long 0x00 3. "EP4_TYP,Endpoint Type Indication" "0: IN outpoint,1: OUT outpoint" newline bitfld.long 0x00 2. "EP3_TYP,Endpoint Type Indication" "0: IN outpoint,1: OUT outpoint" newline bitfld.long 0x00 1. "EP2_TYP,Endpoint Type Indication" "0: IN outpoint,1: OUT outpoint" newline bitfld.long 0x00 0. "EP1_TYP,Endpoint Type Indication" "0: IN outpoint,1: OUT outpoint" group.long 0x240++0x03 line.long 0x00 "ARB_EP2_CFG,Endpoint Configuration Register" bitfld.long 0x00 3. "RESET_PTR,Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction" "0: Do not Reset Pointer Krypton Backward..,1: Reset Pointer recommended value for reduction.." newline bitfld.long 0x00 2. "CRC_BYPASS,Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware" "0: No CRC bypass CRC bytes will be written to..,1: CRC Bypass Set CRC bytes will not be written.." newline bitfld.long 0x00 1. "DMA_REQ,Manual DMA Request for a particular (1 to 8) endpoint changing this field from 0 to 1 causes a DMA request to be generated" "0,1" newline bitfld.long 0x00 0. "IN_DATA_RDY,Indication that Endpoint Packet Data is Ready in Main memory" "0,1" group.long 0x244++0x03 line.long 0x00 "ARB_EP2_INT_EN,Endpoint Interrupt Enable Register" bitfld.long 0x00 5. "DMA_TERMIN_EN,Endpoint DMA Terminated Enable" "0,1" newline bitfld.long 0x00 4. "ERR_INT_EN,Endpoint Error in Transaction Interrupt Enable" "0,1" newline bitfld.long 0x00 3. "BUF_UNDER_EN,Endpoint Buffer Underflow Enable" "0,1" newline bitfld.long 0x00 2. "BUF_OVER_EN,Endpoint Buffer Overflow Enable" "0,1" newline bitfld.long 0x00 1. "DMA_GNT_EN,Endpoint DMA Grant Enable" "0,1" newline bitfld.long 0x00 0. "IN_BUF_FULL_EN,IN Endpoint Local Buffer Full Enable" "0,1" group.long 0x248++0x03 line.long 0x00 "ARB_EP2_SR,Endpoint Interrupt Enable Register" bitfld.long 0x00 5. "DMA_TERMIN,Endpoint DMA Terminated Interrupt" "0,1" newline bitfld.long 0x00 3. "BUF_UNDER,Endpoint Buffer Underflow Interrupt" "0,1" newline bitfld.long 0x00 2. "BUF_OVER,Endpoint Buffer Overflow Interrupt" "0,1" newline bitfld.long 0x00 1. "DMA_GNT,Endpoint DMA Grant Interrupt" "0,1" newline bitfld.long 0x00 0. "IN_BUF_FULL,IN Endpoint Local Buffer Full Interrupt" "0,1" group.long 0x250++0x03 line.long 0x00 "ARB_RW2_WA,Endpoint Write Address value" hexmask.long.byte 0x00 0.--7. 1. "WA,Write Address for EP" group.long 0x254++0x03 line.long 0x00 "ARB_RW2_WA_MSB,Endpoint Write Address value" bitfld.long 0x00 0. "WA_MSB,Write Address for EP" "0,1" group.long 0x258++0x03 line.long 0x00 "ARB_RW2_RA,Endpoint Read Address value" hexmask.long.byte 0x00 0.--7. 1. "RA,Read Address for EP" group.long 0x25C++0x03 line.long 0x00 "ARB_RW2_RA_MSB,Endpoint Read Address value" bitfld.long 0x00 0. "RA_MSB,Read Address for EP" "0,1" group.long 0x260++0x03 line.long 0x00 "ARB_RW2_DR,Endpoint Data Register" hexmask.long.byte 0x00 0.--7. 1. "DR,Data Register for EP This register is linked to the memory hence reset value is undefined" group.long 0x270++0x03 line.long 0x00 "ARB_CFG,Arbiter Configuration Register" bitfld.long 0x00 7. "CFG_CMP,Register Configuration Complete Indication" "0,1" newline bitfld.long 0x00 5.--6. "DMA_CFG,DMA Access Configuration" "0: DMA_NONE,1: DMA_MANUAL,2: DMA_AUTO,?..." newline bitfld.long 0x00 4. "AUTO_MEM,Enables Auto Memory Configuration" "0,1" group.long 0x274++0x03 line.long 0x00 "USB_CLK_EN,USB Block Clock Enable Register" bitfld.long 0x00 0. "CSR_CLK_EN,Clock Enable for Core Logic clocked by AHB bus clock" "0,1" group.long 0x278++0x03 line.long 0x00 "ARB_INT_EN,Arbiter Interrupt Enable" bitfld.long 0x00 7. "EP8_INTR_EN,Enables interrupt for EP8" "0,1" newline bitfld.long 0x00 6. "EP7_INTR_EN,Enables interrupt for EP7" "0,1" newline bitfld.long 0x00 5. "EP6_INTR_EN,Enables interrupt for EP6" "0,1" newline bitfld.long 0x00 4. "EP5_INTR_EN,Enables interrupt for EP5" "0,1" newline bitfld.long 0x00 3. "EP4_INTR_EN,Enables interrupt for EP4" "0,1" newline bitfld.long 0x00 2. "EP3_INTR_EN,Enables interrupt for EP3" "0,1" newline bitfld.long 0x00 1. "EP2_INTR_EN,Enables interrupt for EP2" "0,1" newline bitfld.long 0x00 0. "EP1_INTR_EN,Enables interrupt for EP1" "0,1" rgroup.long 0x27C++0x03 line.long 0x00 "ARB_INT_SR,Arbiter Interrupt Status" bitfld.long 0x00 7. "EP8_INTR,Interrupt status for EP8" "0,1" newline bitfld.long 0x00 6. "EP7_INTR,Interrupt status for EP7" "0,1" newline bitfld.long 0x00 5. "EP6_INTR,Interrupt status for EP6" "0,1" newline bitfld.long 0x00 4. "EP5_INTR,Interrupt status for EP5" "0,1" newline bitfld.long 0x00 3. "EP4_INTR,Interrupt status for EP4" "0,1" newline bitfld.long 0x00 2. "EP3_INTR,Interrupt status for EP3" "0,1" newline bitfld.long 0x00 1. "EP2_INTR,Interrupt status for EP2" "0,1" newline bitfld.long 0x00 0. "EP1_INTR,Interrupt status for EP1" "0,1" group.long 0x280++0x03 line.long 0x00 "ARB_EP3_CFG,Endpoint Configuration Register" bitfld.long 0x00 3. "RESET_PTR,Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction" "0: Do not Reset Pointer Krypton Backward..,1: Reset Pointer recommended value for reduction.." newline bitfld.long 0x00 2. "CRC_BYPASS,Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware" "0: No CRC bypass CRC bytes will be written to..,1: CRC Bypass Set CRC bytes will not be written.." newline bitfld.long 0x00 1. "DMA_REQ,Manual DMA Request for a particular (1 to 8) endpoint changing this field from 0 to 1 causes a DMA request to be generated" "0,1" newline bitfld.long 0x00 0. "IN_DATA_RDY,Indication that Endpoint Packet Data is Ready in Main memory" "0,1" group.long 0x284++0x03 line.long 0x00 "ARB_EP3_INT_EN,Endpoint Interrupt Enable Register" bitfld.long 0x00 5. "DMA_TERMIN_EN,Endpoint DMA Terminated Enable" "0,1" newline bitfld.long 0x00 4. "ERR_INT_EN,Endpoint Error in Transaction Interrupt Enable" "0,1" newline bitfld.long 0x00 3. "BUF_UNDER_EN,Endpoint Buffer Underflow Enable" "0,1" newline bitfld.long 0x00 2. "BUF_OVER_EN,Endpoint Buffer Overflow Enable" "0,1" newline bitfld.long 0x00 1. "DMA_GNT_EN,Endpoint DMA Grant Enable" "0,1" newline bitfld.long 0x00 0. "IN_BUF_FULL_EN,IN Endpoint Local Buffer Full Enable" "0,1" group.long 0x288++0x03 line.long 0x00 "ARB_EP3_SR,Endpoint Interrupt Enable Register" bitfld.long 0x00 5. "DMA_TERMIN,Endpoint DMA Terminated Interrupt" "0,1" newline bitfld.long 0x00 3. "BUF_UNDER,Endpoint Buffer Underflow Interrupt" "0,1" newline bitfld.long 0x00 2. "BUF_OVER,Endpoint Buffer Overflow Interrupt" "0,1" newline bitfld.long 0x00 1. "DMA_GNT,Endpoint DMA Grant Interrupt" "0,1" newline bitfld.long 0x00 0. "IN_BUF_FULL,IN Endpoint Local Buffer Full Interrupt" "0,1" group.long 0x290++0x03 line.long 0x00 "ARB_RW3_WA,Endpoint Write Address value" hexmask.long.byte 0x00 0.--7. 1. "WA,Write Address for EP" group.long 0x294++0x03 line.long 0x00 "ARB_RW3_WA_MSB,Endpoint Write Address value" bitfld.long 0x00 0. "WA_MSB,Write Address for EP" "0,1" group.long 0x298++0x03 line.long 0x00 "ARB_RW3_RA,Endpoint Read Address value" hexmask.long.byte 0x00 0.--7. 1. "RA,Read Address for EP" group.long 0x29C++0x03 line.long 0x00 "ARB_RW3_RA_MSB,Endpoint Read Address value" bitfld.long 0x00 0. "RA_MSB,Read Address for EP" "0,1" group.long 0x2A0++0x03 line.long 0x00 "ARB_RW3_DR,Endpoint Data Register" hexmask.long.byte 0x00 0.--7. 1. "DR,Data Register for EP This register is linked to the memory hence reset value is undefined" group.long 0x2B0++0x03 line.long 0x00 "CWA,Common Area Write Address" hexmask.long.byte 0x00 0.--7. 1. "CWA,Write Address for Common Area" group.long 0x2B4++0x03 line.long 0x00 "CWA_MSB,Endpoint Read Address value" bitfld.long 0x00 0. "CWA_MSB,Write Address for Common Area" "0,1" group.long 0x2C0++0x03 line.long 0x00 "ARB_EP4_CFG,Endpoint Configuration Register" bitfld.long 0x00 3. "RESET_PTR,Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction" "0: Do not Reset Pointer Krypton Backward..,1: Reset Pointer recommended value for reduction.." newline bitfld.long 0x00 2. "CRC_BYPASS,Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware" "0: No CRC bypass CRC bytes will be written to..,1: CRC Bypass Set CRC bytes will not be written.." newline bitfld.long 0x00 1. "DMA_REQ,Manual DMA Request for a particular (1 to 8) endpoint changing this field from 0 to 1 causes a DMA request to be generated" "0,1" newline bitfld.long 0x00 0. "IN_DATA_RDY,Indication that Endpoint Packet Data is Ready in Main memory" "0,1" group.long 0x2C4++0x03 line.long 0x00 "ARB_EP4_INT_EN,Endpoint Interrupt Enable Register" bitfld.long 0x00 5. "DMA_TERMIN_EN,Endpoint DMA Terminated Enable" "0,1" newline bitfld.long 0x00 4. "ERR_INT_EN,Endpoint Error in Transaction Interrupt Enable" "0,1" newline bitfld.long 0x00 3. "BUF_UNDER_EN,Endpoint Buffer Underflow Enable" "0,1" newline bitfld.long 0x00 2. "BUF_OVER_EN,Endpoint Buffer Overflow Enable" "0,1" newline bitfld.long 0x00 1. "DMA_GNT_EN,Endpoint DMA Grant Enable" "0,1" newline bitfld.long 0x00 0. "IN_BUF_FULL_EN,IN Endpoint Local Buffer Full Enable" "0,1" group.long 0x2C8++0x03 line.long 0x00 "ARB_EP4_SR,Endpoint Interrupt Enable Register" bitfld.long 0x00 5. "DMA_TERMIN,Endpoint DMA Terminated Interrupt" "0,1" newline bitfld.long 0x00 3. "BUF_UNDER,Endpoint Buffer Underflow Interrupt" "0,1" newline bitfld.long 0x00 2. "BUF_OVER,Endpoint Buffer Overflow Interrupt" "0,1" newline bitfld.long 0x00 1. "DMA_GNT,Endpoint DMA Grant Interrupt" "0,1" newline bitfld.long 0x00 0. "IN_BUF_FULL,IN Endpoint Local Buffer Full Interrupt" "0,1" group.long 0x2D0++0x03 line.long 0x00 "ARB_RW4_WA,Endpoint Write Address value" hexmask.long.byte 0x00 0.--7. 1. "WA,Write Address for EP" group.long 0x2D4++0x03 line.long 0x00 "ARB_RW4_WA_MSB,Endpoint Write Address value" bitfld.long 0x00 0. "WA_MSB,Write Address for EP" "0,1" group.long 0x2D8++0x03 line.long 0x00 "ARB_RW4_RA,Endpoint Read Address value" hexmask.long.byte 0x00 0.--7. 1. "RA,Read Address for EP" group.long 0x2DC++0x03 line.long 0x00 "ARB_RW4_RA_MSB,Endpoint Read Address value" bitfld.long 0x00 0. "RA_MSB,Read Address for EP" "0,1" group.long 0x2E0++0x03 line.long 0x00 "ARB_RW4_DR,Endpoint Data Register" hexmask.long.byte 0x00 0.--7. 1. "DR,Data Register for EP This register is linked to the memory hence reset value is undefined" group.long 0x2F0++0x03 line.long 0x00 "DMA_THRES,DMA Burst / Threshold Configuration" hexmask.long.byte 0x00 0.--7. 1. "DMA_THS,DMA Threshold count" group.long 0x2F4++0x03 line.long 0x00 "DMA_THRES_MSB,DMA Burst / Threshold Configuration" bitfld.long 0x00 0. "DMA_THS_MSB,DMA Threshold count" "0,1" group.long 0x300++0x03 line.long 0x00 "ARB_EP5_CFG,Endpoint Configuration Register" bitfld.long 0x00 3. "RESET_PTR,Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction" "0: Do not Reset Pointer Krypton Backward..,1: Reset Pointer recommended value for reduction.." newline bitfld.long 0x00 2. "CRC_BYPASS,Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware" "0: No CRC bypass CRC bytes will be written to..,1: CRC Bypass Set CRC bytes will not be written.." newline bitfld.long 0x00 1. "DMA_REQ,Manual DMA Request for a particular (1 to 8) endpoint changing this field from 0 to 1 causes a DMA request to be generated" "0,1" newline bitfld.long 0x00 0. "IN_DATA_RDY,Indication that Endpoint Packet Data is Ready in Main memory" "0,1" group.long 0x304++0x03 line.long 0x00 "ARB_EP5_INT_EN,Endpoint Interrupt Enable Register" bitfld.long 0x00 5. "DMA_TERMIN_EN,Endpoint DMA Terminated Enable" "0,1" newline bitfld.long 0x00 4. "ERR_INT_EN,Endpoint Error in Transaction Interrupt Enable" "0,1" newline bitfld.long 0x00 3. "BUF_UNDER_EN,Endpoint Buffer Underflow Enable" "0,1" newline bitfld.long 0x00 2. "BUF_OVER_EN,Endpoint Buffer Overflow Enable" "0,1" newline bitfld.long 0x00 1. "DMA_GNT_EN,Endpoint DMA Grant Enable" "0,1" newline bitfld.long 0x00 0. "IN_BUF_FULL_EN,IN Endpoint Local Buffer Full Enable" "0,1" group.long 0x308++0x03 line.long 0x00 "ARB_EP5_SR,Endpoint Interrupt Enable Register" bitfld.long 0x00 5. "DMA_TERMIN,Endpoint DMA Terminated Interrupt" "0,1" newline bitfld.long 0x00 3. "BUF_UNDER,Endpoint Buffer Underflow Interrupt" "0,1" newline bitfld.long 0x00 2. "BUF_OVER,Endpoint Buffer Overflow Interrupt" "0,1" newline bitfld.long 0x00 1. "DMA_GNT,Endpoint DMA Grant Interrupt" "0,1" newline bitfld.long 0x00 0. "IN_BUF_FULL,IN Endpoint Local Buffer Full Interrupt" "0,1" group.long 0x310++0x03 line.long 0x00 "ARB_RW5_WA,Endpoint Write Address value" hexmask.long.byte 0x00 0.--7. 1. "WA,Write Address for EP" group.long 0x314++0x03 line.long 0x00 "ARB_RW5_WA_MSB,Endpoint Write Address value" bitfld.long 0x00 0. "WA_MSB,Write Address for EP" "0,1" group.long 0x318++0x03 line.long 0x00 "ARB_RW5_RA,Endpoint Read Address value" hexmask.long.byte 0x00 0.--7. 1. "RA,Read Address for EP" group.long 0x31C++0x03 line.long 0x00 "ARB_RW5_RA_MSB,Endpoint Read Address value" bitfld.long 0x00 0. "RA_MSB,Read Address for EP" "0,1" group.long 0x320++0x03 line.long 0x00 "ARB_RW5_DR,Endpoint Data Register" hexmask.long.byte 0x00 0.--7. 1. "DR,Data Register for EP This register is linked to the memory hence reset value is undefined" group.long 0x330++0x03 line.long 0x00 "BUS_RST_CNT,Bus Reset Count Register" bitfld.long 0x00 0.--3. "BUS_RST_CNT,Bus Reset Count Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x340++0x03 line.long 0x00 "ARB_EP6_CFG,Endpoint Configuration Register" bitfld.long 0x00 3. "RESET_PTR,Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction" "0: Do not Reset Pointer Krypton Backward..,1: Reset Pointer recommended value for reduction.." newline bitfld.long 0x00 2. "CRC_BYPASS,Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware" "0: No CRC bypass CRC bytes will be written to..,1: CRC Bypass Set CRC bytes will not be written.." newline bitfld.long 0x00 1. "DMA_REQ,Manual DMA Request for a particular (1 to 8) endpoint changing this field from 0 to 1 causes a DMA request to be generated" "0,1" newline bitfld.long 0x00 0. "IN_DATA_RDY,Indication that Endpoint Packet Data is Ready in Main memory" "0,1" group.long 0x344++0x03 line.long 0x00 "ARB_EP6_INT_EN,Endpoint Interrupt Enable Register" bitfld.long 0x00 5. "DMA_TERMIN_EN,Endpoint DMA Terminated Enable" "0,1" newline bitfld.long 0x00 4. "ERR_INT_EN,Endpoint Error in Transaction Interrupt Enable" "0,1" newline bitfld.long 0x00 3. "BUF_UNDER_EN,Endpoint Buffer Underflow Enable" "0,1" newline bitfld.long 0x00 2. "BUF_OVER_EN,Endpoint Buffer Overflow Enable" "0,1" newline bitfld.long 0x00 1. "DMA_GNT_EN,Endpoint DMA Grant Enable" "0,1" newline bitfld.long 0x00 0. "IN_BUF_FULL_EN,IN Endpoint Local Buffer Full Enable" "0,1" group.long 0x348++0x03 line.long 0x00 "ARB_EP6_SR,Endpoint Interrupt Enable Register" bitfld.long 0x00 5. "DMA_TERMIN,Endpoint DMA Terminated Interrupt" "0,1" newline bitfld.long 0x00 3. "BUF_UNDER,Endpoint Buffer Underflow Interrupt" "0,1" newline bitfld.long 0x00 2. "BUF_OVER,Endpoint Buffer Overflow Interrupt" "0,1" newline bitfld.long 0x00 1. "DMA_GNT,Endpoint DMA Grant Interrupt" "0,1" newline bitfld.long 0x00 0. "IN_BUF_FULL,IN Endpoint Local Buffer Full Interrupt" "0,1" group.long 0x350++0x03 line.long 0x00 "ARB_RW6_WA,Endpoint Write Address value" hexmask.long.byte 0x00 0.--7. 1. "WA,Write Address for EP" group.long 0x354++0x03 line.long 0x00 "ARB_RW6_WA_MSB,Endpoint Write Address value" bitfld.long 0x00 0. "WA_MSB,Write Address for EP" "0,1" group.long 0x358++0x03 line.long 0x00 "ARB_RW6_RA,Endpoint Read Address value" hexmask.long.byte 0x00 0.--7. 1. "RA,Read Address for EP" group.long 0x35C++0x03 line.long 0x00 "ARB_RW6_RA_MSB,Endpoint Read Address value" bitfld.long 0x00 0. "RA_MSB,Read Address for EP" "0,1" group.long 0x360++0x03 line.long 0x00 "ARB_RW6_DR,Endpoint Data Register" hexmask.long.byte 0x00 0.--7. 1. "DR,Data Register for EP This register is linked to the memory hence reset value is undefined" group.long 0x380++0x03 line.long 0x00 "ARB_EP7_CFG,Endpoint Configuration Register" bitfld.long 0x00 3. "RESET_PTR,Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction" "0: Do not Reset Pointer Krypton Backward..,1: Reset Pointer recommended value for reduction.." newline bitfld.long 0x00 2. "CRC_BYPASS,Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware" "0: No CRC bypass CRC bytes will be written to..,1: CRC Bypass Set CRC bytes will not be written.." newline bitfld.long 0x00 1. "DMA_REQ,Manual DMA Request for a particular (1 to 8) endpoint changing this field from 0 to 1 causes a DMA request to be generated" "0,1" newline bitfld.long 0x00 0. "IN_DATA_RDY,Indication that Endpoint Packet Data is Ready in Main memory" "0,1" group.long 0x384++0x03 line.long 0x00 "ARB_EP7_INT_EN,Endpoint Interrupt Enable Register" bitfld.long 0x00 5. "DMA_TERMIN_EN,Endpoint DMA Terminated Enable" "0,1" newline bitfld.long 0x00 4. "ERR_INT_EN,Endpoint Error in Transaction Interrupt Enable" "0,1" newline bitfld.long 0x00 3. "BUF_UNDER_EN,Endpoint Buffer Underflow Enable" "0,1" newline bitfld.long 0x00 2. "BUF_OVER_EN,Endpoint Buffer Overflow Enable" "0,1" newline bitfld.long 0x00 1. "DMA_GNT_EN,Endpoint DMA Grant Enable" "0,1" newline bitfld.long 0x00 0. "IN_BUF_FULL_EN,IN Endpoint Local Buffer Full Enable" "0,1" group.long 0x388++0x03 line.long 0x00 "ARB_EP7_SR,Endpoint Interrupt Enable Register" bitfld.long 0x00 5. "DMA_TERMIN,Endpoint DMA Terminated Interrupt" "0,1" newline bitfld.long 0x00 3. "BUF_UNDER,Endpoint Buffer Underflow Interrupt" "0,1" newline bitfld.long 0x00 2. "BUF_OVER,Endpoint Buffer Overflow Interrupt" "0,1" newline bitfld.long 0x00 1. "DMA_GNT,Endpoint DMA Grant Interrupt" "0,1" newline bitfld.long 0x00 0. "IN_BUF_FULL,IN Endpoint Local Buffer Full Interrupt" "0,1" group.long 0x390++0x03 line.long 0x00 "ARB_RW7_WA,Endpoint Write Address value" hexmask.long.byte 0x00 0.--7. 1. "WA,Write Address for EP" group.long 0x394++0x03 line.long 0x00 "ARB_RW7_WA_MSB,Endpoint Write Address value" bitfld.long 0x00 0. "WA_MSB,Write Address for EP" "0,1" group.long 0x398++0x03 line.long 0x00 "ARB_RW7_RA,Endpoint Read Address value" hexmask.long.byte 0x00 0.--7. 1. "RA,Read Address for EP" group.long 0x39C++0x03 line.long 0x00 "ARB_RW7_RA_MSB,Endpoint Read Address value" bitfld.long 0x00 0. "RA_MSB,Read Address for EP" "0,1" group.long 0x3A0++0x03 line.long 0x00 "ARB_RW7_DR,Endpoint Data Register" hexmask.long.byte 0x00 0.--7. 1. "DR,Data Register for EP This register is linked to the memory hence reset value is undefined" group.long 0x3C0++0x03 line.long 0x00 "ARB_EP8_CFG,Endpoint Configuration Register" bitfld.long 0x00 3. "RESET_PTR,Configuration Setting to Reset the RA and WA Pointers to their start values at the End of Packet transaction" "0: Do not Reset Pointer Krypton Backward..,1: Reset Pointer recommended value for reduction.." newline bitfld.long 0x00 2. "CRC_BYPASS,Configuration Setting to prevent CRC bytes from being written to memory and being read by firmware" "0: No CRC bypass CRC bytes will be written to..,1: CRC Bypass Set CRC bytes will not be written.." newline bitfld.long 0x00 1. "DMA_REQ,Manual DMA Request for a particular (1 to 8) endpoint changing this field from 0 to 1 causes a DMA request to be generated" "0,1" newline bitfld.long 0x00 0. "IN_DATA_RDY,Indication that Endpoint Packet Data is Ready in Main memory" "0,1" group.long 0x3C4++0x03 line.long 0x00 "ARB_EP8_INT_EN,Endpoint Interrupt Enable Register" bitfld.long 0x00 5. "DMA_TERMIN_EN,Endpoint DMA Terminated Enable" "0,1" newline bitfld.long 0x00 4. "ERR_INT_EN,Endpoint Error in Transaction Interrupt Enable" "0,1" newline bitfld.long 0x00 3. "BUF_UNDER_EN,Endpoint Buffer Underflow Enable" "0,1" newline bitfld.long 0x00 2. "BUF_OVER_EN,Endpoint Buffer Overflow Enable" "0,1" newline bitfld.long 0x00 1. "DMA_GNT_EN,Endpoint DMA Grant Enable" "0,1" newline bitfld.long 0x00 0. "IN_BUF_FULL_EN,IN Endpoint Local Buffer Full Enable" "0,1" group.long 0x3C8++0x03 line.long 0x00 "ARB_EP8_SR,Endpoint Interrupt Enable Register" bitfld.long 0x00 5. "DMA_TERMIN,Endpoint DMA Terminated Interrupt" "0,1" newline bitfld.long 0x00 3. "BUF_UNDER,Endpoint Buffer Underflow Interrupt" "0,1" newline bitfld.long 0x00 2. "BUF_OVER,Endpoint Buffer Overflow Interrupt" "0,1" newline bitfld.long 0x00 1. "DMA_GNT,Endpoint DMA Grant Interrupt" "0,1" newline bitfld.long 0x00 0. "IN_BUF_FULL,IN Endpoint Local Buffer Full Interrupt" "0,1" group.long 0x3D0++0x03 line.long 0x00 "ARB_RW8_WA,Endpoint Write Address value" hexmask.long.byte 0x00 0.--7. 1. "WA,Write Address for EP" group.long 0x3D4++0x03 line.long 0x00 "ARB_RW8_WA_MSB,Endpoint Write Address value" bitfld.long 0x00 0. "WA_MSB,Write Address for EP" "0,1" group.long 0x3D8++0x03 line.long 0x00 "ARB_RW8_RA,Endpoint Read Address value" hexmask.long.byte 0x00 0.--7. 1. "RA,Read Address for EP" group.long 0x3DC++0x03 line.long 0x00 "ARB_RW8_RA_MSB,Endpoint Read Address value" bitfld.long 0x00 0. "RA_MSB,Read Address for EP" "0,1" group.long 0x3E0++0x03 line.long 0x00 "ARB_RW8_DR,Endpoint Data Register" hexmask.long.byte 0x00 0.--7. 1. "DR,Data Register for EP This register is linked to the memory hence reset value is undefined" repeat 512. (increment 0 1) (increment 0 0x04) group.long ($2+0x400)++0x03 line.long 0x00 "MEM_DATA[$1],DATA $1" hexmask.long.byte 0x00 0.--7. 1. "DR,Data Register for EP This register is linked to the memory hence reset value is undefined" repeat.end rgroup.long 0x1060++0x03 line.long 0x00 "SOF16,Start Of Frame Register" hexmask.long.word 0x00 0.--10. 1. "FRAME_NUMBER16,The frame number (11b)" rgroup.long 0x1080++0x03 line.long 0x00 "OSCLK_DR16,Oscillator lock data register" hexmask.long.word 0x00 0.--14. 1. "ADDER16,These bits return the oscillator locking circuits adder output" group.long 0x1210++0x03 line.long 0x00 "ARB_RW1_WA16,Endpoint Write Address value" hexmask.long.word 0x00 0.--8. 1. "WA16,Write Address for EP" group.long 0x1218++0x03 line.long 0x00 "ARB_RW1_RA16,Endpoint Read Address value" hexmask.long.word 0x00 0.--8. 1. "RA16,Read Address for EP" group.long 0x1220++0x03 line.long 0x00 "ARB_RW1_DR16,Endpoint Data Register" hexmask.long.word 0x00 0.--15. 1. "DR16,Data Register for EP This register is linked to the memory hence reset value is undefined" group.long 0x1250++0x03 line.long 0x00 "ARB_RW2_WA16,Endpoint Write Address value" hexmask.long.word 0x00 0.--8. 1. "WA16,Write Address for EP" group.long 0x1258++0x03 line.long 0x00 "ARB_RW2_RA16,Endpoint Read Address value" hexmask.long.word 0x00 0.--8. 1. "RA16,Read Address for EP" group.long 0x1260++0x03 line.long 0x00 "ARB_RW2_DR16,Endpoint Data Register" hexmask.long.word 0x00 0.--15. 1. "DR16,Data Register for EP This register is linked to the memory hence reset value is undefined" group.long 0x1290++0x03 line.long 0x00 "ARB_RW3_WA16,Endpoint Write Address value" hexmask.long.word 0x00 0.--8. 1. "WA16,Write Address for EP" group.long 0x1298++0x03 line.long 0x00 "ARB_RW3_RA16,Endpoint Read Address value" hexmask.long.word 0x00 0.--8. 1. "RA16,Read Address for EP" group.long 0x12A0++0x03 line.long 0x00 "ARB_RW3_DR16,Endpoint Data Register" hexmask.long.word 0x00 0.--15. 1. "DR16,Data Register for EP This register is linked to the memory hence reset value is undefined" group.long 0x12B0++0x03 line.long 0x00 "CWA16,Common Area Write Address" hexmask.long.word 0x00 0.--8. 1. "CWA16,Write Address for Common Area" group.long 0x12D0++0x03 line.long 0x00 "ARB_RW4_WA16,Endpoint Write Address value" hexmask.long.word 0x00 0.--8. 1. "WA16,Write Address for EP" group.long 0x12D8++0x03 line.long 0x00 "ARB_RW4_RA16,Endpoint Read Address value" hexmask.long.word 0x00 0.--8. 1. "RA16,Read Address for EP" group.long 0x12E0++0x03 line.long 0x00 "ARB_RW4_DR16,Endpoint Data Register" hexmask.long.word 0x00 0.--15. 1. "DR16,Data Register for EP This register is linked to the memory hence reset value is undefined" group.long 0x12F0++0x03 line.long 0x00 "DMA_THRES16,DMA Burst / Threshold Configuration" hexmask.long.word 0x00 0.--8. 1. "DMA_THS16,DMA Threshold count" group.long 0x1310++0x03 line.long 0x00 "ARB_RW5_WA16,Endpoint Write Address value" hexmask.long.word 0x00 0.--8. 1. "WA16,Write Address for EP" group.long 0x1318++0x03 line.long 0x00 "ARB_RW5_RA16,Endpoint Read Address value" hexmask.long.word 0x00 0.--8. 1. "RA16,Read Address for EP" group.long 0x1320++0x03 line.long 0x00 "ARB_RW5_DR16,Endpoint Data Register" hexmask.long.word 0x00 0.--15. 1. "DR16,Data Register for EP This register is linked to the memory hence reset value is undefined" group.long 0x1350++0x03 line.long 0x00 "ARB_RW6_WA16,Endpoint Write Address value" hexmask.long.word 0x00 0.--8. 1. "WA16,Write Address for EP" group.long 0x1358++0x03 line.long 0x00 "ARB_RW6_RA16,Endpoint Read Address value" hexmask.long.word 0x00 0.--8. 1. "RA16,Read Address for EP" group.long 0x1360++0x03 line.long 0x00 "ARB_RW6_DR16,Endpoint Data Register" hexmask.long.word 0x00 0.--15. 1. "DR16,Data Register for EP This register is linked to the memory hence reset value is undefined" group.long 0x1390++0x03 line.long 0x00 "ARB_RW7_WA16,Endpoint Write Address value" hexmask.long.word 0x00 0.--8. 1. "WA16,Write Address for EP" group.long 0x1398++0x03 line.long 0x00 "ARB_RW7_RA16,Endpoint Read Address value" hexmask.long.word 0x00 0.--8. 1. "RA16,Read Address for EP" group.long 0x13A0++0x03 line.long 0x00 "ARB_RW7_DR16,Endpoint Data Register" hexmask.long.word 0x00 0.--15. 1. "DR16,Data Register for EP This register is linked to the memory hence reset value is undefined" group.long 0x13D0++0x03 line.long 0x00 "ARB_RW8_WA16,Endpoint Write Address value" hexmask.long.word 0x00 0.--8. 1. "WA16,Write Address for EP" group.long 0x13D8++0x03 line.long 0x00 "ARB_RW8_RA16,Endpoint Read Address value" hexmask.long.word 0x00 0.--8. 1. "RA16,Read Address for EP" group.long 0x13E0++0x03 line.long 0x00 "ARB_RW8_DR16,Endpoint Data Register" hexmask.long.word 0x00 0.--15. 1. "DR16,Data Register for EP This register is linked to the memory hence reset value is undefined" tree "BCD" group.long 0x2000++0x03 line.long 0x00 "POWER_CTRL,Power Control Register" bitfld.long 0x00 31. "ENABLE,Mast enable of PHY and Charger Detector" "0,1" newline bitfld.long 0x00 30. "ENABLE_CHGDET,Enables the charger detection circuitry" "0,1" newline bitfld.long 0x00 29. "ENABLE_DMO,Enables the signle ended receiver on D" "0,1" newline bitfld.long 0x00 28. "ENABLE_DPO,Enables the single ended receiver on D+" "0,1" newline bitfld.long 0x00 27. "ENABLE_RCVR,Enables the differential USB receiver" "0,1" newline bitfld.long 0x00 26. "ENABLE_VBUS_PULLDOWN,Enables the weak pull down on the VBUS default on to prevent floating node crow bar currents" "0,1" newline bitfld.long 0x00 25. "ENABLE_DM_PULLDOWN,Enables the ~15k pull down on the DM default off" "0,1" newline bitfld.long 0x00 5.--6. "CHDET_PWR_CTL,Power programmability for bandgap voltage buffer in the charger detect block" "0,1,2,3" newline bitfld.long 0x00 4. "ISOLATE,Isolates the PHY outputs" "0,1" newline bitfld.long 0x00 3. "SUSPEND_DEL,Delayed version of SUSPEND" "0,1" newline bitfld.long 0x00 2. "SUSPEND,Put PHY into Suspend mode" "0,1" newline bitfld.long 0x00 0.--1. "VBUS_VALID_OVR,Overrides the value received from the GPIO input buffer connected to VBUS" "0: Force vbus_valid=0,1: Force vbus_valid=1,2: Use vbus_valid signal from GPIO input,3: Use vbus_valid signal from PHY detector" group.long 0x2004++0x03 line.long 0x00 "CHGDET_CTRL,Charger Detection Control Register" rbitfld.long 0x00 31. "COMP_OUT,Output of the primary/secondary detection comparator" "0,1" newline bitfld.long 0x00 12.--13. "ADFT_CTRL,ADFT option to bring out buffered version of voltage reference input or adft intput to ADFT output (adft_out)" "0: Normal operating mode reference buffer used..,1: Use reference buffer to bring out voltage..,2: Illegal - do not use,3: Use reference buffer to bring out buffered.." newline bitfld.long 0x00 6. "DCD_SRC_EN,Enable the Data Contact Detect current source on D+" "0,1" newline bitfld.long 0x00 5. "REF_EN,Enable the primary/secondary reference driver" "0,1" newline bitfld.long 0x00 4. "REF_DM,Connect the primary/secondary detection reference driver to D" "0,1" newline bitfld.long 0x00 3. "REF_DP,Connect the primary/secondary detection reference driver to D+" "0,1" newline bitfld.long 0x00 2. "COMP_EN,Enable the primary/secondary detection comparator and current sink" "0,1" newline bitfld.long 0x00 1. "COMP_DM,Connect the primary/secondary detection comparator and current sink to D" "0,1" newline bitfld.long 0x00 0. "COMP_DP,Connect the primary/secondary detection comparator and current sink to D+" "0,1" group.long 0x2008++0x03 line.long 0x00 "USBIO_CTRL,USB IO Control Register" bitfld.long 0x00 3.--5. "DM_M,The GPIO Drive Mode for DM IO pad" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--2. "DM_P,The GPIO Drive Mode for DP IO pad" "0: Mode 0,1: Mode 1,2: Mode 2,?,4: Mode 4,?,6: Mode 6,?..." group.long 0x200C++0x03 line.long 0x00 "FLOW_CTRL,Flow Control Register" bitfld.long 0x00 7. "EP8_ERR_RESP,End Point 8 error response" "0,1" newline bitfld.long 0x00 6. "EP7_ERR_RESP,End Point 7 error response" "0,1" newline bitfld.long 0x00 5. "EP6_ERR_RESP,End Point 6 error response" "0,1" newline bitfld.long 0x00 4. "EP5_ERR_RESP,End Point 5 error response" "0,1" newline bitfld.long 0x00 3. "EP4_ERR_RESP,End Point 4 error response" "0,1" newline bitfld.long 0x00 2. "EP3_ERR_RESP,End Point 3 error response" "0,1" newline bitfld.long 0x00 1. "EP2_ERR_RESP,End Point 2 error response" "0,1" newline bitfld.long 0x00 0. "EP1_ERR_RESP,End Point 1 error response" "0: do nothing (backward compatibility mode),1: if this is an IN EP and an underflow occurs.." group.long 0x2010++0x03 line.long 0x00 "LPM_CTRL,LPM Control Register" bitfld.long 0x00 4. "SUB_RESP,Enable a STALL response for all undefined SubPIDs i.e" "0,1" newline bitfld.long 0x00 2. "NYET_EN,Allow firmware to choose which response to use for an LPM token (LPM_EN=1) when the device is NOT ready to go to the requested low power mode (LPM_ACK_RESP=0)" "0: a LPM token will get an NAK response..,1: a LPM token will get a NYET response" newline bitfld.long 0x00 1. "LPM_ACK_RESP,LPM ACK response enable (if LPM_EN=1) to allow firmware to refuse a low power request" "0: a LPM token will get a NYET or NAK (depending..,1: a LPM token will get an ACK response and the" newline bitfld.long 0x00 0. "LPM_EN,LPM enable" "0: Disabled LPM token will not get a response,1: Enable LPM token will get a handshake response" rgroup.long 0x2014++0x03 line.long 0x00 "LPM_STAT,LPM Status register" bitfld.long 0x00 4. "LPM_REMOTEWAKE," "0,1" newline bitfld.long 0x00 0.--3. "LPM_BESL,Best Effort Service Latency This value should match either the Baseline (DeepSleep) or Deep (Hibernate) BESL in the BOS descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x2020++0x03 line.long 0x00 "INTR_SIE,USB SOF BUS RESET and EP0 Interrupt Status" bitfld.long 0x00 4. "RESUME_INTR,Interrupt status for Resume" "0,1" newline bitfld.long 0x00 3. "LPM_INTR,Interrupt status for LPM (Link Power Management L1 entry)" "0,1" newline bitfld.long 0x00 2. "EP0_INTR,Interrupt status for EP0" "0,1" newline bitfld.long 0x00 1. "BUS_RESET_INTR,Interrupt status for BUS RESET" "0,1" newline bitfld.long 0x00 0. "SOF_INTR,Interrupt status for USB SOF" "0,1" group.long 0x2024++0x03 line.long 0x00 "INTR_SIE_SET,USB SOF BUS RESET and EP0 Interrupt Set" bitfld.long 0x00 4. "RESUME_INTR_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 3. "LPM_INTR_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 2. "EP0_INTR_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 1. "BUS_RESET_INTR_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1" newline bitfld.long 0x00 0. "SOF_INTR_SET,Write with '1' to set corresponding bit in interrupt request register" "0,1" group.long 0x2028++0x03 line.long 0x00 "INTR_SIE_MASK,USB SOF BUS RESET and EP0 Interrupt Mask" bitfld.long 0x00 4. "RESUME_INTR_MASK,Set to 1 to enable interrupt corresponding to interrupt request register" "0,1" newline bitfld.long 0x00 3. "LPM_INTR_MASK,Set to 1 to enable interrupt corresponding to interrupt request register" "0,1" newline bitfld.long 0x00 2. "EP0_INTR_MASK,Set to 1 to enable interrupt corresponding to interrupt request register" "0,1" newline bitfld.long 0x00 1. "BUS_RESET_INTR_MASK,Set to 1 to enable interrupt corresponding to interrupt request register" "0,1" newline bitfld.long 0x00 0. "SOF_INTR_MASK,Set to 1 to enable interrupt corresponding to interrupt request register" "0,1" rgroup.long 0x202C++0x03 line.long 0x00 "INTR_SIE_MASKED,USB SOF BUS RESET and EP0 Interrupt Masked" bitfld.long 0x00 4. "RESUME_INTR_MASKED,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 3. "LPM_INTR_MASKED,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 2. "EP0_INTR_MASKED,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 1. "BUS_RESET_INTR_MASKED,Logical and of corresponding request and mask bits" "0,1" newline bitfld.long 0x00 0. "SOF_INTR_MASKED,Logical and of corresponding request and mask bits" "0,1" group.long 0x2030++0x03 line.long 0x00 "INTR_LVL_SEL,Select interrupt level for each interrupt source" bitfld.long 0x00 30.--31. "EP8_LVL_SEL,EP8 Interrupt level select" "0,1,2,3" newline bitfld.long 0x00 28.--29. "EP7_LVL_SEL,EP7 Interrupt level select" "0,1,2,3" newline bitfld.long 0x00 26.--27. "EP6_LVL_SEL,EP6 Interrupt level select" "0,1,2,3" newline bitfld.long 0x00 24.--25. "EP5_LVL_SEL,EP5 Interrupt level select" "0,1,2,3" newline bitfld.long 0x00 22.--23. "EP4_LVL_SEL,EP4 Interrupt level select" "0,1,2,3" newline bitfld.long 0x00 20.--21. "EP3_LVL_SEL,EP3 Interrupt level select" "0,1,2,3" newline bitfld.long 0x00 18.--19. "EP2_LVL_SEL,EP2 Interrupt level select" "0,1,2,3" newline bitfld.long 0x00 16.--17. "EP1_LVL_SEL,EP1 Interrupt level select" "0,1,2,3" newline bitfld.long 0x00 14.--15. "ARB_EP_LVL_SEL,Arbiter Endpoint Interrupt level select" "0,1,2,3" newline bitfld.long 0x00 8.--9. "RESUME_LVL_SEL,Resume Interrupt level select" "0,1,2,3" newline bitfld.long 0x00 6.--7. "LPM_LVL_SEL,LPM Interrupt level select" "0,1,2,3" newline bitfld.long 0x00 4.--5. "EP0_LVL_SEL,EP0 Interrupt level select" "0,1,2,3" newline bitfld.long 0x00 2.--3. "BUS_RESET_LVL_SEL,BUS RESET Interrupt level select" "0,1,2,3" newline bitfld.long 0x00 0.--1. "SOF_LVL_SEL,USB SOF Interrupt level select" "0: High priority interrupt,1: Medium priority interrupt,2: Low priority interrupt,3: illegal" rgroup.long 0x2034++0x03 line.long 0x00 "INTR_CAUSE_HI,High priority interrupt Cause register" bitfld.long 0x00 15. "EP8_INTR,EP8 Interrupt" "0,1" newline bitfld.long 0x00 14. "EP7_INTR,EP7 Interrupt" "0,1" newline bitfld.long 0x00 13. "EP6_INTR,EP6 Interrupt" "0,1" newline bitfld.long 0x00 12. "EP5_INTR,EP5 Interrupt" "0,1" newline bitfld.long 0x00 11. "EP4_INTR,EP4 Interrupt" "0,1" newline bitfld.long 0x00 10. "EP3_INTR,EP3 Interrupt" "0,1" newline bitfld.long 0x00 9. "EP2_INTR,EP2 Interrupt" "0,1" newline bitfld.long 0x00 8. "EP1_INTR,EP1 Interrupt" "0,1" newline bitfld.long 0x00 7. "ARB_EP_INTR,Arbiter Endpoint Interrupt" "0,1" newline bitfld.long 0x00 4. "RESUME_INTR,Resume Interrupt" "0,1" newline bitfld.long 0x00 3. "LPM_INTR,LPM Interrupt" "0,1" newline bitfld.long 0x00 2. "EP0_INTR,EP0 Interrupt" "0,1" newline bitfld.long 0x00 1. "BUS_RESET_INTR,BUS RESET Interrupt" "0,1" newline bitfld.long 0x00 0. "SOF_INTR,USB SOF Interrupt" "0,1" rgroup.long 0x2038++0x03 line.long 0x00 "INTR_CAUSE_MED,Medium priority interrupt Cause register" bitfld.long 0x00 15. "EP8_INTR,EP8 Interrupt" "0,1" newline bitfld.long 0x00 14. "EP7_INTR,EP7 Interrupt" "0,1" newline bitfld.long 0x00 13. "EP6_INTR,EP6 Interrupt" "0,1" newline bitfld.long 0x00 12. "EP5_INTR,EP5 Interrupt" "0,1" newline bitfld.long 0x00 11. "EP4_INTR,EP4 Interrupt" "0,1" newline bitfld.long 0x00 10. "EP3_INTR,EP3 Interrupt" "0,1" newline bitfld.long 0x00 9. "EP2_INTR,EP2 Interrupt" "0,1" newline bitfld.long 0x00 8. "EP1_INTR,EP1 Interrupt" "0,1" newline bitfld.long 0x00 7. "ARB_EP_INTR,Arbiter Endpoint Interrupt" "0,1" newline bitfld.long 0x00 4. "RESUME_INTR,Resume Interrupt" "0,1" newline bitfld.long 0x00 3. "LPM_INTR,LPM Interrupt" "0,1" newline bitfld.long 0x00 2. "EP0_INTR,EP0 Interrupt" "0,1" newline bitfld.long 0x00 1. "BUS_RESET_INTR,BUS RESET Interrupt" "0,1" newline bitfld.long 0x00 0. "SOF_INTR,USB SOF Interrupt" "0,1" rgroup.long 0x203C++0x03 line.long 0x00 "INTR_CAUSE_LO,Low priority interrupt Cause register" bitfld.long 0x00 15. "EP8_INTR,EP8 Interrupt" "0,1" newline bitfld.long 0x00 14. "EP7_INTR,EP7 Interrupt" "0,1" newline bitfld.long 0x00 13. "EP6_INTR,EP6 Interrupt" "0,1" newline bitfld.long 0x00 12. "EP5_INTR,EP5 Interrupt" "0,1" newline bitfld.long 0x00 11. "EP4_INTR,EP4 Interrupt" "0,1" newline bitfld.long 0x00 10. "EP3_INTR,EP3 Interrupt" "0,1" newline bitfld.long 0x00 9. "EP2_INTR,EP2 Interrupt" "0,1" newline bitfld.long 0x00 8. "EP1_INTR,EP1 Interrupt" "0,1" newline bitfld.long 0x00 7. "ARB_EP_INTR,Arbiter Endpoint Interrupt" "0,1" newline bitfld.long 0x00 4. "RESUME_INTR,Resume Interrupt" "0,1" newline bitfld.long 0x00 3. "LPM_INTR,LPM Interrupt" "0,1" newline bitfld.long 0x00 2. "EP0_INTR,EP0 Interrupt" "0,1" newline bitfld.long 0x00 1. "BUS_RESET_INTR,BUS RESET Interrupt" "0,1" newline bitfld.long 0x00 0. "SOF_INTR,USB SOF Interrupt" "0,1" group.long 0x2070++0x03 line.long 0x00 "DFT_CTRL,DFT control" bitfld.long 0x00 8.--9. "ADFT_VREFOUT_SEL,Select ADFT connection for VREF_OUT" "0: no connections,1: Connect adft_vref_out output to amuxbusa..,2: Connect adft_vref_out output to amuxbusb,3: RSVD" newline bitfld.long 0x00 0.--2. "DDFT_SEL,DDFT select signal" "0: Nothing connected output 0,1: Single Ended output of DP,2: Single Ended output of DM,3: Differential Receiver output,4: Charger detect output,5: Vbus detect output,?..." group.long 0x2F00++0x03 line.long 0x00 "PHY_TRIM0,PHY trim control register" bitfld.long 0x00 0.--5. "TRIM_DP_R_REG,Trim control for D+ pin poly termination resistors when PHY is in regulated mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x2F04++0x03 line.long 0x00 "PHY_TRIM1,PHY trim control register" bitfld.long 0x00 0.--5. "TRIM_DM_R_REG,Trim control for D- pin poly termination resistors when PHY is in regulated mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x2F08++0x03 line.long 0x00 "PHY_TRIM2,PHY trim control register" bitfld.long 0x00 0.--5. "TRIM_DP_R_BYPASS,Trim control for D+ pin poly termination resistors when PHY is in bypass mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x2F0C++0x03 line.long 0x00 "PHY_TRIM3,PHY trim control register" bitfld.long 0x00 0.--5. "TRIM_DM_R_BYPASS,Trim control for D- pin poly termination resistors when PHY is in bypass mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x2F10++0x03 line.long 0x00 "CHGDET_TRIM,Charger detect trim values" bitfld.long 0x00 4.--6. "V600M_TRIM,Trim bits for 600mV voltage reference" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 0.--1. "V325M_TRIM,Trim bits for 325mV voltage reference" "0,1,2,3" group.long 0x2F14++0x03 line.long 0x00 "TRIM,trim values" bitfld.long 0x00 0.--1. "DM_PD_VAL,Trim bit for DM Pull Down register to get resistance value close enough to 15kohm" "0,1,2,3" group.long 0x2F18++0x03 line.long 0x00 "USBIO_TRIM,trim values for IOs" bitfld.long 0x00 5. "X_DEC,This bit enables a decrease of the USB crossover voltage" "0,1" newline bitfld.long 0x00 4. "X_INC,This bit enables a increase of the USB crossover voltage" "0,1" newline bitfld.long 0x00 3. "MINC,When set this bit increases the USB edge matching ratio" "0,1" newline bitfld.long 0x00 2. "MDEC,When set this bit decreases the USB edge matching ratio" "0,1" newline bitfld.long 0x00 0.--1. "TRIM,These two bits of trim are for the suspend mode resistor" "0: No effect,1: Lower idle voltage,2: Higher idle voltage,3: TRIM_DONT_USE" tree.end endif tree.end endif autoindent.off newline