; --------------------------------------------------------------------------------
; @Title: NUC505 On-Chip Peripherals
; @Props: Released
; @Author: NEJ
; @Changelog: 2022-03-03 NEJ
; @Manufacturer: NUVOTON - Nuvoton Technology Corp.
; @Doc: SVD generated, based on: NUC505_v1.svd (Ver. 1.0)
; @Core: Cortex-M4F
; @Chip: NUC505DL13Y, NUC505DLA, NUC505DS13Y, NUC505DSA, NUC505YLA,
;        NUC505YLA2Y, NUC505YO13Y
; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: pernuc505.per 14447 2022-03-04 09:47:28Z kwisniewski $

tree.close "Core Registers (Cortex-M4F)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "System Control"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 12.
group.long 0x08++0x03
line.long 0x00 "ACTLR,Auxiliary Control Register"
bitfld.long 0x00 9. " DISFPCA        ,Disables lazy stacking of floating point context" "No,Yes"
bitfld.long 0x00 8. "                   DISOOFP        ,Disables floating point instructions completing" "No,Yes"
bitfld.long 0x00 2. "              DISFOLD         ,Disables folding of IT instructions" "No,Yes"
textline "                     "
bitfld.long 0x00 1. " DISDEFWBUF     ,Disables write buffer use during default memory map accesses" "No,Yes"
bitfld.long 0x00 0. "                   DISMCYCINT     ,Disables interruption of multi-cycle instructions" "No,Yes"
group.long 0x10++0x0B
line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
rbitfld.long 0x00 16. " COUNTFLAG      ,Counter Flag" "Not counted,Counted"
bitfld.long 0x00 2. "           CLKSOURCE      ,SysTick clock source" "External,Core"
bitfld.long 0x00 1. "         TICKINT         ,SysTick Handler" "No SysTick,SysTick"
textline "                     "
bitfld.long 0x00 0. " ENABLE         ,Counter Enable" "Disabled,Enabled"
line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD         ,The value to load into the SYST_CVR when the counter reaches 0"
line.long 0x08 "SYST_CVR,SysTick Current Value Register"
rgroup.long 0x1C++0x03
line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF          ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
bitfld.long 0x00 30. "       SKEW           ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
hexmask.long.tbyte 0x00 0.--23. 1. "          TENMS           ,Holds a reload value to be used for 10ms (100Hz) timing"
rgroup.long 0xD00++0x03
line.long 0x00 "CPUID,CPU ID Base Register"
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER    ,Implementer Code"
bitfld.long 0x00 20.--23. "                    VARIANT        ,Indicates processor revision" "Revision 0,?..."
bitfld.long 0x00 16.--19. "       ARCHITECTURE    ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                     "
hexmask.long.word 0x00 4.--15. 1. " PARTNO         ,Indicates part number"
bitfld.long 0x00 0.--3. "                  REVISION       ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xD04++0x23
line.long 0x00 "ICSR,Interrupt Control State Register"
bitfld.long 0x00 31. " NMIPENDSET     ,Set Pending NMI Bit" "Inactive,Active"
bitfld.long 0x00 28. "              PENDSVSET      ,Set Pending pendSV Bit" "Not pending,Pending"
bitfld.long 0x00 27. "      PENDSVCLR       ,Removes the pending status of the PendSV exception" "No effect,Removed"
textline "                     "
bitfld.long 0x00 26. " PENDSTSET      ,Set Pending SysTick Bit" "Not pending,Pending"
bitfld.long 0x00 25. "           PENDSTCLR      ,Clear Pending SysTick Bit" "No effect,Removed"
bitfld.long 0x00 23. "        ISRPREEMPT      ,Use Only at Debug Time" "Not active,Active"
textline "                     "
bitfld.long 0x00 22. " ISRPENDING     ,Indicates whether an external interrupt" "Not pending,Pending"
hexmask.long.word 0x00 12.--20. 1. "           VECTPENDING    ,Pending ISR Number Field"
bitfld.long 0x00 11. "             RETTOBASE       ,Interrupt Exception" "Active,Not active"
textline "                     "
hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE     ,The exception number of the current executing exception"
line.long 0x04 "VTOR,Vector Table Offset Register"
hexmask.long 0x04 7.--31. 0x80 " TBLOFF         ,Vector table address"
line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x08 16.--31. 1. " VECTKEY        ,Register Key"
rbitfld.long 0x08 15. "                  ENDIANESS      ,Data endianness Bit" "Little,Big"
bitfld.long 0x08 8.--10. "           PRIGROUP        ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
textline "                     "
bitfld.long 0x08 2. " SYSRESETREQ    ,System Reset Request" "Not requested,Requested"
bitfld.long 0x08 1. "         VECTCLRACTIVE  ,Clear Active Vector Bit" "No effect,Clear"
bitfld.long 0x08 0. "        VECTRESET       ,System Reset" "No effect,Reset"
line.long 0x0C "SCR,System Control Register"
bitfld.long 0x0C 4. " SEVONPEND      ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x0C 2. "            SLEEPDEEP      ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
bitfld.long 0x0C 1. "   SLEEPONEXIT     ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
line.long 0x10 "CCR,Configuration Control Register"
bitfld.long 0x10 18. " BP             ,Branch prediction enable bit" "Disabled,Enabled"
bitfld.long 0x10 17. "              IC             ,Instruction cache enable bit" "Disabled,Enabled"
bitfld.long 0x10 16. "         DC              ,Cache enable bit" "Disabled,Enabled"
textline "                     "
bitfld.long 0x10 9. " STKALIGN       ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment"
bitfld.long 0x10 8. "  BFHFNMIGN      ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
bitfld.long 0x10 4. "         DIV_0_TRP       ,Trap Divide by Zero" "Disabled,Enabled"
textline "                     "
bitfld.long 0x10 3. " UNALIGN_TRP    ,Trap for Unaligned Access" "Disabled,Enabled"
bitfld.long 0x10 1. "              USERSETMPEND   ,Controls whether unprivileged software can access the STIR" "Denied,Allowed"
bitfld.long 0x10 0. "          NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
line.long 0x14 "SHPR1,SSystem Handler Priority Register 1"
hexmask.long.byte 0x14 24.--31. 1. " PRI_7          ,Priority of System Handler 7"
hexmask.long.byte 0x14 16.--23. 1. "                    PRI_6          ,Priority of system handler 6(UsageFault)"
hexmask.long.byte 0x14 8.--15. 1. "               PRI_5           ,Priority of system handler 5(BusFault)"
textline "                     "
hexmask.long.byte 0x14 0.--7. 1. " PRI_4          ,Priority of system handler 4(MemManage)"
line.long 0x18 "SHPR2,System Handler Priority Register 2"
hexmask.long.byte 0x18 24.--31. 1. " PRI_11         ,Priority of system handler 11(SVCall)"
hexmask.long.byte 0x18 16.--23. 1. "                    PRI_10         ,Priority of System Handler 10"
hexmask.long.byte 0x18 8.--15. 1. "               PRI_9           ,Priority of System Handler 9"
textline "                     "
hexmask.long.byte 0x18 0.--7. 1. " PRI_8          ,Priority of System Handler 8"
line.long 0x1C "SHPR3,System Handler Priority Register 3"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_15         ,Priority of System Handler 15(SysTick)"
hexmask.long.byte 0x1C 16.--23. 1. "                    PRI_14         ,Priority of System Handler 14(PendSV)"
hexmask.long.byte 0x1C 8.--15. 1. "               PRI_13          ,Priority of System Handler 13"
textline "                     "
hexmask.long.byte 0x1C 0.--7. 1. " PRI_12         ,Priority of System Handler 12(DebugMonitor)"
line.long 0x20 "SHCSR,System Handler Control and State Register"
bitfld.long 0x20 18. " USGFAULTENA    ,Enable UsageFault" "Disabled,Enabled"
bitfld.long 0x20 17. "              BUSFAULTENA    ,Enable BusFault" "Disabled,Enabled"
bitfld.long 0x20 16. "         MEMFAULTENA     ,Enable MemManage fault" "Disabled,Enabled"
textline "                     "
bitfld.long 0x20 15. " SVCALLPENDED   ,SVCall is pending" "Not pending,Pending"
bitfld.long 0x20 14. "           BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending"
bitfld.long 0x20 13. "      MEMFAULTPENDED  ,MemManage is pending" "Not pending,Pending"
textline "                     "
bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending"
bitfld.long 0x20 11. "           SYSTICKACT     ,SysTick is Active" "Not active,Active"
bitfld.long 0x20 10. "       PENDSVACT       ,PendSV is Active" "Not active,Active"
textline "                     "
bitfld.long 0x20 8. " MONITORACT     ,Monitor is Active" "Not active,Active"
bitfld.long 0x20 7. "            SVCALLACT      ,SVCall is Active" "Not active,Active"
bitfld.long 0x20 3. "       USGFAULTACT     ,UsageFault is Active" "Not active,Active"
textline "                     "
bitfld.long 0x20 1. " BUSFAULTACT    ,BusFault is Active" "Not active,Active"
bitfld.long 0x20 0. "            MEMFAULTACT    ,MemManage is Active" "Not active,Active"
group.byte 0xD28++0x1
line.byte 0x00 "MMFSR,MemManage Status Register"
bitfld.byte 0x00 7. "       MMARVALID      ,Address Valid Flag" "Not valid,Valid"
bitfld.byte 0x00 5. "             MLSPERR        ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
bitfld.byte 0x00 4. "     MSTKERR         ,tacking Access Violations" "Not occurred,Occurred"
textline "                     "
bitfld.byte 0x00 3. " MUNSTKERR      ,Unstack Access Violations" "Not occurred,Occurred"
bitfld.byte 0x00 1. "          DACCVIOL       ,Data Access Violation" "Not occurred,Occurred"
bitfld.byte 0x00 0. "     IACCVIOL        ,Instruction Access Violation" "Not occurred,Occurred"
line.byte 0x01 "BFSR,Bus Fault Status Register"
bitfld.byte 0x01 7. "       BFARVALID      ,Address Valid Flag" "Not valid,Valid"
bitfld.byte 0x01 5. "             LSPERR         ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
bitfld.byte 0x01 4. "     STKERR          ,Derived bus fault(exception entry)" "Not occurred,Occurred"
textline "                     "
bitfld.byte 0x01 3. " UNSTKERR       ,Derived bus fault(exception return)" "Not occurred,Occurred"
bitfld.byte 0x01 2. "          IMPRECISERR    ,Imprecise data access error" "Not occurred,Occurred"
bitfld.byte 0x01 1. "     PRECISERR       ,Precise data access error" "Not occurred,Occurred"
textline "                     "
bitfld.byte 0x01 0. " IBUSERR        ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
group.word 0xD2A++0x1
line.word 0x00 "USAFAULT,Usage Fault Status Register"
bitfld.word 0x00 9. "     DIVBYZERO      ,Divide by zero error" "No error,Error"
bitfld.word 0x00 8. "              UNALIGNED      ,Unaligned access error" "No error,Error"
bitfld.word 0x00 3. "         NOCP            ,A coprocessor access error" "No error,Error"
textline "                     "
bitfld.word 0x00 2. " INVPC          ,An integrity check error" "No error,Error"
bitfld.word 0x00 1. "              INVSTATE       ,Invalid Combination of EPSR and Instruction" "No error,Error"
bitfld.word 0x00 0. "         UNDEFINSTR      ,Undefined instruction error" "No error,Error"
group.long 0xD2C++0x07
line.long 0x00 "HFSR,Hard Fault Status Register"
bitfld.long 0x00 31. " DEBUGEVT       ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
bitfld.long 0x00 30. "          FORCED         ,Indicates that a fault with configurable priority" "Not occurred,Occurred"
bitfld.long 0x00 1. "     VECTTBL         ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
line.long 0x04 "DFSR,Debug Fault Status Register"
bitfld.long 0x04 4. " EXTERNAL       ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted"
bitfld.long 0x04 3. "          VCATCH         ,Vector Catch Flag" "Not occurred,Occurred"
bitfld.long 0x04 2. "     DWTTRAP         ,Indicates a debug event generated by the DWT" "Not occurred,Occurred"
textline "                     "
bitfld.long 0x04 1. " BKPT           ,BKPT Flag" "Not executed,Executed"
bitfld.long 0x04 0. "          HALTED         ,Indicates a debug event generated by either" "Not requested,Requested"
group.long 0xD34++0x0B
line.long 0x00 "MMFAR,MemManage Fault Address Register"
line.long 0x04 "BFAR,BusFault Address Register"
line.long 0x08 "AFSR,Auxiliary Fault Status Register"
group.long 0xD88++0x03
line.long 0x00 "CPACR,Coprocessor Access Control Register"
bitfld.long 0x00 22.--23. " CP11           ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access"
bitfld.long 0x00 20.--21. "       CP10           ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access"
bitfld.long 0x00 14.--15. "  CP7             ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access"
textline "                     "
bitfld.long 0x00 12.--13. " CP6            ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access"
bitfld.long 0x00 10.--11. "       CP5            ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access"
bitfld.long 0x00 8.--9. "  CP4             ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access"
textline "                     "
bitfld.long 0x00 6.--7. " CP3            ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access"
bitfld.long 0x00 4.--5. "       CP2            ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access"
bitfld.long 0x00 2.--3. "  CP1             ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access"
textline "                     "
bitfld.long 0x00 0.--1. " CP0            ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access"
wgroup.long 0xF00++0x03
line.long 0x00 "STIR,Software Trigger Interrupt Register"
hexmask.long.word 0x00 0.--8. 1. " INTID          ,Indicates the interrupt to be triggered"
width 10.
tree "Feature Registers"
rgroup.long 0xD40++0x0B
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
bitfld.long 0x00 4.--7. " STATE1    ,Thumb instruction set support" ",,,Supported,?..."
bitfld.long 0x00 0.--3. "              STATE0         ,ARM instruction set support" "Not supported,?..."
line.long 0x04 "ID_PFR1,Processor Feature Register 1"
bitfld.long 0x04 8.--11. " MPROF     ,M profile programmers' model" ",,2-stack,?..."
line.long 0x08 "ID_DFR0,Debug Feature Register 0"
bitfld.long 0x08 20.--23. " DBGMOD    ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
hgroup.long 0xD4C++0x03
hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
rgroup.long 0xD50++0x03
line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
bitfld.long 0x00 20.--23. " AUXREG    ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
bitfld.long 0x00 16.--19. "          TCMSUP         ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
bitfld.long 0x00 12.--15. "        SHRLEV    ,Indicates the number of shareability levels implemented" "Level 1,?..."
textline "                   "
bitfld.long 0x00 8.--11. " OUTMSHR   ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
bitfld.long 0x00 4.--7. "          PMSASUP        ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
hgroup.long 0xD54++0x03
hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
rgroup.long 0xD58++0x03
line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
bitfld.long 0x00 24.--27. " WFISTALL  ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
rgroup.long 0xD60++0x13
line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
bitfld.long 0x00 24.--27. " DIVIDE    ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
bitfld.long 0x00 20.--23. "          DEBUG          ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
bitfld.long 0x00 16.--19. "        COPROC    ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
textline "                   "
bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
bitfld.long 0x00 8.--11. "          BITFIELD       ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
bitfld.long 0x00 4.--7. "    BITCOUNT  ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
bitfld.long 0x04 20.--23. "          IMMEDIATE      ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
bitfld.long 0x04 16.--19. "  IFTHEN    ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
textline "                   "
bitfld.long 0x04 12.--15. " EXTEND    ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
bitfld.long 0x08 24.--27. " REVERSAL  ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
bitfld.long 0x08 20.--23. "   MULTU          ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
bitfld.long 0x08 16.--19. "    MULTS     ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
textline "                   "
bitfld.long 0x08 12.--15. " MULT      ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
bitfld.long 0x08 8.--11. "          MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
bitfld.long 0x08 4.--7. "  MEMHINT   ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
textline "                   "
bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
bitfld.long 0x0C 24.--27. " TRUENOP   ,Indicates the support for a true  NOP instruction" "Not supported,Supported,?..."
bitfld.long 0x0C 20.--23. "          THUMBCOPY      ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
bitfld.long 0x0C 16.--19. "        TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
textline "                   "
bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
bitfld.long 0x0C 8.--11. "          SVC            ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
bitfld.long 0x0C 4.--7. "        SIMD      ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
textline "                   "
bitfld.long 0x0C 0.--3. " SATURATE  ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
bitfld.long 0x10 24.--27. " PSR_M     ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
bitfld.long 0x10 20.--23. "          SYNCHPRIMFRAC  ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
bitfld.long 0x10 16.--19. "        BARRIER   ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
textline "                   "
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
bitfld.long 0x10 4.--7. "          WITHSHIFTS     ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
bitfld.long 0x10 0.--3. "        UNPRIV    ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
tree.end
width 6.
tree "CoreSight Identification Registers"
rgroup.long 0xFE0++0x0F
line.long 0x00 "PID0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "PID1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. "  Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "PID2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision      ,Revision"
bitfld.long 0x08 3. "  JEDEC          ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. "  JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0C "PID3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd        ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. "  CMB            ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "PID4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count         ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. "  JEP106_CC      ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "CID0,Component ID0 (Preamble)"
line.long 0x04 "CID1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC            ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. "  Preamble       ,Preamble"
line.long 0x08 "CID2,Component ID2"
line.long 0x0C "CID3,Component ID3"
tree.end
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Memory Protection Unit"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 15.
rgroup.long 0xD90++0x03
line.long 0x00 "MPU_TYPE,MPU Type Register"
bitfld.long 0x00 16.--23. " IREGION    ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
bitfld.long 0x00 8.--15. "               DREGION   ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
bitfld.long 0x00 0. "                    SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
group.long 0xD94++0x03
line.long 0x00 "MPU_CTRL,MPU Control Register"
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
bitfld.long 0x00 1. "         HFNMIENA  ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
bitfld.long 0x00 0. "          ENABLE   ,Enables the MPU" "Disabled,Enabled"
group.long 0xD98++0x03
line.long 0x00 "MPU_RNR,MPU Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. " REGION     ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
tree.close "MPU regions"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
group.long 0xD9C++0x03 "Region 0"
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
group.long 0xD9C++0x03 "Region 1"
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
group.long 0xD9C++0x03 "Region 2"
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
group.long 0xD9C++0x03 "Region 3"
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
group.long 0xD9C++0x03 "Region 4"
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
group.long 0xD9C++0x03 "Region 5"
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
group.long 0xD9C++0x03 "Region 6"
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
group.long 0xD9C++0x03 "Region 7"
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
group.long 0xD9C++0x03 "Region 8"
saveout 0xD98 %l 0x8
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x8
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
saveout 0xD98 %l 0x8
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x8
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
group.long 0xD9C++0x03 "Region 9"
saveout 0xD98 %l 0x9
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x9
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
saveout 0xD98 %l 0x9
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x9
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
group.long 0xD9C++0x03 "Region 10"
saveout 0xD98 %l 0xA
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xA
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
saveout 0xD98 %l 0xA
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xA
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
group.long 0xD9C++0x03 "Region 11"
saveout 0xD98 %l 0xB
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xB
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
saveout 0xD98 %l 0xB
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xB
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
group.long 0xD9C++0x03 "Region 12"
saveout 0xD98 %l 0xC
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xC
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
saveout 0xD98 %l 0xC
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xC
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
group.long 0xD9C++0x03 "Region 13"
saveout 0xD98 %l 0xD
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xD
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
saveout 0xD98 %l 0xD
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xD
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
group.long 0xD9C++0x03 "Region 14"
saveout 0xD98 %l 0xE
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xE
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
saveout 0xD98 %l 0xE
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xE
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
group.long 0xD9C++0x03 "Region 15"
saveout 0xD98 %l 0xF
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xF
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
saveout 0xD98 %l 0xF
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xF
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
textline "                        "
textline "                        "
endif
tree.end
width 0x0b
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Nested Vectored Interrupt Controller"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 6.
rgroup.long 0x04++0x03
line.long 0x00 "ICTR,Interrupt Controller Type Register"
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
tree "Interrupt Enable Registers"
width 23.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
group.long 0x100++0x03
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
group.long 0x100++0x7
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
group.long 0x100++0x0B
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
group.long 0x100++0x0F
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
group.long 0x100++0x13
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
group.long 0x100++0x17
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
group.long 0x100++0x1B
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 30. 0x18 30. 0x98 30. "  ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 29. 0x18 29. 0x98 29. "  ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 28. 0x18 28. 0x98 28. "  ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 27. 0x18 27. 0x98 27. "  ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 26. 0x18 26. 0x98 26. "  ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 24. 0x18 24. 0x98 24. "  ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 23. 0x18 23. 0x98 23. "  ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 22. 0x18 22. 0x98 22. "  ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 21. 0x18 21. 0x98 21. "  ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 20. 0x18 20. 0x98 20. "  ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 18. 0x18 18. 0x98 18. "  ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 17. 0x18 17. 0x98 17. "  ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 16. 0x18 16. 0x98 16. "  ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 15. 0x18 15. 0x98 15. "  ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 14. 0x18 14. 0x98 14. "  ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 12. 0x18 12. 0x98 12. "  ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 11. 0x18 11. 0x98 11. "  ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 10. 0x18 10. 0x98 10. "  ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 9. 0x18 9. 0x98 9. "  ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 8. 0x18 8. 0x98 8. "  ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 6. 0x18 6. 0x98 6. "  ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 5. 0x18 5. 0x98 5. "  ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 4. 0x18 4. 0x98 4. "  ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 3. 0x18 3. 0x98 3. "  ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 2. 0x18 2. 0x98 2. "  ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 0. 0x18 0. 0x98 0. "  ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
group.long 0x100++0x1F
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 30. 0x18 30. 0x98 30. "  ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 29. 0x18 29. 0x98 29. "  ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 28. 0x18 28. 0x98 28. "  ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 27. 0x18 27. 0x98 27. "  ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 26. 0x18 26. 0x98 26. "  ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 24. 0x18 24. 0x98 24. "  ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 23. 0x18 23. 0x98 23. "  ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 22. 0x18 22. 0x98 22. "  ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 21. 0x18 21. 0x98 21. "  ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 20. 0x18 20. 0x98 20. "  ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 18. 0x18 18. 0x98 18. "  ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 17. 0x18 17. 0x98 17. "  ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 16. 0x18 16. 0x98 16. "  ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 15. 0x18 15. 0x98 15. "  ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 14. 0x18 14. 0x98 14. "  ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 12. 0x18 12. 0x98 12. "  ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 11. 0x18 11. 0x98 11. "  ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 10. 0x18 10. 0x98 10. "  ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 9. 0x18 9. 0x98 9. "  ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 8. 0x18 8. 0x98 8. "  ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 6. 0x18 6. 0x98 6. "  ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 5. 0x18 5. 0x98 5. "  ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 4. 0x18 4. 0x98 4. "  ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 3. 0x18 3. 0x98 3. "  ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 2. 0x18 2. 0x98 2. "  ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 0. 0x18 0. 0x98 0. "  ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. "  ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. "  ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. "  ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. "  ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. "  ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. "  ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. "  ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. "  ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. "  ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. "  ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. "  ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. "  ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. "  ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x100++0x1F
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
endif
tree.end
tree "Interrupt Pending Registers"
width 23.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
group.long 0x200++0x03
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
group.long 0x200++0x07
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
group.long 0x200++0x0B
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
group.long 0x200++0x0F
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
group.long 0x200++0x13
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
group.long 0x200++0x17
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
group.long 0x200++0x1B
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 30. 0x18 30. 0x98 30. "  PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 29. 0x18 29. 0x98 29. "  PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 28. 0x18 28. 0x98 28. "  PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 27. 0x18 27. 0x98 27. "  PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 26. 0x18 26. 0x98 26. "  PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 24. 0x18 24. 0x98 24. "  PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 23. 0x18 23. 0x98 23. "  PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 22. 0x18 22. 0x98 22. "  PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 21. 0x18 21. 0x98 21. "  PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 20. 0x18 20. 0x98 20. "  PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 18. 0x18 18. 0x98 18. "  PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 17. 0x18 17. 0x98 17. "  PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 16. 0x18 16. 0x98 16. "  PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 15. 0x18 15. 0x98 15. "  PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 14. 0x18 14. 0x98 14. "  PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 12. 0x18 12. 0x98 12. "  PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 11. 0x18 11. 0x98 11. "  PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 10. 0x18 10. 0x98 10. "  PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 9. 0x18 9. 0x98 9. "  PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 8. 0x18 8. 0x98 8. "  PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 6. 0x18 6. 0x98 6. "  PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 5. 0x18 5. 0x98 5. "  PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 4. 0x18 4. 0x98 4. "  PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 3. 0x18 3. 0x98 3. "  PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 2. 0x18 2. 0x98 2. "  PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 0. 0x18 0. 0x98 0. "  PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
group.long 0x200++0x1F
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 30. 0x18 30. 0x98 30. "  PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 29. 0x18 29. 0x98 29. "  PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 28. 0x18 28. 0x98 28. "  PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 27. 0x18 27. 0x98 27. "  PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 26. 0x18 26. 0x98 26. "  PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 24. 0x18 24. 0x98 24. "  PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 23. 0x18 23. 0x98 23. "  PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 22. 0x18 22. 0x98 22. "  PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 21. 0x18 21. 0x98 21. "  PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 20. 0x18 20. 0x98 20. "  PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 18. 0x18 18. 0x98 18. "  PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 17. 0x18 17. 0x98 17. "  PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 16. 0x18 16. 0x98 16. "  PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 15. 0x18 15. 0x98 15. "  PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 14. 0x18 14. 0x98 14. "  PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 12. 0x18 12. 0x98 12. "  PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 11. 0x18 11. 0x98 11. "  PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 10. 0x18 10. 0x98 10. "  PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 9. 0x18 9. 0x98 9. "  PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 8. 0x18 8. 0x98 8. "  PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 6. 0x18 6. 0x98 6. "  PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 5. 0x18 5. 0x98 5. "  PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 4. 0x18 4. 0x98 4. "  PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 3. 0x18 3. 0x98 3. "  PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 2. 0x18 2. 0x98 2. "  PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 0. 0x18 0. 0x98 0. "  PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. "  PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. "  PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. "  PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. "  PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. "  PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. "  PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. "  PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. "  PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. "  PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. "  PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. "  PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. "  PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. "  PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x200++0x1F
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
endif
tree.end
tree "Interrupt Active Bit Registers"
width 9.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
rgroup.long 0x300++0x03
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
rgroup.long 0x300++0x07
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
rgroup.long 0x300++0x0B
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
rgroup.long 0x300++0x0F
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
rgroup.long 0x300++0x13
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
line.long 0x10 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
rgroup.long 0x300++0x17
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
line.long 0x10 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
line.long 0x14 "ACTIVE6,Active Bit Register 6"
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 30. "  ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 29. "  ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 28. "  ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 27. "  ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 26. "  ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 24. "  ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 23. "  ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 22. "  ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 21. "  ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 20. "  ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 18. "  ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 17. "  ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 16. "  ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 15. "  ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 14. "  ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 12. "  ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 11. "  ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 10. "  ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 9. "  ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 8. "  ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 6. "  ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 5. "  ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 4. "  ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 3. "  ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 2. "  ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 0. "  ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
rgroup.long 0x300++0x1B
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
line.long 0x10 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
line.long 0x14 "ACTIVE6,Active Bit Register 6"
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 30. "  ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 29. "  ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 28. "  ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 27. "  ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 26. "  ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 24. "  ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 23. "  ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 22. "  ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 21. "  ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 20. "  ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 18. "  ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 17. "  ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 16. "  ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 15. "  ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 14. "  ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 12. "  ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 11. "  ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 10. "  ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 9. "  ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 8. "  ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 6. "  ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 5. "  ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 4. "  ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 3. "  ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 2. "  ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 0. "  ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
line.long 0x18 "ACTIVE7,Active Bit Register 7"
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 30. "  ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 29. "  ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 28. "  ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 27. "  ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 26. "  ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 24. "  ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 23. "  ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 22. "  ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 21. "  ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 20. "  ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 18. "  ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 17. "  ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 16. "  ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 15. "  ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 14. "  ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 12. "  ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 11. "  ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 10. "  ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 9. "  ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 8. "  ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 6. "  ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 5. "  ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 4. "  ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 3. "  ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 2. "  ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 0. "  ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
rgroup.long 0x300++0x1F
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
line.long 0x10 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
line.long 0x14 "ACTIVE6,Active Bit Register 6"
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 30. "  ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 29. "  ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 28. "  ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 27. "  ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 26. "  ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 24. "  ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 23. "  ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 22. "  ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 21. "  ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 20. "  ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 18. "  ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 17. "  ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 16. "  ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 15. "  ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 14. "  ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 12. "  ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 11. "  ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 10. "  ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 9. "  ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 8. "  ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 6. "  ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 5. "  ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 4. "  ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 3. "  ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 2. "  ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 0. "  ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
line.long 0x18 "ACTIVE7,Active Bit Register 7"
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 30. "  ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 29. "  ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 28. "  ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 27. "  ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 26. "  ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 24. "  ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 23. "  ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 22. "  ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 21. "  ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 20. "  ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 18. "  ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 17. "  ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 16. "  ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 15. "  ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 14. "  ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 12. "  ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 11. "  ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 10. "  ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 9. "  ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 8. "  ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 6. "  ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 5. "  ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 4. "  ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 3. "  ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 2. "  ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 0. "  ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
line.long 0x1c "ACTIVE8,Active Bit Register 8"
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 14. "  ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 13. "  ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 12. "  ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 11. "  ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 10. "  ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 8. "  ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 7. "  ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 6. "  ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 5. "  ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 4. "  ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 2. "  ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 1. "  ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 0. "  ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x300++0x1F
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
endif
tree.end
tree "Interrupt Priority Registers"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
group.long 0x400++0x1F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
group.long 0x400++0x3F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
group.long 0x400++0x5F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
group.long 0x400++0x7F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
group.long 0x400++0x9F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
line.long 0x80 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x80 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x80 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x80 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x84 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x84 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x84 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x84 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x88 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x88 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x88 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x88 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0x8C "IPR35,Interrupt Priority Register"
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0x8C 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0x8C 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0x8C 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x90 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x90 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x90 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x90 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x94 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x94 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x94 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x94 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x98 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x98 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x98 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x98 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x9C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x9C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x9C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x9C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
group.long 0x400++0xBF
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
line.long 0x80 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x80 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x80 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x80 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x84 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x84 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x84 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x84 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x88 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x88 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x88 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x88 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0x8C "IPR35,Interrupt Priority Register"
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0x8C 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0x8C 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0x8C 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x90 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x90 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x90 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x90 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x94 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x94 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x94 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x94 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x98 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x98 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x98 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x98 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x9C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x9C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x9C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x9C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
line.long 0xA0 "IPR40,Interrupt Priority Register"
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
hexmask.long.byte 0xA0 16.--23. 1. "  PRI_162 ,Interrupt 162 Priority"
hexmask.long.byte 0xA0 8.--15. 1. "  PRI_161 ,Interrupt 161 Priority"
hexmask.long.byte 0xA0 0.--7. 1. "  PRI_160 ,Interrupt 160 Priority"
line.long 0xA4 "IPR41,Interrupt Priority Register"
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
hexmask.long.byte 0xA4 16.--23. 1. "  PRI_166 ,Interrupt 166 Priority"
hexmask.long.byte 0xA4 8.--15. 1. "  PRI_165 ,Interrupt 165 Priority"
hexmask.long.byte 0xA4 0.--7. 1. "  PRI_164 ,Interrupt 164 Priority"
line.long 0xA8 "IPR42,Interrupt Priority Register"
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
hexmask.long.byte 0xA8 16.--23. 1. "  PRI_170 ,Interrupt 170 Priority"
hexmask.long.byte 0xA8 8.--15. 1. "  PRI_169 ,Interrupt 169 Priority"
hexmask.long.byte 0xA8 0.--7. 1. "  PRI_168 ,Interrupt 168 Priority"
line.long 0xAC "IPR43,Interrupt Priority Register"
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
hexmask.long.byte 0xAC 16.--23. 1. "  PRI_174 ,Interrupt 174 Priority"
hexmask.long.byte 0xAC 8.--15. 1. "  PRI_173 ,Interrupt 173 Priority"
hexmask.long.byte 0xAC 0.--7. 1. "  PRI_172 ,Interrupt 172 Priority"
line.long 0xB0 "IPR44,Interrupt Priority Register"
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
hexmask.long.byte 0xB0 16.--23. 1. "  PRI_178 ,Interrupt 178 Priority"
hexmask.long.byte 0xB0 8.--15. 1. "  PRI_177 ,Interrupt 177 Priority"
hexmask.long.byte 0xB0 0.--7. 1. "  PRI_176 ,Interrupt 176 Priority"
line.long 0xB4 "IPR45,Interrupt Priority Register"
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
hexmask.long.byte 0xB4 16.--23. 1. "  PRI_182 ,Interrupt 182 Priority"
hexmask.long.byte 0xB4 8.--15. 1. "  PRI_181 ,Interrupt 181 Priority"
hexmask.long.byte 0xB4 0.--7. 1. "  PRI_180 ,Interrupt 180 Priority"
line.long 0xB8 "IPR46,Interrupt Priority Register"
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
hexmask.long.byte 0xB8 16.--23. 1. "  PRI_186 ,Interrupt 186 Priority"
hexmask.long.byte 0xB8 8.--15. 1. "  PRI_185 ,Interrupt 185 Priority"
hexmask.long.byte 0xB8 0.--7. 1. "  PRI_184 ,Interrupt 184 Priority"
line.long 0xBC "IPR47,Interrupt Priority Register"
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
hexmask.long.byte 0xBC 16.--23. 1. "  PRI_190 ,Interrupt 190 Priority"
hexmask.long.byte 0xBC 8.--15. 1. "  PRI_189 ,Interrupt 189 Priority"
hexmask.long.byte 0xBC 0.--7. 1. "  PRI_188 ,Interrupt 188 Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
group.long 0x400++0xDF
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
line.long 0x80 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x80 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x80 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x80 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x84 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x84 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x84 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x84 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x88 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x88 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x88 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x88 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0x8C "IPR35,Interrupt Priority Register"
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0x8C 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0x8C 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0x8C 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x90 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x90 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x90 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x90 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x94 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x94 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x94 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x94 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x98 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x98 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x98 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x98 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x9C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x9C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x9C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x9C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
line.long 0xA0 "IPR40,Interrupt Priority Register"
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
hexmask.long.byte 0xA0 16.--23. 1. "  PRI_162 ,Interrupt 162 Priority"
hexmask.long.byte 0xA0 8.--15. 1. "  PRI_161 ,Interrupt 161 Priority"
hexmask.long.byte 0xA0 0.--7. 1. "  PRI_160 ,Interrupt 160 Priority"
line.long 0xA4 "IPR41,Interrupt Priority Register"
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
hexmask.long.byte 0xA4 16.--23. 1. "  PRI_166 ,Interrupt 166 Priority"
hexmask.long.byte 0xA4 8.--15. 1. "  PRI_165 ,Interrupt 165 Priority"
hexmask.long.byte 0xA4 0.--7. 1. "  PRI_164 ,Interrupt 164 Priority"
line.long 0xA8 "IPR42,Interrupt Priority Register"
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
hexmask.long.byte 0xA8 16.--23. 1. "  PRI_170 ,Interrupt 170 Priority"
hexmask.long.byte 0xA8 8.--15. 1. "  PRI_169 ,Interrupt 169 Priority"
hexmask.long.byte 0xA8 0.--7. 1. "  PRI_168 ,Interrupt 168 Priority"
line.long 0xAC "IPR43,Interrupt Priority Register"
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
hexmask.long.byte 0xAC 16.--23. 1. "  PRI_174 ,Interrupt 174 Priority"
hexmask.long.byte 0xAC 8.--15. 1. "  PRI_173 ,Interrupt 173 Priority"
hexmask.long.byte 0xAC 0.--7. 1. "  PRI_172 ,Interrupt 172 Priority"
line.long 0xB0 "IPR44,Interrupt Priority Register"
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
hexmask.long.byte 0xB0 16.--23. 1. "  PRI_178 ,Interrupt 178 Priority"
hexmask.long.byte 0xB0 8.--15. 1. "  PRI_177 ,Interrupt 177 Priority"
hexmask.long.byte 0xB0 0.--7. 1. "  PRI_176 ,Interrupt 176 Priority"
line.long 0xB4 "IPR45,Interrupt Priority Register"
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
hexmask.long.byte 0xB4 16.--23. 1. "  PRI_182 ,Interrupt 182 Priority"
hexmask.long.byte 0xB4 8.--15. 1. "  PRI_181 ,Interrupt 181 Priority"
hexmask.long.byte 0xB4 0.--7. 1. "  PRI_180 ,Interrupt 180 Priority"
line.long 0xB8 "IPR46,Interrupt Priority Register"
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
hexmask.long.byte 0xB8 16.--23. 1. "  PRI_186 ,Interrupt 186 Priority"
hexmask.long.byte 0xB8 8.--15. 1. "  PRI_185 ,Interrupt 185 Priority"
hexmask.long.byte 0xB8 0.--7. 1. "  PRI_184 ,Interrupt 184 Priority"
line.long 0xBC "IPR47,Interrupt Priority Register"
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
hexmask.long.byte 0xBC 16.--23. 1. "  PRI_190 ,Interrupt 190 Priority"
hexmask.long.byte 0xBC 8.--15. 1. "  PRI_189 ,Interrupt 189 Priority"
hexmask.long.byte 0xBC 0.--7. 1. "  PRI_188 ,Interrupt 188 Priority"
line.long 0xC0 "IPR48,Interrupt Priority Register"
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
hexmask.long.byte 0xC0 16.--23. 1. "  PRI_194 ,Interrupt 194 Priority"
hexmask.long.byte 0xC0 8.--15. 1. "  PRI_193 ,Interrupt 193 Priority"
hexmask.long.byte 0xC0 0.--7. 1. "  PRI_192 ,Interrupt 192 Priority"
line.long 0xC4 "IPR49,Interrupt Priority Register"
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
hexmask.long.byte 0xC4 16.--23. 1. "  PRI_198 ,Interrupt 198 Priority"
hexmask.long.byte 0xC4 8.--15. 1. "  PRI_197 ,Interrupt 197 Priority"
hexmask.long.byte 0xC4 0.--7. 1. "  PRI_196 ,Interrupt 196 Priority"
line.long 0xC8 "IPR50,Interrupt Priority Register"
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
hexmask.long.byte 0xC8 16.--23. 1. "  PRI_202 ,Interrupt 202 Priority"
hexmask.long.byte 0xC8 8.--15. 1. "  PRI_201 ,Interrupt 201 Priority"
hexmask.long.byte 0xC8 0.--7. 1. "  PRI_200 ,Interrupt 200 Priority"
line.long 0xCC "IPR51,Interrupt Priority Register"
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
hexmask.long.byte 0xCC 16.--23. 1. "  PRI_206 ,Interrupt 206 Priority"
hexmask.long.byte 0xCC 8.--15. 1. "  PRI_205 ,Interrupt 205 Priority"
hexmask.long.byte 0xCC 0.--7. 1. "  PRI_204 ,Interrupt 204 Priority"
line.long 0xD0 "IPR52,Interrupt Priority Register"
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
hexmask.long.byte 0xD0 16.--23. 1. "  PRI_210 ,Interrupt 210 Priority"
hexmask.long.byte 0xD0 8.--15. 1. "  PRI_209 ,Interrupt 209 Priority"
hexmask.long.byte 0xD0 0.--7. 1. "  PRI_208 ,Interrupt 208 Priority"
line.long 0xD4 "IPR53,Interrupt Priority Register"
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
hexmask.long.byte 0xD4 16.--23. 1. "  PRI_214 ,Interrupt 214 Priority"
hexmask.long.byte 0xD4 8.--15. 1. "  PRI_213 ,Interrupt 213 Priority"
hexmask.long.byte 0xD4 0.--7. 1. "  PRI_212 ,Interrupt 212 Priority"
line.long 0xD8 "IPR54,Interrupt Priority Register"
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
hexmask.long.byte 0xD8 16.--23. 1. "  PRI_218 ,Interrupt 218 Priority"
hexmask.long.byte 0xD8 8.--15. 1. "  PRI_217 ,Interrupt 217 Priority"
hexmask.long.byte 0xD8 0.--7. 1. "  PRI_216 ,Interrupt 216 Priority"
line.long 0xDC "IPR55,Interrupt Priority Register"
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
hexmask.long.byte 0xDC 16.--23. 1. "  PRI_222 ,Interrupt 222 Priority"
hexmask.long.byte 0xDC 8.--15. 1. "  PRI_221 ,Interrupt 221 Priority"
hexmask.long.byte 0xDC 0.--7. 1. "  PRI_220 ,Interrupt 220 Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
group.long 0x400++0xEF
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2 ,Interrupt 2 Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1 ,Interrupt 1 Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0 ,Interrupt 0 Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6 ,Interrupt 6 Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5 ,Interrupt 5 Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4 ,Interrupt 4 Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10 ,Interrupt 10 Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9 ,Interrupt 9 Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8 ,Interrupt 8 Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14 ,Interrupt 14 Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13 ,Interrupt 13 Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12 ,Interrupt 12 Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18 ,Interrupt 18 Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17 ,Interrupt 17 Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16 ,Interrupt 16 Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22 ,Interrupt 22 Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21 ,Interrupt 21 Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20 ,Interrupt 20 Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26 ,Interrupt 26 Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25 ,Interrupt 25 Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24 ,Interrupt 24 Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30 ,Interrupt 30 Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29 ,Interrupt 29 Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28 ,Interrupt 28 Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34 ,Interrupt 34 Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33 ,Interrupt 33 Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32 ,Interrupt 32 Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38 ,Interrupt 38 Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37 ,Interrupt 37 Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36 ,Interrupt 36 Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42 ,Interrupt 42 Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41 ,Interrupt 41 Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40 ,Interrupt 40 Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46 ,Interrupt 46 Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45 ,Interrupt 45 Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44 ,Interrupt 44 Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50 ,Interrupt 50 Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49 ,Interrupt 49 Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48 ,Interrupt 48 Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54 ,Interrupt 54 Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53 ,Interrupt 53 Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52 ,Interrupt 52 Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58 ,Interrupt 58 Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57 ,Interrupt 57 Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56 ,Interrupt 56 Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62 ,Interrupt 62 Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61 ,Interrupt 61 Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60 ,Interrupt 60 Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66 ,Interrupt 66 Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65 ,Interrupt 65 Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64 ,Interrupt 64 Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70 ,Interrupt 70 Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69 ,Interrupt 69 Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68 ,Interrupt 68 Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74 ,Interrupt 74 Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73 ,Interrupt 73 Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72 ,Interrupt 72 Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78 ,Interrupt 78 Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77 ,Interrupt 77 Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76 ,Interrupt 76 Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82 ,Interrupt 82 Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81 ,Interrupt 81 Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80 ,Interrupt 80 Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86 ,Interrupt 86 Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85 ,Interrupt 85 Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84 ,Interrupt 84 Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90 ,Interrupt 90 Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89 ,Interrupt 89 Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88 ,Interrupt 88 Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94 ,Interrupt 94 Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93 ,Interrupt 93 Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92 ,Interrupt 92 Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98 ,Interrupt 98 Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97 ,Interrupt 97 Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96 ,Interrupt 96 Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
line.long 0x80 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x80 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x80 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x80 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x84 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x84 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x84 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x84 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x88 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x88 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x88 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x88 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0x8C "IPR35,Interrupt Priority Register"
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0x8C 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0x8C 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0x8C 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x90 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x90 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x90 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x90 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x94 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x94 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x94 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x94 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x98 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x98 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x98 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x98 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x9C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x9C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x9C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x9C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
line.long 0xA0 "IPR40,Interrupt Priority Register"
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
hexmask.long.byte 0xA0 16.--23. 1. "  PRI_162 ,Interrupt 162 Priority"
hexmask.long.byte 0xA0 8.--15. 1. "  PRI_161 ,Interrupt 161 Priority"
hexmask.long.byte 0xA0 0.--7. 1. "  PRI_160 ,Interrupt 160 Priority"
line.long 0xA4 "IPR41,Interrupt Priority Register"
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
hexmask.long.byte 0xA4 16.--23. 1. "  PRI_166 ,Interrupt 166 Priority"
hexmask.long.byte 0xA4 8.--15. 1. "  PRI_165 ,Interrupt 165 Priority"
hexmask.long.byte 0xA4 0.--7. 1. "  PRI_164 ,Interrupt 164 Priority"
line.long 0xA8 "IPR42,Interrupt Priority Register"
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
hexmask.long.byte 0xA8 16.--23. 1. "  PRI_170 ,Interrupt 170 Priority"
hexmask.long.byte 0xA8 8.--15. 1. "  PRI_169 ,Interrupt 169 Priority"
hexmask.long.byte 0xA8 0.--7. 1. "  PRI_168 ,Interrupt 168 Priority"
line.long 0xAC "IPR43,Interrupt Priority Register"
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
hexmask.long.byte 0xAC 16.--23. 1. "  PRI_174 ,Interrupt 174 Priority"
hexmask.long.byte 0xAC 8.--15. 1. "  PRI_173 ,Interrupt 173 Priority"
hexmask.long.byte 0xAC 0.--7. 1. "  PRI_172 ,Interrupt 172 Priority"
line.long 0xB0 "IPR44,Interrupt Priority Register"
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
hexmask.long.byte 0xB0 16.--23. 1. "  PRI_178 ,Interrupt 178 Priority"
hexmask.long.byte 0xB0 8.--15. 1. "  PRI_177 ,Interrupt 177 Priority"
hexmask.long.byte 0xB0 0.--7. 1. "  PRI_176 ,Interrupt 176 Priority"
line.long 0xB4 "IPR45,Interrupt Priority Register"
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
hexmask.long.byte 0xB4 16.--23. 1. "  PRI_182 ,Interrupt 182 Priority"
hexmask.long.byte 0xB4 8.--15. 1. "  PRI_181 ,Interrupt 181 Priority"
hexmask.long.byte 0xB4 0.--7. 1. "  PRI_180 ,Interrupt 180 Priority"
line.long 0xB8 "IPR46,Interrupt Priority Register"
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
hexmask.long.byte 0xB8 16.--23. 1. "  PRI_186 ,Interrupt 186 Priority"
hexmask.long.byte 0xB8 8.--15. 1. "  PRI_185 ,Interrupt 185 Priority"
hexmask.long.byte 0xB8 0.--7. 1. "  PRI_184 ,Interrupt 184 Priority"
line.long 0xBC "IPR47,Interrupt Priority Register"
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
hexmask.long.byte 0xBC 16.--23. 1. "  PRI_190 ,Interrupt 190 Priority"
hexmask.long.byte 0xBC 8.--15. 1. "  PRI_189 ,Interrupt 189 Priority"
hexmask.long.byte 0xBC 0.--7. 1. "  PRI_188 ,Interrupt 188 Priority"
line.long 0xC0 "IPR48,Interrupt Priority Register"
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
hexmask.long.byte 0xC0 16.--23. 1. "  PRI_194 ,Interrupt 194 Priority"
hexmask.long.byte 0xC0 8.--15. 1. "  PRI_193 ,Interrupt 193 Priority"
hexmask.long.byte 0xC0 0.--7. 1. "  PRI_192 ,Interrupt 192 Priority"
line.long 0xC4 "IPR49,Interrupt Priority Register"
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
hexmask.long.byte 0xC4 16.--23. 1. "  PRI_198 ,Interrupt 198 Priority"
hexmask.long.byte 0xC4 8.--15. 1. "  PRI_197 ,Interrupt 197 Priority"
hexmask.long.byte 0xC4 0.--7. 1. "  PRI_196 ,Interrupt 196 Priority"
line.long 0xC8 "IPR50,Interrupt Priority Register"
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
hexmask.long.byte 0xC8 16.--23. 1. "  PRI_202 ,Interrupt 202 Priority"
hexmask.long.byte 0xC8 8.--15. 1. "  PRI_201 ,Interrupt 201 Priority"
hexmask.long.byte 0xC8 0.--7. 1. "  PRI_200 ,Interrupt 200 Priority"
line.long 0xCC "IPR51,Interrupt Priority Register"
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
hexmask.long.byte 0xCC 16.--23. 1. "  PRI_206 ,Interrupt 206 Priority"
hexmask.long.byte 0xCC 8.--15. 1. "  PRI_205 ,Interrupt 205 Priority"
hexmask.long.byte 0xCC 0.--7. 1. "  PRI_204 ,Interrupt 204 Priority"
line.long 0xD0 "IPR52,Interrupt Priority Register"
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
hexmask.long.byte 0xD0 16.--23. 1. "  PRI_210 ,Interrupt 210 Priority"
hexmask.long.byte 0xD0 8.--15. 1. "  PRI_209 ,Interrupt 209 Priority"
hexmask.long.byte 0xD0 0.--7. 1. "  PRI_208 ,Interrupt 208 Priority"
line.long 0xD4 "IPR53,Interrupt Priority Register"
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
hexmask.long.byte 0xD4 16.--23. 1. "  PRI_214 ,Interrupt 214 Priority"
hexmask.long.byte 0xD4 8.--15. 1. "  PRI_213 ,Interrupt 213 Priority"
hexmask.long.byte 0xD4 0.--7. 1. "  PRI_212 ,Interrupt 212 Priority"
line.long 0xD8 "IPR54,Interrupt Priority Register"
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
hexmask.long.byte 0xD8 16.--23. 1. "  PRI_218 ,Interrupt 218 Priority"
hexmask.long.byte 0xD8 8.--15. 1. "  PRI_217 ,Interrupt 217 Priority"
hexmask.long.byte 0xD8 0.--7. 1. "  PRI_216 ,Interrupt 216 Priority"
line.long 0xDC "IPR55,Interrupt Priority Register"
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
hexmask.long.byte 0xDC 16.--23. 1. "  PRI_222 ,Interrupt 222 Priority"
hexmask.long.byte 0xDC 8.--15. 1. "  PRI_221 ,Interrupt 221 Priority"
hexmask.long.byte 0xDC 0.--7. 1. "  PRI_220 ,Interrupt 220 Priority"
line.long 0xE0 "IPR56,Interrupt Priority Register"
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
hexmask.long.byte 0xE0 16.--23. 1. "  PRI_226 ,Interrupt 226 Priority"
hexmask.long.byte 0xE0 8.--15. 1. "  PRI_225 ,Interrupt 225 Priority"
hexmask.long.byte 0xE0 0.--7. 1. "  PRI_224 ,Interrupt 224 Priority"
line.long 0xE4 "IPR57,Interrupt Priority Register"
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
hexmask.long.byte 0xE4 16.--23. 1. "  PRI_230 ,Interrupt 230 Priority"
hexmask.long.byte 0xE4 8.--15. 1. "  PRI_229 ,Interrupt 229 Priority"
hexmask.long.byte 0xE4 0.--7. 1. "  PRI_228 ,Interrupt 228 Priority"
line.long 0xE8 "IPR58,Interrupt Priority Register"
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
hexmask.long.byte 0xE8 16.--23. 1. "  PRI_234 ,Interrupt 234 Priority"
hexmask.long.byte 0xE8 8.--15. 1. "  PRI_233 ,Interrupt 233 Priority"
hexmask.long.byte 0xE8 0.--7. 1. "  PRI_232 ,Interrupt 232 Priority"
line.long 0xEC "IPR59,Interrupt Priority Register"
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
hexmask.long.byte 0xEC 16.--23. 1. "  PRI_238 ,Interrupt 238 Priority"
hexmask.long.byte 0xEC 8.--15. 1. "  PRI_237 ,Interrupt 237 Priority"
hexmask.long.byte 0xEC 0.--7. 1. "  PRI_236 ,Interrupt 236 Priority"
else
hgroup.long 0x400++0xEF
hide.long 0x0 "IPR0,Interrupt Priority Register"
hide.long 0x4 "IPR1,Interrupt Priority Register"
hide.long 0x8 "IPR2,Interrupt Priority Register"
hide.long 0xC "IPR3,Interrupt Priority Register"
hide.long 0x10 "IPR4,Interrupt Priority Register"
hide.long 0x14 "IPR5,Interrupt Priority Register"
hide.long 0x18 "IPR6,Interrupt Priority Register"
hide.long 0x1C "IPR7,Interrupt Priority Register"
hide.long 0x20 "IPR8,Interrupt Priority Register"
hide.long 0x24 "IPR9,Interrupt Priority Register"
hide.long 0x28 "IPR10,Interrupt Priority Register"
hide.long 0x2C "IPR11,Interrupt Priority Register"
hide.long 0x30 "IPR12,Interrupt Priority Register"
hide.long 0x34 "IPR13,Interrupt Priority Register"
hide.long 0x38 "IPR14,Interrupt Priority Register"
hide.long 0x3C "IPR15,Interrupt Priority Register"
hide.long 0x40 "IPR16,Interrupt Priority Register"
hide.long 0x44 "IPR17,Interrupt Priority Register"
hide.long 0x48 "IPR18,Interrupt Priority Register"
hide.long 0x4C "IPR19,Interrupt Priority Register"
hide.long 0x50 "IPR20,Interrupt Priority Register"
hide.long 0x54 "IPR21,Interrupt Priority Register"
hide.long 0x58 "IPR22,Interrupt Priority Register"
hide.long 0x5C "IPR23,Interrupt Priority Register"
hide.long 0x60 "IPR24,Interrupt Priority Register"
hide.long 0x64 "IPR25,Interrupt Priority Register"
hide.long 0x68 "IPR26,Interrupt Priority Register"
hide.long 0x6C "IPR27,Interrupt Priority Register"
hide.long 0x70 "IPR28,Interrupt Priority Register"
hide.long 0x74 "IPR29,Interrupt Priority Register"
hide.long 0x78 "IPR30,Interrupt Priority Register"
hide.long 0x7C "IPR31,Interrupt Priority Register"
hide.long 0x80 "IPR32,Interrupt Priority Register"
hide.long 0x84 "IPR33,Interrupt Priority Register"
hide.long 0x88 "IPR34,Interrupt Priority Register"
hide.long 0x8C "IPR35,Interrupt Priority Register"
hide.long 0x90 "IPR36,Interrupt Priority Register"
hide.long 0x94 "IPR37,Interrupt Priority Register"
hide.long 0x98 "IPR38,Interrupt Priority Register"
hide.long 0x9C "IPR39,Interrupt Priority Register"
hide.long 0xA0 "IPR40,Interrupt Priority Register"
hide.long 0xA4 "IPR41,Interrupt Priority Register"
hide.long 0xA8 "IPR42,Interrupt Priority Register"
hide.long 0xAC "IPR43,Interrupt Priority Register"
hide.long 0xB0 "IPR44,Interrupt Priority Register"
hide.long 0xB4 "IPR45,Interrupt Priority Register"
hide.long 0xB8 "IPR46,Interrupt Priority Register"
hide.long 0xBC "IPR47,Interrupt Priority Register"
hide.long 0xC0 "IPR48,Interrupt Priority Register"
hide.long 0xC4 "IPR49,Interrupt Priority Register"
hide.long 0xC8 "IPR50,Interrupt Priority Register"
hide.long 0xCC "IPR51,Interrupt Priority Register"
hide.long 0xD0 "IPR52,Interrupt Priority Register"
hide.long 0xD4 "IPR53,Interrupt Priority Register"
hide.long 0xD8 "IPR54,Interrupt Priority Register"
hide.long 0xDC "IPR55,Interrupt Priority Register"
hide.long 0xE0 "IPR56,Interrupt Priority Register"
hide.long 0xE4 "IPR57,Interrupt Priority Register"
hide.long 0xE8 "IPR58,Interrupt Priority Register"
hide.long 0xEC "IPR59,Interrupt Priority Register"
endif
tree.end
width 0x0b
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
sif CORENAME()=="CORTEXM4F"
tree "Floating-point Unit (FPU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 8.
group.long 0xF34++0x0B
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
bitfld.long 0x00 31. " ASPEN        ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
bitfld.long 0x00 30. "                      LSPEN    ,Enables lazy context save of FP state" "Disabled,Enabled"
bitfld.long 0x00 8. "       MONRDY  ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
textline "                 "
bitfld.long 0x00 6. " BFRDY        ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
bitfld.long 0x00 5. "                      MMRDY    ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
bitfld.long 0x00 4. "       HFRDY   ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
textline "                 "
bitfld.long 0x00 3. " THREAD       ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
bitfld.long 0x00 1. "                       USER     ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
bitfld.long 0x00 0. "   LSPACT  ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
hexmask.long 0x04 3.--31. 0x8 " ADDRESS      ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
bitfld.long 0x08 26. " AHP          ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
bitfld.long 0x08 25. "                 DN       ,Default value for FPSCR.DN" "NaN operands,Any operation"
bitfld.long 0x08 24. "  FZ      ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
textline "                 "
bitfld.long 0x08 22.--23. " RMODE        ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
rgroup.long 0xF40++0x07
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
bitfld.long 0x00 28.--31. " FPRNDMOD     ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
bitfld.long 0x00 24.--27. "                 SRTERR   ,Indicates the hardware support for FP short vectors" "Not supported,?..."
bitfld.long 0x00 20.--23. "  SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
textline "                 "
bitfld.long 0x00 16.--19. " DIV          ,Indicates the hardware support for FP divide operations" ",Supported,?..."
bitfld.long 0x00 12.--15. "                     FPEXTRP  ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..."
bitfld.long 0x00 8.--11. "  DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
textline "                 "
bitfld.long 0x00 4.--7. " SNGLPREC     ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
bitfld.long 0x00 0.--3. "                     A_SIMD   ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
bitfld.long 0x04 24.--27. "                     FP_HPFP  ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
textline "                 "
bitfld.long 0x04 4.--7. " D_NAN        ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
bitfld.long 0x04 0.--3. "               FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..."
width 0xB
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
endif
tree "Debug"
tree "Core Debug"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 7.
group.long 0xD30++0x03
line.long 0x00 "DFSR,Debug Fault Status Register"
eventfld.long 0x00 4. " EXTERNAL     ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
eventfld.long 0x00 3. "  VCATCH     ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
eventfld.long 0x00 2. "  DWTTRAP    ,Indicates a debug event generated by the DWT" "Not generated,Generated"
newline
eventfld.long 0x00 1. " BKPT         ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
eventfld.long 0x00 0. "  HALTED     ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
newline
hgroup.long 0xDF0++0x03
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
in
newline
wgroup.long 0xDF4++0x03
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
bitfld.long 0x00 16. " REGWNR       ,Register Read/Write" "Read,Write"
hexmask.long.byte 0x00 0.--6. 1. "          REGSEL     ,Specifies the ARM core register or special-purpose register or Floating-point extension register"
group.long 0xDF8++0x03
line.long 0x00 "DCRDR,Debug Core Register Data Register"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
group.long 0xDFC++0x03
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x00 24. " TRCENA       ,Global enable for all DWT and ITM features" "Disabled,Enabled"
bitfld.long 0x00 19. "       MON_REQ    ,DebugMonitor semaphore bit" "0,1"
bitfld.long 0x00 18. "              MON_STEP   ,Setting this bit to 1 makes the step request pending" "No step,Step"
newline
bitfld.long 0x00 17. " MON_PEND     ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
bitfld.long 0x00 16. "    MON_EN     ,Enable the DebugMonitor exception" "Disabled,Enabled"
bitfld.long 0x00 10. "       VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 9. " VC_INTERR    ,Enable halting debug trap" "Disabled,Enabled"
bitfld.long 0x00 8. "       VC_BUSERR  ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
bitfld.long 0x00 7. "       VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 6. " VC_CHKERR    ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
bitfld.long 0x00 5. "       VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
bitfld.long 0x00 4. "       VC_MMERR   ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
else
group.long 0xDFC++0x03
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x00 24. " TRCENA       ,Global enable for all DWT and ITM features" "Disabled,Enabled"
bitfld.long 0x00 19. "       MON_REQ    ,DebugMonitor semaphore bit" "0,1"
newline
bitfld.long 0x00 17. " MON_PEND     ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
bitfld.long 0x00 16. "    MON_EN     ,Enable the DebugMonitor exception" "Disabled,Enabled"
bitfld.long 0x00 10. "       VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 9. " VC_INTERR    ,Enable halting debug trap" "Disabled,Enabled"
bitfld.long 0x00 8. "       VC_BUSERR  ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
bitfld.long 0x00 7. "       VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 6. " VC_CHKERR    ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
bitfld.long 0x00 5. "       VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
bitfld.long 0x00 4. "       VC_MMERR   ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
endif
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Flash Patch and Breakpoint Unit (FPB)"
sif COMPonent.AVAILABLE("FPB")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
width 10.
group.long 0x00++0x07
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
bitfld.long 0x00 28.--31. " REV     ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..."
rbitfld.long 0x00 4.--7. 12.--14. "     NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
bitfld.long 0x00 1. "  KEY   ,Key Field" "Low,High"
bitfld.long 0x00 0. "      ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
textline ""
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
bitfld.long 0x04 29. " RMPSPT  ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region"
hexmask.long.tbyte 0x04 5.--28. 0x20 "               REMAP ,Remap Base Address Field"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x8++0x03
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
group.long 0x8++0x03
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x8++0x03
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0xC++0x03
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
group.long 0xC++0x03
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0xC++0x03
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x10++0x03
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
group.long 0x10++0x03
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x10++0x03
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x14++0x03
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
group.long 0x14++0x03
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x14++0x03
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x18++0x03
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
group.long 0x18++0x03
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x18++0x03
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x1C++0x03
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
group.long 0x1C++0x03
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x1C++0x03
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x20++0x03
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
group.long 0x20++0x03
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x20++0x03
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x24++0x03
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
group.long 0x24++0x03
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x24++0x03
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
width 6.
tree "CoreSight Identification Registers"
rgroup.long 0xFE0++0x0F
line.long 0x00 "PID0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "PID1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. "  Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "PID2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision      ,Revision"
bitfld.long 0x08 3. "  JEDEC          ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. "  JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0c "PID3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd        ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. "  CMB            ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "PID4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count         ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. "  JEP106_CC      ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "CID0,Component ID0 (Preamble)"
line.long 0x04 "CID1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC            ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. "  Preamble       ,Preamble"
line.long 0x08 "CID2,Component ID2"
line.long 0x0c "CID3,Component ID3"
tree.end
width 0xB
else
newline
textline "FPB component base address not specified"
newline
endif
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
sif COMPonent.AVAILABLE("DWT")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
width 15.
group.long 0x00++0x1B
line.long 0x00 "DWT_CTRL,Control Register"
rbitfld.long 0x00 28.--31. " NUMCOMP     ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 27. "             NOTRCPKT   ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
rbitfld.long 0x00 26. "  NOEXTTRIG   ,Shows whether the implementation includes external match signals" "Supported,Not supported"
textline "                        "
rbitfld.long 0x00 25. " NOCYCCNT    ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
rbitfld.long 0x00 24. "  NOPRFCNT   ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
bitfld.long 0x00 22. "  CYCEVTENA   ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 21. " FOLDEVTENA  ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 20. "       LSUEVTENA  ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 19. "       SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 18. " EXCEVTENA   ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 17. "       CPIEVTENA  ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 16. "       EXCTRCENA   ,Enables generation of exception trace" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
bitfld.long 0x00 10.--11. "       SYNCTAP    ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
bitfld.long 0x00 9. "     CYCTAP      ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
textline "                        "
bitfld.long 0x00 5.--8. " POSTINIT    ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1.--4. "             POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "             CYCCNTENA   ,Enables CYCCNT" "Disabled,Enabled"
line.long 0x04 "DWT_CYCCNT,Cycle Count Register"
line.long 0x08 "DWT_CPICNT,CPI Count Register"
hexmask.long.byte 0x08 0.--7. 1. " CPICNT      ,The base CPI counter"
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT      ,The exception overhead counter"
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT    ,Sleep Counter"
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT      ,Load-store counter"
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register"
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT     ,Folded-instruction counter"
rgroup.long 0x1C++0x03
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
textline "                        "
group.long 0x20++0x07
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
line.long 0x04 "DWT_MASK0,DWT Mask Registers 0"
bitfld.long 0x04 0.--4. " MASK        ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20)
group.long 0x28++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH    ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
bitfld.long 0x00 5. "    EMITRANGE  ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION   ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00)
group.long 0x28++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH    ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
bitfld.long 0x00 5. "    EMITRANGE  ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION   ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80)
group.long 0x28++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH    ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
bitfld.long 0x00 5. "    EMITRANGE  ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION   ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
else
group.long 0x28++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH    ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
bitfld.long 0x00 5. "    EMITRANGE  ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION   ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
endif
group.long (0x30)++0x07
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
line.long 0x04 "DWT_MASK1,DWT Mask Registers 1"
bitfld.long 0x04 0.--4. " MASK        ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20)
group.long (0x30+0x08)++0x03
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00)
group.long (0x30+0x08)++0x03
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
else
group.long (0x30+0x08)++0x03
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
endif
group.long (0x40)++0x07
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
line.long 0x04 "DWT_MASK2,DWT Mask Registers 2"
bitfld.long 0x04 0.--4. " MASK        ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20)
group.long (0x40+0x08)++0x03
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00)
group.long (0x40+0x08)++0x03
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
else
group.long (0x40+0x08)++0x03
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
endif
group.long (0x50)++0x07
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
line.long 0x04 "DWT_MASK3,DWT Mask Registers 3"
bitfld.long 0x04 0.--4. " MASK        ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20)
group.long (0x50+0x08)++0x03
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00)
group.long (0x50+0x08)++0x03
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
else
group.long (0x50+0x08)++0x03
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
endif
width 6.
tree "CoreSight Identification Registers"
rgroup.long 0xFE0++0x0F
line.long 0x00 "PID0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "PID1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. "  Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "PID2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision      ,Revision"
bitfld.long 0x08 3. "  JEDEC          ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. "  JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0c "PID3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd        ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. "  CMB            ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "PID4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count         ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. "  JEP106_CC      ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "CID0,Component ID0 (Preamble)"
line.long 0x04 "CID1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC            ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. "  Preamble       ,Preamble"
line.long 0x08 "CID2,Component ID2"
line.long 0x0c "CID3,Component ID3"
tree.end
width 0x0B
else
newline
textline "DWT component base address not specified"
newline
endif
tree.end
tree.end
AUTOINDENT.POP
tree.end
autoindent.on center tree
tree "ADC"
base ad:0x400E2000
group.long 0x00++0x03
line.long 0x00 "ADC_CTL,ADC Control Register"
hexmask.long.byte 0x00 24.--31. 1. "EXTSMPT,ADC Extend Sampling Time \nWhen A/D converting at high conversion rate the sampling time of analog input voltage may not enough if the input channel loading is heavy software can extend A/D sampling time after trigger source is coming to get.."
bitfld.long 0x00 16.--18. "CHSEL,Analog Input Selection Signals\nNote1: ADC_CH0 is used for battery voltage detection" "0: ADC_CH0,1: ADC_CH1,2: ADC_CH2,3: ADC_CH3,4: ADC_CH4,5: ADC_CH5,6: ADC_CH6,7: ADC_CH7"
newline
bitfld.long 0x00 15. "PDKEY,Power Down Keypad Detection\n" "0: Power down keypad detection Disabled,1: Power down keypad detection Enabled"
bitfld.long 0x00 13. "PD,Power Down ADC \nNote1: ADC power must be enabled before a trigger to get the data.\nNote2: It needs 100ms to wait analog block stable when setting PD from 1 to 0" "0: ADC is in normal state,1: ADC is in power down state"
newline
bitfld.long 0x00 0. "SWTRG,A/D Conversion Start\nA trigger to start one A/D conversion process.\nNote: This bit will be cleared to '0' automatically" "0: A/D conversion enters idle state,1: Start conversion"
group.long 0x04++0x03
line.long 0x00 "ADC_INTCTL,ADC Interrupt State"
bitfld.long 0x00 9. "KEYIEN,Keypad Interrupt Enable Control\n" "0: Keypad down interrupt Disabled,1: Keypad down interrupt Enabled"
bitfld.long 0x00 8. "ADCIEN,ADC Interrupt Enable Control\n" "0: ADC conversion done interrupt Disabled,1: ADC conversion done interrupt Enabled"
newline
bitfld.long 0x00 1. "KEYIF,Keypad Interrupt Flag\nIn the process of checking keypad the KEYIF shows the state" "0: Keypad is not pressing state,1: keypad is pressing state"
bitfld.long 0x00 0. "ADCIF,ADC Conversion Done Interrupt Flag\nWhen finishing the sample process the ADCIF bit will be set" "0: ADC conversion done flag is not set,1: ADC conversion done flag is set"
rgroup.long 0x08++0x03
line.long 0x00 "ADC_DAT,ADC Data Register"
hexmask.long.word 0x00 0.--11. 1. "RESULT,A/D Conversion Result\nThis field contains conversion result of ADC"
tree.end
tree "CLKCTRL"
base ad:0x40000200
group.long 0x00++0x03
line.long 0x00 "CLK_PWRCTL,System Power-down Control Register"
bitfld.long 0x00 24. "PDWTCPU,Control Power-down Entry Condition\n" "0: Chip enters Power-down mode when the HXTEN..,1: Chip enters Power-down mode when the both.."
hexmask.long.word 0x00 8.--23. 1. "PDWKPSC,PDWKPSC Counter\nAssuming the HXT is stable after the PDWKPSC x 256 HXT cycles Clock controller would not output clock to system before the counter reaches (PDWKPSC x 256)"
newline
bitfld.long 0x00 3. "PDWKIEN,Power-down Mode Wake-up Interrupt Enable Control\nNote: The interrupt will occur when both PDWKIF and PDWKIEN are set" "0: Power-down Mode Wake-up Interrupt Disabled,1: Power-down Mode Wake-up Interrupt Enabled"
bitfld.long 0x00 2. "PDWKIF,Power-down Mode Wake-up Interrupt Flag\nSet by power down wake-up event indicates that resume from Power-down mode \nThe flag is set if the GPIO USBH USBD UART TIMER WDT RTC or I2C wake-up occurred.\nNote1: Write 1 to clear the bit to.." "0,1"
newline
bitfld.long 0x00 1. "HXTCTL,Power-down Mode Wake-up Pre-divider Counter Enable Control\nThe HXT pre-divider controls wake-up time from Power-down mode" "0: PDWKPSC counter Disabled,1: PDWKPSC counter Enabled"
bitfld.long 0x00 0. "HXTEN,Crystal (Power Down) Control\n" "0: Crystal off (Power down),1: Crystal on (Normal operation)"
group.long 0x04++0x03
line.long 0x00 "CLK_AHBCLK,AHB Devices Clock Enable Control Register"
bitfld.long 0x00 9. "USBHCKEN,USB Host Clock Enable Control\n" "0: USB Host Clock Disabled,1: USB Host Clock Enabled"
bitfld.long 0x00 6. "USBDCKEN,USB Device Clock Enable Control\n" "0: USB Device Clock Disabled,1: USB Device Clock Enabled"
newline
bitfld.long 0x00 5. "SDHCKEN,SDH Clock Enable Control\n" "0: SDH Clock Disabled,1: SDH Clock Enabled"
bitfld.long 0x00 3. "SPIMCKEN,SPIM Clock Enable Control\n" "0: SPIM Clock Disabled,1: SPIM Clock Enabled"
newline
bitfld.long 0x00 2. "ROMCKEN,ROM Clock Enable Control\n" "0: ROM Clock Disabled,1: ROM Clock Enabled"
bitfld.long 0x00 1. "SRAM23CKEN,SRAM#2 Clock Enable Control\n" "0: SRAM#2 Clock Disabled,1: SRAM#2 Clock Enabled"
newline
bitfld.long 0x00 0. "SRAM01CKEN,SRAM#1 Clock Enable Control\n" "0: SRAM#1 Clock Disabled,1: SRAM#1 Clock Enabled"
group.long 0x08++0x03
line.long 0x00 "CLK_APBCLK,APB Devices Clock Enable Control Register"
bitfld.long 0x00 15. "ADCCKEN,ADC Clock Enable Control\n" "0: ADC Clock Disabled,1: ADC Clock Enabled"
bitfld.long 0x00 14. "I2SCKEN,I2S Clock Enable Control\n" "0: I2S Clock Disabled,1: I2S Clock Enabled"
newline
bitfld.long 0x00 13. "UART2CKEN,UART2 Clock Enable Control\n" "0: UART2 Clock Disabled,1: UART2 Clock Enabled"
bitfld.long 0x00 12. "UART1CKEN,UART1 Clock Enable Control\n" "0: UART1 Clock Disabled,1: UART1 Clock Enabled"
newline
bitfld.long 0x00 11. "UART0CKEN,UART0 Clock Enable Control\n" "0: UART0 Clock Disabled,1: UART0 Clock Enabled"
bitfld.long 0x00 10. "SPI1CKEN,SPI1 Clock Enable Control\n" "0: SPI1 Clock Disabled,1: SPI1 Clock Enabled"
newline
bitfld.long 0x00 9. "SPI0CKEN,SPI0 Clock Enable Control\n" "0: SPI0 Clock Disabled,1: SPI0 Clock Enabled"
bitfld.long 0x00 8. "PWMCKEN,PWM Clock Enable Control\n" "0: PWM Clock Disabled,1: PWM Clock Enabled"
newline
bitfld.long 0x00 7. "RTCCKEN,RTC Clock Enable Control\n" "0: RTC Clock Disabled,1: RTC Clock Enabled"
bitfld.long 0x00 6. "I2C1CKEN,I2C1 Clock Enable Control\n" "0: I2C1 Clock Disabled,1: I2C1 Clock Enabled"
newline
bitfld.long 0x00 5. "I2C0CKEN,I2C0 Clock Enable Control\n" "0: I2C0 Clock Disabled,1: I2C0 Clock Enabled"
bitfld.long 0x00 4. "WDTCKEN,Watchdog Timer Clock Enable Control\n" "0: Watchdog Timer Clock Disabled,1: Watchdog Timer Clock Enabled"
newline
bitfld.long 0x00 3. "TMR3CKEN,TIMER3 Clock Enable Control\n" "0: TIMER3 Clock Disabled,1: TIMER3 Clock Enabled"
bitfld.long 0x00 2. "TMR2CKEN,TIMER2 Clock Enable Control\n" "0: TIMER2 Clock Disabled,1: TIMER2 Clock Enabled"
newline
bitfld.long 0x00 1. "TMR1CKEN,TIMER1 Clock Enable Control\n" "0: TIMER1 Clock Disabled,1: TIMER1 Clock Enabled"
bitfld.long 0x00 0. "TMR0CKEN,TIMER0 Clock Enable Control\n" "0: TIMER0 Clock Disabled,1: TIMER0 Clock Enabled"
group.long 0x10++0x03
line.long 0x00 "CLK_CLKDIV0,Clock Divider Number Control Register 0"
bitfld.long 0x00 24.--27. "USBHDIV,Defines the Clock Divider Number for USB Host\nThe actual clock divider number is (USBHDIV+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 23. "USBDSEL,USB Device Source Clock Select (USBD_SrcCLK)\n" "0: USB Device Clock source from HXT,1: USB Device Clock source from PLL_FOUT"
newline
bitfld.long 0x00 16.--20. "USBDDIV,Defines the Clock Divider Number for USB Device\nThe actual clock divider number is (USBDDIV+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--11. "PCLKDIV,Defines the Clock Divider Number for APB_CLK\nThe actual clock divider number is (PCLKDIV+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 7. "HCLKSEL,System Source Clock Select (SYS_SrcCLK)\n" "0: System Clock source from HXT,1: System Clock source from PLL_FOUT"
bitfld.long 0x00 0.--3. "HCLKDIV,Defines the Clock Divider Number for SYS_CLK\nThe actual clock divider number is (HCLKDIV+1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x14++0x03
line.long 0x00 "CLK_CLKDIV1,Clock Divider Number Control Register 1"
bitfld.long 0x00 30. "SDHSEL,SDH Clock Select (SDH_SrcCLK)\n" "0: SDH Clock source from HXT,1: SDH Clock source from PLL_FOUT"
bitfld.long 0x00 28. "ADCSEL,ADC Clock Select (ADC_SrcCLK)\n" "0: ADC Clock source from HXT,1: ADC Clock source from PLL_FOUT"
newline
hexmask.long.word 0x00 16.--26. 1. "SDHDIV,Defines the Clock Divider Number for SDH\nThe actual clock divider number is (SDHDIV+1)"
hexmask.long.byte 0x00 8.--15. 1. "STICKDIV,Defines the Clock Divider Number for SYS_TICK\nThe actual clock divider number is (STICKDIV+1)"
newline
hexmask.long.byte 0x00 0.--7. 1. "ADCDIV,Defines the Clock Divider Number for ADC\nThe actual clock divider number is (ADCDIV+1)"
group.long 0x18++0x03
line.long 0x00 "CLK_CLKDIV2,Clock Divider Number Control Register 2"
bitfld.long 0x00 29. "SPI1SEL,SPI1 Engine Clock Select (SPI1SEL)\n" "0: SPI1 Engine Clock source from HXT,1: SPI1 Engine Clock source from PLL_FOUT"
bitfld.long 0x00 28. "SPI0SEL,SPI0 Engine Clock Select (SPI0SEL)\n" "0: SPI0 Engine Clock source from HXT,1: SPI0 Engine Clock source from PLL_FOUT"
newline
bitfld.long 0x00 24.--25. "I2SSEL,I2S Clock Select (I2S_SrcCLK)\n" "0: I2S Clock source from HXT,1: I2S Clock source from PLL_FOUT,2: Reserved,3: I2S Clock source from APLL_FOUT"
hexmask.long.byte 0x00 0.--7. 1. "I2SDIV,Defines the Clock Divider Number for I2S\nThe actual clock divider number is (I2SDIV+1)"
group.long 0x1C++0x03
line.long 0x00 "CLK_CLKDIV3,Clock Divider Number Control Register 3"
bitfld.long 0x00 20. "UART2SEL,UART2 Source Clock Select (UART2_SrcCLK)\n" "0: UART2 Source Clock source from HXT,1: UART2 Source Clock source from PLL_FOUT"
bitfld.long 0x00 16.--19. "UART2DIV,Defines the Clock Divider Number for UART2\nThe actual clock divider number is (UART2DIV +1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 12. "UART1SEL,UART1 Source Clock Select (UART1_SrcCLK)\n" "0: UART1 Source Clock source from HXT,1: UART1 Source Clock source from PLL_FOUT"
bitfld.long 0x00 8.--11. "UART1DIV,Defines the Clock Divider Number for UART1\nThe actual clock divider number is (UART1DIV +1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4. "UART0SEL,UART0 Source Clock Select (UART0_SrcCLK)\n" "0: UART0 Source Clock source from HXT,1: UART0 Source Clock source from PLL_FOUT"
bitfld.long 0x00 0.--3. "UART0DIV,Defines the Clock Divider Number for UART0\nThe actual clock divider number is (UART0DIV +1)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x20++0x03
line.long 0x00 "CLK_PLLCTL,PLL Control Register"
bitfld.long 0x00 17. "PD,Power-down Mode\n" "0: PLL in Normal mode,1: PLL in Power-down mode (Default)"
bitfld.long 0x00 16. "BP,PLL Bypass Control\n" "0: PLL at Normal mode,1: Bypass Fin (i.e. Fout = XIN)"
newline
bitfld.long 0x00 13.--15. "OUTDIV,Output Divider Control (P) \nSet the output divider factor from 1 to 8" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 7.--12. "INDIV,Reference Input Divider (M)\nSet the input reference clock divider factor from 1 to 64" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.byte 0x00 0.--6. 1. "FBDIV,Feedback Divider Control (N)\nSet the feedback divider factor from 1 to 128"
group.long 0x28++0x03
line.long 0x00 "CLK_APLLCTL,APLL Control Register"
hexmask.long.word 0x00 20.--31. 1. "FRAC,Sigma-delta Modulator Control Pins \nSet the fractional number of the Feedback divider"
bitfld.long 0x00 18. "MODE,Mode Select \n" "0: Integer mode,1: Fraction mode"
newline
bitfld.long 0x00 16. "PD,Power Down Enable Control\n" "0: Power down Disabled,1: Power down Enabled"
bitfld.long 0x00 13.--15. "OUTDIV,Output Divider Control \nSet the Output divider factor from 1 to 8" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x00 6.--12. 1. "FBDIV,Feedback Divider Control \nSet the Feedback divider factor from 1 to 128"
bitfld.long 0x00 0.--5. "INDIV,Reference Input Divider Control \nSet the reference divider factor from 1 to 64" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x30++0x03
line.long 0x00 "CLK_CLKDIV4,Clock Divider Number Control Register 4"
bitfld.long 0x00 26. "TMR2SEL,Timer2 Engine Clock Select (TMR2_SrcCLK)\n" "0: Timer2 Engine Clock source from RTC_CLK,1: Timer2 Engine Clock source from HXT"
bitfld.long 0x00 25. "TMR1SEL,Timer1 Engine Clock Select (TMR1_SrcCLK)\n" "0: Timer1 Engine Clock source from RTC_CLK,1: Timer1 Engine Clock source from HXT"
newline
bitfld.long 0x00 24. "TMR0SEL,Timer0 Engine Clock Select (TMR0_SrcCLK)\n" "0: Timer0 Engine Clock source from RTC_CLK,1: Timer0 Engine Clock source from HXT"
hexmask.long.byte 0x00 16.--23. 1. "TMR2DIV,Defines the Clock Divider Number for TMR2\nThe actual clock divider number is (TMR2DIV+1)"
newline
hexmask.long.byte 0x00 8.--15. 1. "TMR1DIV,Defines the Clock Divider Number for TMR1\nThe actual clock divider number is (TMR1DIV+1)"
hexmask.long.byte 0x00 0.--7. 1. "TMR0DIV,Defines the Clock Divider Number for TMR0\nThe actual clock divider number is (TMR0DIV+1)"
group.long 0x34++0x03
line.long 0x00 "CLK_CLKDIV5,Clock Divider Number Control Register 5"
bitfld.long 0x00 26. "PWMSEL,PWM Engine Clock Select (PWM_SrcCLK)\n" "0: PWM Engine Clock source from HXT,1: PWM Engine Clock source from PLL_FOUT"
bitfld.long 0x00 25. "WDTSEL,WDT Engine Clock Select (WDT_SrcCLK)\n" "0: WDT Engine Clock source from RTC_CLK,1: WDT Engine Clock source from HXT"
newline
bitfld.long 0x00 24. "TMR3SEL,Timer3 Engine Clock Select (TMR3_SrcCLK)\n" "0: Timer3 Engine Clock source from RTC_CLK,1: Timer3 Engine Clock source from HXT"
hexmask.long.byte 0x00 16.--23. 1. "PWMDIV,Define the Clock Divider Number for PWM\nThe actual clock divider number is (PWMDIV+1)"
newline
hexmask.long.byte 0x00 8.--15. 1. "WDTDIV,Define the Clock Divider Number for WDT\nThe actual clock divider number is (WDTDIV+1)"
hexmask.long.byte 0x00 0.--7. 1. "TMR3DIV,Define the Clock Divider Number for TMR3\nThe actual clock divider number is (TM3DIV+1)"
tree.end
tree "GCR"
base ad:0x40000000
rgroup.long 0x00++0x03
line.long 0x00 "SYS_PDID,Part Device Identification Number Register"
hexmask.long.tbyte 0x00 0.--23. 1. "PDID,Part Device Identification Number (Read Only)\nThis register reflects device part number code"
group.long 0x04++0x03
line.long 0x00 "SYS_BOOTSET,System Power-on Configuration Register"
bitfld.long 0x00 0.--3. "BOOTSET,System Mode Configuration\nNote: If BOOTSET is equal to ICE Mode the software cannot change BOOTSET to other mode" "?,?,?,?,?,?,6: Boot from ICE Mode with external SPI Flash,7: Boot from ICE Mode with SPI Flash,?,?,?,11: Boot from ICP Mode,?,13: Boot from external SPI Flash,14: Boot from USB,15: Boot from SPI Flash"
group.long 0x08++0x03
line.long 0x00 "SYS_IPRST0,Peripheral Reset Control Register 0"
bitfld.long 0x00 1. "CHIPRST,Chip One-shot Reset\nSetting this bit will reset the whole chip including processor core and all peripherals and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIPRST is same as the POR reset all the chip controllers is.." "0: Chip normal operation,1: Chip one-shot reset"
bitfld.long 0x00 0. "CPURST,Processor Core One-shot Reset\nSetting this bit will only reset the processor core and this bit will automatically return to 0 after the 2 clock cycles.\n" "0: Processor core normal operation,1: Processor core one-shot reset"
group.long 0x0C++0x03
line.long 0x00 "SYS_LVDCTL,Low Voltage Detection Control Register"
bitfld.long 0x00 4. "PORENB,Power on Reset Enable Control\n" "0: Function Enabled,1: Function Disabled"
bitfld.long 0x00 3. "LVREN,Low Voltage Reset Enable Control\nNote: The voltage threshold level is 2.4V" "0: Low Voltage Reset Disabled,1: Low Voltage Reset Enabled"
newline
bitfld.long 0x00 2. "LVDEN,Low Voltage Detection Enable Control\n" "0: Detection Disabled,1: Detection Enabled"
bitfld.long 0x00 1. "LVDSEL,Low Voltage Detection Level Selection\n" "0: The threshold level is 2.6V,1: The threshold level is 2.8V"
newline
bitfld.long 0x00 0. "LVDIF,Low Voltage Detect Flag\nNote: This bit is useful when LVDEN is enabled" "0: Low voltage Period,1: Normal voltage Period"
group.long 0x10++0x03
line.long 0x00 "SYS_WAKEUP,Wake-up Control and Status Resister"
bitfld.long 0x00 29. "USBHWF,USB Host Wake-up Flag\nNote: Write 1 to clear this bit" "0: USB Host wake-up source is deasserted,1: USB Host wake-up source is asserted"
bitfld.long 0x00 28. "USBDWF,USB Device Wake-up Flag\nNote: Write 1 to clear this bit" "0: USB Device wake-up source is deasserted,1: USB Device wake-up source is asserted"
newline
bitfld.long 0x00 27. "UART2WF,UART2 Wake-up Flag\nNote: Write 1 to clear this bit" "0: UART2 wake-up source is deasserted,1: UART2 wake-up source is asserted"
bitfld.long 0x00 26. "UART1WF,UART1 Wake-up Flag\nNote: Write 1 to clear this bit" "0: UART1 wake-up source is deasserted,1: UART1 wake-up source is asserted"
newline
bitfld.long 0x00 25. "UART0WF,UART0 Wake-up Flag\nNote: Write 1 to clear this bit" "0: UART0 wake-up source is deasserted,1: UART0 wake-up source is asserted"
bitfld.long 0x00 24. "TMR3WF,Timer3 Wake-up Flag\nNote: Write 1 to clear this bit" "0: Timer3 wake-up source is deasserted,1: Timer3 wake-up source is asserted"
newline
bitfld.long 0x00 23. "TMR2WF,Timer2 Wake-up Flag\nNote: Write 1 to clear this bit" "0: Timer2 wake-up source is deasserted,1: Timer2 wake-up source is asserted"
bitfld.long 0x00 22. "TMR1WF,Timer1 Wake-up Flag\nNote: Write 1 to clear this bit" "0: Timer1 wake-up source is deasserted,1: Timer1 wake-up source is asserted"
newline
bitfld.long 0x00 21. "TMR0WF,Timer0 Wake-up Flag\nNote: Write 1 to clear this bit" "0: Timer0 wake-up source is deasserted,1: Timer0 wake-up source is asserted"
bitfld.long 0x00 20. "WDTWF,WDT Wake-up Flag\nNote: Write 1 to clear this bit" "0: WDT wake-up source is deasserted,1: WDT wake-up source is asserted"
newline
bitfld.long 0x00 19. "RTCWF,RTC Wake-up Flag\nNote: Write 1 to clear this bit" "0: RTC wake-up source is deasserted,1: RTC wake-up source is asserted"
bitfld.long 0x00 18. "GPIOWF,GPIO Wake-up Flag\nNote: Write 1 to clear this bit" "0: GPIO wake-up source is deasserted,1: GPIO wake-up source is asserted"
newline
bitfld.long 0x00 17. "I2C1WF,I2C1 Wake-up Flag\nNote: Write 1 to clear this bit" "0: I2C1 wake-up source is deasserted,1: I2C1 wake-up source is asserted"
bitfld.long 0x00 16. "I2C0WF,I2C0 Wake-up Flag\nNote: Write 1 to clear this bit" "0: I2C0 wake-up source is deasserted,1: I2C0 wake-up source is asserted"
newline
bitfld.long 0x00 13. "USBHWE,USB Host Wake-up Enable Control\n" "0: USB Host wake-up Disabled,1: USB Host wake-up Enabled"
bitfld.long 0x00 12. "USBDWE,USB Device Wake-up Enable Control\n" "0: USB Device wake-up Disabled,1: USB Device wake-up Enabled"
newline
bitfld.long 0x00 11. "UART2WE,UART2 Wake-up Enable Control\n" "0: UART2 wake-up Disabled,1: UART2 wake-up Enabled"
bitfld.long 0x00 10. "UART1WE,UART1 Wake-up Enable Control\n" "0: UART1 wake-up Disabled,1: UART1 wake-up Enabled"
newline
bitfld.long 0x00 9. "UART0WE,UART0 Wake-up Enable Control\n" "0: UART0 wake-up Disabled,1: UART0 wake-up Enabled"
bitfld.long 0x00 8. "TMR3WE,Timer3 Wake-up Enable Control\n" "0: Timer3 wake-up Disabled,1: Timer3 wake-up Enabled"
newline
bitfld.long 0x00 7. "TMR2WE,Timer2 Wake-up Enable Control\n" "0: Timer2 wake-up Disabled,1: Timer2 wake-up Enabled"
bitfld.long 0x00 6. "TMR1WE,Timer1 Wake-up Enable Control\n" "0: Timer1 wake-up Disabled,1: Timer1 wake-up Enabled"
newline
bitfld.long 0x00 5. "TMR0WE,Timer0 Wake-up Enable Control\n" "0: Timer0 wake-up Disabled,1: Timer0 wake-up Enabled"
bitfld.long 0x00 4. "WDTWE,WDT Wake-up Enable Control\n" "0: WDT wake-up Disabled,1: WDT wake-up Enabled"
newline
bitfld.long 0x00 3. "RTCWE,RTC Wake-up Enable Control\n" "0: RTC wake-up Disabled,1: RTC wake-up Enabled"
bitfld.long 0x00 2. "GPIOWE,GPIO Wake-up Enable Control\n" "0: GPIO wake-up Disabled,1: GPIO wake-up Enabled"
newline
bitfld.long 0x00 1. "I2C1WE,I2C1 Wake-up Enable Control\n" "0: I2C1 wake-up Disabled,1: I2C1 wake-up Enabled"
bitfld.long 0x00 0. "I2C0WE,I2C0 Wake-up Enable Control\n" "0: I2C0 wake-up Disabled,1: I2C0 wake-up Enabled"
group.long 0x14++0x03
line.long 0x00 "SYS_IPRST1,Peripheral Reset Control Register 1"
bitfld.long 0x00 31. "SPI1RST,SPI1 Controller Reset\nSet this bit to 1 will generate a reset signal to the USB host controller" "0: SPI1 controller normal operation,1: SPI1 controller reset"
bitfld.long 0x00 30. "SPI0RST,SPI0 Controller Reset\nSet this bit to 1 will generate a reset signal to the USB host controller" "0: SPI0 controller normal operation,1: SPI0 controller reset"
newline
bitfld.long 0x00 28. "ADCRST,ADC Controller Reset\nSet this bit to 1 will generate a reset signal to the USB host controller" "0: ADC controller normal operation,1: ADC controller reset"
bitfld.long 0x00 27. "GPIORST,GPIO Controller Reset\nSet this bit to 1 will generate a reset signal to the USB host controller" "0: GPIO controller normal operation,1: GPIO controller reset"
newline
bitfld.long 0x00 25. "SRAMRST,SRAM Controller Reset\nSet this bit to 1 will generate a reset signal to the USB host controller" "0: SRAM controller normal operation,1: SRAM controller reset"
bitfld.long 0x00 24. "SDHRST,SDH Controller Reset\nSet this bit to 1 will generate a reset signal to the USB host controller" "0: SDH controller normal operation,1: SDH controller reset"
newline
bitfld.long 0x00 18. "USBHRST,USB Host Controller Reset\nSetting this bit to 1 will generate a reset signal to the USB host controller" "0: USB Host controller normal operation,1: USB Host controller reset"
bitfld.long 0x00 17. "I2SRST,I2S Controller Reset\nSetting this bit to 1 will generate a reset signal to the USB host controller" "0: I2S controller normal operation,1: I2S controller reset"
newline
bitfld.long 0x00 13. "WDTPRST,WDT Controller Reset\nSetting this bit to 1 will generate a reset signal to the USB host controller" "0: WDT controller normal operation,1: WDT controller reset"
bitfld.long 0x00 12. "TMR3RST,Timer3 Controller Reset\nSetting this bit to 1 will generate a reset signal to the USB host controller" "0: Timer3 controller normal operation,1: Timer3 controller reset"
newline
bitfld.long 0x00 11. "USBDRST,USB Device Controller Reset\nSetting this bit to 1 will generate a reset signal to the USB host controller" "0: USB Device controller normal operation,1: USB Device controller reset"
bitfld.long 0x00 10. "SPIMRST,SPIM Controller Reset\nSetting this bit to 1 will generate a reset signal to the USB host controller" "0: SPIM controller normal operation,1: SPIM controller reset"
newline
bitfld.long 0x00 9. "I2C1RST,I2C1 Controller Reset\nSetting this bit to 1 will generate a reset signal to the USB host controller" "0: I2C1 controller normal operation,1: I2C1 controller reset"
bitfld.long 0x00 8. "I2C0RST,I2C0 Controller Reset\nSetting this bit to 1 will generate a reset signal to the USB host controller" "0: I2C0 controller normal operation,1: I2C0 controller reset"
newline
bitfld.long 0x00 7. "PWMRST,PWM Controller Reset\nSetting this bit to 1 will generate a reset signal to the USB host controller" "0: PWM controller normal operation,1: PWM controller reset"
bitfld.long 0x00 6. "UART2RST,UART2 Controller Reset\nSetting this bit to 1 will generate a reset signal to the USB host controller" "0: UART2 controller normal operation,1: UART2 controller reset"
newline
bitfld.long 0x00 5. "TMR2RST,Timer2 Controller Reset\nSetting this bit to 1 will generate a reset signal to the USB host controller" "0: Timer2 controller normal operation,1: Timer2 controller reset"
bitfld.long 0x00 4. "WDTFRST,WDT Hardware Controller Reset\nSetting this bit to 1 will generate a reset signal to the USB host controller" "0: WDT controller normal operation,1: WDT controller reset"
newline
bitfld.long 0x00 3. "TMR1RST,Timer1 Controller Reset\nSetting this bit to 1 will generate a reset signal to the USB host controller" "0: Timer1 controller normal operation,1: Timer1 controller reset"
bitfld.long 0x00 2. "TMR0RST,Timer0 Controller Reset\nSetting this bit to 1 will generate a reset signal to the USB host controller" "0: Timer0 controller normal operation,1: Timer0 controller reset"
newline
bitfld.long 0x00 1. "UART1RST,UART1 Controller Reset\nSetting this bit to 1 will generate a reset signal to the USB host controller" "0: UART1 controller normal operation,1: UART1 controller reset"
bitfld.long 0x00 0. "UART0RST,UART0 Controller Reset\nSetting this bit to 1 will generate a reset signal to the USB host controller" "0: UART0 controller normal operation,1: UART0 controller reset"
group.long 0x18++0x03
line.long 0x00 "SYS_NMICTL,Non Maskable Interrupt Control Register"
rbitfld.long 0x00 23. "LVDIF,Low Voltage Detect (LVD) Interrupt Flag (Read Only)\n" "0: LVD interrupt is deasserted,1: LVD interrupt is asserted"
rbitfld.long 0x00 22. "EINT3IF,External GPIO Group 3 Interrupt Flag (Read Only)\n" "0: External GPIO group 3 interrupt is deasserted,1: External GPIO group 3 interrupt is asserted"
newline
rbitfld.long 0x00 21. "EINT2IF,External GPIO Group 2 Interrupt Flag (Read Only)\n" "0: External GPIO group 2 interrupt is deasserted,1: External GPIO group 2 interrupt is asserted"
rbitfld.long 0x00 20. "EINT1IF,External GPIO Group 1 Interrupt Flag (Read Only)\n" "0: External GPIO group 1 interrupt is deasserted,1: External GPIO group 1 interrupt is asserted"
newline
rbitfld.long 0x00 19. "EINT0IF,External GPIO Group 0 Interrupt Flag (Read Only)\n" "0: External GPIO group 0 interrupt is deasserted,1: External GPIO group 0 interrupt is asserted"
rbitfld.long 0x00 18. "PORIF,Power on Reset (POR) Interrupt Flag (Read Only)\n" "0: POR interrupt is deasserted,1: POR interrupt is asserted"
newline
rbitfld.long 0x00 17. "WDTIF,Watch Dog Timer (WDT) Interrupt Flag (Read Only)\n" "0: WDT interrupt is deasserted,1: WDT interrupt is asserted"
rbitfld.long 0x00 16. "RTCIF,RTC Interrupt Flag (Read Only)\n" "0: RTC interrupt is deasserted,1: RTC interrupt is asserted"
newline
bitfld.long 0x00 7. "LVDIEN,Low Voltage Detect NMI Source Enable Control \n" "0: LVD NMI source Disabled,1: LVD NMI source Enabled"
bitfld.long 0x00 6. "EINT3IEN,External GPIO Group 3 NMI Source Enable Control \n" "0: External GPIO group 3 NMI source Disabled,1: External GPIO group 3 NMI source Enabled"
newline
bitfld.long 0x00 5. "EINT2IEN,External GPIO Group 2 NMI Source Enable Control \n" "0: External GPIO group 2 NMI source Disabled,1: External GPIO group 2 NMI source Enabled"
bitfld.long 0x00 4. "EINT1IEN,External GPIO Group 1 NMI Source Enable Control \n" "0: External GPIO group 1 NMI source Disabled,1: External GPIO group 1 NMI source Enabled"
newline
bitfld.long 0x00 3. "EINT0IEN,External GPIO Group 0 NMI Source Enable Control \n" "0: External GPIO group 0 NMI source Disabled,1: External GPIO group 0 NMI source Enabled"
bitfld.long 0x00 2. "PORIEN,Power on Interrupt NMI Source Enable Control\n" "0: POR NMI source Disabled,1: POR NMI source Enabled"
newline
bitfld.long 0x00 1. "WDTIEN,WDT Interrupt NMI Source Enable Control\n" "0: WDT NMI source Disabled,1: WDT NMI source Enabled"
bitfld.long 0x00 0. "RTCIEN,RTC Interrupt NMI Source Enable Control\n" "0: RTC NMI source Disabled,1: RTC NMI source Enabled"
group.long 0x1C++0x03
line.long 0x00 "SYS_RSTSTS,Reset Status Control Register"
bitfld.long 0x00 4. "PORF,Reset Status for POR Reset\nNote: Write 1 to clear this bit to 0" "0: No effect,1: Power-on Reset (POR) had issued the reset.."
bitfld.long 0x00 3. "CPURF,Reset Status for Software Setting\nNote: Write 1 to clear this bit to 0" "0: No effect,1: The CPURST had be triggered to reset the CPU.."
newline
bitfld.long 0x00 2. "WDTRF,Reset Status for Watch Dog Reset\nNote: Write 1 to clear this bit to 0" "0: No effect,1: The watchdog timer or window watchdog timer.."
bitfld.long 0x00 1. "LVRF,Reset Status for Low Voltage Reset\nNote: Write 1 to clear this bit to 0" "0: No effect,1: LVR controller had issued the reset signal to.."
newline
bitfld.long 0x00 0. "PINRF,Reset Status for External NReset Pin\nNote: Write 1 to clear this bit to 0" "0: No effect,1: nRESET pin had issued the reset signal to.."
group.long 0x20++0x03
line.long 0x00 "SYS_AHBCTL,AHB Bus Control Register"
bitfld.long 0x00 5. "PRISTS,Interrupt Active Status in CPUHPRI Enabled Mode\nIf it is high the CPU has the highest AHB bus priority" "0: No effect,1: The highest AHB bus priority for CPU is active"
bitfld.long 0x00 4. "CPUHPRI,Enable Raising the Priority of CPU in IRQ Period\nIt can be used to reduce the interrupt latency in a real-time system" "0: No effect,1: The function that CPU has the highest AHB bus.."
newline
bitfld.long 0x00 0. "PRISEL,AHB Bus Arbitration Mode Control\nThe priority mode for fixed priority mode is I2S SDH USBH USBD SPIM M4(S) M4(D) M4(I)" "0: Fixed priority mode,1: Round-robin priority mode (rotate)"
group.long 0x30++0x03
line.long 0x00 "SYS_GPA_MFPL,GPIOA Low Byte Multi-function Control Register"
bitfld.long 0x00 28.--30. "PA7MFP,PA.7 Multi-function Pin Selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--26. "PA6MFP,PA.6 Multi-function Pin Selection" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 20.--22. "PA5MFP,PA.5 Multi-function Pin Selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "PA4MFP,PA.4 Multi-function Pin Selection" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 12.--14. "PA3MFP,PA.3 Multi-function Pin Selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--10. "PA2MFP,PA.2 Multi-function Pin Selection" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4.--6. "PA1MFP,PA.1 Multi-function Pin Selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "PA0MFP,PA.0 Multi-function Pin Selection" "0,1,2,3,4,5,6,7"
group.long 0x34++0x03
line.long 0x00 "SYS_GPA_MFPH,GPIOA High Byte Multi-function Control Register"
bitfld.long 0x00 28.--30. "PA15MFP,PA.15 Multi-function Pin Selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--26. "PA14MFP,PA.14 Multi-function Pin Selection" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 20.--22. "PA13MFP,PA.13 Multi-function Pin Selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "PA12MFP,PA.12 Multi-function Pin Selection" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 12.--14. "PA11MFP,PA.11 Multi-function Pin Selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--10. "PA10MFP,PA.10 Multi-function Pin Selection" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4.--6. "PA9MFP,PA.9 Multi-function Pin Selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "PA8MFP,PA.8 Multi-function Pin Selection" "0,1,2,3,4,5,6,7"
group.long 0x38++0x03
line.long 0x00 "SYS_GPB_MFPL,GPIOB Low Byte Multi-function Control Register"
bitfld.long 0x00 28.--30. "PB7MFP,PB.7 Multi-function Pin Selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--26. "PB6MFP,PB.6 Multi-function Pin Selection" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 20.--22. "PB5MFP,PB.5 Multi-function Pin Selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "PB4MFP,PB.4 Multi-function Pin Selection" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 12.--14. "PB3MFP,PB.3 Multi-function Pin Selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--10. "PB2MFP,PB.2 Multi-function Pin Selection" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4.--6. "PB1MFP,PB.1 Multi-function Pin Selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "PB0MFP,PB.0 Multi-function Pin Selection" "0,1,2,3,4,5,6,7"
group.long 0x3C++0x03
line.long 0x00 "SYS_GPB_MFPH,GPIOB High Byte Multi-function Control Register"
bitfld.long 0x00 28.--30. "PB15MFP,PB.15 Multi-function Pin Selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--26. "PB14MFP,PB.14 Multi-function Pin Selection" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 20.--22. "PB13MFP,PB.13 Multi-function Pin Selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "PB12MFP,PB.12 Multi-function Pin Selection" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 12.--14. "PB11MFP,PB.11 Multi-function Pin Selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--10. "PB10MFP,PB.10 Multi-function Pin Selection" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4.--6. "PB9MFP,PB.9 Multi-function Pin Selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "PB8MFP,PB.8 Multi-function Pin Selection" "0,1,2,3,4,5,6,7"
group.long 0x40++0x03
line.long 0x00 "SYS_GPC_MFPL,GPIOC Low Byte Multi-function Control Register"
bitfld.long 0x00 28.--30. "PC7MFP,PC.7 Multi-function Pin Selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--26. "PC6MFP,PC.6 Multi-function Pin Selection" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 20.--22. "PC5MFP,PC.5 Multi-function Pin Selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--18. "PC4MFP,PC.4 Multi-function Pin Selection" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 12.--14. "PC3MFP,PC.3 Multi-function Pin Selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--10. "PC2MFP,PC.2 Multi-function Pin Selection" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4.--6. "PC1MFP,PC.1 Multi-function Pin Selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "PC0MFP,PC.0 Multi-function Pin Selection" "0,1,2,3,4,5,6,7"
group.long 0x44++0x03
line.long 0x00 "SYS_GPC_MFPH,GPIOC High Byte Multi-function Control Register"
bitfld.long 0x00 24.--26. "PC14MFP,PC.14 Multi-function Pin Selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--22. "PC13MFP,PC.13 Multi-function Pin Selection" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PC12MFP,PC.12 Multi-function Pin Selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "PC11MFP,PC.11 Multi-function Pin Selection" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 8.--10. "PC10MFP,PC.10 Multi-function Pin Selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PC9MFP,PC.9 Multi-function Pin Selection" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--2. "PC8MFP,PC.8 Multi-function Pin Selection" "0,1,2,3,4,5,6,7"
group.long 0x48++0x03
line.long 0x00 "SYS_GPD_MFPL,GPIOD Low Byte Multi-function Control Register"
bitfld.long 0x00 16.--18. "PD4MFP,PD.4 Multi-function Pin Selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "PD3MFP,PD.3 Multi-function Pin Selection" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 8.--10. "PD2MFP,PD.2 Multi-function Pin Selection" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PD1MFP,PD.1 Multi-function Pin Selection" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--2. "PD0MFP,PD.0 Multi-function Pin Selection" "0,1,2,3,4,5,6,7"
group.long 0x50++0x03
line.long 0x00 "SYS_LVMPADDR,Load VECMAP Address Parameter Control Register"
hexmask.long 0x00 0.--31. 1. "ADDR,Load VECMAP Address Register\nThis is the start address for mapping to the address 0x0000_0000 in VECMAP function"
group.long 0x54++0x03
line.long 0x00 "SYS_LVMPLEN,Load VECMAP Length Parameter Control Register"
hexmask.long.byte 0x00 0.--7. 1. "LEN,LD_VECMAP Length\nThis is the memory length loading signal for mapping to the address 0x0000_0000 in VECMAP function"
rgroup.long 0x58++0x03
line.long 0x00 "SYS_RVMPADDR,Real VECMAP Address Parameter Register"
hexmask.long 0x00 0.--31. 1. "ADDR,Real VECMAP Address Register Parameter\nThis is the real start address parameter for mapping to the address 0x0000_0000 in VECMAP function"
group.long 0x5C++0x03
line.long 0x00 "SYS_RVMPLEN,Real VECMAP Length Parameter Control Register"
hexmask.long.byte 0x00 24.--31. 1. "LEN,Real VECMAP Length\nThis is the real memory length for mapping to the address 0x0000_0000 in VECMAP function"
bitfld.long 0x00 0. "RLDVMP,Load VECMAP Parameter Signal\nNote: This bit is auto cleared to 0" "0: No effect,1: Load VECMAP Address and Length"
group.long 0x6C++0x03
line.long 0x00 "SYS_EPADPUEN,Embedded SPI Flash Pad Pull-up Enable Control Register"
bitfld.long 0x00 0.--4. "EPADPUEN,Embedded SPI Flash Pad Pull-up Enable Control\nNote: In Power-down mode user should set EPADPUEN[4:0] to 0x12" "0: All embedded pads are pull-up Disabled,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,18: Only SPI Flash MISO pads are pull-up Enabled,?,?,?,?,?,?,?,?,?,?,?,?,31: All embedded pads are pull-up Enabled"
group.long 0x70++0x03
line.long 0x00 "SYS_GPADS,GPIOA Driving Strength Control Register"
bitfld.long 0x00 28.--30. "PA7DS,PA.7 Driving Strength Control\nSetting driving strength for PA.7 analog / digital combo pin.\n" "0: 2.0 mA (Default),1: 6.5 mA,2: 8.7 mA,3: 13.0 mA,4: 15.2 mA,5: 19.5 mA,6: 21.7 mA,7: 26.1 mA"
bitfld.long 0x00 24.--26. "PA6DS,PA.6 Driving Strength Control\nSetting driving strength for PA.6 analog / digital combo pin.\n" "0: 2.0 mA (Default),1: 6.5 mA,2: 8.7 mA,3: 13.0 mA,4: 15.2 mA,5: 19.5 mA,6: 21.7 mA,7: 26.1 mA"
newline
bitfld.long 0x00 20.--22. "PA5DS,PA.5 Driving Strength Control\nSetting driving strength for PA.5 analog / digital combo pin.\n" "0: 2.0 mA (Default),1: 6.5 mA,2: 8.7 mA,3: 13.0 mA,4: 15.2 mA,5: 19.5 mA,6: 21.7 mA,7: 26.1 mA"
bitfld.long 0x00 16.--18. "PA4DS,PA.4 Driving Strength Control\nSetting driving strength for PA.4 analog / digital combo pin.\n" "0: 2.0 mA (Default),1: 6.5 mA,2: 8.7 mA,3: 13.0 mA,4: 15.2 mA,5: 19.5 mA,6: 21.7 mA,7: 26.1 mA"
newline
bitfld.long 0x00 12.--14. "PA3DS,PA.3 Driving Strength Control\nSetting driving strength for PA.3 analog / digital combo pin.\n" "0: 2.0 mA (Default),1: 6.5 mA,2: 8.7 mA,3: 13.0 mA,4: 15.2 mA,5: 19.5 mA,6: 21.7 mA,7: 26.1 mA"
bitfld.long 0x00 8.--10. "PA2DS,PA.2 Driving Strength Control\nSetting driving strength for PA.2 analog / digital combo pin.\n" "0: 2.0 mA (Default),1: 6.5 mA,2: 8.7 mA,3: 13.0 mA,4: 15.2 mA,5: 19.5 mA,6: 21.7 mA,7: 26.1 mA"
newline
bitfld.long 0x00 4.--6. "PA1DS,PA.1 Driving Strength Control\nSetting driving strength for PA.1 analog / digital combo pin.\n" "0: 2.0 mA (Default),1: 6.5 mA,2: 8.7 mA,3: 13.0 mA,4: 15.2 mA,5: 19.5 mA,6: 21.7 mA,7: 26.1 mA"
bitfld.long 0x00 0.--2. "PA0DS,PA.0 Driving Strength Control\nSetting driving strength for PA.0 analog / digital combo pin.\n" "0: 2.0 mA (Default),1: 6.5 mA,2: 8.7 mA,3: 13.0 mA,4: 15.2 mA,5: 19.5 mA,6: 21.7 mA,7: 26.1 mA"
group.long 0x74++0x03
line.long 0x00 "SYS_GPAIBE,GPIOA Input Buffer Enable Control Register"
hexmask.long.byte 0x00 24.--30. 1. "SMTENx,Note: If both Schmitt Trigger and CMOS input buffer are set to 0 the input signal from PAD will always be zero"
hexmask.long.byte 0x00 16.--23. 1. "DINONx,Note1: If setting to 0 the input signal from PAD will always be zero.\nNote2: If using PA.0~PA.7 as analog pads remember to disable input buffer"
newline
hexmask.long.byte 0x00 8.--15. 1. "CMOSENx,Note: If both Schmitt Trigger and CMOS input buffer are set to 0 the input signal from PAD will always be zero"
hexmask.long.byte 0x00 0.--7. 1. "IBSELx,"
group.long 0x78++0x03
line.long 0x00 "SYS_GPBIBE,GPIOB Input Buffer Enable Control Register"
hexmask.long.word 0x00 16.--30. 1. "SMTENx,Note: If both Schmitt Trigger and CMOS input buffer are set to 0 the input signal from PAD will always be zero"
hexmask.long.word 0x00 0.--15. 1. "CMOSENx,Note: If both Schmitt Trigger and CMOS input buffer are set to 0 the input signal from PAD will always be zero"
group.long 0x7C++0x03
line.long 0x00 "SYS_GPCIBE,GPIOC Input Buffer Enable Control Register"
hexmask.long.word 0x00 16.--30. 1. "SMTENx,Note: If both Schmitt Trigger and CMOS input buffer are set to 0 the input signal from PAD will always be zero"
hexmask.long.word 0x00 0.--14. 1. "CMOSENx,Note: If both Schmitt Trigger and CMOS input buffer are set to 0 the input signal from PAD will always be zero"
group.long 0x80++0x03
line.long 0x00 "SYS_GPDIBE,GPIOD Input Buffer Enable Control Register"
bitfld.long 0x00 18.--20. "DINONx,Note1: If setting to 0 the input signal from PAD will always be zero.\nNote2: If using PD.2 PD.3 and PD.4 as analog pads user must disable PD.2 PD.3 and PD.4 input buffer" "0: PD.x Input Buffer Disabled,1: PD.x Input Buffer Enabled (Default),?..."
bitfld.long 0x00 16.--17. "SMTENx,Note: If both Schmitt Trigger and CMOS input buffer are set to 0 the input signal from PAD will always be zero" "0: PD.x Schmitt Trigger Input Buffer Disabled,1: PD.x Schmitt Trigger Input Buffer Enabled..,?..."
newline
bitfld.long 0x00 2.--4. "IBSELx," "0: PD.x CMOS Input Buffer (Default),1: PD.x Schmitt Trigger Input Buffer,?..."
bitfld.long 0x00 0.--1. "CMOSENx,Note: If both Schmitt Trigger and CMOS input buffer are set to 0 the input signal from PAD will always be zero" "0: PD.x CMOS Input Buffer Disabled (Default),1: PD.x CMOS Input Buffer Enabled,?..."
group.long 0x84++0x03
line.long 0x00 "SYS_GPDDS,GPIOD Driving Strength Control Register"
bitfld.long 0x00 8.--10. "PD4DS,PD.4 Driving Strength Control\nSetting driving strength for PD.4 analog / digital combo pin.\n" "0: 2.0 mA (Default),1: 6.5 mA,2: 8.7 mA,3: 13.0 mA,4: 15.2 mA,5: 19.5 mA,6: 21.7 mA,7: 26.1 mA"
bitfld.long 0x00 4.--6. "PD3DS,PD.3 Driving Strength Control\nSetting driving strength for PD.3 analog / digital combo pin.\n" "0: 2.0 mA (Default),1: 6.5 mA,2: 8.7 mA,3: 13.0 mA,4: 15.2 mA,5: 19.5 mA,6: 21.7 mA,7: 26.1 mA"
newline
bitfld.long 0x00 0.--2. "PD2DS,PD.2 Driving Strength Control\nSetting driving strength for PD.2 analog / digital combo pin.\n" "0: 2.0 mA (Default),1: 6.5 mA,2: 8.7 mA,3: 13.0 mA,4: 15.2 mA,5: 19.5 mA,6: 21.7 mA,7: 26.1 mA"
group.long 0x100++0x03
line.long 0x00 "SYS_RSTDBCNT,External NRESET Pin De-bounce Counter Control Register"
hexmask.long.word 0x00 0.--15. 1. "RSTDBCNT,External NRESET De-bounce Counter \n"
group.long 0x104++0x03
line.long 0x00 "SYS_RSTDBEN,External NRESET Pin De-bounce Control Register"
bitfld.long 0x00 0. "RSTDBEN,External NRESET De-bounce Control\nThis bit is to enable or disable the external nRESET pin de-bounce process" "0: De-bounce function Disabled,1: De-bounce function Enabled"
tree.end
tree "GPIO"
base ad:0x400E3000
group.long 0x00++0x03
line.long 0x00 "PA_MODE,PA I/O Mode Control"
bitfld.long 0x00 15. "MODE15,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
bitfld.long 0x00 14. "MODE14,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
newline
bitfld.long 0x00 13. "MODE13,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
bitfld.long 0x00 12. "MODE12,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
newline
bitfld.long 0x00 11. "MODE11,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
bitfld.long 0x00 10. "MODE10,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
newline
bitfld.long 0x00 9. "MODE9,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
bitfld.long 0x00 8. "MODE8,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
newline
bitfld.long 0x00 7. "MODE7,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
bitfld.long 0x00 6. "MODE6,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
newline
bitfld.long 0x00 5. "MODE5,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
bitfld.long 0x00 4. "MODE4,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
newline
bitfld.long 0x00 3. "MODE3,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
bitfld.long 0x00 2. "MODE2,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
newline
bitfld.long 0x00 1. "MODE1,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
bitfld.long 0x00 0. "MODE0,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
group.long 0x04++0x03
line.long 0x00 "PA_PUEN,PA I/O Pull-up/Down Resistor Control"
bitfld.long 0x00 30.--31. "PULLSEL15,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
bitfld.long 0x00 28.--29. "PULLSEL14,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
newline
bitfld.long 0x00 26.--27. "PULLSEL13,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
bitfld.long 0x00 24.--25. "PULLSEL12,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
newline
bitfld.long 0x00 22.--23. "PULLSEL11,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
bitfld.long 0x00 20.--21. "PULLSEL10,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
newline
bitfld.long 0x00 18.--19. "PULLSEL9,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
bitfld.long 0x00 16.--17. "PULLSEL8,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
newline
bitfld.long 0x00 14.--15. "PULLSEL7,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
bitfld.long 0x00 12.--13. "PULLSEL6,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
newline
bitfld.long 0x00 10.--11. "PULLSEL5,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
bitfld.long 0x00 8.--9. "PULLSEL4,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
newline
bitfld.long 0x00 6.--7. "PULLSEL3,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
bitfld.long 0x00 4.--5. "PULLSEL2,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
newline
bitfld.long 0x00 2.--3. "PULLSEL1,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
bitfld.long 0x00 0.--1. "PULLSEL0,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
group.long 0x08++0x03
line.long 0x00 "PA_DOUT,PA Data Output Value"
bitfld.long 0x00 15. "DOUT15,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 14. "DOUT14,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
newline
bitfld.long 0x00 13. "DOUT13,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 12. "DOUT12,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
newline
bitfld.long 0x00 11. "DOUT11,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 10. "DOUT10,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
newline
bitfld.long 0x00 9. "DOUT9,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 8. "DOUT8,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
newline
bitfld.long 0x00 7. "DOUT7,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 6. "DOUT6,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
newline
bitfld.long 0x00 5. "DOUT5,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 4. "DOUT4,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
newline
bitfld.long 0x00 3. "DOUT3,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 2. "DOUT2,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
newline
bitfld.long 0x00 1. "DOUT1,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 0. "DOUT0,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
rgroup.long 0x0C++0x03
line.long 0x00 "PA_PIN,PA Pin Value"
bitfld.long 0x00 15. "PIN15,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
bitfld.long 0x00 14. "PIN14,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
newline
bitfld.long 0x00 13. "PIN13,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
bitfld.long 0x00 12. "PIN12,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
newline
bitfld.long 0x00 11. "PIN11,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
bitfld.long 0x00 10. "PIN10,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
newline
bitfld.long 0x00 9. "PIN9,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
bitfld.long 0x00 8. "PIN8,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
newline
bitfld.long 0x00 7. "PIN7,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
bitfld.long 0x00 6. "PIN6,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
newline
bitfld.long 0x00 5. "PIN5,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
bitfld.long 0x00 4. "PIN4,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
newline
bitfld.long 0x00 3. "PIN3,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
bitfld.long 0x00 2. "PIN2,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
newline
bitfld.long 0x00 1. "PIN1,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
bitfld.long 0x00 0. "PIN0,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
group.long 0x10++0x03
line.long 0x00 "PB_MODE,PB I/O Mode Control"
bitfld.long 0x00 15. "MODE15,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
bitfld.long 0x00 14. "MODE14,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
newline
bitfld.long 0x00 13. "MODE13,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
bitfld.long 0x00 12. "MODE12,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
newline
bitfld.long 0x00 11. "MODE11,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
bitfld.long 0x00 10. "MODE10,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
newline
bitfld.long 0x00 9. "MODE9,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
bitfld.long 0x00 8. "MODE8,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
newline
bitfld.long 0x00 7. "MODE7,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
bitfld.long 0x00 6. "MODE6,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
newline
bitfld.long 0x00 5. "MODE5,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
bitfld.long 0x00 4. "MODE4,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
newline
bitfld.long 0x00 3. "MODE3,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
bitfld.long 0x00 2. "MODE2,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
newline
bitfld.long 0x00 1. "MODE1,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
bitfld.long 0x00 0. "MODE0,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
group.long 0x14++0x03
line.long 0x00 "PB_PUEN,PB I/O Pull-up/Down Resistor Control"
bitfld.long 0x00 30.--31. "PULLSEL15,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
bitfld.long 0x00 28.--29. "PULLSEL14,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
newline
bitfld.long 0x00 26.--27. "PULLSEL13,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
bitfld.long 0x00 24.--25. "PULLSEL12,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
newline
bitfld.long 0x00 22.--23. "PULLSEL11,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
bitfld.long 0x00 20.--21. "PULLSEL10,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
newline
bitfld.long 0x00 18.--19. "PULLSEL9,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
bitfld.long 0x00 16.--17. "PULLSEL8,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
newline
bitfld.long 0x00 14.--15. "PULLSEL7,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
bitfld.long 0x00 12.--13. "PULLSEL6,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
newline
bitfld.long 0x00 10.--11. "PULLSEL5,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
bitfld.long 0x00 8.--9. "PULLSEL4,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
newline
bitfld.long 0x00 6.--7. "PULLSEL3,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
bitfld.long 0x00 4.--5. "PULLSEL2,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
newline
bitfld.long 0x00 2.--3. "PULLSEL1,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
bitfld.long 0x00 0.--1. "PULLSEL0,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
group.long 0x18++0x03
line.long 0x00 "PB_DOUT,PB Data Output Value"
bitfld.long 0x00 15. "DOUT15,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 14. "DOUT14,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
newline
bitfld.long 0x00 13. "DOUT13,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 12. "DOUT12,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
newline
bitfld.long 0x00 11. "DOUT11,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 10. "DOUT10,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
newline
bitfld.long 0x00 9. "DOUT9,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 8. "DOUT8,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
newline
bitfld.long 0x00 7. "DOUT7,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 6. "DOUT6,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
newline
bitfld.long 0x00 5. "DOUT5,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 4. "DOUT4,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
newline
bitfld.long 0x00 3. "DOUT3,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 2. "DOUT2,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
newline
bitfld.long 0x00 1. "DOUT1,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 0. "DOUT0,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
group.long 0x1C++0x03
line.long 0x00 "PB_PIN,PB Pin Value"
rbitfld.long 0x00 15. "PIN15,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 14. "PIN14,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
newline
rbitfld.long 0x00 13. "PIN13,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 12. "PIN12,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
newline
rbitfld.long 0x00 11. "PIN11,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 10. "PIN10,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
newline
rbitfld.long 0x00 9. "PIN9,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 8. "PIN8,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
newline
rbitfld.long 0x00 7. "PIN7,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 6. "PIN6,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
newline
rbitfld.long 0x00 5. "PIN5,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 4. "PIN4,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
newline
rbitfld.long 0x00 3. "PIN3,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 2. "PIN2,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
newline
rbitfld.long 0x00 1. "PIN1,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 0. "PIN0,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
group.long 0x20++0x03
line.long 0x00 "PC_MODE,PC I/O Mode Control"
bitfld.long 0x00 15. "MODE15,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
bitfld.long 0x00 14. "MODE14,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
newline
bitfld.long 0x00 13. "MODE13,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
bitfld.long 0x00 12. "MODE12,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
newline
bitfld.long 0x00 11. "MODE11,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
bitfld.long 0x00 10. "MODE10,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
newline
bitfld.long 0x00 9. "MODE9,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
bitfld.long 0x00 8. "MODE8,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
newline
bitfld.long 0x00 7. "MODE7,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
bitfld.long 0x00 6. "MODE6,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
newline
bitfld.long 0x00 5. "MODE5,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
bitfld.long 0x00 4. "MODE4,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
newline
bitfld.long 0x00 3. "MODE3,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
bitfld.long 0x00 2. "MODE2,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
newline
bitfld.long 0x00 1. "MODE1,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
bitfld.long 0x00 0. "MODE0,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
group.long 0x24++0x03
line.long 0x00 "PC_PUEN,PC I/O Pull-up/Down Resistor Control"
bitfld.long 0x00 30.--31. "PULLSEL15,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
bitfld.long 0x00 28.--29. "PULLSEL14,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
newline
bitfld.long 0x00 26.--27. "PULLSEL13,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
bitfld.long 0x00 24.--25. "PULLSEL12,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
newline
bitfld.long 0x00 22.--23. "PULLSEL11,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
bitfld.long 0x00 20.--21. "PULLSEL10,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
newline
bitfld.long 0x00 18.--19. "PULLSEL9,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
bitfld.long 0x00 16.--17. "PULLSEL8,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
newline
bitfld.long 0x00 14.--15. "PULLSEL7,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
bitfld.long 0x00 12.--13. "PULLSEL6,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
newline
bitfld.long 0x00 10.--11. "PULLSEL5,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
bitfld.long 0x00 8.--9. "PULLSEL4,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
newline
bitfld.long 0x00 6.--7. "PULLSEL3,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
bitfld.long 0x00 4.--5. "PULLSEL2,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
newline
bitfld.long 0x00 2.--3. "PULLSEL1,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
bitfld.long 0x00 0.--1. "PULLSEL0,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
group.long 0x28++0x03
line.long 0x00 "PC_DOUT,PC Data Output Value"
bitfld.long 0x00 15. "DOUT15,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 14. "DOUT14,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
newline
bitfld.long 0x00 13. "DOUT13,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 12. "DOUT12,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
newline
bitfld.long 0x00 11. "DOUT11,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 10. "DOUT10,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
newline
bitfld.long 0x00 9. "DOUT9,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 8. "DOUT8,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
newline
bitfld.long 0x00 7. "DOUT7,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 6. "DOUT6,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
newline
bitfld.long 0x00 5. "DOUT5,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 4. "DOUT4,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
newline
bitfld.long 0x00 3. "DOUT3,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 2. "DOUT2,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
newline
bitfld.long 0x00 1. "DOUT1,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 0. "DOUT0,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
group.long 0x2C++0x03
line.long 0x00 "PC_PIN,PC Pin Value"
rbitfld.long 0x00 15. "PIN15,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 14. "PIN14,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
newline
rbitfld.long 0x00 13. "PIN13,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 12. "PIN12,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
newline
rbitfld.long 0x00 11. "PIN11,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 10. "PIN10,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
newline
rbitfld.long 0x00 9. "PIN9,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 8. "PIN8,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
newline
rbitfld.long 0x00 7. "PIN7,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 6. "PIN6,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
newline
rbitfld.long 0x00 5. "PIN5,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 4. "PIN4,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
newline
rbitfld.long 0x00 3. "PIN3,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 2. "PIN2,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
newline
rbitfld.long 0x00 1. "PIN1,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 0. "PIN0,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
group.long 0x30++0x03
line.long 0x00 "PD_MODE,PD I/O Mode Control"
bitfld.long 0x00 15. "MODE15,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
bitfld.long 0x00 14. "MODE14,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
newline
bitfld.long 0x00 13. "MODE13,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
bitfld.long 0x00 12. "MODE12,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
newline
bitfld.long 0x00 11. "MODE11,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
bitfld.long 0x00 10. "MODE10,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
newline
bitfld.long 0x00 9. "MODE9,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
bitfld.long 0x00 8. "MODE8,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
newline
bitfld.long 0x00 7. "MODE7,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
bitfld.long 0x00 6. "MODE6,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
newline
bitfld.long 0x00 5. "MODE5,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
bitfld.long 0x00 4. "MODE4,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
newline
bitfld.long 0x00 3. "MODE3,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
bitfld.long 0x00 2. "MODE2,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
newline
bitfld.long 0x00 1. "MODE1,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
bitfld.long 0x00 0. "MODE0,Port A-d I/O Pin[N] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode"
group.long 0x34++0x03
line.long 0x00 "PD_PUEN,PD I/O Pull-up/Down Resistor Control"
bitfld.long 0x00 30.--31. "PULLSEL15,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
bitfld.long 0x00 28.--29. "PULLSEL14,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
newline
bitfld.long 0x00 26.--27. "PULLSEL13,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
bitfld.long 0x00 24.--25. "PULLSEL12,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
newline
bitfld.long 0x00 22.--23. "PULLSEL11,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
bitfld.long 0x00 20.--21. "PULLSEL10,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
newline
bitfld.long 0x00 18.--19. "PULLSEL9,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
bitfld.long 0x00 16.--17. "PULLSEL8,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
newline
bitfld.long 0x00 14.--15. "PULLSEL7,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
bitfld.long 0x00 12.--13. "PULLSEL6,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
newline
bitfld.long 0x00 10.--11. "PULLSEL5,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
bitfld.long 0x00 8.--9. "PULLSEL4,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
newline
bitfld.long 0x00 6.--7. "PULLSEL3,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
bitfld.long 0x00 4.--5. "PULLSEL2,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
newline
bitfld.long 0x00 2.--3. "PULLSEL1,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
bitfld.long 0x00 0.--1. "PULLSEL0,Port A-d Pin Pull-up Resistor or Pull-down Resistor Enable Control\nNote2: Refer to Figure 6.41" "0: Px.n pull-up or pull-down resistors are all..,1: Px.n pull-up resistor Enabled,2: Px.n pull-down resistor Enabled,3: Reserved"
group.long 0x38++0x03
line.long 0x00 "PD_DOUT,PD Data Output Value"
bitfld.long 0x00 15. "DOUT15,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 14. "DOUT14,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
newline
bitfld.long 0x00 13. "DOUT13,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 12. "DOUT12,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
newline
bitfld.long 0x00 11. "DOUT11,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 10. "DOUT10,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
newline
bitfld.long 0x00 9. "DOUT9,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 8. "DOUT8,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
newline
bitfld.long 0x00 7. "DOUT7,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 6. "DOUT6,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
newline
bitfld.long 0x00 5. "DOUT5,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 4. "DOUT4,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
newline
bitfld.long 0x00 3. "DOUT3,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 2. "DOUT2,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
newline
bitfld.long 0x00 1. "DOUT1,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
bitfld.long 0x00 0. "DOUT0,Port A-d Pin[N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
group.long 0x3C++0x03
line.long 0x00 "PD_PIN,PD Pin Value"
rbitfld.long 0x00 15. "PIN15,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 14. "PIN14,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
newline
rbitfld.long 0x00 13. "PIN13,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 12. "PIN12,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
newline
rbitfld.long 0x00 11. "PIN11,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 10. "PIN10,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
newline
rbitfld.long 0x00 9. "PIN9,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 8. "PIN8,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
newline
rbitfld.long 0x00 7. "PIN7,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 6. "PIN6,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
newline
rbitfld.long 0x00 5. "PIN5,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 4. "PIN4,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
newline
rbitfld.long 0x00 3. "PIN3,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 2. "PIN2,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
newline
rbitfld.long 0x00 1. "PIN1,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
rbitfld.long 0x00 0. "PIN0,Port A-d Pin[N] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin" "0,1"
group.long 0x70++0x03
line.long 0x00 "GPIO_DBCTL,Interrupt Event (EINT) De-bounce Control"
bitfld.long 0x00 4.--7. "DBCLKSEL,De-bounce Sampling Cycle Selection\n" "0: Sample interrupt input once per 1 APB clocks,1: Sample interrupt input once per 2 APB clocks,2: Sample interrupt input once per 4 APB clocks,3: Sample interrupt input once per 8 APB clocks,4: Sample interrupt input once per 16 APB clocks,5: Sample interrupt input once per 32 APB clocks,6: Sample interrupt input once per 64 APB clocks,7: Sample interrupt input once per 128 APB clocks,8: Sample interrupt input once per 256 APB clocks,9: Sample interrupt input once per 512 APB clocks,10: Sample interrupt input once per 1024 APB..,11: Sample interrupt input once per 2048 APB..,12: Sample interrupt input once per 4096 APB..,13: Sample interrupt input once per 8192 APB..,14: Sample interrupt input once per 16384 APB..,15: Sample interrupt input once per 32768 APB.."
bitfld.long 0x00 3. "DBEN3,EINT (EINT0~EINT3) De-bounce Enable Control\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding EINT" "0: EINTn de-bounce function Disabled,1: EINTn de-bounce function Enabled"
newline
bitfld.long 0x00 2. "DBEN2,EINT (EINT0~EINT3) De-bounce Enable Control\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding EINT" "0: EINTn de-bounce function Disabled,1: EINTn de-bounce function Enabled"
bitfld.long 0x00 1. "DBEN1,EINT (EINT0~EINT3) De-bounce Enable Control\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding EINT" "0: EINTn de-bounce function Disabled,1: EINTn de-bounce function Enabled"
newline
bitfld.long 0x00 0. "DBEN0,EINT (EINT0~EINT3) De-bounce Enable Control\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding EINT" "0: EINTn de-bounce function Disabled,1: EINTn de-bounce function Enabled"
group.long 0x80++0x03
line.long 0x00 "PA_INTSRCGP,PA Interrupt Event (EINT) Source Grouping"
bitfld.long 0x00 30.--31. "INTSEL15,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
bitfld.long 0x00 28.--29. "INTSEL14,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
newline
bitfld.long 0x00 26.--27. "INTSEL13,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
bitfld.long 0x00 24.--25. "INTSEL12,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
newline
bitfld.long 0x00 22.--23. "INTSEL11,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
bitfld.long 0x00 20.--21. "INTSEL10,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
newline
bitfld.long 0x00 18.--19. "INTSEL9,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
bitfld.long 0x00 16.--17. "INTSEL8,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
newline
bitfld.long 0x00 14.--15. "INTSEL7,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
bitfld.long 0x00 12.--13. "INTSEL6,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
newline
bitfld.long 0x00 10.--11. "INTSEL5,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
bitfld.long 0x00 8.--9. "INTSEL4,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
newline
bitfld.long 0x00 6.--7. "INTSEL3,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
bitfld.long 0x00 4.--5. "INTSEL2,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
newline
bitfld.long 0x00 2.--3. "INTSEL1,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
bitfld.long 0x00 0.--1. "INTSEL0,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
group.long 0x84++0x03
line.long 0x00 "PB_INTSRCGP,PB Interrupt Event (EINT) Source Grouping"
bitfld.long 0x00 30.--31. "INTSEL15,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
bitfld.long 0x00 28.--29. "INTSEL14,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
newline
bitfld.long 0x00 26.--27. "INTSEL13,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
bitfld.long 0x00 24.--25. "INTSEL12,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
newline
bitfld.long 0x00 22.--23. "INTSEL11,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
bitfld.long 0x00 20.--21. "INTSEL10,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
newline
bitfld.long 0x00 18.--19. "INTSEL9,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
bitfld.long 0x00 16.--17. "INTSEL8,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
newline
bitfld.long 0x00 14.--15. "INTSEL7,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
bitfld.long 0x00 12.--13. "INTSEL6,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
newline
bitfld.long 0x00 10.--11. "INTSEL5,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
bitfld.long 0x00 8.--9. "INTSEL4,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
newline
bitfld.long 0x00 6.--7. "INTSEL3,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
bitfld.long 0x00 4.--5. "INTSEL2,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
newline
bitfld.long 0x00 2.--3. "INTSEL1,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
bitfld.long 0x00 0.--1. "INTSEL0,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
group.long 0x88++0x03
line.long 0x00 "PC_INTSRCGP,PC Interrupt Event (EINT) Source Grouping"
bitfld.long 0x00 30.--31. "INTSEL15,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
bitfld.long 0x00 28.--29. "INTSEL14,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
newline
bitfld.long 0x00 26.--27. "INTSEL13,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
bitfld.long 0x00 24.--25. "INTSEL12,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
newline
bitfld.long 0x00 22.--23. "INTSEL11,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
bitfld.long 0x00 20.--21. "INTSEL10,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
newline
bitfld.long 0x00 18.--19. "INTSEL9,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
bitfld.long 0x00 16.--17. "INTSEL8,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
newline
bitfld.long 0x00 14.--15. "INTSEL7,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
bitfld.long 0x00 12.--13. "INTSEL6,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
newline
bitfld.long 0x00 10.--11. "INTSEL5,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
bitfld.long 0x00 8.--9. "INTSEL4,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
newline
bitfld.long 0x00 6.--7. "INTSEL3,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
bitfld.long 0x00 4.--5. "INTSEL2,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
newline
bitfld.long 0x00 2.--3. "INTSEL1,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
bitfld.long 0x00 0.--1. "INTSEL0,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
group.long 0x8C++0x03
line.long 0x00 "PD_INTSRCGP,PD Interrupt Event (EINT) Source Grouping"
bitfld.long 0x00 30.--31. "INTSEL15,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
bitfld.long 0x00 28.--29. "INTSEL14,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
newline
bitfld.long 0x00 26.--27. "INTSEL13,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
bitfld.long 0x00 24.--25. "INTSEL12,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
newline
bitfld.long 0x00 22.--23. "INTSEL11,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
bitfld.long 0x00 20.--21. "INTSEL10,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
newline
bitfld.long 0x00 18.--19. "INTSEL9,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
bitfld.long 0x00 16.--17. "INTSEL8,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
newline
bitfld.long 0x00 14.--15. "INTSEL7,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
bitfld.long 0x00 12.--13. "INTSEL6,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
newline
bitfld.long 0x00 10.--11. "INTSEL5,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
bitfld.long 0x00 8.--9. "INTSEL4,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
newline
bitfld.long 0x00 6.--7. "INTSEL3,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
bitfld.long 0x00 4.--5. "INTSEL2,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
newline
bitfld.long 0x00 2.--3. "INTSEL1,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
bitfld.long 0x00 0.--1. "INTSEL0,Selection for Px.N As One of Interrupt Sources to EINT0 EINT1 EINT2 or EINT3\n" "0: Px.n pin is selected as one of interrupt..,1: Px.n pin is selected as one of interrupt..,2: Px.n pin is selected as one of interrupt..,3: Px.n pin is selected as one of interrupt.."
group.long 0x90++0x03
line.long 0x00 "PA_INTEN,PA Interrupt Enable Control Register"
bitfld.long 0x00 31. "REIEN15,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
bitfld.long 0x00 30. "REIEN14,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
newline
bitfld.long 0x00 29. "REIEN13,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
bitfld.long 0x00 28. "REIEN12,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
newline
bitfld.long 0x00 27. "REIEN11,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
bitfld.long 0x00 26. "REIEN10,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
newline
bitfld.long 0x00 25. "REIEN9,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
bitfld.long 0x00 24. "REIEN8,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
newline
bitfld.long 0x00 23. "REIEN7,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
bitfld.long 0x00 22. "REIEN6,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
newline
bitfld.long 0x00 21. "REIEN5,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
bitfld.long 0x00 20. "REIEN4,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
newline
bitfld.long 0x00 19. "REIEN3,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
bitfld.long 0x00 18. "REIEN2,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
newline
bitfld.long 0x00 17. "REIEN1,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
bitfld.long 0x00 16. "REIEN0,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
newline
bitfld.long 0x00 15. "FEIEN15,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
bitfld.long 0x00 14. "FEIEN14,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
newline
bitfld.long 0x00 13. "FEIEN13,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
bitfld.long 0x00 12. "FEIEN12,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
newline
bitfld.long 0x00 11. "FEIEN11,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
bitfld.long 0x00 10. "FEIEN10,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
newline
bitfld.long 0x00 9. "FEIEN9,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
bitfld.long 0x00 8. "FEIEN8,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
newline
bitfld.long 0x00 7. "FEIEN7,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
bitfld.long 0x00 6. "FEIEN6,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
newline
bitfld.long 0x00 5. "FEIEN5,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
bitfld.long 0x00 4. "FEIEN4,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
newline
bitfld.long 0x00 3. "FEIEN3,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
bitfld.long 0x00 2. "FEIEN2,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
newline
bitfld.long 0x00 1. "FEIEN1,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
bitfld.long 0x00 0. "FEIEN0,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
group.long 0x94++0x03
line.long 0x00 "PB_INTEN,PB Interrupt Enable Control Register"
bitfld.long 0x00 31. "REIEN15,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
bitfld.long 0x00 30. "REIEN14,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
newline
bitfld.long 0x00 29. "REIEN13,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
bitfld.long 0x00 28. "REIEN12,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
newline
bitfld.long 0x00 27. "REIEN11,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
bitfld.long 0x00 26. "REIEN10,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
newline
bitfld.long 0x00 25. "REIEN9,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
bitfld.long 0x00 24. "REIEN8,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
newline
bitfld.long 0x00 23. "REIEN7,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
bitfld.long 0x00 22. "REIEN6,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
newline
bitfld.long 0x00 21. "REIEN5,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
bitfld.long 0x00 20. "REIEN4,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
newline
bitfld.long 0x00 19. "REIEN3,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
bitfld.long 0x00 18. "REIEN2,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
newline
bitfld.long 0x00 17. "REIEN1,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
bitfld.long 0x00 16. "REIEN0,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
newline
bitfld.long 0x00 15. "FEIEN15,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
bitfld.long 0x00 14. "FEIEN14,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
newline
bitfld.long 0x00 13. "FEIEN13,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
bitfld.long 0x00 12. "FEIEN12,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
newline
bitfld.long 0x00 11. "FEIEN11,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
bitfld.long 0x00 10. "FEIEN10,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
newline
bitfld.long 0x00 9. "FEIEN9,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
bitfld.long 0x00 8. "FEIEN8,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
newline
bitfld.long 0x00 7. "FEIEN7,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
bitfld.long 0x00 6. "FEIEN6,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
newline
bitfld.long 0x00 5. "FEIEN5,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
bitfld.long 0x00 4. "FEIEN4,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
newline
bitfld.long 0x00 3. "FEIEN3,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
bitfld.long 0x00 2. "FEIEN2,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
newline
bitfld.long 0x00 1. "FEIEN1,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
bitfld.long 0x00 0. "FEIEN0,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
group.long 0x98++0x03
line.long 0x00 "PC_INTEN,PC Interrupt Enable Control Register"
bitfld.long 0x00 31. "REIEN15,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
bitfld.long 0x00 30. "REIEN14,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
newline
bitfld.long 0x00 29. "REIEN13,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
bitfld.long 0x00 28. "REIEN12,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
newline
bitfld.long 0x00 27. "REIEN11,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
bitfld.long 0x00 26. "REIEN10,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
newline
bitfld.long 0x00 25. "REIEN9,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
bitfld.long 0x00 24. "REIEN8,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
newline
bitfld.long 0x00 23. "REIEN7,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
bitfld.long 0x00 22. "REIEN6,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
newline
bitfld.long 0x00 21. "REIEN5,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
bitfld.long 0x00 20. "REIEN4,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
newline
bitfld.long 0x00 19. "REIEN3,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
bitfld.long 0x00 18. "REIEN2,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
newline
bitfld.long 0x00 17. "REIEN1,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
bitfld.long 0x00 16. "REIEN0,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
newline
bitfld.long 0x00 15. "FEIEN15,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
bitfld.long 0x00 14. "FEIEN14,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
newline
bitfld.long 0x00 13. "FEIEN13,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
bitfld.long 0x00 12. "FEIEN12,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
newline
bitfld.long 0x00 11. "FEIEN11,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
bitfld.long 0x00 10. "FEIEN10,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
newline
bitfld.long 0x00 9. "FEIEN9,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
bitfld.long 0x00 8. "FEIEN8,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
newline
bitfld.long 0x00 7. "FEIEN7,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
bitfld.long 0x00 6. "FEIEN6,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
newline
bitfld.long 0x00 5. "FEIEN5,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
bitfld.long 0x00 4. "FEIEN4,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
newline
bitfld.long 0x00 3. "FEIEN3,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
bitfld.long 0x00 2. "FEIEN2,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
newline
bitfld.long 0x00 1. "FEIEN1,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
bitfld.long 0x00 0. "FEIEN0,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
group.long 0x9C++0x03
line.long 0x00 "PD_INTEN,PD Interrupt Enable Control Register"
bitfld.long 0x00 31. "REIEN15,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
bitfld.long 0x00 30. "REIEN14,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
newline
bitfld.long 0x00 29. "REIEN13,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
bitfld.long 0x00 28. "REIEN12,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
newline
bitfld.long 0x00 27. "REIEN11,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
bitfld.long 0x00 26. "REIEN10,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
newline
bitfld.long 0x00 25. "REIEN9,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
bitfld.long 0x00 24. "REIEN8,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
newline
bitfld.long 0x00 23. "REIEN7,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
bitfld.long 0x00 22. "REIEN6,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
newline
bitfld.long 0x00 21. "REIEN5,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
bitfld.long 0x00 20. "REIEN4,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
newline
bitfld.long 0x00 19. "REIEN3,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
bitfld.long 0x00 18. "REIEN2,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
newline
bitfld.long 0x00 17. "REIEN1,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
bitfld.long 0x00 16. "REIEN0,Port A-d Pin[N] Control Rising Edge of Input Px.N Pin to Trigger the Interrupt \nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n low to high interrupt Disabled,1: Px.n low to high interrupt Enabled"
newline
bitfld.long 0x00 15. "FEIEN15,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
bitfld.long 0x00 14. "FEIEN14,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
newline
bitfld.long 0x00 13. "FEIEN13,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
bitfld.long 0x00 12. "FEIEN12,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
newline
bitfld.long 0x00 11. "FEIEN11,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
bitfld.long 0x00 10. "FEIEN10,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
newline
bitfld.long 0x00 9. "FEIEN9,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
bitfld.long 0x00 8. "FEIEN8,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
newline
bitfld.long 0x00 7. "FEIEN7,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
bitfld.long 0x00 6. "FEIEN6,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
newline
bitfld.long 0x00 5. "FEIEN5,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
bitfld.long 0x00 4. "FEIEN4,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
newline
bitfld.long 0x00 3. "FEIEN3,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
bitfld.long 0x00 2. "FEIEN2,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
newline
bitfld.long 0x00 1. "FEIEN1,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
bitfld.long 0x00 0. "FEIEN0,Port A-d Pin[N] Control Falling Edge of Input Px.N Pin to Trigger the Interrupt\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n high to low interrupt Disabled,1: Px.n high to low interrupt Enabled"
group.long 0xA0++0x03
line.long 0x00 "GPIO_INTCTL,Interrupt Latch Trigger Selection Register"
bitfld.long 0x00 8. "INTCTL,Interrupt Request Source Control\n" "0: When the GPIO interrupt occurs the GPIO..,1: When the GPIO interrupt occurs the interrupt.."
bitfld.long 0x00 7. "WKEN3,GPIO Interrupt Wake Up System Enable Control\n" "0: No effect,1: EINTn can wake up the chip from Idle and.."
newline
bitfld.long 0x00 6. "WKEN2,GPIO Interrupt Wake Up System Enable Control\n" "0: No effect,1: EINTn can wake up the chip from Idle and.."
bitfld.long 0x00 5. "WKEN1,GPIO Interrupt Wake Up System Enable Control\n" "0: No effect,1: EINTn can wake up the chip from Idle and.."
newline
bitfld.long 0x00 4. "WKEN0,GPIO Interrupt Wake Up System Enable Control\n" "0: No effect,1: EINTn can wake up the chip from Idle and.."
bitfld.long 0x00 3. "INTLHEN3,Enable Latch PA.N/PB.N/PC.N/PD.N Value When EINTn Happen\n" "0: No effect,1: When EINTn interrupt has happened PA_LATCHDAT.."
newline
bitfld.long 0x00 2. "INTLHEN2,Enable Latch PA.N/PB.N/PC.N/PD.N Value When EINTn Happen\n" "0: No effect,1: When EINTn interrupt has happened PA_LATCHDAT.."
bitfld.long 0x00 1. "INTLHEN1,Enable Latch PA.N/PB.N/PC.N/PD.N Value When EINTn Happen\n" "0: No effect,1: When EINTn interrupt has happened PA_LATCHDAT.."
newline
bitfld.long 0x00 0. "INTLHEN0,Enable Latch PA.N/PB.N/PC.N/PD.N Value When EINTn Happen\n" "0: No effect,1: When EINTn interrupt has happened PA_LATCHDAT.."
rgroup.long 0xA4++0x03
line.long 0x00 "PA_LATCHDAT,PA Interrupt Latch Value"
bitfld.long 0x00 15. "DAT15,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
bitfld.long 0x00 14. "DAT14,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
newline
bitfld.long 0x00 13. "DAT13,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
bitfld.long 0x00 12. "DAT12,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
newline
bitfld.long 0x00 11. "DAT11,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
bitfld.long 0x00 10. "DAT10,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
newline
bitfld.long 0x00 9. "DAT9,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
bitfld.long 0x00 8. "DAT8,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
newline
bitfld.long 0x00 7. "DAT7,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
bitfld.long 0x00 6. "DAT6,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
newline
bitfld.long 0x00 5. "DAT5,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
bitfld.long 0x00 4. "DAT4,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
newline
bitfld.long 0x00 3. "DAT3,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
bitfld.long 0x00 2. "DAT2,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
newline
bitfld.long 0x00 1. "DAT1,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
bitfld.long 0x00 0. "DAT0,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
group.long 0xA8++0x03
line.long 0x00 "PB_LATCHDAT,PB Interrupt Latch Value"
rbitfld.long 0x00 15. "DAT15,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
rbitfld.long 0x00 14. "DAT14,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
newline
rbitfld.long 0x00 13. "DAT13,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
rbitfld.long 0x00 12. "DAT12,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
newline
rbitfld.long 0x00 11. "DAT11,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
rbitfld.long 0x00 10. "DAT10,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
newline
rbitfld.long 0x00 9. "DAT9,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
rbitfld.long 0x00 8. "DAT8,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
newline
rbitfld.long 0x00 7. "DAT7,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
rbitfld.long 0x00 6. "DAT6,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
newline
rbitfld.long 0x00 5. "DAT5,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
rbitfld.long 0x00 4. "DAT4,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
newline
rbitfld.long 0x00 3. "DAT3,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
rbitfld.long 0x00 2. "DAT2,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
newline
rbitfld.long 0x00 1. "DAT1,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
rbitfld.long 0x00 0. "DAT0,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
group.long 0xAC++0x03
line.long 0x00 "PC_LATCHDAT,PC Interrupt Latch Value"
rbitfld.long 0x00 15. "DAT15,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
rbitfld.long 0x00 14. "DAT14,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
newline
rbitfld.long 0x00 13. "DAT13,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
rbitfld.long 0x00 12. "DAT12,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
newline
rbitfld.long 0x00 11. "DAT11,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
rbitfld.long 0x00 10. "DAT10,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
newline
rbitfld.long 0x00 9. "DAT9,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
rbitfld.long 0x00 8. "DAT8,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
newline
rbitfld.long 0x00 7. "DAT7,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
rbitfld.long 0x00 6. "DAT6,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
newline
rbitfld.long 0x00 5. "DAT5,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
rbitfld.long 0x00 4. "DAT4,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
newline
rbitfld.long 0x00 3. "DAT3,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
rbitfld.long 0x00 2. "DAT2,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
newline
rbitfld.long 0x00 1. "DAT1,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
rbitfld.long 0x00 0. "DAT0,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
group.long 0xB0++0x03
line.long 0x00 "PD_LATCHDAT,PD Interrupt Latch Value"
rbitfld.long 0x00 15. "DAT15,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
rbitfld.long 0x00 14. "DAT14,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
newline
rbitfld.long 0x00 13. "DAT13,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
rbitfld.long 0x00 12. "DAT12,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
newline
rbitfld.long 0x00 11. "DAT11,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
rbitfld.long 0x00 10. "DAT10,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
newline
rbitfld.long 0x00 9. "DAT9,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
rbitfld.long 0x00 8. "DAT8,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
newline
rbitfld.long 0x00 7. "DAT7,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
rbitfld.long 0x00 6. "DAT6,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
newline
rbitfld.long 0x00 5. "DAT5,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
rbitfld.long 0x00 4. "DAT4,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
newline
rbitfld.long 0x00 3. "DAT3,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
rbitfld.long 0x00 2. "DAT2,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
newline
rbitfld.long 0x00 1. "DAT1,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
rbitfld.long 0x00 0. "DAT0,Latch Px.N Interrupt Value\nLatched value of Px.n while the EINT (EINT0~EINT3) selected by GPIO_INTCTL is active.\nNote: \n" "0,1"
group.long 0xB4++0x03
line.long 0x00 "GPIO_INTSTSA_B,EINT0~3 Interrupt Trigger Source Indicator From PA and PB"
bitfld.long 0x00 31. "PBIF15,Port B Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at PB.n1 = PB.n..,1: Clear the corresponding pending interrupt"
bitfld.long 0x00 30. "PBIF14,Port B Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at PB.n1 = PB.n..,1: Clear the corresponding pending interrupt"
newline
bitfld.long 0x00 29. "PBIF13,Port B Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at PB.n1 = PB.n..,1: Clear the corresponding pending interrupt"
bitfld.long 0x00 28. "PBIF12,Port B Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at PB.n1 = PB.n..,1: Clear the corresponding pending interrupt"
newline
bitfld.long 0x00 27. "PBIF11,Port B Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at PB.n1 = PB.n..,1: Clear the corresponding pending interrupt"
bitfld.long 0x00 26. "PBIF10,Port B Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at PB.n1 = PB.n..,1: Clear the corresponding pending interrupt"
newline
bitfld.long 0x00 25. "PBIF9,Port B Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at PB.n1 = PB.n..,1: Clear the corresponding pending interrupt"
bitfld.long 0x00 24. "PBIF8,Port B Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at PB.n1 = PB.n..,1: Clear the corresponding pending interrupt"
newline
bitfld.long 0x00 23. "PBIF7,Port B Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at PB.n1 = PB.n..,1: Clear the corresponding pending interrupt"
bitfld.long 0x00 22. "PBIF6,Port B Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at PB.n1 = PB.n..,1: Clear the corresponding pending interrupt"
newline
bitfld.long 0x00 21. "PBIF5,Port B Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at PB.n1 = PB.n..,1: Clear the corresponding pending interrupt"
bitfld.long 0x00 20. "PBIF4,Port B Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at PB.n1 = PB.n..,1: Clear the corresponding pending interrupt"
newline
bitfld.long 0x00 19. "PBIF3,Port B Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at PB.n1 = PB.n..,1: Clear the corresponding pending interrupt"
bitfld.long 0x00 18. "PBIF2,Port B Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at PB.n1 = PB.n..,1: Clear the corresponding pending interrupt"
newline
bitfld.long 0x00 17. "PBIF1,Port B Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at PB.n1 = PB.n..,1: Clear the corresponding pending interrupt"
bitfld.long 0x00 16. "PBIF0,Port B Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at PB.n1 = PB.n..,1: Clear the corresponding pending interrupt"
newline
bitfld.long 0x00 15. "PAIF15,Port a Pin[N] Interrupt Source Flag\nWrite Operation:\nWhen this bit is read as 1 it indicates that PA.n is a trigger source to generate the interrupt.\nNote: Write 1 to clear the correspond interrupt source" "0: No action.\nNo interrupt at PA.n,1: Clear the corresponding pending.."
bitfld.long 0x00 14. "PAIF14,Port a Pin[N] Interrupt Source Flag\nWrite Operation:\nWhen this bit is read as 1 it indicates that PA.n is a trigger source to generate the interrupt.\nNote: Write 1 to clear the correspond interrupt source" "0: No action.\nNo interrupt at PA.n,1: Clear the corresponding pending.."
newline
bitfld.long 0x00 13. "PAIF13,Port a Pin[N] Interrupt Source Flag\nWrite Operation:\nWhen this bit is read as 1 it indicates that PA.n is a trigger source to generate the interrupt.\nNote: Write 1 to clear the correspond interrupt source" "0: No action.\nNo interrupt at PA.n,1: Clear the corresponding pending.."
bitfld.long 0x00 12. "PAIF12,Port a Pin[N] Interrupt Source Flag\nWrite Operation:\nWhen this bit is read as 1 it indicates that PA.n is a trigger source to generate the interrupt.\nNote: Write 1 to clear the correspond interrupt source" "0: No action.\nNo interrupt at PA.n,1: Clear the corresponding pending.."
newline
bitfld.long 0x00 11. "PAIF11,Port a Pin[N] Interrupt Source Flag\nWrite Operation:\nWhen this bit is read as 1 it indicates that PA.n is a trigger source to generate the interrupt.\nNote: Write 1 to clear the correspond interrupt source" "0: No action.\nNo interrupt at PA.n,1: Clear the corresponding pending.."
bitfld.long 0x00 10. "PAIF10,Port a Pin[N] Interrupt Source Flag\nWrite Operation:\nWhen this bit is read as 1 it indicates that PA.n is a trigger source to generate the interrupt.\nNote: Write 1 to clear the correspond interrupt source" "0: No action.\nNo interrupt at PA.n,1: Clear the corresponding pending.."
newline
bitfld.long 0x00 9. "PAIF9,Port a Pin[N] Interrupt Source Flag\nWrite Operation:\nWhen this bit is read as 1 it indicates that PA.n is a trigger source to generate the interrupt.\nNote: Write 1 to clear the correspond interrupt source" "0: No action.\nNo interrupt at PA.n,1: Clear the corresponding pending.."
bitfld.long 0x00 8. "PAIF8,Port a Pin[N] Interrupt Source Flag\nWrite Operation:\nWhen this bit is read as 1 it indicates that PA.n is a trigger source to generate the interrupt.\nNote: Write 1 to clear the correspond interrupt source" "0: No action.\nNo interrupt at PA.n,1: Clear the corresponding pending.."
newline
bitfld.long 0x00 7. "PAIF7,Port a Pin[N] Interrupt Source Flag\nWrite Operation:\nWhen this bit is read as 1 it indicates that PA.n is a trigger source to generate the interrupt.\nNote: Write 1 to clear the correspond interrupt source" "0: No action.\nNo interrupt at PA.n,1: Clear the corresponding pending.."
bitfld.long 0x00 6. "PAIF6,Port a Pin[N] Interrupt Source Flag\nWrite Operation:\nWhen this bit is read as 1 it indicates that PA.n is a trigger source to generate the interrupt.\nNote: Write 1 to clear the correspond interrupt source" "0: No action.\nNo interrupt at PA.n,1: Clear the corresponding pending.."
newline
bitfld.long 0x00 5. "PAIF5,Port a Pin[N] Interrupt Source Flag\nWrite Operation:\nWhen this bit is read as 1 it indicates that PA.n is a trigger source to generate the interrupt.\nNote: Write 1 to clear the correspond interrupt source" "0: No action.\nNo interrupt at PA.n,1: Clear the corresponding pending.."
bitfld.long 0x00 4. "PAIF4,Port a Pin[N] Interrupt Source Flag\nWrite Operation:\nWhen this bit is read as 1 it indicates that PA.n is a trigger source to generate the interrupt.\nNote: Write 1 to clear the correspond interrupt source" "0: No action.\nNo interrupt at PA.n,1: Clear the corresponding pending.."
newline
bitfld.long 0x00 3. "PAIF3,Port a Pin[N] Interrupt Source Flag\nWrite Operation:\nWhen this bit is read as 1 it indicates that PA.n is a trigger source to generate the interrupt.\nNote: Write 1 to clear the correspond interrupt source" "0: No action.\nNo interrupt at PA.n,1: Clear the corresponding pending.."
bitfld.long 0x00 2. "PAIF2,Port a Pin[N] Interrupt Source Flag\nWrite Operation:\nWhen this bit is read as 1 it indicates that PA.n is a trigger source to generate the interrupt.\nNote: Write 1 to clear the correspond interrupt source" "0: No action.\nNo interrupt at PA.n,1: Clear the corresponding pending.."
newline
bitfld.long 0x00 1. "PAIF1,Port a Pin[N] Interrupt Source Flag\nWrite Operation:\nWhen this bit is read as 1 it indicates that PA.n is a trigger source to generate the interrupt.\nNote: Write 1 to clear the correspond interrupt source" "0: No action.\nNo interrupt at PA.n,1: Clear the corresponding pending.."
bitfld.long 0x00 0. "PAIF0,Port a Pin[N] Interrupt Source Flag\nWrite Operation:\nWhen this bit is read as 1 it indicates that PA.n is a trigger source to generate the interrupt.\nNote: Write 1 to clear the correspond interrupt source" "0: No action.\nNo interrupt at PA.n,1: Clear the corresponding pending.."
group.long 0xB8++0x03
line.long 0x00 "GPIO_INTSTSC_D,EINT0~3 Interrupt Trigger Source Indicator From PC and PD"
bitfld.long 0x00 20. "PDIF4,Port D Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at PD.n,1: Clear the corresponding pending.."
bitfld.long 0x00 19. "PDIF3,Port D Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at PD.n,1: Clear the corresponding pending.."
newline
bitfld.long 0x00 18. "PDIF2,Port D Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at PD.n,1: Clear the corresponding pending.."
bitfld.long 0x00 17. "PDIF1,Port D Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at PD.n,1: Clear the corresponding pending.."
newline
bitfld.long 0x00 16. "PDIF0,Port D Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at PD.n,1: Clear the corresponding pending.."
bitfld.long 0x00 14. "PCIF14,Port C Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at PC.n,1: Clear the corresponding pending.."
newline
bitfld.long 0x00 13. "PCIF13,Port C Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at PC.n,1: Clear the corresponding pending.."
bitfld.long 0x00 12. "PCIF12,Port C Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at PC.n,1: Clear the corresponding pending.."
newline
bitfld.long 0x00 11. "PCIF11,Port C Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at PC.n,1: Clear the corresponding pending.."
bitfld.long 0x00 10. "PCIF10,Port C Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at PC.n,1: Clear the corresponding pending.."
newline
bitfld.long 0x00 9. "PCIF9,Port C Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at PC.n,1: Clear the corresponding pending.."
bitfld.long 0x00 8. "PCIF8,Port C Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at PC.n,1: Clear the corresponding pending.."
newline
bitfld.long 0x00 7. "PCIF7,Port C Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at PC.n,1: Clear the corresponding pending.."
bitfld.long 0x00 6. "PCIF6,Port C Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at PC.n,1: Clear the corresponding pending.."
newline
bitfld.long 0x00 5. "PCIF5,Port C Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at PC.n,1: Clear the corresponding pending.."
bitfld.long 0x00 4. "PCIF4,Port C Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at PC.n,1: Clear the corresponding pending.."
newline
bitfld.long 0x00 3. "PCIF3,Port C Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at PC.n,1: Clear the corresponding pending.."
bitfld.long 0x00 2. "PCIF2,Port C Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at PC.n,1: Clear the corresponding pending.."
newline
bitfld.long 0x00 1. "PCIF1,Port C Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at PC.n,1: Clear the corresponding pending.."
bitfld.long 0x00 0. "PCIF0,Port C Pin[N] Interrupt Source Flag\nWrite Operation:\n" "0: No action.\nNo interrupt at PC.n,1: Clear the corresponding pending.."
tree.end
tree "I2C"
repeat 2. (list 0. 1.) (list ad:0x400E4000 ad:0x400E5000)
tree "I2C$1"
base $2
group.long 0x00++0x03
line.long 0x00 "I2C_CTL,I2C Control Register"
bitfld.long 0x00 7. "INTEN,I2C Interrupt Enable Control\n" "0: I2C interrupt Disabled,1: I2C interrupt Enabled"
bitfld.long 0x00 6. "I2CEN,I2C Controller Enable Control\n" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 5. "STA,I2C START Control\nSetting STA to logic 1 to enter Master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free" "0,1"
bitfld.long 0x00 4. "STO,I2C STOP Control\nIn Master mode setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically" "0,1"
newline
bitfld.long 0x00 3. "SI,I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS register the SI flag is set by hardware and if bit INTEN (I2C_CTL [7]) is set the I2C interrupt is requested" "0,1"
bitfld.long 0x00 2. "AA,Assert Acknowledge Control\n" "0,1"
group.long 0x04++0x03
line.long 0x00 "I2C_ADDR0,I2C Slave Address Register0"
hexmask.long.byte 0x00 1.--7. 1. "ADDR,I2C Address Bits\nThe content of this register is irrelevant when I2C is in Master mode"
bitfld.long 0x00 0. "GC,General Call Function\n" "0: General Call Function Disabled,1: General Call Function Enabled"
group.long 0x08++0x03
line.long 0x00 "I2C_DAT,I2C Data Register"
hexmask.long.byte 0x00 0.--7. 1. "DAT,I2C Data Bits\nBit [7:0] is located with the 8-bit transferred data of I2C serial port"
rgroup.long 0x0C++0x03
line.long 0x00 "I2C_STATUS,I2C Status Register"
hexmask.long.byte 0x00 0.--7. 1. "STATUS,I2C Status Bits\nThe status register of I2C:\nThe three least significant bits are always 0"
group.long 0x10++0x03
line.long 0x00 "I2C_CLKDIV,I2C Clock Divided Register"
hexmask.long.byte 0x00 0.--7. 1. "DIVIDER,I2C Clock Divided Bits\n The minimum value of DIVIDER is 4"
group.long 0x14++0x03
line.long 0x00 "I2C_TOCTL,I2C Time-out Control Register"
bitfld.long 0x00 2. "TOCEN,Time-out Counter Enable Control\nNote: When Enabled the 14-bit time-out counter will start counting when SI (I2C_CTL[3]) is cleared" "0: Disabled,1: Enabled"
bitfld.long 0x00 1. "TOCDIV4,Time-out Counter Input Clock Divided by 4\nNote When Enabled The time-out period is extend 4 times" "0: Disabled,1: Enabled"
newline
bitfld.long 0x00 0. "TOIF,Time-out Flag\nThis bit is set by H/W when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN (I2C_CTL[7])) is set to 1.\nWrite 1 to clear this bit" "0,1"
repeat 3. (strings "1" "2" "3" )(list 0x0 0x4 0x8 )
group.long ($2+0x18)++0x03
line.long 0x00 "I2C_ADDR$1,I2C Slave Address Register $1"
hexmask.long.byte 0x00 1.--7. 1. "ADDR,I2C Address Bits\nThe content of this register is irrelevant when I2C is in Master mode"
bitfld.long 0x00 0. "GC,General Call Function\n" "0: General Call Function Disabled,1: General Call Function Enabled"
repeat.end
repeat 4. (strings "0" "1" "2" "3" )(list 0x0 0x4 0x8 0xC )
group.long ($2+0x24)++0x03
line.long 0x00 "I2C_ADDRMSK$1,I2C Slave Address Mask Register $1"
hexmask.long.byte 0x00 1.--7. 1. "ADDRMSK,I2C Address Mask Bits\nI2C bus controllers support multiple address recognition with four address mask register"
repeat.end
group.long 0x3C++0x03
line.long 0x00 "I2C_WKCTL,I2C Wake-up Control Register"
bitfld.long 0x00 0. "WKEN,I2C Wake-up Enable Control\n" "0: I2C wake-up function Disabled,1: I2C wake-up function Enabled"
group.long 0x40++0x03
line.long 0x00 "I2C_WKSTS,I2C Wake-up Status Register"
bitfld.long 0x00 0. "WKIF,I2C Wake-up Flag\nNote: Software can write 1 to clear this bit" "0: No wake up occurred,1: Wake up from Power-down mode"
tree.end
repeat.end
tree.end
tree "I2S"
base ad:0x400E8000
group.long 0x00++0x03
line.long 0x00 "I2S_CTL,I2S Control Register"
bitfld.long 0x00 29. "CODECRST,Internal CODEC Hardware Reset Control\n" "0: Reset Operation,1: Normal Operation"
bitfld.long 0x00 28. "CODECSEL,Internal CODEC or External CODEC Selection\n" "0: I2S interface connected to internal CODEC,1: I2S interface connected to external CODEC"
newline
bitfld.long 0x00 26. "SLAVE,Slave Mode\nI2S can operate as master or slave" "0: Master mode,1: Slave mode"
bitfld.long 0x00 25. "MCLKEN,Master Clock Enable Control\nNote1: I2S_MCLK is always output.\nNote2: I2S_MCLK frequency is controlled by MCLKDIV[5:0]" "0: I2S master clock output Disabled,1: I2S master clock output Enabled"
newline
bitfld.long 0x00 24. "PCMEN,PCM Interface Enable Control\n" "0: I2S Interface,1: PCM Interface"
bitfld.long 0x00 23. "RXLCH,Receive Left Channel Enable Control\n" "0: Receives right channel data when monaural..,1: Receives left channel data when monaural.."
newline
bitfld.long 0x00 21. "RXDMAEN,RX DMA Enable Control (Record Path)\nNote: The I2S_RXSTADDR will be updated to new setting only when RXDMAEN is from low to high" "0: RX DMA mode Disabled,1: RX DMA mode Enabled"
bitfld.long 0x00 20. "TXDMAEN,TX DMA Enable Control (Transmit Path)\nNote: The I2S_TXSTADDR will be updated to new setting only when TXDMAEN is from low to high" "0: TX DMA mode Disabled,1: TX DMA mode Enabled"
newline
bitfld.long 0x00 19. "RXCLR,Clear Receive FIFO\nNote: This bit will be cleared to 0 automatically.\nNote2: If clearing the receiver FIFO RXCNT (I2S_STATUS[27:24]) returns to 0x0 and receiver FIFO becomes empty" "0: No effect,1: Receiver FIFO will be cleared"
bitfld.long 0x00 18. "TXCLR,Clear Transmit FIFO\nNote: This bit will be cleared to 0 automatically.\nNote2: If clearing the transmit FIFO TXCNT (I2S_STATUS[31:28]) returns to 0x0 and transmit FIFO becomes empty" "0: No effect,1: Transmit FIFO will be cleared"
newline
bitfld.long 0x00 17. "LZCEN,Left Channel Zero-cross Detect Enable Control\nIf this bit is set to 1 when left channel data sign bit change or next shift data bits are all zero then LZCIF flag in I2S_STATUS register is set to 1.\n" "0: Left channel zero-cross detect Disabled,1: Left channel zero-cross detect Enabled"
bitfld.long 0x00 16. "RZCEN,Right Channel Zero-cross Detection Enable Control\nIf this bit is set to 1 when right channel data sign bit change or next shift data bits are all zero then RZCIF flag in I2S_STATUS register is set to 1.\n" "0: Right channel zero-cross detect Disabled,1: Right channel zero-cross detect Enabled"
newline
bitfld.long 0x00 12.--15. "RXTH,Receive FIFO Threshold Level\nWhen received data word(s) in buffer is equal to or higher than threshold level then RXTHIF flag is set.\n" "0: 1 word data in receive FIFO,1: 2 word data in receive FIFO,2: 3 word data in receive FIFO,3: 4 word data in receive FIFO,4: 5 word data in receive FIFO,5: 6 word data in receive FIFO,6: 7 word data in receive FIFO,7: 8 word data in receive FIFO,8: 9 word data in receive FIFO,9: 10 word data in receive FIFO,10: 11 word data in receive FIFO,11: 12 word data in receive FIFO,12: 13 word data in receive FIFO,13: 14 word data in receive FIFO,14: 15 word data in receive FIFO,15: 16 word data in receive FIFO"
bitfld.long 0x00 8.--11. "TXTH,Transmit FIFO Threshold Level\nIf remain data word (32 bits) in transmit FIFO is the same or less than threshold level then TXTHIF flag is set.\n" "0: 0 word data in transmit FIFO,1: 1 word data in transmit FIFO,2: 2 words data in transmit FIFO,3: 3 words data in transmit FIFO,4: 4 words data in transmit FIFO,5: 5 words data in transmit FIFO,6: 6 words data in transmit FIFO,7: 7 words data in transmit FIFO,8: 8 word data in transmit FIFO,9: 9 word data in transmit FIFO,10: 10 words data in transmit FIFO,11: 11 words data in transmit FIFO,12: 12 words data in transmit FIFO,13: 13 words data in transmit FIFO,14: 14 words data in transmit FIFO,15: 15 words data in transmit FIFO"
newline
bitfld.long 0x00 7. "FORMAT,Data Format Selection\n" "0: I2S data format.\nPCM mode A,1: MSB justified data format.\nPCM mode B"
bitfld.long 0x00 6. "MONO,Monaural Data\n" "0: Data is stereo format,1: Data is monaural format"
newline
bitfld.long 0x00 4.--5. "WDWIDTH,Word Width\n" "0: Data is 8-bit,1: Data is 16-bit,2: Data is 24-bit,3: Data is 32-bit"
bitfld.long 0x00 3. "MUTE,Transmit Mute Enable Control\n" "0: Transmit data is shifted from buffer,1: Transmit data is fixed to zero"
newline
bitfld.long 0x00 2. "RXEN,Receive Enable Control\n" "0: Data receiving Disabled,1: Data receiving Enabled"
bitfld.long 0x00 1. "TXEN,Transmit Enable Control\n" "0: Data transmission Disabled,1: Data transmission Enabled"
newline
bitfld.long 0x00 0. "I2SEN,I2S Controller Enable Control\n" "0: Disabled,1: Enabled"
group.long 0x04++0x03
line.long 0x00 "I2S_CLKDIV,I2S Clock Divider Control Register"
hexmask.long.word 0x00 8.--16. 1. "BCLKDIV,Bit Clock Divider\nUser can program these bits to generate the frequency of BCLK when I2S operates in master mode"
bitfld.long 0x00 0.--5. "MCLKDIV,Master Clock Divider\nIf F_I2SCLK is (2*MCLKDIV)*256*F_LRCLK then software can program these bits to generate 256*F_LRCLK clock frequency as master clock to audio CODEC" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x03
line.long 0x00 "I2S_IEN,I2S Interrupt Enable Register"
bitfld.long 0x00 12. "LZCIEN,Left Channel Zero-cross Interrupt Enable Control\nInterrupt occurs if this bit is set to 1 and left channel zero-cross is detected.\n" "0: Interrupt Disabled,1: Interrupt Enabled"
bitfld.long 0x00 11. "RZCIEN,Right Channel Zero-cross Interrupt Enable Control\nInterrupt occurs if this bit is set to 1 and right channel zero-cross is detected.\n" "0: Interrupt Disabled,1: Interrupt Enabled"
newline
bitfld.long 0x00 10. "TXTHIEN,Transmit FIFO Threshold Level Interrupt Enable Control\nInterrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than TXTH[3:0].\n" "0: Interrupt Disabled,1: Interrupt Enabled"
bitfld.long 0x00 9. "TXOVIEN,Transmit FIFO Overflow Interrupt Enable Control\nInterrupt occurs if this bit is set to 1 and transmit FIFO overflow flag is set to 1.\n" "0: Interrupt Disabled,1: Interrupt Enabled"
newline
bitfld.long 0x00 8. "TXUDIEN,Transmit FIFO Underflow Interrupt Enable Control\nInterrupt occurs if this bit is set to 1 and transmit FIFO underflow flag is set to 1.\n" "0: Interrupt Disabled,1: Interrupt Enabled"
bitfld.long 0x00 7. "TDMATIEN,TX DMA Threshold Interrupt Enable Control\nInterrupt occurs if this bit is set to 1 and DMA current address is equal to I2S_TXTHADDR register\n" "0: Interrupt Disabled,1: Interrupt Enabled"
newline
bitfld.long 0x00 6. "TDMAEIEN,TX DMA End Interrupt Enable Control\nInterrupt occurs if this bit is set to 1 and DMA current address is equal to I2S_TXEADDR register\n" "0: Interrupt Disabled,1: Interrupt Enabled"
bitfld.long 0x00 5. "RDMATIEN,RX DMA Threshold Interrupt Enable Control\nInterrupt occurs if this bit is set to 1 and DMA current address is equal to I2S_RXTHADDR register\n" "0: Interrupt Disabled,1: Interrupt Enabled"
newline
bitfld.long 0x00 4. "RDMAEIEN,RX DMA End Interrupt Enable Control\nInterrupt occurs if this bit is set to 1 and DMA current address is equal to I2S_RXEADDR register\n" "0: Interrupt Disabled,1: Interrupt Enabled"
bitfld.long 0x00 2. "RXTHIEN,Receive FIFO Threshold Level Interrupt Enable Control\nWhen data word in receive FIFO is equal to or higher then RXTH[3:0] and the RXTHIF bit is set to 1" "0: Interrupt Disabled,1: Interrupt Enabled"
newline
bitfld.long 0x00 1. "RXOVIEN,Receive FIFO Overflow Interrupt Enable Control\n" "0: Interrupt Disabled,1: Interrupt Enabled"
bitfld.long 0x00 0. "RXUDIEN,Receive FIFO Underflow Interrupt Enable Control\nIf software reads receive FIFO when it is empty the RXUDIF flag in I2S_STATUS register is set to 1.\n" "0: Interrupt Disabled,1: Interrupt Enabled"
group.long 0x0C++0x03
line.long 0x00 "I2S_STATUS,I2S Status Register"
bitfld.long 0x00 28.--31. "TXCNT,Transmit FIFO Level\nThese bits indicate word number in transmit FIFO\n" "0: No data or 16 words ( need to check the TX..,1: 1 word in transmit FIFO,?,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 words in transmit FIFO"
bitfld.long 0x00 24.--27. "RXCNT,Receive FIFO Level\nThese bits indicate word number in receive FIFO\n" "0: No data or 16 words (need to check the RX..,1: 1 word in receive FIFO,?,?,?,?,?,?,?,?,?,?,?,?,?,15: 15 words in receive FIFO"
newline
bitfld.long 0x00 23. "LZCIF,Left Channel Zero-cross Flag\nIt indicates left channel next sample data sign bit is changed or all data bits are zero.\nNote: Write 1 to clear this bit to 0" "0: No zero-cross,1: Left channel zero-cross is detected"
bitfld.long 0x00 22. "RZCIF,Right Channel Zero-cross Flag\nIt indicates right channel next sample data sign bit is changed or all data bits are zero.\nNote: Write 1 to clear this bit to 0" "0: No zero-cross,1: Right channel zero-cross is detected"
newline
bitfld.long 0x00 21. "TXBUSY,Transmit Busy\nThis bit is cleared to 0 when all data in transmit FIFO and shift buffer is shifted out" "0: Transmit shift buffer is empty,1: Transmit shift buffer is busy"
bitfld.long 0x00 20. "TXEMPTY,Transmit FIFO Empty\nThis bit reflect data word number in transmit FIFO is zero\nNote: This bit is read only" "0: Not empty,1: Empty"
newline
bitfld.long 0x00 19. "TXFULL,Transmit FIFO Full\nThis bit reflect data word number in transmit FIFO is 16\nNote: This bit is read only" "0: Not full,1: Full"
bitfld.long 0x00 18. "TXTHIF,Transmit FIFO Threshold Flag\nWhen data word(s) in transmit FIFO is equal or lower than threshold value set in TXTH[3:0] the TXTHIF bit becomes to 1" "0: Data word(s) in FIFO is higher than threshold..,1: Data word(s) in FIFO is equal or lower than.."
newline
bitfld.long 0x00 17. "TXOVIF,Transmit FIFO Overflow Flag\nWrite data to transmit FIFO when it is full and this bit set to 1\nNote: Write 1 to clear this bit to 0" "0: No overflow,1: Overflow"
bitfld.long 0x00 16. "TXUDIF,Transmit FIFO Underflow Flag\nWhen transmit FIFO is empty and shift logic hardware read data from data FIFO causes this set to 1.\nNote: Write 1 to clear this bit to 0" "0: No underflow,1: Underflow"
newline
bitfld.long 0x00 12. "RXEMPTY,Receive FIFO Empty\nThis bit reflects data words number in receive FIFO is zero\nNote: This bit is read only" "0: FIFO not empty,1: FIFO empty"
bitfld.long 0x00 11. "RXFULL,Receive FIFO Full\nThis bit reflect data words number in receive FIFO is 16\nNote: This bit is read only" "0: FIFO not full,1: FIFO full"
newline
bitfld.long 0x00 10. "RXTHIF,Receive FIFO Threshold Flag\nWhen data word(s) in receive FIFO is equal to or higher than the threshold value set in RXTH[3:0] the RXTHIF bit becomes to 1" "0: Data word(s) in FIFO is lower than threshold..,1: Data word(s) in FIFO is equal or higher than.."
bitfld.long 0x00 9. "RXOVIF,Receive FIFO Overflow Flag\nWhen receive FIFO is full and receive hardware attempt write to data into receive FIFO this bit is set to 1 and data in 1st buffer is overwritten.\nNote: Write 1 to clear this bit to 0" "0: No overflow occurred,1: Overflow occurred"
newline
bitfld.long 0x00 8. "RXUDIF,Receive FIFO Underflow Flag\nRead receive FIFO when it is empty" "0: No underflow occurred,1: Underflow occurred"
bitfld.long 0x00 7. "TDMATIF,TX DMA Equal Threshold Address Interrupt Flag\nIf TX DMA current address is equal to I2S_TXTHADDR register this interrupt flag will be set" "0: No TX Threshold Interrupt,1: TX Threshold Interrupt"
newline
bitfld.long 0x00 6. "TDMAEIF,TX DMA Equal End Address Interrupt Flag\nIf TX DMA current address is equal to I2S_TXEADDR register this interrupt flag will be set" "0: No TX End Interrupt,1: TX End Interrupt"
bitfld.long 0x00 5. "RDMATIF,RX DMA Equal Threshold Address Interrupt Flag\nIf RX DMA current address is equal to I2S_RXTHADDR register this interrupt flag will be set" "0: No RX Threshold Interrupt,1: RX Threshold Interrupt"
newline
bitfld.long 0x00 4. "RDMAEIF,RX DMA Equal End Address Interrupt Flag\nIf RX DMA current address is equal to I2S_RXEADDR register this interrupt flag will be set" "0: No RX End Interrupt,1: RX End Interrupt"
bitfld.long 0x00 3. "RIGHT,Right Channel\nIndicates that the current transmit data belongs to right channel\nNote: This bit is read only" "0: Left channel,1: Right channel"
newline
bitfld.long 0x00 2. "TXIF,I2S Transmit Interrupt\nNote1: This flag is triggered if any of LZCIF RZCIF TXTHIF TXOIF TXUDIF TDMATIF and TDMAEIF occurs.\nNote2: This bit is read only" "0: No transmit interrupt,1: Transmit interrupt"
bitfld.long 0x00 1. "RXIF,I2S Receive Interrupt\nNote1: This flag is triggered if any of RXTHIF RXOVIF RXUDIF RDMATIF and RDMAEIF occurs.\nNote2: This bit is read only" "0: No receive interrupt,1: Receive interrupt"
newline
bitfld.long 0x00 0. "I2SIF,I2S Interrupt Flag\nNote1: This flag is triggered if any of TXIF and RXIF bits are enabled.\nNote2: This bit is read only" "0: No I2S interrupt,1: I2S interrupt"
wgroup.long 0x10++0x03
line.long 0x00 "I2S_TX,I2S Transmit FIFO Register"
hexmask.long 0x00 0.--31. 1. "TX,Transmit FIFO Register\nI2S contains 16 words (16x32 bit) data FIFO for data transmssion"
rgroup.long 0x14++0x03
line.long 0x00 "I2S_RX,I2S Receive FIFO Register"
hexmask.long 0x00 0.--31. 1. "RX,Receive FIFO Register\nI2S contains 16 words (16x32 bit) data FIFO for data receiving"
group.long 0x18++0x03
line.long 0x00 "I2S_CODECCTL,I2S Virtual I2C Control Register"
bitfld.long 0x00 31. "BUSY,Busy Flag\nIf the register 'I2S_CODECCTL' has been written the HW would change the command to the I2C format because the internal audio CODEC interface is I2C" "0: I2C command is finished,1: I2C command is not finished"
hexmask.long.byte 0x00 24.--30. 1. "I2CCKDIV,SCK Clock Divider\nControl the SCK Timing Parameter.\nThe SCK frequency is (F_I2SCLK / (I2CCKDIV * 16)).\nNote: Cannot be zero.\nNote2: F_SCK must be lower than or equal to F_MCLK / 16"
newline
hexmask.long.byte 0x00 17.--23. 1. "DEVID,Internal Audio CODEC Device ID\nThis parameter should be set to 40H"
bitfld.long 0x00 16. "RW,Read or Write Command\nControl this command to read data from the internal audio CODEC or write data to.\n" "0: Read from the internal audio CODEC,1: Write to the internal audio CODEC"
newline
hexmask.long.byte 0x00 8.--15. 1. "ADDR,Address Information\nThis parameter is used to read from the internal audio CODEC or write to the internal audio CODEC"
hexmask.long.byte 0x00 0.--7. 1. "DAT,Data Information\nThis parameter is used to read from the internal audio CODEC or write to the internal audio CODEC"
group.long 0x20++0x03
line.long 0x00 "I2S_TXSTADDR,I2S TX DMA Start Address Register"
hexmask.long 0x00 0.--31. 1. "ADDR,TX DMA Start Address Register\nNote1: The address is word boundary.\nNote2: The address can't be set smaller than 0x2000_0000"
group.long 0x24++0x03
line.long 0x00 "I2S_TXTHADDR,I2S TX DMA Threshold Address Register"
hexmask.long 0x00 0.--31. 1. "ADDR,TX DMA Threshold Address Register\nNote1: The address is word boundary.\nNote2: The address can't be set smaller than 0x2000_0000"
group.long 0x28++0x03
line.long 0x00 "I2S_TXEADDR,I2S TX DMA End Address Register"
hexmask.long 0x00 0.--31. 1. "ADDR,TX DMA End Address Register\nNote1: The address is word boundary.\nNote2: If WDWIDTH[1:0] is equal to 0x2 or 0x3 user must set the correct end address to avoid the swap between right channel and left channel in stereo mode.\nNote2: The address.."
rgroup.long 0x2C++0x03
line.long 0x00 "I2S_TXCADDR,I2S TX DMA Current Address Register"
hexmask.long 0x00 0.--31. 1. "ADDR,TX DMA Current Address Register"
group.long 0x30++0x03
line.long 0x00 "I2S_RXSTADDR,I2S RX DMA Start Address Register"
hexmask.long 0x00 0.--31. 1. "ADDR,RX DMA Start Address Register\nNote1: The address is word boundary.\nNote2: The address can't be set smaller than 0x2000_0000"
group.long 0x34++0x03
line.long 0x00 "I2S_RXTHADDR,I2S RX DMA Threshold Address Register"
hexmask.long 0x00 0.--31. 1. "ADDR,RX DMA Threshold Address Register\nNote1: The address is word boundary.\nNote2: The address can't be set smaller than 0x2000_0000"
group.long 0x38++0x03
line.long 0x00 "I2S_RXEADDR,I2S RX DMA End Address Register"
hexmask.long 0x00 0.--31. 1. "ADDR,RX DMA End Address Register\nNote1: The address is word boundary.\nNote2: If WDWIDTH[1:0] is equal to 0x2 or 0x3 user must set the correct end address to avoid the swap between right channel and left channel in stereo mode.\nNote3: The address.."
rgroup.long 0x3C++0x03
line.long 0x00 "I2S_RXCADDR,I2S RX DMA Current Address Register"
hexmask.long 0x00 0.--31. 1. "ADDR,RX DMA Current Address Register"
group.long 0x40++0x03
line.long 0x00 "I2S_RXAVGCTL,I2S RX Data Average Control Register"
bitfld.long 0x00 0.--3. "WINSEL,RX Data Average Window Select\nNote: Every window size samples will generate one average result" "0: Average window is 1 (2^0) sample,1: Average window is 2 (2^1) samples,2: Average window is 4 (2^2) samples,?,?,?,?,?,?,?,?,?,?,?,14: Average window is 16384 (2^14) samples,15: Average window is 32768 (2^15) samples"
rgroup.long 0x44++0x03
line.long 0x00 "I2S_RXLCHAVG,I2S RX Left Channel Data Average"
hexmask.long 0x00 0.--31. 1. "RESULT,RX Left Channel Data Average Result\nThe average result of left channel received data.\n"
rgroup.long 0x48++0x03
line.long 0x00 "I2S_RXRCHAVG,I2S RX Right Channel Data Average"
hexmask.long 0x00 0.--31. 1. "RESULT,RX Right Channel Data Average Result\nThe average result of left channel received data.\nNote: If MONO (I2S_CTL[6]) this register will be useless"
tree.end
tree "PWM"
base ad:0x400E6000
group.long 0x00++0x03
line.long 0x00 "PWM_CLKPSC,PWM Pre-scale Register"
hexmask.long.byte 0x00 24.--31. 1. "DZCNT23,Dead-time Interval Register 1\nThese 8-bit determine Dead-time length.\n"
hexmask.long.byte 0x00 16.--23. 1. "DZCNT01,Dead-time Interval Register 0\nThese 8-bit determine Dead-time length.\n"
newline
hexmask.long.byte 0x00 8.--15. 1. "CLKPSC23,Clock Pre-scale 1 for PWM Counter 2 3\nClock input is divided by (CLKPSC23+1) before it is fed to the counter 2 3.\n"
hexmask.long.byte 0x00 0.--7. 1. "CLKPSC01,Clock Pre-scale 0 for PWM Counter 0 1\nClock input is divided by (CLKPSC01+1) before it is fed to the counter 0 1.\n"
group.long 0x04++0x03
line.long 0x00 "PWM_CLKDIV,PWM Clock Select Register"
bitfld.long 0x00 12.--14. "CLKDIV3,PWM Counter 3 Clock Source Selection\nSelect clock input for timer 3.\n" "0: PWM_CLK/2,1: PWM_CLK/4,2: PWM_CLK/8,3: PWM_CLK/16,4: PWM_CLK/1,?..."
bitfld.long 0x00 8.--10. "CLKDIV2,PWM Counter 2 Clock Source Selection\nSelect clock input for PWM Counter 2.\n(Table is the same as CLKDIV3)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4.--6. "CLKDIV1,PWM Counter 1 Clock Source Selection\nSelect clock input for PWM Counter 1.\n(Table is the same as CLKDIV3)" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "CLKDIV0,PWM Counter 0 Clock Source Selection\nSelect clock input for PWM Counter 0.\n(Table is the same as CLKDIV3)" "0,1,2,3,4,5,6,7"
group.long 0x08++0x03
line.long 0x00 "PWM_CTL,PWM Control Register"
bitfld.long 0x00 27. "CNTMODE3,PWM Counter 3 Auto-reload Mode/One-shot Mode\nNote: If there is a rising transition at this bit it will cause PWM_PERIOD3 and PWM_CMPDAT3 be cleared" "0: One-Shot mode,1: Auto-Reload mode"
bitfld.long 0x00 26. "PINV3,PWM Counter 3 Inverter ON/OFF\n" "0: Inverter OFF,1: Inverter ON"
newline
bitfld.long 0x00 24. "CNTEN3,PWM Counter 3 Enable Control\n" "0: PWM Counter and clock prescaler stops running,1: PWM Counter and clock prescaler starts running"
bitfld.long 0x00 19. "CNTMODE2,PWM Counter 2 Auto-reload Mode/One-shot Mode\nNote: If there is a rising transition at this bit it will cause PWM_PERIOD2 and PWM_CMPDAT2 be cleared" "0: One-shot mode,1: Auto-reload mode"
newline
bitfld.long 0x00 18. "PINV2,PWM Counter 2 Inverter ON/OFF\n" "0: Inverter OFF,1: Inverter ON"
bitfld.long 0x00 16. "CNTEN2,PWM Counter 2 Enable Control\n" "0: PWM Counter and clock prescaler stops running,1: PWM Counter and clock prescaler starts running"
newline
bitfld.long 0x00 11. "CNTMODE1,PWM Counter 1 Auto-reload Mode/One-shot Mode\nNote: If there is a rising transition at this bit it will cause PWM_PERIOD1 and PWM_CMPDAT1 be cleared" "0: One-shot mode,1: Auto-reload mode"
bitfld.long 0x00 10. "PINV1,PWM Counter 1 Inverter ON/OFF\n" "0: Inverter OFF,1: Inverter ON"
newline
bitfld.long 0x00 8. "CNTEN1,PWM Counter 1 Enable Control\n" "0: PWM Counter and clock prescaler stops running,1: PWM Counter and clock prescaler starts running"
bitfld.long 0x00 5. "DTEN23,Dead-time 1 Generator Enable Control\n" "0: Dead-time generator stops running,1: Dead-time generator starts running"
newline
bitfld.long 0x00 4. "DTEN01,Dead-time 0 Generator Enable Control\n" "0: Dead-time generator stops running,1: Dead-time generator starts running"
bitfld.long 0x00 3. "CNTMODE0,PWM Counter 0 Auto-reload Mode/One-shot Mode\n If there is a rising transition at this bit it will cause PWM_PERIOD0 and PWM_CMPDAT0 be cleared" "0: One-shot mode,1: Auto-reload mode"
newline
bitfld.long 0x00 2. "PINV0,PWM Counter 0 Inverter ON/OFF\n" "0: Inverter OFF,1: Inverter ON"
bitfld.long 0x00 0. "CNTEN0,PWM Counter 0 Enable Control\n" "0: PWM Counter and clock prescaler stops running,1: PWM Counter and clock prescaler starts running"
group.long 0x0C++0x03
line.long 0x00 "PWM_PERIOD0,PWM Period Register 0"
hexmask.long.word 0x00 0.--15. 1. "PERIOD,PWM Period Register\nPERIOD determines the PWM period.\nNote: Any write to PERIOD will take effect in the next PWM cycle"
group.long 0x10++0x03
line.long 0x00 "PWM_CMPDAT0,PWM Comparator Register 0"
hexmask.long.word 0x00 0.--15. 1. "CMP,PWM Compare Register\nCMP determines the PWM output duty ratio.\nNote: Any write to CMP will take effect in the next PWM cycle"
rgroup.long 0x14++0x03
line.long 0x00 "PWM_CNT0,PWM Data Register 0"
hexmask.long.word 0x00 0.--15. 1. "CNT,PWM Data Register\nUser can monitor CNT to know current value in 16-bit down counter"
group.long 0x18++0x03
line.long 0x00 "PWM_PERIOD1,PWM Period Register 1"
hexmask.long.word 0x00 0.--15. 1. "PERIOD,PWM Period Register\nPERIOD determines the PWM period.\nNote: Any write to PERIOD will take effect in the next PWM cycle"
group.long 0x1C++0x03
line.long 0x00 "PWM_CMPDAT1,PWM Comparator Register 1"
hexmask.long.word 0x00 0.--15. 1. "CMP,PWM Compare Register\nCMP determines the PWM output duty ratio.\nNote: Any write to CMP will take effect in the next PWM cycle"
group.long 0x20++0x03
line.long 0x00 "PWM_CNT1,PWM Data Register 1"
hexmask.long.word 0x00 0.--15. 1. "CNT,PWM Data Register\nUser can monitor CNT to know current value in 16-bit down counter"
group.long 0x24++0x03
line.long 0x00 "PWM_PERIOD2,PWM Period Register 2"
hexmask.long.word 0x00 0.--15. 1. "PERIOD,PWM Period Register\nPERIOD determines the PWM period.\nNote: Any write to PERIOD will take effect in the next PWM cycle"
group.long 0x28++0x03
line.long 0x00 "PWM_CMPDAT2,PWM Comparator Register 2"
hexmask.long.word 0x00 0.--15. 1. "CMP,PWM Compare Register\nCMP determines the PWM output duty ratio.\nNote: Any write to CMP will take effect in the next PWM cycle"
group.long 0x2C++0x03
line.long 0x00 "PWM_CNT2,PWM Data Register 2"
hexmask.long.word 0x00 0.--15. 1. "CNT,PWM Data Register\nUser can monitor CNT to know current value in 16-bit down counter"
group.long 0x30++0x03
line.long 0x00 "PWM_PERIOD3,PWM Period Register 3"
hexmask.long.word 0x00 0.--15. 1. "PERIOD,PWM Period Register\nPERIOD determines the PWM period.\nNote: Any write to PERIOD will take effect in the next PWM cycle"
group.long 0x34++0x03
line.long 0x00 "PWM_CMPDAT3,PWM Comparator Register 3"
hexmask.long.word 0x00 0.--15. 1. "CMP,PWM Compare Register\nCMP determines the PWM output duty ratio.\nNote: Any write to CMP will take effect in the next PWM cycle"
group.long 0x38++0x03
line.long 0x00 "PWM_CNT3,PWM Data Register 3"
hexmask.long.word 0x00 0.--15. 1. "CNT,PWM Data Register\nUser can monitor CNT to know current value in 16-bit down counter"
group.long 0x40++0x03
line.long 0x00 "PWM_INTEN,PWM Interrupt Enable Register"
bitfld.long 0x00 0.--3. "PIEN,PWM Period Interrupt Enable Control\nNote: Each bit controls the corresponding PWM channel" "0: Period interrupt Disabled,1: Period interrupt Enabled,?..."
group.long 0x44++0x03
line.long 0x00 "PWM_INTSTS,PWM Interrupt Indication Register"
bitfld.long 0x00 0.--3. "PIF,PWM Timer Interrupt Flag\nNote1: Each bit controls the corresponding PWM channel.\nNote2: User can clear each interrupt flag by writing a one to corresponding bit" "0: Interrupt Flag OFF,1: Interrupt Flag ON,?..."
group.long 0x50++0x03
line.long 0x00 "PWM_CAPCTL01,Capture Control Register 0"
bitfld.long 0x00 23. "CFLIF1,Capture Falling Latch Interrupt Flag\nNote: This bit must be cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened and.."
bitfld.long 0x00 22. "CRLIF1,Capture Rising Latch Interrupt Flag\nNote: This bit must be cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened and.."
newline
bitfld.long 0x00 20. "CAPIF1,Capture 1 Interrupt Indication \nNote: If this bit is 1 PWM-counter 1 will not reload when the next capture interrupt occurs" "0: Interrupt Flag OFF,1: Interrupt Flag ON"
bitfld.long 0x00 19. "CAPEN1,Capture Channel 1 Function Enable Control\nNote1: When Enabled Capture latched the PMW-counter 1 and saved to PWM_RCAPDAT1 (Rising latch) and PWM_FCAPDAT1 (Falling latch).\nNote2: When Disabled Capture does not update PWM_RCAPDAT1 and.." "0: Capture function Disabled,1: Capture function Enabled"
newline
bitfld.long 0x00 18. "CFLIEN1,Channel1 Falling Interrupt Enable Control\nNote: When Enabled if Capture detects Channel 1 has falling transition Capture issues an Interrupt" "0: Channel1 Falling Interrupt Disabled,1: Channel1 Falling Interrupt Enabled"
bitfld.long 0x00 17. "CRLIEN1,Channel 1 Rising Interrupt Enable Control\nNote: When Enabled if Capture detects Channel 1 has rising transition Capture issues an Interrupt" "0: Channel 1 Rising Interrupt Disabled,1: Channel 1 Rising Interrupt Enabled"
newline
bitfld.long 0x00 16. "CAPINV1,Capture 1 Inverter Enable Control\n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
bitfld.long 0x00 7. "CFLIF0,Capture Falling Latch Interrupt Flag\nNote: This bit must be cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened and.."
newline
bitfld.long 0x00 6. "CRLIF0,Capture Rising Latch Interrupt Flag\nNote: This bit must be cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened and.."
bitfld.long 0x00 4. "CAPIF0,Capture 0 Interrupt Indication\nNote: If this bit is 1 PWM-counter 0 will not reload when the next capture interrupt occur" "0: Interrupt Flag OFF,1: Interrupt Flag ON"
newline
bitfld.long 0x00 3. "CAPEN0,Capture Channel 0 Function Enable Control\nNote1: When Enabled Capture latched the PWM-counter value and saved to PWM_RCAPDAT0 (Rising latch) and PWM_FCAPDAT0 (Falling latch).\nNote2: When Disabled Capture does not update PWM_RCAPDAT0 and.." "0: Capture function Disabled,1: Capture function Enabled"
bitfld.long 0x00 2. "CFLIEN0,Channel 0 Falling Interrupt Enable Control\nNote: When Enabled if Capture detects Channel 0 has falling transition Capture issues an Interrupt" "0: Channel 0 Falling Interrupt Disabled,1: Channel 0 Falling Interrupt Enabled"
newline
bitfld.long 0x00 1. "CRLIEN0,Channel 0 Rising Interrupt Enable Control\nNote: When Enabled if Capture detects Channel 0 has rising transition Capture issues an Interrupt" "0: Channel 0 Rising Interrupt Enable Disabled,1: Channel 0 Rising Interrupt Enable Enabled"
bitfld.long 0x00 0. "CAPINV0,Capture 0 Inverter Enable Control\n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
group.long 0x54++0x03
line.long 0x00 "PWM_CAPCTL23,Capture Control Register 1"
bitfld.long 0x00 23. "CFLIF3,Capture Falling Latch Interrupt Flag\nNote: This bit must be cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
bitfld.long 0x00 22. "CRLIF3,Capture Rising Latch Interrupt Flag\nNote: This bit must be cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
newline
bitfld.long 0x00 20. "CAPIF3,Capture 3 Interrupt Indication\nNote: If this bit is 1 PWM-counter 3 will not reload when next capture interrupt occur" "0: Interrupt Flag OFF,1: Interrupt Flag ON"
bitfld.long 0x00 19. "CAPEN3,Capture Channel 3 Function Enable Control\nNote: When Enabled Capture latched the PMW-counter and saved to PWM_RCAPDAT3 (Rising latch) and PWM_FCAPDAT3 (Falling latch)" "0: Capture function Disabled,1: Capture function Enabled"
newline
bitfld.long 0x00 18. "CFLIEN3,Channel 3 Falling Interrupt Enable Control\nNote: When Enabled if Capture detects Channel 3 has falling transition Capture issues an Interrupt" "0: Channel 3 Falling Interrupt Disabled,1: Channel 3 Falling Interrupt Enabled"
bitfld.long 0x00 17. "CRLIEN3,Channel 3 Rising Interrupt Enable Control\nNote: When Enabled if Capture detects Channel 3 has rising transition Capture issues an Interrupt" "0: Channel 3 Rising Interrupt Disabled,1: Channel 3 Rising Interrupt Enabled"
newline
bitfld.long 0x00 16. "CAPINV3,Capture 3 Inverter Enable Control\n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
bitfld.long 0x00 7. "CFLIF2,Capture Falling Latch Interrupt Flag\nNote: This bit must be cleared by writing 1 to it" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
newline
bitfld.long 0x00 6. "CRLIF2,Capture Rising Latch Interrupt Flag\nNote: This bit must be cleared by writing 1 to it" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
bitfld.long 0x00 4. "CAPIF2,Capture 2 Interrupt Indication\nNote: If this bit is 1 PWM-counter 2 will not reload when next capture interrupt occur" "0: Interrupt Flag OFF,1: Interrupt Flag ON"
newline
bitfld.long 0x00 3. "CAPEN2,Capture Channel 2 Function Enable Control\nNote: When Enabled Capture latched the PMW-counter value and saved to PWM_RCAPDAT2 (Rising latch) and PWM_FCAPDAT2 (Falling latch)" "0: Capture function Disabled,1: Capture function Enabled"
bitfld.long 0x00 2. "CFLIEN2,Channel 2 Falling Interrupt Enable Control\nNote: When Enabled if Capture detects Channel 2 has falling transition Capture issues an Interrupt" "0: Channel 2 Falling Interrupt Disabled,1: Channel 2 Falling Interrupt Enabled"
newline
bitfld.long 0x00 1. "CRLIEN2,Channel 2 Rising Interrupt Enable Control\nNote: When Enabled if Capture detects Channel 2 has rising transition Capture issues an Interrupt" "0: Channel 2 Rising Interrupt Disabled,1: Channel 2 Rising Interrupt Enabled"
bitfld.long 0x00 0. "CAPINV2,Capture 2 Inverter Enable Control\n" "0: Capture source inverter Disabled,1: Capture source inverter Enabled"
group.long 0x58++0x03
line.long 0x00 "PWM_RCAPDAT0,Capture Rising Latch Register (Channel 0)"
hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition"
group.long 0x5C++0x03
line.long 0x00 "PWM_FCAPDAT0,Capture Falling Latch Register (Channel 0)"
hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,Capture Falling Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has Falling transition"
group.long 0x60++0x03
line.long 0x00 "PWM_RCAPDAT1,Capture Rising Latch Register (Channel 1)"
hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition"
group.long 0x64++0x03
line.long 0x00 "PWM_FCAPDAT1,Capture Falling Latch Register (Channel 1)"
hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,Capture Falling Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has Falling transition"
group.long 0x68++0x03
line.long 0x00 "PWM_RCAPDAT2,Capture Rising Latch Register (Channel 2)"
hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition"
group.long 0x6C++0x03
line.long 0x00 "PWM_FCAPDAT2,Capture Falling Latch Register (Channel 2)"
hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,Capture Falling Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has Falling transition"
group.long 0x70++0x03
line.long 0x00 "PWM_RCAPDAT3,Capture Rising Latch Register (Channel 3)"
hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition"
group.long 0x74++0x03
line.long 0x00 "PWM_FCAPDAT3,Capture Falling Latch Register (Channel 3)"
hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,Capture Falling Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has Falling transition"
group.long 0x78++0x03
line.long 0x00 "PWM_CAPINEN,Capture Input Enable Register"
bitfld.long 0x00 0. "CAPINEN,Capture Input Enable Control\n" "0: PWM Channel capture input path Disabled,1: PWM Channel capture input path Enabled"
group.long 0x7C++0x03
line.long 0x00 "PWM_POEN,PWM Output Enable Register"
bitfld.long 0x00 0.--3. "POEN,PWM Counter Output Enable Control\nNote: Each bit controls the corresponding PWM channel" "0: PWM Counter Output Disabled,1: PWM Counter Output Enabled,?..."
tree.end
tree "RTC"
base ad:0x400E7000
group.long 0x00++0x03
line.long 0x00 "RTC_INIT,RTC Initiation Register"
abitfld.long 0x00 1.--31. "INIT_STS,RTC Initiation (While Writing)\nWhen RTC block is powered on RTC is at reset state" "0x00000000=0: pressed and,0x00000001=1: released \n[3]"
rbitfld.long 0x00 0. "ACTIVE,RTC Active Status (Read Only)\n" "0: RTC is at reset state,1: RTC is at normal active state"
group.long 0x04++0x03
line.long 0x00 "RTC_RWEN,RTC Access Enable Register"
rbitfld.long 0x00 16. "RWENF,RTC Register Access Enable Flag (Read Only)\nNote: This bit will be set after RTC_RWEN[15:0] register is load a 0xA965 and it will be cleared when RTC_RWEN[15:0] is not 0xA965" "0: RTC register access Disabled,1: RTC register access Enabled"
hexmask.long.word 0x00 0.--15. 1. "RWEN,RTC Register Access Enable Password (R/W)\n"
group.long 0x08++0x03
line.long 0x00 "RTC_FREQADJ,RTC Frequency Compensation Register"
bitfld.long 0x00 31. "ADJTRG,RTC Clock Calibration Control\nThis bit will be kept at High while the calibration is ongoing and cleared to Low automatically while the calibration is done and the content of RTC_CALCNT register is valid calibration flow as follows.\n" "0: RTC Clock calibration mechanism Disabled,1: RTC Clock calibration mechanism Enabled"
bitfld.long 0x00 24.--27. "PKEYTIME,Minimum Duration That Power Key Must Be Pressed to Turn on Core Power\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x00 8.--23. 1. "INTEGER,Integer Part\n"
bitfld.long 0x00 0.--5. "FRACTION,Fraction Part\nDigit in RTC_FREQADJ must be expressed as hexadecimal number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x0C++0x03
line.long 0x00 "RTC_TIME,RTC Time Loading Register"
bitfld.long 0x00 20.--21. "TENHR,10-Hour Time Digit" "0,1,2,3"
bitfld.long 0x00 16.--19. "HR,1-Hour Time Digit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 12.--14. "TENMIN,10-Min Time Digit" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--11. "MIN,1-Min Time Digit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--6. "TENSEC,10-Sec Time Digit" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--3. "SEC,1-Sec Time Digit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x10++0x03
line.long 0x00 "RTC_CAL,RTC Calendar Loading Register"
bitfld.long 0x00 20.--23. "TENYEAR,10-Year Calendar Digit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "YEAR,1-Year Calendar Digit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 12. "TENMON,10-Month Calendar Digit" "0,1"
bitfld.long 0x00 8.--11. "MON,1-Month Calendar Digit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--5. "TENDAY,10-Day Calendar Digit" "0,1,2,3"
bitfld.long 0x00 0.--3. "DAY,1-Day Calendar Digit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x14++0x03
line.long 0x00 "RTC_CLKFMT,RTC Time Scale Selection Register"
bitfld.long 0x00 0. "_24HEN,24-hour / 12-hour Mode Selection\nIndicate that RTC_TIME and RTC_TALM are in 24-hour mode or 12-hour mode.\n" "0: 12-hour time scale with AM and PM indication..,1: 24-hour time scale selected"
group.long 0x18++0x03
line.long 0x00 "RTC_WEEKDAY,RTC Day of the Week Register"
bitfld.long 0x00 0.--2. "WEEKDAY,Day of the Week Register \n" "0: Sunday,1: Monday,2: Tuesday,3: Wednesday,4: Thursday,5: Friday,6: Saturday,?..."
group.long 0x1C++0x03
line.long 0x00 "RTC_TALM,RTC Time Alarm Register"
bitfld.long 0x00 23. "MSKHR,Mask Alarm by Hour\n" "0: Activate,1: Mask"
bitfld.long 0x00 20.--21. "TENHR,10-hour Time Digit of Alarm Setting (0-2)\nWhen RTC runs as 12-hour time scale mode RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication" "0,1,2,3"
newline
bitfld.long 0x00 16.--19. "HR,1-Hour Time Digit of Alarm Setting (0-9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 15. "MSKMIN,Mask Alarm by Minute\n" "0: Activate,1: Mask"
newline
bitfld.long 0x00 12.--14. "TENMIN,10-Min Time Digit of Alarm Setting (0-5)" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--11. "MIN,1-Min Time Digit of Alarm Setting (0-9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 7. "MSKSEC,Mask Alarm by Second\n" "0: Activate,1: Mask"
bitfld.long 0x00 4.--6. "TENSEC,10-Sec Time Digit of Alarm Setting (0-5)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--3. "SEC,1-Sec Time Digit of Alarm Setting (0-9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x20++0x03
line.long 0x00 "RTC_CALM,RTC Calendar Alarm Register"
bitfld.long 0x00 31. "MSKWEEKDAY,Mask Alarm by Week Day\n" "0: Activate,1: Mask"
bitfld.long 0x00 28.--30. "WEEKDAY,Week Day Alarm Digit" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 24. "MSKYEAR,Mask Alarm by Year\n" "0: Activate,1: Mask"
bitfld.long 0x00 20.--23. "TENYEAR,10-Year Calendar Digit of Alarm Setting (0-9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "YEAR,1-Year Calendar Digit of Alarm Setting (0-9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 15. "MSKMON,Mask Alarm by Month\n" "0: Activate,1: Mask"
newline
bitfld.long 0x00 12. "TENMON,10-Month Calendar Digit of Alarm Setting (0-1)" "0,1"
bitfld.long 0x00 8.--11. "MON,1-Month Calendar Digit of Alarm Setting (0-9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 7. "MSKDAY,Mask Alarm by Day\n" "0: Activate,1: Mask"
bitfld.long 0x00 4.--5. "TENDAY,10-Day Calendar Digit of Alarm Setting (0-3)" "0,1,2,3"
newline
bitfld.long 0x00 0.--3. "DAY,1-Day Calendar Digit of Alarm Setting (0-9)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x24++0x03
line.long 0x00 "RTC_LEAPYEAR,RTC Leap Year Indication Register"
bitfld.long 0x00 0. "LEAPYEAR,Leap Year Indication Register (Read Only)\n" "0: This year is not a leap year,1: This year is leap year"
group.long 0x28++0x03
line.long 0x00 "RTC_INTEN,RTC Interrupt Enable Register"
bitfld.long 0x00 3. "RALMIEN,Relative Alarm Interrupt Enable Control\n" "0: RTC Relative Alarm Interrupt Disabled,1: RTC Relative Alarm Interrupt Enabled"
bitfld.long 0x00 2. "PKEYIEN,Power Switch Interrupt Enable Control\n" "0: Power Switch Be Pressed Interrupt Disabled,1: Power Switch Be Pressed Interrupt Enabled"
newline
bitfld.long 0x00 1. "TICKIEN,Time Tick Interrupt Enable Control\n" "0: RTC Time Tick Interrupt and counter Disabled,1: RTC Time Tick Interrupt and counter Enabled"
bitfld.long 0x00 0. "ALMIEN,Alarm Interrupt Enable Control\n" "0: RTC Alarm Interrupt Disabled,1: RTC Alarm Interrupt Enabled"
group.long 0x2C++0x03
line.long 0x00 "RTC_INTSTS,RTC Interrupt Indication Register"
bitfld.long 0x00 3. "RELALMIF,RTC Relative Alarm Interrupt Indication\nNote: Software can also clear this bit after RTC interrupt has occurred" "0: Relative alarm interrupt never occurred,1: Relative time counter and calendar counter.."
bitfld.long 0x00 2. "POWKEYIF,Power Switch Interrupt Flag\nWhen RTC detect power key (RTC_nRWAKE) is pressed the POWKEYIF (RTC_INTSYS[2]) is set to 1\nNote: Software can also clear this bit after RTC interrupt has occurred" "0: The power switch interrupt never occurred,1: The power switch has been activated"
newline
bitfld.long 0x00 1. "TICKIF,RTC Time Tick Interrupt Flag\nWhen RTC time tick happened this bit will be set to 1 and an interrupt will be generated if RTC Tick Interrupt enabled TICKIEN (RTC_INTEN[1]) is set to 1" "0: Tick condition does not occur,1: Tick condition occur"
bitfld.long 0x00 0. "ALMIF,RTC Alarm Interrupt Flag\nWhen RTC time counters RTC_TIME and RTC_CAL match the alarm setting time registers RTC_TALM and RTC_CALM this bit will be set to 1 and an interrupt will be generated if RTC Alarm Interrupt enabled ALMIEN (RTC_INTEN[0]) is.." "0: Alarm condition is not matched,1: Alarm condition is matched"
group.long 0x30++0x03
line.long 0x00 "RTC_TICK,RTC Time Tick Register"
bitfld.long 0x00 0.--2. "TICKSEL,Time Tick Register\nThese bits are used to select RTC time tick period for Periodic Time Tick Interrupt request" "0: Time tick is 1 second,1: Time tick is 1/2 second,2: Time tick is 1/4 second,3: Time tick is 1/8 second,4: Time tick is 1/16 second,5: Time tick is 1/32 second,6: Time tick is 1/64 second,7: Time tick is 1/28 second"
group.long 0x34++0x03
line.long 0x00 "RTC_POWCTL,RTC Power Time-out Register"
hexmask.long.word 0x00 20.--31. 1. "RALMTIME,Relative Time Alarm Period (Second Unit)\nIndicates the period of the relative time alarm"
bitfld.long 0x00 16.--19. "POWOFFT,Power Clear Period\nIndicates that the period of the power core will be cleared after the power key is pressed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 7. "POWKEY,Power Key Status\n" "0: The power key is pressed to low,1: The power key status is high"
bitfld.long 0x00 5. "EDGE_TRIG,Power Key Trigger Mode \n" "0: LEVEL TRIGGER RTC is powered on while power..,1: EDGE TRIGE RTC is powered on while power key.."
newline
bitfld.long 0x00 4. "RALMIEN,Relative Time Alarm\n" "0: The relative time alarm control Disabled,1: The relative time alarm control Enabled"
bitfld.long 0x00 3. "ALMIEN,Normal Time Alarm\n" "0: Normal time alarm control Disabled,1: Normal time alarm control Enabled"
newline
bitfld.long 0x00 2. "POWOFFEN,Hardware Power Clear Enable Control\n" "0: The RTC_RPWR pin will not be influenced by..,1: The RTC_RPWR pin will be cleared to low when.."
bitfld.long 0x00 1. "SWPOWOFF,Software Core Power Disable Control\nIf the power key is pressed the RTC_RPWR pin can be cleared by setting this bit and this can be cleared to 0 when the pressed power key RTC_RPWR is released" "?,1: Force the RTC_RPWR to low"
newline
bitfld.long 0x00 0. "POWEN,Power ON\nRTC_RPWR will change to high state when POWEN value change from 0 to 1.\nNote: The following conditions will make RTC_RPWR low:\nSet POWEN bit to 0\nPOWOFFEN is set to 1 and the power key is pressed over the period of POWOFFT.\nThis bit.." "0,1"
group.long 0x38++0x03
line.long 0x00 "RTC_SET,RTC Setting Register"
rbitfld.long 0x00 4. "XOUTDAT,X32_OUT PAD Status\n" "0,1"
rbitfld.long 0x00 3. "XININDAT,X32_IN PAD Status\n" "0,1"
newline
bitfld.long 0x00 2. "IOMSEL,X32_IN and X32_OUT PAD Digital Input Mode Control\n" "0: Digital input mode,1: Crystal mode (default value)"
bitfld.long 0x00 1. "CBEN,32768 Hz (LXT) Crystal Control\n" "0: Crystal Disabled,1: Crystal Enabled"
group.long 0x3C++0x03
line.long 0x00 "RTC_CLKSRC,RC Oscillator Setting Register"
bitfld.long 0x00 0. "CKSRC,Internal RC Oscillator Control\n" "0: Internal RC oscillator Disabled,1: Internal RC oscillator Enabled"
rgroup.long 0x40++0x03
line.long 0x00 "RTC_CALCNT,RC Oscillator Calibration Register"
hexmask.long 0x00 0.--31. 1. "CALCNT,Cycle Number of PCLK During 1Hz\nThat is generated by dividing RTC Clock"
rgroup.long 0x44++0x03
line.long 0x00 "RTC_SYNC,RTC Register Write Complete"
bitfld.long 0x00 0. "SYNC,Polling the Flag to Detect RTC Register Write Complete\n" "0: Register cannot be written,1: Register can be written because write complete"
repeat 8. (strings "0" "1" "2" "3" "4" "5" "6" "7" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C )
group.long ($2+0x54)++0x03
line.long 0x00 "RTC_SPR$1,RTC Spare Register $1"
hexmask.long 0x00 0.--31. 1. "RTC_SPRn,RTC Spare Register\n"
repeat.end
tree.end
tree "SCS"
repeat 8. (list 0. 1. 2. 3. 4. 5. 6. 7.) (list ad:0xE000E400 ad:0xE000E404 ad:0xE000E408 ad:0xE000E40C ad:0xE000E410 ad:0xE000E414 ad:0xE000E418 ad:0xE000E41C)
tree "NVIC_IPR$1"
base $2
group.long 0x00++0x03
line.long 0x00 "NVIC_IPRN,IRQ0 ~ IRQ31 Interrupt Priority Control Register"
bitfld.long 0x00 28.--31. "PRI_4n_3,Priority of IRQ_4n+3\n 0 denotes the highest priority and 15 denotes the lowest priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 20.--23. "PRI_4n_2,Priority of IRQ_4n+2\n 0 denotes the highest priority and 15 denotes the lowest priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 12.--15. "PRI_4n_1,Priority of IRQ_4n+1\n 0 denotes the highest priority and 15 denotes the lowest priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "PRI_4n_0,Priority of IRQ_4n+0\n 0 denotes the highest priority and 15 denotes the lowest priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree.end
repeat.end
tree "SCS"
base ad:0xE000E000
group.long 0x10++0x03
line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
bitfld.long 0x00 16. "COUNTFLAG,Returns 1 If Timer Counted to 0 Since Last Time this Register Was Read\nCOUNTFLAG is set by a count transition from 1 to 0.\nCOUNTFLAG is cleared on read or by a write to the Current Value register" "0,1"
bitfld.long 0x00 2. "CLKSRC,SysTick Counting Clock Source Select\n" "0: Clock source is (optional) external reference..,1: Core clock used for SysTick"
newline
bitfld.long 0x00 1. "TICKINT,SysTick Interrupt Enable Control\n" "0: Counting down to 0 does not cause the SysTick..,1: Counting down to 0 will cause the SysTick.."
bitfld.long 0x00 0. "ENABLE,SysTick Function Enable Control\n" "0: Counter Disabled,1: Counter will operate in a multi-shot manner"
group.long 0x14++0x03
line.long 0x00 "SYST_RVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x00 0.--23. 1. "RELOAD,SysTick Reload Value\nThe value to load into the Current Value register when the counter reaches 0"
group.long 0x18++0x03
line.long 0x00 "SYST_CVR,SysTick Current Value Register"
hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT,Current Counter Value\nThis is the value of the counter at the time it is sampled.The counter does not provide read-modify-write protection.The register is write-clear.A software write of any value will clear the register to 0.Unsupported bits.."
group.long 0x100++0x03
line.long 0x00 "NVIC_ISER0,IRQ0 ~ IRQ31 Set-enable Control Register"
hexmask.long 0x00 0.--31. 1. "SETENA,Interrupt Set Enable Control\nThe NVIC_ISER0 registers enable interrupts and show which interrupts are enabled\nWrite Operation:\n"
group.long 0x180++0x03
line.long 0x00 "NVIC_ICER0,IRQ0 ~ IRQ31 Clear-enable Control Register"
hexmask.long 0x00 0.--31. 1. "CLRENA,Interrupt Clear Enable Control\nThe NVIC_ICER0 registers disable interrupts and show which interrupts are enabled.\nWrite Operation:\n"
group.long 0x200++0x03
line.long 0x00 "NVIC_ISPR0,IRQ0 ~ IRQ31 Set-pending Control Register"
hexmask.long 0x00 0.--31. 1. "SETPEND,Interrupt Set-pending \nThe NVIC_ISPR0 registers force interrupts into the pending state and show which interrupts are pending\nWrite Operation:\n"
group.long 0x280++0x03
line.long 0x00 "NVIC_ICPR0,IRQ0 ~ IRQ31 Clear-pending Control Register"
hexmask.long 0x00 0.--31. 1. "CLRPEND,Interrupt Clear-pending\nThe NVIC_ICPR0 registers remove the pending state from interrupts and show which interrupts are pending\nWrite Operation:\n"
group.long 0x300++0x03
line.long 0x00 "NVIC_IABR0,IRQ0 ~ IRQ31 Active Bit Register"
hexmask.long 0x00 0.--31. 1. "ACTIVE,Interrupt Active Flags\nThe NVIC_IABR0 registers indicate which interrupts are active"
group.long 0xD04++0x03
line.long 0x00 "ICSR,Interrupt Control and State Register"
bitfld.long 0x00 31. "NMIPENDSET,NMI Set-pending Bit\nWrite Operation:\nNote: Because NMI is the highest-priority exception normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit" "0: No effect.\nNMI exception is not pending,1: Changes NMI exception state to pending.\nNMI.."
bitfld.long 0x00 28. "PENDSVSET,PendSV Set-pending Bit\nWrite Operation:\nNote: Writing 1 to this bit is the only way to set the PendSV exception state to pending" "0: No effect.\nPendSV exception is not pending,1: Changes PendSV exception state to.."
newline
bitfld.long 0x00 27. "PENDSVCLR,PendSV Clear-pending Bit\nWrite Operation:\nNote: This is a write only bit" "0: No effect,1: Removes the pending state from the PendSV.."
bitfld.long 0x00 26. "PENDSTSET,SysTick Exception Set-pending Bit\nWrite Operation:\n" "0: No effect.\nSysTick exception is not pending,1: Change SysTick exception state to.."
newline
bitfld.long 0x00 25. "PENDSTCLR,SysTick Exception Clear-pending Bit\nWrite Operation:\nNote: This is a write only bit" "0: No effect,1: Removes the pending state from the SysTick.."
rbitfld.long 0x00 23. "ISRPREEMPT,Interrupt Preempt Bit (Read Only)\nIf set a pending exception will be serviced on exit from the debug halt state" "0,1"
newline
rbitfld.long 0x00 22. "ISRPENDING,Interrupt Pending Flag Excluding NMI and Faults (Read Only)\n" "0: Interrupt not pending,1: Interrupt pending"
bitfld.long 0x00 12.--17. "VECTPENDING,Number of the Highest Pended Exception\nIndicates the exception number of the highest priority pending enabled exception.\nNote: The value indicated by this field includes the effect of the BASEPRI and FAULTMASK registers but does not.." "0: No pending exceptions,?..."
newline
bitfld.long 0x00 11. "RETTOBASE,Preempted Active Exceptions Indicator\nIndicate whether there are preempted active exceptions.\n" "0: There are preempted active exceptions to..,1: There are no active exceptions or the.."
bitfld.long 0x00 0.--5. "VECTACTIVE,Number of the Current Active Exception \n" "0: Thread mode,?..."
group.long 0xD0C++0x03
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x00 16.--31. 1. "VECTORKEY,Register Access Key\nWhen writing this register this field should be 0x05FA otherwise the write action will be unpredictable.\nThe VECTORKEY filed is used to prevent accidental write to this register from resetting the system or clearing of.."
bitfld.long 0x00 15. "ENDIANNESS,Data Endianness\n" "0: Little-endian,1: Big-endian"
newline
bitfld.long 0x00 8.--10. "PRIGROUP,Interrupt Priority Grouping\nThis field determines the Split of Group priority from subpriority" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 2. "SYSRESETREQ,System Reset Request\nWriting this bit to 1 will cause a reset signal to be asserted to the chip and indicate a reset is requested\nNote: This bit is write only and self-cleared as part of the reset sequence" "0,1"
newline
bitfld.long 0x00 1. "VECTCLRACTIVE,Exception Active Status Clear Bit\nSetting this bit to 1 will clear all active state information for fixed and configurable exceptions\nNote1: This bit is write only and can only be written when the core is halted.\nNote2: It is the.." "0,1"
group.long 0xD10++0x03
line.long 0x00 "SCR,System Control Register"
bitfld.long 0x00 4. "SEVONPEND,Send Event on Pending\nWhen an event or interrupt enters pending state the event signal wakes up the processor from WFE" "0: Only enabled interrupts or events can wake up..,1: Enabled events and all interrupts including.."
bitfld.long 0x00 2. "SLEEPDEEP,Processor Deep Sleep and Sleep Mode Selection\nControl whether the processor uses Idle mode or Power-down mode as its low power operation.\n" "0: Idle mode,1: Power-down mode"
newline
bitfld.long 0x00 1. "SLEEPONEXIT,Sleep-on-exit Enable Control\nThis bit indicates Sleep-On-Exit when returning from handler mode to thread mode.\nSetting this bit to 1 will enable an interrupt driven application to avoid returning to an empty main application" "0: Do not enter idle mode when returning to..,1: Enter Idle mode or Power-down mode on return.."
group.long 0xD18++0x03
line.long 0x00 "SHPR1,System Handler Priority Register 1"
hexmask.long.byte 0x00 16.--23. 1. "PRI_6,Priority of System Handler"
hexmask.long.byte 0x00 8.--15. 1. "PRI_5,Priority of System Handler"
newline
hexmask.long.byte 0x00 0.--7. 1. "PRI_4,Priority of System Handler"
group.long 0xD1C++0x03
line.long 0x00 "SHPR2,System Handler Priority Register 2"
bitfld.long 0x00 30.--31. "PRI_11,Priority of System Handler" "0,1,2,3"
group.long 0xD20++0x03
line.long 0x00 "SHPR3,System Handler Priority Register 3"
bitfld.long 0x00 30.--31. "PRI_15,Priority of System Handler" "0,1,2,3"
bitfld.long 0x00 22.--23. "PRI_14,Priority of System Handler" "0,1,2,3"
wgroup.long 0xF00++0x03
line.long 0x00 "NVIC_STIR,Software Trigger Interrupt Registers"
hexmask.long.word 0x00 0.--8. 1. "INTID,Write to the STIR to Generate an Interrupt From Software\nWhen the USERSETMPEND bit in the SCR is set to 1 unprivileged software can access the STIR\nInterrupt ID of the interrupt to trigger in the range 0-47"
tree.end
tree.end
tree "SDH"
base ad:0x4000A000
group.long 0x00++0x03
line.long 0x00 "SDH_FB_N,SDH Receiving/Transmit Flash Buffer"
hexmask.long 0x00 0.--31. 1. "DATA,SDH Receiving/Transmit Flash Buffer\nThis buffer is used to receive/transmit data"
group.long 0x400++0x03
line.long 0x00 "SDH_DMACTL,DMAC Control and Status Register"
bitfld.long 0x00 9. "DMABUSY,DMA Transfer in Progress\nThis bit indicates that the DMA is transferred or not.\n" "0: DMA transfer is not in progress,1: DMA transfer is in progress"
bitfld.long 0x00 3. "SGEN,Scatter-gather Function Enable Control\n" "0: Scatter-gather function Disabled (DMAC will..,1: Scatter-gather function Enabled (DMAC will.."
newline
bitfld.long 0x00 1. "DMARST,Software Engine Reset\nNote: Software resets DMA region" "0: No effect,1: Reset internal state machine and pointers"
bitfld.long 0x00 0. "DMAEN,DMAC Engine Enable Control\nNote1: If this bit is cleared DMAC will ignore all DMA request and force Bus Master into IDLE state.\nNote2: If a target abort occurs DMAEN will be cleared" "0: DMAC Disabled,1: DMAC Enabled"
group.long 0x408++0x03
line.long 0x00 "SDH_DMASA,DMAC Transfer Starting Address Register"
hexmask.long 0x00 1.--31. 1. "DMASA,DMA Transfer Starting Address \nThis field pads 0 as least significant bit indicates a 32-bit starting address of system memory (SRAM) for DMAC to retrieve or fill in data.\nIf DMAC is not in Normal mode this field will be interpreted as a.."
bitfld.long 0x00 0. "ORDER,Determined to the PAD Table Fetching in Order or Out of Order\n" "0: PAD table is fetched in order,1: PAD table is fetched out of order"
rgroup.long 0x40C++0x03
line.long 0x00 "SDH_DMABCNT,DMAC Transfer Byte Count Register"
hexmask.long 0x00 0.--25. 1. "BCNT,DMA Transfer Byte Count (Read Only)\nThis field indicates the remained byte count of DMAC transfer"
group.long 0x410++0x03
line.long 0x00 "SDH_DMAINTEN,DMAC Interrupt Enable Control Register"
bitfld.long 0x00 1. "WEOTIEN,Wrong EOT Encountered Interrupt Enable Control\n" "0: Interrupt generation Disabled when wrong EOT..,1: Interrupt generation Enabled when wrong EOT.."
bitfld.long 0x00 0. "ABORTIEN,DMA Read/Write Target Abort Interrupt Enable Control\n" "0: Target abort interrupt generation Disabled..,1: Target abort interrupt generation Enabled.."
group.long 0x414++0x03
line.long 0x00 "SDH_DMAINTSTS,DMAC Interrupt Status Register"
bitfld.long 0x00 1. "WEOTIF,Wrong EOT Encountered Interrupt Flag\nWhen DMA Scatter-Gather function is enabled and EOT of the descriptor is encountered before DMA transfer finished (that means the total sector count of all PAD is less than the sector count of DMAC) this bit.." "0: No EOT encountered before DMA transfer finished,1: EOT encountered before DMA transfer finished"
bitfld.long 0x00 0. "ABORTIF,DMA Read/Write Target Abort Interrupt Flag\nNote: This bit is read only but can be cleared by writing '1' to it" "0: No bus ERROR response received,1: Bus ERROR response received"
group.long 0x800++0x03
line.long 0x00 "SDH_GCTL,Global Control and Status Register"
bitfld.long 0x00 1. "SDEN,Secure-digital Functionality Enable Control\n" "0: SD functionality Disabled,1: SD functionality Enabled"
bitfld.long 0x00 0. "GCTLRST,Software Engine Reset\n" "0: No effect,1: Reset all SDH engines"
group.long 0x804++0x03
line.long 0x00 "SDH_GINTEN,Global Interrupt Control Register"
bitfld.long 0x00 0. "DTAIEN,DMAC READ/WRITE Target Abort Interrupt Enable Control\n" "0: DMAC READ/WRITE target abort interrupt..,1: DMAC READ/WRITE target abort interrupt.."
group.long 0x808++0x03
line.long 0x00 "SDH_GINTSTS,Global Interrupt Status Register"
rbitfld.long 0x00 0. "DTAIF,DMAC READ/WRITE Target Abort Interrupt Flag (Read Only)\nThis bit indicates DMAC received an ERROR response from internal AHB bus during DMA read/write operation" "0: No bus ERROR response received,1: Bus ERROR response received"
group.long 0x820++0x03
line.long 0x00 "SDH_CTL,SD Control and Status Register"
bitfld.long 0x00 24.--27. "SDNWR,NWR Parameter for Block Write Operation\nThis value indicates the NWR parameter for data block write operation in SD clock counts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 16.--23. 1. "BLKCNT,Block Counts to Be Transferred or Received\nThis field contains the block counts for data-in and data-out transfer"
newline
bitfld.long 0x00 15. "DBW,SD Data Bus Width (for 1-bit / 4-bit Selection)\n" "0: Data bus width is 1-bit,1: Data bus width is 4-bit"
bitfld.long 0x00 14. "CTLRST,Software Engine Reset\n" "0: No effect,1: Reset the internal state machine and counters"
newline
bitfld.long 0x00 8.--13. "CMDCODE,SD Command Code\nThis register contains the SD command code (0x00 - 0x3F)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 7. "CLKKEEP0,SD Clock Enable Control for Port 0\n" "0: SD host decides when to output clock and when..,1: SD clock always keeps free running"
newline
bitfld.long 0x00 6. "CLK8OEN,Generating 8 Clock Cycles Output Enable Control\nNote: When operation is finished this bit will be cleared automatically" "0: No effect,1: Enabled and SD host will output 8 clock cycles"
bitfld.long 0x00 5. "CLK74OEN,Generating 74 Clock Cycles Output Enable Control\nNote: When operation is finished this bit will be cleared automatically" "0: No effect,1: Enabled SD host will output 74 clock cycles.."
newline
bitfld.long 0x00 4. "R2EN,Response R2 Input Enable Control\nNote: When operation is finished this bit will be cleared automatically" "0: No effect,1: Enabled SD host will wait to receive a.."
bitfld.long 0x00 3. "DOEN,Data Output Enable Control\nNote: When operation is finished this bit will be cleared automatically" "0: No effect,1: Enabled SD host will transfer block data and.."
newline
bitfld.long 0x00 2. "DIEN,Data Input Enable Control\nNote: When operation is finished this bit will be cleared automatically" "0: No effect,1: Enabled SD host will wait to receive block.."
bitfld.long 0x00 1. "RIEN,Response Input Enable Control\nNote: When operation is finished this bit will be cleared automatically" "0: No effect,1: Enabled SD host will wait to receive a.."
newline
bitfld.long 0x00 0. "COEN,Command Output Enable Control\nNote: When operation is finished this bit will be cleared automatically" "0: No effect,1: Enabled SD host will output a command to SD.."
group.long 0x824++0x03
line.long 0x00 "SDH_CMDARG,SD Command Argument Register"
hexmask.long 0x00 0.--31. 1. "ARGUMENT,SD Command Argument\nThis register contains a 32-bit value specifies the argument of SD command from host controller to SD card"
group.long 0x828++0x03
line.long 0x00 "SDH_INTEN,SD Interrupt Control Register"
bitfld.long 0x00 30. "CDSRC0,SD0 Card Detect Source Selection\n" "0: From SD0 card's DAT3 pin,1: From GPIO pin"
bitfld.long 0x00 13. "DITOIEN,Data Input Time-out Interrupt Enable Control\nEnable/Disable interrupt generation of SD controller when data input time-out" "0: Data Input Time-out Interrupt Disabled,1: Data Input Time-out Interrupt Enabled"
newline
bitfld.long 0x00 12. "RTOIEN,Response Time-out Interrupt Enable Control\nEnable/Disable interrupt generation of SD controller when receiving response or R2 time-out" "0: Response Time-out Interrupt Disabled,1: Response Time-out Interrupt Enabled"
bitfld.long 0x00 10. "SDHIEN0,SDH Interrupt Enable Control for Port 0\nEnable/Disable interrupt generation of SD host when SDH card 0 issues an interrupt via DAT [1] to host.\n" "0: SDH Port 0 Interrupt Disabled,1: SDH Port 0 Interrupt Enabled"
newline
bitfld.long 0x00 8. "CDIEN0,SD0 Card Detection Interrupt Enable Control\nEnable/Disable interrupt generation of SD controller when card 0 is inserted or removed.\n" "0: SD0 Card Detection Interrupt Disabled,1: SD0 Card Detection Interrupt Enabled"
bitfld.long 0x00 1. "CRCIEN,CRC7 CRC16 and CRC Status Error Interrupt Enable Control\n" "0: SD host will not generate interrupt when CRC7..,1: SD host will generate interrupt when CRC7.."
newline
bitfld.long 0x00 0. "BLKDIEN,Block Transfer Done Interrupt Enable Control\n" "0: SD host will not generate interrupt when..,1: SD host will generate interrupt when data-in.."
group.long 0x82C++0x03
line.long 0x00 "SDH_INTSTS,SD Interrupt Status Register"
rbitfld.long 0x00 18. "DAT1STS,DAT1 Pin Status of SD Port (Read Only)\nThis bit indicates the DAT1 pin status of SD port" "0,1"
rbitfld.long 0x00 16. "CDSTS0,Card Detect Status of SD0 (Read Only)\nThis bit indicates the card detect pin status of SD0 and is used for card detection" "0: Card removed.\nCard inserted,1: Card inserted.\nCard removed"
newline
rbitfld.long 0x00 13. "DITOIF,Data Input Time-out Interrupt Flag (Read Only)\nThis bit indicates that SD host counts to time-out value when receiving data (waiting start bit).\nNote: This bit is read only but can be cleared by writing '1' to it" "0: No time-out,1: Data input time-out"
rbitfld.long 0x00 12. "RTOIF,Response Time-out Interrupt Flag (Read Only)\nThis bit indicates that SD host counts to time-out value when receiving response or R2 (waiting start bit).\nNote: This bit is read only but can be cleared by writing '1' to it" "0: No time-out,1: Response time-out"
newline
rbitfld.long 0x00 10. "SDHIF0,SDH 0 Interrupt Flag (Read Only)\nThis bit indicates that SDH card 0 issues an interrupt to host" "0: No interrupt is issued by SDH card 0,1: an interrupt is issued by SDH card 0"
rbitfld.long 0x00 8. "CDIF0,SD0 Card Detection Interrupt Flag (Read Only)\nThis bit indicates that SD card 0 is inserted or removed" "0: No card is inserted or removed,1: There is a card inserted in or removed from SD0"
newline
rbitfld.long 0x00 7. "DAT0STS,DAT0 Pin Status of Current Selected SD Port (Read Only)\nThis bit is the DAT0 pin status of current selected SD port" "0,1"
rbitfld.long 0x00 4.--6. "CRCSTS,CRC Status Value of Data-out Transfer (Read Only)\nSD host will record CRC status of data-out transfer" "?,?,2: Positive CRC status,?,?,5: Negative CRC status,?,7: SD card programming error occurs"
newline
rbitfld.long 0x00 3. "CRC16,CRC-16 Check Status of Data-in Transfer (Read Only)\nSD host will check CRC-16 correctness after data-in transfer.\n" "0: CRC-16 Transfer incorrectness,1: CRC-16 Transfer correctness"
rbitfld.long 0x00 2. "CRC7,CRC-7 Check Status (Read Only)\nSD host will check CRC-7 correctness during each response in" "0: CRC-7 Transfer incorrectness,1: CRC-7 Transfer correctness"
newline
rbitfld.long 0x00 1. "CRCIF,CRC7 CRC16 and CRC Status Error Interrupt Flag (Read Only)\nThis bit indicates that SD host has occurred CRC error during response in data-in or data-out (CRC status error) transfer" "0: No CRC error is occurred,1: CRC error is occurred"
rbitfld.long 0x00 0. "BLKDIF,Block Transfer Done Interrupt Flag (Read Only)\nThis bit indicates that SD host has finished all data-in or data-out block transfer" "0: Not finished yet,1: Done"
rgroup.long 0x830++0x03
line.long 0x00 "SDH_RESP0,SD Receiving Response Token Register 0"
hexmask.long 0x00 0.--31. 1. "RESPTK0,SD Receiving Response Token 0\nSD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set"
rgroup.long 0x834++0x03
line.long 0x00 "SDH_RESP1,SD Receiving Response Token Register 1"
hexmask.long.byte 0x00 0.--7. 1. "RESPTK1,SD Receiving Response Token 1\nSD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set"
group.long 0x838++0x03
line.long 0x00 "SDH_BLEN,SD Block Length Register"
hexmask.long.word 0x00 0.--10. 1. "BLKLEN,SD BLOCK LENGTH in Byte Unit\nAn 11-bit value specifies the SD transfer byte count of a block"
group.long 0x83C++0x03
line.long 0x00 "SDH_TOUT,SD Response/Data-in Time-out Register"
hexmask.long.tbyte 0x00 0.--23. 1. "TOUT,SD Response/Data-in Time-out Value\nA 24-bit value specifies the time-out count of response and data input"
tree.end
tree "SPI"
repeat 2. (list 0. 1.) (list ad:0x400E9000 ad:0x400E1000)
tree "SPI$1"
base $2
group.long 0x00++0x03
line.long 0x00 "SPI_CTL,SPI Control Register"
bitfld.long 0x00 19. "REORDER,Byte Reorder Function Enable Control\nNote: Byte reorder function is only available if DWIDTH is defined as 16 24 and 32 bits" "0: Byte reorder function Disabled,1: Byte reorder function Enabled"
bitfld.long 0x00 18. "SLAVE,Slave Mode Enable Control\n" "0: Master mode,1: Slave mode"
newline
bitfld.long 0x00 17. "UNITIEN,Unit Transfer Interrupt Enable Control\n" "0: SPI unit transfer interrupt Disabled,1: SPI unit transfer interrupt Enabled"
bitfld.long 0x00 13. "LSB,Send LSB First\n" "0: The MSB which bit of transmit/receive..,1: The LSB bit 0 of the SPI TX register is sent.."
newline
bitfld.long 0x00 8.--12. "DWIDTH,Data Transmit Bit Width\nThis field specifies how many bits can be transmitted / received in one transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 4.--7. "SUSPITV,Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "CLKPOL,Clock Polarity\n" "0: SPICLK is idle low,1: SPICLK is idle high"
bitfld.long 0x00 2. "TXNEG,Transmit on Negative Edge\n" "0: Transmitted data output signal is changed on..,1: Transmitted data output signal is changed on.."
newline
bitfld.long 0x00 1. "RXNEG,Receive on Negative Edge\n" "0: Received data input signal is latched on the..,1: Received data input signal is latched on the.."
bitfld.long 0x00 0. "SPIEN,SPI Transfer Control Enable Bit\nNote1: In Master mode the transfer will start when there is data in the FIFO buffer after this is set to 1" "0: Transfer control bit Disabled,1: Transfer control bit Enabled"
group.long 0x04++0x03
line.long 0x00 "SPI_CLKDIV,SPI Clock Divider Register"
hexmask.long.byte 0x00 0.--7. 1. "DIVIDER,Clock Divider 1 Register \nThe value in this field is the frequency divider for generating the SPI engine clock fspi_eclk and the SPI serial clock of SPI master"
group.long 0x08++0x03
line.long 0x00 "SPI_SSCTL,SPI Slave Select Control Register"
hexmask.long.word 0x00 16.--31. 1. "SLVTOCNT,Slave Mode Time-out Period \nIn Slave mode these bits indicate the time-out period when there is serial clock input during slave select active"
bitfld.long 0x00 13. "SSINAIEN,Slave Select Inactive Interrupt Enable Control\n" "0: Slave select inactive interrupt Disable,1: Slave select inactive interrupt Enable"
newline
bitfld.long 0x00 12. "SSACTIEN,Slave Select Active Interrupt Enable Control\n" "0: Slave select active interrupt Disable,1: Slave select active interrupt Enable"
bitfld.long 0x00 9. "SLVURIEN,Slave Mode Error 1 Interrupt Enable Control\n" "0: Slave mode error 1 interrupt Disable,1: Slave mode error 1 interrupt Enable"
newline
bitfld.long 0x00 8. "SLVBEIEN,Slave Mode Error 0 Interrupt Enable Control\n" "0: Slave mode error 0 interrupt Disable,1: Slave mode error 0 interrupt Enable"
bitfld.long 0x00 6. "SLVTORST,Slave Mode Time-out FIFO Clear\nNote: Both the FIFO clear function TX_CLK and RXRST active automatically when there is a slave mode time-out event" "0: Slave mode Time-out FIFO Clear Disable,1: Slave mode Time-out FIFO Clear Enable"
newline
bitfld.long 0x00 5. "SLVTOIEN,Slave Mode Time-out Interrupt Enable Control\n" "0: Slave mode time-out interrupt Disabled,1: Slave mode time-out interrupt Enabled"
bitfld.long 0x00 4. "SLV3WIRE,Slave 3-wire Mode Enable Control\nThis is used to ignore the slave select signal in Slave mode" "0: 2-wire bi-direction interface,1: 3-wire bi-direction interface"
newline
bitfld.long 0x00 3. "AUTOSS,Automatic Slave Select Function Enable (Master Only)\n" "0: If this bit is cleared slave select signals..,1: If this bit is set SS signal will be.."
bitfld.long 0x00 2. "SSACTPOL,Slave Select Active Level\nThis bit defines the active status of slave select signal (SS).\n" "0: The slave select signal SS is active on..,1: The slave select signal SS is active on.."
newline
bitfld.long 0x00 0. "SS,Slave Selection Control (Master Only)\nIf AUTOSS bit is cleared to 0 \n" "0: set the SPIn_SS line to inactive state.\nKeep..,1: set the SPIn_SS line to active.."
group.long 0x10++0x03
line.long 0x00 "SPI_FIFOCTL,SPI FIFO Control Register"
bitfld.long 0x00 28.--30. "TXTH,Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting the TXTHIF (SPI_STATUS[18]) will be set to 1 else the TXTHIF (SPI_STATUS[18]) will be cleared to 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--26. "RXTH,Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting the RXTHIF (SPI_STATUS[10]) will be set to 1 else the RXTHIF (SPI_STATUS[10]) will be cleared to 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 9. "TXFBCLR,Clear Transmit FIFO\n Note: Auto cleared by Hardware" "0: No effect,1: Clear transmit FIFO only"
bitfld.long 0x00 8. "RXFBCLR,Clear Receive FIFO\n Note: Auto cleared by Hardware" "0: No effect,1: Clear receive FIFO only"
newline
bitfld.long 0x00 7. "TXUFIEN,Slave Transmit Under Run Interrupt Enable Control\n" "0: Slave Transmit FIFO under-run interrupt..,1: Slave Transmit FIFO under-run interrupt Enabled"
bitfld.long 0x00 6. "TXUFPOL,Transmit Under-run Data Out\nNote1: The under run event is active after the serial clock input and the hardware synchronous so that the first 1~3 bit (depending on the relation between system clock and the engine clock) data out will be the last.." "0: The SPI data out is keep 0 if there is..,1: The SPI data out is keep 1 if there is.."
newline
bitfld.long 0x00 5. "RXOVIEN,Receive FIFO Overrun Interrupt Enable Control\n" "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled"
bitfld.long 0x00 4. "RXTOIEN,Slave Receive Time-out Interrupt Enable Control\n" "0: Receive time-out interrupt Disabled,1: Receive time-out interrupt Enabled"
newline
bitfld.long 0x00 3. "TXTHIEN,Transmit FIFO Threshold Interrupt Enable Control\n" "0: TX FIFO threshold interrupt Disabled,1: TX FIFO threshold interrupt Enabled"
bitfld.long 0x00 2. "RXTHIEN,Receive FIFO Threshold Interrupt Enable Control\n" "0: RX FIFO threshold interrupt Disabled,1: RX FIFO threshold interrupt Enabled"
newline
bitfld.long 0x00 1. "TXRST,Clear Transmit FIFO Control\nNote: If there is slave receive time-out event the TXRST will be set 1 when the SLVTORST (SPI_SSCTL[6]) is enabled" "0: No effect,1: Clear transmit FIFO control"
bitfld.long 0x00 0. "RXRST,Clear Receive FIFO Control\nNote: If there is slave receive time-out event the RXRST will be set 1 when the SLVTORST (SPI_SSCTL[6]) is enabled" "0: No effect,1: Clear receive FIFO control"
group.long 0x14++0x03
line.long 0x00 "SPI_STATUS,SPI Status Register"
rbitfld.long 0x00 28.--31. "TXCNT,Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 24.--27. "RXCNT,Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 23. "TXRXRST,FIFO CLR Status (Read Only)\nNote: Both the TXRST (SPI_FIFOCTL[1]) RXRST (SPI_FIFOCTL[0]) need 3 system clock+3 engine clock the status of this bit support the user to monitor the clear function is doing or done" "0: Done the FIFO buffer clear function of TXRST..,1: Doing the FIFO buffer clear function of TXRST.."
bitfld.long 0x00 19. "TXUFIF,TX Underflow Interrupt Flag\nWhen the TX underflow event occurs this bit will be set to 1 the state of data output pin depends on the setting of TXUFPOL.\n" "0: No effect,1: No data in Transmit FIFO and TX shift.."
newline
rbitfld.long 0x00 18. "TXTHIF,Transmit FIFO Threshold Interrupt Status (Read Only)\n" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
rbitfld.long 0x00 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)\n" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
newline
rbitfld.long 0x00 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)\n" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
rbitfld.long 0x00 15. "SPIENSTS,SPI Enable Bit Status (Read Only)\nThe clock source of SPI controller logic is engine clock it is asynchronous with the system clock" "0: Indicate the transmit control bit is disabled,1: Indicate the transfer control bit is active"
newline
bitfld.long 0x00 12. "RXTOIF,Receive Time-out Interrupt Status\nNote: This bit will be cleared by writing 1 to itself" "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
bitfld.long 0x00 11. "RXOVIF,Receive FIFO Overrun Status\nNote: This bit will be cleared by writing 1 to itself" "0: No receiver FIFO overrun status,1: Receive FIFO buffer is full the follow-up.."
newline
rbitfld.long 0x00 10. "RXTHIF,Receive FIFO Threshold Interrupt Status (Read Only)\n" "0: The valid data count within the RX FIFO..,1: The valid data count within the receive FIFO.."
rbitfld.long 0x00 9. "RXFULL,Receive FIFO Buffer Empty Indicator (Read Only)\n" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
newline
rbitfld.long 0x00 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)\n" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
rbitfld.long 0x00 7. "SLVURIF,Slave Mode Error 1 Interrupt Status (Read Only)\nIn Slave mode transmit under-run occurs when the slave select line goes to inactive state.\n" "0: No Slave mode error 1 event,1: Slave mode error 1 occurs"
newline
rbitfld.long 0x00 6. "SLVBEIF,Slave Mode Error 0 Interrupt Status (Read Only)\nIn Slave mode there is bit counter mismatch with DWIDTH (SPI_CTL[12:8]) when the slave select line goes to inactive state.\nNote: If the slave select active but there is no any serial clock input.." "0: No Slave mode error 0 event,1: Slave mode error 0 occurs"
rbitfld.long 0x00 5. "SLVTOIF,Slave Time-out Interrupt Status (Read Only)\nWhen the Slave Select is active and the value of SLVTOCNT (SPI_SSCTL[31:16]) is not 0 and the serial clock input the slave time-out counter in SPI controller logic will be start" "0: Slave time-out is not active,1: Slave time-out is active"
newline
rbitfld.long 0x00 4. "SSLINE,Slave Select Line Bus Status (Read Only)\nNote: If SSACTPOL (SPI_SSCTL[2]) is set 0 and the SSLINE is 1 the SPI slave select is in inactive status" "0: Indicates the slave select line bus status is 0,1: Indicates the slave select line bus status is 1"
bitfld.long 0x00 3. "SSINAIF,Slave Select Inactive Interrupt Status\nNote: This bit will be cleared by writing 1 to itself" "0: Slave select inactive interrupt is cleared or..,1: Slave select inactive interrupt event has.."
newline
bitfld.long 0x00 2. "SSACTIF,Slave Select Active Interrupt Status\nNote: This bit will be cleared by writing 1 to itself" "0: Slave select active interrupt is cleared or..,1: Slave select active interrupt event has.."
bitfld.long 0x00 1. "UNITIF,Unit Transfer Interrupt Status\nNote: This bit will be cleared by writing 1 to itself" "0: No transaction has been finished since this..,1: SPI controller has finished one unit transfer"
newline
rbitfld.long 0x00 0. "BUSY,SPI Unit Bus Status (Read Only)\n" "0: No transaction in the SPI bus,1: SPI controller unit in busy state"
wgroup.long 0x20++0x03
line.long 0x00 "SPI_TX,SPI Data Transmit Register"
hexmask.long 0x00 0.--31. 1. "TX,Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 8-level transmit FIFO buffer"
rgroup.long 0x30++0x03
line.long 0x00 "SPI_RX,SPI Data Receive Register"
hexmask.long 0x00 0.--31. 1. "RX,Data Receive Register\nThere is 8-level FIFO buffer in this controller"
tree.end
repeat.end
tree.end
tree "SPIM"
base ad:0x40007000
group.long 0x00++0x03
line.long 0x00 "SPIM_CTL0,Control and Status Register 0"
hexmask.long.byte 0x00 24.--31. 1. "CMDCODE,Page Program Command Code\nNote1: Quad mode of SPI Flash must be enabled first by I/O mode before using quad page program/quad read commands.\nNote2: See support list for SPI Flash which support these command codes.\nNote3: For TYPE_1 TYPE_2 and.."
bitfld.long 0x00 22.--23. "OPMODE,SPI Function Operation Mode\nNote: In DMA Write mode hardware will send just one page program command per operation" "0: I/O mode,1: DMA Write mode,2: DMA Read mode,3: Direct Memory Map (DMM) mode (Default)"
newline
bitfld.long 0x00 20.--21. "BITMODE,SPI Interface Bit Mode\nNote: Only used for I/O mode" "0: Standard mode,1: Dual mode,2: Quad mode,3: Reserved"
bitfld.long 0x00 16.--19. "SUSPITV,Suspend Interval\nNote: Only used for I/O mode" "0: 2 SCLK clock cycles,1: 3 SCLK clock cycles,?,?,?,?,?,?,?,?,?,?,?,?,14: 16 SCLK clock cycles,15: 17 SCLK clock cycles"
newline
bitfld.long 0x00 15. "QDIODIR,SPI Interface Direction Select for Quad/Dual Mode\nNote: Only used for I/O mode" "0: Interface signals are input,1: Interface signals are output"
bitfld.long 0x00 13.--14. "BURSTNUM,Transmit/Receive Burst Number\nThis field specifies how many transmit/receive transactions should be executed continuously in one transfer.\nNote: Only used for I/O Mode" "0: Only one transmit/receive transaction will be..,1: Two successive transmit/receive transactions..,2: Three successive transmit/receive..,3: Four successive transmit/receive transactions.."
newline
bitfld.long 0x00 8.--12. "DWIDTH,Transmit/Receive Bit Length\nThis field specifies how many bits are transmitted/received in one transmit/receive transaction.\nNote1: Only used for I/O mode.\nNote2: Only 8- 16- 24- and 32-bit are allowed" "?,?,?,?,?,?,?,7: 8 bits,?,?,?,?,?,?,?,15: 16 bits,?,?,?,?,?,?,?,23: 24 bits,?,?,?,?,?,?,?,31: 32 bits"
bitfld.long 0x00 7. "IF,Interrupt Flag\nWrite Operation:\n" "0: No effect.\nThe transfer has not finished yet,1: Write 1 to clear.\nThe transfer has done"
newline
bitfld.long 0x00 6. "IEN,Interrupt Enable Control\n" "0: SPIM Interrupt Disabled,1: SPIM Interrupt Enabled"
bitfld.long 0x00 5. "B4ADDREN,4-byte Address Mode Enable Control\nNote: Used for DMA Write/DMA Read/DMM mode" "0: 4-byte address mode Disabled,1: 4-byte address mode Enabled"
newline
bitfld.long 0x00 2. "BALEN,Balance the AHB Control Time Between Cipher Enable and Disable Control\nWhen cipher is enabled the AHB control signal will delay some time caused by the encoding or decoding calculation" "0,1"
bitfld.long 0x00 0. "CIPHOFF,Cipher Disable Control\nNote1: Cipher function only can be disabled" "0: Cipher function Enabled,1: Cipher function Disabled"
group.long 0x04++0x03
line.long 0x00 "SPIM_CTL1,Control Register 1"
hexmask.long.word 0x00 16.--31. 1. "DIVIDER,Clock Divider Register\nThe value in this field is the frequency divider of the system clock to generate the serial clock on the output SPIM_CLK pin"
bitfld.long 0x00 8.--11. "IDLECNT,Idle Interval\nIn DMM mode IDLECNT is set to control the minimum idle time between two SPI Flash accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 6.--7. "IFSEL,Device/Slave Interface Select\nNote: MCP and MCP64 only can be referenced by MCP SPI Flash pad location" "0: SPI Interface from GPIO,1: SPI Interface from MCP,2: SPI Interface from MCP64,3: Reserved"
bitfld.long 0x00 5. "SSACTPOL,Slave Select Active Level\nIt defines the active level of device/slave select signal (SPIM_SS).\n" "0: The SPIM_SS slave select signal is Active Low,1: The SPIM_SS slave select signal is Active High"
newline
bitfld.long 0x00 4. "SS,Slave Select Active Enable Control\nNote: This interface can only drive one device/slave at a given time" "0: SPIM_SS is in active level,1: SPIM_SS is in inactive level"
bitfld.long 0x00 0. "SPIMEN,Go and Busy Status\nWrite Operation:\nNote: All registers should be set before writing 1 to the SPIMEN bit" "0: No effect.\nThe transfer has done,1: Start the transfer"
group.long 0x08++0x03
line.long 0x00 "SPIM_VALIDCTL,Validation Check Register"
bitfld.long 0x00 16. "VALIDEN,Validation Enable Bit\nSetting this bit to enable the validation function" "0: 1 (Rising Edge) = Enable the validation and..,1: 0 (Falling Edge) = Disable the validation and.."
bitfld.long 0x00 0. "VALIDSTS,Validation Status Bit\nThis bit will be updated when the VALIDEN bit changes.\nNote: Write 0 to clear it to 0" "0: Code in SPI Flash is not valid,1: Code in SPI Flash is valid"
group.long 0x0C++0x03
line.long 0x00 "SPIM_RXCLKDLY,Rx Clock Delay Control Register"
bitfld.long 0x00 29.--31. "DLYSEL,Rx Sample Clock Source Delay Chain Select\n" "0: Not Delay,1: Select sample clock through 2 Delay Cell,2: Select sample clock through 4 Delay Cell,3: Select sample clock through 6 Delay Cell,?,?,?,7: Select sample clock through 14 Delay Cell"
rgroup.long 0x10++0x03
line.long 0x00 "SPIM_RX0,Data Receive Register 0"
hexmask.long 0x00 0.--31. 1. "RX,Data Receive Register\nThe Data Receive Registers hold the received data of the last executed transfer"
repeat 3. (strings "1" "2" "3" )(list 0x0 0x4 0x8 )
group.long ($2+0x14)++0x03
line.long 0x00 "SPIM_RX$1,Data Receive Register $1"
hexmask.long 0x00 0.--31. 1. "RX,Data Receive Register\nThe Data Receive Registers hold the received data of the last executed transfer"
repeat.end
repeat 4. (strings "0" "1" "2" "3" )(list 0x0 0x4 0x8 0xC )
group.long ($2+0x20)++0x03
line.long 0x00 "SPIM_TX$1,Data Transmit Register $1"
hexmask.long 0x00 0.--31. 1. "TX,Data Transmit Register\nThe Data Transmit Registers hold the data to be transmitted in next transfer"
repeat.end
group.long 0x30++0x03
line.long 0x00 "SPIM_SRAMADDR,SRAM Memory Address Register"
hexmask.long 0x00 0.--31. 1. "ADDR,SRAM Memory Address\nFor DMA Read mode this is the destination address for DMA transfer.\nFor DMA Write mode this is the source address for DMA transfer.\nNote: This address must be word-aligned"
group.long 0x34++0x03
line.long 0x00 "SPIM_DMATBCNT,DMA Transfer Byte Count Register"
hexmask.long.tbyte 0x00 0.--23. 1. "CNT,DMA Transfer Byte Count Register\nIt indicates the transfer length for DMA process"
group.long 0x38++0x03
line.long 0x00 "SPIM_FADDR,SPI Flash Address Register"
hexmask.long 0x00 0.--31. 1. "ADDR,SPI Flash Address Register\nFor DMA Read mode this is the source address for DMA transfer.\nFor DMA Write mode this is the destination address for DMA transfer.\nNote: This address must be word-aligned"
tree.end
tree "TIMER"
tree "TIMER01"
base ad:0x400EA000
group.long 0x00++0x03
line.long 0x00 "TIMER0_CTL,Timer0 Control and Status Register"
bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Control\nTimer counter will keep going no matter CPU is held by ICE or not" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
bitfld.long 0x00 30. "CNTEN,Timer Enable Control\n" "0: Stops/Suspends counting,1: Starts counting"
newline
bitfld.long 0x00 29. "INTEN,Interrupt Enable Control\nNote: If this bit is enabled when the timer interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer Interrupt Disabled,1: Timer Interrupt Enabled"
bitfld.long 0x00 27.--28. "OPMODE,Timer Operation Mode\n" "0: Timer controller is operated in One-shot mode,1: Timer controller is operated in Periodic mode,2: Timer controller is operated in Toggle-output..,3: Timer controller is operated in Continuous.."
newline
bitfld.long 0x00 26. "RSTCNT,Timer Reset Control\nSetting this bit will reset the 24-bit up counter value (TIMERx_CNT) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.\n" "0: No effect,1: Reset 8-bit PSC counter 24-bit up counter.."
rbitfld.long 0x00 25. "ACTSTS,Timer Active Status Control (Read Only)\nThis bit indicates the 24-bit up counter status.\n" "0: 24-bit up counter is not active,1: 24-bit up counter is active"
newline
bitfld.long 0x00 24. "EXTCNTEN,Counter Mode Enable Control\nThis bit is for external counting pin function to be enabled" "0: External counter mode Disabled,1: External counter mode Enabled"
bitfld.long 0x00 23. "WKEN,Wake-up Enable Control\nIf this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU.\n" "0: Wake-up trigger event Disabled if timer..,1: Wake-up trigger event Enabled if timer.."
newline
bitfld.long 0x00 16. "CNTDATEN,Data Load Enable Control\nWhen this bit is set timer counter value (TIMERx_CNT) will be updated continuously to monitor internal 24-bit up counter value as the counter is counting.\n" "0: Timer Data Register update Disabled,1: Timer Data Register update Enabled while.."
hexmask.long.byte 0x00 0.--7. 1. "PSC,PSC Counter\n"
group.long 0x04++0x03
line.long 0x00 "TIMER0_CMP,Timer0 Compare Register"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPDAT,Timer Compared Value\nCMPDAT is a 24-bit compared value register"
group.long 0x08++0x03
line.long 0x00 "TIMER0_INTSTS,Timer0 Interrupt Status Register"
bitfld.long 0x00 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it" "0: Timer does not cause CPU wake-up,1: CPU wake-up from Power-down mode and Deep.."
bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while TIMERx_CNT value reaches to CMPDAT value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: TIMERx_CNT value matches the CMPDAT value"
rgroup.long 0x0C++0x03
line.long 0x00 "TIMER0_CNT,Timer0 Data Register"
hexmask.long.tbyte 0x00 0.--23. 1. "CNT,Timer Data Register\nNote: User can read CNT for getting the current 24- bit event counter value if TIMERx_CTL[24] is 1"
rgroup.long 0x10++0x03
line.long 0x00 "TIMER0_CAP,Timer0 Capture Data Register"
hexmask.long.tbyte 0x00 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen the CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting CAPIF (TIMERx_EINTSTS[0]) will be set to 1 and the.."
group.long 0x14++0x03
line.long 0x00 "TIMER0_EXTCTL,Timer0 External Control Register"
bitfld.long 0x00 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Control\nNote: If this bit is enabled the edge detection of TMx_CNT_OUT pin is detected with de-bounce circuit" "0: TMx_CNT_OUT (x= 0~3) pin de-bounce Disabled,1: TMx_CNT_OUT (x= 0~3) pin de-bounce Enabled"
bitfld.long 0x00 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Control\nNote: If this bit is enabled the edge detection of TMx_EXT pin is detected with de-bounce circuit" "0: TMx_EXT (x= 0~3) pin de-bounce Disabled,1: TMx_EXT (x= 0~3) pin de-bounce Enabled"
newline
bitfld.long 0x00 5. "CAPIEN,Timer External Interrupt Enable Control\n" "0: TMx_EXT (x= 0~3) pin detection Interrupt..,1: TMx_EXT (x= 0~3) pin detection Interrupt.."
bitfld.long 0x00 4. "CAPFUNCS,Timer External Reset Counter / Capture Mode Select\n" "0: Transition on TMx_EXT (x= 0~3) pin is using..,1: Transition on TMx_EXT (x= 0~3) pin is using.."
newline
bitfld.long 0x00 3. "CAPEN,Timer External Pin Enable Control\nThis bit enables the CAPFUNCS (TIMERx_EXTCTL[4]) function on the TMx_EXT pin" "0: CAPFUNCS function of TMx_EXT (x= 0~3) pin..,1: CAPFUNCS function of TMx_EXT (x= 0~3) pin is.."
bitfld.long 0x00 1.--2. "CAPEDGE,Timer External Pin Edge Detect\n" "0: A 1 to 0 transition on TMx_EXT (x= 0~3) pin..,1: A 0 to 1 transition on TMx_EXT (x= 0~3) pin..,2: Either 1 to 0 or 0 to 1 transition on TMx_EXT..,3: Reserved"
newline
bitfld.long 0x00 0. "CNTPHASE,Timer External Count Phase \nThis bit indicates the detection phase of external counting pin.\n" "0: A falling edge of external counting pin will..,1: A rising edge of external counting pin will.."
group.long 0x18++0x03
line.long 0x00 "TIMER0_EINTSTS,Timer0 External Interrupt Status Register"
bitfld.long 0x00 0. "CAPIF,Timer External Interrupt Flag\nThis bit indicates the timer external interrupt flag status.\nNote: This bit is cleared by writing 1 to it" "0: TMx_EXT (x= 0~3) pin interrupt did not occur,1: TMx_EXT (x= 0~3) pin interrupt occurred"
group.long 0x20++0x03
line.long 0x00 "TIMER1_CTL,Timer1 Control and Status Register"
bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Control\nTimer counter will keep going no matter CPU is held by ICE or not" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
bitfld.long 0x00 30. "CNTEN,Timer Enable Control\n" "0: Stops/Suspends counting,1: Starts counting"
newline
bitfld.long 0x00 29. "INTEN,Interrupt Enable Control\nNote: If this bit is enabled when the timer interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer Interrupt Disabled,1: Timer Interrupt Enabled"
bitfld.long 0x00 27.--28. "OPMODE,Timer Operation Mode\n" "0: Timer controller is operated in One-shot mode,1: Timer controller is operated in Periodic mode,2: Timer controller is operated in Toggle-output..,3: Timer controller is operated in Continuous.."
newline
bitfld.long 0x00 26. "RSTCNT,Timer Reset Control\nSetting this bit will reset the 24-bit up counter value (TIMERx_CNT) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.\n" "0: No effect,1: Reset 8-bit PSC counter 24-bit up counter.."
rbitfld.long 0x00 25. "ACTSTS,Timer Active Status Control (Read Only)\nThis bit indicates the 24-bit up counter status.\n" "0: 24-bit up counter is not active,1: 24-bit up counter is active"
newline
bitfld.long 0x00 24. "EXTCNTEN,Counter Mode Enable Control\nThis bit is for external counting pin function to be enabled" "0: External counter mode Disabled,1: External counter mode Enabled"
bitfld.long 0x00 23. "WKEN,Wake-up Enable Control\nIf this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU.\n" "0: Wake-up trigger event Disabled if timer..,1: Wake-up trigger event Enabled if timer.."
newline
bitfld.long 0x00 16. "CNTDATEN,Data Load Enable Control\nWhen this bit is set timer counter value (TIMERx_CNT) will be updated continuously to monitor internal 24-bit up counter value as the counter is counting.\n" "0: Timer Data Register update Disabled,1: Timer Data Register update Enabled while.."
hexmask.long.byte 0x00 0.--7. 1. "PSC,PSC Counter\n"
group.long 0x24++0x03
line.long 0x00 "TIMER1_CMP,Timer1 Compare Register"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPDAT,Timer Compared Value\nCMPDAT is a 24-bit compared value register"
group.long 0x28++0x03
line.long 0x00 "TIMER1_INTSTS,Timer1 Interrupt Status Register"
bitfld.long 0x00 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it" "0: Timer does not cause CPU wake-up,1: CPU wake-up from Power-down mode and Deep.."
bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while TIMERx_CNT value reaches to CMPDAT value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: TIMERx_CNT value matches the CMPDAT value"
group.long 0x2C++0x03
line.long 0x00 "TIMER1_CNT,Timer1 Data Register"
hexmask.long.tbyte 0x00 0.--23. 1. "CNT,Timer Data Register\nNote: User can read CNT for getting the current 24- bit event counter value if TIMERx_CTL[24] is 1"
group.long 0x30++0x03
line.long 0x00 "TIMER1_CAP,Timer1 Capture Data Register"
hexmask.long.tbyte 0x00 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen the CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting CAPIF (TIMERx_EINTSTS[0]) will be set to 1 and the.."
group.long 0x34++0x03
line.long 0x00 "TIMER1_EXTCTL,Timer1 External Control Register"
bitfld.long 0x00 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Control\nNote: If this bit is enabled the edge detection of TMx_CNT_OUT pin is detected with de-bounce circuit" "0: TMx_CNT_OUT (x= 0~3) pin de-bounce Disabled,1: TMx_CNT_OUT (x= 0~3) pin de-bounce Enabled"
bitfld.long 0x00 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Control\nNote: If this bit is enabled the edge detection of TMx_EXT pin is detected with de-bounce circuit" "0: TMx_EXT (x= 0~3) pin de-bounce Disabled,1: TMx_EXT (x= 0~3) pin de-bounce Enabled"
newline
bitfld.long 0x00 5. "CAPIEN,Timer External Interrupt Enable Control\n" "0: TMx_EXT (x= 0~3) pin detection Interrupt..,1: TMx_EXT (x= 0~3) pin detection Interrupt.."
bitfld.long 0x00 4. "CAPFUNCS,Timer External Reset Counter / Capture Mode Select\n" "0: Transition on TMx_EXT (x= 0~3) pin is using..,1: Transition on TMx_EXT (x= 0~3) pin is using.."
newline
bitfld.long 0x00 3. "CAPEN,Timer External Pin Enable Control\nThis bit enables the CAPFUNCS (TIMERx_EXTCTL[4]) function on the TMx_EXT pin" "0: CAPFUNCS function of TMx_EXT (x= 0~3) pin..,1: CAPFUNCS function of TMx_EXT (x= 0~3) pin is.."
bitfld.long 0x00 1.--2. "CAPEDGE,Timer External Pin Edge Detect\n" "0: A 1 to 0 transition on TMx_EXT (x= 0~3) pin..,1: A 0 to 1 transition on TMx_EXT (x= 0~3) pin..,2: Either 1 to 0 or 0 to 1 transition on TMx_EXT..,3: Reserved"
newline
bitfld.long 0x00 0. "CNTPHASE,Timer External Count Phase \nThis bit indicates the detection phase of external counting pin.\n" "0: A falling edge of external counting pin will..,1: A rising edge of external counting pin will.."
group.long 0x38++0x03
line.long 0x00 "TIMER1_EINTSTS,Timer1 External Interrupt Status Register"
bitfld.long 0x00 0. "CAPIF,Timer External Interrupt Flag\nThis bit indicates the timer external interrupt flag status.\nNote: This bit is cleared by writing 1 to it" "0: TMx_EXT (x= 0~3) pin interrupt did not occur,1: TMx_EXT (x= 0~3) pin interrupt occurred"
tree.end
tree "TIMER23"
base ad:0x400EB000
group.long 0x00++0x03
line.long 0x00 "TIMER2_CTL,Timer2 Control and Status Register"
bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Control\nTimer counter will keep going no matter CPU is held by ICE or not" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
bitfld.long 0x00 30. "CNTEN,Timer Enable Control\n" "0: Stops/Suspends counting,1: Starts counting"
newline
bitfld.long 0x00 29. "INTEN,Interrupt Enable Control\nNote: If this bit is enabled when the timer interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer Interrupt Disabled,1: Timer Interrupt Enabled"
bitfld.long 0x00 27.--28. "OPMODE,Timer Operation Mode\n" "0: Timer controller is operated in One-shot mode,1: Timer controller is operated in Periodic mode,2: Timer controller is operated in Toggle-output..,3: Timer controller is operated in Continuous.."
newline
bitfld.long 0x00 26. "RSTCNT,Timer Reset Control\nSetting this bit will reset the 24-bit up counter value (TIMERx_CNT) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.\n" "0: No effect,1: Reset 8-bit PSC counter 24-bit up counter.."
rbitfld.long 0x00 25. "ACTSTS,Timer Active Status Control (Read Only)\nThis bit indicates the 24-bit up counter status.\n" "0: 24-bit up counter is not active,1: 24-bit up counter is active"
newline
bitfld.long 0x00 24. "EXTCNTEN,Counter Mode Enable Control\nThis bit is for external counting pin function to be enabled" "0: External counter mode Disabled,1: External counter mode Enabled"
bitfld.long 0x00 23. "WKEN,Wake-up Enable Control\nIf this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU.\n" "0: Wake-up trigger event Disabled if timer..,1: Wake-up trigger event Enabled if timer.."
newline
bitfld.long 0x00 16. "CNTDATEN,Data Load Enable Control\nWhen this bit is set timer counter value (TIMERx_CNT) will be updated continuously to monitor internal 24-bit up counter value as the counter is counting.\n" "0: Timer Data Register update Disabled,1: Timer Data Register update Enabled while.."
hexmask.long.byte 0x00 0.--7. 1. "PSC,PSC Counter\n"
group.long 0x04++0x03
line.long 0x00 "TIMER2_CMP,Timer2 Compare Register"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPDAT,Timer Compared Value\nCMPDAT is a 24-bit compared value register"
group.long 0x08++0x03
line.long 0x00 "TIMER2_INTSTS,Timer2 Interrupt Status Register"
bitfld.long 0x00 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it" "0: Timer does not cause CPU wake-up,1: CPU wake-up from Power-down mode and Deep.."
bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while TIMERx_CNT value reaches to CMPDAT value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: TIMERx_CNT value matches the CMPDAT value"
rgroup.long 0x0C++0x03
line.long 0x00 "TIMER2_CNT,Timer2 Data Register"
hexmask.long.tbyte 0x00 0.--23. 1. "CNT,Timer Data Register\nNote: User can read CNT for getting the current 24- bit event counter value if TIMERx_CTL[24] is 1"
rgroup.long 0x10++0x03
line.long 0x00 "TIMER2_CAP,Timer2 Capture Data Register"
hexmask.long.tbyte 0x00 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen the CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting CAPIF (TIMERx_EINTSTS[0]) will be set to 1 and the.."
group.long 0x14++0x03
line.long 0x00 "TIMER2_EXTCTL,Timer2 External Control Register"
bitfld.long 0x00 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Control\nNote: If this bit is enabled the edge detection of TMx_CNT_OUT pin is detected with de-bounce circuit" "0: TMx_CNT_OUT (x= 0~3) pin de-bounce Disabled,1: TMx_CNT_OUT (x= 0~3) pin de-bounce Enabled"
bitfld.long 0x00 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Control\nNote: If this bit is enabled the edge detection of TMx_EXT pin is detected with de-bounce circuit" "0: TMx_EXT (x= 0~3) pin de-bounce Disabled,1: TMx_EXT (x= 0~3) pin de-bounce Enabled"
newline
bitfld.long 0x00 5. "CAPIEN,Timer External Interrupt Enable Control\n" "0: TMx_EXT (x= 0~3) pin detection Interrupt..,1: TMx_EXT (x= 0~3) pin detection Interrupt.."
bitfld.long 0x00 4. "CAPFUNCS,Timer External Reset Counter / Capture Mode Select\n" "0: Transition on TMx_EXT (x= 0~3) pin is using..,1: Transition on TMx_EXT (x= 0~3) pin is using.."
newline
bitfld.long 0x00 3. "CAPEN,Timer External Pin Enable Control\nThis bit enables the CAPFUNCS (TIMERx_EXTCTL[4]) function on the TMx_EXT pin" "0: CAPFUNCS function of TMx_EXT (x= 0~3) pin..,1: CAPFUNCS function of TMx_EXT (x= 0~3) pin is.."
bitfld.long 0x00 1.--2. "CAPEDGE,Timer External Pin Edge Detect\n" "0: A 1 to 0 transition on TMx_EXT (x= 0~3) pin..,1: A 0 to 1 transition on TMx_EXT (x= 0~3) pin..,2: Either 1 to 0 or 0 to 1 transition on TMx_EXT..,3: Reserved"
newline
bitfld.long 0x00 0. "CNTPHASE,Timer External Count Phase \nThis bit indicates the detection phase of external counting pin.\n" "0: A falling edge of external counting pin will..,1: A rising edge of external counting pin will.."
group.long 0x18++0x03
line.long 0x00 "TIMER2_EINTSTS,Timer2 External Interrupt Status Register"
bitfld.long 0x00 0. "CAPIF,Timer External Interrupt Flag\nThis bit indicates the timer external interrupt flag status.\nNote: This bit is cleared by writing 1 to it" "0: TMx_EXT (x= 0~3) pin interrupt did not occur,1: TMx_EXT (x= 0~3) pin interrupt occurred"
group.long 0x20++0x03
line.long 0x00 "TIMER3_CTL,Timer3 Control and Status Register"
bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Control\nTimer counter will keep going no matter CPU is held by ICE or not" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
bitfld.long 0x00 30. "CNTEN,Timer Enable Control\n" "0: Stops/Suspends counting,1: Starts counting"
newline
bitfld.long 0x00 29. "INTEN,Interrupt Enable Control\nNote: If this bit is enabled when the timer interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer Interrupt Disabled,1: Timer Interrupt Enabled"
bitfld.long 0x00 27.--28. "OPMODE,Timer Operation Mode\n" "0: Timer controller is operated in One-shot mode,1: Timer controller is operated in Periodic mode,2: Timer controller is operated in Toggle-output..,3: Timer controller is operated in Continuous.."
newline
bitfld.long 0x00 26. "RSTCNT,Timer Reset Control\nSetting this bit will reset the 24-bit up counter value (TIMERx_CNT) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.\n" "0: No effect,1: Reset 8-bit PSC counter 24-bit up counter.."
rbitfld.long 0x00 25. "ACTSTS,Timer Active Status Control (Read Only)\nThis bit indicates the 24-bit up counter status.\n" "0: 24-bit up counter is not active,1: 24-bit up counter is active"
newline
bitfld.long 0x00 24. "EXTCNTEN,Counter Mode Enable Control\nThis bit is for external counting pin function to be enabled" "0: External counter mode Disabled,1: External counter mode Enabled"
bitfld.long 0x00 23. "WKEN,Wake-up Enable Control\nIf this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU.\n" "0: Wake-up trigger event Disabled if timer..,1: Wake-up trigger event Enabled if timer.."
newline
bitfld.long 0x00 16. "CNTDATEN,Data Load Enable Control\nWhen this bit is set timer counter value (TIMERx_CNT) will be updated continuously to monitor internal 24-bit up counter value as the counter is counting.\n" "0: Timer Data Register update Disabled,1: Timer Data Register update Enabled while.."
hexmask.long.byte 0x00 0.--7. 1. "PSC,PSC Counter\n"
group.long 0x24++0x03
line.long 0x00 "TIMER3_CMP,Timer3 Compare Register"
hexmask.long.tbyte 0x00 0.--23. 1. "CMPDAT,Timer Compared Value\nCMPDAT is a 24-bit compared value register"
group.long 0x28++0x03
line.long 0x00 "TIMER3_INTSTS,Timer3 Interrupt Status Register"
bitfld.long 0x00 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it" "0: Timer does not cause CPU wake-up,1: CPU wake-up from Power-down mode and Deep.."
bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while TIMERx_CNT value reaches to CMPDAT value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: TIMERx_CNT value matches the CMPDAT value"
group.long 0x2C++0x03
line.long 0x00 "TIMER3_CNT,Timer3 Data Register"
hexmask.long.tbyte 0x00 0.--23. 1. "CNT,Timer Data Register\nNote: User can read CNT for getting the current 24- bit event counter value if TIMERx_CTL[24] is 1"
group.long 0x30++0x03
line.long 0x00 "TIMER3_CAP,Timer3 Capture Data Register"
hexmask.long.tbyte 0x00 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen the CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting CAPIF (TIMERx_EINTSTS[0]) will be set to 1 and the.."
group.long 0x34++0x03
line.long 0x00 "TIMER3_EXTCTL,Timer3 External Control Register"
bitfld.long 0x00 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Control\nNote: If this bit is enabled the edge detection of TMx_CNT_OUT pin is detected with de-bounce circuit" "0: TMx_CNT_OUT (x= 0~3) pin de-bounce Disabled,1: TMx_CNT_OUT (x= 0~3) pin de-bounce Enabled"
bitfld.long 0x00 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Control\nNote: If this bit is enabled the edge detection of TMx_EXT pin is detected with de-bounce circuit" "0: TMx_EXT (x= 0~3) pin de-bounce Disabled,1: TMx_EXT (x= 0~3) pin de-bounce Enabled"
newline
bitfld.long 0x00 5. "CAPIEN,Timer External Interrupt Enable Control\n" "0: TMx_EXT (x= 0~3) pin detection Interrupt..,1: TMx_EXT (x= 0~3) pin detection Interrupt.."
bitfld.long 0x00 4. "CAPFUNCS,Timer External Reset Counter / Capture Mode Select\n" "0: Transition on TMx_EXT (x= 0~3) pin is using..,1: Transition on TMx_EXT (x= 0~3) pin is using.."
newline
bitfld.long 0x00 3. "CAPEN,Timer External Pin Enable Control\nThis bit enables the CAPFUNCS (TIMERx_EXTCTL[4]) function on the TMx_EXT pin" "0: CAPFUNCS function of TMx_EXT (x= 0~3) pin..,1: CAPFUNCS function of TMx_EXT (x= 0~3) pin is.."
bitfld.long 0x00 1.--2. "CAPEDGE,Timer External Pin Edge Detect\n" "0: A 1 to 0 transition on TMx_EXT (x= 0~3) pin..,1: A 0 to 1 transition on TMx_EXT (x= 0~3) pin..,2: Either 1 to 0 or 0 to 1 transition on TMx_EXT..,3: Reserved"
newline
bitfld.long 0x00 0. "CNTPHASE,Timer External Count Phase \nThis bit indicates the detection phase of external counting pin.\n" "0: A falling edge of external counting pin will..,1: A rising edge of external counting pin will.."
group.long 0x38++0x03
line.long 0x00 "TIMER3_EINTSTS,Timer3 External Interrupt Status Register"
bitfld.long 0x00 0. "CAPIF,Timer External Interrupt Flag\nThis bit indicates the timer external interrupt flag status.\nNote: This bit is cleared by writing 1 to it" "0: TMx_EXT (x= 0~3) pin interrupt did not occur,1: TMx_EXT (x= 0~3) pin interrupt occurred"
tree.end
tree.end
tree "UART"
tree "UART0"
base ad:0x400EC000
group.long 0x00++0x03
line.long 0x00 "UART_DAT,UART Receive/Transmit Buffer Register"
hexmask.long.byte 0x00 0.--7. 1. "DAT,Receiving/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register the data byte will be stored in transmitter FIFO"
group.long 0x04++0x03
line.long 0x00 "UART_INTEN,UART Interrupt Enable Register"
bitfld.long 0x00 18. "ABRIEN,Auto-baud Rate Interrupt Enable Control\n" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
bitfld.long 0x00 13. "ATOCTSEN,nCTS Auto-flow Control Enable Control\n When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)" "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
newline
bitfld.long 0x00 12. "ATORTSEN,nRTS Auto-flow Control Enable Control\n When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal" "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
bitfld.long 0x00 11. "TOCNTEN,Time-out Counter Enable Control\n" "0: Time-out counter Disabled,1: Time-out counter Enabled"
newline
bitfld.long 0x00 10. "WKDATIEN,Incoming Data Wake-up Interrupt Enable Control\n Hardware will clear this bit when the incoming data wake-up operation finishes and system clock work stable" "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled"
bitfld.long 0x00 9. "WKCTSIEN,nCTS Wake-up Interrupt Enable Control\n" "0: nCTS wake-up system function Disabled,1: Wake-up system function Enabled"
newline
bitfld.long 0x00 8. "LINIEN,LIN Bus Interrupt Enable Control (Not Available in UART1/UART2)\n This bit is used for LIN function mode" "0: LIN bus interrupt Disabled,1: LIN bus interrupt Enabled"
bitfld.long 0x00 5. "BUFERRIEN,Buffer Error Interrupt Enable Control\n" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
newline
bitfld.long 0x00 4. "RXTOIEN,RX Time-out Interrupt Enable Control\n" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
bitfld.long 0x00 3. "MODEMIEN,Modem Status Interrupt Enable Control\n" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
newline
bitfld.long 0x00 2. "RLSIEN,Receive Line Status Interrupt Enable Control\n" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
bitfld.long 0x00 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Control\n" "0: Transmit holding register empty interrupt..,1: Transmit holding register empty interrupt.."
newline
bitfld.long 0x00 0. "RDAIEN,Receive Data Available Interrupt Enable Control\n" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
group.long 0x08++0x03
line.long 0x00 "UART_FIFO,UART FIFO Control Register"
bitfld.long 0x00 16.--19. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control Use\nNote: This field is used for automatic nRTS flow control" "0: nRTS Trigger Level is 1 bytes,1: nRTS Trigger Level is 4bytes,2: nRTS Trigger Level is 8 bytes,3: nRTS Trigger Level is 14 bytes,4: nRTS Trigger Level is 30/14 (64 FIFO/16 FIFO),5: nRTS Trigger Level is 46/14 (64 FIFO/16 FIFO),6: nRTS Trigger Level is 62/14 (64 FIFO/16 FIFO),?..."
bitfld.long 0x00 8. "RXOFF,Receiver Disable Control\nThe receiver is disabled or not (set 1 to disable receiver)\nNote: This bit is used for RS-485 Normal Multi-drop mode" "0: Receiver Enabled,1: Receiver Disabled"
newline
bitfld.long 0x00 4.--7. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL the RDAIF will be set (if RDAIEN (UART_INTEN [0]) enabled and an interrupt will be generated).\n" "0: RX FIFO Interrupt Trigger Level is 1 byte,1: RX FIFO Interrupt Trigger Level is 4 bytes,2: RX FIFO Interrupt Trigger Level is 8 bytes,3: RX FIFO Interrupt Trigger Level is 14 bytes,4: RX FIFO Interrupt Trigger Level is 30/14 (64..,5: RX FIFO Interrupt Trigger Level is 46/14 (64..,6: RX FIFO Interrupt Trigger Level is 62/14 (64..,?..."
bitfld.long 0x00 2. "TXRST,TX Field Software Reset Control\nWhen TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripheral clock cycles" "0: No effect,1: Reset the TX internal state machine and.."
newline
bitfld.long 0x00 1. "RXRST,RX Field Software Reset Control\nWhen RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripheral clock cycles" "0: No effect,1: Reset the RX internal state machine and.."
group.long 0x0C++0x03
line.long 0x00 "UART_LINE,UART Line Control Register"
bitfld.long 0x00 6. "BCB,Break Control\nNote: When this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0)" "0: Break Control Disabled,1: Break Control Enabled"
bitfld.long 0x00 5. "SPE,Stick Parity Enable Control\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the parity bit is transmitted and checked as logic 0" "0: Stick parity Disabled,1: Stick parity Enabled"
newline
bitfld.long 0x00 4. "EPE,Even Parity Enable Control\nNote: This bit is effective only when PBE (UART_LINE[3]) is set" "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
bitfld.long 0x00 3. "PBE,Parity Bit Enable Control\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data" "0: No parity bit generated Disabled,1: Parity bit generated Enabled"
newline
bitfld.long 0x00 2. "NSB,Number of STOP Bit \n" "0: One STOP bit is generated in the transmitted..,1: When select 5-bit word length 1.5 STOP bit is.."
bitfld.long 0x00 0.--1. "WLS,Word Length Selection\nThis field sets UART word length.\n" "0: 5 bits,1: 6 bits,2: 7 bits,3: 8 bits"
group.long 0x10++0x03
line.long 0x00 "UART_MODEM,UART Modem Control Register"
rbitfld.long 0x00 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status.\n" "0: nRTS pin output is low level voltage logic..,1: nRTS pin output is high level voltage logic.."
bitfld.long 0x00 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote1: Refer to Figure 6.1010 and Figure 6.1011 for UART function mode.\nNote2: Refer to Figure 6.1021 and Figure 6.1022 for RS-485 function mode" "0: nRTS pin output is high level active,1: nRTS pin output is low level active"
newline
bitfld.long 0x00 1. "RTS,nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote1: This nRTS signal control bit is not effective when nRTS auto-flow.." "0: nRTS signal is active,1: nRTS signal is inactive"
group.long 0x14++0x03
line.long 0x00 "UART_MODEMSTS,UART Modem Status Register"
bitfld.long 0x00 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\n" "0: nCTS pin input is high level active,1: nCTS pin input is low level active"
rbitfld.long 0x00 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART Controller peripheral clock is enabled and nCTS multi-function port is selected" "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic.."
newline
rbitfld.long 0x00 0. "CTSDETF,Detect nCTS State Change Flag (Read Only)\nThis bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit is read only but can be cleared by writing 1.." "0: nCTS input has not change state,1: nCTS input has change state"
group.long 0x18++0x03
line.long 0x00 "UART_FIFOSTS,UART FIFO Status Register"
rbitfld.long 0x00 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty,1: TX FIFO is empty"
rbitfld.long 0x00 24. "TXOVIF,TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit is read only but can be cleared by writing 1 to it" "0: TX FIFO is not overflow,1: TX FIFO is overflow"
newline
rbitfld.long 0x00 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16/64 otherwise is cleared by hardware" "0: TX FIFO is not full,1: TX FIFO is full"
rbitfld.long 0x00 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high" "0: TX FIFO is not empty,1: TX FIFO is empty"
newline
rbitfld.long 0x00 16.--21. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16/64 otherwise is cleared by hardware" "0: RX FIFO is not full,1: RX FIFO is full"
newline
rbitfld.long 0x00 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high" "0: RX FIFO is not empty,1: RX FIFO is empty"
rbitfld.long 0x00 8.--13. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 6. "BIF,Break Interrupt Flag (Read Only)\nThis bit is set to logic 1 whenever the received data input (RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is the total time of start bit + data bits + parity + stop.." "0: No Break interrupt is generated,1: Break interrupt is generated"
rbitfld.long 0x00 5. "FEF,Framing Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid stop bit (that is the stop bit following the last data bit or parity bit is detected as logic 0).\n Note: This bit is read only but can.." "0: No framing error is generated,1: Framing error is generated"
newline
rbitfld.long 0x00 4. "PEF,Parity Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid parity bit .\nNote: This bit is read only but can be cleared by writing '1' to it" "0: No parity error is generated,1: Parity error is generated"
rbitfld.long 0x00 3. "ADDRDETF,RS-485 Address Byte Detect Flag (Read Only) \nNote1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote2: This bit is read only but can be cleared by writing '1' to it" "0: Receiver detects a data that is not an..,1: Receiver detects a data that is an address.."
newline
rbitfld.long 0x00 2. "ABRDTOIF,Auto-baud Rate Time-out Interrupt (Read Only) \nNote1: This bit is set to logic 1 in Auto-baud Rate Detect mode and the baud rate counter is overflow.\nNote2: This bit is read only but can be cleared by writing 1 to it" "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
rbitfld.long 0x00 1. "ABRDIF,Auto-baud Rate Detect Interrupt (Read Only) \nNote1: This bit is set to logic 1 when auto-baud rate detect function is finished" "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
newline
rbitfld.long 0x00 0. "RXOVIF,RX Overflow Error Interrupt Flag (Read Only)\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16/64 bytes this bit will be set.\nNote: This bit is read only but can be.." "0: RX FIFO is not overflow,1: RX FIFO is overflow"
group.long 0x1C++0x03
line.long 0x00 "UART_INTSTS,UART Interrupt Status Register"
rbitfld.long 0x00 17. "DATWKIF,Data Wake-up Interrupt Flag (Read Only)\nThis bit is set if chip wake-up from Power-down state by data wake-up.\nNote1: If WKDATIEN (UART_INTEN[10]) is enabled the wake-up interrupt is generated.\nNote2: This bit is read only but can be cleared.." "0: Chip stays in Power-down state,1: Chip wake-up from Power-down state by data.."
rbitfld.long 0x00 16. "CTSWKIF,nCTS Wake-up Interrupt Flag (Read Only)\nNote1: If WKCTSIEN (UART_INTEN[9])is enabled the wake-up interrupt is generated.\nNote2: This bit is read only but can be cleared by writing '1' to it" "0: Chip stays in Power-down state,1: Chip wake-up from Power-down state by nCTS.."
newline
rbitfld.long 0x00 15. "LININT,LIN Bus Interrupt Indicator (Read Only)(Not Available in UART0 Channel)\nThis bit is set if LINIEN (UART_INTEN[8]) and LIN IF(UART_INTSTS[7]) are both set to 1.\n" "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
rbitfld.long 0x00 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set when DATWKIF or CTSWKIF is set to 1.\n" "0: NO data or nCTS wake-up interrupt are generated,1: Data or nCTS wake-up interrupt are generated"
newline
rbitfld.long 0x00 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BFERRIEN(UART_INTEN[5] and BUFERRIF(UART_INTSTS[5]) are both set to 1.\n" "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
rbitfld.long 0x00 12. "RXTOINT,Time-out Interrupt Indicator (Read Only)\nThis bit is set if TOUTIEN(UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1.\n" "0: No Tout interrupt is generated,1: Tout interrupt is generated"
newline
rbitfld.long 0x00 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3] and MODEMIF(UART_INTSTS[4]) are both set to 1\n" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
rbitfld.long 0x00 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1.\n" "0: No RLS interrupt is generated,1: RLS interrupt is generated"
newline
rbitfld.long 0x00 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1])and THREIF(UART_INTSTS[1]) are both set to 1.\n" "0: No DATE interrupt is generated,1: DATE interrupt is generated"
rbitfld.long 0x00 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1.\n" "0: No RDA interrupt is generated,1: RDA interrupt is generated"
newline
rbitfld.long 0x00 7. "LINIF,LIN Bus Interrupt Flag (Read Only) (Not Available in UART0 Channel)\nNote: This bit is read only" "0: None of SLVHDETF BRKDETF BITEF SLVIDPEF and..,1: At least one of SLVHDETF BRKDETF BITEF.."
rbitfld.long 0x00 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when DATWKIF (UART_INTSTS[17]) or CTSWKIF(UART_INTSTS[16]) is set to 1.\nNote: This bit is read only" "0: No DATWKIF and CTSWKIF are generated,1: DATWKIF or CTSWKIF"
newline
rbitfld.long 0x00 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
rbitfld.long 0x00 4. "RXTOIF,Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC" "0: No Time-out interrupt flag is generated,1: Time-out interrupt flag is generated"
newline
rbitfld.long 0x00 3. "MODEMIF,MODEM Interrupt Flag (Read Only) Channel \nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])" "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
rbitfld.long 0x00 2. "RLSIF,Receive Line Interrupt Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UART_FIFOSTS[6]) FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
newline
rbitfld.long 0x00 1. "THREIF,Transmit Holding Register Empty Interrupt Flag (Read Only) \nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register" "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
rbitfld.long 0x00 0. "RDAIF,Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set" "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
group.long 0x20++0x03
line.long 0x00 "UART_TOUT,UART Time-out Register"
hexmask.long.byte 0x00 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit"
hexmask.long.byte 0x00 0.--7. 1. "TOIC,Time-out Interrupt Comparator\n"
group.long 0x24++0x03
line.long 0x00 "UART_BAUD,UART Baud Rate Divisor Register"
bitfld.long 0x00 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1" "0,1"
bitfld.long 0x00 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0" "0,1"
newline
bitfld.long 0x00 24.--27. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider"
group.long 0x28++0x03
line.long 0x00 "UART_IRDA,UART IrDA Control Register"
bitfld.long 0x00 6. "RXINV,IrDA Inverse Receive Input Signal \n" "0: None inverse receiving input signal,1: Inverse receiving input signal"
bitfld.long 0x00 5. "TXINV,IrDA Inverse Transmitting Output Signal \n" "0: None inverse transmitting signal,1: Inverse transmitting output signal"
newline
bitfld.long 0x00 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Control\n" "0: IrDA Transmitter Disabled and Receiver Enabled,1: IrDA Transmitter Enabled and Receiver Disabled"
group.long 0x2C++0x03
line.long 0x00 "UART_ALTCTL,UART Alternate Control/Status Register"
hexmask.long.byte 0x00 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\n This field is used for RS-485 auto address detection mode"
bitfld.long 0x00 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote: The calculation of bit number includes the START bit" "0: 1-bit time from Start bit to the 1st rising..,1: 2-bit time from Start bit to the 1st rising..,2: 4-bit time from Start bit to the 1st rising..,3: 8-bit time from Start bit to the 1st rising.."
newline
bitfld.long 0x00 18. "ABRDEN,Auto-baud Rate Detect Enable Control\nNote: This bit is cleared automatically after auto-baud detection is finished" "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
rbitfld.long 0x00 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated" "0,1"
newline
bitfld.long 0x00 15. "ADDRDEN,RS-485 Address Detection Enable Control\nThis bit is used to enable RS-485 Address Detection mode" "0: Address detection mode Disabled,1: Address detection mode Enabled"
bitfld.long 0x00 10. "RS485AUD,RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode" "0: RS-485 Auto Direction Operation function..,1: RS-485 Auto Direction Operation function.."
newline
bitfld.long 0x00 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode (AAD)\n It cannot be active with RS-485_NMM operation mode" "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
bitfld.long 0x00 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode" "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
newline
bitfld.long 0x00 7. "LINTXEN,LIN TX Break Mode Enable Control (Only Available in UART1/UART2 Channel)\nNote: When TX break field transfer operation finished this bit will be cleared automatically" "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
bitfld.long 0x00 6. "LINRXEN,LIN RX Enable Control (Only Available in UART1/UART2 Channel)\n" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
newline
bitfld.long 0x00 0.--3. "BRKFL,UART LIN Break Field Length (Only Available in UART1/UART2 Channel)\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is BRKFL + 1\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x30++0x03
line.long 0x00 "UART_FUNCSEL,UART Function Select Register"
bitfld.long 0x00 0.--1. "FUNCSEL,Function Select\n" "0: UART function,1: LIN function (Only Available in UART1/UART2..,2: IrDA function,3: RS-485 function"
group.long 0x34++0x03
line.long 0x00 "UART_LINCTL,UART LIN Control Register *"
hexmask.long.byte 0x00 24.--31. 1. "PID,LIN PID Bits\nIf the parity generated by hardware and user fills in ID0~ID5 (PID [29:24]) hardware will calculate P0 (PID[30]) and P1 (PID[31]) otherwise user must fill a frame ID and parity in this field.\nNote1: User can fill in any 8-bit value to.."
bitfld.long 0x00 22.--23. "HSEL,LIN Header Select \n" "0: The LIN header includes break field,1: The LIN header includes break field and sync..,2: The LIN header includes break field sync..,3: Reserved"
newline
bitfld.long 0x00 20.--21. "BSL,LIN Break/Sync Delimiter Length \nNote: This bit is used for LIN master to send header field" "0: The LIN break/sync delimiter length is 1-bit..,1: The LIN break/sync delimiter length is 2-bit..,2: The LIN break/sync delimiter length is 3-bit..,3: The LIN break/sync delimiter length is 4-bit.."
bitfld.long 0x00 16.--19. "BRKFL,LIN Break Field Length \nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of BRKFL User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL (UART_LINCTL[19:16]).\nNote2: This break.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 12. "BITERREN,Bit Error Detect Enable Control\n" "0: Bit error detection function Disabled,1: Bit error detection Enabled"
bitfld.long 0x00 11. "RXOFF,LIN Receiver Disable Control\n" "0: LIN receiver Enabled,1: LIN receiver Disabled"
newline
bitfld.long 0x00 10. "BRKDETEN,LIN Break Detection Enable Control\n" "0: LIN break detection Disabled,1: LIN break detection Enabled"
bitfld.long 0x00 9. "IDPEN,LIN ID Parity Enable Control\n" "0: LIN frame ID parity Disabled,1: LIN frame ID parity Enabled"
newline
bitfld.long 0x00 8. "SENDH,LIN TX Send Header Enable Control\nThe LIN TX header can be break field or break and sync field or break sync and frame ID field it is depend on setting HSEL (UART_LINCTL[23:22]).\nNote1: These registers are shadow registers of LINTXEN.." "0: Send LIN TX header Disabled,1: Send LIN TX header Enabled"
bitfld.long 0x00 4. "MUTE,LIN Mute Mode Enable Control\nNote: The exit from mute mode condition and each control and interactions of this field are explained in 6.10.5.9 (LIN Slave mode)" "0: LIN mute mode Disabled,1: LIN mute mode Enabled"
newline
bitfld.long 0x00 3. "SLVDUEN,LIN Slave Divider Update Method Enable Control\nNote2: This bit is used for LIN Slave Automatic Resynchronization mode" "0: UART_BAUD updated is written by software (if..,1: UART_BAUD is updated at the next received.."
bitfld.long 0x00 2. "SLVAREN,LIN Slave Automatic Resynchronization Mode Enable Control\nNote2: When operating in Automatic Resynchronization mode the baud rate setting must be mode2 (BAUDM1 (UART_BAUD [29]) and BAUDM0 (UART_BAUD [28]) must be 1).\nNote3: The control and.." "0: LIN automatic resynchronization Disabled,1: LIN automatic resynchronization Enabled"
newline
bitfld.long 0x00 1. "SLVHDEN,LIN Slave Header Detection Enable Control\n" "0: LIN slave header detection Disabled,1: LIN slave header detection Enabled"
bitfld.long 0x00 0. "SLVEN,LIN Slave Mode Enable Control\n" "0: LIN Slave mode Disabled,1: LIN Slave mode Enabled"
group.long 0x38++0x03
line.long 0x00 "UART_LINSTS,UART LIN Status Register *"
rbitfld.long 0x00 9. "BITEF,Bit Error Detect Status Flag (Read Only) \nAt TX transfer state hardware will monitoring the bus state if the input pin (SIN) state not equals to the output pin (SOUT) state BITEF (UART_LINSTS[9]) will be set.\n" "0,1"
rbitfld.long 0x00 8. "BRKDETF,LIN Break Detection Flag (Read Only)\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it through software.\n" "0: LIN break not detected,1: LIN break detected"
newline
rbitfld.long 0x00 3. "SLVSYNCF,LIN Slave Sync Field (Read Only)\nThis bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode" "0: The current character is not at LIN sync state,1: The current character is at LIN sync state"
bitfld.long 0x00 2. "SLVIDPEF,LIN Slave ID Parity Error Flag \nThis bit is set by hardware when receipted frame ID parity is not correct.\n" "0: No active,1: Receipted frame ID parity is not correct"
newline
rbitfld.long 0x00 1. "SLVHEF,LIN Slave Header Error Flag (Read Only)\nThis bit is set by hardware when a LIN header error is detected in LIN Slave mode and be cleared by writing 1 to it" "0: LIN header error not detected,1: LIN header error detected"
rbitfld.long 0x00 0. "SLVHDETF,LIN Slave Header Detection Flag (Read Only)\nThis bit is set by hardware when a LIN header is detected in LIN Slave mode and be cleared by writing 1 to it.\nNote3: When enable ID parity check IDPEN (UART_LINCTL [9]) if hardware detect complete.." "0: LIN header not detected,1: LIN header detected (break + sync + frame ID)"
tree.end
repeat 2. (list 1. 2.) (list ad:0x400ED000 ad:0x400EE000)
tree "UART$1"
base $2
group.long 0x00++0x03
line.long 0x00 "UART_DAT,UART Receive/Transmit Buffer Register"
hexmask.long.byte 0x00 0.--7. 1. "DAT,Receiving/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register the data byte will be stored in transmitter FIFO"
group.long 0x04++0x03
line.long 0x00 "UART_INTEN,UART Interrupt Enable Register"
bitfld.long 0x00 18. "ABRIEN,Auto-baud Rate Interrupt Enable Control\n" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
bitfld.long 0x00 13. "ATOCTSEN,nCTS Auto-flow Control Enable Control\n When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)" "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
newline
bitfld.long 0x00 12. "ATORTSEN,nRTS Auto-flow Control Enable Control\n When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal" "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
bitfld.long 0x00 11. "TOCNTEN,Time-out Counter Enable Control\n" "0: Time-out counter Disabled,1: Time-out counter Enabled"
newline
bitfld.long 0x00 10. "WKDATIEN,Incoming Data Wake-up Interrupt Enable Control\n Hardware will clear this bit when the incoming data wake-up operation finishes and system clock work stable" "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled"
bitfld.long 0x00 9. "WKCTSIEN,nCTS Wake-up Interrupt Enable Control\n" "0: nCTS wake-up system function Disabled,1: Wake-up system function Enabled"
newline
bitfld.long 0x00 8. "LINIEN,LIN Bus Interrupt Enable Control (Not Available in UART1/UART2)\n This bit is used for LIN function mode" "0: LIN bus interrupt Disabled,1: LIN bus interrupt Enabled"
bitfld.long 0x00 5. "BUFERRIEN,Buffer Error Interrupt Enable Control\n" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
newline
bitfld.long 0x00 4. "RXTOIEN,RX Time-out Interrupt Enable Control\n" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
bitfld.long 0x00 3. "MODEMIEN,Modem Status Interrupt Enable Control\n" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
newline
bitfld.long 0x00 2. "RLSIEN,Receive Line Status Interrupt Enable Control\n" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
bitfld.long 0x00 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Control\n" "0: Transmit holding register empty interrupt..,1: Transmit holding register empty interrupt.."
newline
bitfld.long 0x00 0. "RDAIEN,Receive Data Available Interrupt Enable Control\n" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
group.long 0x08++0x03
line.long 0x00 "UART_FIFO,UART FIFO Control Register"
bitfld.long 0x00 16.--19. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control Use\nNote: This field is used for automatic nRTS flow control" "0: nRTS Trigger Level is 1 bytes,1: nRTS Trigger Level is 4bytes,2: nRTS Trigger Level is 8 bytes,3: nRTS Trigger Level is 14 bytes,4: nRTS Trigger Level is 30/14 (64 FIFO/16 FIFO),5: nRTS Trigger Level is 46/14 (64 FIFO/16 FIFO),6: nRTS Trigger Level is 62/14 (64 FIFO/16 FIFO),?..."
bitfld.long 0x00 8. "RXOFF,Receiver Disable Control\nThe receiver is disabled or not (set 1 to disable receiver)\nNote: This bit is used for RS-485 Normal Multi-drop mode" "0: Receiver Enabled,1: Receiver Disabled"
newline
bitfld.long 0x00 4.--7. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL the RDAIF will be set (if RDAIEN (UART_INTEN [0]) enabled and an interrupt will be generated).\n" "0: RX FIFO Interrupt Trigger Level is 1 byte,1: RX FIFO Interrupt Trigger Level is 4 bytes,2: RX FIFO Interrupt Trigger Level is 8 bytes,3: RX FIFO Interrupt Trigger Level is 14 bytes,4: RX FIFO Interrupt Trigger Level is 30/14 (64..,5: RX FIFO Interrupt Trigger Level is 46/14 (64..,6: RX FIFO Interrupt Trigger Level is 62/14 (64..,?..."
bitfld.long 0x00 2. "TXRST,TX Field Software Reset Control\nWhen TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripheral clock cycles" "0: No effect,1: Reset the TX internal state machine and.."
newline
bitfld.long 0x00 1. "RXRST,RX Field Software Reset Control\nWhen RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripheral clock cycles" "0: No effect,1: Reset the RX internal state machine and.."
group.long 0x0C++0x03
line.long 0x00 "UART_LINE,UART Line Control Register"
bitfld.long 0x00 6. "BCB,Break Control\nNote: When this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0)" "0: Break Control Disabled,1: Break Control Enabled"
bitfld.long 0x00 5. "SPE,Stick Parity Enable Control\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the parity bit is transmitted and checked as logic 0" "0: Stick parity Disabled,1: Stick parity Enabled"
newline
bitfld.long 0x00 4. "EPE,Even Parity Enable Control\nNote: This bit is effective only when PBE (UART_LINE[3]) is set" "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
bitfld.long 0x00 3. "PBE,Parity Bit Enable Control\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data" "0: No parity bit generated Disabled,1: Parity bit generated Enabled"
newline
bitfld.long 0x00 2. "NSB,Number of STOP Bit \n" "0: One STOP bit is generated in the transmitted..,1: When select 5-bit word length 1.5 STOP bit is.."
bitfld.long 0x00 0.--1. "WLS,Word Length Selection\nThis field sets UART word length.\n" "0: 5 bits,1: 6 bits,2: 7 bits,3: 8 bits"
group.long 0x10++0x03
line.long 0x00 "UART_MODEM,UART Modem Control Register"
rbitfld.long 0x00 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status.\n" "0: nRTS pin output is low level voltage logic..,1: nRTS pin output is high level voltage logic.."
bitfld.long 0x00 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote1: Refer to Figure 6.1010 and Figure 6.1011 for UART function mode.\nNote2: Refer to Figure 6.1021 and Figure 6.1022 for RS-485 function mode" "0: nRTS pin output is high level active,1: nRTS pin output is low level active"
newline
bitfld.long 0x00 1. "RTS,nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote1: This nRTS signal control bit is not effective when nRTS auto-flow.." "0: nRTS signal is active,1: nRTS signal is inactive"
group.long 0x14++0x03
line.long 0x00 "UART_MODEMSTS,UART Modem Status Register"
bitfld.long 0x00 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\n" "0: nCTS pin input is high level active,1: nCTS pin input is low level active"
rbitfld.long 0x00 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART Controller peripheral clock is enabled and nCTS multi-function port is selected" "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic.."
newline
rbitfld.long 0x00 0. "CTSDETF,Detect nCTS State Change Flag (Read Only)\nThis bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.\nNote: This bit is read only but can be cleared by writing 1.." "0: nCTS input has not change state,1: nCTS input has change state"
group.long 0x18++0x03
line.long 0x00 "UART_FIFOSTS,UART FIFO Status Register"
rbitfld.long 0x00 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty,1: TX FIFO is empty"
rbitfld.long 0x00 24. "TXOVIF,TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit is read only but can be cleared by writing 1 to it" "0: TX FIFO is not overflow,1: TX FIFO is overflow"
newline
rbitfld.long 0x00 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16/64 otherwise is cleared by hardware" "0: TX FIFO is not full,1: TX FIFO is full"
rbitfld.long 0x00 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high" "0: TX FIFO is not empty,1: TX FIFO is empty"
newline
rbitfld.long 0x00 16.--21. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16/64 otherwise is cleared by hardware" "0: RX FIFO is not full,1: RX FIFO is full"
newline
rbitfld.long 0x00 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high" "0: RX FIFO is not empty,1: RX FIFO is empty"
rbitfld.long 0x00 8.--13. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
rbitfld.long 0x00 6. "BIF,Break Interrupt Flag (Read Only)\nThis bit is set to logic 1 whenever the received data input (RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is the total time of start bit + data bits + parity + stop.." "0: No Break interrupt is generated,1: Break interrupt is generated"
rbitfld.long 0x00 5. "FEF,Framing Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid stop bit (that is the stop bit following the last data bit or parity bit is detected as logic 0).\n Note: This bit is read only but can.." "0: No framing error is generated,1: Framing error is generated"
newline
rbitfld.long 0x00 4. "PEF,Parity Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid parity bit .\nNote: This bit is read only but can be cleared by writing '1' to it" "0: No parity error is generated,1: Parity error is generated"
rbitfld.long 0x00 3. "ADDRDETF,RS-485 Address Byte Detect Flag (Read Only) \nNote1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote2: This bit is read only but can be cleared by writing '1' to it" "0: Receiver detects a data that is not an..,1: Receiver detects a data that is an address.."
newline
rbitfld.long 0x00 2. "ABRDTOIF,Auto-baud Rate Time-out Interrupt (Read Only) \nNote1: This bit is set to logic 1 in Auto-baud Rate Detect mode and the baud rate counter is overflow.\nNote2: This bit is read only but can be cleared by writing 1 to it" "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
rbitfld.long 0x00 1. "ABRDIF,Auto-baud Rate Detect Interrupt (Read Only) \nNote1: This bit is set to logic 1 when auto-baud rate detect function is finished" "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
newline
rbitfld.long 0x00 0. "RXOVIF,RX Overflow Error Interrupt Flag (Read Only)\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16/64 bytes this bit will be set.\nNote: This bit is read only but can be.." "0: RX FIFO is not overflow,1: RX FIFO is overflow"
group.long 0x1C++0x03
line.long 0x00 "UART_INTSTS,UART Interrupt Status Register"
rbitfld.long 0x00 17. "DATWKIF,Data Wake-up Interrupt Flag (Read Only)\nThis bit is set if chip wake-up from Power-down state by data wake-up.\nNote1: If WKDATIEN (UART_INTEN[10]) is enabled the wake-up interrupt is generated.\nNote2: This bit is read only but can be cleared.." "0: Chip stays in Power-down state,1: Chip wake-up from Power-down state by data.."
rbitfld.long 0x00 16. "CTSWKIF,nCTS Wake-up Interrupt Flag (Read Only)\nNote1: If WKCTSIEN (UART_INTEN[9])is enabled the wake-up interrupt is generated.\nNote2: This bit is read only but can be cleared by writing '1' to it" "0: Chip stays in Power-down state,1: Chip wake-up from Power-down state by nCTS.."
newline
rbitfld.long 0x00 15. "LININT,LIN Bus Interrupt Indicator (Read Only)(Not Available in UART0 Channel)\nThis bit is set if LINIEN (UART_INTEN[8]) and LIN IF(UART_INTSTS[7]) are both set to 1.\n" "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated"
rbitfld.long 0x00 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set when DATWKIF or CTSWKIF is set to 1.\n" "0: NO data or nCTS wake-up interrupt are generated,1: Data or nCTS wake-up interrupt are generated"
newline
rbitfld.long 0x00 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BFERRIEN(UART_INTEN[5] and BUFERRIF(UART_INTSTS[5]) are both set to 1.\n" "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
rbitfld.long 0x00 12. "RXTOINT,Time-out Interrupt Indicator (Read Only)\nThis bit is set if TOUTIEN(UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1.\n" "0: No Tout interrupt is generated,1: Tout interrupt is generated"
newline
rbitfld.long 0x00 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN(UART_INTEN[3] and MODEMIF(UART_INTSTS[4]) are both set to 1\n" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
rbitfld.long 0x00 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1.\n" "0: No RLS interrupt is generated,1: RLS interrupt is generated"
newline
rbitfld.long 0x00 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1])and THREIF(UART_INTSTS[1]) are both set to 1.\n" "0: No DATE interrupt is generated,1: DATE interrupt is generated"
rbitfld.long 0x00 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1.\n" "0: No RDA interrupt is generated,1: RDA interrupt is generated"
newline
rbitfld.long 0x00 7. "LINIF,LIN Bus Interrupt Flag (Read Only) (Not Available in UART0 Channel)\nNote: This bit is read only" "0: None of SLVHDETF BRKDETF BITEF SLVIDPEF and..,1: At least one of SLVHDETF BRKDETF BITEF.."
rbitfld.long 0x00 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when DATWKIF (UART_INTSTS[17]) or CTSWKIF(UART_INTSTS[16]) is set to 1.\nNote: This bit is read only" "0: No DATWKIF and CTSWKIF are generated,1: DATWKIF or CTSWKIF"
newline
rbitfld.long 0x00 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
rbitfld.long 0x00 4. "RXTOIF,Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC" "0: No Time-out interrupt flag is generated,1: Time-out interrupt flag is generated"
newline
rbitfld.long 0x00 3. "MODEMIF,MODEM Interrupt Flag (Read Only) Channel \nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])" "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
rbitfld.long 0x00 2. "RLSIF,Receive Line Interrupt Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UART_FIFOSTS[6]) FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
newline
rbitfld.long 0x00 1. "THREIF,Transmit Holding Register Empty Interrupt Flag (Read Only) \nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register" "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
rbitfld.long 0x00 0. "RDAIF,Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set" "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
group.long 0x20++0x03
line.long 0x00 "UART_TOUT,UART Time-out Register"
hexmask.long.byte 0x00 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit"
hexmask.long.byte 0x00 0.--7. 1. "TOIC,Time-out Interrupt Comparator\n"
group.long 0x24++0x03
line.long 0x00 "UART_BAUD,UART Baud Rate Divisor Register"
bitfld.long 0x00 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1" "0,1"
bitfld.long 0x00 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0" "0,1"
newline
bitfld.long 0x00 24.--27. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider"
group.long 0x28++0x03
line.long 0x00 "UART_IRDA,UART IrDA Control Register"
bitfld.long 0x00 6. "RXINV,IrDA Inverse Receive Input Signal \n" "0: None inverse receiving input signal,1: Inverse receiving input signal"
bitfld.long 0x00 5. "TXINV,IrDA Inverse Transmitting Output Signal \n" "0: None inverse transmitting signal,1: Inverse transmitting output signal"
newline
bitfld.long 0x00 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Control\n" "0: IrDA Transmitter Disabled and Receiver Enabled,1: IrDA Transmitter Enabled and Receiver Disabled"
group.long 0x2C++0x03
line.long 0x00 "UART_ALTCTL,UART Alternate Control/Status Register"
hexmask.long.byte 0x00 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\n This field is used for RS-485 auto address detection mode"
bitfld.long 0x00 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote: The calculation of bit number includes the START bit" "0: 1-bit time from Start bit to the 1st rising..,1: 2-bit time from Start bit to the 1st rising..,2: 4-bit time from Start bit to the 1st rising..,3: 8-bit time from Start bit to the 1st rising.."
newline
bitfld.long 0x00 18. "ABRDEN,Auto-baud Rate Detect Enable Control\nNote: This bit is cleared automatically after auto-baud detection is finished" "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
rbitfld.long 0x00 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated" "0,1"
newline
bitfld.long 0x00 15. "ADDRDEN,RS-485 Address Detection Enable Control\nThis bit is used to enable RS-485 Address Detection mode" "0: Address detection mode Disabled,1: Address detection mode Enabled"
bitfld.long 0x00 10. "RS485AUD,RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode" "0: RS-485 Auto Direction Operation function..,1: RS-485 Auto Direction Operation function.."
newline
bitfld.long 0x00 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode (AAD)\n It cannot be active with RS-485_NMM operation mode" "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
bitfld.long 0x00 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode" "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
newline
bitfld.long 0x00 7. "LINTXEN,LIN TX Break Mode Enable Control (Only Available in UART1/UART2 Channel)\nNote: When TX break field transfer operation finished this bit will be cleared automatically" "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled"
bitfld.long 0x00 6. "LINRXEN,LIN RX Enable Control (Only Available in UART1/UART2 Channel)\n" "0: LIN RX mode Disabled,1: LIN RX mode Enabled"
newline
bitfld.long 0x00 0.--3. "BRKFL,UART LIN Break Field Length (Only Available in UART1/UART2 Channel)\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is BRKFL + 1\n" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x30++0x03
line.long 0x00 "UART_FUNCSEL,UART Function Select Register"
bitfld.long 0x00 0.--1. "FUNCSEL,Function Select\n" "0: UART function,1: LIN function (Only Available in UART1/UART2..,2: IrDA function,3: RS-485 function"
group.long 0x34++0x03
line.long 0x00 "UART_LINCTL,UART LIN Control Register *"
hexmask.long.byte 0x00 24.--31. 1. "PID,LIN PID Bits\nIf the parity generated by hardware and user fills in ID0~ID5 (PID [29:24]) hardware will calculate P0 (PID[30]) and P1 (PID[31]) otherwise user must fill a frame ID and parity in this field.\nNote1: User can fill in any 8-bit value to.."
bitfld.long 0x00 22.--23. "HSEL,LIN Header Select \n" "0: The LIN header includes break field,1: The LIN header includes break field and sync..,2: The LIN header includes break field sync..,3: Reserved"
newline
bitfld.long 0x00 20.--21. "BSL,LIN Break/Sync Delimiter Length \nNote: This bit is used for LIN master to send header field" "0: The LIN break/sync delimiter length is 1-bit..,1: The LIN break/sync delimiter length is 2-bit..,2: The LIN break/sync delimiter length is 3-bit..,3: The LIN break/sync delimiter length is 4-bit.."
bitfld.long 0x00 16.--19. "BRKFL,LIN Break Field Length \nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of BRKFL User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL (UART_LINCTL[19:16]).\nNote2: This break.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 12. "BITERREN,Bit Error Detect Enable Control\n" "0: Bit error detection function Disabled,1: Bit error detection Enabled"
bitfld.long 0x00 11. "RXOFF,LIN Receiver Disable Control\n" "0: LIN receiver Enabled,1: LIN receiver Disabled"
newline
bitfld.long 0x00 10. "BRKDETEN,LIN Break Detection Enable Control\n" "0: LIN break detection Disabled,1: LIN break detection Enabled"
bitfld.long 0x00 9. "IDPEN,LIN ID Parity Enable Control\n" "0: LIN frame ID parity Disabled,1: LIN frame ID parity Enabled"
newline
bitfld.long 0x00 8. "SENDH,LIN TX Send Header Enable Control\nThe LIN TX header can be break field or break and sync field or break sync and frame ID field it is depend on setting HSEL (UART_LINCTL[23:22]).\nNote1: These registers are shadow registers of LINTXEN.." "0: Send LIN TX header Disabled,1: Send LIN TX header Enabled"
bitfld.long 0x00 4. "MUTE,LIN Mute Mode Enable Control\nNote: The exit from mute mode condition and each control and interactions of this field are explained in 6.10.5.9 (LIN Slave mode)" "0: LIN mute mode Disabled,1: LIN mute mode Enabled"
newline
bitfld.long 0x00 3. "SLVDUEN,LIN Slave Divider Update Method Enable Control\nNote2: This bit is used for LIN Slave Automatic Resynchronization mode" "0: UART_BAUD updated is written by software (if..,1: UART_BAUD is updated at the next received.."
bitfld.long 0x00 2. "SLVAREN,LIN Slave Automatic Resynchronization Mode Enable Control\nNote2: When operating in Automatic Resynchronization mode the baud rate setting must be mode2 (BAUDM1 (UART_BAUD [29]) and BAUDM0 (UART_BAUD [28]) must be 1).\nNote3: The control and.." "0: LIN automatic resynchronization Disabled,1: LIN automatic resynchronization Enabled"
newline
bitfld.long 0x00 1. "SLVHDEN,LIN Slave Header Detection Enable Control\n" "0: LIN slave header detection Disabled,1: LIN slave header detection Enabled"
bitfld.long 0x00 0. "SLVEN,LIN Slave Mode Enable Control\n" "0: LIN Slave mode Disabled,1: LIN Slave mode Enabled"
group.long 0x38++0x03
line.long 0x00 "UART_LINSTS,UART LIN Status Register *"
rbitfld.long 0x00 9. "BITEF,Bit Error Detect Status Flag (Read Only) \nAt TX transfer state hardware will monitoring the bus state if the input pin (SIN) state not equals to the output pin (SOUT) state BITEF (UART_LINSTS[9]) will be set.\n" "0,1"
rbitfld.long 0x00 8. "BRKDETF,LIN Break Detection Flag (Read Only)\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it through software.\n" "0: LIN break not detected,1: LIN break detected"
newline
rbitfld.long 0x00 3. "SLVSYNCF,LIN Slave Sync Field (Read Only)\nThis bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode" "0: The current character is not at LIN sync state,1: The current character is at LIN sync state"
bitfld.long 0x00 2. "SLVIDPEF,LIN Slave ID Parity Error Flag \nThis bit is set by hardware when receipted frame ID parity is not correct.\n" "0: No active,1: Receipted frame ID parity is not correct"
newline
rbitfld.long 0x00 1. "SLVHEF,LIN Slave Header Error Flag (Read Only)\nThis bit is set by hardware when a LIN header error is detected in LIN Slave mode and be cleared by writing 1 to it" "0: LIN header error not detected,1: LIN header error detected"
rbitfld.long 0x00 0. "SLVHDETF,LIN Slave Header Detection Flag (Read Only)\nThis bit is set by hardware when a LIN header is detected in LIN Slave mode and be cleared by writing 1 to it.\nNote3: When enable ID parity check IDPEN (UART_LINCTL [9]) if hardware detect complete.." "0: LIN header not detected,1: LIN header detected (break + sync + frame ID)"
tree.end
repeat.end
tree.end
tree "USBD"
base ad:0x40019000
rgroup.long 0x00++0x03
line.long 0x00 "USBD_GINTSTS,Global Interrupt Status Register"
bitfld.long 0x00 13. "EPLIF,Endpoints L Interrupt\nWhen set the corresponding Endpoint L's interrupt status register should be read to determine the cause of the interrupt.\n" "0: No interrupt event occurred,1: The related interrupt event is occurred"
bitfld.long 0x00 12. "EPKIF,Endpoints K Interrupt\nWhen set the corresponding Endpoint K's interrupt status register should be read to determine the cause of the interrupt.\n" "0: No interrupt event occurred,1: The related interrupt event is occurred"
newline
bitfld.long 0x00 11. "EPJIF,Endpoints J Interrupt\nWhen set the corresponding Endpoint J's interrupt status register should be read to determine the cause of the interrupt.\n" "0: No interrupt event occurred,1: The related interrupt event is occurred"
bitfld.long 0x00 10. "EPIIF,Endpoints I Interrupt\nWhen set the corresponding Endpoint I's interrupt status register should be read to determine the cause of the interrupt.\n" "0: No interrupt event occurred,1: The related interrupt event is occurred"
newline
bitfld.long 0x00 9. "EPHIF,Endpoints H Interrupt\nWhen set the corresponding Endpoint H's interrupt status register should be read to determine the cause of the interrupt.\n" "0: No interrupt event occurred,1: The related interrupt event is occurred"
bitfld.long 0x00 8. "EPGIF,Endpoints G Interrupt\nWhen set the corresponding Endpoint G's interrupt status register should be read to determine the cause of the interrupt.\n" "0: No interrupt event occurred,1: The related interrupt event is occurred"
newline
bitfld.long 0x00 7. "EPFIF,Endpoints F Interrupt\nWhen set the corresponding Endpoint F's interrupt status register should be read to determine the cause of the interrupt.\n" "0: No interrupt event occurred,1: The related interrupt event is occurred"
bitfld.long 0x00 6. "EPEIF,Endpoints E Interrupt\nWhen set the corresponding Endpoint E's interrupt status register should be read to determine the cause of the interrupt.\n" "0: No interrupt event occurred,1: The related interrupt event is occurred"
newline
bitfld.long 0x00 5. "EPDIF,Endpoints D Interrupt\nWhen set the corresponding Endpoint D's interrupt status register should be read to determine the cause of the interrupt.\n" "0: No interrupt event occurred,1: The related interrupt event is occurred"
bitfld.long 0x00 4. "EPCIF,Endpoints C Interrupt\nWhen set the corresponding Endpoint C's interrupt status register should be read to determine the cause of the interrupt.\n" "0: No interrupt event occurred,1: The related interrupt event is occurred"
newline
bitfld.long 0x00 3. "EPBIF,Endpoints B Interrupt\nWhen set the corresponding Endpoint B's interrupt status register should be read to determine the cause of the interrupt.\n" "0: No interrupt event occurred,1: The related interrupt event is occurred"
bitfld.long 0x00 2. "EPAIF,Endpoints a Interrupt\nWhen set the corresponding Endpoint A's interrupt status register should be read to determine the cause of the interrupt.\n" "0: No interrupt event occurred,1: The related interrupt event is occurred"
newline
bitfld.long 0x00 1. "CEPIF,Control Endpoint Interrupt \nThis bit conveys the interrupt status for control endpoint" "0: No interrupt event occurred,1: The related interrupt event is occurred"
bitfld.long 0x00 0. "USBIF,USB Interrupt \nThis bit conveys the interrupt status for USB specific events endpoint" "0: No interrupt event occurred,1: The related interrupt event is occurred"
group.long 0x08++0x03
line.long 0x00 "USBD_GINTEN,Global Interrupt Enable Register"
bitfld.long 0x00 13. "EPLIEN,Interrupt Enable Control for Endpoint L \nWhen set this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint L\n" "0: The related interrupt Disabled,1: The related interrupt Enabled"
bitfld.long 0x00 12. "EPKIEN,Interrupt Enable Control for Endpoint K \nWhen set this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint K\n" "0: The related interrupt Disabled,1: The related interrupt Enabled"
newline
bitfld.long 0x00 11. "EPJIEN,Interrupt Enable Control for Endpoint J \nWhen set this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint J\n" "0: The related interrupt Disabled,1: The related interrupt Enabled"
bitfld.long 0x00 10. "EPIIEN,Interrupt Enable Control for Endpoint I \nWhen set this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint I\n" "0: The related interrupt Disabled,1: The related interrupt Enabled"
newline
bitfld.long 0x00 9. "EPHIEN,Interrupt Enable Control for Endpoint H \nWhen set this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint H\n" "0: The related interrupt Disabled,1: The related interrupt Enabled"
bitfld.long 0x00 8. "EPGIEN,Interrupt Enable Control for Endpoint G\nWhen set this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint G\n" "0: The related interrupt Disabled,1: The related interrupt Enabled"
newline
bitfld.long 0x00 7. "EPFIEN,Interrupt Enable Control for Endpoint F \nWhen set this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint F\n" "0: The related interrupt Disabled,1: The related interrupt Enabled"
bitfld.long 0x00 6. "EPEIEN,Interrupt Enable Control for Endpoint E \nWhen set this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint E\n" "0: The related interrupt Disabled,1: The related interrupt Enabled"
newline
bitfld.long 0x00 5. "EPDIEN,Interrupt Enable Control for Endpoint D \nWhen set this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint D\n" "0: The related interrupt Disabled,1: The related interrupt Enabled"
bitfld.long 0x00 4. "EPCIEN,Interrupt Enable Control for Endpoint C \nWhen set this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint C\n" "0: The related interrupt Disabled,1: The related interrupt Enabled"
newline
bitfld.long 0x00 3. "EPBIEN,Interrupt Enable Control for Endpoint B \nWhen set this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint B \n" "0: The related interrupt Disabled,1: The related interrupt Enabled"
bitfld.long 0x00 2. "EPAIEN,Interrupt Enable Control for Endpoint a \nWhen set this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint A.\n" "0: The related interrupt Disabled,1: The related interrupt Enabled"
newline
bitfld.long 0x00 1. "CEPIEN,Control Endpoint Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be generated when an interrupt is pending for the control endpoint.\n" "0: The related interrupt Disabled,1: The related interrupt Enabled"
bitfld.long 0x00 0. "USBIEN,USB Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be generated when a USB event occurs on the bus.\n" "0: The related interrupt Disabled,1: The related interrupt Enabled"
group.long 0x10++0x03
line.long 0x00 "USBD_BUSINTSTS,USB Bus Interrupt Status Register"
bitfld.long 0x00 8. "VBUSDETIF,VBUS Detection Interrupt Status \n Write 1 to clear this bit to 0" "0: No VBUS is plug-in,1: VBUS is plug-in"
bitfld.long 0x00 6. "PHYCLKVLDIF,Usable Clock Interrupt \n Write 1 to clear this bit to 0" "0: Usable clock is not available,1: Usable clock is available from the transceiver"
newline
bitfld.long 0x00 5. "DMADONEIF,DMA Completion Interrupt \n Write 1 to clear this bit to 0" "0: No DMA transfer over,1: DMA transfer is over"
bitfld.long 0x00 4. "HISPDIF,High-speed Settle \n Write 1 to clear this bit to 0" "0: No valid high-speed reset protocol is detected,1: Valid high-speed reset protocol is over and.."
newline
bitfld.long 0x00 3. "SUSPENDIF,Suspend Request \nThis bit is set as default and it has to be cleared by writing '1' before the USB reset" "0: No USB Suspend request is detected from the..,1: USB Suspend request is detected from the host"
bitfld.long 0x00 2. "RESUMEIF,Resume \nWhen set this bit indicates that a device resume has occurred.\n Write 1 to clear this bit to 0" "0: No device resume has occurred,1: Device resume has occurred"
newline
bitfld.long 0x00 1. "RSTIF,Reset Status \nWhen set this bit indicates that either the USB root port reset is end.\n Write 1 to clear this bit to 0" "0: No USB root port reset is end,1: USB root port reset is end"
bitfld.long 0x00 0. "SOFIF,SOF Receive Control\nThis bit indicates when a start-of-frame packet has been received" "0: No start-of-frame packet has been received,1: Start-of-frame packet has been received"
group.long 0x14++0x03
line.long 0x00 "USBD_BUSINTEN,USB Bus Interrupt Enable Register"
bitfld.long 0x00 8. "VBUSDETIEN,VBUS Detection Interrupt Enable Control\nThis bit enables the VBUS floating detection interrupt.\n" "0: VBUS floating detection interrupt Disabled,1: VBUS floating detection interrupt Enabled"
bitfld.long 0x00 6. "PHYCLKVLDIEN,Usable Clock Interrupt\nThis bit enables the usable clock interrupt.\n" "0: Usable clock interrupt Disabled,1: Usable clock interrupt Enabled"
newline
bitfld.long 0x00 5. "DMADONEIEN,DMA Completion Interrupt \nThis bit enables the DMA completion interrupt\n" "0: DMA completion interrupt Disabled,1: DMA completion interrupt Enabled"
bitfld.long 0x00 4. "HISPDIEN,High-speed Settle \nThis bit enables the high-speed settle interrupt.\n" "0: High-speed settle interrupt Disabled,1: High-speed settle interrupt Enabled"
newline
bitfld.long 0x00 3. "SUSPENDIEN,Suspend Request \nThis bit enables the Suspend interrupt.\n" "0: Suspend interrupt Disabled,1: Suspend interrupt Enabled"
bitfld.long 0x00 2. "RESUMEIEN,Resume \nThis bit enables the Resume interrupt.\n" "0: Resume interrupt Disabled,1: Resume interrupt Enabled"
newline
bitfld.long 0x00 1. "RSTIEN,Reset Status \nThis bit enables the USB-Reset interrupt.\n" "0: USB-Reset interrupt Disabled,1: USB-Reset interrupt Enabled"
bitfld.long 0x00 0. "SOFIEN,SOF Interrupt\nThis bit enables the SOF interrupt.\n" "0: SOF interrupt Disabled,1: SOF interrupt Enabled"
group.long 0x18++0x03
line.long 0x00 "USBD_OPER,USB Operational Register"
bitfld.long 0x00 2. "CURSPD,Current USB Speed\n" "0: The device has settled in Full Speed,1: The USB device controller has settled in High.."
bitfld.long 0x00 1. "HISPDEN,USB High-speed\n" "0: The USB device controller suppresses the..,1: The USB device controller initiates a.."
newline
bitfld.long 0x00 0. "RESUMEEN,Generate Resume\n" "0: No resume sequence to be initiated to the host,1: A resume sequence to be initiated to the host.."
rgroup.long 0x1C++0x03
line.long 0x00 "USBD_FRAMECNT,USB Frame Count Register"
hexmask.long.word 0x00 3.--13. 1. "FRAMECNT,Frame Counter\nThis field contains the frame count from the most recent start-of-frame packet"
bitfld.long 0x00 0.--2. "MFRAMECNT,Micro-frame Counter\nThis field contains the micro-frame number for the frame number in the frame counter field" "0,1,2,3,4,5,6,7"
group.long 0x20++0x03
line.long 0x00 "USBD_FADDR,USB Function Address Register"
hexmask.long.byte 0x00 0.--6. 1. "FADDR,USB Function Address\nThis field contains the current USB address of the device"
group.long 0x24++0x03
line.long 0x00 "USBD_TEST,USB Test Mode Register"
bitfld.long 0x00 0.--2. "TESTMODE,Test Mode Selection\nNote: This field is cleared when root port reset is detected" "0: Normal Operation,1: Test_J,2: Test_K,3: Test_SE0_NAK,4: Test_Packet,5: Test_Force_Enable,6: Reserved,7: Reserved"
group.long 0x28++0x03
line.long 0x00 "USBD_CEPDAT,Control-endpoint Data Buffer"
hexmask.long 0x00 0.--31. 1. "DAT,Control-endpoint Data Buffer \nControl endpoint data buffer for the buffer transaction (read or write).\nOnly word or byte access is supported"
group.long 0x2C++0x03
line.long 0x00 "USBD_CEPCTL,Control-endpoint Control Register"
bitfld.long 0x00 3. "FLUSH,CEP-fLUSH Bit \n" "0: No packet buffer and its corresponding..,1: The packet buffer and its corresponding.."
bitfld.long 0x00 2. "ZEROLEN,Zero Packet Length\nThis bit is valid for Auto Validation mode only" "0: No zero length packet to the host during Data..,1: USB device controller can send a zero length.."
newline
bitfld.long 0x00 1. "STALLEN,Stall Enable Control\nWhen this stall bit is set the control endpoint sends a stall handshake in response to any in or out token thereafter" "0: No sends a stall handshake in response to any..,1: The control endpoint sends a stall handshake.."
bitfld.long 0x00 0. "NAKCLR,No Acknowledge Control\nThis bit plays a crucial role in any control transfer" "0: The bit is being cleared by the local CPU by..,1: This bit is set to one by the USB device.."
group.long 0x30++0x03
line.long 0x00 "USBD_CEPINTEN,Control-endpoint Interrupt Enable Control Register"
bitfld.long 0x00 12. "BUFEMPTYIEN,Buffer Empty Interrupt \n" "0: The buffer empty interrupt in Control..,1: The buffer empty interrupt in Control.."
bitfld.long 0x00 11. "BUFFULLIEN,Buffer Full Interrupt \n" "0: The buffer full interrupt in Control Endpoint..,1: The buffer full interrupt in Control Endpoint.."
newline
bitfld.long 0x00 10. "STSDONEIEN,Status Completion Interrupt \n" "0: The Status Completion interrupt in Control..,1: The Status Completion interrupt in Control.."
bitfld.long 0x00 9. "ERRIEN,USB Error Interrupt \n" "0: The USB Error interrupt in Control Endpoint..,1: The USB Error interrupt in Control Endpoint.."
newline
bitfld.long 0x00 8. "STALLIEN,STALL Sent Interrupt \n" "0: The STALL sent interrupt in Control Endpoint..,1: The STALL sent interrupt in Control Endpoint.."
bitfld.long 0x00 7. "NAKIEN,NAK Sent Interrupt \n" "0: The NAK sent interrupt in Control Endpoint..,1: The NAK sent interrupt in Control Endpoint.."
newline
bitfld.long 0x00 6. "RXPKIEN,Data Packet Received Interrupt \n" "0: The data received interrupt in Control..,1: The data received interrupt in Control.."
bitfld.long 0x00 5. "TXPKIEN,Data Packet Transmitted Interrupt \n" "0: The data packet transmitted interrupt in..,1: The data packet transmitted interrupt in.."
newline
bitfld.long 0x00 4. "PINGIEN,Ping Token Interrupt \n" "0: The ping token interrupt in Control Endpoint..,1: The ping token interrupt Control Endpoint.."
bitfld.long 0x00 3. "INTKIEN,in Token Interrupt \n" "0: The IN token interrupt in Control Endpoint..,1: The IN token interrupt in Control Endpoint.."
newline
bitfld.long 0x00 2. "OUTTKIEN,Out Token Interrupt \n" "0: The OUT token interrupt in Control Endpoint..,1: The OUT token interrupt in Control Endpoint.."
bitfld.long 0x00 1. "SETUPPKIEN,Setup Packet Interrupt \n" "0: The SETUP packet interrupt in Control..,1: The SETUP packet interrupt in Control.."
newline
bitfld.long 0x00 0. "SETUPTKIEN,Setup Token Interrupt Enable Bit \n" "0: The SETUP token interrupt in Control Endpoint..,1: The SETUP token interrupt in Control Endpoint.."
group.long 0x34++0x03
line.long 0x00 "USBD_CEPINTSTS,Control-endpoint Interrupt Status"
bitfld.long 0x00 12. "BUFEMPTYIF,Buffer Empty Interrupt \nNote: Write 1 to clear this bit to 0" "0: The control-endpoint buffer is not empty,1: The control-endpoint buffer is empty"
bitfld.long 0x00 11. "BUFFULLIF,Buffer Full Interrupt \nNote: Write 1 to clear this bit to 0" "0: The control-endpoint buffer is not full,1: The control-endpoint buffer is full"
newline
bitfld.long 0x00 10. "STSDONEIF,Status Completion Interrupt \nNote: Write 1 to clear this bit to 0" "0: No USB transaction has completed successfully,1: The status stage of a USB transaction has.."
bitfld.long 0x00 9. "ERRIF,USB Error Interrupt\nNote: Write 1 to clear this bit to 0" "0: No error had occurred during the transaction,1: An error had occurred during the transaction"
newline
bitfld.long 0x00 8. "STALLIF,STALL Sent Interrupt \nNote: Write 1 to clear this bit to 0" "0: No stall-token is sent in response to an..,1: A stall-token is sent in response to an.."
bitfld.long 0x00 7. "NAKIF,NAK Sent Interrupt \nNote: Write 1 to clear this bit to 0" "0: No NAK-token is sent in response to an IN/OUT..,1: A NAK-token is sent in response to an IN/OUT.."
newline
bitfld.long 0x00 6. "RXPKIF,Data Packet Received Interrupt \nNote: Write 1 to clear this bit to 0" "0: No data packet is successfully received from..,1: A data packet is successfully received from.."
bitfld.long 0x00 5. "TXPKIF,Data Packet Transmitted Interrupt \nNote: Write 1 to clear this bit to 0" "0: No data packet is successfully transmitted to..,1: A data packet is successfully transmitted to.."
newline
bitfld.long 0x00 4. "PINGIF,Ping Token Interrupt \nNote: Write 1 to clear this bit to 0" "0: The control-endpoint does not receive a ping..,1: The control-endpoint receives a ping token.."
bitfld.long 0x00 3. "INTKIF,in Token Interrupt \n Write 1 to clear this bit to 0" "0: The control-endpoint does not receive an IN..,1: The control-endpoint receives an IN token.."
newline
bitfld.long 0x00 2. "OUTTKIF,Out Token Interrupt \nNote: Write 1 to clear this bit to 0" "0: The control-endpoint does not receive an OUT..,1: The control-endpoint receives an OUT token.."
bitfld.long 0x00 1. "SETUPPKIF,Setup Packet Interrupt \nThis bit must be cleared (by writing 1) before the next setup packet can be received" "0: No setup packet has been received from the host,1: A setup packet has been received from the host"
newline
bitfld.long 0x00 0. "SETUPTKIF,Setup Token Interrupt \nNote: Write 1 to clear this bit to 0" "0: No setup token is received,1: A setup token is received"
group.long 0x38++0x03
line.long 0x00 "USBD_CEPTXCNT,Control-endpoint In-transfer Data Count"
hexmask.long.byte 0x00 0.--7. 1. "TXCNT,In-transfer Data Count\nThere is no mode selection for the control endpoint (but it operates like manual mode).The local-CPU has to fill the control-endpoint buffer with the data to be sent for an in-token and to write the count of bytes in this.."
rgroup.long 0x3C++0x03
line.long 0x00 "USBD_CEPRXCNT,Control-endpoint Out-transfer Data Count"
hexmask.long.byte 0x00 0.--7. 1. "RXCNT,Out-transfer Data Count \nThe USB device controller maintains the count of the data received in case of an out transfer during the control transfer"
rgroup.long 0x40++0x03
line.long 0x00 "USBD_CEPDATCNT,Control-endpoint Data Count"
hexmask.long.word 0x00 0.--15. 1. "DATCNT,Control-endpoint Data Count \nThe USB device controller maintains the count of the data of control-endpoint"
rgroup.long 0x44++0x03
line.long 0x00 "USBD_SETUP1_0,Setup1 Setup0 Bytes"
hexmask.long.byte 0x00 8.--15. 1. "SETUP1,Setup Byte 1[15:8]\nThis register provides byte 1 of the last setup packet received"
hexmask.long.byte 0x00 0.--7. 1. "SETUP0,Setup Byte 0[7:0]\nThis register provides byte 0 of the last setup packet received"
rgroup.long 0x48++0x03
line.long 0x00 "USBD_SETUP3_2,Setup3 Setup2 Bytes"
hexmask.long.byte 0x00 8.--15. 1. "SETUP3,Setup Byte 3 [15:8]\nThis register provides byte 3 of the last setup packet received"
hexmask.long.byte 0x00 0.--7. 1. "SETUP2,Setup Byte 2 [7:0]\nThis register provides byte 2 of the last setup packet received"
rgroup.long 0x4C++0x03
line.long 0x00 "USBD_SETUP5_4,Setup5 Setup4 Bytes"
hexmask.long.byte 0x00 8.--15. 1. "SETUP5,Setup Byte 5[15:8] \nThis register provides byte 5 of the last setup packet received"
hexmask.long.byte 0x00 0.--7. 1. "SETUP4,Setup Byte 4[7:0] \nThis register provides byte 4 of the last setup packet received"
rgroup.long 0x50++0x03
line.long 0x00 "USBD_SETUP7_6,Setup7 Setup6 Bytes"
hexmask.long.byte 0x00 8.--15. 1. "SETUP7,Setup Byte 7[15:8] \nThis register provides byte 7 of the last setup packet received"
hexmask.long.byte 0x00 0.--7. 1. "SETUP6,Setup Byte 6[7:0] \nThis register provides byte 6 of the last setup packet received"
group.long 0x54++0x03
line.long 0x00 "USBD_CEPBUFSTART,Control Endpoint RAM Start Address Register"
hexmask.long.word 0x00 0.--11. 1. "SADDR,Control-endpoint Start Address\nThis is the start-address of the RAM space allocated for the control-endpoint"
group.long 0x58++0x03
line.long 0x00 "USBD_CEPBUFEND,Control Endpoint RAM End Address Register"
hexmask.long.word 0x00 0.--11. 1. "EADDR,Control-endpoint End Address\nThis is the end-address of the RAM space allocated for the control-endpoint"
group.long 0x5C++0x03
line.long 0x00 "USBD_DMACTL,DMA Control Status Register"
bitfld.long 0x00 7. "DMARST,Reset DMA State Machine\n" "0: No reset the DMA state machine,1: Reset the DMA state machine"
bitfld.long 0x00 6. "SGEN,Scatter Gather Function Enable Bit\n" "0: Scatter gather function Disabled,1: Scatter gather function Enabled"
newline
bitfld.long 0x00 5. "DMAEN,DMA Enable Bit\n" "0: DMA function Disabled,1: DMA function Enabled"
bitfld.long 0x00 4. "DMARD,DMA Operation\n" "0: The operation is a DMA write (read from USB..,1: The operation is a DMA read (write to USB.."
newline
bitfld.long 0x00 0.--3. "EPNUM,DMA Endpoint Address Bits\nUsed to define the Endpoint Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x60++0x03
line.long 0x00 "USBD_DMACNT,DMA Count Register"
hexmask.long.tbyte 0x00 0.--19. 1. "DMACNT,DMA Transfer Count\nThe transfer count of the DMA operation to be performed is written to this register"
group.long 0x64++0x03
line.long 0x00 "USBD_EPADAT,Endpoint A Data Register"
hexmask.long 0x00 0.--31. 1. "EPDAT,Endpoint A~L Data Register \nEndpoint A~L data buffer for the buffer transaction (read or write).\n Only word or byte access are supported"
group.long 0x68++0x03
line.long 0x00 "USBD_EPAINTSTS,Endpoint A Interrupt Status Register"
bitfld.long 0x00 12. "SHORTRXIF,Bulk Out Short Packet Received\n Write 1 to clear this bit to 0" "0: No bulk out short packet is received,1: Received bulk out short packet (including.."
bitfld.long 0x00 11. "ERRIF,ERR Sent \n Write 1 to clear this bit to 0" "0: No any error in the transaction,1: There occurs any error in the transaction"
newline
bitfld.long 0x00 10. "NYETIF,NYET Sent \n Write 1 to clear this bit to 0" "0: The space available in the RAM is sufficient..,1: The space available in the RAM is not.."
bitfld.long 0x00 9. "STALLIF,USB STALL Sent\n Write 1 to clear this bit to 0" "0: The last USB packet could be accepted or..,1: The last USB packet could not be accepted or.."
newline
bitfld.long 0x00 8. "NAKIF,USB NAK Sent\n Write 1 to clear this bit to 0" "0: The last USB IN packet could be provided and..,1: The last USB IN packet could not be provided.."
bitfld.long 0x00 7. "PINGIF,PING Token Interrupt \n Write 1 to clear this bit to 0" "0: A Data PING token has not been received from..,1: A Data PING token has been received from the.."
newline
bitfld.long 0x00 6. "INTKIF,Data IN Token Interrupt \n Write 1 to clear this bit to 0" "0: No Data IN token has been received from the..,1: A Data IN token has been received from the host"
bitfld.long 0x00 5. "OUTTKIF,Data OUT Token Interrupt\nNote: Write 1 to clear this bit to 0" "0: A Data OUT token has not been received from..,1: A Data OUT token has been received from the.."
newline
bitfld.long 0x00 4. "RXPKIF,Data Packet Received Interrupt\nNote: Write 1 to clear this bit to 0" "0: No data packet is received from the host by..,1: A data packet is received from the host by.."
bitfld.long 0x00 3. "TXPKIF,Data Packet Transmitted Interrupt \nNote: Write 1 to clear this bit to 0" "0: No data packet is transmitted from the..,1: A data packet is transmitted from the.."
newline
bitfld.long 0x00 2. "SHORTTXIF,Short Packet Transferred Interrupt \n Note: Write 1 to clear this bit to 0" "0: The length of the last packet was not less..,1: The length of the last packet was less than.."
bitfld.long 0x00 1. "BUFEMPTYIF,Buffer Empty\nFor an IN endpoint a buffer is available to the local side for writing up to FIFO full of bytes" "0: The endpoint buffer is not empty.\nThe..,1: The endpoint buffer is empty.\nThe currently.."
newline
bitfld.long 0x00 0. "BUFFULLIF,Buffer Full \nFor an IN endpoint the currently selected buffer is full or no buffer is available to the local side for writing (no space to write)" "0: The endpoint packet buffer is not full,1: The endpoint packet buffer is full"
group.long 0x6C++0x03
line.long 0x00 "USBD_EPAINTEN,Endpoint A Interrupt Enable Register"
bitfld.long 0x00 12. "SHORTRXIEN,Bulk Out Short Packet Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.\n" "0: Bulk out interrupt Disabled,1: Bulk out interrupt Enabled"
bitfld.long 0x00 11. "ERRIEN,ERR Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.\n" "0: Error event interrupt Disabled,1: Error event interrupt Enabled"
newline
bitfld.long 0x00 10. "NYETIEN,NYET Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.\n" "0: NYET condition interrupt Disabled,1: NYET condition interrupt Enabled"
bitfld.long 0x00 9. "STALLIEN,USB STALL Sent Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a stall token is sent to the host.\n" "0: STALL token interrupt Disabled,1: STALL token interrupt Enabled"
newline
bitfld.long 0x00 8. "NAKIEN,USB NAK Sent Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a NAK token is sent to the host.\n" "0: NAK token interrupt Disabled,1: NAK token interrupt Enabled"
bitfld.long 0x00 7. "PINGIEN,PING Token Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a PING token has been received from the host.\n" "0: PING token interrupt Disabled,1: PING token interrupt Enabled"
newline
bitfld.long 0x00 6. "INTKIEN,Data IN Token Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set when a Data IN token has been received from the host.\n" "0: Data IN token interrupt Disabled,1: Data IN token interrupt Enabled"
bitfld.long 0x00 5. "OUTTKIEN,Data OUT Token Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a Data OUT token has been received from the host.\n" "0: Data OUT token interrupt Disabled,1: Data OUT token interrupt Enabled"
newline
bitfld.long 0x00 4. "RXPKIEN,Data Packet Received Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a data packet has been transmitted to the host.\n" "0: Data packet has been transmitted to the host..,1: Data packet has been transmitted to the host.."
bitfld.long 0x00 3. "TXPKIEN,Data Packet Transmitted Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a data packet has been received from the host.\n" "0: Data packet has been received from the host..,1: Data packet has been received from the host.."
newline
bitfld.long 0x00 2. "SHORTTXIEN,Short Packet Transferred Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.\n" "0: Short data packet interrupt Disabled,1: Short data packet interrupt Enabled"
bitfld.long 0x00 1. "BUFEMPTYIEN,Buffer Empty Interrupt\nWhen set this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.\n" "0: Buffer empty interrupt Disabled,1: Buffer empty interrupt Enabled"
newline
bitfld.long 0x00 0. "BUFFULLIEN,Buffer Full Interrupt \nWhen set this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.\n" "0: Buffer full interrupt Disabled,1: Buffer full interrupt Enabled"
rgroup.long 0x70++0x03
line.long 0x00 "USBD_EPADATCNT,Endpoint A Data Available Count Register"
hexmask.long.word 0x00 16.--30. 1. "DMALOOP,DMA Loop\nThis register is the remaining DMA loop to complete"
hexmask.long.word 0x00 0.--15. 1. "DATCNT,Data Count\nFor an IN endpoint (EPDIR(USBD_EPxCFG[3] is high.) this register returns the number of valid bytes in the IN endpoint packet buffer.\nFor an OUT endpoint (EPDIR(USBD_EPxCFG[3] is low.) this register returns the number of received.."
group.long 0x74++0x03
line.long 0x00 "USBD_EPARSPCTL,Endpoint A Response Control Register"
bitfld.long 0x00 7. "DISBUF,Buffer Disable Bit\nThis bit is used to receive unknown size OUT short packet" "0: Buffer Not Disabled when Bulk-OUT short..,1: Buffer Disabled when Bulk-OUT short packet is.."
bitfld.long 0x00 6. "SHORTTXEN,Short Packet Transfer Enable Bit\nThis bit is applicable only in case of Auto-Validate Method" "0: Not validate any remaining data in the buffer..,1: Validate any remaining data in the buffer.."
newline
bitfld.long 0x00 5. "ZEROLEN,Zero Length\nThis bit is used to send a zero-length packet response to an IN-token" "0: A zero packet is not sent to the host on..,1: A zero packet is sent to the host on.."
bitfld.long 0x00 4. "HALT,Endpoint Halt \nThis bit is used to send a STALL handshake as response to the token from the host" "0: Do not send a STALL handshake as response to..,1: Send a STALL handshake as response to the.."
newline
bitfld.long 0x00 3. "TOGGLE,Endpoint Toggle \nThis bit is used to clear the endpoint data toggle bit" "0: Do not clear the endpoint data toggle bit,1: Clear the endpoint data toggle bit"
bitfld.long 0x00 1.--2. "MODE,Mode Control\nThe two bits determine the operation mode of the in-endpoint" "0: Auto-Validate Mode,1: Manual-Validate Mode,2: Fly Mode,3: Reserved"
newline
bitfld.long 0x00 0. "FLUSH,Buffer Flush \nWriting 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared" "0: The packet buffer is not flushed,1: The packet buffer is flushed by user"
group.long 0x78++0x03
line.long 0x00 "USBD_EPAMPS,Endpoint A Maximum Packet Size Register"
hexmask.long.word 0x00 0.--10. 1. "EPMPS,Endpoint Maximum Packet Size \nThis field determines the Maximum Packet Size of the Endpoint"
group.long 0x7C++0x03
line.long 0x00 "USBD_EPATXCNT,Endpoint A Transfer Count Register"
hexmask.long.word 0x00 0.--10. 1. "TXCNT,Endpoint Transfer Count\nFor IN endpoints this field determines the total number of bytes to be sent to the host in case of manual validation method.\nFor OUT endpoints this field has no effect"
group.long 0x80++0x03
line.long 0x00 "USBD_EPACFG,Endpoint A Configuration Register"
bitfld.long 0x00 4.--7. "EPNUM,Endpoint Number\nThis field selects the number of the endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3. "EPDIR,Endpoint Direction\n A maximum of one OUT and IN endpoint is allowed for each endpoint number" "0: out-endpoint (Host OUT to Device),1: in-endpoint (Host IN to Device)"
newline
bitfld.long 0x00 1.--2. "EPTYPE,Endpoint Type\nThis field selects the type of this endpoint" "0: Reserved,1: Bulk,2: Interrupt,3: Isochronous"
bitfld.long 0x00 0. "EPEN,Endpoint Valid\nWhen set this bit enables this endpoint" "0: The endpoint Disabled,1: The endpoint Enabled"
group.long 0x84++0x03
line.long 0x00 "USBD_EPABUFSTART,Endpoint A RAM Start Address Register"
hexmask.long.word 0x00 0.--11. 1. "SADDR,Endpoint Start Address\nThis is the start-address of the RAM space allocated for the endpoint A~L"
group.long 0x88++0x03
line.long 0x00 "USBD_EPABUFEND,Endpoint A RAM End Address Register"
hexmask.long.word 0x00 0.--11. 1. "EADDR,Endpoint End Address\nThis is the end-address of the RAM space allocated for the endpoint A~L"
group.long 0x8C++0x03
line.long 0x00 "USBD_EPBDAT,Endpoint B Data Register"
hexmask.long 0x00 0.--31. 1. "EPDAT,Endpoint A~L Data Register \nEndpoint A~L data buffer for the buffer transaction (read or write).\n Only word or byte access are supported"
group.long 0x90++0x03
line.long 0x00 "USBD_EPBINTSTS,Endpoint B Interrupt Status Register"
bitfld.long 0x00 12. "SHORTRXIF,Bulk Out Short Packet Received\n Write 1 to clear this bit to 0" "0: No bulk out short packet is received,1: Received bulk out short packet (including.."
bitfld.long 0x00 11. "ERRIF,ERR Sent \n Write 1 to clear this bit to 0" "0: No any error in the transaction,1: There occurs any error in the transaction"
newline
bitfld.long 0x00 10. "NYETIF,NYET Sent \n Write 1 to clear this bit to 0" "0: The space available in the RAM is sufficient..,1: The space available in the RAM is not.."
bitfld.long 0x00 9. "STALLIF,USB STALL Sent\n Write 1 to clear this bit to 0" "0: The last USB packet could be accepted or..,1: The last USB packet could not be accepted or.."
newline
bitfld.long 0x00 8. "NAKIF,USB NAK Sent\n Write 1 to clear this bit to 0" "0: The last USB IN packet could be provided and..,1: The last USB IN packet could not be provided.."
bitfld.long 0x00 7. "PINGIF,PING Token Interrupt \n Write 1 to clear this bit to 0" "0: A Data PING token has not been received from..,1: A Data PING token has been received from the.."
newline
bitfld.long 0x00 6. "INTKIF,Data IN Token Interrupt \n Write 1 to clear this bit to 0" "0: No Data IN token has been received from the..,1: A Data IN token has been received from the host"
bitfld.long 0x00 5. "OUTTKIF,Data OUT Token Interrupt\nNote: Write 1 to clear this bit to 0" "0: A Data OUT token has not been received from..,1: A Data OUT token has been received from the.."
newline
bitfld.long 0x00 4. "RXPKIF,Data Packet Received Interrupt\nNote: Write 1 to clear this bit to 0" "0: No data packet is received from the host by..,1: A data packet is received from the host by.."
bitfld.long 0x00 3. "TXPKIF,Data Packet Transmitted Interrupt \nNote: Write 1 to clear this bit to 0" "0: No data packet is transmitted from the..,1: A data packet is transmitted from the.."
newline
bitfld.long 0x00 2. "SHORTTXIF,Short Packet Transferred Interrupt \n Note: Write 1 to clear this bit to 0" "0: The length of the last packet was not less..,1: The length of the last packet was less than.."
bitfld.long 0x00 1. "BUFEMPTYIF,Buffer Empty\nFor an IN endpoint a buffer is available to the local side for writing up to FIFO full of bytes" "0: The endpoint buffer is not empty.\nThe..,1: The endpoint buffer is empty.\nThe currently.."
newline
bitfld.long 0x00 0. "BUFFULLIF,Buffer Full \nFor an IN endpoint the currently selected buffer is full or no buffer is available to the local side for writing (no space to write)" "0: The endpoint packet buffer is not full,1: The endpoint packet buffer is full"
group.long 0x94++0x03
line.long 0x00 "USBD_EPBINTEN,Endpoint B Interrupt Enable Register"
bitfld.long 0x00 12. "SHORTRXIEN,Bulk Out Short Packet Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.\n" "0: Bulk out interrupt Disabled,1: Bulk out interrupt Enabled"
bitfld.long 0x00 11. "ERRIEN,ERR Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.\n" "0: Error event interrupt Disabled,1: Error event interrupt Enabled"
newline
bitfld.long 0x00 10. "NYETIEN,NYET Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.\n" "0: NYET condition interrupt Disabled,1: NYET condition interrupt Enabled"
bitfld.long 0x00 9. "STALLIEN,USB STALL Sent Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a stall token is sent to the host.\n" "0: STALL token interrupt Disabled,1: STALL token interrupt Enabled"
newline
bitfld.long 0x00 8. "NAKIEN,USB NAK Sent Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a NAK token is sent to the host.\n" "0: NAK token interrupt Disabled,1: NAK token interrupt Enabled"
bitfld.long 0x00 7. "PINGIEN,PING Token Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a PING token has been received from the host.\n" "0: PING token interrupt Disabled,1: PING token interrupt Enabled"
newline
bitfld.long 0x00 6. "INTKIEN,Data IN Token Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set when a Data IN token has been received from the host.\n" "0: Data IN token interrupt Disabled,1: Data IN token interrupt Enabled"
bitfld.long 0x00 5. "OUTTKIEN,Data OUT Token Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a Data OUT token has been received from the host.\n" "0: Data OUT token interrupt Disabled,1: Data OUT token interrupt Enabled"
newline
bitfld.long 0x00 4. "RXPKIEN,Data Packet Received Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a data packet has been transmitted to the host.\n" "0: Data packet has been transmitted to the host..,1: Data packet has been transmitted to the host.."
bitfld.long 0x00 3. "TXPKIEN,Data Packet Transmitted Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a data packet has been received from the host.\n" "0: Data packet has been received from the host..,1: Data packet has been received from the host.."
newline
bitfld.long 0x00 2. "SHORTTXIEN,Short Packet Transferred Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.\n" "0: Short data packet interrupt Disabled,1: Short data packet interrupt Enabled"
bitfld.long 0x00 1. "BUFEMPTYIEN,Buffer Empty Interrupt\nWhen set this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.\n" "0: Buffer empty interrupt Disabled,1: Buffer empty interrupt Enabled"
newline
bitfld.long 0x00 0. "BUFFULLIEN,Buffer Full Interrupt \nWhen set this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.\n" "0: Buffer full interrupt Disabled,1: Buffer full interrupt Enabled"
group.long 0x98++0x03
line.long 0x00 "USBD_EPBDATCNT,Endpoint B Data Available Count Register"
hexmask.long.word 0x00 16.--30. 1. "DMALOOP,DMA Loop\nThis register is the remaining DMA loop to complete"
hexmask.long.word 0x00 0.--15. 1. "DATCNT,Data Count\nFor an IN endpoint (EPDIR(USBD_EPxCFG[3] is high.) this register returns the number of valid bytes in the IN endpoint packet buffer.\nFor an OUT endpoint (EPDIR(USBD_EPxCFG[3] is low.) this register returns the number of received.."
group.long 0x9C++0x03
line.long 0x00 "USBD_EPBRSPCTL,Endpoint B Response Control Register"
bitfld.long 0x00 7. "DISBUF,Buffer Disable Bit\nThis bit is used to receive unknown size OUT short packet" "0: Buffer Not Disabled when Bulk-OUT short..,1: Buffer Disabled when Bulk-OUT short packet is.."
bitfld.long 0x00 6. "SHORTTXEN,Short Packet Transfer Enable Bit\nThis bit is applicable only in case of Auto-Validate Method" "0: Not validate any remaining data in the buffer..,1: Validate any remaining data in the buffer.."
newline
bitfld.long 0x00 5. "ZEROLEN,Zero Length\nThis bit is used to send a zero-length packet response to an IN-token" "0: A zero packet is not sent to the host on..,1: A zero packet is sent to the host on.."
bitfld.long 0x00 4. "HALT,Endpoint Halt \nThis bit is used to send a STALL handshake as response to the token from the host" "0: Do not send a STALL handshake as response to..,1: Send a STALL handshake as response to the.."
newline
bitfld.long 0x00 3. "TOGGLE,Endpoint Toggle \nThis bit is used to clear the endpoint data toggle bit" "0: Do not clear the endpoint data toggle bit,1: Clear the endpoint data toggle bit"
bitfld.long 0x00 1.--2. "MODE,Mode Control\nThe two bits determine the operation mode of the in-endpoint" "0: Auto-Validate Mode,1: Manual-Validate Mode,2: Fly Mode,3: Reserved"
newline
bitfld.long 0x00 0. "FLUSH,Buffer Flush \nWriting 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared" "0: The packet buffer is not flushed,1: The packet buffer is flushed by user"
group.long 0xA0++0x03
line.long 0x00 "USBD_EPBMPS,Endpoint B Maximum Packet Size Register"
hexmask.long.word 0x00 0.--10. 1. "EPMPS,Endpoint Maximum Packet Size \nThis field determines the Maximum Packet Size of the Endpoint"
group.long 0xA4++0x03
line.long 0x00 "USBD_EPBTXCNT,Endpoint B Transfer Count Register"
hexmask.long.word 0x00 0.--10. 1. "TXCNT,Endpoint Transfer Count\nFor IN endpoints this field determines the total number of bytes to be sent to the host in case of manual validation method.\nFor OUT endpoints this field has no effect"
group.long 0xA8++0x03
line.long 0x00 "USBD_EPBCFG,Endpoint B Configuration Register"
bitfld.long 0x00 4.--7. "EPNUM,Endpoint Number\nThis field selects the number of the endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3. "EPDIR,Endpoint Direction\n A maximum of one OUT and IN endpoint is allowed for each endpoint number" "0: out-endpoint (Host OUT to Device),1: in-endpoint (Host IN to Device)"
newline
bitfld.long 0x00 1.--2. "EPTYPE,Endpoint Type\nThis field selects the type of this endpoint" "0: Reserved,1: Bulk,2: Interrupt,3: Isochronous"
bitfld.long 0x00 0. "EPEN,Endpoint Valid\nWhen set this bit enables this endpoint" "0: The endpoint Disabled,1: The endpoint Enabled"
group.long 0xAC++0x03
line.long 0x00 "USBD_EPBBUFSTART,Endpoint B RAM Start Address Register"
hexmask.long.word 0x00 0.--11. 1. "SADDR,Endpoint Start Address\nThis is the start-address of the RAM space allocated for the endpoint A~L"
group.long 0xB0++0x03
line.long 0x00 "USBD_EPBBUFEND,Endpoint B RAM End Address Register"
hexmask.long.word 0x00 0.--11. 1. "EADDR,Endpoint End Address\nThis is the end-address of the RAM space allocated for the endpoint A~L"
group.long 0xB4++0x03
line.long 0x00 "USBD_EPCDAT,Endpoint C Data Register"
hexmask.long 0x00 0.--31. 1. "EPDAT,Endpoint A~L Data Register \nEndpoint A~L data buffer for the buffer transaction (read or write).\n Only word or byte access are supported"
group.long 0xB8++0x03
line.long 0x00 "USBD_EPCINTSTS,Endpoint C Interrupt Status Register"
bitfld.long 0x00 12. "SHORTRXIF,Bulk Out Short Packet Received\n Write 1 to clear this bit to 0" "0: No bulk out short packet is received,1: Received bulk out short packet (including.."
bitfld.long 0x00 11. "ERRIF,ERR Sent \n Write 1 to clear this bit to 0" "0: No any error in the transaction,1: There occurs any error in the transaction"
newline
bitfld.long 0x00 10. "NYETIF,NYET Sent \n Write 1 to clear this bit to 0" "0: The space available in the RAM is sufficient..,1: The space available in the RAM is not.."
bitfld.long 0x00 9. "STALLIF,USB STALL Sent\n Write 1 to clear this bit to 0" "0: The last USB packet could be accepted or..,1: The last USB packet could not be accepted or.."
newline
bitfld.long 0x00 8. "NAKIF,USB NAK Sent\n Write 1 to clear this bit to 0" "0: The last USB IN packet could be provided and..,1: The last USB IN packet could not be provided.."
bitfld.long 0x00 7. "PINGIF,PING Token Interrupt \n Write 1 to clear this bit to 0" "0: A Data PING token has not been received from..,1: A Data PING token has been received from the.."
newline
bitfld.long 0x00 6. "INTKIF,Data IN Token Interrupt \n Write 1 to clear this bit to 0" "0: No Data IN token has been received from the..,1: A Data IN token has been received from the host"
bitfld.long 0x00 5. "OUTTKIF,Data OUT Token Interrupt\nNote: Write 1 to clear this bit to 0" "0: A Data OUT token has not been received from..,1: A Data OUT token has been received from the.."
newline
bitfld.long 0x00 4. "RXPKIF,Data Packet Received Interrupt\nNote: Write 1 to clear this bit to 0" "0: No data packet is received from the host by..,1: A data packet is received from the host by.."
bitfld.long 0x00 3. "TXPKIF,Data Packet Transmitted Interrupt \nNote: Write 1 to clear this bit to 0" "0: No data packet is transmitted from the..,1: A data packet is transmitted from the.."
newline
bitfld.long 0x00 2. "SHORTTXIF,Short Packet Transferred Interrupt \n Note: Write 1 to clear this bit to 0" "0: The length of the last packet was not less..,1: The length of the last packet was less than.."
bitfld.long 0x00 1. "BUFEMPTYIF,Buffer Empty\nFor an IN endpoint a buffer is available to the local side for writing up to FIFO full of bytes" "0: The endpoint buffer is not empty.\nThe..,1: The endpoint buffer is empty.\nThe currently.."
newline
bitfld.long 0x00 0. "BUFFULLIF,Buffer Full \nFor an IN endpoint the currently selected buffer is full or no buffer is available to the local side for writing (no space to write)" "0: The endpoint packet buffer is not full,1: The endpoint packet buffer is full"
group.long 0xBC++0x03
line.long 0x00 "USBD_EPCINTEN,Endpoint C Interrupt Enable Register"
bitfld.long 0x00 12. "SHORTRXIEN,Bulk Out Short Packet Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.\n" "0: Bulk out interrupt Disabled,1: Bulk out interrupt Enabled"
bitfld.long 0x00 11. "ERRIEN,ERR Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.\n" "0: Error event interrupt Disabled,1: Error event interrupt Enabled"
newline
bitfld.long 0x00 10. "NYETIEN,NYET Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.\n" "0: NYET condition interrupt Disabled,1: NYET condition interrupt Enabled"
bitfld.long 0x00 9. "STALLIEN,USB STALL Sent Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a stall token is sent to the host.\n" "0: STALL token interrupt Disabled,1: STALL token interrupt Enabled"
newline
bitfld.long 0x00 8. "NAKIEN,USB NAK Sent Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a NAK token is sent to the host.\n" "0: NAK token interrupt Disabled,1: NAK token interrupt Enabled"
bitfld.long 0x00 7. "PINGIEN,PING Token Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a PING token has been received from the host.\n" "0: PING token interrupt Disabled,1: PING token interrupt Enabled"
newline
bitfld.long 0x00 6. "INTKIEN,Data IN Token Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set when a Data IN token has been received from the host.\n" "0: Data IN token interrupt Disabled,1: Data IN token interrupt Enabled"
bitfld.long 0x00 5. "OUTTKIEN,Data OUT Token Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a Data OUT token has been received from the host.\n" "0: Data OUT token interrupt Disabled,1: Data OUT token interrupt Enabled"
newline
bitfld.long 0x00 4. "RXPKIEN,Data Packet Received Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a data packet has been transmitted to the host.\n" "0: Data packet has been transmitted to the host..,1: Data packet has been transmitted to the host.."
bitfld.long 0x00 3. "TXPKIEN,Data Packet Transmitted Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a data packet has been received from the host.\n" "0: Data packet has been received from the host..,1: Data packet has been received from the host.."
newline
bitfld.long 0x00 2. "SHORTTXIEN,Short Packet Transferred Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.\n" "0: Short data packet interrupt Disabled,1: Short data packet interrupt Enabled"
bitfld.long 0x00 1. "BUFEMPTYIEN,Buffer Empty Interrupt\nWhen set this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.\n" "0: Buffer empty interrupt Disabled,1: Buffer empty interrupt Enabled"
newline
bitfld.long 0x00 0. "BUFFULLIEN,Buffer Full Interrupt \nWhen set this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.\n" "0: Buffer full interrupt Disabled,1: Buffer full interrupt Enabled"
group.long 0xC0++0x03
line.long 0x00 "USBD_EPCDATCNT,Endpoint C Data Available Count Register"
hexmask.long.word 0x00 16.--30. 1. "DMALOOP,DMA Loop\nThis register is the remaining DMA loop to complete"
hexmask.long.word 0x00 0.--15. 1. "DATCNT,Data Count\nFor an IN endpoint (EPDIR(USBD_EPxCFG[3] is high.) this register returns the number of valid bytes in the IN endpoint packet buffer.\nFor an OUT endpoint (EPDIR(USBD_EPxCFG[3] is low.) this register returns the number of received.."
group.long 0xC4++0x03
line.long 0x00 "USBD_EPCRSPCTL,Endpoint C Response Control Register"
bitfld.long 0x00 7. "DISBUF,Buffer Disable Bit\nThis bit is used to receive unknown size OUT short packet" "0: Buffer Not Disabled when Bulk-OUT short..,1: Buffer Disabled when Bulk-OUT short packet is.."
bitfld.long 0x00 6. "SHORTTXEN,Short Packet Transfer Enable Bit\nThis bit is applicable only in case of Auto-Validate Method" "0: Not validate any remaining data in the buffer..,1: Validate any remaining data in the buffer.."
newline
bitfld.long 0x00 5. "ZEROLEN,Zero Length\nThis bit is used to send a zero-length packet response to an IN-token" "0: A zero packet is not sent to the host on..,1: A zero packet is sent to the host on.."
bitfld.long 0x00 4. "HALT,Endpoint Halt \nThis bit is used to send a STALL handshake as response to the token from the host" "0: Do not send a STALL handshake as response to..,1: Send a STALL handshake as response to the.."
newline
bitfld.long 0x00 3. "TOGGLE,Endpoint Toggle \nThis bit is used to clear the endpoint data toggle bit" "0: Do not clear the endpoint data toggle bit,1: Clear the endpoint data toggle bit"
bitfld.long 0x00 1.--2. "MODE,Mode Control\nThe two bits determine the operation mode of the in-endpoint" "0: Auto-Validate Mode,1: Manual-Validate Mode,2: Fly Mode,3: Reserved"
newline
bitfld.long 0x00 0. "FLUSH,Buffer Flush \nWriting 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared" "0: The packet buffer is not flushed,1: The packet buffer is flushed by user"
group.long 0xC8++0x03
line.long 0x00 "USBD_EPCMPS,Endpoint C Maximum Packet Size Register"
hexmask.long.word 0x00 0.--10. 1. "EPMPS,Endpoint Maximum Packet Size \nThis field determines the Maximum Packet Size of the Endpoint"
group.long 0xCC++0x03
line.long 0x00 "USBD_EPCTXCNT,Endpoint C Transfer Count Register"
hexmask.long.word 0x00 0.--10. 1. "TXCNT,Endpoint Transfer Count\nFor IN endpoints this field determines the total number of bytes to be sent to the host in case of manual validation method.\nFor OUT endpoints this field has no effect"
group.long 0xD0++0x03
line.long 0x00 "USBD_EPCCFG,Endpoint C Configuration Register"
bitfld.long 0x00 4.--7. "EPNUM,Endpoint Number\nThis field selects the number of the endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3. "EPDIR,Endpoint Direction\n A maximum of one OUT and IN endpoint is allowed for each endpoint number" "0: out-endpoint (Host OUT to Device),1: in-endpoint (Host IN to Device)"
newline
bitfld.long 0x00 1.--2. "EPTYPE,Endpoint Type\nThis field selects the type of this endpoint" "0: Reserved,1: Bulk,2: Interrupt,3: Isochronous"
bitfld.long 0x00 0. "EPEN,Endpoint Valid\nWhen set this bit enables this endpoint" "0: The endpoint Disabled,1: The endpoint Enabled"
group.long 0xD4++0x03
line.long 0x00 "USBD_EPCBUFSTART,Endpoint C RAM Start Address Register"
hexmask.long.word 0x00 0.--11. 1. "SADDR,Endpoint Start Address\nThis is the start-address of the RAM space allocated for the endpoint A~L"
group.long 0xD8++0x03
line.long 0x00 "USBD_EPCBUFEND,Endpoint C RAM End Address Register"
hexmask.long.word 0x00 0.--11. 1. "EADDR,Endpoint End Address\nThis is the end-address of the RAM space allocated for the endpoint A~L"
group.long 0xDC++0x03
line.long 0x00 "USBD_EPDDAT,Endpoint D Data Register"
hexmask.long 0x00 0.--31. 1. "EPDAT,Endpoint A~L Data Register \nEndpoint A~L data buffer for the buffer transaction (read or write).\n Only word or byte access are supported"
group.long 0xE0++0x03
line.long 0x00 "USBD_EPDINTSTS,Endpoint D Interrupt Status Register"
bitfld.long 0x00 12. "SHORTRXIF,Bulk Out Short Packet Received\n Write 1 to clear this bit to 0" "0: No bulk out short packet is received,1: Received bulk out short packet (including.."
bitfld.long 0x00 11. "ERRIF,ERR Sent \n Write 1 to clear this bit to 0" "0: No any error in the transaction,1: There occurs any error in the transaction"
newline
bitfld.long 0x00 10. "NYETIF,NYET Sent \n Write 1 to clear this bit to 0" "0: The space available in the RAM is sufficient..,1: The space available in the RAM is not.."
bitfld.long 0x00 9. "STALLIF,USB STALL Sent\n Write 1 to clear this bit to 0" "0: The last USB packet could be accepted or..,1: The last USB packet could not be accepted or.."
newline
bitfld.long 0x00 8. "NAKIF,USB NAK Sent\n Write 1 to clear this bit to 0" "0: The last USB IN packet could be provided and..,1: The last USB IN packet could not be provided.."
bitfld.long 0x00 7. "PINGIF,PING Token Interrupt \n Write 1 to clear this bit to 0" "0: A Data PING token has not been received from..,1: A Data PING token has been received from the.."
newline
bitfld.long 0x00 6. "INTKIF,Data IN Token Interrupt \n Write 1 to clear this bit to 0" "0: No Data IN token has been received from the..,1: A Data IN token has been received from the host"
bitfld.long 0x00 5. "OUTTKIF,Data OUT Token Interrupt\nNote: Write 1 to clear this bit to 0" "0: A Data OUT token has not been received from..,1: A Data OUT token has been received from the.."
newline
bitfld.long 0x00 4. "RXPKIF,Data Packet Received Interrupt\nNote: Write 1 to clear this bit to 0" "0: No data packet is received from the host by..,1: A data packet is received from the host by.."
bitfld.long 0x00 3. "TXPKIF,Data Packet Transmitted Interrupt \nNote: Write 1 to clear this bit to 0" "0: No data packet is transmitted from the..,1: A data packet is transmitted from the.."
newline
bitfld.long 0x00 2. "SHORTTXIF,Short Packet Transferred Interrupt \n Note: Write 1 to clear this bit to 0" "0: The length of the last packet was not less..,1: The length of the last packet was less than.."
bitfld.long 0x00 1. "BUFEMPTYIF,Buffer Empty\nFor an IN endpoint a buffer is available to the local side for writing up to FIFO full of bytes" "0: The endpoint buffer is not empty.\nThe..,1: The endpoint buffer is empty.\nThe currently.."
newline
bitfld.long 0x00 0. "BUFFULLIF,Buffer Full \nFor an IN endpoint the currently selected buffer is full or no buffer is available to the local side for writing (no space to write)" "0: The endpoint packet buffer is not full,1: The endpoint packet buffer is full"
group.long 0xE4++0x03
line.long 0x00 "USBD_EPDINTEN,Endpoint D Interrupt Enable Register"
bitfld.long 0x00 12. "SHORTRXIEN,Bulk Out Short Packet Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.\n" "0: Bulk out interrupt Disabled,1: Bulk out interrupt Enabled"
bitfld.long 0x00 11. "ERRIEN,ERR Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.\n" "0: Error event interrupt Disabled,1: Error event interrupt Enabled"
newline
bitfld.long 0x00 10. "NYETIEN,NYET Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.\n" "0: NYET condition interrupt Disabled,1: NYET condition interrupt Enabled"
bitfld.long 0x00 9. "STALLIEN,USB STALL Sent Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a stall token is sent to the host.\n" "0: STALL token interrupt Disabled,1: STALL token interrupt Enabled"
newline
bitfld.long 0x00 8. "NAKIEN,USB NAK Sent Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a NAK token is sent to the host.\n" "0: NAK token interrupt Disabled,1: NAK token interrupt Enabled"
bitfld.long 0x00 7. "PINGIEN,PING Token Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a PING token has been received from the host.\n" "0: PING token interrupt Disabled,1: PING token interrupt Enabled"
newline
bitfld.long 0x00 6. "INTKIEN,Data IN Token Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set when a Data IN token has been received from the host.\n" "0: Data IN token interrupt Disabled,1: Data IN token interrupt Enabled"
bitfld.long 0x00 5. "OUTTKIEN,Data OUT Token Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a Data OUT token has been received from the host.\n" "0: Data OUT token interrupt Disabled,1: Data OUT token interrupt Enabled"
newline
bitfld.long 0x00 4. "RXPKIEN,Data Packet Received Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a data packet has been transmitted to the host.\n" "0: Data packet has been transmitted to the host..,1: Data packet has been transmitted to the host.."
bitfld.long 0x00 3. "TXPKIEN,Data Packet Transmitted Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a data packet has been received from the host.\n" "0: Data packet has been received from the host..,1: Data packet has been received from the host.."
newline
bitfld.long 0x00 2. "SHORTTXIEN,Short Packet Transferred Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.\n" "0: Short data packet interrupt Disabled,1: Short data packet interrupt Enabled"
bitfld.long 0x00 1. "BUFEMPTYIEN,Buffer Empty Interrupt\nWhen set this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.\n" "0: Buffer empty interrupt Disabled,1: Buffer empty interrupt Enabled"
newline
bitfld.long 0x00 0. "BUFFULLIEN,Buffer Full Interrupt \nWhen set this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.\n" "0: Buffer full interrupt Disabled,1: Buffer full interrupt Enabled"
group.long 0xE8++0x03
line.long 0x00 "USBD_EPDDATCNT,Endpoint D Data Available Count Register"
hexmask.long.word 0x00 16.--30. 1. "DMALOOP,DMA Loop\nThis register is the remaining DMA loop to complete"
hexmask.long.word 0x00 0.--15. 1. "DATCNT,Data Count\nFor an IN endpoint (EPDIR(USBD_EPxCFG[3] is high.) this register returns the number of valid bytes in the IN endpoint packet buffer.\nFor an OUT endpoint (EPDIR(USBD_EPxCFG[3] is low.) this register returns the number of received.."
group.long 0xEC++0x03
line.long 0x00 "USBD_EPDRSPCTL,Endpoint D Response Control Register"
bitfld.long 0x00 7. "DISBUF,Buffer Disable Bit\nThis bit is used to receive unknown size OUT short packet" "0: Buffer Not Disabled when Bulk-OUT short..,1: Buffer Disabled when Bulk-OUT short packet is.."
bitfld.long 0x00 6. "SHORTTXEN,Short Packet Transfer Enable Bit\nThis bit is applicable only in case of Auto-Validate Method" "0: Not validate any remaining data in the buffer..,1: Validate any remaining data in the buffer.."
newline
bitfld.long 0x00 5. "ZEROLEN,Zero Length\nThis bit is used to send a zero-length packet response to an IN-token" "0: A zero packet is not sent to the host on..,1: A zero packet is sent to the host on.."
bitfld.long 0x00 4. "HALT,Endpoint Halt \nThis bit is used to send a STALL handshake as response to the token from the host" "0: Do not send a STALL handshake as response to..,1: Send a STALL handshake as response to the.."
newline
bitfld.long 0x00 3. "TOGGLE,Endpoint Toggle \nThis bit is used to clear the endpoint data toggle bit" "0: Do not clear the endpoint data toggle bit,1: Clear the endpoint data toggle bit"
bitfld.long 0x00 1.--2. "MODE,Mode Control\nThe two bits determine the operation mode of the in-endpoint" "0: Auto-Validate Mode,1: Manual-Validate Mode,2: Fly Mode,3: Reserved"
newline
bitfld.long 0x00 0. "FLUSH,Buffer Flush \nWriting 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared" "0: The packet buffer is not flushed,1: The packet buffer is flushed by user"
group.long 0xF0++0x03
line.long 0x00 "USBD_EPDMPS,Endpoint D Maximum Packet Size Register"
hexmask.long.word 0x00 0.--10. 1. "EPMPS,Endpoint Maximum Packet Size \nThis field determines the Maximum Packet Size of the Endpoint"
group.long 0xF4++0x03
line.long 0x00 "USBD_EPDTXCNT,Endpoint D Transfer Count Register"
hexmask.long.word 0x00 0.--10. 1. "TXCNT,Endpoint Transfer Count\nFor IN endpoints this field determines the total number of bytes to be sent to the host in case of manual validation method.\nFor OUT endpoints this field has no effect"
group.long 0xF8++0x03
line.long 0x00 "USBD_EPDCFG,Endpoint D Configuration Register"
bitfld.long 0x00 4.--7. "EPNUM,Endpoint Number\nThis field selects the number of the endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3. "EPDIR,Endpoint Direction\n A maximum of one OUT and IN endpoint is allowed for each endpoint number" "0: out-endpoint (Host OUT to Device),1: in-endpoint (Host IN to Device)"
newline
bitfld.long 0x00 1.--2. "EPTYPE,Endpoint Type\nThis field selects the type of this endpoint" "0: Reserved,1: Bulk,2: Interrupt,3: Isochronous"
bitfld.long 0x00 0. "EPEN,Endpoint Valid\nWhen set this bit enables this endpoint" "0: The endpoint Disabled,1: The endpoint Enabled"
group.long 0xFC++0x03
line.long 0x00 "USBD_EPDBUFSTART,Endpoint D RAM Start Address Register"
hexmask.long.word 0x00 0.--11. 1. "SADDR,Endpoint Start Address\nThis is the start-address of the RAM space allocated for the endpoint A~L"
group.long 0x100++0x03
line.long 0x00 "USBD_EPDBUFEND,Endpoint D RAM End Address Register"
hexmask.long.word 0x00 0.--11. 1. "EADDR,Endpoint End Address\nThis is the end-address of the RAM space allocated for the endpoint A~L"
group.long 0x104++0x03
line.long 0x00 "USBD_EPEDAT,Endpoint E Data Register"
hexmask.long 0x00 0.--31. 1. "EPDAT,Endpoint A~L Data Register \nEndpoint A~L data buffer for the buffer transaction (read or write).\n Only word or byte access are supported"
group.long 0x108++0x03
line.long 0x00 "USBD_EPEINTSTS,Endpoint E Interrupt Status Register"
bitfld.long 0x00 12. "SHORTRXIF,Bulk Out Short Packet Received\n Write 1 to clear this bit to 0" "0: No bulk out short packet is received,1: Received bulk out short packet (including.."
bitfld.long 0x00 11. "ERRIF,ERR Sent \n Write 1 to clear this bit to 0" "0: No any error in the transaction,1: There occurs any error in the transaction"
newline
bitfld.long 0x00 10. "NYETIF,NYET Sent \n Write 1 to clear this bit to 0" "0: The space available in the RAM is sufficient..,1: The space available in the RAM is not.."
bitfld.long 0x00 9. "STALLIF,USB STALL Sent\n Write 1 to clear this bit to 0" "0: The last USB packet could be accepted or..,1: The last USB packet could not be accepted or.."
newline
bitfld.long 0x00 8. "NAKIF,USB NAK Sent\n Write 1 to clear this bit to 0" "0: The last USB IN packet could be provided and..,1: The last USB IN packet could not be provided.."
bitfld.long 0x00 7. "PINGIF,PING Token Interrupt \n Write 1 to clear this bit to 0" "0: A Data PING token has not been received from..,1: A Data PING token has been received from the.."
newline
bitfld.long 0x00 6. "INTKIF,Data IN Token Interrupt \n Write 1 to clear this bit to 0" "0: No Data IN token has been received from the..,1: A Data IN token has been received from the host"
bitfld.long 0x00 5. "OUTTKIF,Data OUT Token Interrupt\nNote: Write 1 to clear this bit to 0" "0: A Data OUT token has not been received from..,1: A Data OUT token has been received from the.."
newline
bitfld.long 0x00 4. "RXPKIF,Data Packet Received Interrupt\nNote: Write 1 to clear this bit to 0" "0: No data packet is received from the host by..,1: A data packet is received from the host by.."
bitfld.long 0x00 3. "TXPKIF,Data Packet Transmitted Interrupt \nNote: Write 1 to clear this bit to 0" "0: No data packet is transmitted from the..,1: A data packet is transmitted from the.."
newline
bitfld.long 0x00 2. "SHORTTXIF,Short Packet Transferred Interrupt \n Note: Write 1 to clear this bit to 0" "0: The length of the last packet was not less..,1: The length of the last packet was less than.."
bitfld.long 0x00 1. "BUFEMPTYIF,Buffer Empty\nFor an IN endpoint a buffer is available to the local side for writing up to FIFO full of bytes" "0: The endpoint buffer is not empty.\nThe..,1: The endpoint buffer is empty.\nThe currently.."
newline
bitfld.long 0x00 0. "BUFFULLIF,Buffer Full \nFor an IN endpoint the currently selected buffer is full or no buffer is available to the local side for writing (no space to write)" "0: The endpoint packet buffer is not full,1: The endpoint packet buffer is full"
group.long 0x10C++0x03
line.long 0x00 "USBD_EPEINTEN,Endpoint E Interrupt Enable Register"
bitfld.long 0x00 12. "SHORTRXIEN,Bulk Out Short Packet Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.\n" "0: Bulk out interrupt Disabled,1: Bulk out interrupt Enabled"
bitfld.long 0x00 11. "ERRIEN,ERR Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.\n" "0: Error event interrupt Disabled,1: Error event interrupt Enabled"
newline
bitfld.long 0x00 10. "NYETIEN,NYET Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.\n" "0: NYET condition interrupt Disabled,1: NYET condition interrupt Enabled"
bitfld.long 0x00 9. "STALLIEN,USB STALL Sent Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a stall token is sent to the host.\n" "0: STALL token interrupt Disabled,1: STALL token interrupt Enabled"
newline
bitfld.long 0x00 8. "NAKIEN,USB NAK Sent Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a NAK token is sent to the host.\n" "0: NAK token interrupt Disabled,1: NAK token interrupt Enabled"
bitfld.long 0x00 7. "PINGIEN,PING Token Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a PING token has been received from the host.\n" "0: PING token interrupt Disabled,1: PING token interrupt Enabled"
newline
bitfld.long 0x00 6. "INTKIEN,Data IN Token Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set when a Data IN token has been received from the host.\n" "0: Data IN token interrupt Disabled,1: Data IN token interrupt Enabled"
bitfld.long 0x00 5. "OUTTKIEN,Data OUT Token Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a Data OUT token has been received from the host.\n" "0: Data OUT token interrupt Disabled,1: Data OUT token interrupt Enabled"
newline
bitfld.long 0x00 4. "RXPKIEN,Data Packet Received Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a data packet has been transmitted to the host.\n" "0: Data packet has been transmitted to the host..,1: Data packet has been transmitted to the host.."
bitfld.long 0x00 3. "TXPKIEN,Data Packet Transmitted Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a data packet has been received from the host.\n" "0: Data packet has been received from the host..,1: Data packet has been received from the host.."
newline
bitfld.long 0x00 2. "SHORTTXIEN,Short Packet Transferred Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.\n" "0: Short data packet interrupt Disabled,1: Short data packet interrupt Enabled"
bitfld.long 0x00 1. "BUFEMPTYIEN,Buffer Empty Interrupt\nWhen set this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.\n" "0: Buffer empty interrupt Disabled,1: Buffer empty interrupt Enabled"
newline
bitfld.long 0x00 0. "BUFFULLIEN,Buffer Full Interrupt \nWhen set this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.\n" "0: Buffer full interrupt Disabled,1: Buffer full interrupt Enabled"
group.long 0x110++0x03
line.long 0x00 "USBD_EPEDATCNT,Endpoint E Data Available Count Register"
hexmask.long.word 0x00 16.--30. 1. "DMALOOP,DMA Loop\nThis register is the remaining DMA loop to complete"
hexmask.long.word 0x00 0.--15. 1. "DATCNT,Data Count\nFor an IN endpoint (EPDIR(USBD_EPxCFG[3] is high.) this register returns the number of valid bytes in the IN endpoint packet buffer.\nFor an OUT endpoint (EPDIR(USBD_EPxCFG[3] is low.) this register returns the number of received.."
group.long 0x114++0x03
line.long 0x00 "USBD_EPERSPCTL,Endpoint E Response Control Register"
bitfld.long 0x00 7. "DISBUF,Buffer Disable Bit\nThis bit is used to receive unknown size OUT short packet" "0: Buffer Not Disabled when Bulk-OUT short..,1: Buffer Disabled when Bulk-OUT short packet is.."
bitfld.long 0x00 6. "SHORTTXEN,Short Packet Transfer Enable Bit\nThis bit is applicable only in case of Auto-Validate Method" "0: Not validate any remaining data in the buffer..,1: Validate any remaining data in the buffer.."
newline
bitfld.long 0x00 5. "ZEROLEN,Zero Length\nThis bit is used to send a zero-length packet response to an IN-token" "0: A zero packet is not sent to the host on..,1: A zero packet is sent to the host on.."
bitfld.long 0x00 4. "HALT,Endpoint Halt \nThis bit is used to send a STALL handshake as response to the token from the host" "0: Do not send a STALL handshake as response to..,1: Send a STALL handshake as response to the.."
newline
bitfld.long 0x00 3. "TOGGLE,Endpoint Toggle \nThis bit is used to clear the endpoint data toggle bit" "0: Do not clear the endpoint data toggle bit,1: Clear the endpoint data toggle bit"
bitfld.long 0x00 1.--2. "MODE,Mode Control\nThe two bits determine the operation mode of the in-endpoint" "0: Auto-Validate Mode,1: Manual-Validate Mode,2: Fly Mode,3: Reserved"
newline
bitfld.long 0x00 0. "FLUSH,Buffer Flush \nWriting 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared" "0: The packet buffer is not flushed,1: The packet buffer is flushed by user"
group.long 0x118++0x03
line.long 0x00 "USBD_EPEMPS,Endpoint E Maximum Packet Size Register"
hexmask.long.word 0x00 0.--10. 1. "EPMPS,Endpoint Maximum Packet Size \nThis field determines the Maximum Packet Size of the Endpoint"
group.long 0x11C++0x03
line.long 0x00 "USBD_EPETXCNT,Endpoint E Transfer Count Register"
hexmask.long.word 0x00 0.--10. 1. "TXCNT,Endpoint Transfer Count\nFor IN endpoints this field determines the total number of bytes to be sent to the host in case of manual validation method.\nFor OUT endpoints this field has no effect"
group.long 0x120++0x03
line.long 0x00 "USBD_EPECFG,Endpoint E Configuration Register"
bitfld.long 0x00 4.--7. "EPNUM,Endpoint Number\nThis field selects the number of the endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3. "EPDIR,Endpoint Direction\n A maximum of one OUT and IN endpoint is allowed for each endpoint number" "0: out-endpoint (Host OUT to Device),1: in-endpoint (Host IN to Device)"
newline
bitfld.long 0x00 1.--2. "EPTYPE,Endpoint Type\nThis field selects the type of this endpoint" "0: Reserved,1: Bulk,2: Interrupt,3: Isochronous"
bitfld.long 0x00 0. "EPEN,Endpoint Valid\nWhen set this bit enables this endpoint" "0: The endpoint Disabled,1: The endpoint Enabled"
group.long 0x124++0x03
line.long 0x00 "USBD_EPEBUFSTART,Endpoint E RAM Start Address Register"
hexmask.long.word 0x00 0.--11. 1. "SADDR,Endpoint Start Address\nThis is the start-address of the RAM space allocated for the endpoint A~L"
group.long 0x128++0x03
line.long 0x00 "USBD_EPEBUFEND,Endpoint E RAM End Address Register"
hexmask.long.word 0x00 0.--11. 1. "EADDR,Endpoint End Address\nThis is the end-address of the RAM space allocated for the endpoint A~L"
group.long 0x12C++0x03
line.long 0x00 "USBD_EPFDAT,Endpoint F Data Register"
hexmask.long 0x00 0.--31. 1. "EPDAT,Endpoint A~L Data Register \nEndpoint A~L data buffer for the buffer transaction (read or write).\n Only word or byte access are supported"
group.long 0x130++0x03
line.long 0x00 "USBD_EPFINTSTS,Endpoint F Interrupt Status Register"
bitfld.long 0x00 12. "SHORTRXIF,Bulk Out Short Packet Received\n Write 1 to clear this bit to 0" "0: No bulk out short packet is received,1: Received bulk out short packet (including.."
bitfld.long 0x00 11. "ERRIF,ERR Sent \n Write 1 to clear this bit to 0" "0: No any error in the transaction,1: There occurs any error in the transaction"
newline
bitfld.long 0x00 10. "NYETIF,NYET Sent \n Write 1 to clear this bit to 0" "0: The space available in the RAM is sufficient..,1: The space available in the RAM is not.."
bitfld.long 0x00 9. "STALLIF,USB STALL Sent\n Write 1 to clear this bit to 0" "0: The last USB packet could be accepted or..,1: The last USB packet could not be accepted or.."
newline
bitfld.long 0x00 8. "NAKIF,USB NAK Sent\n Write 1 to clear this bit to 0" "0: The last USB IN packet could be provided and..,1: The last USB IN packet could not be provided.."
bitfld.long 0x00 7. "PINGIF,PING Token Interrupt \n Write 1 to clear this bit to 0" "0: A Data PING token has not been received from..,1: A Data PING token has been received from the.."
newline
bitfld.long 0x00 6. "INTKIF,Data IN Token Interrupt \n Write 1 to clear this bit to 0" "0: No Data IN token has been received from the..,1: A Data IN token has been received from the host"
bitfld.long 0x00 5. "OUTTKIF,Data OUT Token Interrupt\nNote: Write 1 to clear this bit to 0" "0: A Data OUT token has not been received from..,1: A Data OUT token has been received from the.."
newline
bitfld.long 0x00 4. "RXPKIF,Data Packet Received Interrupt\nNote: Write 1 to clear this bit to 0" "0: No data packet is received from the host by..,1: A data packet is received from the host by.."
bitfld.long 0x00 3. "TXPKIF,Data Packet Transmitted Interrupt \nNote: Write 1 to clear this bit to 0" "0: No data packet is transmitted from the..,1: A data packet is transmitted from the.."
newline
bitfld.long 0x00 2. "SHORTTXIF,Short Packet Transferred Interrupt \n Note: Write 1 to clear this bit to 0" "0: The length of the last packet was not less..,1: The length of the last packet was less than.."
bitfld.long 0x00 1. "BUFEMPTYIF,Buffer Empty\nFor an IN endpoint a buffer is available to the local side for writing up to FIFO full of bytes" "0: The endpoint buffer is not empty.\nThe..,1: The endpoint buffer is empty.\nThe currently.."
newline
bitfld.long 0x00 0. "BUFFULLIF,Buffer Full \nFor an IN endpoint the currently selected buffer is full or no buffer is available to the local side for writing (no space to write)" "0: The endpoint packet buffer is not full,1: The endpoint packet buffer is full"
group.long 0x134++0x03
line.long 0x00 "USBD_EPFINTEN,Endpoint F Interrupt Enable Register"
bitfld.long 0x00 12. "SHORTRXIEN,Bulk Out Short Packet Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.\n" "0: Bulk out interrupt Disabled,1: Bulk out interrupt Enabled"
bitfld.long 0x00 11. "ERRIEN,ERR Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.\n" "0: Error event interrupt Disabled,1: Error event interrupt Enabled"
newline
bitfld.long 0x00 10. "NYETIEN,NYET Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.\n" "0: NYET condition interrupt Disabled,1: NYET condition interrupt Enabled"
bitfld.long 0x00 9. "STALLIEN,USB STALL Sent Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a stall token is sent to the host.\n" "0: STALL token interrupt Disabled,1: STALL token interrupt Enabled"
newline
bitfld.long 0x00 8. "NAKIEN,USB NAK Sent Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a NAK token is sent to the host.\n" "0: NAK token interrupt Disabled,1: NAK token interrupt Enabled"
bitfld.long 0x00 7. "PINGIEN,PING Token Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a PING token has been received from the host.\n" "0: PING token interrupt Disabled,1: PING token interrupt Enabled"
newline
bitfld.long 0x00 6. "INTKIEN,Data IN Token Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set when a Data IN token has been received from the host.\n" "0: Data IN token interrupt Disabled,1: Data IN token interrupt Enabled"
bitfld.long 0x00 5. "OUTTKIEN,Data OUT Token Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a Data OUT token has been received from the host.\n" "0: Data OUT token interrupt Disabled,1: Data OUT token interrupt Enabled"
newline
bitfld.long 0x00 4. "RXPKIEN,Data Packet Received Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a data packet has been transmitted to the host.\n" "0: Data packet has been transmitted to the host..,1: Data packet has been transmitted to the host.."
bitfld.long 0x00 3. "TXPKIEN,Data Packet Transmitted Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a data packet has been received from the host.\n" "0: Data packet has been received from the host..,1: Data packet has been received from the host.."
newline
bitfld.long 0x00 2. "SHORTTXIEN,Short Packet Transferred Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.\n" "0: Short data packet interrupt Disabled,1: Short data packet interrupt Enabled"
bitfld.long 0x00 1. "BUFEMPTYIEN,Buffer Empty Interrupt\nWhen set this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.\n" "0: Buffer empty interrupt Disabled,1: Buffer empty interrupt Enabled"
newline
bitfld.long 0x00 0. "BUFFULLIEN,Buffer Full Interrupt \nWhen set this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.\n" "0: Buffer full interrupt Disabled,1: Buffer full interrupt Enabled"
group.long 0x138++0x03
line.long 0x00 "USBD_EPFDATCNT,Endpoint F Data Available Count Register"
hexmask.long.word 0x00 16.--30. 1. "DMALOOP,DMA Loop\nThis register is the remaining DMA loop to complete"
hexmask.long.word 0x00 0.--15. 1. "DATCNT,Data Count\nFor an IN endpoint (EPDIR(USBD_EPxCFG[3] is high.) this register returns the number of valid bytes in the IN endpoint packet buffer.\nFor an OUT endpoint (EPDIR(USBD_EPxCFG[3] is low.) this register returns the number of received.."
group.long 0x13C++0x03
line.long 0x00 "USBD_EPFRSPCTL,Endpoint F Response Control Register"
bitfld.long 0x00 7. "DISBUF,Buffer Disable Bit\nThis bit is used to receive unknown size OUT short packet" "0: Buffer Not Disabled when Bulk-OUT short..,1: Buffer Disabled when Bulk-OUT short packet is.."
bitfld.long 0x00 6. "SHORTTXEN,Short Packet Transfer Enable Bit\nThis bit is applicable only in case of Auto-Validate Method" "0: Not validate any remaining data in the buffer..,1: Validate any remaining data in the buffer.."
newline
bitfld.long 0x00 5. "ZEROLEN,Zero Length\nThis bit is used to send a zero-length packet response to an IN-token" "0: A zero packet is not sent to the host on..,1: A zero packet is sent to the host on.."
bitfld.long 0x00 4. "HALT,Endpoint Halt \nThis bit is used to send a STALL handshake as response to the token from the host" "0: Do not send a STALL handshake as response to..,1: Send a STALL handshake as response to the.."
newline
bitfld.long 0x00 3. "TOGGLE,Endpoint Toggle \nThis bit is used to clear the endpoint data toggle bit" "0: Do not clear the endpoint data toggle bit,1: Clear the endpoint data toggle bit"
bitfld.long 0x00 1.--2. "MODE,Mode Control\nThe two bits determine the operation mode of the in-endpoint" "0: Auto-Validate Mode,1: Manual-Validate Mode,2: Fly Mode,3: Reserved"
newline
bitfld.long 0x00 0. "FLUSH,Buffer Flush \nWriting 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared" "0: The packet buffer is not flushed,1: The packet buffer is flushed by user"
group.long 0x140++0x03
line.long 0x00 "USBD_EPFMPS,Endpoint F Maximum Packet Size Register"
hexmask.long.word 0x00 0.--10. 1. "EPMPS,Endpoint Maximum Packet Size \nThis field determines the Maximum Packet Size of the Endpoint"
group.long 0x144++0x03
line.long 0x00 "USBD_EPFTXCNT,Endpoint F Transfer Count Register"
hexmask.long.word 0x00 0.--10. 1. "TXCNT,Endpoint Transfer Count\nFor IN endpoints this field determines the total number of bytes to be sent to the host in case of manual validation method.\nFor OUT endpoints this field has no effect"
group.long 0x148++0x03
line.long 0x00 "USBD_EPFCFG,Endpoint F Configuration Register"
bitfld.long 0x00 4.--7. "EPNUM,Endpoint Number\nThis field selects the number of the endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3. "EPDIR,Endpoint Direction\n A maximum of one OUT and IN endpoint is allowed for each endpoint number" "0: out-endpoint (Host OUT to Device),1: in-endpoint (Host IN to Device)"
newline
bitfld.long 0x00 1.--2. "EPTYPE,Endpoint Type\nThis field selects the type of this endpoint" "0: Reserved,1: Bulk,2: Interrupt,3: Isochronous"
bitfld.long 0x00 0. "EPEN,Endpoint Valid\nWhen set this bit enables this endpoint" "0: The endpoint Disabled,1: The endpoint Enabled"
group.long 0x14C++0x03
line.long 0x00 "USBD_EPFBUFSTART,Endpoint F RAM Start Address Register"
hexmask.long.word 0x00 0.--11. 1. "SADDR,Endpoint Start Address\nThis is the start-address of the RAM space allocated for the endpoint A~L"
group.long 0x150++0x03
line.long 0x00 "USBD_EPFBUFEND,Endpoint F RAM End Address Register"
hexmask.long.word 0x00 0.--11. 1. "EADDR,Endpoint End Address\nThis is the end-address of the RAM space allocated for the endpoint A~L"
group.long 0x154++0x03
line.long 0x00 "USBD_EPGDAT,Endpoint G Data Register"
hexmask.long 0x00 0.--31. 1. "EPDAT,Endpoint A~L Data Register \nEndpoint A~L data buffer for the buffer transaction (read or write).\n Only word or byte access are supported"
group.long 0x158++0x03
line.long 0x00 "USBD_EPGINTSTS,Endpoint G Interrupt Status Register"
bitfld.long 0x00 12. "SHORTRXIF,Bulk Out Short Packet Received\n Write 1 to clear this bit to 0" "0: No bulk out short packet is received,1: Received bulk out short packet (including.."
bitfld.long 0x00 11. "ERRIF,ERR Sent \n Write 1 to clear this bit to 0" "0: No any error in the transaction,1: There occurs any error in the transaction"
newline
bitfld.long 0x00 10. "NYETIF,NYET Sent \n Write 1 to clear this bit to 0" "0: The space available in the RAM is sufficient..,1: The space available in the RAM is not.."
bitfld.long 0x00 9. "STALLIF,USB STALL Sent\n Write 1 to clear this bit to 0" "0: The last USB packet could be accepted or..,1: The last USB packet could not be accepted or.."
newline
bitfld.long 0x00 8. "NAKIF,USB NAK Sent\n Write 1 to clear this bit to 0" "0: The last USB IN packet could be provided and..,1: The last USB IN packet could not be provided.."
bitfld.long 0x00 7. "PINGIF,PING Token Interrupt \n Write 1 to clear this bit to 0" "0: A Data PING token has not been received from..,1: A Data PING token has been received from the.."
newline
bitfld.long 0x00 6. "INTKIF,Data IN Token Interrupt \n Write 1 to clear this bit to 0" "0: No Data IN token has been received from the..,1: A Data IN token has been received from the host"
bitfld.long 0x00 5. "OUTTKIF,Data OUT Token Interrupt\nNote: Write 1 to clear this bit to 0" "0: A Data OUT token has not been received from..,1: A Data OUT token has been received from the.."
newline
bitfld.long 0x00 4. "RXPKIF,Data Packet Received Interrupt\nNote: Write 1 to clear this bit to 0" "0: No data packet is received from the host by..,1: A data packet is received from the host by.."
bitfld.long 0x00 3. "TXPKIF,Data Packet Transmitted Interrupt \nNote: Write 1 to clear this bit to 0" "0: No data packet is transmitted from the..,1: A data packet is transmitted from the.."
newline
bitfld.long 0x00 2. "SHORTTXIF,Short Packet Transferred Interrupt \n Note: Write 1 to clear this bit to 0" "0: The length of the last packet was not less..,1: The length of the last packet was less than.."
bitfld.long 0x00 1. "BUFEMPTYIF,Buffer Empty\nFor an IN endpoint a buffer is available to the local side for writing up to FIFO full of bytes" "0: The endpoint buffer is not empty.\nThe..,1: The endpoint buffer is empty.\nThe currently.."
newline
bitfld.long 0x00 0. "BUFFULLIF,Buffer Full \nFor an IN endpoint the currently selected buffer is full or no buffer is available to the local side for writing (no space to write)" "0: The endpoint packet buffer is not full,1: The endpoint packet buffer is full"
group.long 0x15C++0x03
line.long 0x00 "USBD_EPGINTEN,Endpoint G Interrupt Enable Register"
bitfld.long 0x00 12. "SHORTRXIEN,Bulk Out Short Packet Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.\n" "0: Bulk out interrupt Disabled,1: Bulk out interrupt Enabled"
bitfld.long 0x00 11. "ERRIEN,ERR Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.\n" "0: Error event interrupt Disabled,1: Error event interrupt Enabled"
newline
bitfld.long 0x00 10. "NYETIEN,NYET Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.\n" "0: NYET condition interrupt Disabled,1: NYET condition interrupt Enabled"
bitfld.long 0x00 9. "STALLIEN,USB STALL Sent Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a stall token is sent to the host.\n" "0: STALL token interrupt Disabled,1: STALL token interrupt Enabled"
newline
bitfld.long 0x00 8. "NAKIEN,USB NAK Sent Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a NAK token is sent to the host.\n" "0: NAK token interrupt Disabled,1: NAK token interrupt Enabled"
bitfld.long 0x00 7. "PINGIEN,PING Token Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a PING token has been received from the host.\n" "0: PING token interrupt Disabled,1: PING token interrupt Enabled"
newline
bitfld.long 0x00 6. "INTKIEN,Data IN Token Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set when a Data IN token has been received from the host.\n" "0: Data IN token interrupt Disabled,1: Data IN token interrupt Enabled"
bitfld.long 0x00 5. "OUTTKIEN,Data OUT Token Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a Data OUT token has been received from the host.\n" "0: Data OUT token interrupt Disabled,1: Data OUT token interrupt Enabled"
newline
bitfld.long 0x00 4. "RXPKIEN,Data Packet Received Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a data packet has been transmitted to the host.\n" "0: Data packet has been transmitted to the host..,1: Data packet has been transmitted to the host.."
bitfld.long 0x00 3. "TXPKIEN,Data Packet Transmitted Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a data packet has been received from the host.\n" "0: Data packet has been received from the host..,1: Data packet has been received from the host.."
newline
bitfld.long 0x00 2. "SHORTTXIEN,Short Packet Transferred Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.\n" "0: Short data packet interrupt Disabled,1: Short data packet interrupt Enabled"
bitfld.long 0x00 1. "BUFEMPTYIEN,Buffer Empty Interrupt\nWhen set this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.\n" "0: Buffer empty interrupt Disabled,1: Buffer empty interrupt Enabled"
newline
bitfld.long 0x00 0. "BUFFULLIEN,Buffer Full Interrupt \nWhen set this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.\n" "0: Buffer full interrupt Disabled,1: Buffer full interrupt Enabled"
group.long 0x160++0x03
line.long 0x00 "USBD_EPGDATCNT,Endpoint G Data Available Count Register"
hexmask.long.word 0x00 16.--30. 1. "DMALOOP,DMA Loop\nThis register is the remaining DMA loop to complete"
hexmask.long.word 0x00 0.--15. 1. "DATCNT,Data Count\nFor an IN endpoint (EPDIR(USBD_EPxCFG[3] is high.) this register returns the number of valid bytes in the IN endpoint packet buffer.\nFor an OUT endpoint (EPDIR(USBD_EPxCFG[3] is low.) this register returns the number of received.."
group.long 0x164++0x03
line.long 0x00 "USBD_EPGRSPCTL,Endpoint G Response Control Register"
bitfld.long 0x00 7. "DISBUF,Buffer Disable Bit\nThis bit is used to receive unknown size OUT short packet" "0: Buffer Not Disabled when Bulk-OUT short..,1: Buffer Disabled when Bulk-OUT short packet is.."
bitfld.long 0x00 6. "SHORTTXEN,Short Packet Transfer Enable Bit\nThis bit is applicable only in case of Auto-Validate Method" "0: Not validate any remaining data in the buffer..,1: Validate any remaining data in the buffer.."
newline
bitfld.long 0x00 5. "ZEROLEN,Zero Length\nThis bit is used to send a zero-length packet response to an IN-token" "0: A zero packet is not sent to the host on..,1: A zero packet is sent to the host on.."
bitfld.long 0x00 4. "HALT,Endpoint Halt \nThis bit is used to send a STALL handshake as response to the token from the host" "0: Do not send a STALL handshake as response to..,1: Send a STALL handshake as response to the.."
newline
bitfld.long 0x00 3. "TOGGLE,Endpoint Toggle \nThis bit is used to clear the endpoint data toggle bit" "0: Do not clear the endpoint data toggle bit,1: Clear the endpoint data toggle bit"
bitfld.long 0x00 1.--2. "MODE,Mode Control\nThe two bits determine the operation mode of the in-endpoint" "0: Auto-Validate Mode,1: Manual-Validate Mode,2: Fly Mode,3: Reserved"
newline
bitfld.long 0x00 0. "FLUSH,Buffer Flush \nWriting 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared" "0: The packet buffer is not flushed,1: The packet buffer is flushed by user"
group.long 0x168++0x03
line.long 0x00 "USBD_EPGMPS,Endpoint G Maximum Packet Size Register"
hexmask.long.word 0x00 0.--10. 1. "EPMPS,Endpoint Maximum Packet Size \nThis field determines the Maximum Packet Size of the Endpoint"
group.long 0x16C++0x03
line.long 0x00 "USBD_EPGTXCNT,Endpoint G Transfer Count Register"
hexmask.long.word 0x00 0.--10. 1. "TXCNT,Endpoint Transfer Count\nFor IN endpoints this field determines the total number of bytes to be sent to the host in case of manual validation method.\nFor OUT endpoints this field has no effect"
group.long 0x170++0x03
line.long 0x00 "USBD_EPGCFG,Endpoint G Configuration Register"
bitfld.long 0x00 4.--7. "EPNUM,Endpoint Number\nThis field selects the number of the endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3. "EPDIR,Endpoint Direction\n A maximum of one OUT and IN endpoint is allowed for each endpoint number" "0: out-endpoint (Host OUT to Device),1: in-endpoint (Host IN to Device)"
newline
bitfld.long 0x00 1.--2. "EPTYPE,Endpoint Type\nThis field selects the type of this endpoint" "0: Reserved,1: Bulk,2: Interrupt,3: Isochronous"
bitfld.long 0x00 0. "EPEN,Endpoint Valid\nWhen set this bit enables this endpoint" "0: The endpoint Disabled,1: The endpoint Enabled"
group.long 0x174++0x03
line.long 0x00 "USBD_EPGBUFSTART,Endpoint G RAM Start Address Register"
hexmask.long.word 0x00 0.--11. 1. "SADDR,Endpoint Start Address\nThis is the start-address of the RAM space allocated for the endpoint A~L"
group.long 0x178++0x03
line.long 0x00 "USBD_EPGBUFEND,Endpoint G RAM End Address Register"
hexmask.long.word 0x00 0.--11. 1. "EADDR,Endpoint End Address\nThis is the end-address of the RAM space allocated for the endpoint A~L"
group.long 0x17C++0x03
line.long 0x00 "USBD_EPHDAT,Endpoint H Data Register"
hexmask.long 0x00 0.--31. 1. "EPDAT,Endpoint A~L Data Register \nEndpoint A~L data buffer for the buffer transaction (read or write).\n Only word or byte access are supported"
group.long 0x180++0x03
line.long 0x00 "USBD_EPHINTSTS,Endpoint H Interrupt Status Register"
bitfld.long 0x00 12. "SHORTRXIF,Bulk Out Short Packet Received\n Write 1 to clear this bit to 0" "0: No bulk out short packet is received,1: Received bulk out short packet (including.."
bitfld.long 0x00 11. "ERRIF,ERR Sent \n Write 1 to clear this bit to 0" "0: No any error in the transaction,1: There occurs any error in the transaction"
newline
bitfld.long 0x00 10. "NYETIF,NYET Sent \n Write 1 to clear this bit to 0" "0: The space available in the RAM is sufficient..,1: The space available in the RAM is not.."
bitfld.long 0x00 9. "STALLIF,USB STALL Sent\n Write 1 to clear this bit to 0" "0: The last USB packet could be accepted or..,1: The last USB packet could not be accepted or.."
newline
bitfld.long 0x00 8. "NAKIF,USB NAK Sent\n Write 1 to clear this bit to 0" "0: The last USB IN packet could be provided and..,1: The last USB IN packet could not be provided.."
bitfld.long 0x00 7. "PINGIF,PING Token Interrupt \n Write 1 to clear this bit to 0" "0: A Data PING token has not been received from..,1: A Data PING token has been received from the.."
newline
bitfld.long 0x00 6. "INTKIF,Data IN Token Interrupt \n Write 1 to clear this bit to 0" "0: No Data IN token has been received from the..,1: A Data IN token has been received from the host"
bitfld.long 0x00 5. "OUTTKIF,Data OUT Token Interrupt\nNote: Write 1 to clear this bit to 0" "0: A Data OUT token has not been received from..,1: A Data OUT token has been received from the.."
newline
bitfld.long 0x00 4. "RXPKIF,Data Packet Received Interrupt\nNote: Write 1 to clear this bit to 0" "0: No data packet is received from the host by..,1: A data packet is received from the host by.."
bitfld.long 0x00 3. "TXPKIF,Data Packet Transmitted Interrupt \nNote: Write 1 to clear this bit to 0" "0: No data packet is transmitted from the..,1: A data packet is transmitted from the.."
newline
bitfld.long 0x00 2. "SHORTTXIF,Short Packet Transferred Interrupt \n Note: Write 1 to clear this bit to 0" "0: The length of the last packet was not less..,1: The length of the last packet was less than.."
bitfld.long 0x00 1. "BUFEMPTYIF,Buffer Empty\nFor an IN endpoint a buffer is available to the local side for writing up to FIFO full of bytes" "0: The endpoint buffer is not empty.\nThe..,1: The endpoint buffer is empty.\nThe currently.."
newline
bitfld.long 0x00 0. "BUFFULLIF,Buffer Full \nFor an IN endpoint the currently selected buffer is full or no buffer is available to the local side for writing (no space to write)" "0: The endpoint packet buffer is not full,1: The endpoint packet buffer is full"
group.long 0x184++0x03
line.long 0x00 "USBD_EPHINTEN,Endpoint H Interrupt Enable Register"
bitfld.long 0x00 12. "SHORTRXIEN,Bulk Out Short Packet Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.\n" "0: Bulk out interrupt Disabled,1: Bulk out interrupt Enabled"
bitfld.long 0x00 11. "ERRIEN,ERR Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.\n" "0: Error event interrupt Disabled,1: Error event interrupt Enabled"
newline
bitfld.long 0x00 10. "NYETIEN,NYET Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.\n" "0: NYET condition interrupt Disabled,1: NYET condition interrupt Enabled"
bitfld.long 0x00 9. "STALLIEN,USB STALL Sent Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a stall token is sent to the host.\n" "0: STALL token interrupt Disabled,1: STALL token interrupt Enabled"
newline
bitfld.long 0x00 8. "NAKIEN,USB NAK Sent Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a NAK token is sent to the host.\n" "0: NAK token interrupt Disabled,1: NAK token interrupt Enabled"
bitfld.long 0x00 7. "PINGIEN,PING Token Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a PING token has been received from the host.\n" "0: PING token interrupt Disabled,1: PING token interrupt Enabled"
newline
bitfld.long 0x00 6. "INTKIEN,Data IN Token Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set when a Data IN token has been received from the host.\n" "0: Data IN token interrupt Disabled,1: Data IN token interrupt Enabled"
bitfld.long 0x00 5. "OUTTKIEN,Data OUT Token Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a Data OUT token has been received from the host.\n" "0: Data OUT token interrupt Disabled,1: Data OUT token interrupt Enabled"
newline
bitfld.long 0x00 4. "RXPKIEN,Data Packet Received Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a data packet has been transmitted to the host.\n" "0: Data packet has been transmitted to the host..,1: Data packet has been transmitted to the host.."
bitfld.long 0x00 3. "TXPKIEN,Data Packet Transmitted Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a data packet has been received from the host.\n" "0: Data packet has been received from the host..,1: Data packet has been received from the host.."
newline
bitfld.long 0x00 2. "SHORTTXIEN,Short Packet Transferred Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.\n" "0: Short data packet interrupt Disabled,1: Short data packet interrupt Enabled"
bitfld.long 0x00 1. "BUFEMPTYIEN,Buffer Empty Interrupt\nWhen set this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.\n" "0: Buffer empty interrupt Disabled,1: Buffer empty interrupt Enabled"
newline
bitfld.long 0x00 0. "BUFFULLIEN,Buffer Full Interrupt \nWhen set this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.\n" "0: Buffer full interrupt Disabled,1: Buffer full interrupt Enabled"
group.long 0x188++0x03
line.long 0x00 "USBD_EPHDATCNT,Endpoint H Data Available Count Register"
hexmask.long.word 0x00 16.--30. 1. "DMALOOP,DMA Loop\nThis register is the remaining DMA loop to complete"
hexmask.long.word 0x00 0.--15. 1. "DATCNT,Data Count\nFor an IN endpoint (EPDIR(USBD_EPxCFG[3] is high.) this register returns the number of valid bytes in the IN endpoint packet buffer.\nFor an OUT endpoint (EPDIR(USBD_EPxCFG[3] is low.) this register returns the number of received.."
group.long 0x18C++0x03
line.long 0x00 "USBD_EPHRSPCTL,Endpoint H Response Control Register"
bitfld.long 0x00 7. "DISBUF,Buffer Disable Bit\nThis bit is used to receive unknown size OUT short packet" "0: Buffer Not Disabled when Bulk-OUT short..,1: Buffer Disabled when Bulk-OUT short packet is.."
bitfld.long 0x00 6. "SHORTTXEN,Short Packet Transfer Enable Bit\nThis bit is applicable only in case of Auto-Validate Method" "0: Not validate any remaining data in the buffer..,1: Validate any remaining data in the buffer.."
newline
bitfld.long 0x00 5. "ZEROLEN,Zero Length\nThis bit is used to send a zero-length packet response to an IN-token" "0: A zero packet is not sent to the host on..,1: A zero packet is sent to the host on.."
bitfld.long 0x00 4. "HALT,Endpoint Halt \nThis bit is used to send a STALL handshake as response to the token from the host" "0: Do not send a STALL handshake as response to..,1: Send a STALL handshake as response to the.."
newline
bitfld.long 0x00 3. "TOGGLE,Endpoint Toggle \nThis bit is used to clear the endpoint data toggle bit" "0: Do not clear the endpoint data toggle bit,1: Clear the endpoint data toggle bit"
bitfld.long 0x00 1.--2. "MODE,Mode Control\nThe two bits determine the operation mode of the in-endpoint" "0: Auto-Validate Mode,1: Manual-Validate Mode,2: Fly Mode,3: Reserved"
newline
bitfld.long 0x00 0. "FLUSH,Buffer Flush \nWriting 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared" "0: The packet buffer is not flushed,1: The packet buffer is flushed by user"
group.long 0x190++0x03
line.long 0x00 "USBD_EPHMPS,Endpoint H Maximum Packet Size Register"
hexmask.long.word 0x00 0.--10. 1. "EPMPS,Endpoint Maximum Packet Size \nThis field determines the Maximum Packet Size of the Endpoint"
group.long 0x194++0x03
line.long 0x00 "USBD_EPHTXCNT,Endpoint H Transfer Count Register"
hexmask.long.word 0x00 0.--10. 1. "TXCNT,Endpoint Transfer Count\nFor IN endpoints this field determines the total number of bytes to be sent to the host in case of manual validation method.\nFor OUT endpoints this field has no effect"
group.long 0x198++0x03
line.long 0x00 "USBD_EPHCFG,Endpoint H Configuration Register"
bitfld.long 0x00 4.--7. "EPNUM,Endpoint Number\nThis field selects the number of the endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3. "EPDIR,Endpoint Direction\n A maximum of one OUT and IN endpoint is allowed for each endpoint number" "0: out-endpoint (Host OUT to Device),1: in-endpoint (Host IN to Device)"
newline
bitfld.long 0x00 1.--2. "EPTYPE,Endpoint Type\nThis field selects the type of this endpoint" "0: Reserved,1: Bulk,2: Interrupt,3: Isochronous"
bitfld.long 0x00 0. "EPEN,Endpoint Valid\nWhen set this bit enables this endpoint" "0: The endpoint Disabled,1: The endpoint Enabled"
group.long 0x19C++0x03
line.long 0x00 "USBD_EPHBUFSTART,Endpoint H RAM Start Address Register"
hexmask.long.word 0x00 0.--11. 1. "SADDR,Endpoint Start Address\nThis is the start-address of the RAM space allocated for the endpoint A~L"
group.long 0x1A0++0x03
line.long 0x00 "USBD_EPHBUFEND,Endpoint H RAM End Address Register"
hexmask.long.word 0x00 0.--11. 1. "EADDR,Endpoint End Address\nThis is the end-address of the RAM space allocated for the endpoint A~L"
group.long 0x1A4++0x03
line.long 0x00 "USBD_EPIDAT,Endpoint I Data Register"
hexmask.long 0x00 0.--31. 1. "EPDAT,Endpoint A~L Data Register \nEndpoint A~L data buffer for the buffer transaction (read or write).\n Only word or byte access are supported"
group.long 0x1A8++0x03
line.long 0x00 "USBD_EPIINTSTS,Endpoint I Interrupt Status Register"
bitfld.long 0x00 12. "SHORTRXIF,Bulk Out Short Packet Received\n Write 1 to clear this bit to 0" "0: No bulk out short packet is received,1: Received bulk out short packet (including.."
bitfld.long 0x00 11. "ERRIF,ERR Sent \n Write 1 to clear this bit to 0" "0: No any error in the transaction,1: There occurs any error in the transaction"
newline
bitfld.long 0x00 10. "NYETIF,NYET Sent \n Write 1 to clear this bit to 0" "0: The space available in the RAM is sufficient..,1: The space available in the RAM is not.."
bitfld.long 0x00 9. "STALLIF,USB STALL Sent\n Write 1 to clear this bit to 0" "0: The last USB packet could be accepted or..,1: The last USB packet could not be accepted or.."
newline
bitfld.long 0x00 8. "NAKIF,USB NAK Sent\n Write 1 to clear this bit to 0" "0: The last USB IN packet could be provided and..,1: The last USB IN packet could not be provided.."
bitfld.long 0x00 7. "PINGIF,PING Token Interrupt \n Write 1 to clear this bit to 0" "0: A Data PING token has not been received from..,1: A Data PING token has been received from the.."
newline
bitfld.long 0x00 6. "INTKIF,Data IN Token Interrupt \n Write 1 to clear this bit to 0" "0: No Data IN token has been received from the..,1: A Data IN token has been received from the host"
bitfld.long 0x00 5. "OUTTKIF,Data OUT Token Interrupt\nNote: Write 1 to clear this bit to 0" "0: A Data OUT token has not been received from..,1: A Data OUT token has been received from the.."
newline
bitfld.long 0x00 4. "RXPKIF,Data Packet Received Interrupt\nNote: Write 1 to clear this bit to 0" "0: No data packet is received from the host by..,1: A data packet is received from the host by.."
bitfld.long 0x00 3. "TXPKIF,Data Packet Transmitted Interrupt \nNote: Write 1 to clear this bit to 0" "0: No data packet is transmitted from the..,1: A data packet is transmitted from the.."
newline
bitfld.long 0x00 2. "SHORTTXIF,Short Packet Transferred Interrupt \n Note: Write 1 to clear this bit to 0" "0: The length of the last packet was not less..,1: The length of the last packet was less than.."
bitfld.long 0x00 1. "BUFEMPTYIF,Buffer Empty\nFor an IN endpoint a buffer is available to the local side for writing up to FIFO full of bytes" "0: The endpoint buffer is not empty.\nThe..,1: The endpoint buffer is empty.\nThe currently.."
newline
bitfld.long 0x00 0. "BUFFULLIF,Buffer Full \nFor an IN endpoint the currently selected buffer is full or no buffer is available to the local side for writing (no space to write)" "0: The endpoint packet buffer is not full,1: The endpoint packet buffer is full"
group.long 0x1AC++0x03
line.long 0x00 "USBD_EPIINTEN,Endpoint I Interrupt Enable Register"
bitfld.long 0x00 12. "SHORTRXIEN,Bulk Out Short Packet Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.\n" "0: Bulk out interrupt Disabled,1: Bulk out interrupt Enabled"
bitfld.long 0x00 11. "ERRIEN,ERR Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.\n" "0: Error event interrupt Disabled,1: Error event interrupt Enabled"
newline
bitfld.long 0x00 10. "NYETIEN,NYET Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.\n" "0: NYET condition interrupt Disabled,1: NYET condition interrupt Enabled"
bitfld.long 0x00 9. "STALLIEN,USB STALL Sent Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a stall token is sent to the host.\n" "0: STALL token interrupt Disabled,1: STALL token interrupt Enabled"
newline
bitfld.long 0x00 8. "NAKIEN,USB NAK Sent Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a NAK token is sent to the host.\n" "0: NAK token interrupt Disabled,1: NAK token interrupt Enabled"
bitfld.long 0x00 7. "PINGIEN,PING Token Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a PING token has been received from the host.\n" "0: PING token interrupt Disabled,1: PING token interrupt Enabled"
newline
bitfld.long 0x00 6. "INTKIEN,Data IN Token Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set when a Data IN token has been received from the host.\n" "0: Data IN token interrupt Disabled,1: Data IN token interrupt Enabled"
bitfld.long 0x00 5. "OUTTKIEN,Data OUT Token Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a Data OUT token has been received from the host.\n" "0: Data OUT token interrupt Disabled,1: Data OUT token interrupt Enabled"
newline
bitfld.long 0x00 4. "RXPKIEN,Data Packet Received Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a data packet has been transmitted to the host.\n" "0: Data packet has been transmitted to the host..,1: Data packet has been transmitted to the host.."
bitfld.long 0x00 3. "TXPKIEN,Data Packet Transmitted Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a data packet has been received from the host.\n" "0: Data packet has been received from the host..,1: Data packet has been received from the host.."
newline
bitfld.long 0x00 2. "SHORTTXIEN,Short Packet Transferred Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.\n" "0: Short data packet interrupt Disabled,1: Short data packet interrupt Enabled"
bitfld.long 0x00 1. "BUFEMPTYIEN,Buffer Empty Interrupt\nWhen set this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.\n" "0: Buffer empty interrupt Disabled,1: Buffer empty interrupt Enabled"
newline
bitfld.long 0x00 0. "BUFFULLIEN,Buffer Full Interrupt \nWhen set this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.\n" "0: Buffer full interrupt Disabled,1: Buffer full interrupt Enabled"
group.long 0x1B0++0x03
line.long 0x00 "USBD_EPIDATCNT,Endpoint I Data Available Count Register"
hexmask.long.word 0x00 16.--30. 1. "DMALOOP,DMA Loop\nThis register is the remaining DMA loop to complete"
hexmask.long.word 0x00 0.--15. 1. "DATCNT,Data Count\nFor an IN endpoint (EPDIR(USBD_EPxCFG[3] is high.) this register returns the number of valid bytes in the IN endpoint packet buffer.\nFor an OUT endpoint (EPDIR(USBD_EPxCFG[3] is low.) this register returns the number of received.."
group.long 0x1B4++0x03
line.long 0x00 "USBD_EPIRSPCTL,Endpoint I Response Control Register"
bitfld.long 0x00 7. "DISBUF,Buffer Disable Bit\nThis bit is used to receive unknown size OUT short packet" "0: Buffer Not Disabled when Bulk-OUT short..,1: Buffer Disabled when Bulk-OUT short packet is.."
bitfld.long 0x00 6. "SHORTTXEN,Short Packet Transfer Enable Bit\nThis bit is applicable only in case of Auto-Validate Method" "0: Not validate any remaining data in the buffer..,1: Validate any remaining data in the buffer.."
newline
bitfld.long 0x00 5. "ZEROLEN,Zero Length\nThis bit is used to send a zero-length packet response to an IN-token" "0: A zero packet is not sent to the host on..,1: A zero packet is sent to the host on.."
bitfld.long 0x00 4. "HALT,Endpoint Halt \nThis bit is used to send a STALL handshake as response to the token from the host" "0: Do not send a STALL handshake as response to..,1: Send a STALL handshake as response to the.."
newline
bitfld.long 0x00 3. "TOGGLE,Endpoint Toggle \nThis bit is used to clear the endpoint data toggle bit" "0: Do not clear the endpoint data toggle bit,1: Clear the endpoint data toggle bit"
bitfld.long 0x00 1.--2. "MODE,Mode Control\nThe two bits determine the operation mode of the in-endpoint" "0: Auto-Validate Mode,1: Manual-Validate Mode,2: Fly Mode,3: Reserved"
newline
bitfld.long 0x00 0. "FLUSH,Buffer Flush \nWriting 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared" "0: The packet buffer is not flushed,1: The packet buffer is flushed by user"
group.long 0x1B8++0x03
line.long 0x00 "USBD_EPIMPS,Endpoint I Maximum Packet Size Register"
hexmask.long.word 0x00 0.--10. 1. "EPMPS,Endpoint Maximum Packet Size \nThis field determines the Maximum Packet Size of the Endpoint"
group.long 0x1BC++0x03
line.long 0x00 "USBD_EPITXCNT,Endpoint I Transfer Count Register"
hexmask.long.word 0x00 0.--10. 1. "TXCNT,Endpoint Transfer Count\nFor IN endpoints this field determines the total number of bytes to be sent to the host in case of manual validation method.\nFor OUT endpoints this field has no effect"
group.long 0x1C0++0x03
line.long 0x00 "USBD_EPICFG,Endpoint I Configuration Register"
bitfld.long 0x00 4.--7. "EPNUM,Endpoint Number\nThis field selects the number of the endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3. "EPDIR,Endpoint Direction\n A maximum of one OUT and IN endpoint is allowed for each endpoint number" "0: out-endpoint (Host OUT to Device),1: in-endpoint (Host IN to Device)"
newline
bitfld.long 0x00 1.--2. "EPTYPE,Endpoint Type\nThis field selects the type of this endpoint" "0: Reserved,1: Bulk,2: Interrupt,3: Isochronous"
bitfld.long 0x00 0. "EPEN,Endpoint Valid\nWhen set this bit enables this endpoint" "0: The endpoint Disabled,1: The endpoint Enabled"
group.long 0x1C4++0x03
line.long 0x00 "USBD_EPIBUFSTART,Endpoint I RAM Start Address Register"
hexmask.long.word 0x00 0.--11. 1. "SADDR,Endpoint Start Address\nThis is the start-address of the RAM space allocated for the endpoint A~L"
group.long 0x1C8++0x03
line.long 0x00 "USBD_EPIBUFEND,Endpoint I RAM End Address Register"
hexmask.long.word 0x00 0.--11. 1. "EADDR,Endpoint End Address\nThis is the end-address of the RAM space allocated for the endpoint A~L"
group.long 0x1CC++0x03
line.long 0x00 "USBD_EPJDAT,Endpoint J Data Register"
hexmask.long 0x00 0.--31. 1. "EPDAT,Endpoint A~L Data Register \nEndpoint A~L data buffer for the buffer transaction (read or write).\n Only word or byte access are supported"
group.long 0x1D0++0x03
line.long 0x00 "USBD_EPJINTSTS,Endpoint J Interrupt Status Register"
bitfld.long 0x00 12. "SHORTRXIF,Bulk Out Short Packet Received\n Write 1 to clear this bit to 0" "0: No bulk out short packet is received,1: Received bulk out short packet (including.."
bitfld.long 0x00 11. "ERRIF,ERR Sent \n Write 1 to clear this bit to 0" "0: No any error in the transaction,1: There occurs any error in the transaction"
newline
bitfld.long 0x00 10. "NYETIF,NYET Sent \n Write 1 to clear this bit to 0" "0: The space available in the RAM is sufficient..,1: The space available in the RAM is not.."
bitfld.long 0x00 9. "STALLIF,USB STALL Sent\n Write 1 to clear this bit to 0" "0: The last USB packet could be accepted or..,1: The last USB packet could not be accepted or.."
newline
bitfld.long 0x00 8. "NAKIF,USB NAK Sent\n Write 1 to clear this bit to 0" "0: The last USB IN packet could be provided and..,1: The last USB IN packet could not be provided.."
bitfld.long 0x00 7. "PINGIF,PING Token Interrupt \n Write 1 to clear this bit to 0" "0: A Data PING token has not been received from..,1: A Data PING token has been received from the.."
newline
bitfld.long 0x00 6. "INTKIF,Data IN Token Interrupt \n Write 1 to clear this bit to 0" "0: No Data IN token has been received from the..,1: A Data IN token has been received from the host"
bitfld.long 0x00 5. "OUTTKIF,Data OUT Token Interrupt\nNote: Write 1 to clear this bit to 0" "0: A Data OUT token has not been received from..,1: A Data OUT token has been received from the.."
newline
bitfld.long 0x00 4. "RXPKIF,Data Packet Received Interrupt\nNote: Write 1 to clear this bit to 0" "0: No data packet is received from the host by..,1: A data packet is received from the host by.."
bitfld.long 0x00 3. "TXPKIF,Data Packet Transmitted Interrupt \nNote: Write 1 to clear this bit to 0" "0: No data packet is transmitted from the..,1: A data packet is transmitted from the.."
newline
bitfld.long 0x00 2. "SHORTTXIF,Short Packet Transferred Interrupt \n Note: Write 1 to clear this bit to 0" "0: The length of the last packet was not less..,1: The length of the last packet was less than.."
bitfld.long 0x00 1. "BUFEMPTYIF,Buffer Empty\nFor an IN endpoint a buffer is available to the local side for writing up to FIFO full of bytes" "0: The endpoint buffer is not empty.\nThe..,1: The endpoint buffer is empty.\nThe currently.."
newline
bitfld.long 0x00 0. "BUFFULLIF,Buffer Full \nFor an IN endpoint the currently selected buffer is full or no buffer is available to the local side for writing (no space to write)" "0: The endpoint packet buffer is not full,1: The endpoint packet buffer is full"
group.long 0x1D4++0x03
line.long 0x00 "USBD_EPJINTEN,Endpoint J Interrupt Enable Register"
bitfld.long 0x00 12. "SHORTRXIEN,Bulk Out Short Packet Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.\n" "0: Bulk out interrupt Disabled,1: Bulk out interrupt Enabled"
bitfld.long 0x00 11. "ERRIEN,ERR Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.\n" "0: Error event interrupt Disabled,1: Error event interrupt Enabled"
newline
bitfld.long 0x00 10. "NYETIEN,NYET Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.\n" "0: NYET condition interrupt Disabled,1: NYET condition interrupt Enabled"
bitfld.long 0x00 9. "STALLIEN,USB STALL Sent Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a stall token is sent to the host.\n" "0: STALL token interrupt Disabled,1: STALL token interrupt Enabled"
newline
bitfld.long 0x00 8. "NAKIEN,USB NAK Sent Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a NAK token is sent to the host.\n" "0: NAK token interrupt Disabled,1: NAK token interrupt Enabled"
bitfld.long 0x00 7. "PINGIEN,PING Token Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a PING token has been received from the host.\n" "0: PING token interrupt Disabled,1: PING token interrupt Enabled"
newline
bitfld.long 0x00 6. "INTKIEN,Data IN Token Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set when a Data IN token has been received from the host.\n" "0: Data IN token interrupt Disabled,1: Data IN token interrupt Enabled"
bitfld.long 0x00 5. "OUTTKIEN,Data OUT Token Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a Data OUT token has been received from the host.\n" "0: Data OUT token interrupt Disabled,1: Data OUT token interrupt Enabled"
newline
bitfld.long 0x00 4. "RXPKIEN,Data Packet Received Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a data packet has been transmitted to the host.\n" "0: Data packet has been transmitted to the host..,1: Data packet has been transmitted to the host.."
bitfld.long 0x00 3. "TXPKIEN,Data Packet Transmitted Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a data packet has been received from the host.\n" "0: Data packet has been received from the host..,1: Data packet has been received from the host.."
newline
bitfld.long 0x00 2. "SHORTTXIEN,Short Packet Transferred Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.\n" "0: Short data packet interrupt Disabled,1: Short data packet interrupt Enabled"
bitfld.long 0x00 1. "BUFEMPTYIEN,Buffer Empty Interrupt\nWhen set this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.\n" "0: Buffer empty interrupt Disabled,1: Buffer empty interrupt Enabled"
newline
bitfld.long 0x00 0. "BUFFULLIEN,Buffer Full Interrupt \nWhen set this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.\n" "0: Buffer full interrupt Disabled,1: Buffer full interrupt Enabled"
group.long 0x1D8++0x03
line.long 0x00 "USBD_EPJDATCNT,Endpoint J Data Available Count Register"
hexmask.long.word 0x00 16.--30. 1. "DMALOOP,DMA Loop\nThis register is the remaining DMA loop to complete"
hexmask.long.word 0x00 0.--15. 1. "DATCNT,Data Count\nFor an IN endpoint (EPDIR(USBD_EPxCFG[3] is high.) this register returns the number of valid bytes in the IN endpoint packet buffer.\nFor an OUT endpoint (EPDIR(USBD_EPxCFG[3] is low.) this register returns the number of received.."
group.long 0x1DC++0x03
line.long 0x00 "USBD_EPJRSPCTL,Endpoint J Response Control Register"
bitfld.long 0x00 7. "DISBUF,Buffer Disable Bit\nThis bit is used to receive unknown size OUT short packet" "0: Buffer Not Disabled when Bulk-OUT short..,1: Buffer Disabled when Bulk-OUT short packet is.."
bitfld.long 0x00 6. "SHORTTXEN,Short Packet Transfer Enable Bit\nThis bit is applicable only in case of Auto-Validate Method" "0: Not validate any remaining data in the buffer..,1: Validate any remaining data in the buffer.."
newline
bitfld.long 0x00 5. "ZEROLEN,Zero Length\nThis bit is used to send a zero-length packet response to an IN-token" "0: A zero packet is not sent to the host on..,1: A zero packet is sent to the host on.."
bitfld.long 0x00 4. "HALT,Endpoint Halt \nThis bit is used to send a STALL handshake as response to the token from the host" "0: Do not send a STALL handshake as response to..,1: Send a STALL handshake as response to the.."
newline
bitfld.long 0x00 3. "TOGGLE,Endpoint Toggle \nThis bit is used to clear the endpoint data toggle bit" "0: Do not clear the endpoint data toggle bit,1: Clear the endpoint data toggle bit"
bitfld.long 0x00 1.--2. "MODE,Mode Control\nThe two bits determine the operation mode of the in-endpoint" "0: Auto-Validate Mode,1: Manual-Validate Mode,2: Fly Mode,3: Reserved"
newline
bitfld.long 0x00 0. "FLUSH,Buffer Flush \nWriting 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared" "0: The packet buffer is not flushed,1: The packet buffer is flushed by user"
group.long 0x1E0++0x03
line.long 0x00 "USBD_EPJMPS,Endpoint J Maximum Packet Size Register"
hexmask.long.word 0x00 0.--10. 1. "EPMPS,Endpoint Maximum Packet Size \nThis field determines the Maximum Packet Size of the Endpoint"
group.long 0x1E4++0x03
line.long 0x00 "USBD_EPJTXCNT,Endpoint J Transfer Count Register"
hexmask.long.word 0x00 0.--10. 1. "TXCNT,Endpoint Transfer Count\nFor IN endpoints this field determines the total number of bytes to be sent to the host in case of manual validation method.\nFor OUT endpoints this field has no effect"
group.long 0x1E8++0x03
line.long 0x00 "USBD_EPJCFG,Endpoint J Configuration Register"
bitfld.long 0x00 4.--7. "EPNUM,Endpoint Number\nThis field selects the number of the endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3. "EPDIR,Endpoint Direction\n A maximum of one OUT and IN endpoint is allowed for each endpoint number" "0: out-endpoint (Host OUT to Device),1: in-endpoint (Host IN to Device)"
newline
bitfld.long 0x00 1.--2. "EPTYPE,Endpoint Type\nThis field selects the type of this endpoint" "0: Reserved,1: Bulk,2: Interrupt,3: Isochronous"
bitfld.long 0x00 0. "EPEN,Endpoint Valid\nWhen set this bit enables this endpoint" "0: The endpoint Disabled,1: The endpoint Enabled"
group.long 0x1EC++0x03
line.long 0x00 "USBD_EPJBUFSTART,Endpoint J RAM Start Address Register"
hexmask.long.word 0x00 0.--11. 1. "SADDR,Endpoint Start Address\nThis is the start-address of the RAM space allocated for the endpoint A~L"
group.long 0x1F0++0x03
line.long 0x00 "USBD_EPJBUFEND,Endpoint J RAM End Address Register"
hexmask.long.word 0x00 0.--11. 1. "EADDR,Endpoint End Address\nThis is the end-address of the RAM space allocated for the endpoint A~L"
group.long 0x1F4++0x03
line.long 0x00 "USBD_EPKDAT,Endpoint K Data Register"
hexmask.long 0x00 0.--31. 1. "EPDAT,Endpoint A~L Data Register \nEndpoint A~L data buffer for the buffer transaction (read or write).\n Only word or byte access are supported"
group.long 0x1F8++0x03
line.long 0x00 "USBD_EPKINTSTS,Endpoint K Interrupt Status Register"
bitfld.long 0x00 12. "SHORTRXIF,Bulk Out Short Packet Received\n Write 1 to clear this bit to 0" "0: No bulk out short packet is received,1: Received bulk out short packet (including.."
bitfld.long 0x00 11. "ERRIF,ERR Sent \n Write 1 to clear this bit to 0" "0: No any error in the transaction,1: There occurs any error in the transaction"
newline
bitfld.long 0x00 10. "NYETIF,NYET Sent \n Write 1 to clear this bit to 0" "0: The space available in the RAM is sufficient..,1: The space available in the RAM is not.."
bitfld.long 0x00 9. "STALLIF,USB STALL Sent\n Write 1 to clear this bit to 0" "0: The last USB packet could be accepted or..,1: The last USB packet could not be accepted or.."
newline
bitfld.long 0x00 8. "NAKIF,USB NAK Sent\n Write 1 to clear this bit to 0" "0: The last USB IN packet could be provided and..,1: The last USB IN packet could not be provided.."
bitfld.long 0x00 7. "PINGIF,PING Token Interrupt \n Write 1 to clear this bit to 0" "0: A Data PING token has not been received from..,1: A Data PING token has been received from the.."
newline
bitfld.long 0x00 6. "INTKIF,Data IN Token Interrupt \n Write 1 to clear this bit to 0" "0: No Data IN token has been received from the..,1: A Data IN token has been received from the host"
bitfld.long 0x00 5. "OUTTKIF,Data OUT Token Interrupt\nNote: Write 1 to clear this bit to 0" "0: A Data OUT token has not been received from..,1: A Data OUT token has been received from the.."
newline
bitfld.long 0x00 4. "RXPKIF,Data Packet Received Interrupt\nNote: Write 1 to clear this bit to 0" "0: No data packet is received from the host by..,1: A data packet is received from the host by.."
bitfld.long 0x00 3. "TXPKIF,Data Packet Transmitted Interrupt \nNote: Write 1 to clear this bit to 0" "0: No data packet is transmitted from the..,1: A data packet is transmitted from the.."
newline
bitfld.long 0x00 2. "SHORTTXIF,Short Packet Transferred Interrupt \n Note: Write 1 to clear this bit to 0" "0: The length of the last packet was not less..,1: The length of the last packet was less than.."
bitfld.long 0x00 1. "BUFEMPTYIF,Buffer Empty\nFor an IN endpoint a buffer is available to the local side for writing up to FIFO full of bytes" "0: The endpoint buffer is not empty.\nThe..,1: The endpoint buffer is empty.\nThe currently.."
newline
bitfld.long 0x00 0. "BUFFULLIF,Buffer Full \nFor an IN endpoint the currently selected buffer is full or no buffer is available to the local side for writing (no space to write)" "0: The endpoint packet buffer is not full,1: The endpoint packet buffer is full"
group.long 0x1FC++0x03
line.long 0x00 "USBD_EPKINTEN,Endpoint K Interrupt Enable Register"
bitfld.long 0x00 12. "SHORTRXIEN,Bulk Out Short Packet Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.\n" "0: Bulk out interrupt Disabled,1: Bulk out interrupt Enabled"
bitfld.long 0x00 11. "ERRIEN,ERR Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.\n" "0: Error event interrupt Disabled,1: Error event interrupt Enabled"
newline
bitfld.long 0x00 10. "NYETIEN,NYET Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.\n" "0: NYET condition interrupt Disabled,1: NYET condition interrupt Enabled"
bitfld.long 0x00 9. "STALLIEN,USB STALL Sent Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a stall token is sent to the host.\n" "0: STALL token interrupt Disabled,1: STALL token interrupt Enabled"
newline
bitfld.long 0x00 8. "NAKIEN,USB NAK Sent Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a NAK token is sent to the host.\n" "0: NAK token interrupt Disabled,1: NAK token interrupt Enabled"
bitfld.long 0x00 7. "PINGIEN,PING Token Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a PING token has been received from the host.\n" "0: PING token interrupt Disabled,1: PING token interrupt Enabled"
newline
bitfld.long 0x00 6. "INTKIEN,Data IN Token Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set when a Data IN token has been received from the host.\n" "0: Data IN token interrupt Disabled,1: Data IN token interrupt Enabled"
bitfld.long 0x00 5. "OUTTKIEN,Data OUT Token Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a Data OUT token has been received from the host.\n" "0: Data OUT token interrupt Disabled,1: Data OUT token interrupt Enabled"
newline
bitfld.long 0x00 4. "RXPKIEN,Data Packet Received Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a data packet has been transmitted to the host.\n" "0: Data packet has been transmitted to the host..,1: Data packet has been transmitted to the host.."
bitfld.long 0x00 3. "TXPKIEN,Data Packet Transmitted Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a data packet has been received from the host.\n" "0: Data packet has been received from the host..,1: Data packet has been received from the host.."
newline
bitfld.long 0x00 2. "SHORTTXIEN,Short Packet Transferred Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.\n" "0: Short data packet interrupt Disabled,1: Short data packet interrupt Enabled"
bitfld.long 0x00 1. "BUFEMPTYIEN,Buffer Empty Interrupt\nWhen set this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.\n" "0: Buffer empty interrupt Disabled,1: Buffer empty interrupt Enabled"
newline
bitfld.long 0x00 0. "BUFFULLIEN,Buffer Full Interrupt \nWhen set this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.\n" "0: Buffer full interrupt Disabled,1: Buffer full interrupt Enabled"
group.long 0x200++0x03
line.long 0x00 "USBD_EPKDATCNT,Endpoint K Data Available Count Register"
hexmask.long.word 0x00 16.--30. 1. "DMALOOP,DMA Loop\nThis register is the remaining DMA loop to complete"
hexmask.long.word 0x00 0.--15. 1. "DATCNT,Data Count\nFor an IN endpoint (EPDIR(USBD_EPxCFG[3] is high.) this register returns the number of valid bytes in the IN endpoint packet buffer.\nFor an OUT endpoint (EPDIR(USBD_EPxCFG[3] is low.) this register returns the number of received.."
group.long 0x204++0x03
line.long 0x00 "USBD_EPKRSPCTL,Endpoint K Response Control Register"
bitfld.long 0x00 7. "DISBUF,Buffer Disable Bit\nThis bit is used to receive unknown size OUT short packet" "0: Buffer Not Disabled when Bulk-OUT short..,1: Buffer Disabled when Bulk-OUT short packet is.."
bitfld.long 0x00 6. "SHORTTXEN,Short Packet Transfer Enable Bit\nThis bit is applicable only in case of Auto-Validate Method" "0: Not validate any remaining data in the buffer..,1: Validate any remaining data in the buffer.."
newline
bitfld.long 0x00 5. "ZEROLEN,Zero Length\nThis bit is used to send a zero-length packet response to an IN-token" "0: A zero packet is not sent to the host on..,1: A zero packet is sent to the host on.."
bitfld.long 0x00 4. "HALT,Endpoint Halt \nThis bit is used to send a STALL handshake as response to the token from the host" "0: Do not send a STALL handshake as response to..,1: Send a STALL handshake as response to the.."
newline
bitfld.long 0x00 3. "TOGGLE,Endpoint Toggle \nThis bit is used to clear the endpoint data toggle bit" "0: Do not clear the endpoint data toggle bit,1: Clear the endpoint data toggle bit"
bitfld.long 0x00 1.--2. "MODE,Mode Control\nThe two bits determine the operation mode of the in-endpoint" "0: Auto-Validate Mode,1: Manual-Validate Mode,2: Fly Mode,3: Reserved"
newline
bitfld.long 0x00 0. "FLUSH,Buffer Flush \nWriting 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared" "0: The packet buffer is not flushed,1: The packet buffer is flushed by user"
group.long 0x208++0x03
line.long 0x00 "USBD_EPKMPS,Endpoint K Maximum Packet Size Register"
hexmask.long.word 0x00 0.--10. 1. "EPMPS,Endpoint Maximum Packet Size \nThis field determines the Maximum Packet Size of the Endpoint"
group.long 0x20C++0x03
line.long 0x00 "USBD_EPKTXCNT,Endpoint K Transfer Count Register"
hexmask.long.word 0x00 0.--10. 1. "TXCNT,Endpoint Transfer Count\nFor IN endpoints this field determines the total number of bytes to be sent to the host in case of manual validation method.\nFor OUT endpoints this field has no effect"
group.long 0x210++0x03
line.long 0x00 "USBD_EPKCFG,Endpoint K Configuration Register"
bitfld.long 0x00 4.--7. "EPNUM,Endpoint Number\nThis field selects the number of the endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3. "EPDIR,Endpoint Direction\n A maximum of one OUT and IN endpoint is allowed for each endpoint number" "0: out-endpoint (Host OUT to Device),1: in-endpoint (Host IN to Device)"
newline
bitfld.long 0x00 1.--2. "EPTYPE,Endpoint Type\nThis field selects the type of this endpoint" "0: Reserved,1: Bulk,2: Interrupt,3: Isochronous"
bitfld.long 0x00 0. "EPEN,Endpoint Valid\nWhen set this bit enables this endpoint" "0: The endpoint Disabled,1: The endpoint Enabled"
group.long 0x214++0x03
line.long 0x00 "USBD_EPKBUFSTART,Endpoint K RAM Start Address Register"
hexmask.long.word 0x00 0.--11. 1. "SADDR,Endpoint Start Address\nThis is the start-address of the RAM space allocated for the endpoint A~L"
group.long 0x218++0x03
line.long 0x00 "USBD_EPKBUFEND,Endpoint K RAM End Address Register"
hexmask.long.word 0x00 0.--11. 1. "EADDR,Endpoint End Address\nThis is the end-address of the RAM space allocated for the endpoint A~L"
group.long 0x21C++0x03
line.long 0x00 "USBD_EPLDAT,Endpoint L Data Register"
hexmask.long 0x00 0.--31. 1. "EPDAT,Endpoint A~L Data Register \nEndpoint A~L data buffer for the buffer transaction (read or write).\n Only word or byte access are supported"
group.long 0x220++0x03
line.long 0x00 "USBD_EPLINTSTS,Endpoint L Interrupt Status Register"
bitfld.long 0x00 12. "SHORTRXIF,Bulk Out Short Packet Received\n Write 1 to clear this bit to 0" "0: No bulk out short packet is received,1: Received bulk out short packet (including.."
bitfld.long 0x00 11. "ERRIF,ERR Sent \n Write 1 to clear this bit to 0" "0: No any error in the transaction,1: There occurs any error in the transaction"
newline
bitfld.long 0x00 10. "NYETIF,NYET Sent \n Write 1 to clear this bit to 0" "0: The space available in the RAM is sufficient..,1: The space available in the RAM is not.."
bitfld.long 0x00 9. "STALLIF,USB STALL Sent\n Write 1 to clear this bit to 0" "0: The last USB packet could be accepted or..,1: The last USB packet could not be accepted or.."
newline
bitfld.long 0x00 8. "NAKIF,USB NAK Sent\n Write 1 to clear this bit to 0" "0: The last USB IN packet could be provided and..,1: The last USB IN packet could not be provided.."
bitfld.long 0x00 7. "PINGIF,PING Token Interrupt \n Write 1 to clear this bit to 0" "0: A Data PING token has not been received from..,1: A Data PING token has been received from the.."
newline
bitfld.long 0x00 6. "INTKIF,Data IN Token Interrupt \n Write 1 to clear this bit to 0" "0: No Data IN token has been received from the..,1: A Data IN token has been received from the host"
bitfld.long 0x00 5. "OUTTKIF,Data OUT Token Interrupt\nNote: Write 1 to clear this bit to 0" "0: A Data OUT token has not been received from..,1: A Data OUT token has been received from the.."
newline
bitfld.long 0x00 4. "RXPKIF,Data Packet Received Interrupt\nNote: Write 1 to clear this bit to 0" "0: No data packet is received from the host by..,1: A data packet is received from the host by.."
bitfld.long 0x00 3. "TXPKIF,Data Packet Transmitted Interrupt \nNote: Write 1 to clear this bit to 0" "0: No data packet is transmitted from the..,1: A data packet is transmitted from the.."
newline
bitfld.long 0x00 2. "SHORTTXIF,Short Packet Transferred Interrupt \n Note: Write 1 to clear this bit to 0" "0: The length of the last packet was not less..,1: The length of the last packet was less than.."
bitfld.long 0x00 1. "BUFEMPTYIF,Buffer Empty\nFor an IN endpoint a buffer is available to the local side for writing up to FIFO full of bytes" "0: The endpoint buffer is not empty.\nThe..,1: The endpoint buffer is empty.\nThe currently.."
newline
bitfld.long 0x00 0. "BUFFULLIF,Buffer Full \nFor an IN endpoint the currently selected buffer is full or no buffer is available to the local side for writing (no space to write)" "0: The endpoint packet buffer is not full,1: The endpoint packet buffer is full"
group.long 0x224++0x03
line.long 0x00 "USBD_EPLINTEN,Endpoint L Interrupt Enable Register"
bitfld.long 0x00 12. "SHORTRXIEN,Bulk Out Short Packet Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.\n" "0: Bulk out interrupt Disabled,1: Bulk out interrupt Enabled"
bitfld.long 0x00 11. "ERRIEN,ERR Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.\n" "0: Error event interrupt Disabled,1: Error event interrupt Enabled"
newline
bitfld.long 0x00 10. "NYETIEN,NYET Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.\n" "0: NYET condition interrupt Disabled,1: NYET condition interrupt Enabled"
bitfld.long 0x00 9. "STALLIEN,USB STALL Sent Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a stall token is sent to the host.\n" "0: STALL token interrupt Disabled,1: STALL token interrupt Enabled"
newline
bitfld.long 0x00 8. "NAKIEN,USB NAK Sent Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a NAK token is sent to the host.\n" "0: NAK token interrupt Disabled,1: NAK token interrupt Enabled"
bitfld.long 0x00 7. "PINGIEN,PING Token Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a PING token has been received from the host.\n" "0: PING token interrupt Disabled,1: PING token interrupt Enabled"
newline
bitfld.long 0x00 6. "INTKIEN,Data IN Token Interrupt Enable Bit\nWhen set this bit enables a local interrupt to be set when a Data IN token has been received from the host.\n" "0: Data IN token interrupt Disabled,1: Data IN token interrupt Enabled"
bitfld.long 0x00 5. "OUTTKIEN,Data OUT Token Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a Data OUT token has been received from the host.\n" "0: Data OUT token interrupt Disabled,1: Data OUT token interrupt Enabled"
newline
bitfld.long 0x00 4. "RXPKIEN,Data Packet Received Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a data packet has been transmitted to the host.\n" "0: Data packet has been transmitted to the host..,1: Data packet has been transmitted to the host.."
bitfld.long 0x00 3. "TXPKIEN,Data Packet Transmitted Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a data packet has been received from the host.\n" "0: Data packet has been received from the host..,1: Data packet has been received from the host.."
newline
bitfld.long 0x00 2. "SHORTTXIEN,Short Packet Transferred Interrupt Enable Bit \nWhen set this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.\n" "0: Short data packet interrupt Disabled,1: Short data packet interrupt Enabled"
bitfld.long 0x00 1. "BUFEMPTYIEN,Buffer Empty Interrupt\nWhen set this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.\n" "0: Buffer empty interrupt Disabled,1: Buffer empty interrupt Enabled"
newline
bitfld.long 0x00 0. "BUFFULLIEN,Buffer Full Interrupt \nWhen set this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.\n" "0: Buffer full interrupt Disabled,1: Buffer full interrupt Enabled"
group.long 0x228++0x03
line.long 0x00 "USBD_EPLDATCNT,Endpoint L Data Available Count Register"
hexmask.long.word 0x00 16.--30. 1. "DMALOOP,DMA Loop\nThis register is the remaining DMA loop to complete"
hexmask.long.word 0x00 0.--15. 1. "DATCNT,Data Count\nFor an IN endpoint (EPDIR(USBD_EPxCFG[3] is high.) this register returns the number of valid bytes in the IN endpoint packet buffer.\nFor an OUT endpoint (EPDIR(USBD_EPxCFG[3] is low.) this register returns the number of received.."
group.long 0x22C++0x03
line.long 0x00 "USBD_EPLRSPCTL,Endpoint L Response Control Register"
bitfld.long 0x00 7. "DISBUF,Buffer Disable Bit\nThis bit is used to receive unknown size OUT short packet" "0: Buffer Not Disabled when Bulk-OUT short..,1: Buffer Disabled when Bulk-OUT short packet is.."
bitfld.long 0x00 6. "SHORTTXEN,Short Packet Transfer Enable Bit\nThis bit is applicable only in case of Auto-Validate Method" "0: Not validate any remaining data in the buffer..,1: Validate any remaining data in the buffer.."
newline
bitfld.long 0x00 5. "ZEROLEN,Zero Length\nThis bit is used to send a zero-length packet response to an IN-token" "0: A zero packet is not sent to the host on..,1: A zero packet is sent to the host on.."
bitfld.long 0x00 4. "HALT,Endpoint Halt \nThis bit is used to send a STALL handshake as response to the token from the host" "0: Do not send a STALL handshake as response to..,1: Send a STALL handshake as response to the.."
newline
bitfld.long 0x00 3. "TOGGLE,Endpoint Toggle \nThis bit is used to clear the endpoint data toggle bit" "0: Do not clear the endpoint data toggle bit,1: Clear the endpoint data toggle bit"
bitfld.long 0x00 1.--2. "MODE,Mode Control\nThe two bits determine the operation mode of the in-endpoint" "0: Auto-Validate Mode,1: Manual-Validate Mode,2: Fly Mode,3: Reserved"
newline
bitfld.long 0x00 0. "FLUSH,Buffer Flush \nWriting 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared" "0: The packet buffer is not flushed,1: The packet buffer is flushed by user"
group.long 0x230++0x03
line.long 0x00 "USBD_EPLMPS,Endpoint L Maximum Packet Size Register"
hexmask.long.word 0x00 0.--10. 1. "EPMPS,Endpoint Maximum Packet Size \nThis field determines the Maximum Packet Size of the Endpoint"
group.long 0x234++0x03
line.long 0x00 "USBD_EPLTXCNT,Endpoint L Transfer Count Register"
hexmask.long.word 0x00 0.--10. 1. "TXCNT,Endpoint Transfer Count\nFor IN endpoints this field determines the total number of bytes to be sent to the host in case of manual validation method.\nFor OUT endpoints this field has no effect"
group.long 0x238++0x03
line.long 0x00 "USBD_EPLCFG,Endpoint L Configuration Register"
bitfld.long 0x00 4.--7. "EPNUM,Endpoint Number\nThis field selects the number of the endpoint" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 3. "EPDIR,Endpoint Direction\n A maximum of one OUT and IN endpoint is allowed for each endpoint number" "0: out-endpoint (Host OUT to Device),1: in-endpoint (Host IN to Device)"
newline
bitfld.long 0x00 1.--2. "EPTYPE,Endpoint Type\nThis field selects the type of this endpoint" "0: Reserved,1: Bulk,2: Interrupt,3: Isochronous"
bitfld.long 0x00 0. "EPEN,Endpoint Valid\nWhen set this bit enables this endpoint" "0: The endpoint Disabled,1: The endpoint Enabled"
group.long 0x23C++0x03
line.long 0x00 "USBD_EPLBUFSTART,Endpoint L RAM Start Address Register"
hexmask.long.word 0x00 0.--11. 1. "SADDR,Endpoint Start Address\nThis is the start-address of the RAM space allocated for the endpoint A~L"
group.long 0x240++0x03
line.long 0x00 "USBD_EPLBUFEND,Endpoint L RAM End Address Register"
hexmask.long.word 0x00 0.--11. 1. "EADDR,Endpoint End Address\nThis is the end-address of the RAM space allocated for the endpoint A~L"
group.long 0x248++0x03
line.long 0x00 "USBD_UVCHDAT0,USB Header Word0"
hexmask.long 0x00 0.--31. 1. "DAT,The first head data(byte 0 was sent first)"
group.long 0x24C++0x03
line.long 0x00 "USBD_UVCHDAT1,USB Header Word1"
hexmask.long 0x00 0.--31. 1. "DAT,The second head data(byte 0 was sent first)"
group.long 0x250++0x03
line.long 0x00 "USBD_UVCHDAT2,USB Header Word2"
hexmask.long 0x00 0.--31. 1. "DAT,The third head data(byte 0 was sent first)"
group.long 0x254++0x03
line.long 0x00 "USBD_UVCEPAHCNT,Endpoint A Header Count"
bitfld.long 0x00 0.--3. "CNT,This is the header count for the endpoint A~L The header count must be EVEN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x258++0x03
line.long 0x00 "USBD_UVCEPBHCNT,Endpoint B Header Count"
bitfld.long 0x00 0.--3. "CNT,This is the header count for the endpoint A~L The header count must be EVEN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x25C++0x03
line.long 0x00 "USBD_UVCEPCHCNT,Endpoint C Header Count"
bitfld.long 0x00 0.--3. "CNT,This is the header count for the endpoint A~L The header count must be EVEN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x260++0x03
line.long 0x00 "USBD_UVCEPDHCNT,Endpoint D Header Count"
bitfld.long 0x00 0.--3. "CNT,This is the header count for the endpoint A~L The header count must be EVEN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x264++0x03
line.long 0x00 "USBD_UVCEPEHCNT,Endpoint E Header Count"
bitfld.long 0x00 0.--3. "CNT,This is the header count for the endpoint A~L The header count must be EVEN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x268++0x03
line.long 0x00 "USBD_UVCEPFHCNT,Endpoint F Header Count"
bitfld.long 0x00 0.--3. "CNT,This is the header count for the endpoint A~L The header count must be EVEN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x26C++0x03
line.long 0x00 "USBD_UVCEPGHCNT,Endpoint G Header Count"
bitfld.long 0x00 0.--3. "CNT,This is the header count for the endpoint A~L The header count must be EVEN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x270++0x03
line.long 0x00 "USBD_UVCEPHHCNT,Endpoint H Header Count"
bitfld.long 0x00 0.--3. "CNT,This is the header count for the endpoint A~L The header count must be EVEN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x274++0x03
line.long 0x00 "USBD_UVCEPIHCNT,Endpoint I Header Count"
bitfld.long 0x00 0.--3. "CNT,This is the header count for the endpoint A~L The header count must be EVEN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x278++0x03
line.long 0x00 "USBD_UVCEPJHCNT,Endpoint J Header Count"
bitfld.long 0x00 0.--3. "CNT,This is the header count for the endpoint A~L The header count must be EVEN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x27C++0x03
line.long 0x00 "USBD_UVCEPKHCNT,Endpoint K Header Count"
bitfld.long 0x00 0.--3. "CNT,This is the header count for the endpoint A~L The header count must be EVEN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x280++0x03
line.long 0x00 "USBD_UVCEPLHCNT,Endpoint L Header Count"
bitfld.long 0x00 0.--3. "CNT,This is the header count for the endpoint A~L The header count must be EVEN" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x700++0x03
line.long 0x00 "USBD_DMAADDR,AHB DMA Address Register"
hexmask.long 0x00 0.--31. 1. "DMAADDR,DMAADDR\nThe register specifies the address from which the DMA has to read /"
group.long 0x704++0x03
line.long 0x00 "USBD_PHYCTL,USB PHY Control Register"
bitfld.long 0x00 31. "VBUSDET,VBUS Status\n" "0: The VBUS is not detected yet,1: The VBUS is detected"
bitfld.long 0x00 24. "WKEN,Wake-up Enable Bit\n" "0: The wake-up function Disabled,1: The wake-up function Enabled"
newline
bitfld.long 0x00 9. "PHYEN,PHY Suspend Enable Bit\n" "0: The USB PHY is suspend,1: The USB PHY is not suspend"
bitfld.long 0x00 8. "DPPUEN,DP Pull-up\n" "0: Pull-up resistor on D+ Disabled,1: Pull-up resistor on D+ Enabled"
newline
bitfld.long 0x00 3. "LOWPWREN,PHY Low Power Mode Enable Bit (Low Active)\nUSB PHY HS low power mode configuration control bit.\nWhen this bit is 0 USB PHY is in Low Power Mode and USB PHY TX driver is enable only when USB Device Controller (USBD) transmit the data out to.." "0: USB PHY Low Power Mode Enabled,1: USB PHY Low Power Mode Disabled"
tree.end
tree "USBH"
base ad:0x4000B000
rgroup.long 0x00++0x03
line.long 0x00 "HCREVISION,Host Controller Revision Register"
hexmask.long.byte 0x00 0.--7. 1. "REV,Revision\nIndicates the Open HCI Specification revision number implemented by the Hardware"
group.long 0x04++0x03
line.long 0x00 "HCCONTROL,Host Controller Control Register"
bitfld.long 0x00 6.--7. "HCFS,Host Controller Functional State\nThis field sets the Host Controller state" "0: USBRESET,1: USBRESUME,2: USBOPERATIONAL,3: USBSUSPEND"
bitfld.long 0x00 5. "BLE,Bulk List Enable Bit\n" "0: Processing of the Bulk list after next SOF..,1: Processing of the Bulk list in the next frame.."
newline
bitfld.long 0x00 4. "CLE,Control List Enable Bit\n" "0: Processing of the Control list after next SOF..,1: Processing of the Control list in the next.."
bitfld.long 0x00 3. "IE,Isochronous Enable Bit\nBoth ISOEn and PLE (HcControl[2]) high enables Host Controller to process the Isochronous list" "0: Processing of the Isochronous list after next..,1: Processing of the Isochronous list in the.."
newline
bitfld.long 0x00 2. "PLE,Periodic List Enable Bit\nWhen set this bit enables processing of the Periodic (interrupt and isochronous) list" "0: Processing of the Periodic (Interrupt and..,1: Processing of the Periodic (Interrupt and.."
bitfld.long 0x00 0.--1. "CBSR,Control Bulk Service Ratio\nThis specifies the service ratio between Control and Bulk EDs" "0: Number of Control EDs over Bulk EDs served is..,1: Number of Control EDs over Bulk EDs served is..,2: Number of Control EDs over Bulk EDs served is..,3: Number of Control EDs over Bulk EDs served is.."
group.long 0x08++0x03
line.long 0x00 "HCCOMMANDSTATUS,Host Controller Command Status Register"
bitfld.long 0x00 16.--17. "SOC,Scheduling Overrun Count\nThese bits are incremented on each scheduling overrun error" "0,1,2,3"
bitfld.long 0x00 2. "BLF,Bulk List Filled\nSet high to indicate there is an active TD on the Bulk list" "0: No active TD found or Host Controller begins..,1: An active TD added or found on the Bulk list"
newline
bitfld.long 0x00 1. "CLF,Control List Filled\nSet high to indicate there is an active TD on the Control List" "0: No active TD found or Host Controller begins..,1: An active TD added or found on the Control list"
bitfld.long 0x00 0. "HCR,Host Controller Reset\nThis bit is set to initiate the software reset of Host Controller" "0: Host Controller is not in software reset state,1: Host Controller is in software reset state"
group.long 0x0C++0x03
line.long 0x00 "HCINTERRUPTSTATUS,Host Controller Interrupt Status Register"
bitfld.long 0x00 6. "RHSC,Root Hub Status Change\nThis bit is set when the content of HcRhStatus or the content of HcRhPortStatus1 register has changed.\n" "0: The content of HcRhStatus and the content of..,1: The content of HcRhStatus or the content of.."
bitfld.long 0x00 5. "FNO,Frame Number Overflow\nThis bit is set when bit 15 of Frame Number changes from 1 to 0 or from 0 to 1.\n" "0: The bit 15 of Frame Number didn't change,1: The bit 15 of Frame Number changes from 1 to.."
newline
bitfld.long 0x00 3. "RD,Resume Detected\nSet when Host Controller detects resume signaling on a downstream port.\n" "0: No resume signaling detected on a downstream..,1: Resume signaling detected on a downstream port"
bitfld.long 0x00 2. "SF,Start of Frame\nSet when the Frame Management functional block signals a 'Start of Frame' event" "0: .Not the start of a frame,1: .Indicate the start of a frame and Host.."
newline
bitfld.long 0x00 1. "WDH,Write Back Done Head\nSet after the Host Controller has written HcDoneHead to HccaDoneHead" "0: .Host Controller didn't update HccaDoneHead,1: .Host Controller has written HcDoneHead to.."
bitfld.long 0x00 0. "SO,Scheduling Overrun\nSet when the List Processor determines a Schedule Overrun has occurred.\n" "0: Schedule Overrun didn't occur,1: Schedule Overrun has occurred"
group.long 0x10++0x03
line.long 0x00 "HCINTERRUPTENABLE,Host Controller Interrupt Enable Control Register"
bitfld.long 0x00 31. "MIE,Master Interrupt Enable Bit\nThis bit is a global interrupt enable" "0: No effect.\nInterrupt generation due to RHSC..,1: Interrupt generation due to RHSC.."
bitfld.long 0x00 6. "RHSC,Root Hub Status Change Interrupt Enable Bit\nWrite Operation:\n" "0: No effect.\nInterrupt generation due to RHSC..,1: Interrupt generation due to RHSC.."
newline
bitfld.long 0x00 5. "FNO,Frame Number Overflow Interrupt Enable Bit\nWrite Operation:\n" "0: No effect.\nInterrupt generation due to FNO..,1: Interrupt generation due to FNO.."
bitfld.long 0x00 3. "RD,Resume Detected Interrupt Enable Bit\nWrite Operation:\n" "0: No effect.\nInterrupt generation due to RD..,1: Interrupt generation due to RD.."
newline
bitfld.long 0x00 2. "SF,Start of Frame Interrupt Enable Bit\nWrite Operation:\n" "0: No effect.\nInterrupt generation due to SF..,1: Interrupt generation due to SF.."
bitfld.long 0x00 1. "WDH,Write Back Done Head Interrupt Enable Bit\nWrite Operation:\n" "0: No effect.\nInterrupt generation due to WDH..,1: Interrupt generation due to WDH.."
newline
bitfld.long 0x00 0. "SO,Scheduling Overrun Interrupt Enable Bit\nWrite Operation:\n" "0: No effect.\nInterrupt generation due to SO..,1: Interrupt generation due to SO.."
group.long 0x14++0x03
line.long 0x00 "HCINTERRUPTDISABLE,Host Controller Interrupt Disable Control Register"
bitfld.long 0x00 31. "MIE,Master Interrupt Disable Bit\nGlobal interrupt disable" "0: No effect.\nInterrupt generation due to RHSC..,1: Interrupt generation due to RHSC.."
bitfld.long 0x00 6. "RHSC,Root Hub Status Change Disable Bit\nWrite Operation:\n" "0: No effect.\nInterrupt generation due to RHSC..,1: Interrupt generation due to RHSC.."
newline
bitfld.long 0x00 5. "FNO,Frame Number Overflow Disable Bit\nWrite Operation:\n" "0: No effect.\nInterrupt generation due to FNO..,1: Interrupt generation due to FNO.."
bitfld.long 0x00 3. "RD,Resume Detected Disable Bit\nWrite Operation:\n" "0: No effect.\nInterrupt generation due to RD..,1: Interrupt generation due to RD.."
newline
bitfld.long 0x00 2. "SF,Start of Frame Disable Bit\nWrite Operation:\n" "0: No effect.\nInterrupt generation due to SF..,1: Interrupt generation due to SF.."
bitfld.long 0x00 1. "WDH,Write Back Done Head Disable Bit\nWrite Operation:\n" "0: No effect.\nInterrupt generation due to WDH..,1: Interrupt generation due to WDH.."
newline
bitfld.long 0x00 0. "SO,Scheduling Overrun Disable Bit\nWrite Operation:\n" "0: No effect.\nInterrupt generation due to SO..,1: Interrupt generation due to SO.."
group.long 0x18++0x03
line.long 0x00 "HCHCCA,Host Controller Communication Area Register"
hexmask.long.tbyte 0x00 8.--31. 1. "HCCA,Host Controller Communication Area\nPointer to indicate base address of the Host Controller Communication Area (HCCA)"
group.long 0x1C++0x03
line.long 0x00 "HCPERIODCURRENTED,Host Controller Period Current ED Register"
hexmask.long 0x00 4.--31. 1. "PCED,Periodic Current ED\nPointer to indicate physical address of the current Isochronous or Interrupt Endpoint Descriptor"
group.long 0x20++0x03
line.long 0x00 "HCCONTROLHEADED,Host Controller Control Head ED Register"
hexmask.long 0x00 4.--31. 1. "CHED,Control Head ED\nPointer to indicate physical address of the first Endpoint Descriptor of the Control list"
group.long 0x24++0x03
line.long 0x00 "HCCONTROLCURRENTED,Host Controller Control Current ED Register"
hexmask.long 0x00 4.--31. 1. "CCED,Control Current Head ED\nPointer to indicate the physical address of the current Endpoint Descriptor of the Control list"
group.long 0x28++0x03
line.long 0x00 "HCBULKHEADED,Host Controller Bulk Head ED Register"
hexmask.long 0x00 4.--31. 1. "BHED,Bulk Head ED\nPointer to indicate the physical address of the first Endpoint Descriptor of the Bulk list"
group.long 0x2C++0x03
line.long 0x00 "HCBULKCURRENTED,Host Controller Bulk Current ED Register"
hexmask.long 0x00 4.--31. 1. "BCED,Bulk Current Head ED\nPointer to indicate the physical address of the current endpoint of the Bulk list"
group.long 0x30++0x03
line.long 0x00 "HCDONEHEAD,Host Controller Done Head Register"
hexmask.long 0x00 4.--31. 1. "DH,Done Head\nPointer to indicate the physical address of the last completed Transfer Descriptor that was added to the Done queue"
group.long 0x34++0x03
line.long 0x00 "HCFMINTERVAL,Host Controller Frame Interval Register"
bitfld.long 0x00 31. "FIT,Frame Interval Toggle\nThis bit is toggled by Host Controller Driver when it loads a new value into FI (HcFmInterval[13:0]).\n" "0: Host Controller Driver didn't load new value..,1: Host Controller Driver loads a new value into.."
hexmask.long.word 0x00 16.--30. 1. "FSMPS,FS Largest Data Packet\nThis field specifies a value that is loaded into the Largest Data Packet Counter at the beginning of each frame"
newline
hexmask.long.word 0x00 0.--13. 1. "FI,Frame Interval\nThis field specifies the length of a frame as (bit times - 1)"
rgroup.long 0x38++0x03
line.long 0x00 "HCFMREMAINING,Host Controller Frame Remaining Register"
bitfld.long 0x00 31. "FRT,Frame Remaining Toggle\nThis bit is loaded from the FIT (HcFmInterval[31]) whenever FR (HcFmRemaining[13:0]) reaches 0" "0,1"
hexmask.long.word 0x00 0.--13. 1. "FR,Frame Remaining\nWhen the Host Controller is in the USBOPERATIONAL state this 14-bit field decrements each 12 MHz clock period"
rgroup.long 0x3C++0x03
line.long 0x00 "HCFMNUMBER,Host Controller Frame Number Register"
hexmask.long.word 0x00 0.--15. 1. "FN,Frame Number\nThis 16-bit incrementing counter field is incremented coincident with the loading of FR (HcFmRemaining[13:0])"
group.long 0x40++0x03
line.long 0x00 "HCPERIODICSTART,Host Controller Periodic Start Register"
hexmask.long.word 0x00 0.--13. 1. "PS,Periodic Start\nThis field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin"
group.long 0x44++0x03
line.long 0x00 "HCLSTHRESHOLD,Host Controller Low-speed Threshold Register"
hexmask.long.word 0x00 0.--11. 1. "LST,Low-speed Threshold\n"
group.long 0x48++0x03
line.long 0x00 "HCRHDESCRIPTORA,Host Controller Root Hub Descriptor A Register"
bitfld.long 0x00 12. "NOCP,No Overcurrent Protection\nThis bit describes how the overcurrent status for the Root Hub ports reported.\n" "0: Overcurrent status is reported,1: Overcurrent status is not reported"
bitfld.long 0x00 11. "OCPM,Overcurrent Protection Mode\nThis bit describes how the overcurrent status for the Root Hub ports reported" "0: Global Overcurrent,1: Individual Overcurrent"
newline
bitfld.long 0x00 8. "PSM,Power Switching Mode\nThis bit is used to specify how the power switching of the Root Hub ports is controlled.\n" "0: Global Switching,1: Individual Switching"
hexmask.long.byte 0x00 0.--7. 1. "NDP,Number Downstream Ports\nRoot Hub supports two downstream ports"
group.long 0x4C++0x03
line.long 0x00 "HCRHDESCRIPTORB,Host Controller Root Hub Descriptor B Register"
hexmask.long.word 0x00 16.--31. 1. "PPCM,Port Power Control Mask\nGlobal power switching"
group.long 0x50++0x03
line.long 0x00 "HCRHSTATUS,Host Controller Root Hub Status Register"
bitfld.long 0x00 31. "CRWE,Clear Remote Wake-up Enable Bit\nThis bit is used to clear DRWE (HcRhStatus[15]).\nThis bit is always read as zero.\nWrite Operation:\n" "0: No effect,1: Clear DRWE (HcRhStatus[15])"
bitfld.long 0x00 17. "OCIC,Overcurrent Indicator Change\nThis bit is set by hardware when a change has occurred in OCI (HcRhStatus[1]).\nWrite 1 to clear this bit to zero.\n" "0: OCI (HcRhStatus[1]) is not changed,1: OCI (HcRhStatus[1]) is changed"
newline
bitfld.long 0x00 16. "LPSC,Set Global Power\n" "0: No effect,1: Set global power"
bitfld.long 0x00 15. "DRWE,Device Remote Wake-up Enable Bit\nThis bit controls if port's Connect Status Change as a remote wake-up event.\nWrite Operation:\n" "0: No effect.\nConnect status changed as a..,1: Connect status changed as a remote wake-up.."
newline
bitfld.long 0x00 1. "OCI,Overcurrent Indicator\nThis bit reflects the state of the overcurrent status pin" "0: No overcurrent condition,1: Overcurrent condition"
bitfld.long 0x00 0. "LPS,Clear Global Power\n" "0: No effect,1: Clear global power"
repeat 2. (strings "1" "2" )(list 0x0 0x4 )
group.long ($2+0x54)++0x03
line.long 0x00 "HCRHPORTSTATUS$1,Host Controller Root Hub Port Status [1]"
bitfld.long 0x00 20. "PRSC,Port Reset Status Change\nThis bit indicates that the port reset signal has completed.\nWrite 1 to clear this bit to zero.\n" "0: Port reset is not completed,1: Port reset is completed"
bitfld.long 0x00 19. "OCIC,Port Overcurrent Indicator Change\nThis bit is set when POCI (HcRhPortStatus1[3]) changes.\nWrite 1 to clear this bit to zero.\n" "0: POCI (HcRhPortStatus1[3]) is not changed,1: POCI (HcRhPortStatus1[3]) is changed"
newline
bitfld.long 0x00 18. "PSSC,Port Suspend Status Change\nThis bit indicates the completion of the selective resume sequence for the port.\nWrite 1 to clear this bit to zero.\n" "0: Port resume is not completed,1: Port resume is completed"
bitfld.long 0x00 17. "PESC,Port Enable Status Change\nThis bit indicates that the port has been disabled (PES (HcRhPortStatus1[1]) cleared) due to a hardware event.\nWrite 1 to clear this bit to zero.\n" "0: PES (HcRhPortStatus1[1]) is not changed,1: PES (HcRhPortStatus1[1]) is changed"
newline
bitfld.long 0x00 16. "CSC,Connect Status Change\nThis bit indicates connect or disconnect event has been detected (CCS (HcRhPortStatus1[0]) changed).\nWrite 1 to clear this bit to zero.\n" "0: No connect/disconnect event (CCS..,1: Hardware detection of connect/disconnect.."
bitfld.long 0x00 9. "LSDA,Low Speed Device Attached (Read) or Clear Port Power (Write)\nThis bit defines the speed (and bud idle) of the attached device" "0: No effect.\nFull Speed device,1: Clear PPS (HcRhPortStatus1[8]).\nLow-speed.."
newline
bitfld.long 0x00 8. "PPS,Port Power Status\nThis bit reflects the power state of the port regardless of the power switching mode.\nWrite Operation:\n" "0: No effect.\nPort power Diabled,1: Port Power Enabled.\nPort power Enabled"
bitfld.long 0x00 4. "PRS,Port Reset Status\nThis bit reflects the reset state of the port.\nWrite Operation:\n" "0: No effect.\nPort reset signal is not active,1: Set port reset.\nPort reset signal is active"
newline
bitfld.long 0x00 3. "POCI,Port Overcurrent Indicator (Read) or Clear Port Suspend (Write)\nThis bit reflects the state of the overcurrent status pin dedicated to this port" "0: No effect.\nNo overcurrent condition,1: Clear port suspend.\nOvercurrent condition"
bitfld.long 0x00 2. "PSS,Port Suspend Status\nThis bit indicates the port is suspended\nWrite Operation:\n" "0: No effect.\nPort is not suspended,1: Set port suspend.\nPort is selectively.."
newline
bitfld.long 0x00 1. "PES,Port Enable Status\nWrite Operation:\n" "0: No effect.\nPort Disabled,1: Set port Enabled.\nPort Enabled"
bitfld.long 0x00 0. "CCS,Current Connect Status (Read) or Clear Port Enable Bit (Write)\nWrite Operation:\n" "0: No effect.\nNo device connected,1: Clear port Enabled.\nDevice connected"
repeat.end
group.long 0x200++0x03
line.long 0x00 "HCPHYCONTROL,Host Controller PHY Control Register"
bitfld.long 0x00 27. "STBYEN,USB Transceiver Standby Enable Bit\nThis bit controls if USB transceiver could enter the standby mode to reduce power consumption.\n" "0: The USB transceiver would never enter the..,1: The USB transceiver will enter Standby mode.."
group.long 0x204++0x03
line.long 0x00 "HCMISCCONTROL,Host Controller Miscellaneous Control Register"
bitfld.long 0x00 17. "DPRT2,Port 2 Disable Bit\nThis bit controls if the connection between USB host controller and transceiver of port 2 is disabled" "0: The connection between USB host controller..,1: The connection between USB host controller.."
bitfld.long 0x00 16. "DPRT1,Port 1 Disable Bit\nThis bit controls if the connection between USB host controller and transceiver of port 1 is disabled" "0: The connection between USB host controller..,1: The connection between USB host controller.."
newline
bitfld.long 0x00 8. "SIEPD,SIE Pipeline Disable Bit\nWhen set waits for all USB bus activity to complete prior to returning completion status to the List Processor" "0,1"
bitfld.long 0x00 4. "PCAL,Port Power Control Active Low\nThis bit controls the polarity of port power control to external power IC.\n" "0: Port power control is high active,1: Port power control is low active"
newline
bitfld.long 0x00 3. "OCAL,Overcurrent Active Low\nThis bit controls the polarity of overcurrent flag from external power IC.\n" "0: Overcurrent flag is high active,1: Overcurrent flag is low active"
bitfld.long 0x00 1. "ABORT,AHB Bus ERROR Response\nThis bit indicates there is an ERROR response received in AHB bus.\n" "0: No ERROR response received,1: ERROR response received"
newline
bitfld.long 0x00 0. "DBR16,Data Buffer Region 16\nWhen set the size of the data buffer region is 16 bytes" "0,1"
tree.end
tree "WDT"
base ad:0x400EF000
group.long 0x00++0x03
line.long 0x00 "WDT_CTL,Watchdog Timer Control Register"
bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Control \nWatchdog Timer counter will keep going no matter CPU is held by ICE or not" "0: ICE debug mode acknowledgement affects..,1: ICE debug mode acknowledgement Disabled"
bitfld.long 0x00 8.--10. "TOUTSEL,Watchdog Timer Time-out Interval Selection \nThese three bits select the time-out interval period for the Watchdog Timer.\n" "0: 24 *TWDT,1: 26 *TWDT,2: 28 *TWDT,3: 210 *TWDT,4: 212 *TWDT,5: 214 *TWDT,6: 216 *TWDT,7: 218 *TWDT"
newline
bitfld.long 0x00 7. "WDTEN,Watchdog Timer Enable Control \n" "0: Watchdog Timer Disabled (This action will..,1: Watchdog Timer Enabled"
bitfld.long 0x00 6. "INTEN,Watchdog Timer Interrupt Enable Control \nIf this bit is enabled the Watchdog Timer time-out interrupt signal is generated and inform to CPU" "0: Watchdog Timer interrupt Disabled,1: Watchdog Timer interrupt Enabled"
newline
bitfld.long 0x00 5. "WKF,Watchdog Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of Watchdog Timer \nNote: This bit is cleared by writing 1 to it" "0: Watchdog Timer does not cause chip wake-up,1: Chip wake-up from Power-down if Watchdog.."
bitfld.long 0x00 4. "WKEN,Watchdog Timer Wake-up Function Enable Control \nIf this bit is set to 1 while Watchdog Timer interrupt flag IF (WDT_CTL[3]) is generated to 1 and INTEN (WDT_CTL[6] Watchdog Timer interrupt enable) is enabled the Watchdog Timer time-out interrupt.." "0: Wake-up trigger event Disabled if Watchdog..,1: Wake-up trigger event Enabled if Watchdog.."
newline
bitfld.long 0x00 3. "IF,Watchdog Timer Interrupt Flag\nThis bit will set to 1 while Watchdog Timer counter value reaches the selected Watchdog Timer time-out interval\nNote: This bit is cleared by writing 1 to it" "0: Watchdog Timer time-out interrupt did not occur,1: Watchdog Timer time-out interrupt occurred"
bitfld.long 0x00 2. "RSTFC,Watchdog Timer Reset Flag Cleared\nWrite 1 to clear the RSTF (WDT_RSTSTS [2])" "0,1"
newline
bitfld.long 0x00 1. "RSTEN,Watchdog Timer Reset Enable Control \nSetting this bit will enable the Watchdog Timer time-out reset function If the Watchdog Timer counter value has not been cleared after the specific Watchdog Timer reset delay period expires.\n" "0: Watchdog Timer time-out reset function Disabled,1: Watchdog Timer time-out reset function Enabled"
bitfld.long 0x00 0. "RSTCNT,Clear Watchdog Timer\nNote: This bit will be automatically cleared by hardware" "0: No effect,1: Reset the internal 18-bit Watchdog Timer.."
group.long 0x04++0x03
line.long 0x00 "WDT_ALTCTL,Watchdog Timer Alternative Control Register"
bitfld.long 0x00 0.--1. "RSTDSEL,Watchdog Timer Reset Delay Selection\nWhen Watchdog Timer time-out happened software has a time named Watchdog Timer reset delay period to clear Watchdog Timer counter to prevent Watchdog Timer time-out reset happened" "0: Watchdog Timer reset delay period is (1024+2)..,1: Watchdog Timer reset delay period is (128+2)..,2: Watchdog Timer reset delay period is (16+2) *..,3: Watchdog Timer reset delay period is (1+2) *.."
rgroup.long 0x10++0x03
line.long 0x00 "WDT_RSTSTS,Watchdog Timer Reset Status Register"
bitfld.long 0x00 2. "RSTF,Watchdog Timer Reset Flag \nThis bit indicates the system has been reset by Watchdog Timer time-out reset or not.\nNote: This bit is cleared by writing 1 to RSTFC (WDT_CTL [2])" "0: Watchdog Timer time-out reset did not occur,1: Watchdog Timer time-out reset occurred"
tree.end
tree "WWDT"
base ad:0x400EF100
wgroup.long 0x00++0x03
line.long 0x00 "WWDT_RLDCNT,Window Watchdog Timer Reload Counter Register"
hexmask.long 0x00 0.--31. 1. "RLDCNT,WWDT Reload Counter Bits\nWriting 0x00005AA5 to this register will reload the Window Watchdog Timer counter value to 0x3F"
group.long 0x04++0x03
line.long 0x00 "WWDT_CTL,Window Watchdog Timer Control Register"
bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Control\nWWDT down counter will keep going no matter CPU is held by ICE or not" "0: ICE debug mode acknowledgement effects WWDT..,1: ICE debug mode acknowledgement Disabled"
bitfld.long 0x00 16.--21. "CMPDAT,WWDT Window Compare Bits\nSet this register to adjust the valid reload window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--11. "PSCSEL,WWDT Counter Prescale Period Selection\n" "0: Pre-scale is 1 Max time-out period is 1 * 64..,1: Pre-scale is 2 Max time-out period is 2 * 64..,2: Pre-scale is 4 Max time-out period is 4 * 64..,3: Pre-scale is 8 Max time-out period is 8 * 64..,4: Pre-scale is 16 Max time-out period is 16 *..,5: Pre-scale is 32 Max time-out period is 32 *..,6: Pre-scale is 64 Max time-out period is 64 *..,7: Pre-scale is 128 Max time-out period is 128 *..,8: Pre-scale is 192 Max time-out period is 192 *..,9: Pre-scale is 256 Max time-out period is 256 *..,10: Pre-scale is 384 Max time-out period is 384..,11: Pre-scale is 512 Max time-out period is 512..,12: Pre-scale is 768 Max time-out period is 768..,13: Pre-scale is 1024 Max time-out period is..,14: Pre-scale is 1536 Max time-out period is..,15: Pre-scale is 2048 Max time-out period is.."
bitfld.long 0x00 1. "INTEN,WWDT Interrupt Enable Control\nIf this bit is enabled the WWDT counter compare match interrupt signal is generated and inform to CPU.\n" "0: WWDT counter compare match interrupt Disabled,1: WWDT counter compare match interrupt Enabled"
newline
bitfld.long 0x00 0. "WWDTEN,WWDT Enable Control\nSet this bit to enable Window Watchdog Timer counter counting.\n" "0: Window Watchdog Timer counter is stopped,1: Window Watchdog Timer counter is starting.."
group.long 0x08++0x03
line.long 0x00 "WWDT_STATUS,Window Watchdog Timer Status Register"
bitfld.long 0x00 1. "WWDTRFC,WWDT Timer-out Reset Flag Cleared\nWhen the window watch dog reset happened the register WWDTRF (WWDT_RSTSTS [1]) will be set to 1" "0,1"
bitfld.long 0x00 0. "WWDTIF,WWDT Compare Match Interrupt Flag \nThis bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT value.\n This bit is cleared by writing 1 to WWDT_STATUS[0]" "0: No effect,1: WWDT counter value matches CMPDAT value"
rgroup.long 0x0C++0x03
line.long 0x00 "WWDT_CNT,Window Watchdog Timer Counter Value Register"
bitfld.long 0x00 0.--5. "CNTDAT,WWDT Counter Value\nThis register reflects the current WWDT counter value and is read only" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x18++0x03
line.long 0x00 "WWDT_RSTSTS,Window Watchdog Timer Reset Status Register"
bitfld.long 0x00 1. "WWDTRF,WWDT Timer-out Reset Flag \nThis bit indicates the system has been reset by WWDT time-out reset or not.\n This bit is cleared by writing 1 to WWDTRFC (WWDT_STATUS [1])" "0: WWDT time-out reset did not occur,1: WWDT time-out reset occurred"
tree.end
autoindent.off
newline